TLV4968-1TB [INFINEON]
The Infineon TLV496x-xTA/B Hall sensor family comprises a line of Hall switches for contactless position sensing. The sensors are specially designed to provide an easy-to-use and cost effective solution for position sensing applications.;
| 型号： | TLV4968-1TB |
| 厂家： | 
Infineon |
| 描述： | The Infineon TLV496x-xTA/B Hall sensor family comprises a line of Hall switches for contactless position sensing. The sensors are specially designed to provide an easy-to-use and cost effective solution for position sensing applications. |
| 文件： | 总21页 (文件大小：665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Bipolar Hall Latch
High Precision Hall Effect Latch for Consumer Applications
TLV4968-1TA
TLV4968-1TB
SP001274788
SP001283508
TLV4968-1T
Data Sheet
Revision 1.2, 2019-12-20
Sense & Control
TLV4968-1T
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
List of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Default start-up behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
3
Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical and magnetic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
3.4
4
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distance between chip and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
4.2
4.3
4.4
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Sheet
2
Revision 1.2, 2019-12-20
TLV4968-1T
List of tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum rating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ESD protection (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating conditions parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Magnetic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Sheet
3
Revision 1.2, 2019-12-20
TLV4968-1T
List of figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
TLV4968-1T in the TO92S-3-1 and TO92S-3-2 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration and center of sensitive area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional block diagram TLV4968-1T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timing diagram TLV4968-1T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output signal TLV4968-1T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Start-up behavior of the TLV4968-1T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Basic application circuit #1: only pull-up resistor is necessary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Enhanced application circuit #2: for extended ESD robustness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Definition of magnetic field direction TO92S-3-1, TO92S-3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10 Package outline TLV4968-1TA: TO92S-3-1 (all dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11 Package outline TLV4968-1TB: TO92S-3-2 (all dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12 Packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13 Distance between chip and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14 Marking of TLV4968-1T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Sheet
4
Revision 1.2, 2019-12-20
TLV4968-1T
Product description
1
Product description
1)
1.1
Overview
Characteristic
Supply Voltage Supply Current Sensitivity
Interface
Temperature
-40°C to 125°C
Bipolar Hall
Effect Latch
3.0 V ~ 26 V
1.6 mA
B
B
OP: 1 mT
RP: -1 mT
Open Drain
Output
Figure 1
TLV4968-1T in the TO92S-3-1 and TO92S-3-2 package
1.2
Features
•
•
•
•
•
•
•
3.0 V to 26 V operating supply voltage
Operation from unregulated power supply
Output overcurrent and overtemperature protection
Active error compensation
High stability of magnetic thresholds
High ESD performance
Leaded, halogen-free package TO92S-3-1 for TLV4968-1TA,
TO92S-3-2 for TLV4968-1TB
For automotive applications please refer to the Infineon TLE Hall Switches/Latches series.
Table 1 Ordering information
Product name
TLV4968-1TA
TLV4968-1TB
Product type
Ordering code
SP001274788
SP001283508
Package
TO92S-3-1 (Bulk)
TO92S-3-2 (Ammo pack)
Bipolar Hall Latch
Bipolar Hall Latch
1) Only the package is halogen-free.
Data Sheet
5
Revision 1.2, 2019-12-20
TLV4968-1T
Product description
1.3
Target applications
Target applications for the TLV496x Hall Latch family are all applications which require a high precision
Hall Switch with an operating temperature range from -40°C to 125°C.
The magnetic behavior as a latch and switching thresholds of typical ±1 mT make the device especially suited
for the use with a pole wheel for index counting applications, for rotor position detection as in brushless DC
motor commutation and for white goods or open/closing detection.
Data Sheet
6
Revision 1.2, 2019-12-20
TLV4968-1T
Functional description
2
Functional description
2.1
General
The TLV4968-1T is an integrated Hall effect switch designed specifically for highly accurate applications with
superior supply voltage capability and temperature stability of the magnetic thresholds.
2.2
Pin configuration (top view)
1
2
3
Q
VDD GND
Figure 2
Pin configuration and center of sensitive area
Pin description
2.3
Table 2
Pin description
Pin no.
Symbol
VDD
GND
Q
Function
Supply voltage
Ground
1
2
3
Output
Data Sheet
7
Revision 1.2, 2019-12-20
TLV4968-1T
Functional description
2.4
Block diagram
VDD
To All Subcircuits
Voltage
Regulator
Oscillator and
Sequencer
Bias and
Compensation
Circuits
Reference
Q
Amplifier
Control
Spinning Hall
Probe
Comparator
with
Hysteresis
Low Pass
Filter
Overtemperature
& overcurrent
protection
GND
Figure 3
Functional block diagram TLV4968-1T
Data Sheet
8
Revision 1.2, 2019-12-20
TLV4968-1T
Functional description
2.5
Functional block description
The chopped Hall IC switch comprises a Hall probe, bias generator, compensation circuits, oscillator and
output transistor.
The bias generator provides currents for the Hall probe and the active circuits. Compensation circuits stabilize
the temperature behavior and reduce influence of technology variations.
The active error compensation (chopping technique) rejects offsets in the signal path and the influence of
mechanical stress to the Hall probe caused by molding and soldering processes and other thermal stress in
the package. The chopped measurement principle together with the threshold generator and the comparator
ensures highly accurate and temperature stable magnetic thresholds.
The output transistor has an integrated overcurrent and overtemperature protection.
Applied
Magnetic
Field
BOP
BRP
td
tf
td
tr
VQ
90%
10%
Figure 4
Timing diagram TLV4968-1T
VQ
B
BRP
0
BOP
Figure 5
Output signal TLV4968-1T
Data Sheet
9
Revision 1.2, 2019-12-20
TLV4968-1T
Functional description
2.6
Default start-up behavior
The magnetic thresholds exhibit a hysteresis BHYS = BOP - BRP. In case of a power-on with a magnetic field B
within hysteresis (BOP > B > BRP) the output of the sensor is set to the pull up voltage level (VQ) per default. After
the first crossing of BOP or BRP of the magnetic field the internal decision logic is set to the corresponding
magnetic input value.
VDDA is the internal supply voltage which is following the external supply voltage VDD.
This means for B > BOP the output is switching, for B < BRP and BOP > B > BRP the output stays at VQ.
VDDA
tPon
3V
The device always applies
Power on ramp
VQ level at start-up
t
VQ
independent from the
applied magnetic field !
Magnetic field above threshold
B > BOP
t
VQ
Magnetic field below threshold
B < BRP
t
t
VQ
Magnetic field in hysteresis
BOP > B > BRP
Figure 6
Start-up behavior of the TLV4968-1T
Data Sheet
10
Revision 1.2, 2019-12-20
TLV4968-1T
Specification
3
Specification
3.1
Application circuit
The following Figure 7 shows the basic option of an application circuit. Only a pull-up resistor RQ is necessary.
The resistor RQ has to be in a dimension to match the applied VS to keep IQ limited to the operating range of
maximum 25 mA.
e.g.: VS = 12 V; IQ = 12 V/1200 Ω = 10 mA
Vs
VDD
RQ = 1.2kΩ
Q
GND
Figure 7
Basic application circuit #1: only pull-up resistor is necessary
Vs
VDD
RQ = 1.2kΩ
Q
CDD = 47nF
TVS diode
e.g. ESD24VS2U
GND
Figure 8
Enhanced application circuit #2: for extended ESD robustness
With an additional capacitor CDD and a transient voltage suppression (TVS) diode an extended ESD robustness
on system level is achieved (Figure 8).
Data Sheet
11
Revision 1.2, 2019-12-20
TLV4968-1T
Specification
3.2
Absolute maximum ratings
Table 3
Absolute maximum rating parameters
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
3
Typ.
Max.
26
Supply voltage1)
Output voltage
VDD
VQ
–
–
–
–
–
–
V
–
–
–
–
–
-0.5
-70
-40
-40
–
26
V
Reverse output current IQ
Junction temperature1) TJ
–
mA
°C
°C
150
150
250
Storage temperature
TS
Thermal resistance
Junction ambient
RthJA
K/W for TO92S-3-1, TO92S-3-2 (2s2p)
1) This lifetime statement is an anticipation based on an extrapolation of Infineon’s qualification test results. The actual
lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement.
The lifetime statement shall in no event extend the agreed warranty period.
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
Calculation of the dissipated power PDIS and junction temperature TJ of the chip (TO92S example):
e.g. for: VDD = 12 V, IS = 2.5 mA, VQSAT = 0.5 V, IQ = 20 mA
Power dissipation: PDIS = 12 V x 2.5 mA + 0.5 V x 20 mA = 30 mW + 10 mW = 40 mW
Temperature ∆T = RthJA x PDIS = 250 K/W x 40 mW = 10 K
For TA = 50°C: TJ = TA + ∆T = 50°C + 10 K = 60°C
Data Sheet
12
Revision 1.2, 2019-12-20
TLV4968-1T
Specification
Table 4
ESD protection1) (TA = 25°C)
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
-4
Typ.
Max.
ESD voltage (HBM)2)
ESD voltage (CDM)3)
VESD
VESD
–
–
4
1
kV
kV
R = 1.5 kΩ, C = 100 pF
-1
–
1) Characterization of ESD is carried out on a sample basis, not subject to production test.
2) Human Body Model (HBM) tests according to ANSI/ESDA/JEDEC JS-001.
3) Charge device model (CDM) tests according to JESD22-C101.
3.3
Operating range
The following operating conditions must not be exceeded in order to ensure correct operation of
the TLV4968-1T.
All parameters specified in the following sections refer to these operating conditions unless otherwise
mentioned.
The maximum tested magnetic field is 600 mT.
Table 5
Operating conditions parameters
Symbol
Parameter
Values
Typ.
Unit Note or
Test Condition
Min.
3.0
3.0
-40
0
Max.
261)
26
Supply voltage
VDD
VQ
TA
IQ
–
–
–
–
V
–
Output voltage
V
–
Operation temperature
125
25
°C
mA
RthJA ≤ 250 K/W
Output current
–
1) Latch-up test with factor 1.5 is not covered. Please see max ratings also.
Data Sheet
13
Revision 1.2, 2019-12-20
TLV4968-1T
Specification
3.4
Electrical and magnetic characteristics
Product characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production and correspond to VDD = 12 V and
TA = 25°C. The below listed specification is valid in combination with the application circuit shown in Figure 7
and Figure 8.
Table 6
General electrical characteristics
Parameter
Symbol
Min.
Values
Typ.
1.6
Unit Note or Test Condition
Max.
2.5
Supply current
IS
1.1
30
mA
mA
–
Output current limitation IQLIMIT
56
70
internally limited and thermal
shutdown
Output fall time1)
Output rise time1)
Delay time1)2)
tf
0.17
0.4
12
0.4
0.5
15
1
μs
μs
μs
μs
1.2 kΩ / 50 pF, see Figure 4
1.2 kΩ / 50 pF, see Figure 4
see Figure 4
tr
1
td
30
150
Power-on time1)3)
tPON
–
80
VDD = 3 V, B ≤ BRP - 0.5 mT or
B ≥ BOP + 0.5 mT
1) Not subject to production test, verified by design/characterization.
2) Systematic delay between magnetic threshold reached and output switching.
3) Time from applying VDD = 3.0 V to the sensor until the output is valid.
Data Sheet
14
Revision 1.2, 2019-12-20
TLV4968-1T
Specification
Table 7
Magnetic characteristics
Symbol T (°C)
Parameter
Values
Unit
Note / Test
Condition
Min.
-0.3
-0.4
-0.4
-2.3
-2.3
-2.1
1.2
Typ. Max.
Operating point
Release point
Hysteresis
BOP
-40
25
1.1
2.3
2.3
2.1
0.3
0.4
0.4
3.1
2.9
2.7
–
mT
–
–
–
–
1.0
125
-40
25
0.9
BRP
-1.1
-1.0
-0.9
2.1
mT
125
-40
25
BHYS
mT
1.1
2.0
125
–
1.0
1.8
Temperaturecompensationof TC
–
-1000
ppm/K
magnetic thresholds1)
1) Not subject to production test, verified by design/characterization.
Field direction definition
Positive magnetic fields are defined with the south pole of the magnet to the branded side of package.
N
S
Branded Side
Figure 9
Definition of magnetic field direction TO92S-3-1, TO92S-3-2
Data Sheet
15
Revision 1.2, 2019-12-20
TLV4968-1T
Package information
4
Package information
The TLV4968-1TA is available in Bulk packing with TO92S-3-1-package.
The TLV4968-1TB is available in AMMO packing with TO92S-3-2-package.
4.1
Package outline
Figure 10 Package outline TLV4968-1TA: TO92S-3-1 (all dimensions in mm)
Data Sheet
16
Revision 1.2, 2019-12-20
TLV4968-1T
Package information
Figure 11 Package outline TLV4968-1TB: TO92S-3-2 (all dimensions in mm)
Data Sheet
17
Revision 1.2, 2019-12-20
TLV4968-1T
Package information
4.2
Packing information
Figure 12 Packing information
4.3
Distance between chip and package
Figure 13 Distance between chip and package
Data Sheet
18
Revision 1.2, 2019-12-20
TLV4968-1T
Package information
4.4
Package marking
Halogen free (H)
Year (Y) = 0...9
HYWWLL
Calendar Week (WW) = 01...52
Lot Code (LL)
V681T
Figure 14 Marking of TLV4968-1T
Data Sheet
19
Revision 1.2, 2019-12-20
TLV4968-1T
Revision history
5
Revision history
Revision
Date
Changes
Revision 1.2 2019-12-20 Updated text and figure in Chapter 2.6
Updated standards in Table 4
Added maximum tested magnetic field in Chapter 3.3
Editorial changes
Revision 1.0 2015-05-18 Initial release
Data Sheet
20
Revision 1.2 2019-12-20
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
www.infineon.com
Edition 2019-12-20
Published by
Infineon Technologies AG
81726 Munich, Germany
Legal Disclaimer
The information given in this document shall in
no event be regarded as
Warnings
Due to technical requirements, components
may contain dangerous substances. For
information on the types in question, please
contact the nearest Infineon Technologies
Office. Infineon Technologies components may
be used in life-support devices or systems only
with the express written approval of Infineon
Technologies, if a failure of such components
can reasonably be expected to cause the failure
of that life-support device or system or to affect
the safety or effectiveness of that device or
system. Life support devices or systems are
intended to be implanted in the human body or
to support and/or maintain and sustain and/or
protect human life. If they fail, it is reasonable to
assume that the health of the user or other
persons may be endangered.
a guarantee of
conditions or characteristics. With respect to any
examples or hints given herein, any typical
values stated herein and/or any information
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