TRAVEO? T2G CYT2CL_技术文档

CYT2CL

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

General description

CYT2CL is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as cluster entry units.

CYT2CL has an Arm® Cortex®-M4 CPU for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and

security processing. These devices contain embedded peripherals supporting controller area network with

flexible data rate (CAN FD), local interconnect network (LIN), clock extension peripheral interface (CXPI), LCD

controller. TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT2CL incorporates

Infineon' low-power flash memory, multiple high-performance analog and digital peripherals, and enables the

creation of a secure computing platform.

Features

• Dual CPU subsystem

- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with

• Single-cycle multiply

• Single-precision floating point unit (FPU)

• Memory protection unit (MPU)

- 100-MHz (max) 32-bit Arm® Cortex®-M0+ CPU with

• Single-cycle multiply

• Memory protection unit

- Inter-processor communication in hardware

- Three DMA controllers

• Peripheral DMA controller #0 (P-DMA0) with 76 channels

• Peripheral DMA controller #1 (P-DMA1) with 84 channels

• Memory DMA controller #0 (M-DMA0) with 4 channels

• Integrated memories

- Up to 4160 KB of code-flash with an additional 128 KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- Up to 512 KB of SRAM with selectable retention granularity

• Crypto engine^[1]

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification

• Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

Note

1. Crypto engine features are available on select MPNs.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Features

• Functional safety for ASIL-B

- Memory protection unit (MPU)

- Shared memory protection unit (SMPU)

- Peripheral protection unit (PPU)

- Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

- Low-voltage detector (LVD)

- Brown-out detector (BOD)

- Overvoltage detection (OVD)

- Clock supervisor (CSV)

• Supported in all power modes

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)

• Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

• Two threshold levels (2.7 V and 3.0 V) for BOD on V_DDDand V_{DDA_ADC}

• One threshold level (1.1 V) for BOD on V_CCD

• Wakeup support

- Up to four pins to wakeup from Hibernate mode

- Wakeup recognition bit for each wakeup source

- Up to 128 GPIO pins to wakeup from Sleep modes

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

• Clock sources

- Internal main oscillator (IMO)

- Internal low-speed oscillator (ILO)

- External crystal oscillator (ECO)

- Watch crystal oscillator (WCO)

- Phase-locked loop (PLL)

- Frequency-locked loop (FLL)

- Low-power external crystal oscillator (LPECO)

• LCD controller

- Up to four LCD controllers, with 32 segments (SEG) and four commons (COM)

- Supports both Type A (standard) and Type B (low-power) drive waveforms

- Three drive modes

• PWM drive at 1/2 bias

• PWM drive at 1/3 bias

• Digital correlation

- Operates in ACTIVE, SLEEP, and DeepSleep power modes

- Digital contrast control

• Sound subsystem

- Two time-division multiplexing (TDM) interfaces

- Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces

- Up to five sound generator (SG) interfaces

- One PCM Audio stream mixer with five input streams

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Features

• Communication interfaces

- Up to four CAN FD channels

• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

• Compliant to ISO 11898-1:2015

• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

• ISO 16845:2015 certificate available

- Up to 12 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I²C, SPI,

or UART

- Up to two independent LIN channels

• LIN protocol compliant with ISO 17987

- Up to two CXPI channels with data rate up to 20 kbps

• Serial memory interface (SMIF)

- One SPI (single, dual, quad, or octal), xSPI interface

- On-the-fly encryption and decryption

- Execute-In-Place (XIP) from external memory

• Timers

- Up to 46 16-bit and 16 32-bit timer/counter pulse-width modulator (TCPWM) blocks for regular operations

• Up to 12 16-bit counters optimized for motor-control operations (Equivalent to 6 stepper motor-control

[SMC] channels with ZPD and slew rate control capability)

• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PW-

M_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

• Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- Supports both 12- and 24-hour formats

- Automatic leap-year correction

• I/O

- Up to 140 Programmable I/Os

- Two I/O types

• GPIO Standard (GPIO_STD)

• GPIO Enhanced (GPIO_ENH)

• GPIO Stepper Motor Control (GPIO_SMC)

• High-Speed I/O Standard with Low Noise (HSIO_STDLN)

• Regulators

- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Two types of regulators

• DeepSleep

• Core internal

• Programmable analog

- One SAR A/D converter

• Each ADC supports 32 logical channels, with 48 external channels. Any external channel can be connected

to any logical channel in the SAR.

• 12-bit resolution and sampling rates up to 1 Msps

- The ADC also supports six internal analog inputs like:

• Bandgap reference to establish absolute voltage levels

• Calibrated diode for junction temperature calculations

• Two AMUXBUS inputs and two direct connections to monitor supply levels

- ADC supports addressing of external multiplexers

- ADC has a sequencer supporting autonomous scanning of configured channels

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Features

• Smart I/O

- One smart I/O block, which can perform Boolean operations on signals going to and from I/Os

- Up to eight I/Os (GPIO_STD) supported

• Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm® SWD (serial wire debug) port

- Supports Arm® Embedded Trace Macrocell (ETM) Trace

• Data trace using SWD

• Instruction and data trace using JTAG

• Compatible with industry-standard tools

- GHS/MULTI or IAR EWARM for code development and debugging

• Packages

- 144-LQFP, 16 × 16 × 1.7 mm (max), 0.4-mm lead pitch

- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch

- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch

Datasheet

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Based on Arm® Cortex®-M4F single

Table of contents

General description ...........................................................................................................................1

Features ...........................................................................................................................................1

Table of contents...............................................................................................................................5

1 Features list ...................................................................................................................................6

1.1 Peripheral instance list...........................................................................................................................................8

2 Blocks and functionality..................................................................................................................9

Block diagram...................................................................................................................................9

3 Functional description ..................................................................................................................10

3.1 CPU subsystem .....................................................................................................................................................10

3.2 System resources..................................................................................................................................................11

3.3 Peripherals ............................................................................................................................................................14

3.4 I/Os.........................................................................................................................................................................18

4 CYT2CL address map .....................................................................................................................20

5 Flash base address map.................................................................................................................22

6 Peripheral I/O map........................................................................................................................23

7 CYT2CL clock diagram ...................................................................................................................25

8 CYT2CL CPU start-up sequence ......................................................................................................26

9 Pin assignment .............................................................................................................................27

10 High-speed I/O matrix connections...............................................................................................31

11 Package pin list and alternate functions .......................................................................................32

12 Power pin assignments................................................................................................................37

13 Alternate function pin assignments ..............................................................................................38

14 Pin function description ..............................................................................................................44

15 Interrupts and wake-up assignments............................................................................................47

16 Core interrupt types....................................................................................................................56

17 Trigger multiplexer .....................................................................................................................57

18 Triggers group inputs ..................................................................................................................59

19 Triggers group outputs................................................................................................................63

20 Triggers one-to-one.....................................................................................................................64

21 Peripheral clocks ........................................................................................................................67

22 Faults.........................................................................................................................................69

23 Peripheral protection unit fixed structure pairs.............................................................................72

24 Bus masters................................................................................................................................83

25 Miscellaneous configuration ........................................................................................................84

26 Development support..................................................................................................................85

26.1 Documentation ...................................................................................................................................................85

26.2 Tools ....................................................................................................................................................................85

27 Electrical specifications...............................................................................................................86

27.1 Absolute maximum ratings ................................................................................................................................86

27.2 Device-level specifications .................................................................................................................................90

27.3 DC specifications.................................................................................................................................................91

27.4 Reset specifications ............................................................................................................................................94

27.5 I/O Specifications................................................................................................................................................95

27.6 Analog peripherals............................................................................................................................................101

27.7 AC specifications...............................................................................................................................................106

27.8 Digital peripherals.............................................................................................................................................107

27.9 Memory..............................................................................................................................................................119

27.10 System resources............................................................................................................................................121

27.11 Clock specifications ........................................................................................................................................134

27.12 Clock timing diagrams ........................................................................................................... 141

27.13 Sound subsystem specifications....................................................................................................................143

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Table of contents

27.14 CXPI specifications..........................................................................................................................................146

27.15 Serial memory interface specifications .........................................................................................................148

27.16 LCD controller specifications .........................................................................................................................153

28 Ordering information ................................................................................................................ 154

28.1 Part number nomenclature..............................................................................................................................155

29 Packaging ................................................................................................................................ 156

30 Appendix.................................................................................................................................. 160

30.1 Bootloading or End-of-line programming.......................................................................................................160

30.2 External IP revisions..........................................................................................................................................161

30.3 Internal IP revisions ..........................................................................................................................................161

31 Acronyms ................................................................................................................................. 162

32 Errata ...................................................................................................................................... 164

Revision history ............................................................................................................................ 170

Revision history change log............................................................................................................ 171

Datasheet

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Features list

1

Features list

Table 1-1

CYT2CL feature list for all packages

Package

Features

144-LQFP

176-LQFP

CPU

Core

32-bit Arm® Cortex®-M4F CPU and 32-bit Arm® Cortex®-M0+ CPU

Functional safety

ASIL-B

Operation voltage for GPIO_STD

Operation voltage for GPIO_ENH

Operation voltage for GPIO_SMC

Operation voltage for HSIO_STDLN

Core voltage

2.7 V to 5.5 V

3.0 V to 3.6 V

1.05 V to 1.15 V

Arm® Cortex®-M4 160 MHz (max) and Arm® Cortex®-M0+ 100 MHz (max),

related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on)

Operating frequency

MPU, PPU

Supported

FPU

Single precision (32-bit)

DSP-MUL/DIV/MAC

Memory

Supported by Arm® Cortex®-M4F CPU

Code-flash

Work-flash

SRAM (configurable for retention)

ROM

4160 KB (4032 KB/Large Sectors + 128 KB/Small Sectors)

128 KB (96 KB/Large Sectors + 32 KB/Small Sectors)

512 KB (SRAM0/256 KB + SRAM1/256 KB)

32 KB

Communication interfaces

CAN0 (CAN-FD: Up to 8 Mbps)

CAN1 (CAN-FD: Up to 8 Mbps)

CAN RAM

2 ch

16 KB per instance (2 ch), 32 KB in total

Serial communication block (SCB)

LIN/UART master support

CXPI controller

12 ch

2 ch

Memory interfaces

SMIF(SingleSPI/DualSPI/QuadSPI

/Octal SPI / xSPI)

1 ch (HSIO_STDLN at 100 MHz)

Timers

RTC

1 ch

34 ch

12 ch

16 ch

TCPWM (16-bit)

TCPWM (16-bit) SMC

TCPWM (32-bit)

External interrupts

Analog

108

140

1 Unit (SAR0, 32 logical channels)

48 external channels

12-bit, 1 Msps SAR ADC

6 ch for Internal sampling

Datasheet

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Features list

Table 1-1

CYT2CL feature list for all packages (continued)

Features

Package

144-LQFP

176-LQFP

Security

Flash security (program/work read

protection)

Supported

Flash chip erase enable

eSHE/HSM

Sound

Configurable

By separate firmware^[2]

Mixer

PCM-PWM

TDM

Sound generator (SG)

LCD controller

Common

1 ch (5 mixer sources)

2 ch

2 TDM structures (TDM0/1 with up to 16 ch)

5 ch

4

Segments

Type

Up to 32 segments

Type A and Type B

System

P-DMA0 with 76 channels (32 general purpose), P-DMA1 with 84 channels

(16 general purpose), and M-DMA0 with 4 channels

DMA controller

Internal main oscillator

8 MHz

Internal low-speed oscillator

32.768 kHz (nominal)

PLL

FLL

Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 160 MHz

Input frequency: 0.25 to 80 MHz, FLL output frequency: up to 100 MHz

Watchdog timer and multi-counter

Watchdog timer

Supported

Clock supervisor

Cyclic wakeup

Supported

GPIO standard (GPIO_STD)

GPIO enhanced (GPIO_ENH)

GPIO SMC (GPIO_SMC)

HSIO standard low noise (HSIO_ST-

DLN)

66

6

96

8

24

12

Smart I/O (Blocks)

Low-voltage detect

Maximum ambient temperature

Debug interface

1 block, mapped through 8 I/Os

Two, 26 selectable levels

105°C for S-grade

SWD/JTAG

Debug trace

Arm® Cortex®-M4 ETB size of 8 KB, Arm® Cortex®-M0+ MTB size of 4 KB

Note

2. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.

Datasheet

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Features list

1.1

Peripheral instance list

The following table lists the instances supported under each package for communication peripherals, based on

the minimum pins needed for the functionality.

Table 1-2

Module

CXPI

CAN0

CAN1

Peripheral instance list

144-LQFP

0/1

176-LQFP

0/1

Minimum pin function set

TX, RX

SCL, SDA

0/1

0 to 11

0/1

0 to 4

0/1

0 to 11

0/1

0 to 4

0/1

LIN0

SCB/UART

SCB/I2C

SCB/SPI

TDM/RX

TDM/TX

SG

MISO, MOSI, CLK, SELECT0

MCK, FSYNC, SCK, SD

TONE, AMPL

PWM

LINE1/2_P/N

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Blocks and functionality

2

Blocks and functionality

Block diagram

CPU Subsystem

CYT2CL

SWJ/MTB/CTI

MXS40-HT

ASIL-B

SWJ/ETM/ITM/CTI

eCT Flash

CRYPTO

AES, SHA, CRC,

TRNG, RSA, ECC

SRAM0

SRAM1

Up to 256 KB

ROM

32 KB

Arm Cortex

M0+

100 MHz

Up to 4160 KB Code-flash +

128 KB Work-flash

Arm Cortex M4

160 MHz

Up to 256 KB

8 KB $

System Resources

SRAM Controller

Initiator/MMIO

ROM Controller

FPU, NVIC, MPU

FLASH Controller

MUL, NVIC, MPU

Power

Sleep Control

POR

OVD

BOD

LVD

System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)

Peripheral Interconnect (MMIO, PPU)

REF

PWRSYS-HT

LDO

PCLK

Clock

Clock Control

Prog.

Analog

2xILO

WDT

ECO

CSV

IMO

FLL

SAR ADC

(12-bit)

3xPLL

LPECO

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

x1

Analog DFT

SARMUX

48 ch

WCO

RTC

Power Modes

Active/Sleep

LowePowerActive/Sleep

High-Speed I/O Matrix, Smart I/O, Boundary Scan

5x Smart I/O

DeepSleep

Up to 96x GPIO_STD, Up to 8x GPIO_ENH, 24x GPIO_SMC, 12x HSIO_STDLN

Hibernate

I/O Subsystem

The Block diagram gives a simplified view of the interconnection between subsystems and blocks. CYT2CL has

four major subsystems: CPU, system resources, peripherals, and I/O^[3,4]. The color-coding shows the lowest

power mode where the particular block is still functional.

CYT2CL provides extensive support for programming, testing, debugging, and tracing of both hardware and

firmware.

Debug-on-chip functionality enables in-system debugging using the production device. It does not require

special interfaces, debugging pods, simulators, or emulators.

The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.

The debug circuits are enabled by default.

CYT2CL provides a high level of security with robust flash protection and the ability to disable features such as

debug.

Additionally, each device interface can be permanently disabled for applications concerned with phishing

attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash

programming sequences. All programming, debug, and test interfaces are disabled when maximum device

security is enabled.

Notes

3. GPIO_STD supporting 2.7 V to 5.5 V V_DDIOrange.

4. GPIO_ENH supporting 2.7 V to 5.5 V V_DDIOrange with higher currents at lower voltages.

5. GPIO_SMC supporting 2.7 V to 5.5 V V_DDIOrange with currents higher than GPIO_ENH.

6. HSIO_STDLN supporting 3.0 V to 3.6 V V_DDIOrange with high-speed signaling and programmable drive strength.

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Functional description

3

Functional description

CPU subsystem

CPU

3.1

3.1.1

The CYT2CL CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and a 32-bit Arm® Cortex®-M4F

CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic

accelerator, code-flash of up to 4160 KB, 128 KB of work-flash, SRAM of up to 512 KB, and 32 KB of ROM.

The Cortex®-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following

completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,

SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by

an inter-processor communication (IPC) mechanism using hardware semaphores.

3.1.2

DMA controllers

CYT2CL has three DMA controllers: P-DMA0 with 32 general-purpose and 44 dedicated channels, P-DMA1 with 16

general-purpose and 68 dedicated channels, and M-DMA0 with four channels. P-DMA is used for

peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of

channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.

General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables

demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)

to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high

memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each

channel. They support independent accesses to peripherals using the AHB multi-layer bus.

3.1.3

Flash

CYT2CL has up to 4160 KB (4032 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash

with an additional work-flash of up to 128 KB (96 KB with 2-KB sector size, and 32 KB with 128-B sectors size).

Work-flash is optimized for reprogramming many more times than code-flash. Code-flash supports

Read-While-Write (RWW) operation allowing flash to be updated while the CPU is active. Both the code-flash and

work-flash areas support dual-bank operation for over-the-air (OTA) programming.

3.1.4

SRAM

CYT2CL has up to 512 KB of SRAM (512 KB) with two independent controllers. The first controller SRAM0 provides

DeepSleep retention in 32-KB increments while SRAM1 is selectable between fully retained and not retained.

3.1.5

ROM

CYT2CL has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and authen-

tication of user flash to guarantee a secure system.

3.1.6

Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy

check, pseudo random number generation, true random number generation, galois/counter mode, and a vector

unit to support asymmetric key cryptography such as RSA and ECC.

Depending on the part number, this block is either completely or partially available or not available at all. See

Ordering information for more details.

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Functional description

3.2

System resources

Power system

3.2.1

The power system ensures that the supply voltage levels meet the requirements of each power mode, and

provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip

reset during the initial power ramp.

Three Brown-Out Detection (BOD) circuits monitor the external supply voltages (V_DDD, V_{DDA_ADC}, V_CCD). The BOD

on V_DDDand V_CCDare initially enabled and cannot be disabled. The BOD on V_{DDA_ADC}is initially disabled and can

be enabled by the user. For the external supplies V_DDDand V_{DDA_ADC}, BOD circuits are software configurable with

two settings; a 2.7-V minimum voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which

is also robust for all I/O specifications (which are guaranteed at 2.7 V). The BOD on V_CCDis provided as a safety

measure and is not a robust detector.

Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (V_DDD, V_{DDA_ADC}, V_CCD),

and overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on V_DDD

and V_{DDA_ADC}are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.

Two voltage detection circuits are provided to monitor the external supply voltage (V_DDD) for falling and rising

levels, each configurable for one of the 26 selectable levels.

All BOD, OVD, and OCD circuits on V_DDDand V_CCDgenerate a reset, because these protect the CPUs and fault logic.

The BOD and OVD circuits on V_{DDA_ADC}can be configured to generate either a reset, or a fault.

3.2.2

Regulators

CYT2CL contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core

internal. These regulators accept a 2.7–5.5-V V_DDDsupply and provide a low-noise 1.1-V supply to various parts

of the device. These regulators are automatically enabled and disabled by hardware and firmware when

switching between power modes. The core internal regulators operate in Active mode, and provide power to the

CPU subsystem and associated peripherals.

3.2.2.1

DeepSleep

The DeepSleep regulator is used to maintain power to a small number of blocks when in DeepSleep mode. These

blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration

memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal regulator is

disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is disabled.

3.2.2.2

Core internal

The core internal regulator supports load currents up to 150 mA, and is operational during device startup (boot

process), and in Active/Sleep modes.

3.2.3

Clock system

The CYT2CL clock system provides clocks to all subsystems that require them, and glitch-free switching between

different clock sources. In addition, the clock system ensures that no metastable conditions occur.

The clock system for CYT2CL consists of the 8-MHz IMO, two ILOs, three watchdog timers, three PLLs, an FLL, five

clock supervisors (CSV), a 7.2- to 33.34-MHz ECO, a 4- to 8-MHz LPECO, and a 32.768-kHz WCO.

The clock system supports two main clock domains: CLK_HF and CLK_LF.

• CLK_HFx are the active domain clocks. Each can use any of the high-frequency clock sources including IMO,

EXT_CLK, ECO, LPECO, FLL, or PLL.

• CLK_LF is a DeepSleep domain clock and provides source for MCWDT or RTC modules. The reference clock for

the CLK_LF domain is selectable from ILO0, ILO1, WCO, or disabled.

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Functional description

Table 3-1

Name

CLK_HF destinations

Description

CLK_HF0

CLK_HF1

CLK_HF2

CLK_HF3

CLK_HF4

CLK_HF5

CPUSS clocks, PERI, and AHB infrastructure

Event Generator, also available in HSIOM as an output

Sound Subsystem #0

Sound Subsystem #1

Sound Subsystem #2

SMIF #0

3.2.3.1

IMO clock source

The IMO is the frequency reference in CYT2CL when no external reference is available or enabled. The IMO

operates at a frequency of around 8 MHz.

3.2.3.2

ILO clock source

An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in

DeepSleep mode. There are two ILOs to ensure CSV (clock supervisor) capability in DeepSleep mode. ILO-driven

counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-

vision.

3.2.3.3

PLL and FLL

A PLL (two 200 MHz and one 400 MHz) or FLL may be used to generate high-speed clocks from the IMO, ECO, or

an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 35 µs) in exchange for a small

amount (±2%) of frequency error^[7]and a lower max output frequency (100 MHz instead of up to 400 MHz).

400-MHz PLLs supports spread spectrum clock generation (SSCG) with down spreading.

3.2.3.4

Clock supervisor

Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).

Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the

frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the

frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an

abnormal state is signaled and either a reset or an interrupt is generated.

3.2.3.5

EXT_CLK

One of two I/Os can be used to provide an external clock input of up to 100 MHz. This clock can be used as the

source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.

3.2.3.6

ECO

The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.

It supports fundamental mode (non-overtone) quartz crystals, in the range of 7.2 to 33.34 MHz. When used in

conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO

accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the

available I/O functions.

Note

7. Operation of reference-timed peripherals (such as a UART) with an FLL-based reference is not recommended due to the allowed

frequency error.

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.2.3.7

LPECO

The LPECO provides high-frequency clocking using an external crystal connected to the LPECO_IN and

LPECO_OUT pins. It supports fundamental mode (non-overtone) quartz crystals, in the range of 3.99 to 8.01 MHz.

LPECO can operate during DeepSleep, and Hibernate modes with significant lower current consumptions. It can

also be used for real-time-clock applications. When used in conjunction with the PLL, it generates CPU and

peripheral clocks up to device’s maximum frequency.

3.2.3.8

WCO

The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external

32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock

reference for CLK_LF, which is the clock source for the MCWDT and RTC.

3.2.4

Reset

CYT2CL can be reset from a variety of sources, including software. Reset events are asynchronous and guarantee

reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset,

fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software

to determine the cause of the reset. An XRES_L pin is available for external reset.

3.2.5

Watchdog timers

CYT2CL has one watchdog timer (WDT) and two multi-counter watchdog timers (MCWDT).

The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from

Hibernate. This allows watchdog operation during all power modes and needs to be serviced during a configured

window, otherwise generates a watchdog reset, if not serviced before the timeout occurs. A watchdog reset is

recorded in the Reset Cause register.

An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are

only available in the Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used

separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.

3.2.6

Power modes

CYT2CL has six different power modes:

• Active – All peripherals are available

• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are

available, but with limited capability

• Sleep – All peripherals except the CPUs are available

• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are

available, but with limited capability

• DeepSleep – Only peripherals which work with CLK_LF are available

• Hibernate – The device and I/O states are frozen; the device resets on wakeup

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.3

Peripherals

3.3.1

Peripheral clock dividers

Integer and fractional clock dividers are provided for peripheral and timing purposes.

Table 3-2 Clock dividers

Divider

Count

11

16

Description

div_8

div_16

Integer divider, 8 bits

Integer divider, 16 bits

div_16_5

div_24_5

4

11

Fractional divider, 16.5 bits (16 integer bits, 5 fractional bits)

Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

3.3.2

Peripheral protection unit

The Peripheral protection unit (PPU) controls and monitors unauthorized access from all masters (CPU,

P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the

bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address

range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).

3.3.3

12-bit SAR ADC

CYT2CL contains one 1-Msps SAR ADCs. This ADC can be clocked at up to 26.67 MHz and provide a 12-bit result in

26 clock cycles.

The references for the SAR ADC comes from a dedicated pair of inputs: VREFH and VREFL^[8]

.

CYT2CL supports 32 logical ADC channels which can select one of 54 input sources. Sources include 48 external

inputs from I/Os, and six internal connections for diagnostic and monitoring purposes.

The number of ADC channels (per ADC and package type) are listed in Table 1-1.

SAR ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with

zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1

Msps whether it is for a single channel or distributed over several channels). The sequencer switching is

controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the

appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates

subsequent conversions for repetitive or group conversions without CPU intervention.

SAR ADC has two analog multiplexers used to connect the signals to be measured to the ADC. One is SARMUX0

which has 24 GPIO_STD inputs (ADC[0]_0 to ADC[0]_23), and six additional inputs to measure internal signals

such as a band-gap reference, a temperature sensor, V_CCD, V_{DDA_ADC}power supplies and AMUXBUSA/B signals.

The other multiplexer is SARMUX1 which has 24 GPIO_SMC inputs (ADC[1]_0 to ADC[1]_23).

CYT2CL has a temperature sensor. Software post processing is required to convert the temperature sensor

reading into kelvin or Celsius values.

To accommodate signals with varying source impedances and frequencies, it is possible to have different sample

times programmed for each channel. ADC also supports range comparison, which allows fast detection of

out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate

the measurement for out-of-range values.

The ADC is not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input

reference voltage VREFH range is 2.7 V to V_{DDA_ADC}and VREFL is V_{SSA_ADC}

.

Note

8. VREF_L prevents IR drops in the VSSIO and VSSA_ADC paths from impacting the measurements. VREF_L, when properly connected,

reduces or removes the impact of IR drops in the VSSIO and VSSA_ADC paths from measurements.

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.3.4

Timer/counter/PWM block (TCPWM)

The TCPWM block consists of 16-bit (46 channels) and 32-bit (16 channels) counters with user-programmable

period. Twelve of the 16-bit counters are optimized for DC and stepper motor-control operations. Each TCPWM

counter contains a capture register to record the count at the time of an event, a period register (used to either

stop or auto-reload the counter when its count is equal to the period register), and compare registers to generate

signals that are used as PWM duty-cycle outputs.

Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,

PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.

The TCPWM block also provides true and complement outputs, with programmable offset between them, to

allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the

PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems

when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time

for software intervention).

Twelve of the 16-bit counters are optimized for DC and stepper motor-control operations, these also have ZPD

(Zero Point detection) and slew rate control capabilities. Two of these TCPWM channels constitute one SMC

channel.

3.3.5

Serial Communication Blocks (SCB)

CYT2CL contains 12 serial communication blocks, each configurable to support I²C, UART, or SPI.

3.3.5.1

I²C interface

An SCB can be configured to implement a full I²C master (capable of multi-master arbitration) or slave interface.

Each SCB configured for I²C can operate at speeds of up to 1 Mbps (Fast-mode Plus^[9]) and has flexible buffering

options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO buffering

for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the need for

clock stretching. The₂I²C interface is compatible with Standard, Fast-mode, and Fast-mode Plus devices as

specified in the NXP I C-bus specification and user manual (UM10204). The I²C-bus I/O is implemented with GPIO

in open-drain modes^{[10, 11]}

.

3.3.5.2

UART interface

When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined

by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and

SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit multi-

processor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common

UART functions such as parity, number of stop bits, break detect, and frame error are supported. FIFO buffering

of transmit and receive data allows greater CPU service latencies to be tolerated.

The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one

master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.

Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software interaction

and increased CPU load.

Notes

9. I/Os drive level does not support the full bus capacitance in Fast-mode Plus speeds.

10.This is not 100 percent compliant with the I²C-bus specification; I/Os are not high-voltage compliant, do not support the 20-mA sink

requirement of Fast-mode Plus, and violate the leakage specification when no power is applied.

11.See Table 27-10 'Serial Communication Block (SCB) specifications' for supported IO-cells and I²C modes.

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.3.5.3

SPI interface

The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start

pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The SPI

interface can use the FIFO and operates with up to a 12.5-MHz SPI Clock. SCB also supports EZSPI^[12]mode.

SCB0 supports the following additional features:

• Operable as a slave in DeepSleep mode

• I²C slave EZ (EZI2C^[13]) mode with up to 256-B data buffer for multi-byte communication without CPU

intervention

• I²C slave externally-clocked operations

• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention

3.3.6

CAN FD

CYT2CL supports two CAN FD controller blocks, each supporting two CAN FD channel. All CAN FD controllers are

compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the

time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in

hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx

handler manages message acceptance filtering, transfer of received messages from the CAN core to a message

RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages

from the message RAM, to the CAN core, and provides transmit-message status.

3.3.7

Local interconnect network (LIN)

CYT2CL contains up to two LIN channels. Each channel supports transmission/reception of data following the LIN

protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin

interface (including an enable function) and supports master and slave functionality. Each channel also supports

classic and enhanced checksum, along with break detection during message reception and wake-up signaling.

Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.

3.3.8

Clock extension peripheral interface (CXPI)

CYT2CL contains up to two CXPI channels compliant with JASO D015 and ISO standard 20794 including the

controller specification.

Each channel supports:

• Master and slave functionality

• Polling and event trigger method for both normal and long frames

• Non-return to zero (NRZ) and PWM signaling modes

• Collision resolution and carries sense multiple access

• Wakeup pulse generation and detection

• CRC8 and CRC16 for both normal and long frames

• Error detection

• Dedicated FIFO (16 B) for transmit and receive

Notes

12.The Easy SPI (EZSPI) protocol is based on the Motorola SPI operating in any mode (0, 1, 2, or 3). It allows communication between

master and slave, and reduces the need for CPU intervention.

13.The Easy I²C (EZI2C) protocol is a unique communication scheme built on top of the I²C protocol by Infineon. It uses a meta protocol

around the standard I²C protocol to communicate to an I²C slave using indexed memory transfers. This reduces the need for CPU

intervention.

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Based on Arm® Cortex®-M4F single

Functional description

3.3.9

Serial memory interface

In addition to the internal flash memory, CYT2CL supports direct connection to 128 MB of external flash or RAM

memory. This connection is made through either a xSPI or serial peripheral interface (SPI). xSPI allows

connection to HYPERFLASH™ and HYPERRAM™ devices, while SPI (single, dual, quad, or octal SPI) can connect

with serial flash memory. Code stored in memory connected through this interface allows execute-in-place (XIP)

operation, which does not require the instructions to be first copied to internal memory, and on-the-fly

encryption and decryption for environments requiring secure external data and code.

3.3.10

Sound subsystem

CYT2CL supports the following,

• Up to two time-division multiplexing (TDM) interfaces

- Full-duplex transmitter and receiver operation

- Independent transmitter or receiver operation, each in master or slave mode

- Up to 16 channels, each channel can be individually enabled or disabled

• Up to two pulse code modulation-pulse width modulation (PCM-PWM) interface

- Conversion of PCM audio streaming to PWM signals

- Up to 32-bit output sample resolution

- Supports E- and H-bridge formats

- Dead time insertion

• Up to five sound generator (SG) interfaces

- PWM modulated (amplitude, tone) sound generation

- Separate volume and frequency control (two signals) and combined volume-frequency control (one signal)

formats

• One mixer supporting five input sources

- Combines multiple PCM source streams into a single PCM destination stream

- PCM source stream can be gain/volume controlled

- Fixed PCM sample formatting (16-bit pairs)

- LPF support by FIR filter

- Fade-in and Fade-out control for both source and destination PCM streams

3.3.11

One-time-programmable (OTP) eFuse

CYT2CL devices contain a 1024-bit OTP eFuse memory that can be used to store and access a unique and

unalterable identifier or serial number for each device. eFuses are also used to control the device life-cycle

(manufacturing, programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits,

192 are available for user purposes.

3.3.12

Event generator

The event generator supports generation of interrupts and triggers in the Active mode and interrupts in the

DeepSleep mode. The event generators are used to trigger a specific device function (execution of an interrupt

handler, a SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from the DeepSleep mode.

They provide CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions,

thus reducing overall power consumption and processing overhead.

3.3.13

Trigger multiplexer

CYT2CL supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of

the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other

peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers

provide active logic functionality and are typically supported in the Active mode.

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Based on Arm® Cortex®-M4F single

Functional description

3.4

I/Os

CYT2CL has up to 140 programmable I/Os.

The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on and

reset, the I/Os are forced to the High-Z state. During the Hibernate mode, the I/Os are frozen.

Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service

routine (ISR) associated with it.

The I/O port power source mapping is listed in Table 3-3. The associated supply determines the V_OH, V_OL, V_IH, and

V_ILlevels when configured for CMOS and Automotive thresholds.

Table 3-3

I/O port power source

Supply

Ports

VDDD

P0, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19

VDDIO_GPIO

VDDIO_HSIO

VDDIO_SMC

P1, P2, P3, P4

P8, P9

P5, P6, P7

Each I/O implements the following:

• Programmable drive mode

- High impedance

- Resistive pull-up

- Resistive pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up or pull-down

- Weak pull-up or pull-down

CYT2CL has four types of programmable GPIOs: GPIO Standard, GPIO Enhanced, GPIO SMC, HSIO Standard with

Low noise. Only GPIO_STD, GPIO_ENH, and GPIO_SMC have the capability to wakeup the device from DeepSleep

mode.

3.4.1

GPIO

Three types of GPIOs are supported:

• GPIO_STD, GPIO_ENH, and GPIO_SMC

These implement the following:

• Configurable input threshold (CMOS, TTL, or Automotive)

• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)

• Analog input mode (input and output buffers disabled)

• Edge-triggered interrupts on rising edge, falling edge, or on both the edges, on pin basis

3.4.1.1

GPIO standard (GPIO_STD)

Supports standard automotive signaling across the 2.7-V to 5.5-V V_DDIOrange. GPIO Standard I/Os have multiple

configurable drive levels, drive modes, and selectable input levels.

3.4.1.2

GPIO enhanced (GPIO_ENH)

Supports extended functionality automotive signaling across the 2.7-V to 5.5-V V_DDIOrange with higher currents

at lower voltages (full I²C timing support, slew-rate control).

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.4.1.3

GPIO SMC (GPIO_SMC)

Provides significant drive strength than GPIO_STD and GPIO_ENH (Supports 30-mA drive).

3.4.2

HSIO

These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep

operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIOs support programmable

drive strength. They are available only in Active mode.

3.4.2.1

HSIO standard low noise (HSIO_STDLN)

Supports clocking and signaling up to 100 MHz. Also supports holding state during DeepSleep mode. Low noise

version optimizes the noise generated by having specific modes for each interface support.

3.4.3

Port nomenclature

Px.y describes a particular bit “y” available within an I/O port “x.”

• For example, P4.2 reads “port 4, bit 2”.

3.4.4

Smart I/O

Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals

coming into the chip. CYT2CL has one Smart I/O block. Operation can be synchronous or asynchronous and the

blocks operate in all device power modes except for the Hibernate mode.

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Based on Arm® Cortex®-M4F single

CYT2CL address map

4

CYT2CL address map

The CYT2CL microcontroller supports the memory spaces shown in Figure 4-1:

• Code-flash

- 4160 KB (4032 KB + 128 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit

in the flash control register

• Single-bank mode - 4160 KB

• Dual-bank mode - 2080 KB per bank

• Work-flash

- 128 KB (96 KB + 32 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the

flash control register

• Single-bank mode - 128 KB

• Dual-bank mode - 64 KB per bank

• 32 KB of secure ROM

• 512 KB of SRAM (First 2 KB is reserved for internal usage)

• 128 MB SMIF XIP

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CYT2CL address map

0xFFFF FFFF

Arm System

Space

CPU & Debug Registers

0xE000 0000

0x43FF FFFF

Reserved

Peripheral

Interconnect or

Memory map

Mainly used for on-chip peripherals

e.g., AHB or APB Peripherals

0x4000 0000

0x1FFF FFFF

Reserved

128 MB

Serial Memory Interface XIP

SMIF_XIP

0x1800 0000

Reserved

32 KB

Reserved

32 KB

Alternate Flash

Supervisory Region

0x1780 7FFF

0x1780 0000

Used to store manufacture specific

data like flash protection settings, trim

settings, device addresses, serial numbers,

calibration data, etc.

Flash Supervisory

Region

0x1700 7FFF

0x1700 0000

Reserved

0x1401 FFFF

32 KB

(128 B Small Sectors)

Work flash used for long

term data retention

0x1401 8000

0x1401 7FFF

Work flash

Code flash

96 KB

(2 KB Large Sectors)

0x1400 0000

0x1040 FFFF

Reserved

128 KB

(8 KB Small Sectors)

0x103F 0000

0x103E FFFF

Mainly used for user program code

4032 KB

(32 KB Large Sectors)

0x1000 0000

0x0807 FFFF

Reserved

256 KB

SRAM1

SRAM0

General purpose RAM,

mainly used for data

0x0804 0000

0x0803 FFFF

254 KB

2 KB

0x0800 0800

0x0800 0000

Secured Boot ROM to set user specified

protection levels, trim and configuration

data, code authentication, jump to user mode etc.

Reserved

0x0000 7FFF

0x0000 0000

ROM

32 KB

Figure 4-1

CYT2CL address map^{[14, 15]}

Notes

14.The size representation is not up to scale.

15.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained

in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.

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Flash base address map

5

Flash base address map

Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions

along with their respective base addresses.

Table 5-1

Code-flash address mapping in single bank mode

Code-flash Size (KB) Large Sectors (LS) Small Sectors (SS)

4160 32 KB × 126 8 KB × 16

Large Sector Base Address

Small Sector Base Address

0x1000 0000

0x103F 0000

Table 5-2

Work-flash address mapping in single bank mode

Work-flash Size (KB)

Large Sectors

Small Sectors

Large Sector Base Address

Small Sector Base Address

128

2 KB × 48

128 B × 256

0x1400 0000

0x1401 8000

Table 5-3

Code-flash address mapping in dual bank mode (Mapping A)

First Half

LS Base

Address

First Half

Second Half Second Half

Code-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

LS Base

Address

SS Base

Address

Half LS

Half SS

4160

32 KB × 63

8KB × 8

32 KB × 63

8 KB × 8

0x1000 0000 0x101F 8000 0x1200 0000 0x121F 8000

Table 5-4

Code-flash address mapping in dual bank mode (Mapping B)

First Half

LS Base

Address

First Half

Second Half Second Half

Code-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

LS Base

Address

SS Base

Address

Half LS

Half SS

4160

32 KB × 63

8 KB × 8

32 KB × 63

8 KB × 8

0x1200 0000 0x121F 8000 0x1000 0000 0x101F 8000

Table 5-5

Work-flash address mapping in dual bank mode (Mapping A)

First Half

LS Base

Address

First Half

Second Half Second Half

Work-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

LS Base

Address

SS Base

Address

Half LS

Half SS

128

2 KB × 24

128 B × 128

2 KB × 24

128 B × 128 0x1400 0000 0x1400 C000 0x1500 0000 0x1500 C000

Table 5-6

Work-flash address mapping in dual bank mode (Mapping B)

First Half

LS Base

Address

First Half

Second Half Second Half

Work-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

LS Base

Address

SS Base

Address

Half LS

Half SS

128

2 KB × 24

128 B × 128

2 KB × 24

128 B × 128 0x1500 0000 0x1500 C000 0x1400 0000 0x1400 C000

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Peripheral I/O map

6

Peripheral I/O map

CYT2CL peripheral I/O map

Description

Table 6-1

Base

Instance

size

Section

Instances

Group Slave

address

Peripheral interconnect

Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9)

Peripheral trigger group

Peripheral 1:1 trigger group

Peripheral interconnect, master interface

PERI Programmable PPU

PERI Fixed PPU

0x4000 0000

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 0800

0x4010 0000

0x4020 0000

0x4021 0000

0x4022 0000

0x4022 1000

0x4023 0000

0x4023 2000

0x4023 4000

0x4024 0000

9

0x20

0x400

PERI

0

13

[16]

PERI_MS

6

0x40

0

1

450

Crypto

CPUSS

Cryptography component

CPU subsystem (CPUSS)

Fault structure subsystem

Fault structures

1

2

0

FAULT

2

1

4

0x100

Inter process communication

IPC structures

IPC

8

0x20

2

IPC interrupt structures

Protection

PROT

Shared memory protection unit structures

Memory protection unit structures

Flash controller

16

0x40

2

3

4

0x400

FLASHC

System Resources Sub-System Core Registers 0x4026 0000

Clock Supervision High Frequency

Clock Supervision Reference Frequency

Clock Supervision Low Frequency

Clock Supervision Internal Low Frequency

Multi Counter WDT

0x4026 1400

0x4026 1710

0x4026 1720

0x4026 1730

0x4026 8000

0x4026 C000

0x4027 0000

0x4027 1000

0x4028 0000

0x4028 8000

0x4029 0000

0x4029 8000

0x402A 0000

0x402A 1000

0x402C 0868

0x4030 0000

0x4031 0000

3

1

2

1

0x10

SRSS

2

5

0x100

Free Running WDT

SRSS Backup Domain/RTC

Backup Register

BACKUP

P-DMA

2

6

7

8

9

4

0x04

0x40

P-DMA0 Controller

P-DMA0 channel structures

P-DMA1 Controller

76

84

P-DMA1 channel structures

M-DMA0 Controller

M-DMA

M-DMA0 channels

4

6

0x100

0x04

0x10

0x80

eFUSE

HSIOM

GPIO

eFUSE Customer Data (192 bits)

High-Speed I/O Matrix (HSIOM)

GPIO port control/configuration

2

3

10

0

20

1

Note

16.These six Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the

device specific TRM to know more about the configuration of these programmable PPUs.

Datasheet

24

002-32508 Rev. *F

2022-10-20

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Peripheral I/O map

Table 6-1

Section

CYT2CL peripheral I/O map (continued)

Base

Instance

size

Description

Instances

Group Slave

address

Programmable I/O configuration

SMART I/O port configuration

Timer/Counter/PWM 0 (TCPWM0)

TCPWM0 Group #0 (16-bit)

TCPWM0 Group #1 (16-bit, Motor control)

TCPWM0 Group #2 (32-bit)

LCD Controller

0x4032 0000

0x4032 0C00

0x4038 0000

0x4038 8000

0x4039 0000

0x403B 0000

0x403B 0100

0x403F 0000

0x403F 0800

0x4042 0000

0x4042 0800

0x4050 0000

0x4050 8000

SMARTIO

3

2

1

0x100

34

12

16

0x80

TCPWM

3

LCD

3

4

5

4

5

0

1

2

LCD Data

4

16

2

0x100

0x20

Event generator 0 (EVTGEN0)

Event generator 0 comparator structures

Serial Memory Interface 0 (SMIF0)

SMIF0 Devices

EVTGEN

SMIF

LIN

0x80

Local Interconnect Network 0 (LIN0)

LIN0 Channels

2

0x100

Clock Extension Peripheral Interface 0 (CXPI0) 0x4051 0000

CXPI

CXPI0 Channels

CAN0 controller

Message RAM CAN0

CAN1 controller

Message RAM CAN1

0x4051 8000

0x4052 0000

0x4053 0000

0x4054 0000

0x4055 0000

0x4060 0000

0x4081 0000

0x4081 8000

0x4082 0000

0x4082 8000

0x4083 0000

0x4083 8000

0x4088 0000

0x4088 8000

0x4088 C000

0x4090 0000

0x4090 0800

0x4090 1800

2

0x100

0x200

0x1FFF

0x200

TTCANFD

SCB

2

12

2

5

6

8

3

0-11

0

0x1FFF

0x10000

2

Serial Communications Block (SPI/UART/I C)

Time Division Multiplexer 0 (TDM0)

TDM0 Structures

0x200

0x100

Sound Generator 0 (SG0)

SG0 Structures

8

1

2

5

Sound

Pulse Width Modulation 0 (PWM0)

PWM0 Structures

2

Mixer0

Mixer0 Source Structures

Mixer0 Destination Structures

Programmable Analog Subsystem (PASS0)

SAR0 channel controller

SAR0 channel structures

SAR1 channel structures

5

1

8

9

4

0

SAR PASS

24

0x40

Datasheet

25

002-32508 Rev. *F

2022-10-20

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

CYT2CL clock diagram

7

CYT2CL clock diagram

IMO EXT_CLK ECO

WCO

LS

ILO0

LS

ILO1

LS

LPECO

LS

LPECO

ECO

Prescaler

LS

MUX

LS

MUX

PLL#0

PLL400#0

PLL#1

PLL200#1

PLL#2

PLL200#2

MUX

FLL

CLK_ILO0

LS

CLK_

PATH0

CLK_

PATH1

CLK_

PATH2

CLK_

PATH3

CLK_

PATH4

CLK_REF_HF

WDT

MUX

CLK_LF

CLK_BAK

RTC

CSV

MUX

CLK_ILO0

MCWDT

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

CLK_HF0

CLK_HF1

CLK_HF2

CLK_HF3

CLK_HF4

CLK_HF5

CLK_HF6

CSV

CLK_ILO0

CLK_LF

CLK_ILO0

CLK_REF_HF

SMIF

Event

Generator

ROM/SRAM/

FLASH

Divider

(1-256)

Divider

(1-256)

CM4

CLK_FAST

CLK_SLOW

CLK_PERI

CPUSS Fast

Infrastructure

Divider

(1-256)

CM0+

CPUSS Slow

Infrastructure

P-DMA /

M-DMA

Divider

(1-256)

CRYPTO

PERI

CLK_GR3

CLK_GR4

CLK_GR5

CLK_GR6

CLK_GR9

Divider

(1-256)

SRSS

EFUSE

TCPWM

Segment LCD

IOSS

Divider

(1-256)

Divider

(1-256)

CAN FD

LIN

Divider

(1-256)

CXPI

SCB[*]

SCB[0]

SAR ADC

Serial Interface Clock

LEGEND 1:

LEGEND 2:

CPUSS

(Trace Clock)

Active Domain

DeepSleep Domain

Hibernate Domain

PCLK_TCPWM0_CLOCKS[x]

PCLK_LCD0_CLOCK

Peripheral

Clock Dividers

PCLK_SMARTTIO7_CLOCK

PCLK_CANFD[x]_CLOCK_CAN[y]

PCLK_LIN_CLOCK_CH_EN[x]

PCLK_CXPI_CLOCK_CH_EN[x]

PCLK_SCB[x]_CLOCK

Relationship of Monitored Clock and

Reference Clock

PCLK_PASS_CLOCK_SAR0

PCLK_CPUSS_CLOCK_TRACE_IN

Monitored Clock

TDM

SG

Reference Clock

CSV

Divider

(1-256)

CLK_GR8

LEGEND 3:

One Clock Line

Multiple Clock Lines

PWM

MIXER

Figure 7-1

CYT2CL clock diagram

Datasheet

26

002-32508 Rev. *F

2022-10-20

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

CYT2CL CPU start-up sequence

8

CYT2CL CPU start-up sequence

The following steps describe the start-up sequence:

1. System Reset (@0x0000 0000)

2. CM0+ executes ROM boot (@0x0000 0004)

i. Applies trims

ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory

flash

iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it

3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)

i. Debug pins are configured as per the SWD/JTAG spec^[17]

ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash

(@0x1000 0000)

iii.CM0+ branches to its Reset handler

4. CM0+ starts execution

i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)

ii. Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the location of CM4 vector table mentioned in flash

(specified in CM4 linker definition file)

iii.Releases CM4 from reset

iv.Continues execution of CM0+ user application

5. CM4 executes directly from either code-flash or SRAM

i. CM4 branches to its Reset handler

ii. Continues execution of CM4 user application

Note

17.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, see

Table 11-1 for pin assignments.

Datasheet

27

002-32508 Rev. *F

2022-10-20

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Pin assignment

9

Pin assignment

VSSIO_HSIO

P8.0

1

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

VDDIO_GPIO

VSSA_ADC

VDDA_ADC

VREFH

P3.3

2

P8.1

3

P8.2

4

P8.3

5

VSSIO_HSIO

VDDIO_HSIO

P8.4

6

P3.2

7

P3.1

8

P3.0

P8.5

9

P2.7

P8.6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P2.6

P8.7

P2.5

VSSIO_HSIO

VDDIO_HSIO

P9.0

P2.4

P2.3

P2.2

P9.1

P2.1

P9.2

P2.0

P9.3

P1.7

VDDIO_HSIO

VSSIO_HSIO

VDDD

P1.6

P1.5

P1.4

VCCD

P1.3

VSSD

P1.2

P10.0

P1.1

176-LQFP

P10.1

P1.0

P10.2

XRES_L

VSSD

VCCD

VDDD

P0.3

P10.3

P10.4

P11.0

P11.1

P11.2

P11.3

P0.2

P11.4

P0.1

P11.5

P0.0

P11.6

VSSD

P19.6

P19.5

P19.4

P19.3

P19.2

P19.1

P19.0

P18.7

P18.6

VSSD

P11.7

98

P12.0

97

P12.1

96

P12.2

95

P12.3

94

P12.4

93

P12.5

92

P12.6

91

P12.7

90

VSSD

89

Figure 9-1

176-LQFP pin assignment

Datasheet

28

002-32508 Rev. *F

2022-10-20

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Pin assignment

VSSIO_HSIO

SCB10_CLK (0)/SCB10_RX (0)/SCB10_SDA (0)/IO_CLK_HF[2]/SPIHB_SELECT1 P8.0

SCB10_MOSI (0)/SCB10_TX (0)/SCB10_SCL (0)/SPIHB_SELECT0 P8.1

SCB10_MISO (0)/SCB10_RTS (0)/SPIHB_DATA7 P8.2

1

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

VDDIO_GPIO

2

VSSA_ADC

3

VDDA_ADC

4

VREFH

SCB10_SEL0 (0)/SCB10_CTS (0)/SPIHB_DATA6 P8.3

5

P3.3 PWM0_27/PWM0_26_N/TC0_25_TR/SCB8_SEL0 (1)/SCB8_CTS (1)/TRIG_IN[5]/ADC[0]_13

P3.2 PWM0_26/PWM0_25_N/TC0_24_TR/EXT_MUX[0]_EN/SCB8_MISO (1)/SCB8_RTS (1)/TRIG_IN[4]/SWJ_TRSTN/ADC[0]_12

P3.1 PWM0_25/PWM0_24_N/TC0_33_TR/EXT_MUX[0]_2/SCB8_MOSI (1)/SCB8_TX (1)/SCB8_SCL (1)/SWJ_SWDOE_TDI/ADC[0]_11

P3.0 PWM0_24/PWM0_33_N/TC0_32_TR/EXT_MUX[0]_1/LIN1_EN/CXPI1_EN/SCB8_CLK (1)/SCB8_RX (1)/SCB8_SDA (1)/SWJ_SWDIO_TMS/ADC[0]_10

P2.7 PWM0_H_15/PWM0_H_14_N/TC0_H_13_TR/EXT_MUX[0]_0/LIN1_TX/CXPI1_TX/TRIG_IN[3]/SWJ_SWCLK_TCLK/ADC[0]_9

P2.6 PWM0_H_14/PWM0_H_13_N/TC0_H_12_TR/LIN1_RX/CXPI1_RX/TRIG_IN[0]/SWJ_SWO_TDO/HIBERNATE_WAKEUP[2]

P2.5 PWM0_H_13/PWM0_H_12_N/TC0_H_11_TR/CAN0_1_RX/TRIG_DBG[0]/CAL_SUP_NZ/RTC_CAL/HIBERNATE_WAKEUP[1]

P2.4 PWM0_H_12/PWM0_H_11_N/TC0_H_10_TR/LIN0_EN/CXPI0_EN/CAN0_1_TX/SCB8_SEL1 (0)/TRIG_IN[2]/ADC[0]_8

P2.3 PWM0_H_11/PWM0_H_10_N/TC0_H_9_TR/LIN0_RX/CXPI0_RX/CAN0_0_RX/SCB8_SEL0 (0)/SCB8_CTS (0)/TRIG_IN[1]/ADC[0]_7/HIBERNATE_WAKEUP[0]

P2.2 PWM0_H_10/PWM0_H_9_N/TC0_H_8_TR/LIN0_TX/CXPI0_TX/CAN0_0_TX/SCB8_MISO (0)/SCB8_RTS (0)/TRIG_DBG[1]/ADC[0]_6

P2.1 PWM0_H_9/PWM0_H_8_N/TC0_H_7_TR/SCB8_MOSI (0)/SCB8_TX (0)/SCB8_SCL (0)/ADC[0]_5

P2.0 PWM0_H_8/PWM0_H_7_N/TC0_H_6_TR/SCB8_CLK (0)/SCB8_RX (0)/SCB8_SDA (0)/ADC[0]_4

P1.7 PWM0_H_7/PWM0_H_6_N/TC0_H_5_TR

VSSIO_HSIO

6

VDDIO_HSIO

7

SCB10_SEL1 (0)/SPIHB_DATA5 P8.4

8

EXT_CLK/SPIHB_DATA4 P8.5

9

SCB11_CLK (0)/SCB11_RX (0)/SCB11_SDA (0)/SPIHB_DATA3 P8.6

SCB11_MOSI (0)/SCB11_TX (0)/SCB11_SCL (0)/TRACE_DATA_3/SPIHB_DATA2 P8.7

VSSIO_HSIO

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VDDIO_HSIO

SCB11_MISO (0)/SCB11_RTS (0)/TRACE_DATA_2/SPIHB_DATA1 P9.0

SCB11_SEL0 (0)/SCB11_CTS (0)/TRACE_DATA_1/SPIHB_DATA0 P9.1

SCB11_SEL1 (0)/TRACE_DATA_0/SPIHB_CLK P9.2

TRACE_CLOCK/SPIHB_RWDS P9.3

VDDIO_HSIO

P1.6 PWM0_H_6/PWM0_H_5_N/TC0_H_4_TR

VSSIO_HSIO

P1.5 PWM0_H_5/PWM0_H_4_N/TC0_H_3_TR

VDDD

P1.4 PWM0_H_4/PWM0_H_3_N/TC0_H_2_TR/SCB7_SEL1 (0)

VCCD

P1.3 PWM0_H_3/PWM0_H_2_N/TC0_H_1_TR/SCB7_SEL0 (0)/SCB7_CTS (0)/FAULT_OUT_3/ADC[0]_3

P1.2 PWM0_H_2/PWM0_H_1_N/TC0_H_0_TR/SCB7_MISO (0)/SCB7_RTS (0)/FAULT_OUT_2/ADC[0]_2

P1.1 PWM0_H_1/PWM0_H_0_N/TC0_H_15_TR/SCB7_MOSI (0)/SCB7_TX (0)/SCB7_SCL (0)/FAULT_OUT_1/ADC[0]_1

P1.0 PWM0_H_0/PWM0_H_15_N/TC0_H_14_TR/SCB7_CLK (0)/SCB7_RX (0)/SCB7_SDA (0)/FAULT_OUT_0/ADC[0]_0

XRES_L

VSSD

PWM0_4/PWM0_3_N/SG_TONE[0] (1)/SCB2_CLK (1)/SCB2_RX (1)/SCB2_SDA (1)/LCD_SEG_0/LCD_COM_0 P10.0

PWM0_5/PWM0_4_N/SG_AMPL[0] (1)/SCB2_MOSI (1)/SCB2_TX (1)/SCB2_SCL (1)/LCD_SEG_1/LCD_COM_1 P10.1

PWM0_6/PWM0_5_N/SG_MCK[0] (1)/SCB2_MISO (1)/SCB2_RTS (1)/LCD_SEG_2/LCD_COM_2 P10.2

PWM0_7/PWM0_6_N/SG_TONE[1] (1)/SCB2_SEL0 (1)/SCB2_CTS (1)/LCD_SEG_3/LCD_COM_3 P10.3

PWM0_8/PWM0_7_N/SG_AMPL[1] (1)/LCD_SEG_4/LCD_COM_4 P10.4

PWM0_9/PWM0_8_N/SG_MCK[1] (1)/SCB1_CLK (0)/SCB1_RX (0)/SCB1_SDA (0)/LCD_SEG_5/LCD_COM_5 P11.0

PWM0_10/PWM0_9_N/SCB1_MOSI (0)/SCB1_TX (0)/SCB1_SCL (0)/LCD_SEG_6/LCD_COM_6 P11.1

PWM0_H_0/PWM0_10_N/TDM_TX_MCK[0] (0)/TDM_RX_MCK[1] (0)/SCB1_MISO (0)/SCB1_RTS (0)/LCD_SEG_7/LCD_COM_7 P11.2

PWM0_H_1/PWM0_H_0_N/TDM_TX_SCK[0] (0)/TDM_RX_SCK[1] (0)/SCB1_SEL0 (0)/SCB1_CTS (0)/LCD_SEG_8/LCD_COM_8 P11.3

PWM0_H_2/PWM0_H_1_N/TC0_H_0_TR/TDM_TX_FSYNC[0] (0)/TDM_RX_FSYNC[1] (0)/SCB1_SEL1 (0)/LCD_SEG_9/LCD_COM_9 P11.4

PWM0_11/PWM0_H_2_N/TC0_H_1_TR/TDM_TX_SD[0] (0)/TDM_RX_SD[1] (0)/SG_TONE[2] (1)/LCD_SEG_12/LCD_COM_12 P11.5

PWM0_6/PWM0_11_N/SG_AMPL[2] (1)/LCD_SEG_13/LCD_COM_13 P11.6

PWM0_7/PWM0_6_N/SG_MCK[2] (1)/TRIG_IN[18]/LCD_SEG_14/LCD_COM_14 P11.7

PWM0_8/PWM0_7_N/TC0_H_2_TR/SG_TONE[0] (0)/SCB2_CLK (0)/SCB2_RX (0)/SCB2_SDA (0)/LCD_SEG_10/LCD_COM_10 P12.0

PWM0_9/PWM0_8_N/SG_AMPL[0] (0)/SCB2_MOSI (0)/SCB2_TX (0)/SCB2_SCL (0)/LCD_SEG_11/LCD_COM_11 P12.1

PWM0_10/PWM0_9_N/SG_MCK[0] (0)/SCB2_MISO (0)/SCB2_RTS (0)/LCD_SEG_15/LCD_COM_15 P12.2

PWM0_11/PWM0_10_N/TDM_TX_MCK[1] (0)/TDM_RX_MCK[0] (0)/SCB2_SEL0 (0)/SCB2_CTS (0)/LCD_SEG_16/LCD_COM_16 P12.3

PWM0_0/PWM0_11_N/TDM_TX_SCK[1] (0)/TDM_RX_SCK[0] (0)/SCB2_SEL1 (0)/LCD_SEG_17/LCD_COM_17 P12.4

PWM0_1/PWM0_0_N/TDM_TX_FSYNC[1] (0)/TDM_RX_FSYNC[0] (0)/LCD_SEG_18/LCD_COM_18 P12.5

PWM0_2/PWM0_1_N/TDM_TX_SD[1] (0)/TDM_RX_SD[0] (0)/LCD_SEG_19/LCD_COM_19 P12.6

PWM0_3/PWM0_2_N/TRIG_IN[19]/LCD_SEG_20/LCD_COM_20 P12.7

VSSD

176-LQFP

VSSD

VCCD

VDDD

P0.3 ECO_OUT

P0.2 EXT_CLK/ECO_IN

P0.1 WCO_OUT/LPECO_OUT

P0.0 WCO_IN/LPECO_IN

VSSD

98

P19.6 PWM0_23/PWM0_22_N/LCD_SEG_31/LCD_COM_31

97

P19.5 PWM0_22/PWM0_21_N/LCD_SEG_30/LCD_COM_30

96

P19.4 PWM0_21/PWM0_20_N/TC0_33_TR/SCB6_SEL1 (1)/LCD_SEG_33/LCD_COM_33

P19.3 PWM0_20/PWM0_19_N/TC0_32_TR/CAN1_0_RX/SCB6_SEL0 (1)/SCB6_CTS (1)/FAULT_OUT_3/LCD_SEG_32/LCD_COM_32

P19.2 PWM0_19/PWM0_18_N/TC0_31_TR/LIN0_EN/CXPI0_EN/CAN1_0_TX/SCB6_MISO (1)/SCB6_RTS (1)/FAULT_OUT_2/LCD_SEG_29/LCD_COM_29

P19.1 PWM0_18/PWM0_17_N/LIN0_RX/CXPI0_RX/CAN1_1_RX/SCB6_MOSI (1)/SCB6_TX (1)/SCB6_SCL (1)/FAULT_OUT_1/LCD_SEG_28/LCD_COM_28

P19.0 PWM0_17/PWM0_16_N/LIN0_TX/CXPI0_TX/CAN1_1_TX/SCB6_CLK (1)/SCB6_RX (1)/SCB6_SDA (1)/FAULT_OUT_0/LCD_SEG_25/LCD_COM_25

P18.7 PWM0_16/PWM0_15_N/TC0_23_TR/TRIG_IN[31]/LCD_SEG_27/LCD_COM_27

P18.6 PWM0_15/PWM0_14_N/TC0_22_TR/TRIG_IN[30]

95

94

93

92

91

90

89

VSSD

Figure 9-2

176-LQFP pin assignment with alternate functions

Datasheet

29

002-32508 Rev. *F

2022-10-20

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Pin assignment

VSSIO_HSIO

P8.0

1

108

107

106

105

104

103

102

101

100

99

VDDIO_GPIO

VSSA_ADC

VDDA_ADC

VREFH

P3.3

2

P8.1

3

P8.2

4

P8.3

5

VSSIO_HSIO

VDDIO_HSIO

P8.4

6

P3.2

7

P3.1

8

P3.0

P8.5

9

P2.7

P8.6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

P2.6

P8.7

98

P2.5

VSSIO_HSIO

VDDIO_HSIO

P9.0

97

P2.4

96

P2.3

95

P2.2

P9.1

94

P2.1

P9.2

93

P2.0

P9.3

92

P1.3

VDDIO_HSIO

VSSIO_HSIO

VDDD

91

P1.2

90

P1.1

144-LQFP

89

P1.0

VCCD

88

XRES_L

VSSD

VCCD

VDDD

P0.3

VSSD

87

P11.0

86

P11.1

85

P11.2

84

P11.3

83

P11.4

82

P0.2

P11.5

81

P0.1

P12.0

80

P0.0

P12.1

79

VSSD

P19.4

P19.3

P19.2

P19.1

P19.0

VSSD

P12.2

78

P12.3

77

P12.4

76

P12.5

75

P12.6

74

VSSD

73

Figure 9-3

144-LQFP pin assignment