XC228X [INFINEON]
16/32-Bit Single-Chip Microcontroller with 32-Bit Performance; 16位/ 32位单芯片微控制器与32位性能
| 型号： | XC228X |
| 厂家： | 
Infineon |
| 描述： | 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance |
| 文件： | 总110页 (文件大小：2339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V0.91, Feb. 2007
XC228x
16/32-Bit Single-Chip Microcontroller with
32-Bit Performance
Microcontrollers
Edition 2007-02
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-
infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V0.91, Feb. 2007
XC228x
16/32-Bit Single-Chip Microcontroller with
32-Bit Performance
Microcontrollers
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
XC228x
Revision History: V0.91, 2007-02
Previous Version(s):
V0.9, 2006-11, Preliminary
Page
82
Subjects (major changes since last revision)
Current value numbers added to diagram
Wrong decimal point removed from formula
81
70
Description for instruction PWRDN corrected
Standby RAM added to list
6
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . 60
MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 77
DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 79
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
5
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1
5.2
5.3
Data Sheet
3
V0.91, 2007-02
Draft Version
Preliminary
16/32-Bit Single-Chip Microcontroller with 32-Bit
Performance
XC228x
XC2000 Family
1
Summary of Features
For a quick overview or reference, the XC228x’s properties are listed here in a
condensed way.
•
High Performance 16-bit CPU with 5-Stage Pipeline
– 15 ns Instruction Cycle Time at 66 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle 32-bit Addition and Subtraction with 40-bit Result
– 1-Cycle Multiplication (16 × 16 bit)
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Background Division (32 / 16 bit) in 21 Cycles
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
16-Priority-Level Interrupt System with up to 87 Sources, Selectable External Inputs
for Interrupt Generation and Wake-Up, Sample-Rate down to 15 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
Clock Generation from Internal or External Clock Sources,
via on-chip PLL or via Prescaler
•
•
•
•
On-Chip Memory Modules
– 1 Kbyte On-Chip Stand-By RAM (SBRAM)
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 16 Kbytes On-Chip Data SRAM (DSRAM)
– Upt to 64 Kbytes On-Chip Program/Data SRAM (PSRAM)
– Up to 768 Kbytes On-Chip Program Memory (Flash Memory)
On-Chip Peripheral Modules
•
– Two Synchronizable A/D Converters with a total of 24 Channels, 10-bit Resolution,
Conversion Time down to 1.2 µs, Optional Data Preprocessing (Data Reduction,
Range Check)
– 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Up to four Capture/Compare Units for flexible PWM Signal Generation (CCU6x)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Six Serial Interface Channels to be used as UART, LIN, High-Speed Synchronous
Channel (SPI/QSPI), IIC Bus Interface (10-bit addressing, 400 kbit/s), IIS Interface
Data Sheet
4
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Summary of Features
– On-Chip MultiCAN Interface (Rev. 2.0B active) with 128 Message Objects
(Full CAN/Basic CAN) on up to 5 CAN Nodes and Gateway Functionality
– On-Chip Real Time Clock
•
Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
Single Power Supply from 3.0 V to 5.5 V
Power Reduction Modes with Flexible Power Management
Programmable Watchdog Timer and Oscillator Watchdog
Up to 118 General Purpose I/O Lines
•
•
•
•
•
•
On-Chip Bootstrap Loader
Supported by a Large Range of Development Tools like C-Compilers, Macro-
Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators,
Logic Analyzer Disassemblers, Programming Boards
On-Chip Debug Support via JTAG Interface
•
•
144-Pin Green LQFP Package, 0.5 mm (19.7 mil) pitch
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
the derivative itself, i.e. its function set, the temperature range, and the supply voltage
the package and the type of delivery.
For the available ordering codes for the XC228x please refer to your responsible sales
representative or your local distributor.
This document describes several derivatives of the XC228x group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC228x throughout this document.
Data Sheet
5
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Summary of Features
Table 1
XC228x Derivative Synopsis
Derivative1)
Temp.
Range
Program
Memory
PSRAM2) CCU6 ADC3) Interfaces
Mod. Chan.
SAK-XC2287-
96F66L
-40 °C to 768Kbytes 64 Kbytes 0, 1,
125 °C Flash 2, 3
-40 °C to 576Kbytes 32 Kbytes 0, 1,
125 °C Flash 2, 3
-40 °C to 448Kbytes 16 Kbytes 0, 1,
125 °C Flash 2, 3
-40 °C to 768Kbytes 64 Kbytes 0, 1
125 °C Flash
-40 °C to 576Kbytes 32 Kbytes 0, 1
125 °C Flash
-40 °C to 448Kbytes 16 Kbytes 0, 1
125 °C Flash
-40 °C to 768Kbytes 64 Kbytes 0, 1
125 °C Flash
-40 °C to 576Kbytes 32 Kbytes 0, 1
125 °C Flash
-40 °C to 448Kbytes 16 Kbytes 0, 1
125 °C Flash
16 + 8 5 CAN Nodes,
6 Serial Chan.
SAK-XC2287-
72F66L
16 + 8 5 CAN Nodes,
6 Serial Chan.
SAK-XC2287-
56F66L
16 + 8 5 CAN Nodes,
6 Serial Chan.
SAK-XC2286-
96F66L
16 + 8 3 CAN Nodes,
6 Serial Chan.
SAK-XC2286-
72F66L
16 + 8 3 CAN Nodes,
6 Serial Chan.
SAK-XC2286-
56F66L
16 + 8 3 CAN Nodes,
6 Serial Chan.
SAK-XC2285-
96F66L
12
12
12
2 CAN Nodes,
4 Serial Chan.
SAK-XC2285-
72F66L
2 CAN Nodes,
4 Serial Chan.
SAK-XC2285-
56F66L
2 CAN Nodes,
4 Serial Chan.
1) This Data Sheet is valid for devices starting with and including design step AA.
2) All derivatives additionally provide 1 Kbyte SBRAM, 2 Kbytes DPRAM, and 16 Kbytes DSRAM.
3) Analog input channels are listed for each Analog/Digital Converter module separately.
Data Sheet
6
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
2
General Device Information
The XC228x derivatives are high-performance members of the Infineon XC2000 Family
of full featured single-chip CMOS microcontrollers. These devices extend the
functionality and performance of the C166 Family in terms of instructions (MAC unit),
peripherals, and speed. They combine high CPU performance (up to 66 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities.
Optimized peripherals can be adapted to the application’s requirements in a flexible way.
These derivatives also provide clock generation via PLL and internal or external clock
sources, and various on-chip memory modules such as program Flash, program RAM,
and data RAM.
VAREFVAGND TRef VDDI VDDP VSS
(2) (1)
(4) (9) (4)
Port 0
8 bit
XTAL1
XTAL2
ESR0
ESR1
ESR2
Port 1
8 bit
Port 2
13 bit
Port 11
6 bit
Port 3
8 bit
XC228x
Port 10
16 bit
Port 4
8 bit
Port 9
8 bit
Port 6
4 bit
Port 15
8 bit
Port 7
5 bit
Port 5
16 bit
Port 8
7 bit
PORST TRST JTAG Debug
4 bit 2 bit
TESTM
via Port Pins
MC_XC2X_LOGSYMB3
Figure 1
Logic Symbol
Data Sheet
7
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
2.1
Pin Configuration and Definition
The pins of the XC228x are described in detail in Table 2, including all their alternate
functions. For explanations, please refer to the footnotes at the table’s end. Figure 2
summarizes all pins in a condensed way, showing their location on the 4 sides of the
package.
VSS
VDDPB
VDDPB
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
P3.7
P0.7
P10.7
P3.6
P10.6
P0.6
P3.5
P10.5
P3.4
P10.4
P3.3
P0.5
TESTM
P7.2
P8.4
TRST
P8.3
P7.0
P7.3
P8.2
P7.1
P7.4
P8.1
9
10
11
12
13
98
97
96
P8.0
VDDIM
14
15
95
94
P10.3
P2.10
P6.0
P6.1
P6.2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P3.2
TRef
VDDI1
P0.4
XC228x
P6.3
VDDPA
P10.2
P3.1
P15.0
P15.1
P15.2
P15.3
P15.4
P15.5
P15.6
P15.7
VAREF1
VAREF0
VAGND
P5.0
P0.3
P10.1
P3.0
P10.0
P0.2
P2.9
P4.7
P2.8
P0.1
P2.7
P4.6
P4.5
P0.0
VDDPB
VSS
P5.1
P5.2
P5.3
VDDPB
MC_XC2X_PIN144
Figure 2
Pin Configuration (top view)
Data Sheet
8
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Notes to Pin Definitions
1. Ctrl.: The output signal for a port pin is selected via bitfield PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
2. Type: Indicates the employed pad type (St=standard pad, Sp=special pad,
DP=double pad, In=input pad, PS=power supply) and its power supply domain (A, B,
M, 1).
Table 2
Pin Definitions and Functions
Ctrl. Type Function
Pin Symbol
3
TESTM
I
In/B Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
4
P7.2
O0 / I St/B Bit 2 of Port 7, General Purpose Input/Output
EMUX0
TxDC4
O1
O2
I
St/B External Analog MUX Control Output 0
St/B CAN Node 4 Transmit Data Output
St/B CCU62 Position Input 0
CCU62_
CCPOS0A
TDI_C
P8.4
I
St/B JTAG Test Data Input
5
6
O0 / I St/B Bit 4 of Port 8, General Purpose Input/Output
CCU60_
COUT61
O1
St/B CCU60 Channel 1 Output
TMS_D
TRST
I
I
St/B JTAG Test Mode Selection Input
In/B Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XC228x’s debug system.
In this case, pin TRST must be driven low once to
reset the debug system.
7
P8.3
O0 / I St/B Bit 3 of Port 8, General Purpose Input/Output
CCU60_
COUT60
O1
St/B CCU60 Channel 0 Output
TDI_D
I
St/B JTAG Test Data Input
Data Sheet
9
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
8
P7.0
O0 / I St/B Bit 0 of Port 7, General Purpose Input/Output
T3OUT
T6OUT
TDO
O1
O2
OH
I
St/B GPT1 Timer T3 Toggle Latch Output
St/B GPT2 Timer T6 Toggle Latch Output
St/B JTAG Test Data Output
RxDC4B
P7.3
St/B CAN Node 4 Receive Data Input
9
O0 / I St/B Bit 3 of Port 7, General Purpose Input/Output
EMUX1
O1
St/B External Analog MUX Control Output 1
St/B USIC0 Channel 1 Shift Data Output
St/B USIC0 Channel 0 Shift Data Output
St/B CCU62 Position Input 1
U0C1_DOUT O2
U0C0_DOUT O3
CCU62_
I
CCPOS1A
TMS_C
U0C1_DX0F
P8.2
I
I
St/B JTAG Test Mode Selection Input
St/B USIC0 Channel 1 Shift Data Input
10
11
O0 / I St/B Bit 2 of Port 8, General Purpose Input/Output
O1 / I St/B CCU60 Channel 2 Input/Output
CCU60_
CC62
P7.1
O0 / I St/B Bit 1 of Port 7, General Purpose Input/Output
EXTCLK
TxDC4
O1
O2
I
St/B Programmable Clock Signal Output
St/B CAN Node 4 Transmit Data Output
St/B CCU62 Emergency Trap Input
CCU62_
CTRAPA
BRKIN_C
P7.4
I
St/B OCDS Break Signal Input
12
O0 / I St/B Bit 4 of Port 7, General Purpose Input/Output
EMUX2
O1
St/B External Analog MUX Control Output 2
St/B USIC0 Channel 1 Shift Data Output
St/B USIC0 Channel 1 Shift Clock Output
St/B CCU62 Position Input 2
U0C1_DOUT O2
U0C1_SCLK O3
CCU62_
I
CCPOS2A
TCK_C
I
St/B JTAG Clock Input
U0C0_DX0D I
U0C1_DX1E
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 1 Shift Clock Input
I
Data Sheet
10
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
13
14
16
P8.1
O0 / I St/B Bit 1 of Port 8, General Purpose Input/Output
O1 / I St/B CCU60 Channel 1 Input/Output
CCU60_
CC61
P8.0
O0 / I St/B Bit 0 of Port 8, General Purpose Input/Output
O1 / I St/B CCU60 Channel 0 Input/Output
CCU60_
CC60
P6.0
O0 / I St/A Bit 0 of Port 6, General Purpose Input/Output
EMUX0
O1
St/A External Analog MUX Control Output 0
St/A USIC1 Channel 1 Shift Data Output
St/A OCDS Break Signal Output
U1C1_DOUT O2
BRKOUT
O3
I
ADCx_
St/A External Request Gate Input for ADC0/1
REQGTyC
U1C1_DX0E
P6.1
I
St/A USIC1 Channel 1 Shift Data Input
17
O0 / I St/A Bit 1 of Port 6, General Purpose Input/Output
EMUX1
T3OUT
O1
O2
St/A External Analog MUX Control Output 1
St/A GPT1 Timer T3 Toggle Latch Output
St/A USIC1 Channel 1 Shift Data Output
St/A External Request Trigger Input for ADC0/1
U1C1_DOUT O3
ADCx_
I
REQTRyC
18
19
P6.2
O0 / I St/A Bit 2 of Port 6, General Purpose Input/Output
EMUX2
T6OUT
O1
O2
St/A External Analog MUX Control Output 2
St/A GPT2 Timer T6 Toggle Latch Output
St/A USIC1 Channel 1 Shift Clock Output
St/A USIC1 Channel 1 Shift Clock Input
U1C1_SCLK O3
U1C1_DX1C I
P6.3
O0 / I St/A Bit 3 of Port 6, General Purpose Input/Output
T3OUT
O2
O3
St/A GPT1 Timer T3 Toggle Latch Output
U1C1_
SELO0
St/A USIC1 Channel 1 Select/Control 0 Output
U1C1_DX2D I
St/A USIC1 Channel 1 Shift Control Input
ADCx_
I
St/A External Request Trigger Input for ADC0/1
REQTRyD
Data Sheet
11
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
21
22
23
P15.0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
-
I
I
I
I
I
I
I
In/A Bit 0 of Port 15, General Purpose Input
In/A Analog Input Channel 0 for ADC1
ADC1_CH0
P15.1
In/A Bit 1 of Port 15, General Purpose Input
In/A Analog Input Channel 1 for ADC1
In/A Bit 2 of Port 15, General Purpose Input
In/A Analog Input Channel 2 for ADC1
In/A GPT2 Timer T5 Count/Gate Input
ADC1_CH1
P15.2
ADC1_CH2
T5IN
24
25
26
P15.3
In/A Bit 3 of Port 15, General Purpose Input
In/A Analog Input Channel 3 for ADC1
In/A GPT2 Timer T5 External Up/Down Control Input
In/A Bit 4 of Port 15, General Purpose Input
In/A Analog Input Channel 4 for ADC1
In/A GPT2 Timer T6 Count/Gate Input
ADC1_CH3
T5EUD
P15.4
ADC1_CH4
T6IN
P15.5
In/A Bit 5 of Port 15, General Purpose Input
In/A Analog Input Channel 5 for ADC1
In/A GPT2 Timer T6 External Up/Down Control Input
In/A Bit 6 of Port 15, General Purpose Input
In/A Analog Input Channel 6 for ADC1
In/A Bit 7 of Port 15, General Purpose Input
In/A Analog Input Channel 7 for ADC1
PS/A Reference Voltage for A/D Converter ADC1
PS/A Reference Voltage for A/D Converter ADC0
PS/A Reference Ground for A/D Converters ADC0/1
In/A Bit 0 of Port 5, General Purpose Input
In/A Analog Input Channel 0 for ADC0
In/A Bit 1 of Port 5, General Purpose Input
In/A Analog Input Channel 1 for ADC0
In/A Bit 2 of Port 5, General Purpose Input
In/A Analog Input Channel 2 for ADC0
In/A JTAG Test Data Input
ADC1_CH5
T6EUD
P15.6
27
28
ADC1_CH6
P15.7
ADC1_CH7
VAREF1
29
30
31
32
VAREF0
VAGND
P5.0
ADC0_CH0
P5.1
33
34
ADC0_CH1
P5.2
ADC0_CH2
TDI_A
Data Sheet
12
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
35
P5.3
I
I
I
I
I
I
In/A Bit 3 of Port 5, General Purpose Input
In/A Analog Input Channel 3 for ADC0
ADC0_CH3
T3IN
In/A GPT1 Timer T3 Count/Gate Input
39
P5.4
In/A Bit 4 of Port 5, General Purpose Input
In/A Analog Input Channel 4 for ADC0
In/A External Run Control Input for T12 of CCU63
ADC0_CH4
CCU63_
T12HRB
T3EUD
TMS_A
P5.5
I
I
I
I
I
In/A GPT1 Timer T3 External Up/Down Control Input
In/A JTAG Test Mode Selection Input
40
In/A Bit 5 of Port 5, General Purpose Input
In/A Analog Input Channel 5 for ADC0
ADC0_CH5
CCU60_
T12HRB
In/A External Run Control Input for T12 of CCU60
41
42
43
P5.6
I
I
I
I
I
I
I
In/A Bit 6 of Port 5, General Purpose Input
In/A Analog Input Channel 6 for ADC0
In/A Bit 7 of Port 5, General Purpose Input
In/A Analog Input Channel 7 for ADC0
In/A Bit 8 of Port 5, General Purpose Input
In/A Analog Input Channel 8 for ADC0
ADC0_CH6
P5.7
ADC0_CH7
P5.8
ADC0_CH8
CCU6x_
T12HRC
In/A External Run Control Input for T12 of
CCU60/1/2/3
CCU6x_
T13HRC
I
In/A External Run Control Input for T13 of
CCU60/1/2/3
44
45
46
P5.9
I
I
I
I
In/A Bit 9 of Port 5, General Purpose Input
In/A Analog Input Channel 9 for ADC0
In/A CAPCOM2 Timer T7 Count Input
In/A Bit 10 of Port 5, General Purpose Input
In/A Analog Input Channel 10 for ADC0
In/A OCDS Break Signal Input
ADC0_CH9
CC2_T7IN
P5.10
ADC0_CH10 I
BRKIN_A
P5.11
I
I
In/A Bit 11 of Port 5, General Purpose Input
In/A Analog Input Channel 11 for ADC0
ADC0_CH11 I
Data Sheet
13
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
47
P5.12
ADC0_CH12 I
P5.13
ADC0_CH13 I
I
In/A Bit 12 of Port 5, General Purpose Input
In/A Analog Input Channel 12 for ADC0
48
I
In/A Bit 13 of Port 5, General Purpose Input
In/A Analog Input Channel 13 for ADC0
EX0BINB
P5.14
I
I
In/A External Interrupt Trigger Input
49
50
51
In/A Bit 14 of Port 5, General Purpose Input
In/A Analog Input Channel 14 for ADC0
ADC0_CH14 I
P5.15
I
In/A Bit 15 of Port 5, General Purpose Input
In/A Analog Input Channel 15 for ADC0
ADC0_CH15 I
P2.12
O0 / I St/B Bit 12 of Port 2, General Purpose Input/Output
U0C0_
SELO4
O1
St/B USIC0 Channel 0 Select/Control 4 Output
St/B USIC0 Channel 1 Select/Control 3 Output
St/B External Bus Interface READY Input
U0C1_
SELO3
O2
I
READY
P2.11
52
O0 / I St/B Bit 11 of Port 2, General Purpose Input/Output
U0C0_
SELO2
O1
O2
OH
St/B USIC0 Channel 0 Select/Control 2 Output
U0C1_
SELO2
St/B USIC0 Channel 1 Select/Control 2 Output
BHE/WRH
St/B External Bus Interf. High-Byte Control Output
Can operate either as Byte High Enable (BHE) or
as Write strobe for High Byte (WRH).
53
55
P11.5
P2.0
O0 / I St/B Bit 5 of Port 11, General Purpose Input/Output
O0 / I St/B Bit 0 of Port 2, General Purpose Input/Output
O2 / I St/B CCU63 Channel 0 Input/Output
CCU63_
CC60
AD13
OH / I St/B External Bus Interface Address/Data Line 13
RxDC0C
I
St/B CAN Node 0 Receive Data Input
Data Sheet
14
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
56
P2.1
O0 / I St/B Bit 1 of Port 2, General Purpose Input/Output
O1 St/B CAN Node 0 Transmit Data Output
TxDC0
CCU63_
CC61
O2 / I St/B CCU63 Channel 1 Input/Output
AD14
OH / I St/B External Bus Interface Address/Data Line 14
EX0AINA
P11.4
I
St/B External Interrupt Trigger Input
57
58
O0 / I St/B Bit 4 of Port 11, General Purpose Input/Output
O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output
P2.2
TxDC1
O1
St/B CAN Node 1 Transmit Data Output
CCU63_
CC62
O2 / I St/B CCU63 Channel 2 Input/Output
AD15
EX1AINA
P11.3
P4.0
OH / I St/B External Bus Interface Address/Data Line 15
I
St/B External Interrupt Trigger Input
59
60
O0 / I St/B Bit 3 of Port 11, General Purpose Input/Output
O0 / I St/B Bit 0 of Port 4, General Purpose Input/Output
O3 / I St/B CAPCOM2 CC8IO Capture Inp./ Compare Out.
CC2_8
CS0
OH
St/B External Bus Interface Chip Select 0 Output
61
P2.3
O0 / I St/B Bit 3 of Port 2, General Purpose Input/Output
U0C0_DOUT O1
St/B USIC0 Channel 0 Shift Data Output
St/B CCU63 Channel 3 Output
CCU63_
COUT63
O2
CC2_0
O3 / I St/B CAPCOM2 CC0IO Capture Inp./ Compare Out.
A16
OH
I
St/B External Bus Interface Address Line 16
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 1 Shift Data Input
Note: Not available in step AA.
U0C0_DX0E
U0C1_DX0D I
RxDC0A
P11.2
I
St/B CAN Node 0 Receive Data Input
62
O0 / I St/B Bit 2 of Port 11, General Purpose Input/Output
CCU63_
I
St/B CCU63 Position Input 2
CCPOS2A
Data Sheet
15
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
63
P4.1
O0 / I St/B Bit 1 of Port 4, General Purpose Input/Output
O2 St/B CAN Node 2 Transmit Data Output
O3 / I St/B CAPCOM2 CC9IO Capture Inp./ Compare Out.
OH St/B External Bus Interface Chip Select 1 Output
O0 / I St/B Bit 4 of Port 2, General Purpose Input/Output
TxDC2
CC2_9
CS1
64
P2.4
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
Note: Not available in step AA.
TxDC0
CC2_1
A17
O2
St/B CAN Node 0 Transmit Data Output
O3 / I St/B CAPCOM2 CC1IO Capture Inp./ Compare Out.
OH
St/B External Bus Interface Address Line 17
St/B USIC0 Channel 0 Shift Data Input
St/B CAN Node 1 Receive Data Input
U0C0_DX0F
RxDC1A
P11.1
I
I
65
66
67
O0 / I St/B Bit 1 of Port 11, General Purpose Input/Output
St/B CCU63 Position Input 1
CCU63_
I
CCPOS1A
P11.0
O0 / I St/B Bit 0 of Port 11, General Purpose Input/Output
St/B CCU63 Position Input 0
CCU63_
CCPOS0A
I
P2.5
O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output
U0C0_
O1
St/B USIC0 Channel 0 Shift Clock Output
SCLKOUT
TxDC0
CC2_2
A18
O2
St/B CAN Node 0 Transmit Data Output
O3 / I St/B CAPCOM2 CC2IO Capture Inp./ Compare Out.
OH
I
St/B External Bus Interface Address Line 18
St/B USIC0 Channel 0 Shift Clock Input
U0C0_DX1D
P4.2
68
O0 / I St/B Bit 2 of Port 4, General Purpose Input/Output
O2 St/B CAN Node 2 Transmit Data Output
O3 / I St/B CAPCOM2 CC10IO Capture Inp./ Compare Out.
TxDC2
CC2_10
CS2
OH
I
St/B External Bus Interface Chip Select 2 Output
St/B GPT1 Timer T2 Count/Gate Input
T2IN
Data Sheet
16
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
69
P2.6
O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output
U0C0_
SELO0
O1
St/B USIC0 Channel 0 Select/Control 0 Output
U0C1_
SELO1
O2
St/B USIC0 Channel 1 Select/Control 1 Output
CC2_3
A19
O3 / I St/B CAPCOM2 CC3IO Capture Inp./ Compare Out.
OH
St/B External Bus Interface Address Line 19
St/B USIC0 Channel 0 Shift Control Input
St/B CAN Node 0 Receive Data Input
U0C0_DX2D I
RxDC0D
P4.4
I
70
71
O0 / I St/B Bit 4 of Port 4, General Purpose Input/Output
O3 / I St/B CAPCOM2 CC12IO Capture Inp./ Compare Out.
CC2_12
CS4
OH
I
St/B External Bus Interface Chip Select 4 Output
St/B RTC Count Clock Signal Input
DRTC
P4.3
O0 / I St/B Bit 3 of Port 4, General Purpose Input/Output
O3 / I St/B CAPCOM2 CC11IO Capture Inp./ Compare Out.
CC2_11
CS3
OH
St/B External Bus Interface Chip Select 3 Output
St/B CAN Node 2 Receive Data Input
RxDC2A
T2EUD
P0.0
I
I
St/B GPT1 Timer T2 External Up/Down Control Input
75
O0 / I St/B Bit 0 of Port 0, General Purpose Input/Output
St/B USIC1 Channel 0 Shift Data Output
O3 / I St/B CCU61 Channel 0 Input/Output
U1C0_DOUT O1
CCU61_
CC60
A0
OH
I
St/B External Bus Interface Address Line 0
St/B USIC1 Channel 0 Shift Data Input
U1C0_DX0A
P4.5
76
77
O0 / I St/B Bit 5 of Port 4, General Purpose Input/Output
O3 / I St/B CAPCOM2 CC13IO Capture Inp./Compare Out.
O0 / I St/B Bit 6 of Port 4, General Purpose Input/Output
O3 / I St/B CAPCOM2 CC14IO Capture Inp./ Compare Out.
CC2_13
P4.6
CC2_14
T4IN
I
St/B GPT1 Timer T4 Count/Gate Input
Data Sheet
17
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
78
P2.7
O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output
U0C1_
SELO0
O1
St/B USIC0 Channel 1 Select/Control 0 Output
U0C0_
SELO1
O2
St/B USIC0 Channel 0 Select/Control 1 Output
CC2_4
A20
O3 / I St/B CAPCOM2 CC4IO Capture Inp./ Compare Out.
OH
St/B External Bus Interface Address Line 20
St/B USIC0 Channel 1 Shift Control Input
St/B CAN Node 1 Receive Data Input
U0C1_DX2C I
RxDC1C
P0.1
I
79
O0 / I St/B Bit 1 of Port 0, General Purpose Input/Output
U1C0_DOUT O1
St/B USIC1 Channel 0 Shift Data Output
St/B CAN Node 0 Transmit Data Output
TxDC0
O2
CCU61_
CC61
O3 / I St/B CCU61 Channel 1 Input/Output
A1
OH
St/B External Bus Interface Address Line 1
St/B USIC1 Channel 0 Shift Data Input
St/B USIC1 Channel 0 Shift Clock Input
U1C0_DX0B
U1C0_DX1A
P2.8
I
I
80
O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output
U0C1_
O1
DP/B USIC0 Channel 1 Shift Clock Output
SCLKOUT
EXTCLK
O2
DP/B Programmable Clock Signal Output
1)
CC2_5
A21
O3 / I DP/B CAPCOM2 CC5IO Capture Inp./ Compare Out.
OH
DP/B External Bus Interface Address Line 21
DP/B USIC0 Channel 1 Shift Clock Input
U0C1_DX1D I
P4.7
81
O0 / I St/B Bit 7 of Port 4, General Purpose Input/Output
O3 / I St/B CAPCOM2 CC15IO Capture Inp./ Compare Out.
CC2_15
T4EUD
I
St/B GPT1 Timer T4 External Up/Down Control Input
Data Sheet
18
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
82
P2.9
O0 / I St/B Bit 9 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
St/B CAN Node 1 Transmit Data Output
TxDC1
CC2_6
A22
O2
O3 / I St/B CAPCOM2 CC6IO Capture Inp./ Compare Out.
OH
St/B External Bus Interface Address Line 22
St/B Clock Signal Input
DIRIN
TCK_A
P0.2
I
I
St/B JTAG Clock Input
83
O0 / I St/B Bit 2 of Port 0, General Purpose Input/Output
U1C0_
O1
St/B USIC1 Channel 0 Shift Clock Output
SCLKOUT
TxDC0
O2
St/B CAN Node 0 Transmit Data Output
CCU61_
CC62
O3 / I St/B CCU61 Channel 2 Input/Output
A2
OH
I
St/B External Bus Interface Address Line 2
St/B USIC1 Channel 0 Shift Clock Input
U1C0_DX1B
P10.0
84
O0 / I St/B Bit 0 of Port 10, General Purpose Input/Output
St/B USIC0 Channel 1 Shift Data Output
U0C1_DOUT O1
CCU60_
CC60
O2 / I St/B CCU60 Channel 0 Input/Output
AD0
OH / I St/B External Bus Interface Address/Data Line 0
U0C0_DX0A
U0C1_DX0A
P3.0
I
I
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 1 Shift Data Input
85
O0 / I St/B Bit 0 of Port 3, General Purpose Input/Output
U2C0_DOUT O1
St/B USIC2 Channel 0 Shift Data Output
St/B External Bus Request Output
St/B USIC2 Channel 0 Shift Data Input
St/B CAN Node 3 Receive Data Input
St/B USIC2 Channel 0 Shift Clock Input
BREQ
OH
U2C0_DX0A
RxDC3B
I
I
I
U2C0_DX1A
Data Sheet
19
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
86
P10.1
O0 / I St/B Bit 1 of Port 10, General Purpose Input/Output
St/B USIC0 Channel 0 Shift Data Output
U0C0_DOUT O1
CCU60_
CC61
O2 / I St/B CCU60 Channel 1 Input/Output
AD1
OH / I St/B External Bus Interface Address/Data Line 1
U0C0_DX0B
U0C0_DX1A
P0.3
I
I
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 0 Shift Clock Input
87
O0 / I St/B Bit 3 of Port 0, General Purpose Input/Output
U1C0_
SELO0
O1
O2
O3
St/B USIC1 Channel 0 Select/Control 0 Output
St/B USIC1 Channel 1 Select/Control 1 Output
St/B CCU61 Channel 0 Output
U1C1_
SELO1
CCU61_
COUT60
A3
OH
St/B External Bus Interface Address Line 3
St/B USIC1 Channel 0 Shift Control Input
St/B CAN Node 0 Receive Data Input
U1C0_DX2A
RxDC0B
P3.1
I
I
88
89
O0 / I St/B Bit 1 of Port 3, General Purpose Input/Output
U2C0_DOUT O1
St/B USIC2 Channel 0 Shift Data Output
St/B CAN Node 3 Transmit Data Output
TxDC3
HLDA
O2
OH / I St/B External Bus Hold Acknowledge Output/Input
Output in master mode, input in slave mode.
U2C0_DX0B
P10.2
I
St/B USIC2 Channel 0 Shift Data Input
O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output
O1 St/B USIC0 Channel 0 Shift Clock Output
U0C0_
SCLKOUT
CCU60_
CC62
O2 / I St/B CCU60 Channel 2 Input/Output
AD2
OH / I St/B External Bus Interface Address/Data Line 2
U0C0_DX1B
I
St/B USIC0 Channel 0 Shift Clock Input
Data Sheet
20
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
90
P0.4
O0 / I St/B Bit 4 of Port 0, General Purpose Input/Output
U1C1_
SELO0
O1
O2
O3
St/B USIC1 Channel 1 Select/Control 0 Output
St/B USIC1 Channel 0 Select/Control 1 Output
St/B CCU61 Channel 1 Output
U1C0_
SELO1
CCU61_
COUT61
A4
OH
St/B External Bus Interface Address Line 4
St/B USIC1 Channel 1 Shift Control Input
St/B CAN Node 1 Receive Data Input
U1C1_DX2A
RxDC1B
TRef
I
I
92
93
IO
Sp/1 Control Pin for Core Voltage Generation
Connect TRef to VDDPB to use the on-chip EVRs.
Connect TRef to VDDI1 for external core voltage
supply (on-chip EVRs off).
P3.2
O0 / I St/B Bit 2 of Port 3, General Purpose Input/Output
U2C0_
O1
St/B USIC2 Channel 0 Shift Clock Output
SCLKOUT
TxDC3
O2
St/B CAN Node 3 Transmit Data Output
St/B USIC2 Channel 0 Shift Clock Input
St/B External Bus Master Hold Request Input
U2C0_DX1B
HOLD
I
I
94
P2.10
O0 / I St/B Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
U0C0_
SELO3
O2
St/B USIC0 Channel 0 Select/Control 3 Output
CC2_7
A23
O3 / I St/B CAPCOM2 CC7IO Capture Inp./ Compare Out.
OH
St/B External Bus Interface Address Line 23
St/B USIC0 Channel 1 Shift Data Input
St/B GPT2 Register CAPREL Capture Input
U0C1_DX0E
CAPIN
I
I
Data Sheet
21
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
95
P10.3
O0 / I St/B Bit 3 of Port 10, General Purpose Input/Output
O2 St/B CCU60 Channel 0 Output
CCU60_
COUT60
AD3
OH / I St/B External Bus Interface Address/Data Line 3
U0C0_DX2A
U0C1_DX2A
P0.5
I
I
St/B USIC0 Channel 0 Shift Control Input
St/B USIC0 Channel 1 Shift Control Input
96
O0 / I St/B Bit 5 of Port 0, General Purpose Input/Output
U1C1_
SCLKOUT
O1
O2
O3
St/B USIC1 Channel 1 Shift Clock Output
St/B USIC1 Channel 0 Select/Control 2 Output
St/B CCU61 Channel 2 Output
U1C0_
SELO2
CCU61_
COUT62
A5
OH
I
St/B External Bus Interface Address Line 5
St/B USIC1 Channel 1 Shift Clock Input
U1C1_DX1A
U1C0_DX1C I
P3.3
St/B USIC1 Channel 0 Shift Clock Input
97
O0 / I St/B Bit 3 of Port 3, General Purpose Input/Output
U2C0_
SELO0
O1
St/B USIC2 Channel 0 Select/Control 0 Output
U2C1_
SELO1
O2
St/B USIC2 Channel 1 Select/Control 1 Output
U2C0_DX2A
RxDC3A
P10.4
I
I
St/B USIC2 Channel 0 Shift Control Input
St/B CAN Node 3 Receive Data Input
98
O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output
U0C0_
SELO3
O1
St/B USIC0 Channel 0 Select/Control 3 Output
CCU60_
COUT61
O2
St/B CCU60 Channel 1 Output
AD4
OH / I St/B External Bus Interface Address/Data Line 4
U0C0_DX2B
U0C1_DX2B
I
I
St/B USIC0 Channel 0 Shift Control Input
St/B USIC0 Channel 1 Shift Control Input
Data Sheet
22
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
99
P3.4
O0 / I St/B Bit 4 of Port 3, General Purpose Input/Output
U2C1_
SELO0
O1
O2
O3
St/B USIC2 Channel 1 Select/Control 0 Output
St/B USIC2 Channel 0 Select/Control 1 Output
St/B USIC0 Channel 0 Select/Control 4 Output
U2C0_
SELO1
U0C0_
SELO4
U2C1_DX2A
RxDC4A
I
I
St/B USIC2 Channel 1 Shift Control Input
St/B CAN Node 4 Receive Data Input
100 P10.5
U0C1_
O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output
O1
St/B USIC0 Channel 1 Shift Clock Output
SCLKOUT
CCU60_
COUT62
O2
St/B CCU60 Channel 2 Output
AD5
OH / I St/B External Bus Interface Address/Data Line 5
St/B USIC0 Channel 1 Shift Clock Input
O0 / I St/B Bit 5 of Port 3, General Purpose Input/Output
U0C1_DX1B
I
101 P3.5
U2C1_
SCLKOUT
O1
O2
O3
I
St/B USIC2 Channel 1 Shift Clock Output
St/B USIC2 Channel 0 Select/Control 2 Output
St/B USIC0 Channel 0 Select/Control 5 Output
St/B USIC2 Channel 1 Shift Clock Input
U2C0_
SELO2
U0C0_
SELO5
U2C1_DX1A
Data Sheet
23
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
102 P0.6
Ctrl. Type Function
O0 / I St/B Bit 6 of Port 0, General Purpose Input/Output
U1C1_DOUT O1
St/B USIC1 Channel 1 Shift Data Output
St/B CAN Node 1 Transmit Data Output
St/B CCU61 Channel 3 Output
TxDC1
O2
O3
CCU61_
COUT63
A6
OH
St/B External Bus Interface Address Line 6
St/B USIC1 Channel 1 Shift Data Input
St/B CCU61 Emergency Trap Input
U1C1_DX0A
I
I
CCU61_
CTRAPA
U1C1_DX1B
I
St/B USIC1 Channel 1 Shift Clock Input
103 P10.6
O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B USIC0 Channel 0 Shift Data Output
St/B CAN Node 4 Transmit Data Output
St/B USIC1 Channel 0 Select/Control 0 Output
TxDC4
O2
O3
U1C0_
SELO0
AD6
OH / I St/B External Bus Interface Address/Data Line 6
St/B USIC0 Channel 0 Shift Data Input
U0C0_DX0C I
U1C0_DX2D I
St/B USIC1 Channel 0 Shift Control Input
CCU60_
CTRAPA
I
St/B CCU60 Emergency Trap Input
104 P3.6
O0 / I St/B Bit 6 of Port 3, General Purpose Input/Output
U2C1_DOUT O1
St/B USIC2 Channel 1 Shift Data Output
St/B CAN Node 4 Transmit Data Output
St/B USIC0 Channel 0 Select/Control 6 Output
TxDC4
O2
O3
U0C0_
SELO6
U2C1_DX0A
U2C1_DX1B
I
I
St/B USIC2 Channel 1 Shift Data Input
St/B USIC2 Channel 1 Shift Clock Input
Data Sheet
24
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
105 P10.7
Ctrl. Type Function
O0 / I St/B Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
St/B CCU60 Channel 3 Output
CCU60_
COUT63
O2
AD7
OH / I St/B External Bus Interface Address/Data Line 7
U0C1_DX0B
I
I
St/B USIC0 Channel 1 Shift Data Input
St/B CCU60 Position Input 0
CCU60_
CCPOS0A
RxDC4C
I
St/B CAN Node 4 Receive Data Input
106 P0.7
O0 / I St/B Bit 7 of Port 0, General Purpose Input/Output
U1C1_DOUT O1
St/B USIC1 Channel 1 Shift Data Output
U1C0_
SELO3
O2
St/B USIC1 Channel 0 Select/Control 3 Output
A7
OH
St/B External Bus Interface Address Line 7
St/B USIC1 Channel 1 Shift Data Input
St/B CCU61 Emergency Trap Input
U1C1_DX0B
I
I
CCU61_
CTRAPB
107 P3.7
O0 / I St/B Bit 7 of Port 3, General Purpose Input/Output
U2C1_DOUT O1
St/B USIC2 Channel 1 Shift Data Output
U2C0_
SELO3
O2
O3
I
St/B USIC2 Channel 0 Select/Control 3 Output
U0C0_
SELO7
St/B USIC0 Channel 0 Select/Control 7 Output
U2C1_DX0B
St/B USIC2 Channel 1 Shift Data Input
111 P1.0
O0 / I St/B Bit 0 of Port 1, General Purpose Input/Output
U1C0_
O1
St/B USIC1 Channel 0 Master Clock Output
MCLKOUT
U1C0_
SELO4
O2
St/B USIC1 Channel 0 Select/Control 4 Output
A8
OH
St/B External Bus Interface Address Line 8
St/B External Interrupt Trigger Input
St/B CCU62 Emergency Trap Input
EX0BINA
I
I
CCU62_
CTRAPB
Data Sheet
25
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
112 P9.0
Ctrl. Type Function
O0 / I St/B Bit 0 of Port 9, General Purpose Input/Output
O1 / I St/B CCU63 Channel 0 Input/Output
CCU63_
CC60
113 P10.8
O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output
U0C0_
O1
St/B USIC0 Channel 0 Master Clock Output
MCLKOUT
U0C1_
SELO0
O2
St/B USIC0 Channel 1 Select/Control 0 Output
AD8
OH / I St/B External Bus Interface Address/Data Line 8
CCU60_
I
St/B CCU60 Position Input 1
CCPOS1A
U0C0_DX1C I
BRKIN_B
114 P9.1
St/B USIC0 Channel 0 Shift Clock Input
St/B OCDS Break Signal Input
I
O0 / I St/B Bit 1 of Port 9, General Purpose Input/Output
O1 / I St/B CCU63 Channel 1 Input/Output
CCU63_
CC61
115 P10.9
O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output
U0C0_
SELO4
O1
St/B USIC0 Channel 0 Select/Control 4 Output
U0C1_
O2
St/B USIC0 Channel 1 Master Clock Output
MCLKOUT
AD9
OH / I St/B External Bus Interface Address/Data Line 9
CCU60_
I
St/B CCU60 Position Input 2
CCPOS2A
TCK_B
I
St/B JTAG Clock Input
Data Sheet
26
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
116 P1.1
Ctrl. Type Function
O0 / I St/B Bit 1 of Port 1, General Purpose Input/Output
CCU62_
COUT62
O1
St/B CCU62 Channel 2 Output
U1C0_
SELO5
O2
St/B USIC1 Channel 0 Select/Control 5 Output
U2C1_DOUT O3
St/B USIC2 Channel 1 Shift Data Output
St/B External Bus Interface Address Line 9
St/B External Interrupt Trigger Input
A9
OH
I
EX1BINA
U2C1_DX0C I
117 P10.10
St/B USIC2 Channel 1 Shift Data Input
O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output
U0C0_
SELO0
O1
St/B USIC0 Channel 0 Select/Control 0 Output
CCU60_
COUT63
O2
St/B CCU60 Channel 3 Output
AD10
OH / I St/B External Bus Interface Address/Data Line 10
St/B USIC0 Channel 0 Shift Control Input
U0C0_DX2C I
TDI_B
I
St/B JTAG Test Data Input
U0C1_DX1A
I
St/B USIC0 Channel 1 Shift Clock Input
118 P10.11
O0 / I St/B Bit 11 of Port 10, General Purpose Input/Output
U1C0_
O1
St/B USIC1 Channel 0 Shift Clock Output
SCLKOUT
BRKOUT
O2
St/B OCDS Break Signal Output
AD11
OH / I St/B External Bus Interface Address/Data Line 11
St/B USIC1 Channel 0 Shift Clock Input
U1C0_DX1D I
RxDC2B
TMS_B
I
St/B CAN Node 2 Receive Data Input
St/B JTAG Test Mode Selection Input
I
119 P9.2
O0 / I St/B Bit 2 of Port 9, General Purpose Input/Output
O1 / I St/B CCU63 Channel 2 Input/Output
CCU63_
CC62
Data Sheet
27
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
120 P1.2
Ctrl. Type Function
O0 / I St/B Bit 2 of Port 1, General Purpose Input/Output
O1 / I St/B CCU62 Channel 2 Input/Output
CCU62_
CC62
U1C0_
SELO6
O2
O3
St/B USIC1 Channel 0 Select/Control 6 Output
St/B USIC2 Channel 1 Shift Clock Output
U2C1_
SCLKOUT
A10
OH
I
St/B External Bus Interface Address Line 10
CCU61_
T12HRB
St/B External Run Control Input for T12 of CCU61
EX2AINA
I
St/B External Interrupt Trigger Input
St/B USIC2 Channel 1 Shift Data Input
U2C1_DX0D I
U2C1_DX1C I
121 P10.12
U1C0_DOUT O1
St/B USIC2 Channel 1 Shift Clock Input
O0 / I St/B Bit 12 of Port 10, General Purpose Input/Output
St/B USIC1 Channel 0 Shift Data Output
St/B CAN Node 2 Transmit Data Output
St/B JTAG Test Data Output
TxDC2
O2
O3
TDO
AD12
OH / I St/B External Bus Interface Address/Data Line 12
St/B USIC1 Channel 0 Shift Data Input
U1C0_DX0C I
U1C0_DX1E
122 P9.3
I
St/B USIC1 Channel 0 Shift Clock Input
O0 / I St/B Bit 3 of Port 9, General Purpose Input/Output
CCU63_
COUT60
O1
St/B CCU63 Channel 0 Output
BRKOUT
O2
St/B OCDS Break Signal Output
Data Sheet
28
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
123 P10.13
Ctrl. Type Function
O0 / I St/B Bit 13 of Port 10, General Purpose Input/Output
U1C0_DOUT O1
St/B USIC1 Channel 0 Shift Data Output
St/B CAN Node 3 Transmit Data Output
St/B USIC1 Channel 0 Select/Control 3 Output
TxDC3
O2
O3
U1C0_
SELO3
WR/WRL
OH
St/B External Bus Interface Write Strobe Output
Active for each external write access, when WR,
active for ext. writes to the low byte, when WRL.
U1C0_DX0D I
124 P1.3
CCU62_
St/B USIC1 Channel 0 Shift Data Input
O0 / I St/B Bit 3 of Port 1, General Purpose Input/Output
O1
O2
O3
St/B CCU62 Channel 3 Output
COUT63
U1C0_
SELO7
St/B USIC1 Channel 0 Select/Control 7 Output
St/B USIC2 Channel 0 Select/Control 4 Output
U2C0_
SELO4
A11
OH
I
St/B External Bus Interface Address Line 11
CCU62_
T12HRB
St/B External Run Control Input for T12 of CCU62
EX3AINA
I
St/B External Interrupt Trigger Input
125 P9.4
O0 / I St/B Bit 4 of Port 9, General Purpose Input/Output
CCU63_
COUT61
O1
St/B CCU63 Channel 1 Output
U2C0_DOUT O2
126 P9.5
CCU63_
COUT62
U2C0_DOUT O2
St/B USIC2 Channel 0 Shift Data Output
O0 / I St/B Bit 5 of Port 9, General Purpose Input/Output
O1
St/B CCU63 Channel 2 Output
St/B USIC2 Channel 0 Shift Data Output
St/B USIC2 Channel 0 Shift Data Input
St/B CCU60 Position Input 2
U2C0_DX0E
I
I
CCU60_
CCPOS2B
Data Sheet
29
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
128 P10.14
Ctrl. Type Function
O0 / I St/B Bit 14 of Port 10, General Purpose Input/Output
U1C0_
SELO1
O1
St/B USIC1 Channel 0 Select/Control 1 Output
U0C1_DOUT O2
RD OH
U0C1_DX0C I
RxDC3C
129 P1.4
St/B USIC0 Channel 1 Shift Data Output
St/B External Bus Interface Read Strobe Output
St/B USIC0 Channel 1 Shift Data Input
St/B CAN Node 3 Receive Data Input
I
O0 / I St/B Bit 4 of Port 1, General Purpose Input/Output
CCU62_
COUT61
O1
O2
O3
St/B CCU62 Channel 1 Output
U1C1_
SELO4
St/B USIC1 Channel 1 Select/Control 4 Output
St/B USIC2 Channel 0 Select/Control 5 Output
U2C0_
SELO5
A12
OH
I
St/B External Bus Interface Address Line 12
St/B USIC2 Channel 0 Shift Control Input
U2C0_DX2B
130 P10.15
O0 / I St/B Bit 15 of Port 10, General Purpose Input/Output
U1C0_
SELO2
O1
St/B USIC1 Channel 0 Select/Control 2 Output
U0C1_DOUT O2
U1C0_DOUT O3
St/B USIC0 Channel 1 Shift Data Output
St/B USIC1 Channel 0 Shift Data Output
ALE
U0C1_DX1C I
131 P1.5
OH
St/B External Bus Interf. Addr. Latch Enable Output
St/B USIC0 Channel 1 Shift Clock Input
O0 / I St/B Bit 5 of Port 1, General Purpose Input/Output
CCU62_
COUT60
O1
St/B CCU62 Channel 0 Output
U1C1_
SELO3
O2
St/B USIC1 Channel 1 Select/Control 3 Output
BRKOUT
A13
O3
St/B OCDS Break Signal Output
OH
St/B External Bus Interface Address Line 13
St/B USIC2 Channel 0 Shift Data Input
U2C0_DX0C I
Data Sheet
30
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
132 P9.6
Ctrl. Type Function
O0 / I St/B Bit 6 of Port 9, General Purpose Input/Output
CCU63_
COUT63
O1
St/B CCU63 Channel 3 Output
St/B CCU63 Channel 2 Output
St/B CCU63 Emergency Trap Input
St/B CCU60 Position Input 1
CCU63_
COUT62
O2
CCU63 _
CTRAPA
I
I
CCU60_
CCPOS1B
133 P1.6
O0 / I St/B Bit 6 of Port 1, General Purpose Input/Output
O1 / I St/B CCU62 Channel 1 Input/Output
CCU62_
CC61
U1C1_
SELO2
O2
St/B USIC1 Channel 1 Select/Control 2 Output
U2C0_DOUT O3
A14 OH
U2C0_DX0D I
134 P9.7
St/B USIC2 Channel 0 Shift Data Output
St/B External Bus Interface Address Line 14
St/B USIC2 Channel 0 Shift Data Input
O0 / I St/B Bit 7 of Port 9, General Purpose Input/Output
CCU63_
CTRAPB
I
St/B CCU63 Emergency Trap Input
U2C0_DX1D I
St/B USIC2 Channel 0 Shift Clock Input
St/B CCU60 Position Input 0
CCU60_
I
CCPOS0B
135 P1.7
O0 / I St/B Bit 7 of Port 1, General Purpose Input/Output
O1 / I St/B CCU62 Channel 0 Input/Output
CCU62_
CC60
U1C1_
MCLKOUT
O2
O3
OH
St/B USIC1 Channel 1 Master Clock Output
St/B USIC2 Channel 0 Shift Clock Output
U2C0_
SCLKOUT
A15
St/B External Bus Interface Address Line 15
St/B USIC2 Channel 0 Shift Clock Input
Sp/1 Crystal Oscillator Amplifier Output
U2C0_DX1C I
136 XTAL2
O
Data Sheet
31
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
137 XTAL1
Ctrl. Type Function
I
Sp/1 Crystal Oscillator Amplifier Input
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDI1
.
138 PORST
I
In/B Power On Reset Input
A low level at this pin resets the XC228x
completely. A spike filter suppresses input pulses
<10 ns. Input pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition
should be 120 ns.
139 ESR1
EX0AINB
O0 / I St/B External Service Request 1
St/B External Interrupt Trigger Input
O0 / I St/B External Service Request 2
St/B External Interrupt Trigger Input
O0 / I St/B External Service Request 0
Note: After power-up, ESR0 operates as open-
I
140 ESR2
EX1AINB
I
141 ESR0
drain bidirectional reset with a weak pull-up.
142 P8.6
O0 / I St/B Bit 6 of Port 8, General Purpose Input/Output
CCU60_
COUT63
O1
St/B CCU60 Channel 3 Output
St/B CCU60 Emergency Trap Input
St/B OCDS Break Signal Input
CCU60_
CTRAPB
I
BRKIN_D
I
143 P8.5
O0 / I St/B Bit 5 of Port 8, General Purpose Input/Output
CCU60_
COUT62
O1
St/B CCU60 Channel 2 Output
TCK_D
I
St/B JTAG Clock Input
15
VDDIM
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a 680 nF ceramic capacitor.
54, VDDI1
91,
127
-
PS/1 Digital Core Supply Voltage for Domain 1
Decouple each with a 220 nF ceramic capacitor.
All VDDI1 pins must be connected to each other.
Data Sheet
32
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
20
VDDPA
-
PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent
V
DDP/VSS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6, and
P15 are fed from supply voltage VDDPA
.
2,
VDDPB
-
PS/B Digital Pad Supply Voltage for Domain B
36,
38,
72,
74,
108,
110,
144
Connect decoupling capacitors to adjacent
V
DDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6, and P15 are fed from supply
voltage VDDPB
.
1,
VSS
-
PS/-- Digital Ground
37,
73,
109
All VSS pins must be connected to the ground-line
or ground-plane.
1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
Data Sheet
33
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3
Functional Description
The architecture of the XC228x combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3). This bus structure enhances the overall system performance
by enabling the concurrent operation of several subsystems of the XC228x.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC228x.
PSRAM
16/32/64 Kbytes
DPRAM
2 Kbytes
DSRAM
16 Kbytes
OCDS
Debug Support
Program Flash 0
256 Kbytes
EBC
LXBus Control
External Bus
Control
CPU
Program Flash 1
192/256 Kbytes
C166SV2 - Core
Program Flash 2
0/64/256 Kbytes
WDT
RTC
Oscillators/PLL, System Fct.
Clock, Reset, Power Control,
Stand-By RAM
Interrupt & PEC
Interrupt Bus
CCU63 ...
ADC1 ADC0 GPT
CC2
CCU60
USIC2 USIC1 USIC0 Multi
2 Ch., 2 Ch., 2 Ch., CAN
64 x 64 x 64 x
8-Bit/
10-Bit 10-Bit
8 Ch. 16 Ch.
8-Bit/
T2
T7
T8
T12
T13
T12
T13
T3
T4
Buffer Buffer Buffer
RS232, RS232, RS232,
LIN,
SPI,
LIN,
SPI,
LIN,
SPI,
T5
2/5ch.
T6
IIC, IIS IIC, IIS IIC, IIS
P15
Port 5
16
P11
P10
16
P9
P8 P7 P6 P4
P3
P2
P1
8
P0
8
6
8
7
5
4
8
8
13
8
MC_XC2X_BLOCKDIAGRAM
Figure 3
Block Diagram
Data Sheet
34
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC228x is configured in a von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space.
Table 3
XC228x Memory Map
Address Area
Start Loc. End Loc. Area Size1)
Notes
IMB register space
FF’FF00H FF’FFFFH 256 Bytes
–
Reserved (Access trap) F0’0000H
Reserved for EPSRAM E9’0000H
FF’FEFFH <1 Mbyte
EF’FFFFH 448 Kbytes
E8’FFFFH 64 Kbytes
E7’FFFFH 448 Kbytes
E0’FFFFH 64 Kbytes
Minus IMB reg.
Mirrors EPSRAM
Flash timing
Mirrors PSRAM
Maximum speed
Emulated PSRAM
Reserved for PSRAM
Program SRAM
E8’0000H
E1’0000H
E0’0000H
Reserved for pr. mem. CC’0000H DF’FFFFH <1.25 Mbytes –
Program Flash 2
Program Flash 1
Program Flash 0
C8’0000H CB’FFFFH 256 Kbytes
C4’0000H C7’FFFFH 256 Kbytes
C0’0000H C3’FFFFH 256 Kbytes
–
–
2)
External memory area 40’0000H
Available Ext. IO area3) 20’5800H
BF’FFFFH 8 Mbytes
3F’FFFFH < 2 Mbytes
–
Minus USIC/CAN
USIC registers
20’4000H
20’0000H
20’57FFH
6 Kbytes
Accessed via EBC
MultiCAN registers
20’3FFFH 16 Kbytes
1F’FFFFH < 2 Mbytes
Accessed via EBC
External memory area 01’0000H
Minus segment 0
SFR area
00’FE00H 00’FFFFH 0.5 Kbyte
–
–
–
–
–
–
–
–
Dual-Port RAM
Reserved for DPRAM
ESFR area
00’F600H
00’F200H
00’F000H
00’E000H
00’A000H
00’8000H
00’FDFFH 2 Kbytes
00’F5FFH 1 Kbyte
00’F1FFH 0.5 Kbyte
00’EFFFH 4 Kbytes
00’DFFFH 16 Kbytes
00’9FFFH 8 Kbytes
00’7FFFH 32 Kbytes
XSFR area
Data SRAM
Reserved for DSRAM
External memory area 00’0000H
1) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
2) One 4-Kbyte sector reserved for internal use.
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
35
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
This common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed byte wise or word wise. Portions of the
on-chip DPRAM and the register spaces (ESFR/SFR) have additionally been made
directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXBus (such as USIC or MultiCAN). The
system bus allows concurrent two-way communication for maximum transfer
performance.
Up to 64 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is therefore optimized for code
fetches. A section of the PSRAM with programmable size can be write-protected.
Note: The actual size of the PSRAM depends on the chosen derivative (see Table 1).
16 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data. The DSRAM is accessed via a separate interface and is, therefore, optimized for
data accesses.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, general purpose register banks. A register bank
can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RH0, …, RL7, RH7)
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
1 Kbyte of on-chip Stand-By SRAM (SBRAM) is provided as a storage for system-
relevant user data that must be preserved while the major part of the device is powered
down. The SBRAM is accessed via a specific interface and is powered via domain M.
Data Sheet
36
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word wide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC2000 Family. Therefore, they
should either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Up to 768 Kbytes of on-chip Flash memory store code, constant data, and control
data. The on-chip Flash memory consists of up to 3 modules with a maximum capacity
of 256 Kbytes each. Each module is organized in 4-Kbyte sectors. One 4-Kbyte sector
of Flash module 0 is used internally to store operation control parameters and protection
information.
Note: The actual size of the Flash memory depends on the chosen derivative (see
Table 1).
Each sector can be separately write protected1), erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read accesses with protected and efficient writing algorithms for programming and
erasing. Dynamic error correction provides extremely high read data security for all read
accesses. Accesses to different Flash modules can be executed in parallel.
For timing characteristics, please refer to Section 4.4.2, for further Flash parameters,
please refer to Section 5.3.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
Data Sheet
37
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). The EBC also controls accesses to resources connected to the on-chip
LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of
the external bus and allows accessing integrated peripherals and modules in the same
way as external components.
The EBC can be programmed either to Single Chip Mode when no external memory is
required, or to an external bus mode with the following possible selections1):
•
•
•
Address Bus Width with a range of 0 … 24-bit
Data Bus Width 8-bit or 16-bit
Bus Operation Multiplexed or Demultiplexed
The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed
bus modes, the lower addresses are separately output on Port 0 and Port 1. The number
of active segment address lines is selectable, restricting the external address space to
8 Mbytes … 64 Kbytes. This is required when interface lines shall be assigned to Port 2.
Up to 5 external CS signals (4 windows plus default) can be generated and output on
Port 4 in order to save external glue logic. External modules can directly be connected
to the common address/data bus and their individual select lines.
A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software. After
enabling, pins P3.0 … P3.2 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin
HLDA is switched to input. This allows the direct connection of the slave controller to
another master controller without glue logic.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
Access to very slow memories or modules with varying access times is supported via a
particular ‘Ready’ function. The active level of the control input signal is selectable.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control accesses to resources with different bus characteristics.
These address windows are arranged hierarchically where window 4 overrides
window 3, and window 2 overrides window 1. All accesses to locations not covered by
these 4 address windows are controlled by TCONCS0/FCONCS0. The currently active
window can generate a chip select signal.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
38
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
PSRAM
Flash/ROM
PMU
CPU
Prefetch
CSP
IP
VECSEG
TFR
2-Stage
Prefetch
Pipeline
Unit
CPUCON1
CPUCON2
Branch
Unit
5-Stage
Pipeline
Injection/
Exception
Handler
DPRAM
Return
Stack
FIFO
IFU
DPP0
IPIP
IDX0
IDX1
QX0
QX1
QR0
QR1
SPSEG
SP
CP
R15
DPP1
DPP2
DPP3
STKOV
STKUN
R15
R14
R14
GPRs
GPRs
+/-
+/-
ADU
s
R1
R0
R1
Division Unit
Multiply Unit
Bit-Mask-Gen.
Barrel-Shifter
R0
Multiply
Unit
MRW
R0
R0
MCW
MSW
MDC
PSW
RF
+/-
+/-
MDH
MDL
ONES
ALU
DSRAM
EBC
Peripherals
Buffer
WB
MAH
MAL
ZEROS
MAC
DMU
mca04917_x.vsd
Figure 4
CPU Block Diagram
Data Sheet
39
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
Based on these hardware provisions, most of the XC228x’s instructions can be executed
in just one machine cycle which requires 15 ns at 66 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,
while the remaining cycles are executed in the background. Another pipeline
optimization, the branch target prediction, allows eliminating the execution time of
branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 word
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank to be accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC228x instruction set which includes
the following instruction classes:
•
•
•
•
•
•
•
•
•
•
•
•
•
Standard Arithmetic Instructions
DSP-Oriented Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
40
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.4
Interrupt System
With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC228x is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the XC228x supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC228x has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bit field exists for each of the possible interrupt nodes. Via
its related register, each node can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4 shows all of the possible XC228x interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may
be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).
Data Sheet
41
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 4
Functional Description
XC228x Interrupt Nodes
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Trap
Number
Location1)
CAPCOM Register 16, or
ERU Request 0
CC2_CC16IC
CC2_CC17IC
CC2_CC18IC
CC2_CC19IC
CC2_CC20IC
CC2_CC21IC
CC2_CC22IC
CC2_CC23IC
CC2_CC24IC
CC2_CC25IC
CC2_CC26IC
CC2_CC27IC
CC2_CC28IC
CC2_CC29IC
xx’0040H
xx’0044H
xx’0048H
xx’004CH
xx’0050H
xx’0054H
xx’0058H
xx’005CH
xx’0060H
xx’0064H
xx’0068H
xx’006CH
xx’0070H
xx’0074H
10H / 16D
11H / 17D
12H / 18D
13H / 19D
14H / 20D
15H / 21D
16H / 22D
17H / 23D
18H / 24D
19H / 25D
1AH / 26D
1BH / 27D
1CH / 28D
1DH / 29D
CAPCOM Register 17, or
ERU Request 1
CAPCOM Register 18, or
ERU Request 2
CAPCOM Register 19, or
ERU Request 3
CAPCOM Register 20, or
USIC0 Request 6
CAPCOM Register 21, or
USIC0 Request 7
CAPCOM Register 22, or
USIC1 Request 6
CAPCOM Register 23, or
USIC1 Request 7
CAPCOM Register 24, or
ERU Request 0
CAPCOM Register 25, or
ERU Request 1
CAPCOM Register 26, or
ERU Request 2
CAPCOM Register 27, or
ERU Request 3
CAPCOM Register 28, or
USIC2 Request 6
CAPCOM Register 29, or
USIC2 Request 7
CAPCOM Register 30
CAPCOM Register 31
GPT1 Timer 2
CC2_CC30IC
CC2_CC31IC
xx’0078H
xx’007CH
1EH / 30D
1FH / 31D
20H / 32D
21H / 33D
22H / 34D
GPT12E_T2IC xx’0080H
GPT12E_T3IC xx’0084H
GPT12E_T4IC xx’0088H
GPT1 Timer 3
GPT1 Timer 4
Data Sheet
42
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 4
Functional Description
XC228x Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Trap
Number
Location1)
GPT2 Timer 5
GPT12E_T5IC xx’008CH
GPT12E_T6IC xx’0090H
GPT12E_CRIC xx’0094H
23H / 35D
24H / 36D
25H / 37D
26H / 38D
27H / 39D
28H / 40D
29H / 41D
2AH / 42D
2BH / 43D
2CH / 44D
2DH / 45D
2EH / 46D
2FH / 47D
30H / 48D
31H / 49D
32H / 50D
33H / 51D
34H / 52D
35H / 53D
36H / 54D
37H / 55D
38H / 56D
39H / 57D
3AH / 58D
3BH / 59D
3CH / 60D
3DH / 61D
3EH / 62D
3FH / 63D
40H / 64D
GPT2 Timer 6
GPT2 CAPREL Register
CAPCOM Timer 7
CC2_T7IC
CC2_T8IC
ADC_0IC
xx’0098H
xx’009CH
xx’00A0H
xx’00A4H
xx’00A8H
xx’00ACH
xx’00B0H
xx’00B4H
xx’00B8H
xx’00BCH
xx’00C0H
xx’00C4H
xx’00C8H
xx’00CCH
xx’00D0H
xx’00D4H
xx’00D8H
xx’00DCH
xx’00E0H
xx’00E4H
xx’00E8H
xx’00ECH
xx’00F0H
xx’00F4H
xx’00F8H
xx’00FCH
xx’0100H
CAPCOM Timer 8
A/D Converter Request 0
A/D Converter Request 1
A/D Converter Request 2
A/D Converter Request 3
A/D Converter Request 4
A/D Converter Request 5
A/D Converter Request 6
A/D Converter Request 7
CCU60 Request 0
CCU60 Request 1
CCU60 Request 2
CCU60 Request 3
CCU61 Request 0
CCU61 Request 1
CCU61 Request 2
CCU61 Request 3
CCU62 Request 0
CCU62 Request 1
CCU62 Request 2
CCU62 Request 3
CCU63 Request 0
CCU63 Request 1
CCU63 Request 2
CCU63 Request 3
CAN Request 0
ADC_1IC
ADC_2IC
ADC_3IC
ADC_4IC
ADC_5IC
ADC_6IC
ADC_7IC
CCU60_0IC
CCU60_1IC
CCU60_2IC
CCU60_3IC
CCU61_0IC
CCU61_1IC
CCU61_2IC
CCU61_3IC
CCU62_0IC
CCU62_1IC
CCU62_2IC
CCU62_3IC
CCU63_0IC
CCU63_1IC
CCU63_2IC
CCU63_3IC
CAN_0IC
Data Sheet
43
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 4
Functional Description
XC228x Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Trap
Number
Location1)
CAN Request 1
CAN Request 2
CAN Request 3
CAN Request 4
CAN Request 5
CAN Request 6
CAN Request 7
CAN Request 8
CAN Request 9
CAN Request 10
CAN Request 11
CAN Request 12
CAN Request 13
CAN Request 14
CAN Request 15
USIC0 Request 0
USIC0 Request 1
USIC0 Request 2
USIC0 Request 3
USIC0 Request 4
USIC0 Request 5
USIC1 Request 0
USIC1 Request 1
USIC1 Request 2
USIC1 Request 3
USIC1 Request 4
USIC1 Request 5
USIC2 Request 0
USIC2 Request 1
USIC2 Request 2
CAN_1IC
CAN_2IC
CAN_3IC
CAN_4IC
CAN_5IC
CAN_6IC
CAN_7IC
CAN_8IC
CAN_9IC
CAN_10IC
CAN_11IC
CAN_12IC
CAN_13IC
CAN_14IC
CAN_15IC
U0C0_0IC
U0C0_1IC
U0C0_2IC
U0C1_0IC
U0C1_1IC
U0C1_2IC
U1C0_0IC
U1C0_1IC
U1C0_2IC
U1C1_0IC
U1C1_1IC
U1C1_2IC
U2C0_0IC
U2C0_1IC
U2C0_2IC
xx’0104H
xx’0108H
xx’010CH
xx’0110H
xx’0114H
xx’0118H
xx’011CH
xx’0120H
xx’0124H
xx’0128H
xx’012CH
xx’0130H
xx’0134H
xx’0138H
xx’013CH
xx’0140H
xx’0144H
xx’0148H
xx’014CH
xx’0150H
xx’0154H
xx’0158H
xx’015CH
xx’0160H
xx’0164H
xx’0168H
xx’016CH
xx’0170H
xx’0174H
xx’0178H
41H / 65D
42H / 66D
43H / 67D
44H / 68D
45H / 69D
46H / 70D
47H / 71D
48H / 72D
49H / 73D
4AH / 74D
4BH / 75D
4CH / 76D
4DH / 77D
4EH / 78D
4FH / 79D
50H / 80D
51H / 81D
52H / 82D
53H / 83D
54H / 84D
55H / 85D
56H / 86D
57H / 87D
58H / 88D
59H / 89D
5AH / 90D
5BH / 91D
5CH / 92D
5DH / 93D
5EH / 94D
Data Sheet
44
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 4
Functional Description
XC228x Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Trap
Number
Location1)
USIC2 Request 3
USIC2 Request 4
USIC2 Request 5
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
SCU Request 1
U2C1_0IC
xx’017CH
xx’0180H
xx’0184H
xx’0188H
xx’018CH
xx’0190H
xx’0194H
xx’0198H
xx’019CH
xx’01A0H
xx’01A4H
xx’01A8H
xx’01ACH
xx’01B0H
xx’01B4H
xx’01B8H
xx’01BCH
5FH / 95D
60H / 96D
U2C1_1IC
U2C1_2IC
61H / 97D
–
62H / 98D
–
63H / 99D
–
64H / 100D
65H / 101D
66H / 102D
67H / 103D
68H / 104D
69H / 105D
6AH / 106D
6BH / 107D
6CH / 108D
6DH / 109D
6EH / 110D
6FH / 111D
–
–
–
–
–
–
SCU_1IC
SCU_0IC
PFM_IC
RTC_IC
EOPIC
SCU Request 0
Program Flash Modules
RTC
End of PEC Subchannel
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
45
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
The XC228x also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
Location1) Number Priority
Reset Functions
–
RESET
xx’0000H
00H
III
Class A Hardware Traps:
•
•
•
•
System Request 0
Stack Overflow
Stack Underflow
Software Break
SR0
STKOF
STKUF
SR0TRAP
STOTRAP
STUTRAP
xx’0008H
xx’0010H
xx’0018H
02H
04H
06H
08H
II
II
II
II
SOFTBRK SBRKTRAP xx’0020H
Class B Hardware Traps:
•
•
•
•
System Request 1
Undefined Opcode
Memory Access Error
Protected Instruction
Fault
SR1
BTRAP
xx’0028H
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
0AH
I
I
I
I
UNDOPC BTRAP
ACER
PRTFLT
BTRAP
BTRAP
•
Illegal Word Operand
Access
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
–
–
–
[2CH - 3CH] [0BH -
0FH]
–
Software Traps:
Any
Any
Current
CPU
Priority
•
TRAP Instruction
[xx’0000H - [00H -
xx’01FCH] 7FH]
in steps of
4H
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
46
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.5
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC228x. The user software running on the XC228x can thus be
debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface or via the external bus interface for
increased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 optional break
lines) to communicate with external circuitry.
Data Sheet
47
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.6
Capture/Compare Unit (CAPCOM2)
The CAPCOM2 unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM2 unit is typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, an external
count input for CAPCOM2 timer T7 allows event scheduling for the capture/compare
registers relative to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM2 timer T7 or T8
and programmed for capture or compare function.
All registers of the CAPCOM2 module have each one port pin associated with it which
serves as an input pin for triggering the capture function, or as an output pin to indicate
the occurrence of a compare event.
Table 6
Compare Modes (CAPCOM2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
Several compare interrupts per timer period are possible
Mode 1
Mode 2
Mode 3
Pin toggles on each compare match;
Several compare events per timer period are possible
Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
Can be used with any compare mode
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
Data Sheet
48
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Data Sheet
49
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
Reload Reg.
T7REL
fCC
T7
T7IN
T6OUF
Input
Control
Timer T7
T7IRQ
CCxIO
CCxIO
CCxIRQ
CCxIRQ
Mode
Control
(Capture
or
Sixteen
16-bit
Capture/
Compare
Registers
Compare)
CCxIO
CCxIRQ
T8IRQ
T8
Input
fCC
Timer T8
T6OUF
Control
Reload Reg.
T8REL
CAPCOM2 provides channels x = 16 … 31.
(see signals CCxIO and CCxIRQ)
MCB05569_2
Figure 5
CAPCOM2 Unit Block Diagram
Data Sheet
50
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.7
Capture/Compare Units CCU6x
The XC228x features up to four CCU6 units (CCU60, CCU61, CCU62, CCU63).
The CCU6 is a high-resolution capture and compare unit with application specific modes.
It provides inputs to start the timers synchronously, an important feature in devices with
several CCU6 modules.
The module provides two independent timers (T12, T13), that can be used for PWM
generation, especially for AC-motor control. Additionally, special control modes for block
commutation and multi-phase machines are supported.
Timer 12 Features
•
Three capture/compare channels, each channel can be used either as capture or as
compare channel.
•
Generation of a three-phase PWM supported (six outputs, individual signals for high-
side and low-side switches)
•
•
•
•
•
•
•
•
16 bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of the required T12/13 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Many interrupt request sources
Hysteresis-like control mode
Automatic start on an HW event (T12HR, for synchronization purposes)
Timer 13 Features
•
•
•
•
•
•
One independent compare channel with one output
16 bit resolution, maximum count frequency = peripheral clock
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Automatic start on an HW event (T13HR, for synchronization purposes)
Additional Features
•
•
•
•
•
•
•
Block commutation for Brushless DC-drives implemented
Position detection via Hall-sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
Data Sheet
51
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
CCU6 Module Kernel
fSYS
compare
Channel 0
T12 Channel 1
Channel 2
1
Dead-
time
Control
Multi-
channel
Control
Trap
Control
TxHR
1
1
start
Interrupts
T13 Channel 3
compare
1
3
2
2
2
3
1
Input / Output Control
mc_ccu6_blockdiagram.vsd
Figure 6
CCU6 Block Diagram
Timer T12 can work in capture and/or compare mode for its three channels. The modes
can also be combined. Timer T13 can work in compare mode only. The multi-channel
control unit generates output patterns that can be modulated by timer T12 and/or timer
T13. The modulation sources can be selected and combined for the signal modulation.
Data Sheet
52
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.8
General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
53
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
T3CON.BPS1
2n:1
Basic Clock
fGPT
Interrupt
Request
(T2IRQ)
Aux. Timer T2
U/D
T2IN
T2
Mode
Control
Reload
T2EUD
Capture
Interrupt
Request
(T3IRQ)
T3
Mode
Control
Core Timer T3
T3OTL
Toggle
Latch
T3IN
T3OUT
U/D
T3EUD
Capture
Reload
T4IN
T4
Mode
Control
Interrupt
Request
(T4IRQ)
Aux. Timer T4
T4EUD
U/D
MCA05563
Figure 7
Block Diagram of GPT1
Data Sheet
54
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the XC228x to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Data Sheet
55
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
T6CON.BPS2
2n:1
Basic Clock
fGPT
Interrupt
Request
(T5IRQ)
GPT2 Timer T5
T5
Mode
Control
U/D
T5IN
Clear
Capture
CAPIN
GPT2 CAPREL
CAPREL
Mode
Control
Interrupt
Request
(CRIRQ)
Reload
Clear
T3IN/
T3EUD
Interrupt
Request
(T6IRQ)
Toggle
FF
GPT2 Timer T6
T6OTL
T6OUT
T6OUF
T6
Mode
Control
U/D
T6IN
MCA05564
Figure 8
Block Diagram of GPT2
Data Sheet
56
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.9
Real Time Clock
The Real Time Clock (RTC) module of the XC228x can be clocked with a selectable
clock signal from internal sources (oscillators or PLL) or external sources (pins).
The RTC basically consists of a chain of divider blocks:
•
•
•
Selectable 32:1 and 8:1 dividers (on - off)
The reloadable 16-bit timer T14
The 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
fRTC
MUX
:
32
RUN
RTCINT
MUX
Interrupt Sub Node
: 8
CNT
INT0
CNT
INT1
CNT
INT2
CNT
INT3
PRE
REFCLK
REL-Register
T14REL
10 Bits
6 Bits
6 Bits
10 Bits
fCNT
T14
10 Bits
6 Bits
6 Bits
10 Bits
T14-Register
CNT-Register
MCB05568B
Figure 9
RTC Block Diagram
Note: The registers associated with the RTC are only affected by a power reset.
Data Sheet
57
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
The RTC module can be used for different purposes:
•
•
System clock to determine the current time and date
Cyclic time based interrupt, to provide a system time tick independent of CPU
frequency and other resources
•
•
48-bit timer for long term measurements
Alarm interrupt upon a defined time
Data Sheet
58
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.10
A/D Converters
For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with 16
(or 8) multiplexed input channels including a sample and hold circuit have been
integrated on-chip. They use the method of successive approximation. The sample time
(for loading the capacitors) and the conversion time are programmable and can thus be
adjusted to the external circuitry. The A/D converters can also operate in 8-bit conversion
mode, where the conversion time is further reduced.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to fulfill
the requirements of the respective application. Both modules can be synchronized to
allow parallel sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically.
For applications that require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converters of the XC228x support two types of request sources which can be
triggered by several internal and external events.
•
Parallel requests are activated at the same time and then executed in a predefined
sequence.
•
Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing this sequence. All requests are arbitrated according to the priority level
that has been assigned to them.
Data reduction features, such as limit checking or result accumulation, reduce the
number of required CPU accesses and so allow the precise evaluation of analog inputs
(high conversion rate) even at low CPU speed.
The Peripheral Event Controller (PEC) may be used to control the A/D converters or to
automatically store conversion results into a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Therefore, each A/D converter contains 8 result registers which can be concatenated to
build a result FIFO. Wait-for-read mode can be enabled for each result register to
prevent loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital input stages under
software control. This can be selected for each pin separately via registers P5_DIDIS
and P15_DIDIS (Port x Digital Input Disable).
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Data Sheet
59
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.11
Universal Serial Interface Channel Modules (USIC)
The XC228x features three USIC modules (USIC0, USIC1, USIC2), each providing two
serial communication channels.
The Universal Serial Interface Channel (USIC) module is based on a generic data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent from the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit, so the inputs
and outputs of each USIC channel can be assigned to different interface pins providing
great flexibility to the application software. All assignments can be done during runtime.
Bus
Buffer & Shift Structure Protocol Preprocessors
Pins
Control 0
PPP_A
PPP_B
PPP_C
PPP_D
DBU
0
DSU
0
Control 1
PPP_A
PPP_B
PPP_C
PPP_D
DBU
1
DSU
1
fsys
Fractional
Dividers
Baud rate
Generators
USIC_basic.vsd
Figure 10
General Structure of a USIC Module
The regular structure of the USIC module brings the following advantages:
•
•
•
Higher flexibility through configuration with same look-and-feel for data management
Reduced complexity for low-level drivers serving different protocols
Wide range of protocols, but improved performances (baud rate, buffer handling)
Data Sheet
60
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
Target Protocols
Each USIC channel can receive and transmit data frames with a selectable data word
width from 1 to 16 bits in each of the following protocols:
•
•
•
UART (asynchronous serial channel)
– maximum baud rate: fSYS / 4
– data frame length programmable from 1 to 63 bits
– MSB or LSB first
LIN Support (Local Interconnect Network)
– maximum baud rate: fSYS / 16
– checksum generation under software control
– baud rate detection possible by built-in capture event of baud rate generator
SSC/SPI/QSPI (synchronous serial channel with or without data buffer)
– maximum baud rate in slave mode: fSYS
– maximum baud rate in master mode: fSYS / 2
– number of data bits programmable from 1 to 63, more with explicit stop condition
– MSB or LSB first
– optional control of slave select signals
IIC (Inter-IC Bus)
– supports baud rates of 100 kbit/s and 400 kbit/s
IIS (Inter-IC Sound Bus)
•
•
– maximum baud rate: fSYS / 2 for transmitter, fSYS for receiver
Note: Depending on the selected functions (such as digital filters, input synchronization
stages, sample point adjustment, etc.), the maximum reachable baud rate can be
limited. Please also take care about additional delays, such as internal or external
propagation delays and driver delays (e.g. for collision detection in UART mode,
for IIC, etc.).
Data Sheet
61
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.12
MultiCAN Module
The MultiCAN module contains up to five independently operating CAN nodes with Full-
CAN functionality which are able to exchange Data and Remote Frames via a gateway
function. Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All CAN nodes share a common set of 128 message objects. Each message object can
be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to its own message object list, and it transmits only messages
belonging to this message object list. A powerful, command-driven list controller
performs all message object list operations.
MultiCAN Module Kernel
TXDC4
CAN
Node 4
RXDC4
Clock
Control
fCAN
.
.
.
.
.
.
.
.
.
Message
Object
Buffer
Linked
List
Control
Address
Decoder
Port
Control
TXDC1
RXDC1
CAN
Node 1
128
Objects
TXDC0
RXDC0
CAN
Node 0
Interrupt
Control
CAN Control
mc_mcan_block5.vsd
Figure 11
Block Diagram of MultiCAN Module
Data Sheet
62
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
MultiCAN Features
•
CAN functionality conforms to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
•
•
•
•
•
•
Up to five independent CAN nodes
128 independent message objects (shared by the CAN nodes)
Dedicated control registers for each CAN node
Data transfer rate up to 1 Mbit/s, individually programmable for each node
Flexible and powerful message transfer control and error handling capabilities
Full-CAN functionality for message objects:
– Can be assigned to one of the CAN nodes
– Configurable as transmit or receive objects, or as message buffer FIFO
– Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering
– Remote Monitoring Mode, and frame counter for monitoring
Automatic Gateway Mode support
16 individually programmable interrupt nodes
Analyzer mode for CAN bus monitoring
•
•
•
Data Sheet
63
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.13
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT. Thus, the
chip’s start-up procedure is always monitored. The software has to be designed to
service the Watchdog Timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the Watchdog Timer overflows and generates a
prewarning interrupt and then a reset request.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 16,384
or 256. The Watchdog Timer register is set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it
is serviced by the application software, the Watchdog Timer is reloaded and the
prescaler is cleared.
Thus, time intervals between 3.9 µs and 16.3 s can be monitored (@ 66 MHz).
The default Watchdog Timer interval after power-up is 6.5 ms (@ 10 MHz).
Data Sheet
64
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.14
Clock Generation
The Clock Generation Unit can generate the system clock signal fSYS for the XC228x with
high flexibility from several external or internal clock sources.
•
•
•
•
External clock signals on pad- or core-voltage level
External crystal controlled by on-chip oscillator
On-chip oscillator (IOSC) for operation without crystal
Wake-up oscillator (ultra-low power) to further reduce power consumption
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals or from the on-chip oscillator. See
also Section 4.4.1.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can also be output on one of two selectable pins.
Data Sheet
65
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.15
Parallel Ports
The XC228x provides up to 118 I/O lines which are organized into 11 input/output ports
and 2 input ports. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have programmable alternate input or output functions associated with
them. These alternate functions can be assigned to various port pins to support the
optimal utilization for a given application. For this reason, certain functions appear
several times in Table 7.
All port lines that are not used for these alternate functions may be used as general
purpose I/O lines.
Table 7
Summary of the XC228x’s Parallel Ports
Port
Width
Alternate Functions
Port 0
8
Address lines,
Serial interface lines of USIC1, CAN0, and CAN1,
Input/Output lines for CCU61
Port 1
Port 2
8
Address lines,
Serial interface lines of USIC1 and USIC2,
Input/Output lines for CCU62,
OCDS control, interrupts
13
Address and/or data lines, bus control,
Serial interface lines of USIC0, CAN0, and CAN1,
Input/Output lines for CCU60, CCU63, and CAPCOM2,
Timer control signals,
JTAG, interrupts, system clock output
Port 3
Port 4
8
8
Bus arbitration signals,
Serial interface lines of USIC0, USIC2, CAN3, and CAN4
Chip select signals,
Serial interface lines of CAN2,
Input/Output lines for CAPCOM2,
Timer control signals
Data Sheet
66
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 7
Functional Description
Summary of the XC228x’s Parallel Ports (cont’d)
Port
Width
Alternate Functions
Port 5
16
Analog input channels to ADC0,
Input/Output lines for CCU6x,
Timer control signals,
JTAG, OCDS control, interrupts
Port 6
Port 7
4
ADC control lines,
Serial interface lines of USIC1,
Timer control signals,
OCDS control
5
ADC control lines,
Serial interface lines of USIC0 and CAN4,
Input/Output lines for CCU62,
Timer control signals,
JTAG, OCDS control,system clock output
Port 8
Port 9
7
8
Input/Output lines for CCU60,
JTAG, OCDS control
Serial interface lines of USIC2,
Input/Output lines for CCU60 and CCU63,
OCDS control
Port 10
16
Address and/or data lines, bus control,
Serial interface lines of USIC0, USIC1, CAN2, CAN3, and CAN4,
Input/Output lines for CCU60,
JTAG, OCDS control
Port 11
Port 15
6
8
Input/Output lines for CCU63
Analog input channels to ADC1,
Timer control signals
Data Sheet
67
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.16
Power Management
The XC228x provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
•
Supply Voltage Management allows the temporary reduction of the supply voltage
of major parts of the logic, or even the complete disconnection. This drastically
reduces the power consumed because of leakage current, in particular at high
temperature.
Several power reduction modes provide the optimal balance of power reduction and
wake-up time.
•
•
Clock Generation Management controls the frequency of internal and external
clock signals. While the clock signals for currently inactive parts of logic are disabled
automatically, the user can reduce the XC228x’s system clock frequency which
drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output EXTCLK.
Peripheral Management permits temporary disabling of peripheral modules. Each
peripheral can separately be disabled/enabled. Also the CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally by signals
generated by the external system, or internally by the on-chip wake-up timer, which
supports intermittent operation of the XC228x by generating cyclic wake-up signals. This
offers full performance to quickly react on action requests while the intermittent sleep
phases greatly reduce the average power consumption of the system.
Note: When selecting the supply voltage and the clock source and generation method,
the required parameters must be carefully written to the respective bitfields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the intended operation of power supply system and clock system.
Data Sheet
68
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.17
Instruction Set Summary
Table 8 lists the instructions of the XC228x in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 8
Instruction Set Summary
Description
Mnemonic
ADD(B)
Bytes
2 / 4
2 / 4
2 / 4
2 / 4
2
Add word (byte) operands
ADDC(B)
SUB(B)
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
SUBC(B)
MUL(U)
(Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit)
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
DIVL(U)
CPL(B)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise exclusive OR, (word/byte operands)
Clear/Set direct bit
2
NEG(B)
AND(B)
OR(B)
2
2 / 4
2 / 4
2 / 4
2
XOR(B)
BCLR/BSET
BMOV(N)
Move (negated) direct bit to direct bit
4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
4
BCMP
Compare direct bit to direct bit
4
BFLDH/BFLDL
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
Compare word (byte) operands
2 / 4
Compare word data to GPR and decrement GPR by 1/2 2 / 4
Compare word data to GPR and increment GPR by 1/2
2 / 4
2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
SHL/SHR
Data Sheet
Shift left/right direct word GPR
2
69
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Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
Table 8
Mnemonic
ROL/ROR
ASHR
Instruction Set Summary (cont’d)
Description
Bytes
Rotate left/right direct word GPR
2
Arithmetic (sign bit) shift right direct word GPR
Move word (byte) data
2
MOV(B)
MOVBS/Z
JMPA/I/R
JMPS
2 / 4
Move byte operand to word op. with sign/zero extension 2 / 4
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
4
4
4
4
JB(C)
Jump relative if direct bit is set (and clear bit)
Jump relative if direct bit is not set (and set bit)
JNB(S)
CALLA/I/R
CALLS
Call absolute/indirect/relative subroutine if condition is met 4
Call absolute subroutine in any code segment
4
4
PCALL
Push direct word register onto system stack and call
absolute subroutine
TRAP
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
2
2
4
PUSH/POP
SCXT
Push direct word register onto system stack and update
register with word operand
RET(P)
Return from intra-segment subroutine
2
(and pop direct word register from system stack)
RETS
Return from inter-segment subroutine
Return from interrupt service subroutine
Software Break
2
RETI
2
SBRK
SRST
2
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
SRVWDT
Unused instruction1)
4
Service Watchdog Timer
4
DISWDT/ENWDT Disable/Enable Watchdog Timer
4
EINIT
End-of-Initialization Register Lock
4
ATOMIC
EXTR
Begin ATOMIC sequence
2
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
2
EXTP(R)
EXTS(R)
2 / 4
2 / 4
Data Sheet
70
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
Table 8
Mnemonic
NOP
Instruction Set Summary (cont’d)
Description
Bytes
Null operation
2
4
4
4
4
CoMUL/CoMAC
CoADD/CoSUB
Co(A)SHR
Multiply (and accumulate)
Add/Subtract
(Arithmetic) Shift right
Shift left
CoSHL
CoLOAD/STORE
CoCMP
Load accumulator/Store MAC register
Compare
4
4
4
4
4
4
CoMAX/MIN
CoABS/CoRND
CoMOV
Maximum/Minimum
Absolute value/Round accumulator
Data move
CoNEG/NOP
Negate accumulator/Null operation
1) The Enter Power Down Mode instruction is not used in the XC228x, due to the enhanced power control
scheme. PWRDN will be correctly decoded, but will trigger no action.
Data Sheet
71
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4
Electrical Parameters
The operating range for the XC228x is defined by its electrical parameters. For proper
operation the indicated limitations must be respected when designing a system.
Attention: The parameters and values listed in the following sections of this
Preliminary Data Sheet are preliminary and will be adjusted and
amended after the complete device characterization has been
completed.
4.1
General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
Table 9
Absolute Maximum Rating Parameters
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
-65
Typ.
Max.
150
Storage temperature
Junction temperature
TST
TJ
–
–
–
°C
°C
V
–
-40
150
under bias
–
Voltage on VDDI pins with VDDIM
respect to ground (VSS)
Voltage on VDDP pins with VDDPA
,
-0.5
1.65
VDDI1
,
-0.5
-0.5
-10
–
–
–
–
–
6.0
V
–
respect to ground (VSS)
VDDPB
Voltage on any pin with
VIN
VDDP
+ 0.5
V
VIN < VDDPmax
respect to ground (VSS)
Input current on any pin
during overload condition
–
–
10
mA
mA
–
–
Absolute sum of all input
currents during overload
condition
|100|
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
72
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC228x. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Table 10
Operating Condition Parameters
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
Typ.
Max.
Digital core supply voltage VDDI
1.4
–
1.6
V
(if supplied externally)
Core Supply Voltage
Difference
∆VDDI -10
–
–
+10
5.5
mV VDDIM - VDDI1
1)
2)
Digital supply voltage for VDDPA
,
4.5
V
IO pads and voltage
VDDPB
regulators,
upper voltage range
2)
Digital supply voltage for VDDPA
,
3.0
–
4.5
V
IO pads and voltage
VDDPB
regulators,
lower voltage range
3)
Supply Voltage Difference ∆VDD
-0.5
0
–
–
–
0
V
V
VDDP - VDDI
Digital ground voltage
VSS
Reference
voltage
Overload current
IOV
-5
-2
–
–
5
5
mA Per IO pin4)5)
mA Per analog input
pin4)5)
Overload positive current KOVA
coupling factor for analog
inputs6)
–
–
–
–
–
–
–
–
1.0 ×
–
–
–
–
I
I
I
I
OV > 0
OV < 0
OV > 0
OV < 0
10-4
Overload negative current KOVA
coupling factor for analog
inputs6)
1.5 ×
10-3
Overload positive current KOVD
coupling factor for digital
I/O pins6)
5.0 ×
10-3
Overload negative current KOVD
coupling factor for digital
I/O pins6)
1.0 ×
10-2
Data Sheet
73
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Table 10
Operating Condition Parameters (cont’d)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Min.
Max.
5)
Absolute sum of overload Σ|IOV|
currents
–
50
mA
pF
nF
°C
External Pin Load
Capacitance
CL
–
–
–
20
680
–
–
–
–
Pin drivers in
default mode7)
Voltage Regulator Buffer CEVR
Capacitance
For each core
domain8)
Ambient temperature
TA
See Table 1
1) In case both core power domains are clocked, the difference between the power supply voltages must be less
than 10mV. This condition imposes additional constraints when using external power supplies. In order to
supply both core power domains, two independent external voltage regulators may not be used. The simplest
possibility is to supply both power domains directly via a single external power supply.
2) Performance of pad drivers, A/D Converter, and Flash module depends on VDDP
.
3) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down,
and power-save modes, if VDDI is supplied externally.
4) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin (IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application.
Overload conditions must not occur on pin XTAL1 (powered by VDDI).
5) Not subject to production test - verified by design/characterization.
6) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
7) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
8) To ensure the stability of the voltage regulators each core voltage domain must be buffered with a ceramic
capacitor. For domain M a 680 nF capacitor is recommended, for domain 1 three 220 nF capacitors are
recommended. All buffer capacitors must be connected als close to the VDDI pins as possible to keep the
resistance of the board tracks below 2 Ω.
Data Sheet
74
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the XC228x
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the XC228x will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC228x.
Data Sheet
75
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.2
DC Parameters
These parameters are static or average values, which may be exceeded during
switching transitions (e.g. output current).
The XC228x can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must not vary within the complete
operating voltage range, but must remain within a certain band of 10% of the chosen
nominal supply voltage.
For this reason and because the electrical behaviour partly depends on the supply
voltage, the parameters are specified twice for the upper and the lower voltage area.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
The leakage currents strongly depend on the operating temperature and the actual
voltage level at the respective pin. The maximum values given in the following tables
apply under worst case conditions, i.e. maximum temperature and an input level equal
to the supply voltage.
The actual value for the leakage current can be determined by evaluating the respective
leakage derating formula (see tables) using values from the actual application.
The pads of the XC228x are designed to operate in various driver modes. The DC
parameter specifications refer to the current limits given in Table 11.
Table 11
Current Limits for Port Output Drivers
Port Output Driver
Mode
Maximum Output Current
Nominal Output Current
(IOLnom, -IOHnom
VDDP ≥ 4.5 V VDDP < 4.5 V VDDP ≥ 4.5 V VDDP < 4.5 V
1)
(IOLmax, -IOHmax
)
)
Strong driver
Medium driver
Weak driver
10 mA
4.0 mA
0.5 mA
10 mA
2.5 mA
0.5 mA
2.5 mA
1.0 mA
0.1 mA
2.5 mA
1.0 mA
0.1 mA
1) An output current above |IOXnom| may be drawn from up to three pins at the same time.
For any group of 16 neighboring output pins the total output current in each direction (ΣIOL and Σ-IOH) must
remain below 50 mA.
Data Sheet
76
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.2.1
DC Parameters for Upper Voltage Area
These parameters apply to the upper IO voltage area of 4.5 V ≤ VDDP ≤ 5.5 V.
Table 12
DC Characteristics for 4.5 V ≤ VDDP ≤ 5.5 V
(Operating Conditions apply)1)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Min.
VIL SR -0.3
Max.
Input low voltage
(all except XTAL1)
0.3 ×
VDDP
V
V
V
V
V
–
Input low voltage for
XTAL1
V
ILC SR -1.7 +
–
–
–
–
0.3 ×
VDDI
–
VDDI
Input high voltage
(all except XTAL1)
VIH SR 0.7 ×
VDDP
+ 0.3
–
VDDP
2)
Input high voltage for
XTAL1
Input Hysteresis3)
V
IHC SR 0.7 ×
1.7
–
VDDI
HYS CC 0.11
× VDDP
V
DD in [V],
Series
resistance = 0 Ω
4)
Output low voltage
Output low voltage
Output high voltage6)
VOL CC –
VOL CC –
–
–
–
1.0
0.4
–
V
V
V
IOL ≤ IOLmax
4) 5)
IOL ≤ IOLnom
4)
V
OH CC VDDP
IOH ≥ IOHmax
- 1.0
4) 5)
Output high voltage6)
V
OH CC VDDP
–
–
V
IOH ≥ IOHnom
- 0.4
Input leakage current
(Port 5, Port 15)7)
I
I
OZ1 CC –
OZ2 CC –
±200
±2
–
nA 0 V < VIN < VDDP
Input leakage current
(all other)7)8)
±5
µA TJ ≤ 110°C,
0.45 V < VIN
< VDDP
Input leakage current
(all other)7)8)
I
OZ2 CC –
±10
±30
µA TJ ≤ 150°C,
0.45 V < VIN
< VDDP
Level inactive hold current ILHI
Level active hold current ILHA
–
–
–
-30
–
µA VOUT ≥ VIHmin
µA VOUT ≤ VILmax
-220
Data Sheet
77
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 12
Electrical Parameters
DC Characteristics for 4.5 V ≤ VDDP ≤ 5.5 V (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
±20
10
XTAL1 input current
Pin capacitance9)
IIL CC
–
–
–
–
µA 0 V < VIN < VDDI
CIO CC
pF
(digital inputs/outputs)
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV
.
2) Overload conditions must not occur on pin XTAL1.
3) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot suppress switching due to external system
noise under all conditions.
4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 11, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are verified.
6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
7) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV
.
8) The given values are worst-case values. In the production test, this leakage current value is only tested at
125°C, other values are ensured via correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
I
OZ = 0.009 × e(0.054×TJ) [µA]. For example, at a temperature of 130°C the resulting leakage current is 10.07 µA.
Leakage derating depending on voltage level (DV = VDDP - VPIN [V]):
I
OZ = IOZtempmax - (1.6 × DV) [µA]
The shown voltage derating formula is an approximation which applies for maximum temperature.
Pin P2.8 is connected to two pads (additionally the high-speed clock pad), so it sees twice the normal leakage.
9) Not subject to production test - verified by design/characterization.
Pin P2.8 is connected to two pads (additionally the high-speed clock pad), so it sees twice the normal
capacitance.
Data Sheet
78
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.2.2
DC Parameters for Lower Voltage Area
These parameters apply to the lower IO voltage area of 3.0 V ≤ VDDP ≤ 4.5 V.
Table 13
DC Characteristics for 3.0 V ≤ VDDP ≤ 4.5 V
(Operating Conditions apply)1)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Min.
VIL SR -0.3
Max.
Input low voltage
(all except XTAL1)
0.3 ×
VDDP
V
V
V
V
V
–
Input low voltage for
XTAL1
V
ILC SR -1.7 +
–
–
–
–
0.3 ×
VDDI
–
VDDI
Input high voltage
(all except XTAL1)
VIH SR 0.7 ×
VDDP
+ 0.3
–
VDDP
2)
Input high voltage for
XTAL1
Input Hysteresis3)
V
IHC SR 0.7 ×
1.7
–
VDDI
HYS CC 0.11
× VDDP
V
DD in [V],
Series
resistance = 0 Ω
4)
Output low voltage
Output low voltage
Output high voltage6)
VOL CC –
VOL CC –
–
–
–
1.0
0.4
–
V
V
V
IOL ≤ IOLmax
4) 5)
IOL ≤ IOLnom
4)
V
OH CC VDDP
IOH ≥ IOHmax
- 1.0
4) 5)
Output high voltage6)
V
OH CC VDDP
–
–
V
IOH ≥ IOHnom
- 0.4
Input leakage current
(Port 5, Port 15)7)
I
I
OZ1 CC –
OZ2 CC –
±100
±1
–
nA 0 V < VIN < VDDP
Input leakage current
(all other)7)8)
±2.5
µA TJ ≤ 110°C,
0.45 V < VIN
< VDDP
Input leakage current
(all other)7)8)
I
OZ2 CC –
±5
±15
µA TJ ≤ 150°C,
0.45 V < VIN
< VDDP
Level inactive hold current ILHI
Level active hold current ILHA
–
–
–
-10
–
µA VOUT ≥ VIHmin
µA VOUT ≤ VILmax
-150
Data Sheet
79
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 13
Electrical Parameters
DC Characteristics for 3.0 V ≤ VDDP ≤ 4.5 V (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
±20
10
XTAL1 input current
Pin capacitance9)
IIL CC
–
–
–
–
µA 0 V < VIN < VDDI
CIO CC
pF
(digital inputs/outputs)
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV
.
2) Overload conditions must not occur on pin XTAL1.
3) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot suppress switching due to external system
noise under all conditions.
4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 11, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are verified.
6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
7) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV
.
The leakage current value is not tested in the lower voltage range, but only in the upper voltage range. This
parameter is ensured via correlation.
8) The given values are worst-case values. In the production test, this leakage current value is only tested at
125°C, other values are ensured via correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
I
OZ = 0.005 × e(0.054×TJ) [µA]. For example, at a temperature of 130°C the resulting leakage current is 5.6 µA.
Leakage derating depending on voltage level (DV = VDDP - VPIN [V]):
I
OZ = IOZtempmax - (1.3 × DV) [µA]
The shown voltage derating formula is an approximation which applies for maximum temperature.
Pin P2.8 is connected to two pads (additionally the high-speed clock pad), so it sees twice the normal leakage.
9) Not subject to production test - verified by design/characterization.
Pin P2.8 is connected to two pads (additionally the high-speed clock pad), so it sees twice the normal
capacitance.
Data Sheet
80
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.2.3
Power Consumption
The amount of power that is consumed by the XC228x depends on several factors, such
as supply voltage, operating frequency, amount of active circuitry, and operating
temperature. Part of this depends on the device’s activity (switching current), part of this
is independent (leakage current). Therefore, the leakage current must be added to all
other (frequency-dependent) parameters.
For additional information, please refer to Section 5.2, Thermal Considerations.
Table 14
Power Consumption XC228x (Operating Conditions apply)
Parameter
Sym-
bol
Values
Min. Typ.
Unit Note /
Test Condition
Max.
2)
Supply current caused by IDDL
leakage1)
(DMP_1 powered)
–
–
–
600,000 tbd
mA VDDP = VDDPmax
α =
× e-α
5000 / (273 + TJ),
TJ in [°C]
2)
Supply current caused by IDDL
leakage1)
(DMP_1 switched off)
500,000 tbd
µA
VDDP = VDDPmax
× e-α
α =
3000 / (273 + TJ),
TJ in [°C]
Power supply current
(active) withallperipherals
active and EVVRs on
IDDP
10 +
tbd
mA Active Mode3)
SYSin [MHz]
0.6×fSYS
f
1) The supply current caused by leakage mainly depends on the junction temperature (see Figure 12) and the
supply voltage. The temperature difference between the junction temperature TJ and the ambient temperature
TA must be taken into account. As this fraction of the supply current does not depend on the device’s activity,
it must be added to each other power consumption parameter.
2) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including
pins configured as outputs) disconnected. This parameter is tested at 25 °C and is valid for TJ ≥ 25 °C.
3) The pad supply voltage pins (VDDP) provide the input current for the on-chip EVVRs and the current consumed
by the pin output drivers. A small amount of current is consumed because the drivers’ input stages are
switched.
Data Sheet
81
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
I
DDL [mA]
6
4
2
DMP_1 ON
DMP_1 off
TJ [°C]
-50
0
50
100
150
MC_XC2X_IDDL
Figure 12
Leakage Supply Current as a Function of Temperature
Data Sheet
82
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
IDDtyp
I
DD [mA]
100
80
60
50
40
30
20
10
f
SYS [MHz]
20
40
60
80
MC_XC2X_IDD
Figure 13
Supply Current in Active Mode as a Function of Frequency
Data Sheet
83
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.3
Analog/Digital Converter Parameters
These parameters describe how the optimum ADC performance can be reached.
Table 15
A/D Converter Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Max.
Unit Test
Condition
Min.
1)
Analog reference supply
VAREF SR VAGND
VDDPA
+ 0.05
V
V
+ 1.0
Analog reference ground VAGND SR VSS
- 0.05
SR VAGND
0.5
VAREF
- 1.0
–
2)
3)
Analog input voltage range VAIN
Basic clock frequency
VAREF
V
fADCI
16.5
MHz
–
Conversion time for 10-bit tC10
CC (17 + STC) × tADCI
–
–
result4)
Conversion time for 8-bit tC8
CC (15 + STC) × tADCI
–
result4)
1)
5)
Total unadjusted error
TUE
CC –
±2
LSB
pF
Total capacitance
of an analog input
CAINT CC –
15
5)
5)
5)
5)
5)
Switched capacitance
of an analog input
CAINS CC –
7
pF
kΩ
pF
pF
kΩ
Resistance of
the analog input path
RAIN
CC –
1.5
20
20
2
Total capacitance
of the reference input
CAREFT CC –
CAREFS CC –
RAREF CC –
Switched capacitance
of the reference input
Resistance of
the reference input path
1) TUE is tested at VAREFx = VDDPA, VAGND = 0 V. It is verified by design for all other voltages within the defined
voltage range.
The specified TUE is valid only, if the absolute sum of input overload currents on Port 5 or Port 15 pins (see
I
OV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the respective period
of time.
2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler
setting.
Data Sheet
84
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4) This parameter includes the sample time (also the additional sample time specified by STC), the time for
determining the digital result and the time to load the result register with the conversion result.
Values for the basic clock tADCI depend on programming and can be taken from Table 16.
5) Not subject to production test - verified by design/characterization.
The given parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal
supply voltage the following typical values can be used:
CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kΩ.
A/D Converter
RSource
RAIN, On
VAIN
-
CExt
CAINT CAINS
CAINS
MCS05570
Figure 14
Equivalent Circuitry for Analog Inputs
Data Sheet
85
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Sample time and conversion time of the XC228x’s A/D Converters are programmable.
The above timing can be calculated using Table 16.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Table 16
A/D Converter Computation Table
GLOBCTR.5-0
(DIVA)
A/D Converter
Basic Clock fADCI
INPCRx.7-0
(STC)
Sample Time
tS
000000B
000001B
000010B
:
fSYS
00H
01H
02H
:
tADCI × 2
f
f
f
f
f
SYS / 2
tADCI × 3
SYS / 3
tADCI × 4
SYS / (DIVA+1)
SYS / 63
tADCI × (STC+2)
tADCI × 256
tADCI × 257
111110B
111111B
FEH
FFH
SYS / 64
Converter Timing Example:
Assumptions:
Basic clock
fSYS = 66 MHz (i.e. tSYS = 15.2 ns), DIVA = 03H, STC = 00H
fADCI = fSYS / 4 = 16.5 MHz, i.e. tADCI = 60.6 ns
Sample time
tS
= tADCI × 2 = 121 ns
Conversion 10-bit:
tC10 = 17 × tADCI = 17 × 60.6 ns = 1.03 µs
Conversion 8-bit:
tC8
= 15 × tADCI = 15 × 60.6 ns = 0.91 µs
Converter Timing Example:
Assumptions:
Basic clock
fSYS = 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H
fADCI = fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns
tS = tADCI × 5 = 375 ns
Sample time
Conversion 10-bit:
tC10 = 20 × tADCI = 20 × 75 ns = 1.5 µs
Conversion 8-bit:
tC8
= 18 × tADCI = 18 × 75 ns = 1.35 µs
Data Sheet
86
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.4
AC Parameters
These parameters describe the dynamic behavior of the XC228x.
4.4.1
Definition of Internal Timing
The internal operation of the XC228x is controlled by the internal system clock fSYS
.
Because the system clock signal fSYS can be generated from several internal and
external sources via different mechanisms, the duration of system clock periods (TCSs)
and their variation (and also the derived external timing) depend on the used mechanism
to generate fSYS. This influence must be regarded when calculating the timings for the
XC228x.
Phase Locked Loop Operation (1:N)
fIN
fSYS
TCS
Direct Clock Drive (1:1)
fIN
fSYS
TCS
Prescaler Operation (N:1)
fIN
fSYS
TCS
MC_XC2X_CLOCKGEN
Figure 15
Generation Mechanisms for the System Clock
Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
Data Sheet
87
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Direct Drive
When direct drive operation is configured (SYSCON0.CLKSEL = 11B), the system clock
is derived directly from the input clock signal DIRIN:
f
SYS = fIN.
The frequency of fSYS directly follows the frequency of fIN. In this case, the high and low
time of fSYS is defined by the duty cycle of the input clock fIN.
A similar configuration can be achieved by selecting the XTAL11) input.
Prescaler Operation
When prescaler operation is configured (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY
= 1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal oscillator through the output-prescaler:
f
SYS = fOSC / (K1DIV + 1).
If the divider factor is selected as 1, the frequency of fSYS directly follows the frequency
of fOSC. In this case, the high and low time of fSYS is defined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency can be achieved in this mode by selecting the
maximum value for divider factor K1:
f
SYS = fOSC / 1024.
Phase Locked Loop (PLL)
When PLL operation is configured (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop provides the system clock. The PLL multiplies the
selected input frequency by the factor F (fSYS = fIN × F), which results from the input
divider (P), the multiplication factor (N), and the output divider (K2): (F = N+1 / (P+1 ×
K2+1)).
The input clock can be derived either from an external source via XTAL1 or from the on-
chip oscillator.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
done smoothly, i.e. the system clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fSYS is constantly adjusted so it
is locked to fIN. The slight variation causes a jitter of fSYS which also affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDI1
.
Data Sheet
88
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
The timing listed in the AC Characteristics refers to TCSs. Therefore, the timing must be
calculated using the minimum TCS possible under the respective circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator), the accumulated jitter is limited, which means that the relative
deviation for periods of more than one TCS is lower than for one single TCS.
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is, therefore, negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K2+1) to generate the system clock signal fSYS. Therefore, the number
of VCO cycles can be represented as (K2+1) × T, where T is the number of consecutive
f
SYS cycles (TCS).
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Table 17
PLLCON0.VCOSEL VCO Frequency Range
VCO Bands for PLL Operation1)
Base Frequency Range
10 … 40 MHz
00
01
1X
40 … 120 MHz
90 … 160 MHz
Reserved
20 … 80 MHz
1) Not subject to production test - verified by design/characterization.
Wakeup Oscillator
When wakeup oscillator operation is configured (SYSCON0.CLKSEL = 00B), the system
clock is derived from the low-frequency wakeup oscillator:
f
SYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consumption.
Data Sheet
89
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bitfields, to avoid unintended
intermediate states.
Many applications change the frequency of the system clock (fSYS) during the operation,
to optimize performance and power consumption of the system. Changing the operating
frequency also changes the consumed switching current, which influences the power
supply. Therefore, while the core voltage is generated by the on-chip EVRs, the
operating frequency may only be changed by factors of 5 maximum, or in steps of
20 MHz maximum, whatever condition is tighter.
To avoid the indicated problems, recommended sequences are provided which ensure
the intended operation of the clock system interacting with the power system.
4.4.2
On-chip Flash Operation
Accesses to the XC228x’s Flash modules are controlled by the IMB.
Built-in prefetching mechanisms optimize the performance for sequential accesses.
Table 18
Flash Characteristics (Operating Conditions apply)
Symbol Limit Values
Parameter
Unit
Min.
CC –
CC –
Typ.
31)
41)
Max.
tbd
Programming time per 128-byte page tPR
Erase time per sector/page
ms
ms
tER
tbd
1) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles, which only becomes relevant for extremely low system frequencies.
Data Sheet
90
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.4.3
External Clock Drive
These parameters define the external clock supply for the XC228x. The clock signal can
be supplied either to pin P2.9 or to pin XTAL1.
Table 19
External Clock Drive Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
Min.
25
6
Max.
2501)
Oscillator period
High time2)
Low time2)
Rise time2)
Fall time2)
tOSC
t1
SR
SR
SR
SR
SR
ns
ns
ns
ns
ns
–
–
8
8
t2
6
t3
–
t4
–
1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
2) The clock input signal must reach the defined levels VILC and VIHC (for XTAL1) or VIL and VIH for P2.9.
t3
t4
t1
VIHC
VILC
0.5 VDDI
t2
tOSC
MCT05572
Figure 16
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified input frequency
range. Operation at input frequencies below 4 MHz is possible but is verified by
design only (not subject to production test).
Data Sheet
91
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.4.4
Testing Waveforms
These references are used for characterization and production testing (except for pin
XTAL1).
Output delay
Hold time
Output delay
Hold time
0.8 VDDP
0.7 VDDP
Input Signal
(driven by tester)
0.3 VDDP
0.2 VDDP
Output Signal
(measured)
Output timings refer to the rising edge of CLKOUT.
Input timings are calculated from the time, when the input signal reaches
VIH or VIL, respectively.
MCD05556C
Figure 17
Input Output Waveforms
V
Load + 0.1 V
V
V
OH - 0.1 V
OL + 0.1 V
Timing
Reference
Points
V
Load - 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded VOH /VOL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 18
Float Waveforms
Data Sheet
92
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
4.4.5
External Bus Timing
The following parameters define the behavior of the XC228x’s bus interface.
Table 20
CLKOUT Reference Signal
Symbol
Parameter
Limits
Max.
Unit
Min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
tc5
tc6
tc7
tc8
tc9
CC
40/25/151)
ns
ns
ns
ns
ns
CC
CC
CC
CC
3
3
–
–
–
–
3
3
1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/40/66 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
tC9
tC8
tC5
tC6
tC7
CLKOUT
MCT05571
Figure 19
CLKOUT Signal Timing
Note: The term CLKOUT refers to the reference clock output signal which is generated
by selecting fSYS as source signal for the clock output signal EXTCLK on pin P2.8
and by enabling the high-speed clock driver on this pin.
Data Sheet
93
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Variable Memory Cycles
External bus cycles of the XC228x are executed in five subsequent cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Table 21
Programmable Bus Cycle Phases (see timing diagrams)
Parameter Valid Values Unit
Bus Cycle Phase
Address setup phase, the standard duration of this tpAB
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
1 … 2 (5)
TCS
Command delay phase
tpC
tpD
tpE
tpF
0 … 3
0 … 1
1 … 32
0 … 3
TCS
TCS
TCS
TCS
Write Data setup/MUX Tristate phase
Access phase
Address/Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Timing values are listed in Table 22 and Table 23. The shaded parameters have been
verified by characterization. They are not subject to production test.
Data Sheet
94
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 22
Electrical Parameters
External Bus Cycle Timing for 4.5 V ≤ VDDP ≤ 5.5 V
(Operating Conditions apply)
Parameter
Symbol
Limits
Unit Note
Min. Typ. Max.
Output valid delay for:
RD, WR(L/H)
tc10 CC –
13
13
14
14
13
14
14
ns
ns
ns
ns
ns
ns
ns
Output valid delay for:
BHE, ALE
tc11 CC –
tc12 CC –
tc13 CC –
tc14 CC –
tc15 CC –
tc16 CC –
Output valid delay for:
A23 … A16, A15 … A0 (on P0/P1)
Output valid delay for:
A15 … A0 (on P2/P10)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-
mode)
Output hold time for:
RD, WR(L/H)
tc20 CC 0
tc21 CC 0
tc23 CC 0
tc24 CC 0
tc25 CC 0
tc30 SR 18
tc31 SR -4
8
8
8
8
8
–
–
ns
ns
ns
ns
ns
ns
ns
Output hold time for:
BHE, ALE
Output hold time for:
A23 … A16, A15 … A0 (on P2/P10)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
READY, D15 … D0 (read data)
Input hold time for:
READY, D15 … D0 (read data)1)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Data Sheet
95
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Table 23
Electrical Parameters
External Bus Cycle Timing for 3.0 V ≤ VDDP ≤ 4.5 V
(Operating Conditions apply)
Parameter
Symbol
Limits
Unit Note
Min. Typ. Max.
Output valid delay for:
RD, WR(L/H)
tc10 CC –
20
20
22
22
20
21
21
ns
ns
ns
ns
ns
ns
ns
Output valid delay for:
BHE, ALE
tc11 CC –
tc12 CC –
tc13 CC –
tc14 CC –
tc15 CC –
tc16 CC –
Output valid delay for:
A23 … A16, A15 … A0 (on P0/P1)
Output valid delay for:
A15 … A0 (on P2/P10)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-
mode)
Output hold time for:
RD, WR(L/H)
tc20 CC 0
tc21 CC 0
tc23 CC 0
tc24 CC 0
tc25 CC 0
tc30 SR 29
tc31 SR -6
10
10
10
10
10
–
ns
ns
ns
ns
ns
ns
ns
Output hold time for:
BHE, ALE
Output hold time for:
A23 … A16, A15 … A0 (on P2/P10)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
READY, D15 … D0 (read data)
Input hold time for:
–
READY, D15 … D0 (read data)1)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Data Sheet
96
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
ALE
tc21
tc11
tc11/tc14
A23-A16,
BHE, CSx
High Address
tc20
tc10
RD
WR(L/H)
tc31
tc13
tc23
tc30
AD15-AD0
(read)
Low Address
Data In
tc13
tc15
tc25
AD15-AD0
(write)
Low Address
Data Out
MCT05557
Figure 20
Multiplexed Bus Cycle
Data Sheet
97
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
ALE
tc21
tc11
tc11/tc14
A23-A0,
BHE, CSx
Address
tc20
tc10
RD
WR(L/H)
tc31
tc30
D15-D0
(read)
Data In
tc16
tc25
D15-D0
(write)
Data Out
MCT05558
Figure 21
Demultiplexed Bus Cycle
Data Sheet
98
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage. The minimum duration
of an asynchronous READY signal to be safely synchronized must be one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next following bus cycle is READY-controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the programmed phases of the next following cycle.
Data Sheet
99
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
tpD
tpE
tpRDY
tpF
CLKOUT
RD, WR
tc10
tc20
tc31
tc30
D15-D0
(read)
Data In
tc25
D15-D0
(write)
Data Out
tc31
tc30
tc31
tc30
READY
Synchronous
Not Rdy
READY
tc31
tc31
tc30
tc30
READY
Asynchron.
Not Rdy
READY
MCT05559
Figure 22
READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (tpRDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tpE) before the READY input is
evaluated.
Data Sheet
100
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
External Bus Arbitration
If the arbitration signals are enabled the XC228x makes its external resources available
in response to an arbitration request.
Table 24
Bus Arbitration Timing for 4.5 V ≤ VDDP ≤ 5.5 V
(Operating Conditions apply)
Parameter
Sym
bol
Limits
Unit Note
Min. Typ. Max.
Input setup time for:
HOLD input
tc40
tc41
tc42
18
–
ns
ns
ns
Output delay rising edge for:
HLDA, BREQ
0
13
14
Output delay falling edge for:
HLDA
1
Table 25
Bus Arbitration Timing for 3.0 V ≤ VDDP ≤ 4.5 V
(Operating Conditions apply)
Parameter
Sym
bol
Limits
Min. Typ. Max.
Unit Note
Input setup time for:
HOLD input
tc40
tc41
tc42
28
–
ns
ns
ns
Output delay rising edge for:
HLDA, BREQ
0
19
21
Output delay falling edge for:
HLDA
1
Note: The shaded parameters have been verified by characterization.
They are not subject to production test.
Data Sheet
101
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
CLKOUT
HOLD
tc40
tc42
HLDA
BREQ
2)
tc10/tc14
CSx, RD,
WR(L/H)
3)
Addr, Data,
BHE
1)
MCT05560
Figure 23
Notes
External Bus Arbitration, Releasing the Bus
1. The XC228x will complete the currently running bus cycle before granting bus
access.
2. This is the first possibility for BREQ to get active.
3. The control outputs will be resistive high (pull-up) after being driven inactive (ALE will
be low).
Data Sheet
102
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Electrical Parameters
3)
CLKOUT
HOLD
tc40
tc41
HLDA
tc41
BREQ
1)
tc10/tc14
CSx, RD,
WR(L/H)
2)
tc11/tc12
/tc13/tc15
/tc16
Addr, Data,
BHE
MCT05561
Figure 24
Notes
External Bus Arbitration, Regaining the Bus
1. This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going
high. Please note that HOLD may also be deactivated without the XC228x requesting
the bus.
2. The control outputs will be resistive high (pull-up) before being driven inactive (ALE
will be low).
3. The next XC228x driven bus cycle may start here.
Data Sheet
103
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Package and Reliability
5
Package and Reliability
In addition to the electrical parameters, the following information ensures proper
integration of the XC228x into the target system.
5.1
Packaging
These parameters describe the housing rather than the silicon.
Table 26
Package Parameters (PG-LQFP-144)
Symbol Limit Values
Min. Max.
Exposed Pad Dimension Ex × Ey – 6.5 × 6.5 mm
Parameter
Unit
Notes
–
Power Dissipation
PDISS
RΘJA
–
–
1.0
45
36
22
W
–
Thermal resistance
Junction-Ambient
K/W
K/W
K/W
No thermal via1)
4-layer, no pad2)
4-layer, pad3)
1) Device mounted on a 2-layer or 4-layer board without thermal vias.
2) Device mounted on a 4-layer board with thermal vias, exposed pad not soldered.
3) Device mounted on a 4-layer board with thermal vias, exposed pad soldered to the board.
Data Sheet
104
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Package and Reliability
Package Outlines
H
0.5
0.15
0.6
0.08
C
17.5
2)
0.05
0.22
M
0.08 A-B D C 144x
22
20
Bottom View
Ex
0.2 A-B
144x
D
1)
0.2 A-B
4x
D H
D
A
B
Exposed Pad
144
144
1
1
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
GPP01178
Figure 25
PG-LQFP-144 (Plastic Green Thin Quad Flat Package)
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Packages”: http://www.infineon.com/packages
Dimensions in mm.
Data Sheet
105
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Package and Reliability
5.2
Thermal Considerations
When operating the XC228x in a system, the total heat generated on the chip must be
dissipated to the ambient environment to prevent overheating and resulting thermal
damages.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” is a measure for these parameters.
The power dissipation must be limited so the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
∆T = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
P
INT = VDDP × IDDP (see Table 14).
The static external power consumption caused by the output drivers is defined as
IOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
P
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and the switching frequencies.
If the total power dissipation determined for a given system configuration exceeds the
defined limit countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
106
V0.91, 2007-02
Draft Version
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Package and Reliability
5.3
Flash Memory Parameters
The data retention time of the XC228x’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Table 27
Flash Parameters (XC228x, 768 Kbytes)
Parameter
Symbol
Limit Values
Unit
Notes
Min.
Max.
Data retention time
tRET
20
–
years 103 erase/program
cycles
Flash Erase Endurance NER
15 × 103
–
cycles Dataretentiontime
5 years
Data Sheet
107
V0.91, 2007-02
Draft Version
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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