XDPS21071 [INFINEON]
Switching Controller,;
| 型号： | XDPS21071 |
| 厂家： | 
Infineon |
| 描述： | Switching Controller, 开关 |
| 文件： | 总54页 (文件大小：2165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XDPS21071
Forced Frequency Resonant Flyback controller
Based on FW: REV 1.0
Product Highlights
•
•
•
•
•
•
Integrated 600 V startup cell for fast startup and direct bus voltage sensing
Multi-mode operation with forced frequency resonant mode (FFR)
DCM operation guaranteed
Adaptive current limitation for variable Vout
Supports low no load input power to meet stringent regulatory standard
One pin UART interface for configuration
Features
Description
• Multi-mode operation with BM, DCM
• Configurable ZVS enabled line voltage
• ZVS gate drive signal for forced resonant mode
• Built-in soft-start
• Built-in protection modes
• Brown-in and brownout detection via integrated HV
startup cell
The XDPS21071 is a digital PWM controller for high density
adapter applications based on DCM flyback topology. A wide
feature set is provided in a DSO-12 package and requires
only a minimum of external components. An integrated
ASSP digital engine provides advanced algorithms for multi-
mode operation and protection features. A forced frequency
resonant operation support optimized high density adapter
• Pb-free lead plating; RoHS compliant
• Halogen-free according to IEC61249-2-21
system dimensioning. In addition
a
one-time-
programmable (OTP) unit is integrated to provide
a
Applications
selective set of configurable parameters, which can be
matched to a dedicated system design.
•
High density adapter/charger
Product Validation
•
Qualified for industrial applications according to the
relevant tests of JEDEC47/20/22
85 ... 264 VAC
VCC
ZCD
GD1
HV
GPIO
GD0
XDPS21071
CS
MFIO
GND
Figure 1
Typical application
Package
Marking
XDPS21071
FW Revision
REV 1.0
SP Ordering Code
PG-DSO-12-20
SP005355100
Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Revision 2.0
2019-10-30
Forced Frequency Resonant Flyback controller
Table of contents
Table of contents
Based on FW: REV 1.0 ...................................................................................................................... 1
Product Highlights.......................................................................................................................... 1
Features
1
Applications................................................................................................................................... 1
Product Validation.......................................................................................................................... 1
Description1
Table of contents............................................................................................................................ 2
1
2
3
Pin Configuration and Functionality ................................................................................ 4
Representative Block Diagram ........................................................................................ 5
Introduction.................................................................................................................. 6
4
4.1
Functional Description ................................................................................................... 7
Power supply management....................................................................................................................7
VCC capacitor charge-up and startup sequence...............................................................................7
Brown-in monitoring..........................................................................................................................8
Brown-out protection response ........................................................................................................9
During burst mode operation ...........................................................................................................9
Bang-bang mode during latched and auto-restart operation .......................................................10
During latched operation............................................................................................................11
During auto-restart operation ....................................................................................................11
Control features.....................................................................................................................................12
Reflected voltage sensing and Vcs offset calculation based on output voltage............................14
Output voltage sensing via ZCD pin ...........................................................................................15
Ringing suppression time ...........................................................................................................17
Vcs offset calculation based on output voltage sensed at ZCD pin ..........................................17
Vbulk voltage measurement via HV startup cell .............................................................................18
Propagation delay compensation (PDC).........................................................................................18
Soft-start...........................................................................................................................................20
Leading edge blanking (LEB) at CS pin............................................................................................20
Spike blanking at CS pin for 2nd level over-current detection (OCP2) ..........................................21
Gate driver output GD0 and GD1 .....................................................................................................21
Multi-mode operation......................................................................................................................22
Frequency law setting for XDPS21071........................................................................................24
Frequency jittering...........................................................................................................................25
Burst mode operation......................................................................................................................26
Burst mode entry ........................................................................................................................27
Burst operation ...........................................................................................................................27
Burst mode exit ................................................................................................................................28
Forced frequency resonant (FFR) mode operation.........................................................................28
UART function at GPIO pin...............................................................................................................30
Protection features ...............................................................................................................................30
Auto-Restart Mode (ARM).................................................................................................................31
Latch Mode (LM)...............................................................................................................................31
VCC Under-Voltage lockout (UVOFF) ...............................................................................................31
Brown-In Protection (BIP)................................................................................................................31
Brown-Out Protection (BOP) ...........................................................................................................32
Over-Current Protection level 1 (OCP1) ..........................................................................................32
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.5.1
4.1.5.2
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.8.1
4.2.9
4.2.10
4.2.10.1
4.2.10.2
4.2.11
4.2.12
4.2.13
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Data Sheet
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Table of contents
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
Over-Current Protection level 2 (OCP2) ..........................................................................................32
High input at CS pin (CShigh) ..........................................................................................................32
MFIO pin high (MFIOH) .....................................................................................................................32
Internal over-temperature detection (IntOTP) ...............................................................................32
Primary side output Over-Voltage Protection (VoutOVP)...............................................................33
Over load power protection.............................................................................................................33
CS pin short protection....................................................................................................................33
5
Configuration...............................................................................................................34
Overview of configurable parameters using .dp Vision .......................................................................34
Overview of configurable parameters and functions ..........................................................................34
Configurable parameters and functions .........................................................................................34
5.1
5.2
5.2.1
6
Electrical Characteristics...............................................................................................36
Definitions .............................................................................................................................................36
Absolute Maximum Ratings ..................................................................................................................36
Package Characteristics........................................................................................................................37
Operating Range....................................................................................................................................38
Characteristics.......................................................................................................................................39
6.1
6.2
6.3
6.4
6.5
7
7.1
7.2
Package Information.....................................................................................................48
Outline dimensions ...............................................................................................................................48
Footprint and packing...........................................................................................................................49
8
Marking .......................................................................................................................50
9
9.1
Appendix .....................................................................................................................51
Minimum required capacitive load at GD0 and GD1 pin......................................................................51
10
References...................................................................................................................52
Revision history.............................................................................................................................53
Data Sheet
3
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Pin Configuration and Functionality
1
Pin Configuration and Functionality
The pin configuration is shown in Figure 2 and the functions are described in Table 1.
1
2
3
4
12
11
10
9
ZCD
MFIO
GPIO
CS
GND
VCC
GD0
GD1
5
6
8
7
HV
HV
HV
HV
PG-DSO-12-20
Figure 2
Pin Configuration of XDPS21071
Pin Definitions and Functions
Table 1
Symbol
ZCD
Pin
Type
Function
1
I
Zero Crossing Detection
ZCD pin is connected to an auxiliary winding for zero crossing detection and positive
pin voltage measurement.
2
I
Multi-Functional Input Output
MFIO pin is connected to an optocoupler that provides an amplified error signal for
the PWM mode operation.
MFIO
GPIO
CS
3
IO
I
Digital General Purpose Input Output
GPIO pin provides an UART interface until brown-in. It is switched to weak
pull down mode and disabled UART function during normal operation.
Current Sense
4
CS pin is connected via a resistor in series to an external shunt resistor and
the source of the power MOSFET.
HV
5, 6, 7, 8
I
High Voltage Input
HV pin is connected to the rectified bulk voltage. An internally connected 600
V HV startup-cell is used for initial VCC charge. Furthermore brown-in and
brownout detection is provided.
GD1
9
I
FFR Signal Gate Driver Output
GD1 pin provides a gate driver pulse signal to initiate the forced frequency
resonant mode operation.
GD0
VCC
GND
10
11
12
O
I
Gate Driver Output
Output for directly driving the main power MOSFET.
Positive Voltage Supply
IC power supply.
O
Power and Signal Ground
Data Sheet
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Representative Block Diagram
2
Representative Block Diagram
Figure 3 shows a simplified top level block diagram of the IC functionality.
HV
XDPS21071
HV Startup-cell
Bang-Bang Ctrl
VVCCBBoff = 20.5 V
Closed/Open
Startup-Cell
Driver
VVCCBBonAR/LM = 9 V
Vbulk Brown-out
Protection
IHVBO = 0.443 mA
QM
D1
Vbulk
Vbulk Brown-in
measurement
Protection
Overtemperature
Detection
TJOTP = 130 °C
IHVBI = 1.15 mA
RM
&
VCC Brown-in
VCC
Protection
VVCCBI = 9.1 V
Protection
Modes
HW Reset
UVLO
VVCCon = 20.5 V
Auto Restart
Mode
Power
Management
VVCCoffx = 7.2 V / 9.6 V
Vout OV
Protection
Latch
Mode
Vout reflected Voltage
Measurement
ZCD
1 k ꢀ
VZCDOVP = 2.75 V
Soft-Start
Open Loop Timer
tMFIOH = 31.3 ms
Frequency clamp
Gate Driver
FFR Mode
With ZVS Pulse
Generation
PWM
Logic
Frequency Law
fSW
GD0
C2
VCSPK
VMFIO
VMFIOH = 2.41 V
PDC
VVDDP = 3.3 V
VMFIO
Gate Driver
RMFIOPU
GD1
Burst Mode Function
Vcs_offset
MFIO
C3
VMFIOBMEX1
BM Exit
C5
VMFIOBMWK
on-phase
off-phase
BM 2-point
Regulation
BM Ctrl
C6
VMFIOBMPA
C7
BM Entry
VMFIOBMEN
Cycle by Cycle Peak Current Ctrl
OCP1
CS
tCSLEB
VCSPK
10k ꢀ
1 k ꢀ
1 pF
Auto Restart
Input Detection
2nd Level Overcurrent Detection
OCP2
tCSOCP2BL
VCSOCP2 = 0.8 V
VVDDP = 3.3 V
IGPIOLPU
UART
Communication
Parameter
Configuration
GPIO
Figure 3
Representative Block Diagram of XDPS21071
Data Sheet
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Introduction
3
Introduction
The XDPS21071 is a digital AC/DC current-mode controller for high density adapter applications. The IC provides a
configurable multi-mode operation controlled by the feedback signal from the secondary side control loop. The multi-mode
operation supports different operation modes like forced frequency resonant control (see chapter 4.2.12) or burst mode,
frequency reduction mode depending on line and load conditions. With supporting those modes high power density designs
can be dressed in a very flexible manner.
An embedded application specific digital core provides advanced algorithms for the multi-mode operation and a variety of
protection features. Special analog and mixed-signal peripherals are integrated to support the requirements for low stand-
by power.
The IC supports highest design flexibility in the application by means of an advanced set of configurable parameters and
state machines, which supports very dedicated system dimensioning. The configuration can be done via a single pin UART
interface at GPIO pin that supports in-circuit configuration. Chapter 5 contains the parameter default configuration setting
for XDPS21071 and the correlated specific firmware version. Furthermore, it provides a mapping table for the defined FW
symbols and the correlated data sheet parameters. Each listed parameter is specified in the electrical characteristics
Chapter 6.
The following functional description in Chapter 4 is based on the default parameter setting in the configuration Chapter 5.
Chapter 7.1 provides information about the package outline and dimensions.
An appendix Chapter 9 provides additional information about specific electrical characteristics or test conditions.
The reference Chapter 10 provides an overview about correlated documents.
Data Sheet
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Functional Description
4
Functional Description
The functional description gives an overview about the integrated functions and features and their relationship. The
mentioned parameters and equations are based on typical values at TA = 25 °C. The correlated minimal and maximal values
are shown in the electrical characteristics in Chapter 6.
The functional description is grouped in following sections:
Power supply management (Chapter 4.1)
Control features (Chapter 4.2)
Protection features (Chapter 4.3)
4.1
Power supply management
The power supply management ensures a reliable and robust IC operation. Depending on the operation mode of the control
IC, the power supply management unit runs in different ways for VCC supply and for brown-in monitoring, which are
described in the sequel:
•
•
•
•
•
•
VCC capacitor charge-up and startup sequence (see Chapter 4.1.1)
Brown-in monitoring (Chapter 4.1.2)
Brown-out protection response (Chapter 4.1.3)
During burst mode (QBM) operation (Chapter 4.1.4)
Bang-bang mode during latch mode (LM) operation (Chapter 4.1.5.1 )
Bang-bang mode during auto-restart mode (ARM) operation (Chapter 4.1.5.2)
4.1.1
VCC capacitor charge-up and startup sequence
There are two main functions supported at HV pin by a resistor RHV connected to the bulk capacitor (see Figure 5). They are
the VCC capacitor charge-up, and the bulk voltage monitoring (see Chapter 4.1.2).
At beginning of a cold startup, the depletion startup cell is on. Once the AC line voltage is applied and charging the bulk
capacitor, a current flows through the external resistor RHV into HV pin. Via the integrated diode D1, that current may charge
up the external VCC capacitor (see Figure 5). Once VCC voltage exceeds the threshold VVCCon = 20.5 V, the startup cell is turned
off, the control IC is enabled and the firmware boot sequence follows which takes about 1.2 ms. Both bulk voltage brown-in
and VCC brown-in condition (see Chapter 4.3.4) are checked continuously. Once they both are above the brown-in level,
respectively, the first GD0 pulse according to the soft-start control will be generated earliest after the 1.2 ms boot sequence
time. The voltage VVCC drops until the supply via the auxiliary winding (VVCCSS) takes over the VCC supply (see Figure 4). For a
proper system startup and operation, the supply voltage VVCC must be always above the VCC off-threshold VVCCoff=7.2 V (see
Chapter 4.3.3).
Data Sheet
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Functional Description
VVCC(t)
Initial startup and normal operation
VVCCon = 20.5 V
VCC brown-in window
VVCCSS
VVCCBI = 9.1 V
VVCCoffOP = 7.2 V
VCC self supply takes over
t
t
VHV(t)
VVACpeak
ca. 1.2ms internal boot sequence
VAC brown-in condition fulfilled
IVCC(t)
Start of GD0 switching
IVCCop
IVCCop1 = 7.5 mA
IVCCUVOFF = 30 µA
t
TYPICAL STARTUP SEQUENCE
Figure 4
Typical startup sequence
4.1.2
Brown-in monitoring
Once the IC is activated, brown-in monitoring is enabled for input brown-in protection (see Chapter 4.3.4) by measuring
the current at HV pin through the internal shunt resistor RM (see Chapter 4.2.2). If the input brown-in is not detected before
VCC falls below VVCCBI, the startup cell measurement unit remains enabled until VCC falls down to VVCCoff
.
Data Sheet
8
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Forced Frequency Resonant Flyback controller
Functional Description
VBULK
VAC = 85 ... 264
CBulk
Vrms
RHV = 100kW
CVCC
VCC
HV
HV Startup-
cell
Startup-Cell
Driver
Closed/Open
D1
Brown-in &
Brown-out
Protection
QM
&
I
I
HVBI = 1.15 mA
HVBO = 0.442mA
PWM
Logic
RM
VCC Brown-in
Protection
Power Supply
Management
VVCCBI = 9.1 V
UVLO
VVCCon = 20.5 V
HW Reset
VVCCoffx = 7.2 V / 9.6 V
Figure 5
High voltage brown-in sensing and VCC startup at HV pin
4.1.3
Brown-out protection response
In case of brown-out (see Chapter 4.3.5), the IC stops gate driver switching and stays active. At the same time, the VCC turn-
off threshold is switched over from VVCCoff to the threshold VVCCoffBO = 9.6 V. The threshold VVCCoffBO is higher than the threshold
VVCCoff, which supports an earlier system restart than using the threshold VVCCoff
.
4.1.4
During burst mode operation
After the control IC enters quiet burst mode, the IC enters repeatedly a sleep mode, in which the IC current consumption is
reduced to IVCCquBM2 = 460 µA. Waking up from and entering this sleep mode (pause) is controlled by the feedback voltage at
MFIO pin VMFIO via the internal comparators C5 and C6 (see Figure 6 and Chapter 4.2.910).
Data Sheet
9
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Forced Frequency Resonant Flyback controller
Functional Description
MFIO
C5
burst-on
VMFIOBMWK
BM 2-point
Regulation
Power
Management
BM Ctrl
burst-off
C6
VMFIOBMPA
Figure 6
Burst mode control
For the system dimensioning, it should be ensured that the voltage VVCC should be always well above the
threshold VVCCoff, including the burst-off phase. Figure 7 shows a typical burst mode operation signal for VCC and
correlated current consumption.
VVCC(t)
burst-on phase
VVCCSS
VVCCoff = 7.2 V
t
burst-off phase
VMFIO(t)
VMFIOBMWK = 1.6 V
VMFIOBMPA
t
VGD0(t)
t
IVCC(t)
IVCCop
IVCCquBM2 = 460 µA
t
Figure 7
Burst operation
4.1.5
Bang-bang mode during latched and auto-restart operation
The bang-bang mode supports an IC operation without external VCC supply during the latched and auto-restart operation.
It directly controls the HV startup cell depending on the set bang-bang mode turn-on threshold VVCCBBon of the corresponding
auto-restart and latch mode (see Figure 8). In latch mode, the HV startup cell switch-on threshold is set to VVCCBBon = 9 V (see
Chapter 4.1.5.1 and Chapter 4.1.5.2). In auto-restart mode, there is also an additional stand-by timer active that switches on
the HV startup cell in a fixed time period of 500ms scheme to keep the VCC all the time at a high level above the brown-in
threshold VVCCBI = 9.1 V. Then a restart can take place without going through an additional VCC brown-in cycle. Due to the low
current consumption during the auto-restart break time, the startup cell is always turned on by the 500 ms timer.
Protection Modes
HV
HV Startup-cell
Auto Restart
Mode
Bang-Bang Ctrl
Closed/Open
Startup-Cell
Driver
VVCCBBoff = 20.5 V
Latch
Mode
VVCCBBonAR/LM = 9 V
D1
Power
Management
VCC
Figure 8
Bang-bang mode control of HV startup-cell
Data Sheet
10
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Forced Frequency Resonant Flyback controller
Functional Description
4.1.5.1
During latched operation
If latch mode is entered (see Chapter 4.3.2), the IC stops gate switching and the VCC current consumption is reduced to
IVCCquLM = 150 µA. The enabled bang-bang mode ensures that the IC is kept alive by keeping the voltage at VCC pin above the
threshold VVCCoff = 7.2 V (see Figure 9). A reset of the latch mode takes place only after the VCC drops below the VVCCoff threshold.
VVCC(t)
Latch mode operation
VVCCBBoff = 20.5 V
VVCCSS
VVCCBBonLM = 9 V
VVCCoff = 7.2 V
t
Reset of latch mode due to low VAC
VHV(t)
VVACpeak
t
IVCC(t)
IVCCop
IVCCquLM = 150 µA
IVCCUVOFF = 30 µA
t
Figure 9
Latch mode operation
4.1.5.2
During auto-restart operation
Once auto-restart mode is entered (see Chapter 4.3.1), the IC stops GD0 switching, the VCC current consumption is reduced
to IVCCquAR = 160 µA, and a stand-by timer with 500 ms (tBBoffAR) period is activated which turns on the HV startup cell
periodically, to charge up the VCC capacitor. Once the voltage at VCC pin exceeds the switch-off threshold VVCCBBoff = 20.5 V,
the startup cell is turned off (see Figure 10). This is bang-bang mode operation for the VCC management during the auto-
restart break time. In this way, the VCC voltage is kept at a level well above the VCC brown-in threshold to ensure enough
energy stored in the VCC capacitor for the coming restart of the system, that is initiated after the auto-restart break time
tAR = 3 s. Then after an additional time ∆t = ε, the gate driver switching is activated with a soft-start sequence. Here the
additional time ε depends on the VCC capacitor charge-up time which is related to the VCC capacitance and the voltage at
HV pin.
Data Sheet
11
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Forced Frequency Resonant Flyback controller
Functional Description
VVCC(t)
Auto-restart mode operation
VVCCBBoff = 20.5 V
VVCCSS
VVCCBI = 9.1 V
VVCCBBonAR = 9 V
VVCCoff = 7.2 V
t
t
tBBoffAR = 500 ms
VHV(t)
VVACpeak
D
t = e
IVCC(t)
IVCCop
IVCCop1 = 7.5 mA
IVCCquAR = 160 µA
t
t
VGD0(t)
VGD0H = 10.5 V
tAR = 3s
Figure 10 Auto-restart mode operation
4.2
Control features
The XDPS21071 provides peak current control assisted by the features listed in Table 2. A simplified block diagram
representing the controller features is shown in Figure 11.
Data Sheet
12
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Forced Frequency Resonant Flyback controller
Functional Description
tCSOCP2BL
CS
VCSOCP2
CLEAR
VCS
GD0
+
&
FF
Cold Start,
BM Wake-Up,
Autorestart
SET
&
+
stop GD0
VCSOCP1
Soft-Start
Control
CLEAR
VCSSS
&
M
I
N
VVDDP
FF
Multi-Mode
Control
frequency law,
burst mode control
MFIO
HV
tCSLEB
SET
VMFIO
IHV
VBulk
Measurment
Propagation
Delay
Compensation
tZCDRS
Vcs_offset
start GD0
Start Request
Generator
Vout
Measurement
ZCD
fSW
FFR ZVS
PWM
GD1
Generator
ZCD
MULTIMODE_OVERVIEW_DIGITAL
Figure 11 Block Diagram of PWM Control
Table 2 gives an overview about the controller features that are described in the mentioned chapters.
Table 2
Controller Features
Reflected voltage sensing and zero crossing detection at auxiliary winding
Vbulk voltage measurement via HV startup cell
Propagation delay compensation (PDC)
Soft-start
Chapter 4.2.1
Chapter 4.2.2
Chapter 4.2.3
Chapter 4.2.4
Chapter 4.2.5
Chapter 4.2.6
Chapter 4.2.7
Chapter 4.2.8
Chapter 4.2.9
Chapter 4.2.12
Chapter 4.2.13
Leading edge blanking (LEB) time at CS pin
Spike blanking at CS pin for 2nd level over-current detection
Gate driver output GD0 and GD1
Multi-mode operation
Burst mode (QBM) operation
Forced frequency resonant (FFR) mode operation
UART function at GPIO pin
Data Sheet
13
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Forced Frequency Resonant Flyback controller
Functional Description
4.2.1
Reflected voltage sensing and Vcs offset calculation based on
output voltage
The IC provides output voltage detection by means of measuring the reflected voltage at the auxiliary winding VAux at the
primary side of the transformer via ZCD pin and an external resistive voltage divider. The voltage signal VAux contains the
information of the flyback output voltage, VOut, at the secondary side.
The ZCD pin related circuit is shown in Figure 12. Figure 13 shows a typical voltage waveform of the drain voltage VDrain and
the related auxiliary winding voltage VAux. The sensed output voltage is used for over-voltage protection (see Chapter 4.3.11).
Following topics are described in the sequel:
•
•
Output voltage sensing via ZCD pin (Chapter 4.2.1.1)
Vcs offset with sensed Vo at ZCD pin (Chapter 4.2.1.3)
vPri
vSec
VOut
VBulk
vDrain
RZCDH
iZCD
vZCD
vAux
ZCD
GND
RZCDL
vZVS
VOLTAGE_SENSING_OVERVIEW
Figure 12 Functionality at ZCD pin
Data Sheet
14
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Forced Frequency Resonant Flyback controller
Functional Description
vDrain(t)
NPri / NSec × vSec
VBulk
0
t
Free-wheeling phase
Oscillation phase
vAux(t)
NAux / NSec × vSec
0
t
NAux / NPri × VBulk
1 1 1 1
4 4 4 4
tOn
tf
tOsc
tOff
iMag(t)
t
VOLTAGE_SENSING_SIGNALS
Figure 13 Auxiliary voltage and magnetization current waveforms for standard discontinuous
conduction mode operation
4.2.1.1
Output voltage sensing via ZCD pin
Output voltage is sensed at a fixed point of time during the free-wheeling phase. The free-wheeling phase begins when the
gate driver is switched off and ends when the secondary side demagnetization current becomes zero. During free-wheeling
phase the VCC capacitor of the IC, the output stage and the additional ZVS capacitor at ZVS winding for introducing a forced
resonant cycle (see Chapter 4.2.12) are supplied. As soon as VCC capacitor is charged, the auxiliary voltage is a function of
secondary side voltage.
푵
푨푼푿
푽푨푼푿
=
∙ 푽푺풆풄
( 1 )
푵
푺풆풄
Figure 14 shows the schematic related to secondary side voltage sensing and the equivalent network.
Data Sheet
15
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Forced Frequency Resonant Flyback controller
Functional Description
NSec:NAux
RZCDH
iZCD=0
vZCD>0
vSec(t)
vAux(t)
ZCD
GND
RZCDL
ZCD
+
vZCDSEC(vSec
)
GND
VOLTAGE_SENSING_ZCDSH
Figure 14 Secondary Side Voltage Sensing
No current clamping applies during the free-wheeling time and the voltage at ZCD pin is given by
푽
푨푼푿
푽풁푪푫푺푬푪(푽푺풆풄) = 푹풁푪푫∙
(
)
( 2 )
푹
풁푪푫푯
RZCD is the internal resistance of VZCDSEC (VSec)and is the equivalent parallel resistance of RZCDH and RZCDL. The related waveforms
are presented in Figure 15. After the primary side gate driver is turned off, the auxiliary voltage goes from its negative level
to positive. After a ringing phase, the positive level is given by the output voltage plus the secondary side diode voltage drop.
During the free-wheeling phase the secondary side diode operates in the linear region until the demagnetization current
becomes very small. This linear relationship can be described as a resistor RDSonSec, resulting in a falling slope according to
RDSonSec·iLSec(t). The secondary side current iLSec(t) decreases with a slope given by the output voltage and the transformer
secondary side inductance. Hence the resulting auxiliary winding voltage is more or less constant until the secondary side
current becomes zero. The reflected voltage at auxiliary winding is sampled at the end of the ringing suppression time (see
Chapter 4.2.1.2). The measured voltage VZCDSEC includes the output voltage level and a superimposed offset ∆VZCDOFFSET that is
depending on the secondary side chosen rectification approach and the associated component dimensioning.
To ensure an accurate measurement of the reflected output voltage, the system dimensioning must provide a free-wheeling
phase that only finishes after the ringing suppression time tZCDRS
.
Furthermore following effects can influence the output voltage sensing if not properly considered in system dimensioning:
•
•
VCC and ZVS capacitor charging
Voltage drop on secondary side at the free-wheeling diode or the secondary side switch
The VCC and ZVS capacitors need to be charged up before the ringing suppression time tZCDRS ends. The superimposed
voltage offset ∆VZCDOFFSET at sample time point due to secondary side rectification approach needs to be considered either by
the dimensioning of the ZCD resistor divider or the internal overvoltage threshold setting VZCDOVP (see Chapter 4.3.11).
Data Sheet
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Functional Description
tGD0offZC
vGD0(t)
tf
tOsc/4
tZCDRS
t
vZCD(t)
Voltage sampling
DVZCDOFFSET
VZCDSEC(VSec
)
VZCDVO(VOut
)
VZCDTHR
t
VZCDclp
Ringing
suppression
VOLTAGE_SENSING_SIGNALS_ZCDSH
Figure 15 Output Voltage Sensing Signals
4.2.1.2
Ringing suppression time
To prevent erroneous ZCD events due to primary side gate driver turn off ringing, a ringing suppression time tZCDRS = 1.9µs
applies for the zero-crossing events. During this time no zero-crossing is considered.
4.2.1.3
Vcs offset calculation based on output voltage sensed at ZCD pin
To limit the output current at different output voltage, a linear scaled Vcs offset is inserted to the peak current command.
This offset will be minused from the current command mapping from the frequency law curve.
It is an inverse of the output voltage based on positive ZCD winding voltage. Figure 16 shows when the Vzcd is at
Vzcd_zero_point, the Vcs offset is zero. While Vzcd voltage is at minimum level, the Vcs offset is maximum. The Vcs offset level
depends on the slew rate of Kvcs_offset and the starting point of Vzcd. The equation is as below:
푽풄풔풐풇풇풔풆풕 = 푲풗풄풔풐풇풇풔풆풕 ∗ (푽풛풄풅 − 푽풛풄풅_풛풆풓풐_풑풐풊풏풕)/ퟔퟓퟓퟑퟔ
( 3 )
All the number in above equation is decimal digital value.
At ZCD pin, the sensed voltage will minus 1.2V offset first, then feed into an ADC channel to get the sense the voltage. Also
due to the ADC input voltage range is 1.2-2.8V, so any ZCD voltage out of this range is ignored by the IC and ADC converter
value will be saturated at its min(0) and max value(255).
Below is the example on how to set the value,
Vzcd_zero_point is the voltage level without compensation, here we choose Vzcd=1.41V, the digital value of Vzcd_zero_point_dig=(1.41-
1.2)*1.5/2.4*255=148, Kvcsoffset=28000, for Vzcd=1.2V, the digital value of it will be
Vzcd_dig=(1.2-1.2)*1.5/2.4*256=0, so Vcsoffset_dig=28000*(0-79)/65536=34, its analog value will be 34/255*0.6=80mV.
If system parameters like transformer turns ratio, ZCD pin voltage divider is known, then the corresponding output voltage
can be calculated. E.g. Naux=2, Nsec=2, RzcdH is 39kohm, RzcdL is 5.6kohm.
푵
풔풆풄
푽풐 = 푽풛풄풅
∗
∗ (푹풛풄풅푳 + 푹풛풄풅푯)/푹풛풄풅푳
( 4 )
푵
풂풖풙
Data Sheet
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Functional Description
So for Vzcd=1.41V, Vo will be 1.41*2/2*(39+5.6)/5.6=11.23V assuming transformer coupling is 1.
For Vzcd=1.2V, Vo will be 1.2*2/2*(39+5.6)/5.6=9.56V.
This means that when output voltage is above 11.23V, there is no Vcs offset compensation, below 9.56V the compensation
is clamped at 80mV as calculated above.
Vzcd
Vzcd_zero_point
Kvcs_offset
Vzcd_LowV
Vcs offset
Vcs_offset
VCSOFFSET
Figure 16 Vcs_offset calculation
4.2.2
Vbulk voltage measurement via HV startup cell
The VBulk voltage is measured via the HV pin that is connected at the bulk capacitor node. The current IHV is sampled in the IC
and processed for the following functions:
•
•
•
Brown-in protection ( Chapter 4.3.4)
Brown-out protection (Chapter 4.3.5),
Propagation delay compensation (Chapter 4.2.3),
In all these functions, the current IHV represents the bulk voltage.
4.2.3
Propagation delay compensation (PDC)
Due to the gate driver turn-off propagation delay tPD, the level VCSOCP1 set by the OCP1 comparator will not directly control
the inductor peak current, ILPk
.
Without propagation delay, the peak current would be given by ILPk = RCS-1·VCSOCP1. However, due to the propagation delay,
the OCP1 level is exceeded by
푹푪푺 ∙ 푰푳풑풌 = 푽푪푺푶푪푷ퟏ + 푽푪푺푷푫(푽푩풖풍풌
)
( 5 )
where the propagation delay overshoot VCSPD(VBulk) is
푹
푪푺
푽푪푺푷푫(푽푩풖풍풌) =
∙ 풕푷푫 ∙ 푽푩풖풍풌
( 6 )
푳
푷풓풊
In Figure 17 related example waveforms are presented.
Data Sheet
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Functional Description
vGD0(t)
vGD0(t)
t
t
t
t
vDrain(t)
vDrain(t)
VBulkHL
VBulkLL
vCS(t)
vCS(t)
tPD
tPD
tCS
RCSILpk
(t)
RCSILpk(t)
tCS
dvCS/dt
dvCS/dt
t
t
MULTIMODE_PDC
Figure 17 Propagation Delay and Propagation Delay Compensation
On the left side, the bulk voltage is low, the slope of inductor current and of the CS voltage are low, too. When the CS voltage
reaches the OCP1 level, the gate driver turns off and the inductor current reaches its peak after the turn off propagation
delay tPD. The turn off propagation delay tPD includes the delay tCS of the filter capacitor connected to CS pin and the resistor
connected between shunt resistor and CS pin (see Typical Application Figure). The overshoot of the inductor current due to
propagation delay is small due to the small slope
풅푽
푹
∙푽
푪푺
푪푺 푩풖풍풌
=
( 7 )
풅풕
푳
풑
The right side of Figure 17 shows the same operating waveforms for a higher bulk voltage. In this case, the OCP1 comparator
limit needs to be less than on the left side to reach the same inductor peak current. Although the propagation delay remains
the same, the slope as well as the overshoot due to propagation delay is larger.
The XDPS21071 controller is defined to measure the HV current IHV representing the bulk voltage VBulk. The OCP1 comparator
limit is adjusted depending on the measured bulk voltage so that the real peak current due to the propagation delay is
compensated. For this HV pin needs to be connected to VBulk
.
Consequently, any CS peak parameter VCSx is specified in the electrical characteristics (Chapter 6.5) for a low-line use case
(VCSxLL) and for a high-line use case (VCSxHL).
Low-Line Use Case (LL)
•
•
IHVLL = 70 µA as for VBulk = 72 V, RHV = 100 kΩ
(dvCS /dt)LL = 96 mV/µs as for VBulk = 72 V, LPri = 220 µH, RCS = 0.294 Ω
High-Line Use Case (HL)
•
•
IHVHL = 370 µA as for VBulk = 372 V, RHV = 100 kΩ
(dvCS /dt)HL = 497 mV/µs as for VBulk = 372 V, LPri = 220 µH, RCS = 0.294 Ω
These use cases set the corners of the propagation delay compensation which operates in a linear manner so that the typical
OCP1 threshold for any IHV is given by
(
)
ꢀ푽
푽
푰
푽
ꢀ푽
푪푺풙 푯푽
푪푺풙푳푳
푪푺풙푯푳 푪푺풙푳푳
=
( 8 )
푰
ꢀ푰
푰
ꢀ푰
푯푽 푯푽푳푳
푯푽푯푳 푯푽푳푳
Data Sheet
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Functional Description
4.2.4
Soft-start
The IC control provides a soft-start during initial startup and auto-restart cycles. The soft-start slew rate is defined by the
step ∆VCSS = 2.5 mV taking place every time step of tBase1 = 52.14 µs. Furthermore, the peak current start level is determined
by the parameter VCSSS
.
The soft-start phase is latest finished after VCS has ramped up to the maximum level of VCSmax (see Figure 18).
The total soft-start time tSSmax is therefore based on the following equation:
푽
ꢀ푽
푪푺풎풂풙
푪푺푺푺
풕푺푺풎풂풙 = 풕푩풂풔풆ퟏ
∙
( 9 )
∆푽
푪푺푺
The associated ramped up peak current limitation is determined by internal digital numbers, which are not depending on
the propagation delay during peak current limitation process.
VCS(t)
tSSmax
VCSmax
tBase1
DVCSS
VCSSS
t
Figure 18 Soft-start timing
The internal soft-start phase is finished once the voltage level at MFIO pin is getting lower than 2.42 V. Then the setting for
CS limitation is determined by the feedback signal at MFIO pin via the frequency law (see Chapter 4.2.8.1).
4.2.5
Leading edge blanking (LEB) at CS pin
A digital leading edge blanking filter with tCSLEB = 269 ns (see Chapter 5) is integrated in the OCP1 peak current control path
to prevent the current limitation process from distortions, caused by the leading edge spike at the switch-on of the power
MOSFET (see Figure 19). The LEB applies only for the OCP1 comparator (see Figure 3) that is used for cycle-by-cycle peak
current limitation. The LEB needs also to ensure a monotonous peak current control without being impacted by ringing
taking place directly after the leading edge spike.
VGD0(t)
t
VCS(t)
tCSLEB
VCSOCP1
t
Figure 19 Leading edge blanking
Data Sheet
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Functional Description
4.2.6
Spike blanking at CS pin for 2nd level over-current detection
(OCP2)
A further comparator OCP2 is implemented at CS pin (see Figure 3) to detect dangerous current levels (see Chapter 5), which
could occur if one or more transformer windings are shorted or if the secondary side diode is shorted. To avoid an accidental
trigger by exceeding this 2nd level over-current protection threshold VCSOCP2 = 0.8 V, a spike blanking time tCSOCP2BL = 616.2 ns
(see Chapter 5) is implemented in the output path of the OCP2 comparator.
4.2.7
Gate driver output GD0 and GD1
The gate driver GD0 and GD1 are of the same type. The GD0 is used for controlling the main MOSFET connected to the primary
main inductance of the flyback transformer. The GD1 is used for controlling the FFR mode (see Chapter 4.2.8) by driving the
dedicated MOSFET that is connected to the ZVS winding at the flyback transformer.
The gate driver output stages consist of a regulated current source connected to VCC pin and a MOSFET switch connected
to GND (see Figure 20 and Figure 21). The peak source current at GDx is set to IGDxHPKSRC = -118 mA. The MOSFET switch
provides a discharge path for the main power MOSFET with a sink capability of RGDxLSNK ≤ 6.5 Ω.
The controlled source current determines together with the gate-source capacitance CGS and the gate-drain capacitance CGD
of the external power MOSFET the rising slope during turn-on phase (see Figure 22). The gate driver state control ensures
that the charged gate driver output voltage is clamped at the level VGDxH = 10.5 V.
The external gate resistor RGDx is therefore only meant for adjusting the peak sink current and the corresponding gate voltage
falling slope during the turn-off phase. Here the turn-on behavior is mainly dominated by the controlled limited current
source IGDxHPKSRC as the size of the external gate resistor is mainly limiting the higher peak sink current at GDx pin. When
dimensioning the serial gate resistor RGDx, also a minimum load capacitance needs to be considered after RGDx (see Chapter
9.1), which needs to be provided by the corresponding gate-source capacitance CGS of the external power MOSFET. This
ensures a smooth and stable settling of the voltage level VGDxH at the end of the turn-on phase.
Primary main
inductance
VCC
VCC
Power
MOSFET
VD
Source current
control
IGD0HPKSRC
Q1
CGD
CGS
CS
Gate driver
state control
RGD0
Flyback
ctrl
GD0
GND
VGD0H
RGD0LSNK
RCS
Figure 20 GD0 output stage structure
Data Sheet
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Functional Description
ZVS-winding
VCC
VCC
Power
MOSFET
VD
Source current
control
IGD1HPKSRC
Q2
CGD
Gate driver
state control
RGD1
FFR mode
pulse control
GD1
CGS
VGD1H
RGD1LSNK
GND
Figure 21 GD1 output stage structure
VGDx(t)
turn-on phase
VGDxH = 10.5 V
dVGDx/dt is determined
by IGDxHPKSRC and CGS
The turn-off phase is determined by
RGDx, RGDxLSNK, CGS, CGD and VD
Miller plateau is determined by
IGDxHPKSRC, CGD and VD
t
tGDxon
Figure 22 Gate drive output
4.2.8
Multi-mode operation
The multi-mode operation consists of two different operation modes that are controlled by the feedback voltage signal at
MFIO pin (see Table 3).
Table 3
Overview multi-modes
Symbol
BM
Operation Mode
Description
Chapter 4.2.9
Chapter 4.2.12
Burst mode
FFR
Forced frequency resonant mode during BM and DCMx operation
The configurable multi-mode operation depends on the inductance design, switching frequency, load condition and the
bulk voltage VBulk. It is characterized by the frequency scheme and peak current correlation shown in Figure 23. The peak
current limit VCSPK (y-axis) and the frequency limits are set according to the input signal at MFIO pin. The peak current limits
for VCSPK are shown for the low and high-line use case (see Chapter 4.2.3), which consider the propagation delay
compensation (PDC). The border for entering the burst mode (BM) is determined by the setpoint D. The actual peak current
and the actual switching frequency areas follow:
Data Sheet
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Functional Description
•
in DCM1, DCM2 and DCM3 operation, the peak current and the switching frequency are directly given by the curve A-B-
C-D.
•
•
•
in DCM1 the peak current changes with the voltage VMFIO and the switching frequency is fixed.
in DCM2 the peak current is fixed, and the switching frequency changes with VMFIO
.
in DCM3 the peak current changes with the voltage VMFIO and the switching frequency is fixed until CRM operation is
taking place. The start of CRM cycles is depending on VBulk. The frequency in DCM3 is configurable. The highest
frequency is 139.4 kHz.
•
the multi-mode controller selects the operating mode (BM, DCM1, DCM2, DCM3 with FFRZVS or CRM)
CRM switching cycles occur in DCM3 when the Vbulk voltage exceeds a lower Vbulk voltage level and the remaining off-time
is not sufficient to fully demagnetize the flyback transformer. In this mode no zero crossing is detected before the end of the
switching period determined, however IC gate is only allowed when zero crossing is detected. In such condition, IC will wait
the demagnetization finshes until the first zero crossing comes, once zero crossing is detected, IC will allow gate on. The fix
frequency operation will be bypassed here and frequency will be reduced and IC will switch at valley.
The following Figure 23 shows an example of using all possible multi-mode operation phases that are determined by the
corresponding setpoints A, B, C and D. The specific frequency law setting for XDPS21071 based on the FW: REV 1.0 is shown
in Chapter 4.2.8.1. Setpoints A and B can change from lowest switching frequency (burst frequency) e.g. 30 kHz to maximum
switching frequency 139.4 kHz. Setpoint B and C are also configurable, i.e VmfioC, VmfioB, VcsC are also configurable, so the
middle to light load efficiency can be optimized for different combination of frequency and peak current.
There is a special condition to limit the maximum frequency, when the bulk voltage is higher than Vbulk_high=200V and ZCD pin
voltage is lower than Vzcd_low=1.30V, the frequency will be clamped to fclamp which is a configurable based on different system
design, the default value is 105 kHz. When the bulk voltage is less than 200V and zcd pin voltage is higher than 1.47V, the
fclamp will be removed. By lower the frequency and work in DCM, switching loss can be reduced at high line and thus
increase efficiency.
Data Sheet
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Functional Description
fSW(VMFIO
)
B
A
fSWmax
Freq clamp at
special condition
fsw_clamp
Start of CRM
operation
depending on
VBulk
D
C
fSWmin
ABM
DCM1
DCM2
DCM3
CRM
VMFIO
VMFIOBMEN
VCSPK(VMFIO
VMFIOC
VMFIOB
VMFIOmax
)
A
VCSmax
C
B
VCSC
D
VCSmin
VMFIO
MULTIMODE_FREQLAW
Figure 23 Configurable frequency law and peak current schemes depending on signal at MFIO pin
4.2.8.1
Frequency law setting for XDPS21071
The frequency law setting for XDPS21071 based on the is defined by the set point A, B, C and D as shown in Table 4.
Table 4
Setpoint
A
Corner points for frequency limitation curve and peak current setting for XDPS21071
Corner point for maximum current at fixed frequency
V
MFIOmax = 2.42 V
f
SWmax = 139.4 kHz
V
V
CSmaxLL = 594 mV
CSmaxHL =392 mV
Data Sheet
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Functional Description
B
C
D
Corner point for border between DCM3 and DCM2 for frequency reduction
V
MFIOB = 1.82 V
f
SWB = 140 kHz
V
V
CSBLL = 443 mV
CSBHL = 366 mV
Corner point for border between DCM2 and DCM1 for fixed frequency and peak current reduction
V
MFIOC = 1.01 V
f
SWC = 24.9 kHz
V
V
CSCLL = 443 mV
CSCHL = 366 mV
Corner point at minimum frequency setting
V
MFIOD = 0.408 V
f
SWmin = 24.9 kHz
V
V
CSminLL = 92mV
CSminHL =15 mV
4.2.9
Frequency jittering
In order to improve the EMI performance, the XDPS21071 enables frequency jittering at heavy load where the
switching frequency is the maximum (fSWmax). The frequency jittering can improve the EMI signature.
Both the frequency amplitude and frequency period will jitter over time as shown in Figure 24 and Figure 25. The
default jittering magnitude is ± 3.125% of the maximum switching frequency fSWmax and the jittering period is
3.2ms.
fSW
No. of sampled points = 256
No. of sampled
points = 2N
Jitter magnitude
= +/- (fSW * X%)
fSWmax
fSWmin
VMFIOC
VMFIOB
VMFIO
Figure 24 Frequency jitter range
Data Sheet
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Functional Description
fSW + Ajitter_Max
Ajitter_Max / 8 points
fSW
fSW - AjitterMax
t
100µs
Jitter Period = 32 points * 100µs = 3200µs
Figure 25 Jittering magnitude and period
Table 5 Frequency jitter parameters
Parameter Name
A_Jitter_percent_val
Physical value
3.125%
Digital value
5
3
A_Jitter_period_val
3.2ms
4.2.10
Burst mode operation
The burst mode (BM) is entered at light load to optimize efficiency and correlated total power consumption. The BM consists
of three main phases:
•
•
•
Burst mode entry (see 4.2.10.1)
Burst operation (see 4.2.10.2)
Burst mode exit (see 4.2.11)
The burst mode control is described in the following chapters based on the block diagram in Figure 27 and the signal
overview in 4.2.10.1.
VVDDP = 3.3 V
RMFIOPU
MFIO
C3
BM Exit
VMFIOBMEX1
C5
Power
Management
VMFIOBMWK
burst-on
BM 2-point
Regulation
BM Ctrl
burst-off
C6
C7
VMFIOBMPA
Frequency
Law
BM Entry
VMFIOBMEN
Figure 26 Block diagram burst mode control
Data Sheet
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Functional Description
IOUT(t)
t
t
VOUT(t)
VOUTnom
Wake-up when wake-
up threshold met
tMFIOBMWK
exit burst mode
VMFIO(t)
VMFIOBMEX
wake-up
VMFIOBMWK
VMFIOBMPA
entering pause
VMFIOBMEN
t
entering burst mode
burst-on phase
VCS(t)
burst-off (pause) phase
VCSmin,
VCSBSP4,
VCSBMEX
t
Figure 27 Burst mode signals
4.2.10.1
Burst mode entry
Figure 27 is showing a typical signal scheme for entering quiet burst mode. The frequency law limits the minimum possible
power transfer defined at the setpoint D (see Chapter 4.2.8.1). With decreasing load, the voltage at MFIO pin sinks. Once the
voltage at MFIO pin falls below the burst mode entry threshold VMFIOBMEN, BM is then entered, the IC initiates a burst-off phase,
where the IC current consumption is reduced to IVCCquBM2. Afterwards, the voltage at MFIO pin controls the output voltage
control via the two-point regulator (see Chapter 4.2.10.2).
As the MFIO voltage determines the frequency and current command value, i.e the power. The efficiency at different output
voltage is also different. A look up table (LUT) based burst mode entry is implemented to cover very small burst enter/leave
hysteresis. Based on the sensed ZCD voltage signal which is output voltage related, a different VMFIO is used to determine the
entering energy for burst mode operation. The small the output voltage, the bigger the entering energy, i.e larger Vmfio
4.2.10.2
Burst operation
The two-point regulator, that is activated during burst mode operation, is implemented with the comparators C5 and C6
(see Figure 26) with the two thresholds VMFIOBMWK and VMFIOBMPA to determine the burst-on and burst-off phase depending on
the feedback signal at the MFIO pin. During this phase, the error signal is now used for the two-point regulator scheme,
whereas it correlates with the inverse output voltage AC ripple signal shape (see Figure 27). The wake-up threshold VMFIOBMWK
determines the output voltage bottom peak ripple point and the pause threshold VMFIOBMPA determines the output voltage
upper peak ripple point. Once the voltage at the MFIO pin exceeds the threshold VMFIOBMWK, IC will be waked-up, it takes
tMFIOBMWK = 26.6 µs till the first gate pulse of the burst sequence starts. The switching cycles during burst-on phase are
predefined and not depending on the voltage at the MFIO pin. All burst sequence pulses have the same switching frequency
fSWBSPx, but progressive changed voltage VCSBSPx as shown in Table 17. All following pulses have then the same peak value for
VCS as the fourth pulse VCSBSP4. The peak value of the Vcs determines, together with the set frequency fSWBSP4, the deliverable
limited maximum power during the quiet burst operation. If the output load is exceeding the deliverable limited power for
the burst operation, the voltage at MFIO pin will increase. After it exceeds the burst mode exit threshold VMFIOBMEX, the control
IC may exit burst mode (see Chapter 4.2.11).
Data Sheet
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Functional Description
4.2.11
Burst mode exit
At load jumps above the burst mode exit power level, a fast burst mode exit is supported to limit the drop in output voltage.
A sudden load demand causes a rising slope at MFIO pin. Once the voltage VMFIO exceeds the threshold VMFIOBMEX, the IC exits
the burst mode immediately.
Once burst mode is exit, the two-point regulation is terminated and the next pulse is determined by the fixed peak current
setting VCSBMEX. The further consecutive pulses are determined by the frequency law (see Chapter 4.2.8) with the voltage VMFIO
controlling the switching cycles.
4.2.12
Forced frequency resonant (FFR) mode operation
XDPS21071 provides a special forced frequency resonant (FFR) mode to reduce significantly switching losses during
operation in discontinuous conduction mode (DCM). Furthermore conducted EMI in the high frequency spectrum > 10MHz
and especially radiated EMI can be greatly reduced, which supports the usage of high speed optimized super junction
MOSFETs. The idea is to turn on the main power MOSFET only at a controlled lowest drain voltage level in a self-generated
oscillation period after demagnetization phase of the flyback transformer has been finished. This self-generated oscillation
period is derived from an additional gate driver pulse that introduces to the flyback transformer at a self-determined time a
defined negative magnetization. The level of negative magnetization current can be configured (see Chapter 5)
Compared to the so called quasi-resonant (QR) operation, which is focusing on turning on the main power MOSFET only in
the valleys after transformer demagnetization, the FFR provides full control on the switching frequency and the drain
voltage swing down level for turning on the MOSFET. Higher frequency design approaches can now be exploited for low line
without compromising on efficiency and EMI for the high line operation. When reducing the load, frequency foldback to
lowest frequency levels can be supported with avoiding any hard switching cycle (see Chapter 4.2.8.1).
Figure 28 shows the required signals in the application for FFR mode operation. The second gate driver GD1 drives Q1 for
initiating the self-controlled zero voltage switching (ZVS) cycle. The HV pin provides the VBulk voltage measurement to adapt
the timings for the ZVS pulse.
vPri
vSec
VOut
VBulk
vDrain
Q0
RZCDH
vAux
ZCD
GND
RZCDL
vZVS
Q1
GD1
GD0
HV
FFR MODE
Figure 28 Required signals for forced frequency resonant (FFR) mode operation
Data Sheet
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Functional Description
The ZCD pin provides the zero crossing detection to enable main gate generation. The ZVS gate can be enabled based on
configurable line voltage with 20Vdc hysteresis.
Figure 29 shows the FFR mode signal wave forms and associated timings. The FFR mode is caused by introducing a ZVS pulse
via the gate driver GD1 during the time frame t1-t2 and subsequent dead-time tZVSdead from t2-t3 until gate driver GD0 turns
on the main power MOSFET. The dead-time tZVSdead should be dimensioned in such a manner that the turn-on of GD0 takes
place at the minimum drain voltage oscillation magnitude, which correlates to a transformer magnetization close to zero.
The forced frequency operation of GD0 is achieved by directly controlling the switching period tSWperiod of GD0. GD1 is
prematurely turned on after the delay time tZVSdelay, when a zero crossing has been detected.
vDrain(t)
NPri / NSec × vSec
VBulk
t
Forced frequency resonant mode
vZVS(t)
NZVS / NSec × vSec
0
t
NZVS / NPri × VBulk
iMag(t)
tf
tZVSdelay
0
t
t
vGD0(t)
tSWperiod
tGD0Off
vGD1(t)
tZVSdead
tGD1on
tGD1Off
t
t1 t2 t3
t4
t5
t1 t2 t3
t4
FFR_MODE_SIGNALS
Figure 29 Signal overview for forced frequency resonant mode operation
The length of the ZVS pulse and the charged voltage of the ZVS capacitor determine the amount of introduced negative
transformer magnetization. A higher level of introduced negative magnetization leads to a lower drain voltage swing down,
which could further optimize the switching losses and high frequency EMI behavior of the main power MOSFET. However,
as this comes along with the expense of increased power losses associated with the additional ZVS pulse generation, a trade
off needs to be found to maximize the potential increase in efficiency and reduction in EMI. Depending on the chosen main
power MOSFET different drain voltage levels might be adapted for turning on the main power MOSFET. This is mainly
depending on the output capacitor characteristic of the power MOSFET, which is highly nonlinear increasing, when going
for low drain voltages. The amount of necessary negative magnetization current increases with the size of the output
capacitor of the power MOSFET and parastics coupling capacitor of transformer. Therefore the dimensioning for the ZVS
pulse generation is significantly depending on the system dimensioning. The default parameter set is optimized for a 45 W
USB PD adapter.
Data Sheet
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Functional Description
The required ZVS pulse length tGD1on is depending on VBulk. The GD1 on-time tGD1on needs to increase with increasing VBulk to
ensure the same low drain voltage level for turning on the main power MOSFET for the whole VAC input range. Whereas the
ZVS dead-time is fixed at tZVSdead = 220 ns (see Chapter 5.2 ).
The default configured relationship between tGD1on and VBulk and determined by following implemented equation:
풕푮푫ퟏ풐풏 = ꢁ푩푼푳푲_푽푶푳푻푨푮푬(푽) ∙ 푲
풏풔ꢂ ∗ ퟏퟓ. ퟏퟓ풏풔 + ퟑퟏ. ퟔ 풏풔
( 10 )
풛풗풔풐풏풇풂풄풕풐풓
ퟔퟓퟓퟑퟔ
푽
The parameter BULK_VOLTAGE(V) is calculated based on the measured current at HV pin IHV via the external resistor RHV
=
102kΩ. Figure 30 shows the default configured relationship between the controlled ZVS pulse length tGD1on and VBulk based on
default Kzvsonfactor=3200.
ZVS ontime Vs Bulk voltage
350
300
250
200
150
100
50
0
70
120
170
220
270
320
370
Vbulk(V)
Figure 30 VBulk depended adaptive ZVS pulse length tGD1on
4.2.13
UART function at GPIO pin
GPIO pin provides a digital IO interface for UART communication. Configuration of defined parameters and HW setups are
supported (see Chapter 5.2). The UART function at GPIO pin is normally enabled till the VCC brown-in is reached (see Chapter
4.1.2). After VCC brown-in, the UART function is disabled.
On the other hand, the UART function can be kept enabled during normal operation by sending a corresponding soft
command before VCC brown-in. Then configuration “on the fly” is supported and change of parameters during normal
operation is possible.
4.3
Protection features
Table 6 shows the protection features and their corresponding reaction on malfunction. Two protection modes (auto-restart
mode and latch mode) as well as a HW reset (IC reset by VCC under-voltage lockout) are implemented.
Note: All protection features w/o UVOFF only apply during normal operation. During sleep phase (in burst or protection
mode), neither pin measurement of pin voltage nor temperature sensor is active.
Table 6
Protection Features
Protection Feature
Symbol
Reaction
Description
VCC Under-Voltage lockout
UVOFF
Deactivate IC
Chapter 4.3.3
Data Sheet
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Functional Description
Brown-In Protection (when Brown-in conditions not met)
Brown-Out Protection
BIP
Block switching Chapter 4.3.4
BOP
Stop switching
CbC limit
Chapter 4.3.5
Chapter 4.3.6
Chapter 4.3.7
Chapter 4.3.8
Chapter 4.3.9
Chapter 4.3.10
Over-Current Protection level 1
Over-current protection level 2
High input at CS pin (> 200 µs)
MFIO pin High
OCP1
OCP2
CShigh
MFIOH
IntOTP
Auto-restart
Auto-restart
Auto-restart
Auto-restart
Internal Over-Temperature Protection
Auto-restart /
Latch mode
Primary side output Over-Voltage Protection
VoutOVP
Chapter 4.3.11
Over load protection
OLP
CSP
Auto-restart
Auto-restart
Chapter 4.3.12
Chapter 4.3.13
CS pin short protection
4.3.1
Auto-Restart Mode (ARM)
Once the auto-restart mode is entered, the IC stops the gate driver switching at GD0 pin and enters stand-by mode with
reduced current consumption of IVCCquAR = 160 µA. After the auto-restart off-time tAR = 3 s, the control IC resumes its operation
with soft-start after the VCC capacitor is charged up and the VCC voltage reaches its turn-on threshold. During the auto-
restart off-phase, the HV startup-cell is operating in the bang-bang mode (see Chapter 4.1.5.2) to keep the VCC voltage at a
high level to have enough energy stored in the VCC capacitor for the system startup.
4.3.2
Latch Mode (LM)
When latch mode is entered, the gate driver switching at GD0 pin is stopped and the control IC enters stand-by mode where
the current consumption is reduced to IVCCquLM = 150 µA. During the latch mode the HV startup-cell is operating in the bang-
bang mode to keep the IC alive and staying in latch mode. Here the voltage VVCC is varying in a wider range compared to the
bang-bang mode operation in auto-restart mode (see Chapter 4.1.5.1).
4.3.3
VCC Under-Voltage lockout (UVOFF)
The implemented VCC under-voltage lockout (UVLO) ensures a defined activation and deactivation of the IC operation
depending on the supply voltage VVCC. The UVLO contains a hysteresis with the voltage thresholds VVCCon = 20.5 V for
activating the IC. For deactivating the IC, two thresholds are defined. They are:
•
•
V
V
VCCoff = 7.2 V during normal operation / during auto-restart break time
VCCoffBO = 9.6 V after brown-out detected
The higher VVCCoffBO threshold leads to earlier deactivation of the IC and earlier charge-up of the VCC capacitor and supports
a new system startup earlier.
Both VCC on- and off-thresholds contain a spike blanking tVCCon and tVCCoff
.
4.3.4
Brown-In Protection (BIP)
At initial power-up or auto-restart, the brown-in condition at the HV pin and at the VCC pin must be fulfilled for starting the
soft-start procedure. The controller measures the current at HV pin through the internal shunt resistor RM (see Figure 3). The
input brown-in is fulfilled if the current IHV exceeds the threshold IHVBI = 1.15 mA. The VCC brown-in is fulfilled if the voltage
V
VCC is above the threshold VVCCBI = 15 V. No blanking time applies for brown-in detection. If one of the brown-in conditions is
not fulfilled, the IC stays active, but without gate switching. The voltage at VCC pin drops then. Once it falls below the
Data Sheet
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Functional Description
threshold VVCCoff = 7.2 V, the control IC is deactivated, and the startup cell is turned on automatically to charge up the VCC
capacitor.
4.3.5
Brown-Out Protection (BOP)
The brown-out protection for bulk voltage prevents the IC from operating with a too low line voltage, which could lead to
high RMS current stress in the application. Brown-out detection is also performed via the HV pin as for brown-in detection.
Here an under-voltage detection of the bulk voltage VBulk is provided to support brown-out protection. The measured current
IHV is compared with the bulk under-voltage detection threshold IHVBO = 0.443 mA. The brown-out protection applies if bulk
under-voltage is detected for certain blanking time. This blanking time is set to tHVBO = 1.09 ms during normal operation and
to tHVBOSS = 5.27 ms during soft-start phase. Once brown-out protection is entered, the IC stops switching, but it is still active
and the VCC turn-off threshold is increased to VVCCoffBO = 9.6V. Once VCC falls below VVCCoffBO, the HV startup cell turns on to
charge up the VCC capacitor (see Chapter 4.1.3).
4.3.6
Over-Current Protection level 1 (OCP1)
The over-current protection level 1 (OCP1) is performed by means of the cycle-by-cycle peak current control via the
comparator OCP1 (see Figure 3). A leading edge blanking (see Chapter 4.2.5) prevents the IC from false switching-off the
power MOSFET due to the leading edge spike. The maximum peak setting for VCS is compensated by the propagation delay
compensation (see Chapter 4.2.3), to provide an input voltage level independent current limitation. The highest peak setting
for VCS of VCSmaxLL(max) = 594 mV occurs at low-line and defines the maximal saturation current of the flyback transformer.
4.3.7
Over-Current Protection level 2 (OCP2)
The over-current protection level 2 (OCP2) protects the flyback converter under critical fault conditions such as shorted
transformer windings or shorted secondary side rectifier diode. In this case, the repeating cycle-by-cycle over-current
protection level OCP1 cannot properly limit the inductor current due to the very steep slope of the current ramp and the
propagation delay in the peak current control. With the over-current protection OCP2, once the threshold VCSOCP2 = 0.8 V is
exceeded for longer than tCSOCP2BL = 616.2 ns during normal operation or tCSOCP2BL = 1.001 µs during startup operation, auto-
restart mode (see Chapter 4.3.1) is entered. In this way, over-heating of the flyback converter is avoided.
4.3.8
High input at CS pin (CShigh)
The CS pin can also be used in a combined manner for a high input signal like external over-temperature which is having a
temperature detection circuit together with a reference voltage, to trigger auto-restart mode (see Chapter 4.3.1).The auto-
restart mode is triggered by pushing up the CS pin for 10ms. The trigger threshold for CShigh is 0.5V ~ 0.8V. In case of
transformer short winding, VCS voltage goes quickly above VCSOCP2; IC will stop the gate and goes to auto-restart mode after
OCP2 blanking time tCSOCP2BL
.
4.3.9
MFIO pin high (MFIOH)
There are several phenomena that causes MFIO pin high; feedback loop open, overload, etc. The feedback open-loop
protection is implemented by means of a digital comparator C2 (see Figure 3). When the voltage at MFIO pin exceeds the
threshold VMFIOH = 2.41 V, a timer is triggered. Auto-restart mode (see Chapter 4.3.1) is entered if the timer exceeds the period
of tMFIOH = 31.3 ms. This is mainly for open loop and startup protection, during startup, since the output voltage hasn’t reach
the setpoint, MFIO pin voltage is always high.
4.3.10
Internal over-temperature detection (IntOTP)
An internal over-temperature protection is implemented in this control IC. Once the internal temperature exceeds the
threshold of TJOTP = 130 °C for longer than the blanking time tJOTP = 10.5 ms, internal over-temperature is detected and the
Data Sheet
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Functional Description
control IC enters auto-restart mode (see Chapter 4.3.1). The normal operation will be resumed if the internal temperature is
dropped by 20 °C from TJOTP
.
4.3.11
Primary side output Over-Voltage Protection (VoutOVP)
The IC provides primary side output over-voltage detection via the ZCD pin. Here the reflected output voltage from the
flyback transformer is sampled at ZCD pin during the demagnetization phase (see Chapter 4.2.1.1). In each switching cycle,
the XDPS21071 compares the measured output voltage VZCDVO with the output over-voltage threshold VZCDOVP = 2.75V.
That comparison can refer to
•
•
the demagnetization phase of the same switching cycle or
the demagnetization phase of an earlier switching cycle.
A blanking filter is implemented to avoid erroneous output over-voltage detection. This filter consists of a symmetrical
counter. Each comparison where VZCDVO < VZCDOVP, will decrement the counter (but not below zero) while each comparison
where VZCDVO ≥ VZCDOVP will increment the counter. If the counter is increased to NZCDOVP+1, auto-restart mode (see Chapter 4.3.1)
is entered. This protection mode is a configurable parameter. It can be changed to latch mode (see Chapter 4.3.2) by .dp
Vision.
4.3.12
Over load power protection
The IC provides protection against over load by means of the integrated maximum peak current limitation combined with
an over-load timer (OLPT). Once OLP is detected, the control IC enters auto-restart mode (see Chapter 4.3.1).
XDPS21071 uses current mode control, so the OCP1 Look-Up-Table (LUT) values are designed by considering the propagation
delay at different line voltages and operation modes. Once the OCP1 LUT value is hit, the OLP timer will start to count up. The
counter will reduce the count if OCP1 LUT value is not hit in the cause of OCP1 protection. Finally the IC will enter AR if
protection timer reaches the pre-definite time.
This protection can distinguish with open loop protection by setting different OLP timer. E.g during power up, Vmfio is always
high before voltage rise up, so with different timer, it can separately control the open loop protection and over load
protection.
Table 7
Power protection parameters
Protection
Parameter Name
Protection level
Digital value
Blanking time
0.594 V @ 80 VDC
0.392 V @ 376 VDC
255 @ 80 VDC
202 @ 376 VDC
OLP
LOLP
31.3ms
4.3.13
CS pin short protection
During fisrt power up, IC will check three pulses continuously, if the pulses length are longer than 1.5 µs , IC will
go to auto restart mode.
Data Sheet
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Configuration
5
Configuration
This chapter contains an overview about the parameters and functions that can be configured via the UART interface at GPIO
pin. Furthermore the configuration procedure is described. Mapping overviews show the correlation between the data sheet
parameters and the correlated firmware symbols. Furthermore the equations are listed to provide the specific correlation
between the configured FW parameter and the system parameter.
The chapter “configuration” is grouped in following sections:
•
•
Overview of configuration parameters using .dp Vision (Chapter 5.1)
Overview of configurable parameters and functions (Chapter 5.2)
The following shown default parameter settings correlate to the firmware version REV 1.4 .
5.1
Overview of configurable parameters using .dp Vision
The Infineon graphic user interface (GUI) .dp Vision connects to XDPS21071 via the isolated USB interface board called .dp
Interface Gen2. The .dp interface Gen2 provides power via VCC to XDPS21071 and connects via UART interface at pin
GPIO/UART. The common UART interface enables communication with the IC even without the interactive GUI tool. This
allows easy configuration during mass production.
For project development, a graphic user interface called .dp Vision guides the designer through the configuration of
parameters. More detailed information on .dp Vision can be found in the .dp Vision User Manual prepared by Infineon.
5.2
Overview of configurable parameters and functions
There are 2 types of parameters; configurable and fixed. The configurable parameters are allowed to change. On the other
hands, the fixed parameters are not recommended to change. The list of parameters shown is default value and has been
verified in the 45W HD adapter demonstrator. The parameters are typical values. Please refer to the corresponding electrical
characteristics in Chapter 6.5 for the min/max tolerances.
5.2.1
Configurable parameters and functions
The following table shows the default value of the configurable parameters. If necessary, the parameters can be changed.
Table 8
List of configurable Parameters
Feature
Parameter
Default
Description
Chapter/Table
Propagation
delay
PDC_FACTOR
13000d
Propagation Delay Compensation factor
compensation for
peak current
control
Chapter 4.2.3,
PDC_OFFSET
0d
Propagation Delay Compensation offset
Blanking filter at CS pin to avoid erroneous turn-
off of GD0 due to leading edge spike at GD0 turn- Chapter 4.2.5
on
Leading edge
blanking (LEB)
269 ns
tCSLEB
Dead-time between end of ZVS pulse at GD1 and
start of GD0
ZVS dead-time
220 ns
3200
tZVSdead
Chapter 4.2.11
ZVS pulse length
factor
ZVS pulse length factor
kZVSonfactor
Gate driver
capability
31mA
130 °C
Sourcing current of Gate driver 0
Chapter 4.2.7
Chapter 4.3.10
I_GD0_drive
TJOTP
Internal Over-temperature detection level
34
Protections
Data Sheet
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Forced Frequency Resonant Flyback controller
Configuration
600ns
Blanking time for OCP2 of Vcs signal
Blanking time for overload protection
To enable or disable over load protection
tocp2
30ms
tpeakpower
En_OLP
Enabled
Protection mode for OVP, configurable for AR or
Latch
Autorestart
Response_OVP
Chapter 4.1.5
Chapter 4.2.10
0.128V
Burst mode current limit
Burst mode frequency
Vcs_bst
50.0 kHz
Freq_bst
Burst mode
parameters
Pause threshold at MFIO pin during on-phase in
burst mode operation
1.35V
V_bst_pause
2.00V
5ms
Burst mode exit voltage at MFIO pin
V_bst_exit
minimum time to re-entry the burst mode
T_reentry_bst
Chapter 4.2.8
140kHz
Frequency settings for point A
Fsw_A
1.00V
1.80V
0.45V
105kHz
28000
MFIO pin corner point C voltage
Vmfio_C
Vmifo_B
Vcs_BC
Frequency law
settings
MFIO pin corner point B voltage
Current sense limit between point B and C
Frequency clamp when Vin>200 V, Vzcd<1.28 V
Gradient for compensation curve
fclamp
K_Vcs_offset
Vcs_offset_Vzcdzeropoi
nt
Adaptive Vcs
offset
ZCD voltage level( digital value) without Vcs
offset
79
Chapter 4.2.1.3
Enabled
To enable or disable Vcs_offset compensation
En_Vcs_offset
Data Sheet
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Electrical Characteristics
6
Electrical Characteristics
All signals are measured with respect to ground GND pin. The voltage levels are valid if other ratings are not violated.
Attention: Limits are subject to change according to test engineering results
6.1
Definitions
Figure 31 illustrates the definition for the voltage and current parameters used in this data sheet.
+I
+IPIN
PIN
+
+VPIN
DUT
+V
_
GND
DEFINITIONS_V_I_DS
Figure 31 Voltage and Current Definitions
Values indicated under “absolute maximum ratings” must not be exceeded.
Values indicated under “operating conditions” can be exceeded if a corresponding explicit “absolute maximum rating” is
given for this parameter, but the related function of the device is not ensured.
6.2
Absolute Maximum Ratings
Stresses above the values listed below may cause permanent damage to the device. Exposure to absolute maximum rating
conditions for given periods may affect device reliability. Maximum ratings are absolute ratings; exceeding anyone of these
values may cause irreversible damage to the device.
Table 9
Absolute Maximum Ratings
Symbol
Parameter
Limit Values
Unit Remarks
min
-0.5
-0.5
—
max
3)
Voltage at VCC pin
26
V
VVCC
VGD0
Voltage at GD0 pin
V
V
VCC+0.3
Internally clamped to VGD0H
1), absolute average over
1 ms
Average current at GD0 pin
20
mA
|IGD0 AVG
|
RMS Current at GD0 pin
Voltage at GD1 pin
—
100
mA
V
2), RMS over 20 µs
IGD0RMS
VGD1
-0.5
Internally clamped to
VGD1H
V
VCC+0.3
3)
Voltage at HV pin
Current at HV pin
Voltage at ZCD pin
-0.5
—
600
10
V
VHV
mA
V
IHV
3)
-0.5
—
3.6
2.0
VZCD
-VZCD_TR
Maximum negative transient
input voltage for ZCD
V
4) <500ns
3)
Voltage at CS pin
Data Sheet
-0.5
3.6
V
VCS
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Electrical Characteristics
4)<500ns
4)<500ns
Maximum negative transient
input voltage for CS
—
—
3
6
V
-VCS_TR
-ICLN_TR
Maximum transient input
clamping current for ZCD
and CS
mA
Maximum permanent input
clamping current for ZCD
—
—
3.5
2.5
mA
mA
-ICLN_DC_ZCD
Maximum permanent input
clamping current for CS
-Icln_DC_CS
3)
3)
Voltage at MFIO pin
-0.5
-0.5
-40
-55
—
3.6
V
VMFIO
VGPIO
TJ
Voltage at GPIO pin
3.6
V
Junction temperature
Storage temperature
Maximum power dissipation
125
150
0.46
°C
°C
W
TS
PTOT
TA = 60 °C
TJ = 125 °C
RthJA = 141 K/W
Soldering temperature
ESD capability
—
—
—
—
260
2
°C
kV
V
5), wave soldering
TSold
VHBM
VCDM
ILU
6), human body model
500
150
7), charged device model
8)
Latch-up capability
1) Relevant w.r.t. electromigration.
mA
2) Relevant w.r.t. thermal heating at small duty cycles.
3) Permanently applied as DC value.
4) Negative range must fulfill clamping current limits
5) According to JESD22-A111A
6) According to ANSI/ESDA/JEDEC JS-001-2012
7) According to JESD22-C101F
8) According to JESD78D, 85 °C (Class II) temperature
6.3
Package Characteristics
Table 10
Thermal Characteristics
Symbol Limit Values
Parameter
Unit
Remarks
min
—
max
1), JEDEC 1s0p
1), JEDEC 2s2p
Thermal resistance from junction to
ambient
141
K/W
K/W
RthJA1
RthJA2
—
81
Creepage distance between HV vs.
GND-related pins
3.3
—
mm
DCR
1) IC footprint and PCB trace with 35 µm Cu, TA = 85 °C, 180 mW power dissipation
Data Sheet
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Electrical Characteristics
6.4
Operating Range
Table 11 shows the operating range, in which the electrical characteristics shown in Chapter 6.5 are valid.
Table 11
Operating Range
Parameter
Symbol Limit Values
Unit
Remarks
min
max
Junction Temperature
Voltage at VCC pin
Voltage at HV pin
-25
°C
V
TJ
125
VVCCon
600
5
4)
VVCC
VHV
IHV
VVCCoff
-0.3
—
V
Current into HV pin
Voltage at ZCD pin
mA
V
Limited by external RHV
-0.3
3.3
An applied voltage lower
than 0V needs to respect
the negative maximum
clamping current IZCD
VZCD
Current into ZCD pin
Voltage at CS pin
-1.5
-0.3
-10
—
mA
V
IZCD
3.3
0.1
3.3
3.3
VCS
Current into CS pin
Voltage at MFIO pin
Voltage at GPIO pin
Voltage at GD0 pin
mA
V
ICS
-0.3
-0.3
-0.3
VMFIO
VGPIO
VGD0
V
V
V
V
VCC+0.3
VCC+0.3
Internally clamped at VGD0H
Internally clamped at VGD1H
Voltage at GD1 pin
-0.3
1.5
V
VGD1
1), 2), RGDxload = 10 Ω in
series to CGDxload
Minimum required capacitive load at
GDx pin
—
nF
CGDxload
Low state output reverse current at
GDx pin
—
100
mA
-IGDxLREV
3), applies if VGDx < 0 V
and driver at low state
1) Not tested in production test.
2) See figure in Chapter 8.1
3) Assured by design.
4) In practical application design, the applied Vcc voltage nees to be less than 19V ( min. value of VVCCon
)
Data Sheet
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Electrical Characteristics
6.5
Characteristics
The electrical characteristics involve the spread of values given within the specified supply voltage and junction
temperature range TJ from -25 °C to 125 °C. Typical values represent the median values related to TJ = 25°C. All voltages refer
to GND and the assumed supply voltage is VVCC = 14 V, if not otherwise mentioned.
The following characteristics are specified
•
•
•
•
•
•
•
•
•
Power Supply at VCC pin (Table 12)
HV pin (Table 13)
ZCD pin(Table 14)
MFIO pin (Table 15)
GPIO pin (Table 16)
CS pin (Table 17)
GDx pin (Table 18)
IC Control Features (Table 19)
IC Protection Features (Table 20)
Table 12
Electrical Characteristics of the Power Supply at VCC pin
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
—
Typ.
30
Max.
50
VCC UVOFF current
µA
IVCCUVOFF
IVCCop1
VVCC < VVCCon(min) - 0.3 V
1), normal operation
with gate driver GDx
output low, GPIO pin
open, IMFIO-=280 µA
VCC operating current
—
7.5
8.7
mA
—
—
—
—
—
—
—
11
8.4
8.2
8.0
—
mA
mA
mA
mA
IVCCop2
IVCCop3
IVCCop4
IVCCop5
1), as for IVCCop1, but
TJ = 110 °C
1), as for IVCCop1, but
TJ = 100 °C
1), as for IVCCop1, but
TJ = 85 °C
1), Cload = 2 nF,
f
SWGDx = 83 kHz,
IMFIO=-280µA,TJ=25˚C
VCC average quiescent
current in latched mode
0.080
0.150
0.160
0.300
0.310
mA
mA
IVCCquLM
IVCCquAR
V
VCC=8 V, latch mode,
MFIO, GPIO open
VCC average quiescent
current during sleep
phase in auto-restart
mode
—
V
VCC=7 V, sleep phase
in auto-restart mode,
MFIO, GPIO open
VCC quiescent current
during sleep phase in
quiet burst mode
—
—
0.18
0.46
1.2
1.5
mA
mA
Burst mode entered,
MFIO, GPIO pin open
IVCCquBM1
IVCCquBM2
1), 2), burst mode
entered, IMFIO=-280
µA,
GPIO pin open
Data Sheet
39
Revision 2.0
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
—
—
—
—
—
—
1.2
1.0
0.8
mA
mA
mA
IVCCquBM3
IVCCquBM4
IVCCquBM5
1), as for IVCCquBM2
TJ=110˚C
,
,
,
1), as for IVCCquBM2
TJ=100˚C
1), as for IVCCquBM2
TJ=85˚C
VCC turn-on threshold
VCC turn-off threshold
19
20.5
7.2
21.5
7.56
V
V
VVCCon
VVCCoff
dVVCC/dt =0.2 V/ms
6.84
During normal
operation, IC latched
and auto-restart
break time
9.12
9.6
10.08
V
V
After brown-out
detected
VVCCoffBO
VVCChysOP
1)
VCC turn-on/off
hysteresis during normal
operation
—
13.3
—
VCC turn-off blanking
time
550
—
—
ns
1), 1 V overdrive
tVCCoff
1)
VCC turn-on delay
—
—
2
µs
V
tVCCon
VCC threshold for turning
on HV startup cell in
protection mode
8.5
9
9.5
1), bang-bang mode
during auto-restart
and latch mode
VVCCBBon
Blanking time for turning
on HV startup cell in
auto-restart and latch
mode
0.6
19
—
2.2
21.5
2.4
9.7
µs
V
1), 1 V overdrive,
bang-bang mode
tVCCBBon
VVCCBBoff
tVCCBBoff
VVCCBI
VCC threshold for turning
off HV startup cell in
auto-restart and latch
mode
20.5
—
Blanking time for turning
off HV startup cell in
auto-restart and latch
mode
0.7
µs
1), 1 V overdrive,
bang-bang mode
1) 3)
VCC brown-in threshold
1) Not tested in production test.
2) Current value is based on the sum of external sink current IMFIO and IC quiescent current IVCCquBM1
3) See configuration Chapter5
8.4
9.1
V
,
.
Table 13
Electrical Characteristics of HV pin
Parameter
Symbol
Min.
Values
Typ.
Unit Note/Test Condition
Max.
Data Sheet
40
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
1),2), no blanking
with blanking tHVBO
1), 2), 3)
Brown-in threshold
Brown-out threshold
1.10
0.420
0.99
1.156
0.443
1.09
1.21
0.465
1.21
mA
mA
ms
IHVBI
IHVBO
tHVBO
Brown-out blanking time
during normal load
1) 2)
Brown-out blanking time
during soft-start
4.95
2.4
5.27
5
5.59
10
ms
mA
,
tHVBOSS
IHVchargeVCC
IHVLK
4), VVCC=1 V,
VHV=30 V
HV peak VCC charge
current capability
Leakage current at HV pin
—
—
10
µA
V
VHV=600 V,
HV startup cell
disabled
1)
Bulk voltage threshold for
special frequency clamp
1) Not tested in production test.
Vbulk_high
200
2) See configuration Chapter 5.
3) Min. and max. values are based on master clock period tMCLK limits (see Table 20).
4) Max. peak charge current will be limited in the application by an external resistor connected to HV pin.
Table 14
Electrical Characteristics of ZCD pin
Parameter
Symbol
Min.
Values
Unit Note/Test Condition
Typ.
Max.
Input leakage current, no pull
device
-10
—
10
µA
µA
IZCDLK
V
ZCD=0 V/3 V
1), TJ=85˚C
-1
—
1
V
ZCD=0 V/3 V
ZCD voltage threshold
20
35
55
mV
ns
VZCDTHR
tZCDPW
ZCD voltage threshold
debouncing time
150
—
—
1), shorter pulses are
ignored
1)
ZCD zero crossing
comparator propagation
delay
20
40
60
ns
tZCDP
1) 2)
ZCD ringing suppression
time
1.80
150
—
1.91
180
—
2.03
220
µs
,
tZCDRS
ZCD clamping of neg.
voltages
mV
µs
-VZCDclp
tGD0offZCMin
1)
Minimum time from GD0
turn off to first zero-
crossing to ensure settling
of ZCD sampling
3.33
1), 2) tGD0offZC≥tGD0offZCMin
ZCD output over-voltage
threshold in HV mode
2.72
2.75
41
2.79
V
VZCDOVP
Data Sheet
Revision 2.0
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
1), 2) tGD0offZC
tGD0offZCMin
≥
ZCD debouncing counter
threshold for output over-
voltage detection
—
2
—
NZCDOVP
1)
ZCD threshold voltage for
special clamp of switching
frequency
1.272
-
1.296
0.177
1.320
-
V
V
Vzcd_low
1)
ZCD threshold voltage
hysteresis
1)
Not tested in production test.
2) See configuration Chapter 5.
Table 15
Electrical Characteristics of MFIO pin
Parameter
Symbol
Min.
Values
Unit Note/Test Condition
Typ.
—
Max.
10
Input leakage current without
pull device activated
-10
-1
µA
µA
IMFIOLK
V
MFIO=0 V/3 V
1), TJ=85˚C
—
1
V
MFIO=0 V/3 V
Open circuit output
voltage
3.0
3.3
3.6
V
V
V
Normal mode
VMFIOOC
3.0
3.2
3.4
1), 2), sleep mode
1) 3)
Open-loop detection
threshold
2.35
2.41
2.47
,
VMFIOH
1) 3)
Maximum control range
—
2.42
—
V
V
,
VMFIOmax
VMFIOB
1) 3)
Setpoint B of the
frequency law
1.773
1.821
1.869
,
1) 3)
Setpoint C of the
frequency law
0.965
0.372
1.01
1.046
0.443
V
V
,
VMFIOC
1) 3)
Setpoint D of the
frequency law
0.408
,
VMFIOD
1)
Burst mode entry
threshold
0.570
0.419
0.607
0.455
0.644
0.491
V
V
,
3) Vzcd<1.723V
VMFIOBMEN1
VMFIOBMEN2
1) 3)
,
1.723V=<Vzcd<2.152V
1)
0.372
8.8
0.408
11
0.443
13.2
1.73
V
,
3) Vzcd>=2.152V
VMFIOBMEN3
RMFIOPU
3)
Internal pull-up resistor
kΩ
V
1), 3)
Burst wake-up threshold
during burst-off phase
1.47
1.60
VMFIOBMWK
Minimum input pulse
width for burst wake-up
Data Sheet
300
—
—
ns
1), shorter pulses will
be suppressed
tMFIOBMWKPW
42
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
1)
Time between burst
wake-up and the first
burst sequence pulse
—
26.6
32
µs
V
,
tMFIOBMWK
VMFIOBMPA
VMFIOBMEX
dVMFIO/dt = 100 mV/µs
1) 3)
Burst-off entering
threshold during burst-
on phase
1.322
1.970
1.366
2.020
1.410
2.070
,
1) 3)
BM exit threshold
V
,
Not tested in production test.
During burst mode, auto restart and latch mode operation.
See configuration Chapter 5.
Table 16
Electrical Characteristics of GPIO pin
Symbol
Parameter
Values
Typ.
Unit
Note/Test Condition
Min.
Max.
Input leakage current without
pull device activated
-10
-1
—
—
10
1
µA
µA
IGPIOLK
V
GPIO=0 V/3 V
1), TJ=85˚C
GPIO=0 V/3 V
V
Open circuit output
voltage
3.0
3.3
3.6
V
VGPIOOC
1
Input capacitance
—
—
—
—
—
10
1.0
—
pF
V
CGPIOIN
VGPIOIL
VGPIOIH
-IGPIOLPU
Threshold for logic “0”
Threshold for logic “1”
—
2.0
30
V
2) at VGPIOIL(max)
Low input pull-up
current
90
µA
Output sink current
—
—
—
—
—
—
2
mA
mA
ns
IGPIOSNKOL
-IGPIOSRCOH
tGPIORISE
Output source current
Output rise time (0 → 1)
2
50
20 pF load, push/pull
output
Output fall time (1 → 0)
—
—
50
ns
20 pF load, push/pull
output
tGPIOFALL
1) Not tested in production test.
2) Currents flowing out of the device (DUT) are marked with a negative sign in the ‘Symbol’ column
Table 17
Electrical Characteristics of CS pin
Parameter
Symbol
Min.
Values
Unit Note/Test Condition
Typ.
Max.
Input leakage current without
pull device activated
-10
—
10
µA
µA
ICSLK
VCS=0 V/3 V
1), TJ=85˚C
VCS=0 V/3 V
-1
—
1
Data Sheet
43
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
CS OCP2 threshold
0.76
125
0.80
155
0.84
190
V
VCSOCP2
CS OCP2 propagation delay
until GD0 turn-off at
ns
1) dVCS/dt=100 V/µs
tCSGD0OCP2
IGD0>2mA
CS OCP2 blanking time for
auto-restart
498.8
810
616.2
1001
733.6
1192
ns
ns
Normal operation
During startup
1), 2), 3)
tCSOCP2BL
CS OCP1 comparator
minimum pulse width
—
35
—
ns
1), shorter pulses will
be suppressed
tCSOCP1PW
CS OCP1 propagation delay
until GD0 turn-off at
180
120
100
—
260
185
130
2.371
—
345
250
165
—
ns
1), low line use case
1), high line use case
1), dVCS/dt=100 V/µs
tCSOCP1PDLL
tCSOCP1PDHL
tCSOCP1PD
ns
IGD0 > 2 mA
ns
CS OCP1 threshold steps
mV
mV
∆VCSOCP1
1)
CS OCP1 threshold
accuracy
-25
25
∆VCSOCP1THR
Leading edge blanking time
255
269
284
ns
1), 2), 3)
tCSLEB
CS OCP1 maximum CS limit
560
325
-50
-60
594
392
—
631
456
50
mV
mV
mV
mV
1), 2), low line use case
1), 2), high line use case
1),low line use case
1), high line use case
VCSmaxLL
VCSmaxHL
Tolerance for CS OCP1
maximum CS FASTOPP
limit
∆VCSFASTOPPLL
∆VCSFASTOPPHL
—
60
CS limit at setpoint B
408
299
408
443
366
443
479
430
479
mV
mV
mV
1), 2),low line use case
1), 2),high line use case
1), 2),low line use case
VCSBLL
VCSBHL
VCSCLL
CS limit at setpoint C
299
57
0
366
92
430
128
79
mV
mV
mV
1), 2),high line use case
1), 2),low line use case
1), 2),high line use case
VCSCHL
Minimum CS limit at burst
mode entry
VCSminLL
VCSminHL
15
Burst sequence:
1st pulse CS limit
—
—
—
—
—
—
120
43
—
—
—
—
—
—
mV
mV
mV
mV
mV
mV
mV
1), 2),low line use case
1), 2),high line use case
1), 2),low line use case
1), 2),high line use case
1), 2),low line use case
1), 2),high line use case
VCSBSP1LL
VCSBSP1HL
VCSBSP2LL
VCSBSP2HL
VCSBSP3LL
VCSBSP3HL
VCSBSP4LL
Burst sequence:
2nd pulse CS limit
120
43
Burst sequence:
3rd pulse CS limit
120
43
Maximum CS limit during
burst mode operation
120
1), 2), low line use case
4th and consecutive
Data Sheet
44
Revision 2.0
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
pulses after start of
burst sequence
43
mV
1), 2), high line use case
4th and consecutive
pulses after start of
burst sequence
VCSBSP4HL
CS limit for 1st pulse
directly after BM exit
92
15
—
mV
mV
mV
mV
mV
1), 2),low line use case
1), 2),high line use case
1), 2),low line use case
1), 2),high line use case
VCSBMEXLL
VCSBMEXHL
VCSSSLL
Initial soft-start CS limit
limitation without PDC
45
70
—
110
155
—
—
VCSSSHL
∆VCSS
1), 2),step every t
Soft-start step for cycle by
cycle limitation
1) Not tested in production test.
2.5
VCSS
2) See configuration Chapter 5.
3) Min. and max. values are based on master clock period tMCLK limits (see Table 19).
Table 18
Electrical Characteristics of GDx pin
Parameter
Symbol
Min.
Values
Unit Note/Test Condition
Typ.
Max.
Low state sink peak current
Low state resistance
500
—
—
mA
IGDxLPKSNK
1), VGDx=4 V,
C
Load=2 nF
—
—
6.5
RGDxLSNK
Ω
High state peak source
current of GD1
100
118
136
mA
-IGD1HPKSRC
2), 3), CLoad=2 nF
2), 3), CLoad=2 nF
3), IGDx=-1 mA
High state peak source
current of GD0
30
35
41
mA
-IGD0HPKSRC
High state output voltage
9.97
10.5
11.03
V
V
VGDxH
High state rail-to-rail output
voltage
—
VGDxHRR
V
VCC-0.5
VVCC
V
VCC<VGDxH
APD low voltage
—
—
1.6
V
VGDxAPD
IGDx=5 mA
(active pull down while
device is not powered or
gate driver is not enabled)
Permanent pull-down
resistor inside gate driver
450
600
750
kΩ
RGDxPPD
1)
Not tested in production test.
2)
Currents flowing out of the device (DUT) are marked with a negative sign in the ‘Symbol’ column.
3)
See configuration Chapter 5.
Table 19
Electrical Characteristics of IC Control
Symbol
Parameter
Values
Unit Note/Test Condition
Data Sheet
45
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
Min.
2.397
49.50
99.0
Typ.
2.428
52.1
Max.
2.459
54.78
109.56
VREF internal voltage reference
Time base 1
V
VREF
1)
1)
µs
µs
ns
µs
ms
ms
tBase1
tBase2
tMCLK
tSTBCLK
tSSmax
tBootIC
Time base 2
104.28
2)
3)
1)
Master clock period
Stand-by clock period
Maximum soft-start time
15.0
9.09
6.64
—
15.8
10.0
7.0
16.6
11.11
7.36
—
1),4), VVCC>VVCCon
Boot sequence time when
activating IC
1.2
1)
Maximum frequency
operation
132.6
23.6
139.4
24.9
146.9
26.3
kHz
kHz
fSWmax
fSWmin
1)
1)
1)
1)
1)
1)
Switching frequency
setting at minimum power
operation point
Burst sequence:
1st pulse switching
frequency
—
50.2
50.2
50.2
50.2
139.4
—
kHz
kHz
kHz
kHz
kHz
fSWBSP1
fSWBSP2
fSWBSP3
fSWBSP4
fSWBMEXHV
Burst sequence:
2nd pulse switching
frequency
—
—
Burst sequence:
3rd pulse switching
frequency
—
—
Burst sequence:
4th and consecutive pulse
switching frequency
—
—
Switching frequency 1st
pulse directly after BM exit
1) Not tested in production test.
132.6
146.9
2) The master clock period is the base for all time measurements without stand-by. Relative tolerances of all performed time
measurements are same as with tMCLK
.
3) The stand-by clock is the base for all time related characteristics during stand-by operation.
4) Phase for loading the OTP content to the internal RAM
Table 20
Electrical Characteristics of IC Protection Features
Parameter
Symbol
Values
Unit Note/Test Condition
Min.
Typ.
Max.
1) 2)
Auto-restart bang-bang mode
off-time
455
500
556
ms
,
tBBoffAR
1) 2)
Auto-restart time
2.73
29.7
3
—
s
,
tAR
1) 3)
Blanking time of open-loop
timer
31.3
33
ms
,
tMFIOH
V
MFIO>VMFIOOLP
Data Sheet
46
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Forced Frequency Resonant Flyback controller
Electrical Characteristics
1),4)
Over-temperature detection
122
130
-
°C
TJOTP
tJOTP
1) 3)
Over-temperature blanking
time
9.90
10.50
11.10
ms
,
1)
Over-temperature
Hysteresis
-
20
-
°C
TJHYS_OTP
1) Not tested in production test.
2) Min. and max. values are based on stand-by clock period tSTBCLK limits (see Table 20).
3) Min. and max. values are based on master clock period tMCLK (see Table 20).
4)
The recommended temp is below 125 ˚C , above this temperature, IC function cannot be guaranteed, Customer should
guarantee the design will never exceed the 125 ˚C of IC die temperature.
Data Sheet
47
Revision 2.0
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Forced Frequency Resonant Flyback controller
Package Information
7
Package Information
The package information contains the outline dimensions (see Chapter 7.1); footprint and packing overviews (see Chapter
7.2).
Notes
1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
2. Dimensions in mm.
7.1
Outline dimensions
Figure 32 PG-DSO-12-20 Package Outline
Data Sheet
48
Revision 2.0
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Forced Frequency Resonant Flyback controller
Package Information
7.2
Footprint and packing
Figure 33 Overview footprint
Figure 34 Overview packing
Data Sheet
49
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Forced Frequency Resonant Flyback controller
Marking
8
Marking
Figure 35 Marking of XDPS21071
Data Sheet
50
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Forced Frequency Resonant Flyback controller
Appendix
9
Appendix
This appendix contains additional information on electrical characteristics and specific test conditions.
9.1
Minimum required capacitive load at GD0 and GD1 pin
The output stage of GD0 and GD1 consist of a controlled current source (see 4.2.7). This current source charges up an external
capacitive load until the voltage level VGDxH = 10.5 V is reached. The internal control loop for this source current requires a
minimum load capacitance at GDx pin to avoid a turn-on ringing on the signal VGDx
.
The minimum required capacitive load is depending on the dimensioned serial gate resistor at GDx pin, which is meant for
limiting the low state sink current.
Furthermore, the required load is depending on the configured source current. The shown dependency in Figure 36 is based
on the typical source current of –IGDxHPKSRC=118mA. Lower configured values for the source current requires also smaller
capactive loads.
Figure 36 Minimum required capacitive load at GDx pin in correlation with serial gate resistor
Data Sheet
51
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Forced Frequency Resonant Flyback controller
References
10
References
The following list shows the reference documents that are used as base for this data sheet.
[1] Development firmware version: REV 1.0
Data Sheet
52
Revision 2.0
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Forced Frequency Resonant Flyback controller
Revision history
Revision history
Major changes since the last revision
Page or Reference
Description of change
16/Aug/2019
Draft 0.9 release
Data Sheet
53
Revision 2.0
2019-10-30
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBlade™, EasyPIM™,
EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, Infineon™, ISOFACE™, IsoPACK™,
i-Wafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™,
PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Trademarks updated August 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
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Edition 2019-10-30
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Published by
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contact your nearest Infineon Technologies office
(www.infineon.com).
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With respect to any examples, hints or any typical
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Technologies hereby disclaims any and all
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Document reference
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相关型号：
XDPS21081
英飞凌 XDPS21081 是一款反激式控制器IC，其初级侧引入 ZVS （零电压开关），通过简化电路和经济型开关来实现更高的工作效率。与传统的谷值开关方案相比，通过驱动外部低压开关产生负电流使主高压开关 MOSFET 放电，从而进一步降低开关损耗。 为了以同步整流实现更高效率，XDPS21081 多模式数字强制准谐振 (FQR) 反激控制器 IC 通过谷值检测来确保 DCM （非连续导通模式）工作模式，从而实现更安全可靠的运行。
INFINEON
XDPS2201
XDP™ 数字电源 XDPS2201是一种多模式、数字可配置的混合反激控制器，它结合了传统简化的反激拓扑结构和谐振变换器的性能。通过使用两个高压MOSFET，例如CoolMOSTM，混合反激XDPS2201控制器能够在不对称半桥反激拓扑中驱动高压侧和低压侧MOSFET。通过调节正负磁化电流的方法，可以在初级实现零电压开关和次级实现零电流开关，提高了效率。此外，变压器漏感能量被回收，更进一步提高效率。
INFINEON
XDRA821UXXGALM
Dual Arm Cortex-A72, quad Cortex-R5F, 4-port Ethernet switch, and a PCIe controller | ALM | 433 | -40 to 125
TI
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