XE161FU4F40VAAKXUMA1 [INFINEON]
RISC Microcontroller, CMOS,;
| 型号： | XE161FU4F40VAAKXUMA1 |
| 厂家： | 
Infineon |
| 描述： | RISC Microcontroller, CMOS, 微控制器 |
| 文件： | 总106页 (文件大小：2720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit
Architecture
XE161FU
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family / Compact Line
Data Sheet
V1.2 2012-07
Microcontrollers
Edition 2012-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
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16-Bit
Architecture
XE161FU
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family / Compact Line
Data Sheet
V1.2 2012-07
Microcontrollers
XE161FU
XE166 Family / Compact Line
XE161FU Data Sheet
Revision History: V1.2 2012-07
Previous Versions: V1.0 2010-12, V1.1 2011-09
Page
Subjects (major changes since last revision)
48, 49
The value of absolute sum of overload currents parameter in absolute
maximum rating parameter and operating conditions tables are switched.
70
Table description on coding of bit field LEVxV is updated.
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
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Data Sheet
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Data Sheet
5
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Table of Contents
Table of Contents
1
1.1
1.2
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
2.1
2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capture/Compare Unit (CC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . 40
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Window Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
4
4.1
4.1.1
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.4
4.5
4.6
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Voltage Range definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 54
DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.7
4.7.1
Data Sheet
1
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Table of Contents
4.7.2
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Selecting and Changing the Operating Frequency . . . . . . . . . . . . . . 78
External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7.2.1
4.7.2.2
4.7.2.3
4.7.3
4.7.4
4.7.5
4.7.6
5
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.1
5.2
5.3
Data Sheet
2
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Summary of Features
16-Bit Single-Chip
Real Time Signal Controller
XE161FU (XE166 Family)
1
Summary of Features
For a quick overview and easy reference, the features of the XE161FU are summarized
here.
•
High-performance CPU with five-stage pipeline and MPU
– 15.2 ns instruction cycle @ 66 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for code and data
– 1,024 Bytes on-chip special function register area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
•
Interrupt system with 16 priority levels providing 46 interrupt nodes
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 15.2 ns
•
•
•
•
Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
Clock generation from internal or external clock sources,
using on-chip PLL or prescaler
Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
On-chip memory modules
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– 2 Kbytes on-chip data SRAM (DSRAM)
– 4 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 64 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC) for Flash
memory and through parity for RAMs
Data Sheet
3
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Summary of Features
•
On-Chip Peripheral Modules
– Synchronizable 12-bit A/D Converter with up to 10 channels,
conversion time below 1 μs, optional data preprocessing (data reduction, range
check), broken wire detection
– 16-channel general purpose capture/compare unit (CC2)
– Capture/compare unit for flexible PWM signal generation (CCU60)
– Multi-functional general purpose timer unit with 5 timers
– Up to 2 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),
IIS interface
– On-chip system timer and on-chip real time clock
•
•
•
•
•
•
Single power supply from 3.0 V to 5.5 V
Power reduction and wake-up modes with flexible power management
Programmable window watchdog timer and oscillator watchdog
Up to 33 general purpose I/O lines
On-chip bootstrap loaders
Supported by a full range of development tools including C compilers, macro-
assembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
•
•
On-chip debug support via Device Access Port (DAP), Single-Pin DAP (SPD) or
JTAG interface
48-pin Green VQFN package, 0.5 mm (10.7 mil) pitch
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. This ordering code identifies:
•
•
the function set of the corresponding product type
the temperature range1):
– SAF-…: -40°C to 85°C
– SAK-…: -40°C to 125°C
•
the package and the type of delivery.
For ordering codes for the XE161FU please contact your sales representative or local
distributor.
1) Not all derivatives are offered in all temperature ranges.
Data Sheet
4
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Summary of Features
1.1
Device Types
The following XE161FU device types are available and can be ordered through
Infineon’s direct and/or distribution channels.
Table 1
Derivative1)
Synopsis of XE161FU Device Types
Flash PSRAM
Capt./Comp. ADC4) Interfaces4)
Memory2) DSRAM3) Modules
Chan.
XE161FU-4FxV
32 Kbytes 4 Kbytes
2 Kbytes
CC2
CCU60
10
2 Serial Chan.
XE161FU-8FxV
64 Kbytes 4 Kbytes
2 Kbytes
CC2
CCU60
10
2 Serial Chan.
1) x is a placeholder for available speed grade in MHz. Can be 40 or 66.
2) Specific information about the on-chip Flash memory in Table 3.
3) All derivatives additionally provide 2 Kbytes DPRAM.
4) Specific information about the available channels in Table 5.
Data Sheet
5
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Summary of Features
1.2
Definition of Feature Variants
The XE161FU types are offered with several Flash memory sizes. Table 3 and Table 4
describe the location of the available Flash memory.
Table 3
Continuous Flash Memory Ranges
Total Flash Size
1st Range1)
2nd Range
3rd Range
64 Kbytes
C0’0000H …
C1’0000H …
n.a.
C0’EFFFH
C1’0FFFH
32 Kbytes
C0’0000H …
n.a.
n.a.
C0’7FFFH
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
Table 4
Flash Memory Module Allocation (in Kbytes)
Total Flash Size
Flash 01)
Flash 1
n.a.
64
32
64
32
n.a.
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
The XE161FU types are offered with different interface options. Table 5 lists the
available channels for each option.
Table 5
Interface Channel Association
Total Number
Available Channels / Message Objects
10 ADC0 channels
CH0, CH2, CH3, CH4, CH8, CH9, CH16, CH17, CH19,
CH20
2 serial channels
U0C0, U0C1
Data Sheet
6
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
2
General Device Information
The XE161FU series (16-Bit Single-Chip
Real Time Signal Controller) is a part of the Infineon XE166 Family of full-feature single-
chip CMOS microcontrollers. These devices extend the functionality and performance of
the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They
combine high CPU performance (up to 66 million instructions per second) with extended
peripheral functionality and enhanced IO capabilities. Optimized peripherals can be
adapted flexibly to meet the application requirements. These derivatives utilize clock
generation via PLL and internal or external clock sources. On-chip memory modules
include program Flash, program RAM, and data RAM.
VAREF VAGND
VDDIMVDDPB VSS
(1) (1)
(2) (3) (3)
XTAL1
XTAL2
Port 2
12 bit
Port 10
12 bit
Port 5
6 bit
Port 6
3 bit
PORST TRST SPD/DAP/ Debug
JTAG
1 / 2 / 4 bit
2 bit
TESTM
via Port Pins
MC_XY_LOGSYMB48
Figure 1
XE161FU Logic Symbol
Data Sheet
7
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
2.1
Pin Configuration and Definition
The pins of the XE161FU are described in detail in Table 6, which includes all alternate
functions. For further explanations please refer to the footnotes at the end of the table.
The following figure summarizes all pins, showing their locations on the four sides of the
package.
TESTM
TRST
P6.3
P6.1
P6.0
P10.5
P10.4
P10.3
P10.2
P10.1
P10.0
P2.13
P2.10
P2.9
P2. 8
P2. 7
P2. 6
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
VSS
VDDPB
VQFN48
VAREF
VAGND
P5.0
P5.2
P5.3
9
10
11
12
MC_XY_PIN48
Figure 2
XE161FU Pin Configuration (top view)
Data Sheet
8
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Key to Pin Definitions
•
Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
Type: Indicates the pad type and its power supply domain (B, M).
– St: Standard pad
•
– Sp: Special pad e.g. XTALx
– DA: Digital IO and analog input
– In: Input only pad
– PS: Power supply pad
Table 6
Pin Definitions and Functions
Ctrl. Type Function
Pin Symbol
1
TESTM
I
In/B Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
An internal pullup device will hold this pin high
when nothing is driving it.
2
TRST
I
In/B Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XE161FU’s debug
system. In this case, pin TRST must be driven low
once to reset the debug system.
An internal pulldown device will hold this pin low
when nothing is driving it.
3
4
P6.3
O0 / I St/B Bit 3 of Port 6, General Purpose Input/Output
T3OUT
O2
I
St/B GPT12E Timer T3 Toggle Latch Output
St/B External Request Trigger Input for ADC0/1
ADC0_REQT
RyF
P6.1
O0 / I DA/B Bit 1 of Port 6, General Purpose Input/Output
ADC0_CH17
EMUX1
T3OUT
I
DA/B Analog Input Channel 17 for ADC0
O1
O2
I
DA/B External Analog MUX Control Output 1 (ADC0)
DA/B GPT12E Timer T3 Toggle Latch Output
DA/B External Request Trigger Input for ADC0
ADC0_REQT
RyE
ESR1_6
I
DA/B ESR1 Trigger Input 6
Data Sheet
9
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
5
P6.0
O0 / I DA/B Bit 0 of Port 6, General Purpose Input/Output
ADC0_CH16
EMUX0
I
DA/B Analog Input Channel 16 for ADC0
DA/B External Analog MUX Control Output 0 (ADC0)
DA/B OCDS Break Signal Output
O1
O3
BRKOUT
ADC0_REQG I
TyG
DA/B External Request Gate Input for ADC0
10
11
P5.0
I
I
I
I
I
I
I
I
I
I
I
In/B Bit 0 of Port 5, General Purpose Input
In/B Analog Input Channel 0 for ADC0
In/B Bit 2 of Port 5, General Purpose Input
In/B Analog Input Channel 2 for ADC0
In/B JTAG Test Data Input
ADC0_CH0
P5.2
ADC0_CH2
TDI_A
12
13
P5.3
In/B Bit 3 of Port 5, General Purpose Input
In/B Analog Input Channel 3 for ADC0
In/B GPT12E Timer T3 Count/Gate Input
In/B Bit 4 of Port 5, General Purpose Input
In/B Analog Input Channel 4 for ADC0
ADC0_CH3
T3INA
P5.4
ADC0_CH4
T3EUDA
In/B GPT12E Timer T3 External Up/Down Control
Input
TMS_A
P5.8
I
I
I
I
In/B JTAG Test Mode Selection Input
14
In/B Bit 8 of Port 5, General Purpose Input
In/B Analog Input Channel 8 for ADC0
In/B External Run Control Input for T12 of CCU60
ADC0_CH8
CCU60_T12
HRC
CCU60_T13
HRC
I
In/B External Run Control Input for T13 of CCU60
15
16
P5.9
I
I
I
In/B Bit 9 of Port 5, General Purpose Input
In/B Analog Input Channel 9 for ADC0
In/B CAPCOM2 Timer T7 Count Input
ADC0_CH9
CC2_T7IN
P2.0
O0 / I DA/B Bit 0 of Port 2, General Purpose Input/Output
ADC0_CH19
T5INB
I
I
DA/B Analog Input Channel 19 for ADC0
DA/B GPT12E Timer T5 Count/Gate Input
Data Sheet
10
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
17
P2.1
O0 / I DA/B Bit 1 of Port 2, General Purpose Input/Output
ADC0_CH20
T5EUDB
I
I
DA/B Analog Input Channel 20 for ADC0
DA/B GPT12E Timer T5 External Up/Down Control
Input
ESR1_5
ERU_0A0
P2.2
I
I
DA/B ESR1 Trigger Input 5
DA/B External Request Unit Channel 0 Input A0
21
22
O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output
ESR2_5
ERU_1A0
P2.3
I
I
St/B ESR2 Trigger Input 5
St/B External Request Unit Channel 1 Input A0
O0 / I St/B Bit 3 of Port 2, General Purpose Input/Output
St/B USIC0 Channel 0 Shift Data Output
O3 / I St/B CAPCOM2 CC16IO Capture Inp./ Compare Out.
U0C0_DOUT O1
CC2_CC16
ESR2_0
I
I
I
St/B ESR2 Trigger Input 0
U0C0_DX0E
U0C1_DX0D
P2.4
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 1 Shift Data Input
23
24
O0 / I St/B Bit 4 of Port 2, General Purpose Input/Output
St/B USIC0 Channel 1 Shift Data Output
O3 / I St/B CAPCOM2 CC17IO Capture Inp./ Compare Out.
U0C1_DOUT O1
CC2_CC17
ESR1_0
I
I
St/B ESR1 Trigger Input 0
U0C0_DX0F
P2.5
St/B USIC0 Channel 0 Shift Data Input
O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output
U0C0_SCLK O1
OUT
St/B USIC0 Channel 0 Shift Clock Output
CC2_CC18
U0C0_DX1D
ESR1_10
O3 / I St/B CAPCOM2 CC18IO Capture Inp./ Compare Out.
I
I
St/B USIC0 Channel 0 Shift Clock Input
St/B ESR1 Trigger Input 10
Data Sheet
11
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
25
P2.6
O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output
U0C0_SELO O1
0
St/B USIC0 Channel 0 Select/Control 0 Output
U0C1_SELO O2
1
St/B USIC0 Channel 1 Select/Control 1 Output
CC2_CC19
CLKIN1
O3 / I St/B CAPCOM2 CC19IO Capture Inp./ Compare Out.
I
I
I
St/B Clock Signal Input 1
U0C0_DX2D
ESR2_6
P2.7
St/B USIC0 Channel 0 Shift Control Input
St/B ESR2 Trigger Input 6
26
O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output
U0C1_SELO O1
0
St/B USIC0 Channel 1 Select/Control 0 Output
U0C0_SELO O2
1
St/B USIC0 Channel 0 Select/Control 1 Output
CC2_CC20
U0C1_DX2C
ESR2_7
O3 / I St/B CAPCOM2 CC20IO Capture Inp./ Compare Out.
I
I
St/B USIC0 Channel 1 Shift Control Input
St/B ESR2 Trigger Input 7
27
28
P2.8
O0 / I St/B Bit 8 of Port 2, General Purpose Input/Output
U0C1_SCLK O1
OUT
St/B USIC0 Channel 1 Shift Clock Output
EXTCLK
CC2_CC21
U0C1_DX1D
P2.9
O2
St/B Programmable Clock Signal Output
O3 / I St/B CAPCOM2 CC21IO Capture Inp./ Compare Out.
St/B USIC0 Channel 1 Shift Clock Input
O0 / I St/B Bit 9 of Port 2, General Purpose Input/Output
St/B USIC0 Channel 1 Shift Data Output
O3 / I St/B CAPCOM2 CC22IO Capture Inp./ Compare Out.
I
U0C1_DOUT O1
CC2_CC22
C1
I
I
St/B Configuration Pin 1
TCK_A
St/B DAP0/JTAG Clock Input
Data Sheet
12
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
29
P2.10
O0 / I St/B Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
U0C0_SELO O2
3
St/B USIC0 Channel 0 Select/Control 3 Output
CC2_CC23
U0C1_DX0E
CAPINA
O3 / I St/B CAPCOM2 CC23IO Capture Inp./ Compare Out.
I
I
St/B USIC0 Channel 1 Shift Data Input
St/B GPT12E Register CAPREL Capture Input
30, P2.13
31 P10.0
O0 / I St/B Bit 13 of Port 2, General Purpose Input/Output
O0 / I St/B Bit 0 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
St/B CCU60 Channel 0 Output
CCU60_CC6 O2
0
CCU60_CC6
0INA
I
St/B CCU60 Channel 0 Input
ESR1_2
I
I
I
St/B ESR1 Trigger Input 2
U0C0_DX0A
U0C1_DX0A
P10.1
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 1 Shift Data Input
32
O0 / I St/B Bit 1 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B USIC0 Channel 0 Shift Data Output
St/B CCU60 Channel 1 Output
CCU60_CC6 O2
1
CCU60_CC6
1INA
I
St/B CCU60 Channel 1 Input
U0C0_DX0B
U0C0_DX1A
I
I
St/B USIC0 Channel 0 Shift Data Input
St/B USIC0 Channel 0 Shift Clock Input
Data Sheet
13
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
33
P10.2
O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output
U0C0_SCLK O1
OUT
St/B USIC0 Channel 0 Shift Clock Output
CCU60_CC6 O2
2
St/B CCU60 Channel 2 Output
CCU60_CC6
2INA
I
St/B CCU60 Channel 2 Input
U0C0_DX1B
P10.3
I
St/B USIC0 Channel 0 Shift Clock Input
34
35
O0 / I St/B Bit 3 of Port 10, General Purpose Input/Output
CCU60_COU O2
T60
St/B CCU60 Channel 0 Output
U0C0_DX2A
U0C1_DX2A
P10.4
I
I
St/B USIC0 Channel 0 Shift Control Input
St/B USIC0 Channel 1 Shift Control Input
O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output
U0C0_SELO O1
3
St/B USIC0 Channel 0 Select/Control 3 Output
CCU60_COU O2
T61
St/B CCU60 Channel 1 Output
U0C0_DX2B
U0C1_DX2B
ESR1_9
I
I
I
St/B USIC0 Channel 0 Shift Control Input
St/B USIC0 Channel 1 Shift Control Input
St/B ESR1 Trigger Input 9
36
37
P10.5
O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output
U0C1_SCLK O1
OUT
St/B USIC0 Channel 1 Shift Clock Output
CCU60_COU O2
T62
St/B CCU60 Channel 2 Output
U0C1_DX1B
P10.6
I
St/B USIC0 Channel 1 Shift Clock Input
O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B USIC0 Channel 0 Shift Data Output
St/B USIC0 Channel 0 Shift Data Input
St/B CCU60 Emergency Trap Input
U0C0_DX0C
I
I
CCU60_CTR
APA
Data Sheet
14
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
38
P10.7
O0 / I St/B Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B USIC0 Channel 1 Shift Data Output
St/B CCU60 Channel 3 Output
CCU60_COU O2
T63
U0C1_DX0B
I
I
St/B USIC0 Channel 1 Shift Data Input
St/B CCU60 Position Input 0
CCU60_CCP
OS0A
T4INB
P10.8
I
St/B GPT12E Timer T4 Count/Gate Input
39
O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output
U0C0_MCLK O1
OUT
St/B USIC0 Channel 0 Master Clock Output
St/B USIC0 Channel 1 Select/Control 0 Output
St/B CCU60 Position Input 1
U0C1_SELO O2
0
CCU60_CCP
OS1A
I
U0C0_DX1C
BRKIN_B
T3EUDB
I
I
I
St/B USIC0 Channel 0 Shift Clock Input
St/B OCDS Break Signal Input
St/B GPT12E Timer T3 External Up/Down Control
Input
ESR2_11
P10.9
I
St/B ESR2 Trigger Input 11
40
O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output
U0C0_SELO O1
4
St/B USIC0 Channel 0 Select/Control 4 Output
St/B USIC0 Channel 1 Master Clock Output
St/B CCU60 Position Input 2
U0C1_MCLK O2
OUT
CCU60_CCP
OS2A
I
TCK_B
T3INB
I
I
St/B DAP0/JTAG Clock Input
St/B GPT12E Timer T3 Count/Gate Input
Data Sheet
15
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
44
P10.10
O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output
U0C0_SELO O1
0
St/B USIC0 Channel 0 Select/Control 0 Output
CCU60_COU O2
T63
St/B CCU60 Channel 3 Output
U0C0_DX2C
TDI_B
I
I
I
St/B USIC0 Channel 0 Shift Control Input
St/B JTAG Test Data Input
U0C1_DX1A
P10.12
St/B USIC0 Channel 1 Shift Clock Input
45
O0 / I St/B Bit 12 of Port 10, General Purpose Input/Output
U0C0_DOUT O2
St/B USIC0 Channel 0 Shift Data Output
St/B DAP1/JTAG Test Data Output
TDO_A
SPD_0
C0
OH
I/OH St/B SPD Input/Output
I
St/B Configuration Pin 0
U0C0_DX0D
XTAL2
XTAL1
I
St/B USIC0 Channel 0 Shift Data Input
Sp/M Crystal Oscillator Amplifier Output
46
47
O
I
Sp/M Crystal Oscillator Amplifier Input
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDIM
.
ESR2_9
PORST
I
I
St/B ESR2 Trigger Input 9
48
In/B Power On Reset Input
A low level at this pin resets the XE161FU
completely. A spike filter suppresses input pulses
<10 ns. Input pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition
should be 120 ns.
An internal pullup device will hold this pin high
when nothing is driving it.
8
9
VAREF
VAGND
-
-
PS/B Reference Voltage for A/D Converters ADC0
PS/B Reference Ground for A/D Converters ADC0
Data Sheet
16
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Ctrl. Type Function
Pin Symbol
18, VDDIM
-
PS/M Digital Core Supply Voltage for Domain M
43
Decouple with a ceramic capacitor, see Data
Sheet for details.
All VDDIM pins must be connected to each other.
7,
20,
41
VDDPB
-
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
V
DDP/VSS pin pairs as close as possible to the pins.
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
6,
19,
42
VSS
Data Sheet
17
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
General Device Information
2.2
Identification Registers
The identification registers describe the current version of the XE161FU and of its
modules.
Table 7
XE161FU Identification Registers
Short Name
SCU_IDMANUF
SCU_IDCHIP
SCU_IDMEM
SCU_IDPROG
JTAG_ID
Value
1820H
5001H
3010H
1313H
Address
Notes
00’F07EH
00’F07CH
00’F07AH
00’F078H
001D’7083H ---
Data Sheet
18
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3
Functional Description
The architecture of the XE161FU combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XE161FU.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XE161FU.
OCDS
Debug Support
DPRAM
DSRAM
PSRAM
LXBUS
Controller
CPU
Flash Memory
MAC Unit
MCHK
WWD
RTC
System Functions
Clock, Reset, Power
Control
MPU
Interrupt& PEC
Interrupt Bus
CC2
ADC0
GPT
CCU60
USIC0
Module
Module
Module
Module
8-/10-/
12-Bit
5
16
Chan.
3+1
Chan.
2
Timers
Chan.
Analog and Digital General Purpose IO (GPIO) Ports
MC_U- SERIES_BLOCKDIAGRAM
Figure 3
Block Diagram
Data Sheet
19
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XE161FU is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XE161FU Memory Map 1)
Address Area
Start Loc. End Loc. Area Size2)
FF’FF00H FF’FFFFH 256 bytes
F0’0000H FF’FEFFH < 1 Mbyte
Notes
IMB register space
Reserved
Minus IMB
registers.
Reserved for EPSRAM E8’1000H EF’FFFFH 508 Kbytes
Mirrors EPSRAM
Emulated PSRAM
Reserved for PSRAM
PSRAM
E8’0000H E8’0FFFH up to 4 Kbytes With Flash timing.
E0’1000H E7’FFFFH 508 Kbytes Mirrors PSRAM
E0’0000H E0’0FFFH up to 4 Kbytes Program SRAM.
C1’1000H DF’FFFFH 1980 Kbytes
C0’0000H C1’0FFFH 68 Kbytes3)
40’0000H BF’FFFFH 8 Mbytes
Reserved for Flash
Flash 0
External memory area
External IO area4)
Reserved
21’0000H 3F’FFFFH 1984 Kbytes
20’B400H 20’FFFFH 19 Kbytes
USIC0 alternate regs.
20’B000H 20’B3FFH 1 Kbytes
Accessed via
LXBus controller
Reserved
20’4800H 20’AFFFH 26 Kbytes
20’4000H 20’47FFH 2 Kbytes
USIC0 registers
Accessed via
LXBus controller
Reserved
20’0000H 20’3FFFH 16 Kbytes
01’0000H 1F’FFFFH 1984 Kbytes
00’FE00H 00’FFFFH 0.5 Kbytes
00’F600H 00’FDFFH 2 Kbytes
External memory area
SFR area
Dual-port RAM
(DPRAM)
Reserved for DPRAM
ESFR area
00’F200H 00’F5FFH 1 Kbytes
00’F000H 00’F1FFH 0.5 Kbytes
00’E000H 00’EFFFH 4 Kbytes
00’D800H 00’DFFFH 2 Kbytes
XSFR area
Data SRAM (DSRAM)
Data Sheet
20
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Table 8
XE161FU Memory Map (cont’d)1) (cont’d)
Address Area
Start Loc. End Loc. Area Size2)
00’8000H 00’D7FFH 22 Kbytes
00’0000H 00’7FFFH 32 Kbytes
Notes
Reserved for DSRAM
External memory area
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
4) Several pipeline optimizations are not active within the external IO area.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
4 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the
PSRAM with programmable size can be write-protected.
Data Sheet
21
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
2 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.
The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for general purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word-wide registers which are
used to control and monitor functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XE166 Family. In order to ensure
upward compatibility they should either not be accessed or written with zeros.
The on-chip Flash memory stores code, constant data, and control data. The on-chip
Flash memory consist of 1 module of 64 Kbytes. Each module is organized in 4-Kbyte
sectors.
The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used
internally to store operation control parameters and protection information.
Each sector can be separately write protected1), erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read access with protected and efficient writing algorithms for programming and erasing.
Dynamic error correction provides extremely high read data security for all read access
operations. Access to different Flash modules can be executed in parallel.
For Flash parameters, please see Section 4.6.
Memory Content Protection
The contents of on-chip memories can be protected against soft errors (induced e.g. by
radiation) by activating the parity mechanism or the Error Correction Code (ECC).
The parity mechanism can detect a single-bit error and prevent the software from using
incorrect data or executing incorrect instructions.
The ECC mechanism can detect and automatically correct single-bit errors. This
supports the stable operation of the system.
It is strongly recommended to activate the ECC mechanism wherever possible because
this dramatically increases the robustness of an application against such soft errors.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
Data Sheet
22
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.2
Central Processing Unit (CPU)
The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-
fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and
accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply-and-divide unit, a bit-mask generator, and a barrel
shifter.
PSRAM
Flash/ROM
PMU
CPU
Prefetch
CSP
IP
VECSEG
TFR
2-Stage
Prefetch
Pipeline
Unit
CPUCON1
CPUCON2
Branch
Unit
5-Stage
Pipeline
Injection/
Exception
Handler
DPRAM
Return
Stack
FIFO
IFU
DPP0
IPIP
IDX0
IDX1
QX0
QX1
QR0
QR1
SPSEG
SP
CP
R15
DPP1
DPP2
DPP3
STKOV
STKUN
R15
R14
R14
GPRs
GPRs
+/-
+/-
ADU
s
R1
R0
R1
Division Unit
Multiply Unit
Bit-Mask-Gen.
Barrel-Shifter
R0
Multiply
Unit
MRW
R0
R0
MCW
MSW
MDC
PSW
RF
+/-
+/-
MDH
MDL
ONES
ALU
DSRAM
EBC
Peripherals
Buffer
WB
MAH
MAL
ZEROS
MAC
DMU
mca04917_x.vsd
Figure 4
CPU Block Diagram
Data Sheet
23
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
With this hardware most XE161FU instructions are executed in a single machine cycle
of 15.2 ns @ 66-MHz CPU clock. For example, shift and rotate instructions are always
processed during one machine cycle, no matter how many bits are shifted. Also,
multiplication and most MAC instructions execute in one cycle. All multiple-cycle
instructions have been optimized so that they can be executed very fast; for example, a
32-/16-bit division is started within 4 cycles while the remaining cycles are executed in
the background. Another pipeline optimization, the branch target prediction, eliminates
the execution time of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 word-
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided for storage of temporary data. The system
stack can be allocated to any location within the address space (preferably in the on-chip
RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during
each stack access to detect stack overflow or underflow.
The high performance of the CPU hardware implementation can be best utilized by the
programmer with the highly efficient XE161FU instruction set. This includes the following
instruction classes:
•
•
•
•
•
•
•
•
•
•
•
•
•
Standard Arithmetic Instructions
DSP-Oriented Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
24
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.3
Memory Protection Unit (MPU)
The XE161FU’s Memory Protection Unit (MPU) protects user-specified memory areas
from unauthorized read, write, or instruction fetch accesses. The MPU can protect the
whole address space including the peripheral area. This completes established
mechanisms such as the register security mechanism or stack overrun/underrun
detection.
Four Protection Levels support flexible system programming where operating system,
low level drivers, and applications run on separate levels. Each protection level permits
different access restrictions for instructions and/or data.
Every access is checked (if the MPU is enabled) and an access violating the permission
rules will be marked as invalid and leads to a protection trap.
A set of protection registers for each protection level specifies the address ranges and
the access permissions. Applications requiring more than 4 protection levels can
dynamically re-program the protection registers.
3.4
Memory Checker Module (MCHK)
The XE161FU’s Memory Checker Module calculates a checksum (fractional polynomial
division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on
a 32-bit linear feedback shift register and may, therefore, also be used to generate
pseudo-random numbers.
The Memory Checker Module is a 16-bit parallel input signature compression circuitry
which enables error detection within a block of data stored in memory, registers, or
communicated e.g. via serial communication lines. It reduces the probability of error
masking due to repeated error patterns by calculating the signature of blocks of data.
The polynomial used for operation is configurable, so most of the commonly used
polynomials may be used. Also, the block size for generating a CRC result is
configurable via a local counter. An interrupt may be generated if testing the current data
block reveals an error.
An autonomous CRC compare circuitry is included to enable redundant error detection,
e.g. to enable higher safety integrity levels.
The Memory Checker Module provides enhanced fault detection (beyond parity or ECC)
for data and instructions in volatile and non volatile memories. This is especially
important for the safety and reliability of embedded systems.
Data Sheet
25
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.5
Interrupt System
The architecture of the XE161FU supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Using a standard interrupt service the current program execution is suspended and a
branch to the interrupt vector table is performed. With the PEC just one cycle is ‘stolen’
from the current CPU activity to perform the PEC service. A PEC service implies a single
byte or word data transfer between any two memory locations with an additional
increment of either the PEC source pointer, the destination pointer, or both. An individual
PEC transfer counter is implicitly decremented for each PEC service except when
performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source-related vector location. PEC services
are particularly well suited to supporting the transmission or reception of blocks of data.
The XE161FU has eight PEC channels, each with fast interrupt-driven data transfer
capabilities.
With a minimum interrupt response time of 7/111) CPU clocks, the XE161FU can react
quickly to the occurrence of non-deterministic events.
Interrupt Nodes and Source Selection
The interrupt system provides 46 physical nodes with separate control register
containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit
field. Most interrupt sources are assigned to a dedicated node. A particular subset of
interrupt sources shares a set of nodes. The source selection can be programmed using
the interrupt source selection (ISSR) registers.
External Request Unit (ERU)
A dedicated External Request Unit (ERU) is provided to route and preprocess selected
on-chip peripheral and external interrupt requests. The ERU features 4 programmable
input channels with event trigger logic (ETL) a routing matrix and 4 output gating units
(OGU). The ETL features rising edge, falling edge, or both edges event detection. The
OGU combines the detected interrupt events and provides filtering capabilities
depending on a programmable pattern match or miss.
Trap Processing
The XE161FU provides efficient mechanisms to identify and process exceptions or error
conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap
causes an immediate system reaction similar to a standard interrupt service (branching
1) Depending if the jump cache is used or not.
Data Sheet
26
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in the trap flag register (TFR). Unless another higher-priority trap service
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.6
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XE161FU provides a broad range of
debug and emulation features. User software running on the XE161FU can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
consists of the 2-pin Device Access Port (DAP) or of the 1-pin Single Pin DAP (SPD) or
of the JTAG port conforming to IEEE-1149. The debug interface can be completed with
an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (SPD, DAP or JTAG). In addition the OCDS system can be controlled
by the CPU, e.g. by a monitor program. An injection interface allows the execution of
OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing of data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XE166 Family emulation device.
The SPD interface uses one interface signal, DAP interface uses two interface signals,
the JTAG interface uses four interface signals, to communicate with external circuitry.
The debug interface can be amended with two optional break lines.
Data Sheet
27
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.7
Capture/Compare Unit (CC2)
The CAPCOM unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of one system clock cycle (eight cycles in
staggered mode). The CAPCOM unit is typically used to handle high-speed I/O tasks
such as pulse and waveform generation, pulse width modulation (PWM), digital to
analog (D/A) conversion, software timing, or time recording with respect to external
events.
Two 16-bit timers with reload registers provide two independent time bases for the
capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs allow event scheduling for the capture/compare registers relative to external
events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer and
programmed for capture or compare function.
All registers have each one port pin associated with it which serves as an input pin for
triggering the capture function, or as an output pin to indicate the occurrence of a
compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Table 9
Compare Modes
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
Several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
Several compare events per timer period are possible
Data Sheet
28
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Table 9
Compare Modes (cont’d)
Compare Modes
Function
Mode 2
Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
Can be used with any compare mode
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin associated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition
at the pin can be selected as the triggering event.
The contents of all registers selected for one of the five compare modes are continuously
compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the compare mode selected.
Data Sheet
29
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Reload Reg.
T7REL
fCC
T7
T7IN
T6OUF
Input
Control
Timer T7
T7IRQ
CC16IO
CC17IO
CC16IRQ
CC17IRQ
Mode
Control
(Capture
or
Sixteen
16-bit
Capture/
Compare
Registers
Compare)
CC31IO
CC31IRQ
T8IRQ
T8
Input
fCC
Timer T8
T6OUF
Control
Reload Reg.
T8REL
MC_CAPCOM2_BLOCKDIAG
Figure 5
CAPCOM Unit Block Diagram
Data Sheet
30
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.8
Capture/Compare Units CCU6x
The XE161FU types feature the CCU60 unit.
CCU6 is a high-resolution capture and compare unit with application-specific modes. It
provides inputs to start the timers synchronously, an important feature in devices with
several CCU6 modules.
The module provides two independent timers (T12, T13), that can be used for PWM
generation, especially for AC motor control. Additionally, special control modes for block
commutation and multi-phase machines are supported.
Timer 12 Features
•
Three capture/compare channels, where each channel can be used either as a
capture or as a compare channel.
•
Supports generation of a three-phase PWM (six outputs, individual signals for high-
side and low-side switches)
•
•
•
•
•
•
•
•
16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short circuits in the power stage
Concurrent update of the required T12/13 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Many interrupt request sources
Hysteresis-like control mode
Automatic start on a HW event (T12HR, for synchronization purposes)
Timer 13 Features
•
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Can be synchronized to T12
Interrupt generation at period match and compare match
Single-shot mode supported
Automatic start on a HW event (T13HR, for synchronization purposes)
Additional Features
•
•
•
•
•
•
•
Block commutation for brushless DC drives implemented
Position detection via Hall sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC drives
Output levels can be selected and adapted to the power stage
Data Sheet
31
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
CCU6 Module Kernel
fSYS
compare
Channel 0
T12 Channel 1
Channel 2
1
Dead-
time
Control
Multi-
channel
Control
Trap
Control
TxHR
1
1
start
Interrupts
T13 Channel 3
compare
1
3
2
2
2
3
1
Input / Output Control
mc_ccu6_blockdiagram.vsd
Figure 6
CCU6 Block Diagram
Timer T12 can work in capture and/or compare mode for its three channels. The modes
can also be combined. Timer T13 can work in compare mode only. The multi-channel
control unit generates output patterns that can be modulated by timer T12 and/or timer
T13. The modulation sources can be selected and combined for signal modulation.
Data Sheet
32
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.9
General Purpose Timer (GPT12E) Unit
The GPT12E unit is a very flexible multifunctional timer/counter structure which can be
used for many different timing tasks such as event timing and counting, pulse width and
duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers organized in two separate modules,
GPT1 and GPT2. Each timer in each module may either operate independently in a
number of different modes or be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental
Interface Mode. In Timer Mode, the input clock for a timer is derived from the system
clock and divided by a programmable prescaler. Counter Mode allows timer clocking in
reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes each timer has one associated port pin (TxIN) which serves as a gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The counting direction (up/down) for each timer can be programmed by software or
altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position
tracking.
In Incremental Interface Mode the GPT1 timers can be directly connected to the
incremental position sensor signals A and B through their respective inputs TxIN and
TxEUD. Direction and counting signals are internally derived from these two input
signals, so that the contents of the respective timer Tx corresponds to the sensor
position. The third position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to the basic operating modes, T2 and T4 may be configured as reload or
capture register for timer T3. A timer used as capture or reload register is stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at the associated
input pin (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered either by
an external signal or a selectable state transition of its toggle latch T3OTL. When both
T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL
with the low and high times of a PWM signal, this signal can be continuously generated
without software intervention.
Note: Signals T2IN, T2EUD, T4EUD, T6OUT, T6IN and T6EUD are not connected to
pins.
Data Sheet
33
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
T3CON.BPS1
2n:1
Basic Clock
fGPT
Interrupt
Aux. Timer T2
Request
(T2IRQ)
U/D
T2IN
T2
Mode
Control
Reload
T2EUD
Capture
Interrupt
Request
(T3IRQ)
T3
Core Timer T3
T3OTL
Toggle
Latch
T3IN
Mode
Control
T3OUT
U/D
T3EUD
Capture
Reload
T4IN
T4
Mode
Control
Interrupt
Request
(T4IRQ)
Aux. Timer T4
T4EUD
U/D
MC_GPT_BLOCK1
Figure 7
Block Diagram of GPT1
Data Sheet
34
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
counting direction (up/down) for each timer can be programmed by software or altered
dynamically with an external signal on a port pin (TxEUD). Concatenation of the timers
is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2
timers and to initiate a reload from the CAPREL register.
The CAPREL register can capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared
after the capture procedure. This allows the XE161FU to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of
GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Data Sheet
35
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
T6CON.BPS2
2n:1
Basic Clock
GPT2 Timer T5
fGPT
Interrupt
Request
(T5IRQ)
T5IN
T5
Mode
Control
U/D
T5EUD
Clear
Capture
CAPIN
GPT2 CAPREL
CAPREL
Mode
Control
Interrupt
Request
(CRIRQ)
Reload
Clear
T3IN/
T3EUD
Interrupt
Request
(T6IRQ)
Toggle
FF
GPT2 Timer T6
U/D
T6OTL
T6OUT
T6OUF
T6
Mode
Control
T6IN
T6EUD
MC_GPT_BLOCK2
Figure 8
Block Diagram of GPT2
Data Sheet
36
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.10
Real Time Clock
The Real Time Clock (RTC) module of the XE161FU can be clocked with a clock signal
selected from internal sources or external sources (pins).
The RTC basically consists of a chain of divider blocks:
•
•
•
Selectable 32:1 and 8:1 dividers (on - off)
The reloadable 16-bit timer T14
The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
fRTC
MUX
:
32
RUN
RTCINT
MUX
Interrupt Sub Node
: 8
CNT
INT0
CNT
INT1
CNT
INT2
CNT
INT3
PRE
REFCLK
REL-Register
T14REL
10 Bits
6 Bits
6 Bits
10 Bits
fCNT
T14
10 Bits
6 Bits
6 Bits
10 Bits
T14-Register
CNT-Register
MCB05568B
Figure 9
RTC Block Diagram
Note: The registers associated with the RTC are only affected by a power reset.
Data Sheet
37
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
The RTC module can be used for different purposes:
•
•
System clock to determine the current time and date
Cyclic time-based interrupt, to provide a system time tick independent of CPU
frequency and other resources
•
•
48-bit timer for long-term measurements
Alarm interrupt at a defined time
Data Sheet
38
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.11
A/D Converters
For analog signal measurement, a 12-bit A/D converters (ADC0) with 10 multiplexed
input channels and a sample and hold circuit have been integrated on-chip. Conversions
use the successive approximation method. The sample time (to charge the capacitors)
and the conversion time are programmable so that they can be adjusted to the external
circuit. The A/D converters can also operate in 8-bit and 10-bit conversion mode, further
reducing the conversion time.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to meet
the application requirements.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically. For applications that require fewer analog input
channels, the remaining channel inputs can be used as digital input port pins.
The A/D converters of the XE161FU support two types of request sources which can be
triggered by several internal and external events.
•
Parallel requests are activated at the same time and then executed in a predefined
sequence.
•
Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing that sequence. All requests are arbitrated according to the priority
level assigned to them.
Data reduction features reduce the number of required CPU access operations allowing
the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed.
Result data can be reduced by limit checking or accumulation of results. Two cascadable
filters build the hardware to generate a configurable moving average.
The Peripheral Event Controller (PEC) can be used to control the A/D converters or to
automatically store conversion results to a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Each A/D converter contains eight result registers which can be concatenated to build a
result FIFO. Wait-for-read mode can be enabled for each result register to prevent the
loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise,
those pins used for analog input can be disconnected from the digital input stages. This
can be selected for each pin separately with the Port x Digital Input Disable registers.
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Broken wire detection for each channel and a multiplexer test mode provide information
to verify the proper operation of the analog signal sources (e.g. a sensor system).
Data Sheet
39
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.12
Universal Serial Interface Channel Modules (USIC)
The XE161FU features the USIC module USIC0. The module provides two serial
communication channels.
The Universal Serial Interface Channel (USIC) module is based on a generic data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during runtime.
Bus
Buffer & Shift Structure Protocol Preprocessors
Pins
Control 0
PPP_A
PPP_B
PPP_C
PPP_D
DBU
0
DSU
0
Control 1
PPP_A
PPP_B
PPP_C
PPP_D
DBU
1
DSU
1
fsys
Fractional
Dividers
Baud rate
Generators
USIC_basic.vsd
Figure 10
General Structure of a USIC Module
The regular structure of the USIC module brings the following advantages:
•
•
•
Higher flexibility through configuration with same look-and-feel for data management
Reduced complexity for low-level drivers serving different protocols
Wide range of protocols with improved performances (baud rate, buffer handling)
Data Sheet
40
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Target Protocols
Each USIC channel can receive and transmit data frames with a selectable data word
width from 1 to 16 bits in each of the following protocols:
•
•
•
UART (asynchronous serial channel)
– module capability: maximum baud rate = fSYS / 4
– data frame length programmable from 1 to 63 bits
– MSB or LSB first
LIN Support (Local Interconnect Network)
– module capability: maximum baud rate = fSYS / 16
– checksum generation under software control
– baud rate detection possible by built-in capture event of baud rate generator
SSC/SPI (synchronous serial channel with or without data buffer)
– module capability: maximum baud rate = fSYS / 2, limited by loop delay
– number of data bits programmable from 1 to 63, more with explicit stop condition
– MSB or LSB first
– optional control of slave select signals
•
•
IIC (Inter-IC Bus)
– supports baud rates of 100 kbit/s and 400 kbit/s
IIS (Inter-IC Sound Bus)
– module capability: maximum baud rate = fSYS / 2
Note: Depending on the selected functions (such as digital filters, input synchronization
stages, sample point adjustment, etc.), the maximum achievable baud rate can be
limited. Please note that there may be additional delays, such as internal or
external propagation delays and driver delays (e.g. for collision detection in UART
mode, for IIC, etc.).
3.13
System Timer
The System Timer consists of a programmable prescaler and two concatenated timers
(10 bits and 6 bits). Both timers can generate interrupt requests. The clock source can
be selected and the timers can also run during power reduction modes.
Therefore, the System Timer enables the software to maintain the current time for
scheduling functions or for the implementation of a clock.
3.14
Window Watchdog Timer
The Window Watchdog Timer is one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Window Watchdog Timer is always enabled after an application reset of the chip. It
can be disabled and enabled at any time by executing the instructions DISWDT and
ENWDT respectively. The software has to service the Window Watchdog Timer before
Data Sheet
41
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
it overflows. If this is not the case because of a hardware or software failure, the Window
Watchdog Timer overflows, generating a reset request.
The Window Watchdog Timer has a ‘programmable window boundary’, it disallows
refresh during the Window Watchdog Timer’s count-up. A refresh during this window-
boundary will cause the Window Watchdog Timer to also generate a reset request.
The Window Watchdog Timer is a 16-bit timer clocked with either the system clock or the
independent wake-up oscillator clock, divided by 16,384 or 256. The Window Watchdog
Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow
further variation of the monitored time interval. Each time it is serviced by the application
software, the Window Watchdog Timer is reloaded.
When clocked by fSYS = 66 MHz, time intervals between 15.2 ns and 16.3 s can be
monitored.
When clocked by fWU = 500 kHz, time intervals between 2.0 µs and 2147.5 s can be
monitored.
The default Watchdog Timer interval after power-up is 0.13 s (@ fWU = 500 kHz).
3.15
Clock Generation
The Clock Generation Unit can generate the system clock signal fSYS for the XE161FU
from a number of external or internal clock sources:
•
•
•
•
External clock signals with pad voltage or core voltage levels
External crystal or resonator using the on-chip oscillator
On-chip clock source for operation without crystal/resonator
Wake-up clock (ultra-low-power) to further reduce power consumption
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.7.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on the EXTCLK pin.
Data Sheet
42
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.16
Parallel Ports
The XE161FU provides up to 33 I/O lines which are organized into 3 input/output ports
and 1 input port. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have alternate input or output functions associated with them. These
alternate functions can be programmed to be assigned to various port pins to support the
best utilization for a given application. For this reason, certain functions appear several
times in Table 10.
All port lines that are not used for alternate functions may be used as general purpose
I/O lines.
Table 10
Summary of the XE161FU’s Ports
Group
Width
I/O Connected Modules
P2
12
I/O Analog inputs, ADC, CC2, DAP/JTAG, GPT12E, SCU,
USIC
P5
6
I
Analog inputs, CCU6, JTAG, GPT12E, CC2
P6
3
I/O Analog inputs, ADC, JTAG, GPT12E
I/O CCU6, GPT12E, DAP/JTAG, SPD, USIC
P10
12
Data Sheet
43
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.17
Power Management
The XE161FU provides the means to control the power it consumes either at a given
time or averaged over a certain duration.
Two mechanisms can be used (and partly in parallel):
•
Clock Generation Management controls the frequency of internal and external
clock signals. Clock signals for currently inactive parts of logic are disabled
automatically. The user can drastically reduce the consumed power by reducing the
XE161FU system clock frequency.
External circuits can be controlled using the programmable frequency output
EXTCLK.
•
Peripheral Management permits temporary disabling of peripheral modules. Each
peripheral can be disabled and enabled separately. The CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally with signals
generated by the external system, or internally by the on-chip wake-up timer. This
supports intermittent operation of the XE161FU by generating cyclic wake-up signals.
Full performance is available to quickly react to action requests while the intermittent
sleep phases greatly reduce the average system power consumption.
Note: When selecting the supply voltage and the clock source and generation method,
the required parameters must be carefully written to the respective bit fields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the intended operation of power supply system and clock system.
Please refer to the Programmer’s Guide.
Data Sheet
44
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
3.18
Instruction Set Summary
Table 11 lists the instructions of the XE161FU.
The addressing modes that can be used with a specific instruction, the function of the
instructions, parameters for conditional execution of instructions, and the opcodes for
each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 11
Mnemonic
ADD(B)
Instruction Set Summary
Description
Bytes
2 / 4
2 / 4
2 / 4
2 / 4
2
Add word (byte) operands
ADDC(B)
SUB(B)
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
SUBC(B)
MUL(U)
(Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit)
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
DIVL(U)
CPL(B)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise exclusive OR, (word/byte operands)
Clear/Set direct bit
2
NEG(B)
AND(B)
OR(B)
2
2 / 4
2 / 4
2 / 4
2
XOR(B)
BCLR/BSET
BMOV(N)
Move (negated) direct bit to direct bit
4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
4
BCMP
Compare direct bit to direct bit
4
BFLDH/BFLDL
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
Compare word (byte) operands
2 / 4
Compare word data to GPR and decrement GPR by 1/2 2 / 4
Compare word data to GPR and increment GPR by 1/2
2 / 4
2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
SHL/SHR
Data Sheet
Shift left/right direct word GPR
2
45
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Table 11
Mnemonic
ROL/ROR
ASHR
Instruction Set Summary (cont’d)
Description
Bytes
Rotate left/right direct word GPR
2
Arithmetic (sign bit) shift right direct word GPR
Move word (byte) data
2
MOV(B)
MOVBS/Z
JMPA/I/R
JMPS
2 / 4
Move byte operand to word op. with sign/zero extension 2 / 4
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
4
4
4
4
JB(C)
Jump relative if direct bit is set (and clear bit)
Jump relative if direct bit is not set (and set bit)
JNB(S)
CALLA/I/R
CALLS
Call absolute/indirect/relative subroutine if condition is met 4
Call absolute subroutine in any code segment
4
4
PCALL
Push direct word register onto system stack and call
absolute subroutine
TRAP
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
2
2
4
PUSH/POP
SCXT
Push direct word register onto system stack and update
register with word operand
RET(P)
Return from intra-segment subroutine
2
(and pop direct word register from system stack)
RETS
Return from inter-segment subroutine
Return from interrupt service subroutine
Software Break
2
RETI
2
SBRK
SRST
2
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
SRVWDT
Unused instruction1)
4
Service Watchdog Timer
4
DISWDT/ENWDT Disable/Enable Watchdog Timer
4
EINIT
End-of-Initialization Register Lock
4
ATOMIC
EXTR
Begin ATOMIC sequence
2
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
2
EXTP(R)
EXTS(R)
2 / 4
2 / 4
Data Sheet
46
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Table 11
Mnemonic
NOP
Instruction Set Summary (cont’d)
Description
Bytes
Null operation
2
4
4
4
4
CoMUL/CoMAC
CoADD/CoSUB
Co(A)SHR
Multiply (and accumulate)
Add/Subtract
(Arithmetic) Shift right
Shift left
CoSHL
CoLOAD/STORE
CoCMP
Load accumulator/Store MAC register
Compare
4
4
4
4
4
4
CoMAX/MIN
CoABS/CoRND
CoMOV
Maximum/Minimum
Absolute value/Round accumulator
Data move
CoNEG/NOP
Negate accumulator/Null operation
1) The Enter Power Down Mode instruction is not used in the XE161FU, due to the enhanced power control
scheme. PWRDN will be correctly decoded, but will trigger no action.
Data Sheet
47
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Functional Description
Data Sheet
48
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4
Electrical Parameters
The operating range for the XE161FU is defined by its electrical parameters. For proper
operation the specified limits must be respected when integrating the device in its target
environment.
4.1
General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
Table 12
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
OH SR -15
Max.
Output current on a pin
when high value is driven
I
I
I
−
mA
mA
Output current on a pin
when low value is driven
OL SR
−
−
15
1)
1)
Overload current
OV SR -5
−
−
5
mA
mA
Absolute sum of overload Σ|IOV
|
−
50
currents
SR
Junction Temperature
Storage Temperature
TJ SR
-40
−
−
−
150
150
6.0
°C
°C
V
T
ST SR -65
Digital supply voltage for
IO pads and voltage
regulators
V
DDP SR -0.5
Voltage on any pin with
respect to ground (Vss)
V
IN SR -0.5
−
VDDP
0.5
+
V
VIN≤ VDDP(max)
1) Overload condition occurs if the input voltage VIN is out of the absolute maximum rating range. In this case the
current must be limited to the listed values by design measures.
Note: Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only. Functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for an extended time may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
48
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.1.1
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XE161FU. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Note: Typical parameter values refer to room temperature and nominal supply voltage,
minimum/maximum
parameter
values
also
include
conditions
of
minimum/maximum temperature and minimum/maximum supply voltage.
Additional details are described where applicable.
Table 13
Parameter
Operating Conditions
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
1)2)
Voltage Regulator Buffer CEVRM
1.0
4.7
μF
Capacitance for DMP_M SR
External Load
Capacitance
CL SR
−
203)
−
pF
pin out
driver= default
4)
5)
System frequency
f
SYS SR
−
−
−
66
5
MHz
Overload current for
analog inputs6)
I
OVA SR -2
mA not subject to
production test
Overload current for digital IOVD SR -5
−
5
mA not subject to
production test
inputs6)
Overload current coupling KOVA
factor for analog inputs7)
CC
−
−
2.5 x
10-4
1.5 x
10-3
-
IOV< 0 mA; not
subject to
production test
1.0 x
10-6
1.0 x
10-4
-
IOV> 0 mA; not
subject to
production test
Data Sheet
49
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 13
Operating Conditions (cont’d)
Parameter
Symbol
Min.
Values
Unit Note /
Test Condition
Typ.
Max.
Overload current coupling KOVD
factor for digital I/O pins CC
−
−
1.0 x
10-2
3.0 x
10-2
IOV< 0 mA; not
subject to
production test
1.0 x
10-4
5.0 x
10-3
IOV> 0 mA; not
subject to
production test
Absolute sum of overload Σ|IOV
currents SR
|
−
−
−
30
mA not subject to
production test
Digital core supply voltage VDDIM
1.5
−
V
V
for domain M8)
CC
Digital supply voltage for
IO pads and voltage
regulators
V
DDP SR 3.0
−
5.5
Digital ground voltage
V
SS SR
−
0
−
V
1) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate
buffer capacitors with the recomended values shall be connected as close as possible to each VDDIM pin to
keep the resistance of the board tracks below 2 Ohm. Connect all VDDIM pins together. The minimum
capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values
slightly increase the startup time.
2) Use one Capacitor for each pin.
3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties
section.
4) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
5) The operating frequency range may be reduced for specific device types. This is indicated in the device
designation (...FxxL). 40 MHz devices are marked ...F40L.
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application. Overload conditions must not
occur on pin XTAL1.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pins leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.The total current through a pin is |ITOT| = |IOZ
|
+ (|IOV| KOV). The additional error current may distort the input voltage on analog inputs.
Data Sheet
50
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
8) Value is controlled by on-chip regulator.
4.2
Voltage Range definitions
The XE161FU timing depends on the supply voltage. If such a dependency exists the
timing values are given for 2 voltage areas commonly used. The voltage areas are
defined in the following tables.
Table 14
Upper Voltage Range Definition
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
DDP SR 4.5
Typ.
Max.
Digital supply voltage for
IO pads and voltage
regulators
V
5.0
5.5
V
Table 15
Lower Voltage Range Definition
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
DDP SR 3.0
Typ.
Max.
Digital supply voltage for
IO pads and voltage
regulators
V
3.3
4.5
V
4.2.1
Parameter Interpretation
The parameters listed in the following include both the characteristics of the XE161FU
and its demands on the system. To aid in correctly interpreting the parameters when
evaluating them for a design, they are marked accordingly in the column “Symbol”:
CC (Controller Characteristics):
The logic of the XE161FU provides signals with the specified characteristics.
SR (System Requirement):
The external system must provide signals with the specified characteristics to the
XE161FU.
Data Sheet
51
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.3
DC Parameters
These parameters are static or average values that may be exceeded during switching
transitions (e.g. output current).
The XE161FU can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must remain within 10 percent of the
selected nominal supply voltage. It cannot vary across the full operating voltage range.
Because of the supply voltage restriction and because electrical behavior depends on
the supply voltage, the parameters are specified separately for the upper and the lower
voltage range.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
Leakage current is strongly dependent on the operating temperature and the voltage
level at the respective pin. The maximum values in the following tables apply under worst
case conditions, i.e. maximum temperature and an input level equal to the supply
voltage.
The value for the leakage current in an application can be determined by using the
respective leakage derating formula (see tables) with values from that application.
The pads of the XE161FU are designed to operate in various driver modes. The DC
parameter specifications refer to the pad current limits specified in Section 4.7.4.
Data Sheet
52
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Pullup/Pulldown Device Behavior
Most pins of the XE161FU feature pullup or pulldown devices. For some special pins
these are fixed; for the port pins they can be selected by the application.
The specified current values indicate how to load the respective pin depending on the
intended signal level. Figure 11 shows the current paths.
The shaded resistors shown in the figure may be required to compensate system pull
currents that do not match the given limit values.
VDDP
Pullup
Pulldown
VSS
MC_XC2X_PULL
Figure 11
Pullup/Pulldown Current Definition
Data Sheet
53
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.3.1
DC Parameters for Upper Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV
.
Note: Operating Conditions apply.
Table 16 is valid under the following conditions: VDDP≤ 5.5 V; VDDPtyp. 5 V; VDDP≥ 4.5 V
Table 16
DC Characteristics for Upper Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Pin capacitance (digital
inputs/outputs).
CIO CC
−
10
pF
not subject to
production test
Input Hysteresis1)
HYS CC 0.11 x
−
−
V
RS= 0 Ohm
VDDP
Absolute input leakage
|IOZ1
|
−
−
−
10
200
nA
VIN> VSS ;
VIN< VDDP
current on pins of analog CC
ports2)
Absolute input leakage
|IOZ2
CC
|
0.2
0.2
−
5
μA
μA
μA
TJ≤ 110 °C;
VIN> VSS ;
VIN< VDDP
current for all other pins.
2)3)
10
−
TJ≤ 150 °C;
VIN> VSS
;
VIN< VDDP
Pull Level Force Current4) |IPLF| SR 220
VIN≥ VIHmin
(pulldown_ena
bled);
VIN≤ VILmax
(pullup_enable
d)
Pull Level Keep Current5) |IPLK
|
−
−
−
30
μA
VIN≥ VIHmin
(pullup_enable
d);
VIN≤ VILmax
(pulldown_ena
bled)
SR
Input high voltage (all
except XTAL1)
V
IH SR 0.7 x
VDDP
0.3
+
V
VDDP
Data Sheet
54
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 16
DC Characteristics for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
VIL SR -0.3
Max.
Input low voltage
(all except XTAL1)
Output High voltage6)
0.3 x
VDDP
V
V
V
V
OH CC VDDP
-
-
−
−
−
IOH≥ IOHmax
1.0
7)
VDDP
−
IOH≥ IOHnom
0.4
8)
Output Low Voltage6)
V
OL CC
−
−
−
−
0.4
1.0
V
V
IOL≤ IOLnom
IOL≤ IOLmax
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
Please refer to the definition of the overload coupling factor KOV
.
3) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
4) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull
device.
5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level.
6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
8) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS
OH->VDDP). However, only the levels for nominal output currents are verified.
,
V
Data Sheet
55
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.3.2
DC Parameters for Lower Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV
.
Note: Operating Conditions apply.
Table 17 is valid under the following conditions: VDDP≥ 3.0 V; VDDPtyp. 3.3 V;
VDDP≤ 4.5 V
Table 17
DC Characteristics for Lower Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Pin capacitance (digital
inputs/outputs).
CIO CC
−
10
pF
not subject to
production test
Input Hysteresis1)
HYS CC 0.07 x
−
−
V
RS= 0 Ohm
VDDP
Absolute input leakage
|IOZ1
|
−
−
−
10
200
nA
VIN> VSS ;
VIN< VDDP
current on pins of analog CC
ports2)
Absolute input leakage
|IOZ2
CC
|
0.2
0.2
−
2
6
−
μA
μA
μA
TJ≤ 110 °C;
VIN> VSS ;
VIN< VDDP
current for all other pins.
2)3)
TJ≤ 150 °C;
VIN> VSS
;
VIN< VDDP
Pull Level Force Current4) |IPLF| SR 150
VIN≥ VIHmin
(pulldown_ena
bled);
VIN≤ VILmax
(pullup_enable
d) ;
Pull Level Keep Current5) |IPLK
|
−
−
10
μA
VIN≥ VIHmin
(pullup_enable
d);
SR
VIN≤ VILmax
(pulldown_ena
bled)
Data Sheet
56
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 17
DC Characteristics for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
IH SR 0.7 x
VDDP
VIL SR -0.3
Max.
Input high voltage (all
except XTAL1)
V
VDDP
0.3
+
V
V
V
V
Input low voltage
(all except XTAL1)
Output High voltage6)
−
−
−
0.3 x
VDDP
V
OH CC VDDP
-
-
−
IOH≥ IOHmax
1.0
7)
VDDP
−
IOH≥ IOHnom
0.4
8)
Output Low Voltage6)
V
OL CC
−
−
−
−
0.4
1.0
V
V
IOL≤ IOLnom
IOL≤ IOLmax
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
Please refer to the definition of the overload coupling factor KOV
.
3) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
4) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull
device.
5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level.
6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
8) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS
OH->VDDP). However, only the levels for nominal output currents are verified.
,
V
Data Sheet
57
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.3.3
Power Consumption
The power consumed by the XE161FU depends on several factors such as supply
voltage, operating frequency, active circuits, and operating temperature. The power
consumption specified here consists of two components:
•
•
The switching current IS depends on the device activity
The leakage current ILK depends on the device temperature
To determine the actual power consumption, always both components, switching current
IS and leakage current ILK must be added:
I
DDP = IS + ILK.
Note: The power consumption values are not subject to production test. They are
verified by design/characterization.
To determine the total power consumption for dimensioning the external power
supply, also the pad driver currents must be considered.
The given power consumption parameters and their values refer to specific operating
conditions:
•
Active mode:
Regular operation, i.e. peripherals are active, code execution out of Flash.
Stopover mode:
•
Crystal oscillator and PLL stopped, Flash switched off, clock in most parts of domain
DMP_M stopped.
Note: The maximum values cover the complete specified operating range of all
manufactured devices.
The typical values refer to average devices under typical conditions, such as
nominal supply voltage, room temperature, application-oriented activity.
After a power reset, the decoupling capacitors for VDDIM are charged with the
maximum possible current.
For additional information, please refer to Section 5.2, Thermal Considerations.
Note: Operating Conditions apply.
Data Sheet
58
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 18
Switching Power Consumption
Symbol
Parameter
Values
Typ.
Unit Note /
Test Condition
Min.
Max.
7 + 0.6 mA power_mode=
Power supply current
(active)withall peripherals CC
active and EVVRs on
ISACT
−
5.5 +
0.4 x
fSYS
1)
x fSYS
active ;
1)
voltage_range=
both 2)3)4)
Power supply current in
stopover mode, EVVRs on
I
SSO CC
−
0.7
2.0
mA power_mode=
stopover ;
voltage_range=
both
1)
fSYS in MHz
2) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current
consumed by the pin output drivers. A small current is consumed because the drivers input stages are
switched.
3) Please consider the additional conditions described in section "Active Mode Power Supply Current".
4) The pad supply voltage only has a minor influence on this parameter.
Active Mode Power Supply Current
The actual power supply current in active mode not only depends on the system
frequency but also on the configuration of the XE161FU’s subsystem.
Besides the power consumed by the device logic the power supply pins also provide the
current that flows through the pin output drivers.
A small current is consumed because the drivers’ input stages are switched.
Data Sheet
59
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
IS [mA]
60
50
40
30
20
10
ISACTmax
ISACTtyp
fSYS [MHz]
20
40
60
80
MC_XC2XU_IS
Figure 12
Supply Current in Active Mode as a Function of Frequency
Note: Operating Conditions apply.
Table 19
Leakage Power Consumption
Symbol
Parameter
Values
Typ.
0.03
0.4
Unit Note /
Test Condition
Min.
Max.
0.04
0.95
4.6
Leakage supply current1)2)
I
LK1 CC
−
−
−
−
mA TJ= 25 °C
mA TJ= 85 °C
mA TJ= 125 °C
mA TJ= 150 °C
1.5
3.3
10.1
1) The supply current caused by leakage depends mainly on the junction temperature and the supply voltage.
The temperature difference between the junction temperature TJ and the ambient temperature TA must be
taken into account. As this fraction of the supply current does not depend on device activity, it must be added
to other power consumption values.
2) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs
(including pins configured as outputs) are disconnected.
Leakage Power Consumption Calculation
The leakage power consumption can be calculated according to the following formulas:
Data Sheet
60
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
ILK1 = 440,000 + e-α with α = 5000 / (273 + B×TJ)
Parameter B must be replaced by
•
•
1.0 for typical values
1.3 for maximum values
ILK [mA]
ILK1max
12
10
8
6
ILK1typ
4
2
TJ [°C]
-50
0
50
100 125 150
MC_XC2XU_ILKN
Figure 13
Leakage Supply Current as a Function of Temperature
Data Sheet
61
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.4
Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance.
Note: Operating Conditions apply.
Table 20
ADC Parameters for All Voltage Ranges
Parameter
Symbol
Values
Typ.
9
Unit Note /
Test Condition
Min.
Max.
Switched capacitance at CAINSW
an analog input
−
20
pF
pF
pF
pF
not subject to
CC
production test
1)
Total capacitance at an
analog input
CAINT
CC
−
−
−
20
15
20
30
30
40
not subject to
production test
1)
Switched capacitance at CAREFSW
the reference input
not subject to
CC
production test
1)
Total capacitance at the
reference input
CAREFT
CC
not subject to
production test
1)
Broken wire detection
delay against VAGND2)
t
t
t
BWG CC −
−
−
503)
504)
Broken wire detection
delay against VAREF2)
BWR CC
c8 CC
−
Conversion time for 8-bit
result2)
(10 + STC x tADCI + 2 x
tSYS
Conversion time for 10-bit tc10 CC (12 + STC x tADCI + 2 x
result2)
tSYS
Conversion time for 12-bit tc12 CC (16 + STC x tADCI + 2 x
result2)
tSYS
Analog reference ground VAGND
VSS
0.05
-
−
−
−
1.5
V
V
V
SR
5)
Analog input voltage
range
V
AIN SR VAGND
VAREF
Analog reference voltage VAREF
VAGND
VDDPB
SR
+ 1.0
+ 0.05
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
Data Sheet
62
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
2) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 µs. Result below 10% (66H)
4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high
temperature. Result above 80% (332H)
5)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
Table 21
ADC Parameters for Upper Voltage Range
Parameter
Symbol
Values
Typ.
0.9
Unit Note /
Test Condition
Min.
Max.
Input resistance of the
selected analog channel
R
AIN CC
−
1.5
kOh not subject to
production test
m
1)
Input resistance of the
reference input
RAREF
CC
−
0.5
1
kOh not subject to
m
production test
1)
Differential Non-Linearity |EADNL
|
−
−
−
−
2.5
2.5
2.0
2.0
−
5.0
6.0
4.0
4.0
20
LSB
LSB
LSB
LSB
Error2)3)4)5)
CC
Gain Error2)3)4)5)
|EAGAIN|
CC
Integral Non-
Linearity2)3)4)5)
|EAINL|
CC
Offset Error2)3)4)5)
|EAOFF|
CC
Analog clock frequency
f
ADCI SR 2
2
MHz Std. reference
input (VAREF
)
−
17.5
5.5
7.0
11.5
MHz Alt. reference
input (CH0)
Total Unadjusted Error3)4) |TUE|
CC
−
−
−
2.5
−
LSB
6)7)
Wakeup time from analog tWAF CC
powerdown, fast mode
μs
μs
Wakeup time from analog tWAS CC
−
powerdown, slow mode
Data Sheet
63
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and VDDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below VDDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,
DNL, INL, Gain and Offset errors increase also by the factor 1/k.
5) If the analog reference voltage is > VDDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at VAREF = VDDPB = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
Table 22
ADC Parameters for Lower Voltage Range
Parameter
Symbol
Values
Typ.
1.4
Unit Note /
Test Condition
Min.
Max.
Input resistance of the
selected analog channel
R
AIN CC
−
2.5
kOh not subject to
production test
m
1)
Input resistance of the
reference input
RAREF
CC
−
1.0
2.0
kOh not subject to
m
production test
1)
Differential Non-Linearity |EADNL
|
−
−
−
−
2.5
3.0
2.5
2.0
−
5.5
LSB
LSB
LSB
LSB
Error2)3)4)5)
CC
Gain Error2)3)4)5)
|EAGAIN
|
8.0
CC
Integral Non-
Linearity2)3)4)5)
|EAINL
CC
|
7.5
Offset Error2)3)4)5)
|EAOFF
|
5.5
CC
Analog clock frequency
f
ADCI SR 2
2
16.7
12.1
7.5
MHz Std. reference
input (VAREF
)
−
MHz Alt. reference
input (CH0)
Total Unadjusted Error3)4) |TUE|
CC
−
2.5
LSB
6)7)
Data Sheet
64
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 22
ADC Parameters for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Wakeup time from analog tWAF CC
powerdown, fast mode
−
8.5
μs
μs
Wakeup time from analog tWAS CC
−
−
15.0
powerdown, slow mode
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and VDDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below VDDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,
DNL, INL, Gain and Offset errors increase also by the factor 1/k.
5) If the analog reference voltage is > VDDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at VAREF = VDDPB = 3.3 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
A/D Converter
RSource
RAIN, On
VAIN
-
CExt
CAINT CAINS
CAINS
MCS05570
Figure 14
Equivalent Circuitry for Analog Inputs
Sample time and conversion time of the XE161FU’s A/D converters are programmable.
The timing above can be calculated using Table 23.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Data Sheet
65
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 23
A/D Converter Computation Table
GLOBCTR.5-0
(DIVA)
A/D Converter
Analog Clock fADCI
INPCRx.7-0
Sample Time1)
tS
(STC)
00H
01H
02H
:
000000B
000001B
000010B
:
fSYS
tADCI × 2
f
f
f
f
f
SYS / 2
tADCI × 3
SYS / 3
tADCI × 4
SYS / (DIVA+1)
SYS / 63
tADCI × (STC+2)
tADCI × 256
tADCI × 257
111110B
111111B
FEH
FFH
SYS / 64
1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase).
Converter Timing Example A:
Assumptions:
Analog clock
Sample time
fSYS = 66 MHz (i.e. tSYS = 15.2 ns), DIVA = 03H, STC = 00H
fADCI = fSYS / 4 = 16.5 MHz, i.e. tADCI = 60.6 ns
tS
= tADCI × 2 = 121.2 ns
Conversion 12-bit:
tC12 = 16 × tADCI + 2 × tSYS = 16 × 60.6 ns + 2 × 15.2 ns = 1.0 μs
Conversion 10-bit:
tC10 = 12 × tADCI + 2 × tSYS = 12 × 60.6 ns + 2 × 15.2 ns = 0.758 μs
Conversion 8-bit:
tC8
= 10 × tADCI + 2 × tSYS = 10 × 60.6 ns + 2 × 15.2 ns = 0.636 μs
Converter Timing Example B:
Assumptions:
Analog clock
Sample time
fSYS = 40 MHz (i.e. tSYS = 25 ns), DIVA = 01H, STC = 00H
fADCI = fSYS / 2 = 20 MHz, i.e. tADCI = 50 ns
tS = tADCI × 2 = 100 ns
Conversion 12-bit:
tC12 = 16 × tADCI + 2 × tSYS = 16 × 50 ns + 2 × 25 ns = 0.85 μs
Conversion 10-bit:
tC10 = 12 × tADCI + 2 × tSYS = 12 × 50 ns + 2 × 25 ns = 0.65 μs
Data Sheet
66
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Conversion 8-bit:
tC8
= 10 × tADCI + 2 × tSYS = 10 × 50 ns + 2 × 25 ns = 0.55 μs
Data Sheet
67
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.5
System Parameters
The following parameters specify several aspects which are important when integrating
the XE161FU into an application system.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 24
Various System Parameters
Parameter
Symbol
Min.
Values
Typ.
−
Unit Note /
Test Condition
Max.
Short-term deviation of
internal clock source
frequency1)
ΔfINT CC -1
1
%
ΔTJ = ≤ 10°C
Internal clock source
frequency
f
f
INT CC 4.8
5.0
5.2
MHz
Wakeup clock source
frequency2)
WU CC 400
210
−
700
390
260
200
2.4
kHz FREQSEL= 00
kHz FREQSEL= 01
kHz FREQSEL= 10
kHz FREQSEL= 11
−
140
−
110
−
Startup time from power-
on with code execution
from Flash
t
SPO CC 1.4
1.9
ms
f
WU = 500 kHz
Startup time from stopover tSSO CC 11 /
−
12 /
fWU
μs
3)
3)
mode with code execution
fWU
from PSRAM
5)
Core voltage (PVC)
supervision level
V
PVC CC VLV
-
VLV
VLV
VLV
VLV
0.074)
VLV
0.15
+
V
V
V
0.03
Supply watchdog (SWD) VSWD
supervision level CC
VLV
-
+
voltage_range=
lower 5)
0.106)
VLV
0.15
-
VLV
+
voltage_range=
upper 5)
0.15
1) The short-term frequency deviation refers to a timeframe of a few hours and is measured relative to the current
frequency at the beginning of the respective timeframe. This parameter is useful to determine a time span for
re-triggering a LIN synchronization.
2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to
production test - verified by design/characterization.
3)
fWU in MHz.
Data Sheet
68
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4) This value includes a hysteresis of approximately 50 mV for rising voltage.
5) LV = selected SWD voltage level
V
6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.
Conditions for tSPO Timing Measurement
The time required for the transition from Power-On to Base mode is called tSPO. It is
measured under the following conditions:
Precondition: The pad supply is valid, i.e. VDDPB is above 3.0 V and remains above 3.0 V
even though the XE161FU is starting up. No debugger is attached.
Start condition: Power on reset is removed (PORST = 1).
End condition: External pin toggle caused by first user instruction executed from Flash
after startup.
Conditions for tSSO Timing Measurement
The time required for the transition from Stopover to Stopover Waked-Up mode is
called tSSO. It is measured under the following conditions:
Precondition: The Stopover mode has been entered using the procedure defined in the
Programmer’s Guide.
Start condition: Pin toggle on ESR pin triggering the startup sequence.
End condition: External pin toggle caused by first user instruction executed from PSRAM
after startup.
Data Sheet
69
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Coding of bit fields LEVxV in SWD Configuration Registers
After power-on the supply watch dog is preconfigured to operate in the lower voltage
range.
Table 25
Code
Coding of bit fields LEVxV in Register SWDCON0
Default Voltage Level
Notes1)
0000B
-
out of valid operation range
LEV1V: reset request
step width is 0.1 V
0001B
3.0 V
0010B - 0101B
0110B
3.1 V - 3.4 V
3.6 V
0111B
4.0 V
1000B
4.2 V
1001B
4.5 V
LEV2V: no request
step width is 0.1 V
1010B - 1110B
1111B
4.6 V - 5.0 V
5.5 V
1) The indicated default levels are selected automatically after a power reset.
Coding of bit fields LEVxV in PVC Configuration Registers
The core voltages are controlled internally to the nominal value of 1.5 V; a variation of
±10 % is allowed. These operation conditions limit the possible PVC monitoring values
to the predefined reset values shown in Table 26.
Table 26
Code
Coding of bit fields LEVxV in Registers PVCyCONz
Default Voltage Level
Notes1)
000B - 011B
100B
-
out of valid operation range
LEV1V: reset request
LEV2V: interrupt request2)
out of valid operation range
1.35 V
1.45 V
-
101B
110B - 111B
1) The indicated default levels are selected automatically after a power reset.
2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and PVC levels, this
interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is,
therefore, recommended not to use this warning level.
Data Sheet
70
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.6
Flash Memory Parameters
The XE161FU is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XE161FU’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 27
Flash Parameters
Symbol
Parameter
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
11)
Parallel Flash module
program/erase limit
depending on Flash read
activity
NPP SR
−
NFL_RD≤ 1
Flash erase endurance
for security pages
NSEC SR 10
−
−
cycle tRET≥ 20 years
s
Flash wait states2)
NWSFLASH
SR
1
2
3
4
−
−
−
fSYS≤ 8 MHz
fSYS≤ 13 MHz
fSYS≤ 17 MHz
−
−
−
−
−
73)
−
fSYS> 17 MHz
Erase time per
sector/page
t
t
t
ER CC
PR CC
8.0
ms
ms
Programming time per
page
−
33)
−
3.5
−
Data retention time
RET CC 20
DD SR 32
year NER≤ 1,000 cycl
s
es
Drain disturb limit
N
−
−
cycle
s
Data Sheet
71
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 27
Flash Parameters (cont’d)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
15000 cycle tRET≥ 5 years;
Number of erase cycles
NER SR
−
−
s
Valid for up to
64 user
selected
sectors (data
storage)
−
−
1000
cycle tRET≥ 20 years
s
1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one Flash
module or from PSRAM. The Flash module that delivers code/data can, of course, not be erased/programmed.
2) Value of IMB_IMBCTRL.WSFLASH.
3) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
Access to the XE161FU Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Data Sheet
72
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.7
AC Parameters
These parameters describe the dynamic behavior of the XE161FU.
4.7.1
Testing Waveforms
These values are used for characterization and production testing (except pin XTAL1).
Output delay
Hold time
Output delay
Hold time
0.8 VDDP
0.7 VDDP
Input Signal
(driven by tester)
0.3 VDDP
0.2 VDDP
Output Signal
(measured)
Output timings refer to the rising edge of CLKOUT.
Input timings are calculated from the time, when the input signal reaches
VIH or VIL, respectively.
MCD05556C
Figure 15
Input Output Waveforms
V
Load + 0.1 V
V
V
OH - 0.1 V
OL + 0.1 V
Timing
Reference
Points
V
Load - 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded VOH /VOL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 16
Floating Waveforms
Data Sheet
73
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.7.2
Definition of Internal Timing
The internal operation of the XE161FU is controlled by the internal system clock fSYS
.
Because the system clock signal fSYS can be generated from a number of internal and
external sources using different mechanisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate fSYS. This must be considered when calculating the timing
for the XE161FU.
Phase Locked Loop Operation (1:N)
fIN
fSYS
TCS
Direct Clock Drive (1:1)
fIN
fSYS
TCS
Prescaler Operation (N:1)
fIN
fSYS
TCS
MC_XC2X_CLOCKGEN
Figure 17
Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 17 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Data Sheet
74
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
f
SYS = fIN.
The frequency of fSYS is the same as the frequency of fIN. In this case the high and low
times of fSYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
f
SYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In
this case the high and low times of fSYS are determined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f
SYS = fOSC / 1024.
4.7.2.1 Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (fSYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of fSYS so that it is
locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDIM
.
Data Sheet
75
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the given circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 18).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles
is K2 × T, where T is the number of consecutive fSYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
f
SYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
max = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97 × [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63 × [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
Data Sheet
76
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Acc. jitter DT
ns
±9
fSYS = 33 MHz fSYS = 66 MHz
fVCO = 66 MHz
fVCO = 132MHz
±8
±7
±6
±5
±4
±3
±2
±1
Cycles
100
T
0
1
20
40
60
80
MC_XC2X_JITTER
Figure 18
Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF.
The maximum peak-to-peak noise on the pad supply voltage (measured between
V
DDPB pin and VSS pin) is limited to a peak-to-peak voltage of VPP = 50 mV. This
can be achieved by appropriate blocking of the supply voltage as close as possible
to the supply pins and using PCB supply and ground planes.
PLL frequency band selection
Different frequency bands can be selected for the VCO so that the operation of the PLL
can be adjusted to a wide range of input and output frequencies:
Data Sheet
77
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 28
System PLL Parameters
Parameter
Symbol
Min.
Values
Typ.
−
Unit Note /
Test Condition
Max.
VCO output frequency
fVCO CC 50
110
MHz VCOSEL= 00B;
VCOmode=
controlled
10
−
−
−
40
MHz VCOSEL= 00B;
VCOmode= free
running
100
160
80
MHz VCOSEL= 01B;
VCOmode=
controlled
20
MHz VCOSEL= 01B;
VCOmode= free
running
4.7.2.2 Wakeup Clock
When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is
derived from the low-frequency wakeup clock source:
f
SYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consumption.
4.7.2.3 Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bit fields, to avoid unintended
intermediate states.
Many applications change the frequency of the system clock (fSYS) during operation in
order to optimize system performance and power consumption. Changing the operating
frequency also changes the switching currents, which influences the power supply.
To ensure proper operation of the on-chip EVRs while they generate the core voltage,
the operating frequency shall only be changed in certain steps. This prevents overshoots
and undershoots of the supply voltage.
To avoid the indicated problems, recommended sequences are provided which ensure
the intended operation of the clock system interacting with the power system.
Please refer to the Programmer’s Guide.
Data Sheet
78
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.7.3
External Clock Input Parameters
These parameters specify the external clock generation for the XE161FU. The clock can
be generated in two ways:
•
•
By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
By supplying an external clock signal. This clock signal can be supplied either to
pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).
If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH.
If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (t1 … t4) are only valid for an external clock
input signal.
Note: Operating Conditions apply.
Table 29
External Clock Input Characteristics
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Oscillator frequency
f
OSC SR
4
40
MHz Input= Clock
Signal
4
−
−
16
20
MHz Input= Crystal
or Resonator
XTAL1 input current
absolute value
|IIL| CC
−
μA
Input clock high time
Input clock low time
Input clock rise time
Input clock fall time
t1 SR
t2 SR
t3 SR
t4 SR
6
6
−
−
−
−
8
8
−
−
−
8
8
−
ns
ns
ns
ns
Input voltage amplitude on VAX1 SR 0.3 x
V
V
V
V
fOSC≥ 4 MHz;
fOSC≤ 16 MHz
XTAL11)
VDDIM
0.4 x
VDDIM
−
−
−
−
fOSC≥ 16 MHz;
fOSC≤ 25 MHz
0.5 x
VDDIM
−
fOSC≥ 25 MHz;
fOSC≤ 40 MHz
2)
Input voltage range limits
for signal on XTAL1
V
IX1 SR -1.7 +
1.7
VDDIM
1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by VIX1
.
Data Sheet
79
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
2) Overload conditions must not occur on pin XTAL1.
Note: For crystal/resonator operation, it is strongly recommended to measure the
oscillation allowance (negative resistance) in the final target system (layout) to
determine the optimum parameters for oscillator operation.
The manufacturers of crystals and ceramic resonators offer an oscillator
evaluation service. This evaluation checks the crystal/resonator specification
limits to ensure a reliable oscillatior operation.
t1
t3
0.9 VAX1
VOFF
VAX1
0.1 VAX1
t2
t4
tOSC = 1/fOSC
MC_EXTCLOCK
Figure 19
External Clock Drive XTAL1
Data Sheet
80
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.7.4
Pad Properties
The output pad drivers of the XE161FU can operate in several user-selectable modes.
Strong driver mode allows controlling external components requiring higher currents
such as power bridges or LEDs. Reducing the driving power of an output pad reduces
electromagnetic emissions (EME). In strong driver mode, selecting a slower edge
reduces EME.
The dynamic behavior, i.e. the rise time and fall time, depends on the applied external
capacitance that must be charged and discharged. Timing values are given for a
capacitance of 20 pF, unless otherwise noted.
In general, the performance of a pad driver depends on the available supply voltage
V
DDP. Therefore the following tables list the pad parameters for the upper voltage range
and the lower voltage range, respectively.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 30 is valid under the following conditions: VDDP≤ 5.5 V; VDDPtyp. 5 V; VDDP≥ 4.5 V
Table 30
Standard Pad Parameters for Upper Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Maximum output driver
IOmax
−
3.0
mA Driver_Strength
= Medium
current (absolute value)1) CC
−
−
−
−
−
−
−
−
−
−
5.0
0.5
1.0
1.6
0.25
mA Driver_Strength
= Strong
mA Driver_Strength
= Weak
Nominal output driver
current (absolute value)
IOnom
CC
mA Driver_Strength
= Medium
mA Driver_Strength
= Strong
mA Driver_Strength
= Weak
Data Sheet
81
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 30
Standard Pad Parameters for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Rise and Fall times (10% - tRF CC
90%)
−
38 +
0.6 x
CL
ns
ns
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Medium
−
−
−
−
−
−
1 +
0.45 x
CL
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Soft
16 +
0.45 x
CL
ns
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Slow
200 + ns
2.5 x
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Weak
CL
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and Σ-
I
OH) must remain below 25 mA.
Table 31
Standard Pad Parameters for Lower Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Maximum output driver
IOmax
−
1.8
mA Driver_Strength
= Medium
current (absolute value)1) CC
−
−
−
−
3.0
0.3
mA Driver_Strength
= Strong
mA Driver_Strength
= Weak
Data Sheet
82
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 31
Standard Pad Parameters for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Nominal output driver
current (absolute value)
IOnom
CC
−
0.8
mA Driver_Strength
= Medium
−
−
−
−
−
−
1.0
mA Driver_Strength
= Strong
0.15
mA Driver_Strength
= Weak
Rise and Fall times (10% - tRF CC
90%)
73 +
0.85 x
CL
ns
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Medium
−
−
−
−
−
−
6 + 0.6 ns
x CL
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Soft
33 +
0.6 x
CL
ns
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Slow
385 + ns
3.25 x
CL
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Weak
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and Σ-
I
OH) must remain below 25 mA.
Data Sheet
83
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.7.5
Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 32
is valid under the following conditions: CL= 20 pF; SSC= master ;
voltage_range= upper
Table 32
USIC SSC Master Mode Timing for Upper Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Slave select output SELO t1 CC
active to first SCLKOUT
transmit edge
tSYS
-
−
ns
81)
Slave select output SELO t2 CC
inactive after last
tSYS
-
−
−
ns
61)
SCLKOUT receive edge
Data output DOUT valid
time
t3 CC
-6
−
−
9
ns
ns
Receive data input setup t4 SR
time to SCLKOUT receive
edge
31
−
Data input DX0 hold time t5 SR
from SCLKOUT receive
edge
-4
−
−
ns
1)
tSYS = 1 / fSYS
Data Sheet
84
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 33
is valid under the following conditions: CL= 20 pF; SSC= master ;
voltage_range= lower
Table 33
USIC SSC Master Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Slave select output SELO t1 CC
active to first SCLKOUT
transmit edge
tSYS
-
−
ns
101)
Slave select output SELO t2 CC
inactive after last
tSYS
-
−
−
ns
91)
SCLKOUT receive edge
Data output DOUT valid
time
t3 CC
-7
−
−
11
ns
ns
Receive data input setup t4 SR
time to SCLKOUT receive
edge
40
−
Data input DX0 hold time t5 SR
from SCLKOUT receive
edge
-5
−
−
ns
1)
tSYS = 1 / fSYS
Table 34
is valid under the following conditions: CL= 20 pF; SSC= slave ;
voltage_range= upper
Table 34
USIC SSC Slave Mode Timing for Upper Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Select input DX2 setup to
first clock input DX1
transmit edge1)
t
10 SR
10
−
ns
ns
ns
Select input DX2 hold after t11 SR
last clock input DX1
7
7
−
−
−
−
receive edge1)
Receive data input setup
time to shift clock receive
edge1)
t12 SR
Data Sheet
85
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 34
USIC SSC Slave Mode Timing for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Data input DX0 hold time
from clock input DX1
receive edge1)
t
t
13 SR
14 CC
5
−
ns
Data output DOUT valid
time
7
−
33
ns
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Table 35
is valid under the following conditions: CL= 20 pF; SSC= slave ;
voltage_range= lower
Table 35
USIC SSC Slave Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Select input DX2 setup to
first clock input DX1
transmit edge1)
t
10 SR
10
−
ns
ns
ns
ns
ns
Select input DX2 hold after t11 SR
last clock input DX1
7
7
5
8
−
−
−
−
−
receive edge1)
Receive data input setup
time to shift clock receive
edge1)
t
t
t
12 SR
13 SR
14 CC
−
Data input DX0 hold time
from clock input DX1
receive edge1)
−
Data output DOUT valid
time
41
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
86
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Master Mode Timing
t1
t2
Select Output
SELOx
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
Last Receive
Transmit
Edge
First Transmit
Edge
Edge
t3
t3
Data Output
DOUT
t4
t4
t5
t5
Data Input
DX0
Data
valid
Data
valid
Slave Mode Timing
t10
t11
Select Input
DX2
Inactive
Active
Inactive
Clock Input
DX1
Receive
Edge
Last Receive
Edge
First Transmit
Edge
Transmit
Edge
t12
t12
t13
t13
Data Input
DX0
Data
valid
Data
valid
t14
t14
Data Output
DOUT
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signa.l
USIC_SSC_TMGX.VSD
Figure 20
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
Data Sheet
87
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
4.7.6
Debug Interface Timing
The debugger can communicate with the XE161FU via 1-pin SPD interface, via the 2-
pin DAP interface or via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 36 is valid under the following conditions: CL= 20 pF; voltage_range= upper
Table 36
DAP Interface Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
DAP0 clock period
DAP0 high time
t
t
t
t
t
t
11 SR
12 SR
13 SR
14 SR
15 SR
16 SR
1001)
−
−
−
−
−
−
−
−
−
4
4
−
ns
ns
ns
ns
ns
ns
8
8
−
−
6
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t
t
17 SR
19 CC
6
−
−
−
ns
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
92
95
pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS
.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
88
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 37 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Table 37
DAP Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
DAP0 clock period
DAP0 high time
t
t
t
t
t
t
11 SR
12 SR
13 SR
14 SR
15 SR
16 SR
1001)
−
−
−
−
−
−
−
−
−
4
4
−
ns
ns
ns
ns
ns
ns
8
8
−
−
6
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t
t
17 SR
19 CC
6
−
−
−
ns
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
87
92
pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS
.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VDDP
0.1 VDDP
0.5 VDDP
t15
t14
t12
t13
MC_DAP0
Figure 21
Test Clock Timing (DAP0)
Data Sheet
89
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
DAP0
DAP1
t16
t17
MC_DAP1_RX
Figure 22
DAP Timing Host to Device
t11
DAP1
t19
MC_DAP1_TX
Figure 23
DAP Timing Device to Host
Note: The transmission timing is determined by the receiving debugger by evaluating the
sync-request synchronization pattern telegram.
Data Sheet
90
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 38 is valid under the following conditions: CL= 20 pF; voltage_range= upper
Table 38
JTAG Interface Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
1001)
16
16
−
Typ.
Max.
2)
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
−
−
−
−
−
−
−
−
−
8
8
−
ns
ns
ns
ns
ns
ns
TCK low time
TCK clock rise time
TCK clock fall time
−
TDI/TMS setup to TCK
rising edge
6
TDI/TMS hold after TCK
rising edge
t7 SR
6
−
−
−
−
ns
ns
ns
TDO valid from TCK falling t8 CC
29
29
32
32
edge (propagation delay)3)
TDO high impedance to
valid output from TCK
falling edge4)3)
t9 CC
TDO valid output to high
impedance from TCK
falling edge3)
t
10 CC
−
29
32
ns
ns
TDO hold after TCK falling t18 CC
5
−
−
edge3)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS
.
2) Under typical conditions, the JTAG interface can operate at transfer rates up to 10 MHz.
3) The falling edge on TCK is used to generate the TDO timing.
4) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
91
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Table 39 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Table 39
JTAG Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
1001)
16
16
−
Typ.
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
−
−
−
−
−
−
−
−
−
8
8
−
ns
ns
ns
ns
ns
ns
TCK low time
TCK clock rise time
TCK clock fall time
−
TDI/TMS setup to TCK
rising edge
6
TDI/TMS hold after TCK
rising edge
t7 SR
6
−
−
−
−
ns
ns
ns
TDO valid from TCK falling t8 CC
39
39
43
43
edge (propagation delay)2)
TDO high impedance to
valid output from TCK
falling edge3)2)
t9 CC
TDO valid output to high
impedance from TCK
falling edge2)
t
10 CC
−
39
43
ns
ns
TDO hold after TCK falling t18 CC
5
−
−
edge2)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS
.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
92
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
t1
0.9 VDDP
0.5 VDDP
0.1 VDDP
t5
t4
t2
t3
MC_JTAG_TCK
Figure 24
Test Clock Timing (TCK)
TCK
t6
t7
TMS
TDI
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 25
JTAG Timing
Data Sheet
93
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Debug via SPD
The SPD interface will work with standard SPD tools having a sample/output clock
frequency deviation of +/- 5% or less.
Note: For further details please refer to application note AP24004 in section SPD Timing
Requirements.
Note: Operating Conditions apply.
Data Sheet
94
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Electrical Parameters
Data Sheet
95
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Package and Reliability
5
Package and Reliability
The XE166 Family devices use the package type:
PG-VQFN (Plastic Green - Very Thin Profile Quad Flat Non-Leaded Package)
•
The following specifications must be regarded to ensure proper integration of the
XE161FU in its target environment.
5.1
Packaging
These parameters specify the packaging rather than the silicon.
Table 40
Package Parameters (PG-VQFN-48-54)
Parameter
Symbol
Limit Values
Max.
Unit Notes
Min.
Exposed Pad Dimension Ex × Ey
–
–
–
5.2 x 5.2
mm
W
–
–
Power Dissipation
PDISS
RΘJA
0.6
75
Thermal resistance
Junction-Ambient
K/W No thermal via,
2-layer1)
51
K/W No thermal via,
4-layer2)
46
36
K/W 4-layer, no pad3)
K/W 4-layer, pad4)
1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) without thermal vias; exposed pad not
soldered.
2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) without thermal vias; exposed pad not
soldered.
3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not
soldered.
4) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered
to the board.
Note: To improve the EMC behavior, it is recommended to connect the exposed pad to
the board ground, independent of the thermal requirements.
Board layout examples are given in an application note.
Package Compatibility Considerations
The XE161FU is a member of the XE166 Family of microcontrollers. It is also compatible
to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
Data Sheet
95
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Package and Reliability
particular, the size of the Exposed Pad (if present) may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
Package Outlines
0.9 MAX.
11 x 0.5 = 5.5
0.5
0.1
7
A
(0.65)
6.8
B
+0.03
48x
36
25
24
13
37
48
0.08
0.26
1
12
Index Marking
48x
0.1
0.4 x 45˚
Index Marking
0.05
0.23
0.15
M
A B C
(0.2)
0.05 MAX.
0.03
(5.2)
(6.2)
C
PG-VQFN-48-15, -19, -20, -22, -24, -48, -51, -52, -53, -55, -56-PO V12
Figure 26
PG-VQFN-48-54 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet
96
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Package and Reliability
5.2
Thermal Considerations
When operating the XE161FU in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
P
INT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
IOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
P
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
97
V1.2, 2012-07
XE161FU
XE166 Family / Compact Line
Package and Reliability
5.3
Quality Declarations
The operation lifetime of the XE161FU depends on the operating temperature. The
lifetime decreases with increasing temperature as shown in Table 42.
Table 41
Quality Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
20
Operation lifetime
ESD susceptibility
t
OP CC
−
−
−
−
a
See Table 42
VHBM
2000
V
EIA/JESD22-
A114-B
according to Human Body SR
Model (HBM)
Moisture sensitivity level
MSL CC −
−
3
−
JEDEC
J-STD-020C
Table 42
Operating Time
20 a
Lifetime Dependency on Temperature
Operating Temperature
TJ ≤ 110°C
95 500 h
68 500 h
49 500 h
26 400 h
14 500 h
TJ = 120°C
TJ = 125°C
TJ = 130°C
TJ = 140°C
TJ = 150°C
Data Sheet
98
V1.2, 2012-07
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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