XMC1301-T038X0064 AB [INFINEON]
32 位微控制器，带 ARM® Cortex®-M0，重点用于低成本嵌入式控制应用。对于将传统 32 位设计带入一个新的水平，涵盖从典型 32 位应用到数字功率换算，甚至是磁场定向电动机控制的广泛应用领域，当首选 XMC1000。XMC1300 系列可集成无传感器现场定向控制（FOC）电机、无刷（BLDC）电机、有刷直流电机以及永磁同步电机所需的所有控制和模拟接口功能。;
| 型号： | XMC1301-T038X0064 AB |
| 厂家： | 
Infineon |
| 描述： | 32 位微控制器，带 ARM® Cortex®-M0，重点用于低成本嵌入式控制应用。对于将传统 32 位设计带入一个新的水平，涵盖从典型 32 位应用到数字功率换算，甚至是磁场定向电动机控制的广泛应用领域，当首选 XMC1000。XMC1300 系列可集成无传感器现场定向控制（FOC）电机、无刷（BLDC）电机、有刷直流电机以及永磁同步电机所需的所有控制和模拟接口功能。 电动机控制 电机 控制器 微控制器 传感器 |
| 文件： | 总11页 (文件大小：955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XMC1100 / XMC1200 /
XMC1300
Fixed Flash Wait States
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet Addendum
V1.0 2016-02
Microcontrollers
Edition 2016-02
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
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question, please contact the nearest Infineon Technologies Office.
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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
XMC1100 / XMC1200 /
XMC1300
Fixed Flash Wait States
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet Addendum
V1.0 2016-02
Microcontrollers
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
XMC1100 / XMC1200 / XMC1300 Data Sheet Addendum
Revision History: V1.0 2016-02
Previous Version: none
Page
Subjects
Initial version.
Trademarks
C166™, TriCore™ , XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
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Data Sheet Addendum
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Table of Contents
Table of Contents
1
Fixed Flash Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash read access with fixed wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
NVM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
1.2
1.3
1.3.1
Data Sheet Addendum
5
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
1
Fixed Flash Wait States
The parameter limits defined in this addendum extend the electrical parameters defined
in the XMC1100 / XMC1200 / XMC1300 Data Sheet stated below.
•
•
Data Sheet AA-Step, V1.4, 2014-05
Data Sheet AB-Step, V1.6, 2015-04
1.1
Flash read access with fixed wait states
Per default the XMC1100 / XMC1200 / XMC1300 devices use a configuration with
adaptive wait states for read accesses to the flash memory, dynamically adapting to the
system frequency and flash access timing without user software interaction.
Alternatively, it is possible to configure the XMC1100 / XMC1200 / XMC1300 devices to
apply fixed wait states to each flash read access, improving determinism of program
execution from flash. The required number of wait states depends on the system
frequency fMCLK, as defined in the parameter NFWSFLASH. The number of wait states can
be configured with the bit NVM_NVMCONF.WS, the selection of adaptive or fixed wait
states is done with the bit NVM_CONFIG1.WS.
Attention: Any write operation to the register NVM_CONFIG1 to switch between
adaptive and fixed wait states configuration must only modify the bit
NVM_CONFIG1.FIXWS. Changing other bits in NVM_CONFIG1 can lead
to unpredictable results.
Attention: Before and after the fixed wait states configuration or the system
frequency fMCLK is changed, the number of selected wait states must
always comply to the parameter NFWSFLASH
.
Below is a code snippet defining the register addresses, configuring one wait state and
then switching to operation with fixed wait states.
Example
// Headers and variables to fix number of wait states to "1"
#define ADDR1 0x40050008
uint32_t * NVM_NVMCONF = (uint32_t *) ADDR1;
#define ADDR2 0x40050048 //Address of NVM_CONFIG1
//Address of NVM_NVMCONF
uint32_t * NVM_CONFIG1 = (uint32_t *) ADDR2;
// init sequence to fix number of wait states to "1"
*NVM_NVMCONF = *NVM_NVMCONF | 0x1000; //Set .WS bit => 1WS
*NVM_CONFIG1 = *NVM_CONFIG1 | 0x0800; //Set .FIXWS bit => fixed
WS scheme
Data Sheet Addendum
6
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
1.2
NVM Registers
NVM Configuration Register
The definition of bit NVMCONF.12 changes to NVMCONF.WS.
NVM_NVMCONF
NVM Configuration Register
(4005 0008H)
Reset Value: 9000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVM INT_
_ON ON
0
WS
SECPROT
0
HRLEV
0
rw
rw
rw
rw
rw
r
rw
rw
Field
Bits Type Description
NVM_ON
15
rw
NVM On
When cleared, no software code can be executed anymore
from the NVM, until it is set again. I.e., already the software
code that initiates the change in NVM_ON itself may not
reside in the NVM, otherwise the software is stalled forever.
0B
1B
SLEEP, NVM is switched to or stays in sleep mode.
NORM, NVM is switched to or stays in normal mode.
INT_ON
14
rw
Interrupt On
When enabled the completion of a sequence started by
setting NVMPROG.ACTION (write or erase sequence) will
be indicated by NVM interrupt. The same is true for the
wake-up sequence.
0B
1B
INTOFF, No NVM ready interrupts are generated.
INTON, NVM ready interrupts are generated.
0
13
12
rw
rw
Reserved for Future Use
Must be written with 0 to allow correct operation.
WS
Number of fixed Wait States
Defines the number of fixed wait states when
NVM_CONFIG1.FIXWS = 1B.
0B
1B
0 fixed wait states.
1 fixed wait state.
SECPROT 11:4 rw
Sector Protection1)
This field defines the number of write, erase, verify
protected sectors, starting with physical sector 0.
Data Sheet Addendum
7
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Field
0
Bits Type Description
3
r
Reserved
Read as 0; should be written with 0.
HRLEV
2:1
rw
Hardread Level2)
Defines single hardread level for verification with
NVMPROG.ACTION.VERIFY = 11B:
00B NR, Normal read
01B HRW, Hardread written
10B HRE, Hardread erased
11B RFU, Reserved for Future Use
0
0
rw
Reserved for Future Use
Must be written with 0 to allow correct operation.
1) For SECPROT > 0, SECPROT defines the number of protected sectors. The sectors 0 to SECPROT-1 cannot
be written, erased, or verified. All writes that target the protected sectors are accepted, but are internally
ignored.
2) HRLEV defines the hardread level for
a
stand-alone verification sequence started with
NVMPROG.ACTION.VERIFY = 11B. This hardread level is used until the end of the verification sequence.
HRLEV may not be changed in between.
Configuration 1 Register
The bit NVM_CONFIG1.FIXWS allows to switch between adaptive and fixed wait state
configuration.
Attention: Any write operation to the register NVM_CONFIG1 to switch between
adaptive and fixed wait states configuration must only modify the bit
NVM_CONFIG1.FIXWS. Changing other bits in NVM_CONFIG1 can lead
to unpredictable results.
NVM_CONFIG1
Configuration 1 Register
(4005 0048H)
Reset Value: XXXXH
15
14
RES
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIX
WS
RES
rw
rw
Field
RES
Bits Type Description
15:12 rw Reserved
Must not be changed when programming the
NVM_CONFIG1 register.
Data Sheet Addendum
8
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Field
Bits Type Description
11 rw Wait States Scheme
FIXWS
Defines the scheme by which flash wait states are
generated. Withfixed wait states NVM_NVMCONF.WS
defines the number of wait states.
0B
1B
adaptive wait states.
fixed wait states.
RES
10:0 rw
Reserved
Must not be changed when programming the
NVM_CONFIG1 register.
Data Sheet Addendum
9
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
1.3
Electrical Parameters
1.3.1
Flash Memory Parameters
This definition expands the flash wait states definition by parameters for the
configuration with fixed wait states.
Table 1
Flash Memory Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min. Typ. Max.
Fixed Flash Wait States
configured in bit
NFWSFLASH
SR
0
0
1
NVM_CONFIG1.
FIXWS = 1B,
NVM_NVMCONF.WS
fMCLK ≤ 16 MHz
1
1
1
NVM_CONFIG1.
FIXWS = 1B,
16 MHz < fMCLK
≤
32 MHz
Data Sheet Addendum
10
V1.0, 2016-02
Subject to Agreement on the Use of Product Information
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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