XMC1302-T028X0128 AB

XMC1300 AB-Step

Microcontroller Series

for Industrial Applications

XMC1000 Family

ARM^®Cortex^®-M0

32-bit processor core

Data Sheet

V2.0 2017-10

Microcontrollers

Edition 2017-10

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

XMC1300 AB-Step

Microcontroller Series

for Industrial Applications

XMC1000 Family

ARM^®Cortex^®-M0

32-bit processor core

Data Sheet

V2.0 2017-10

Microcontrollers

XMC1300 AB-Step

XMC1000 Family

XMC1300 Data Sheet

Revision History: V2.0 2017-10

Previous Version: V1.9 2017-03

Page

Subjects

Page 10, Add marking option for XMC1302-T28X0032, XMC1302-T28X0064,

Page 13

XMC1302-T28X0128, XMC1302-T28X0200.

Trademarks

C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.

ARM^®, ARM Powered^®and AMBA^®are registered trademarks of ARM, Limited.

Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace

Buffer™ are trademarks of ARM, Limited.

We Listen to Your Comments

Is there any information in this document that you feel is wrong, unclear or missing?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Data Sheet

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Table of Contents

1

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1

1.2

1.3

1.4

2

2.1

2.2

2.2.1

2.2.2

2.2.3

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 27

3

3.1

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . 46

Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . . 57

On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . 61

SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 63

Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 68

3.1.1

3.1.2

3.1.3

3.1.4

3.2

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.2.7

3.3

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.3.6.1

3.3.6.2

3.3.6.3

4

Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.1

4.1.1

4.2

Data Sheet

5

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Table of Contents

5

Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Sheet

6

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

About this Document

This Data Sheet is addressed to embedded hardware and software developers. It

provides the reader with detailed descriptions about the ordering designations, available

features, electrical and physical characteristics of the XMC1300 series devices.

The document describes the characteristics of a superset of the XMC1300 series

devices. For simplicity, the various device types are referred to by the collective term

XMC1300 throughout this document.

XMC1000 Family User Documentation

The set of user documentation includes:

•

Reference Manual

– decribes the functionality of the superset of devices.

Data Sheets

•

– list the complete ordering designations, available features and electrical

characteristics of derivative devices.

•

Errata Sheets

– list deviations from the specifications given in the related Reference Manual or

Data Sheets. Errata Sheets are provided for the superset of devices.

Attention: Please consult all parts of the documentation set to attain consolidated

knowledge about your device.

Application related guidance is provided by Users Guides and Application Notes.

Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions

of those documents.

Data Sheet

7

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

1

Summary of Features

The XMC1300 devices are members of the XMC1000 Family of microcontrollers based

on the ARM Cortex-M0 processor core. The XMC1300 series addresses the real-time

control needs of motor control, digital power conversion. It also features peripherals for

LED Lighting applications.

SWD

Cortex-M0

Analog system

Debug

system

CPU

SPD

EVR

2 x DCO

NVIC

Temperature sensor

ANACTRL SFRs

PRNG

AHB to APB

Bridge

PAU

AHB-Lite Bus

Flash SFRs

200k + 0.5k¹⁾

Flash

ACMP &

ORC

MATH

CCU40

16k

SRAM

USIC0

VADC

ERU0

PORTS

WDT

BCCU0

CCU80

POSIF0

8k ROM

Memories

SCU

RTC

1) 0.5kbytes of sector 0 (readable only).

Figure 1

System Block Diagram

CPU Subsystem

CPU Core

– High-performance 32-bit ARM Cortex-M0 CPU

•

– Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set

– Single cycle 32-bit hardware multiplier

– System timer (SysTick) for Operating System support

Data Sheet

8

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

– Ultra low power consumption

•

Nested Vectored Interrupt Controller (NVIC)

Event Request Unit (ERU) for processing of external and internal service requests

MATH Co-processor (MATH)

– CORDIC unit for trigonometric calculation

– division unit

On-Chip Memories

•

8 kbytes on-chip ROM

16 kbytes on-chip high-speed SRAM

up to 200 kbytes on-chip Flash program and data memory

Communication Peripherals

•

Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,

quad-SPI, IIC, IIS and LIN interfaces

Analog Frontend Peripherals

•

A/D Converters

– up to 12 analog input pins

– 2 sample and hold stages with 8 analog input channels each

– fast 12-bit analog to digital converter with adjustable gain

Up to 8 channels of out of range comparators (ORC)

Up to 3 fast analog comparators (ACMP)

Temperature Sensor (TSE)

•

Industrial Control Peripherals

•

Capture/Compare Units 4 (CCU4) as general purpose timers

Capture/Compare Units 8 (CCU8) for motor control and power conversion

Position Interfaces (POSIF) for hall and quadrature encoders and motor positioning

Brightness and Colour Control Unit (BCCU), for LED color and dimming application

System Control

•

Window Watchdog Timer (WDT) for safety sensitive applications

Real Time Clock module with alarm support (RTC)

System Control Unit (SCU) for system configuration and control

Pseudo random number generator (PRNG) for fast random data generation

Input/Output Lines

•

Tri-stated in input mode

Push/pull or open drain output mode

Data Sheet

9

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

•

Configurable pad hysteresis

On-Chip Debug Support

•

Support for debug features: 4 breakpoints, 2 watchpoints

Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD)

1.1

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a

specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:

•

<DDD> the derivatives function set

<Z> the package variant

– T: TSSOP

– Q: VQFN

•

<PPP> package pin count

<T> the temperature range:

– F: -40°C to 85°C

– X: -40°C to 105°C

•

<FFFF> the Flash memory size.

For ordering codes for the XMC1300 please contact your sales representative or local

distributor.

This document describes several derivatives of the XMC1300 series, some descriptions

may not apply to a specific product. Please see Table 1.

For simplicity the term XMC1300 is used for all derivatives throughout this document.

1.2

Device Types

These device types are available and can be ordered through Infineon’s direct and/or

distribution channels.

Table 1

Synopsis of XMC1300 Device Types

Package

Derivative

Flash

SRAM

Kbytes

XMC1301-T016F0008

XMC1301-T016F0016

XMC1301-T016F0032

XMC1301-T016X0008

XMC1301-T016X0016

XMC1302-T016X0008

PG-TSSOP-16-8

8

16

32

8

16

8

Data Sheet

10

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

Table 1

Synopsis of XMC1300 Device Types (cont’d)

Derivative

Package

Flash

Kbytes

SRAM

Kbytes

16

XMC1302-T016X0016

XMC1302-T016X0032

XMC1302-T028X0016

XMC1302-T028X0032

XMC1302-T028X0064

XMC1302-T028X0128

XMC1302-T028X0200

XMC1301-T038F0008

XMC1301-T038F0016

XMC1301-T038F0032

XMC1301-T038X0032

XMC1301-T038F0064

XMC1302-T038X0016

XMC1302-T038X0032

XMC1302-T038X0064

XMC1302-T038X0128

XMC1302-T038X0200

XMC1301-Q024F0008

XMC1301-Q024F0016

XMC1302-Q024F0016

XMC1302-Q024F0032

XMC1302-Q024F0064

XMC1302-Q024X0016

XMC1302-Q024X0032

XMC1302-Q024X0064

XMC1301-Q040F0008

XMC1301-Q040F0016

XMC1301-Q040F0032

XMC1302-Q040X0016

XMC1302-Q040X0032

PG-TSSOP-16-8

PG-TSSOP-28-8

PG-TSSOP-38-9

PG-VQFN-24-19

PG-VQFN-40-13

16

32

16

32

64

128

200

8

16

32

64

16

32

64

128

200

8

16

32

64

16

32

64

8

16

32

16

32

Data Sheet

11

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

Table 1

Synopsis of XMC1300 Device Types (cont’d)

Derivative

Package

Flash

Kbytes

SRAM

Kbytes

16

XMC1302-Q040X0064

XMC1302-Q040X0128

XMC1302-Q040X0200

PG-VQFN-40-13

64

128

200

16

1.3

Device Type Features

The following table lists the available features per device type.

Table 2

Features of XMC1300 Device Types¹⁾

Derivative

ADC channel

ACMP

BCCU

MATH

XMC1301-T016

XMC1302-T016

XMC1302-T028

XMC1301-T038

XMC1302-T038

XMC1301-Q024

XMC1302-Q024

XMC1301-Q040

XMC1302-Q040

11

14

16

13

16

2

3

-

1

-

1

-

1

-

1

-

1

-

1

-

1

1) Features that are not included in this table are available in all the derivatives

Table 3

ADC Channels ¹⁾

VADC0 G0

Package

VADC0 G1

PG-TSSOP-16

PG-TSSOP-28

PG-TSSOP-38

PG-VQFN-24

PG-VQFN-40

CH0..CH5

CH0..CH7

CH0..CH4

CH0 .. CH4, CH7

CH0..CH7

CH0..CH4

CH0..CH7

1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port

I/O Function table.

Data Sheet

12

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

1.4

Chip Identification Number

The Chip Identification Number allows software to identify the marking. It is a 8 words

value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at

address location : 1000 0F00_H(MSB) - 1000 0F1B_H(LSB). The least significant word and

most significant word of the Chip Identification Number are the value of registers

DBGROMID and IDCHIP, respectively.

Table 4

XMC1300 Chip Identification Number

Value

Derivative

Marking

XMC1301-T016F0008

XMC1301-T016F0016

XMC1301-T016F0032

XMC1301-T016X0008

XMC1301-T016X0016

XMC1302-T016X0008

XMC1302-T016X0016

XMC1302-T016X0032

XMC1302-T028X0016

XMC1302-T028X0032

XMC1302-T028X0064

XMC1302-T028X0128

XMC1302-T028X0200

XMC1301-T038F0008

00013032 01CF00FF 00001FF7 0000100F

00000C00 00001000 00003000 201ED083_H

AB

00013032 01CF00FF 00001FF7 0000100F

00000C00 00001000 00005000 201ED083_H

AB

00013032 01CF00FF 00001FF7 0000100F

00000C00 00001000 00009000 201ED083_H

00013033 01CF00FF 00001FF7 0000100F

00000C00 00001000 00003000 201ED083_H

00013033 01CF00FF 00001FF7 0000100F

00000C00 00001000 00005000 201ED083_H

00013033 01FF00FF 00001FF7 0000900F

00000C00 00001000 00003000 201ED083_H

00013033 01FF00FF 00001FF7 0000900F

00000C00 00001000 00005000 201ED083_H

00013033 01FF00FF 00001FF7 0000900F

00000C00 00001000 00009000 201ED083_H

00013023 01FF00FF 00001FF7 0000900F

00000C00 00001000 00005000 201ED083_H

00013023 01FF00FF 00001FF7 0000900F

00000C00 00001000 00009000 201ED083_H

00013023 01FF00FF 00001FF7 0000900F

00000C00 00001000 00011000 201ED083_H

00013023 01FF00FF 00001FF7 0000900F

00000C00 00001000 00021000 201ED083_H

00013023 01FF00FF 00001FF7 0000900F

00000C00 00001000 00033000 201ED083_H

00013012 01CF00FF 00001FF7 0000100F

00000C00 00001000 00003000 201ED083_H

Data Sheet

13

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

Table 4

XMC1300 Chip Identification Number (cont’d)

Derivative

Value

Marking

XMC1301-T038F0016

XMC1301-T038F0032

XMC1301-T038X0032

XMC1301-T038F0064

XMC1302-T038X0016

XMC1302-T038X0032

XMC1302-T038X0064

XMC1302-T038X0128

XMC1302-T038X0200

XMC1301-Q024F0008

XMC1301-Q024F0016

XMC1302-Q024F0016

XMC1302-Q024F0032

XMC1302-Q024F0064

XMC1302-Q024X0016

XMC1302-Q024X0032

XMC1302-Q024X0064

00013012 01CF00FF 00001FF7 0000100F

00000C00 00001000 00005000 201ED083_H

AB

00013012 01CF00FF 00001FF7 0000100F

00000C00 00001000 00009000 201ED083_H

00013013 01CF00FF 00001FF7 0000100F

00000C00 00001000 00009000 201ED083_H

00013012 01CF00FF 00001FF7 0000100F

00000C00 00001000 00011000 201ED083_H

00013013 01FF00FF 00001FF7 0000900F

00000C00 00001000 00005000 201ED083_H

00013013 01FF00FF 00001FF7 0000900F

00000C00 00001000 00009000 201ED083_H

00013013 01FF00FF 00001FF7 0000900F

00000C00 00001000 00011000 201ED083_H

00013013 01FF00FF 00001FF7 0000900F

00000C00 00001000 00021000 201ED083_H

00013013 01FF00FF 00001FF7 0000900F

00000C00 00001000 00033000 201ED083_H

00013062 01CF00FF 00001FF7 0000100F

00000C00 00001000 00003000 201ED083_H

00013062 01CF00FF 00001FF7 0000100F

00000C00 00001000 00005000 201ED083_H

00013062 01FF00FF 00001FF7 0000900F

00000C00 00001000 00005000 201ED083_H

00013062 01FF00FF 00001FF7 0000900F

00000C00 00001000 00009000 201ED083_H

00013062 01FF00FF 00001FF7 0000900F

00000C00 00001000 00011000 201ED083_H

00013063 01FF00FF 00001FF7 0000900F

00000C00 00001000 00005000 201ED083_H

00013063 01FF00FF 00001FF7 0000900F

00000C00 00001000 00009000 201ED083_H

00013063 01FF00FF 00001FF7 0000900F

00000C00 00001000 00011000 201ED083_H

Data Sheet

14

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Summary of Features

Table 4

XMC1300 Chip Identification Number (cont’d)

Derivative

Value

Marking

XMC1301-Q040F0008

XMC1301-Q040F0016

XMC1301-Q040F0032

XMC1302-Q040X0016

XMC1302-Q040X0032

XMC1302-Q040X0064

XMC1302-Q040X0128

XMC1302-Q040X0200

00013042 01CF00FF 00001FF7 0000100F

00000C00 00001000 00003000 201ED083_H

AB

00013042 01CF00FF 00001FF7 0000100F

00000C00 00001000 00005000 201ED083_H

00013042 01CF00FF 00001FF7 0000100F

00000C00 00001000 00009000 201ED083_H

00013043 01FF00FF 00001FF7 0000900F

00000C00 00001000 00005000 201ED083_H

00013043 01FF00FF 00001FF7 0000900F

00000C00 00001000 00009000 201ED083_H

00013043 01FF00FF 00001FF7 0000900F

00000C00 00001000 00011000 201ED083_H

00013043 01FF00FF 00001FF7 0000900F

00000C00 00001000 00021000 201ED083_H

00013043 01FF00FF 00001FF7 0000900F

00000C00 00001000 00033000 201ED083_H

Data Sheet

15

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

2

General Device Information

This section summarizes the logic symbols and package pin configurations with a

detailed list of the functional I/O mapping.

2.1

Logic Symbols

V_DDP

V_SSP

(2)

V_DDP

(1)

V_SSP

(1)

(2)

Port 0

16 bit

Port 0

12 bit

Port 1

6 bit

Port 1

4 bit

XMC13XX

TSSOP-38

XMC13XX

TSSOP-28

Port 2

4 bit

Port 2

4 bit

Port 2

8 bit

Port 2

6 bit

V_DDP

V_SSP

(1)

Port 0

8 bit

XMC13XX

TSSOP-16

Port 2

3 bit

Port 2

3 bit

Figure 2

XMC1300 Logic Symbol for TSSOP-38, TSSOP-28 and TSSOP-16

Data Sheet

16

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

V_DDP

V_SSP

(1)

V_DDV_SSV_DDPV_SSP

(1) (1) (2) (1)

(1)

Port 0

10 bit

Port 0

16 bit

Port 1

4 bit

Port 1

7 bit

XMC1300

VQFN-24

XMC1300

VQFN-40

Port 2

4 bit

Port 2

4 bit

Port 2

4 bit

Port 2

8 bit

Figure 3

XMC1300 Logic Symbol for VQFN-24 and VQFN-40

Data Sheet

17

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

2.2

Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the different

packages.

P2.4

P2.5

1

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

P2.3

Top View

2

P2.2

P2.6

3

P2.1

P2.7

4

P2.0

P2.8

5

P0.15

P0.14

P0.13

P2.9

6

P2.10

P2.11

_SSP/V_SS

7

8

P0.12

P0.11

P0.10

V

9

V_DDP/V_DD

10

11

12

13

14

15

16

17

18

19

P1.5

P1.4

P1.3

P0.9

P0.8

V_DDP

P1.2

P1.1

P1.0

V_SSP

P0.7

P0.6

P0.5

P0.4

P0.3

P0.0

P0.1

P0.2

Figure 4

XMC1300 PG-TSSOP-38 Pin Configuration (top view)

Data Sheet

18

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

P2.6

P2.7

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

P2.5

Top View

2

P2.2

P2.8

3

P2.1

P2.9

4

P2.0

P2.10

P2.11

_SSP/V_SS

5

P0.15

P0.14

P0.13

6

V

7

V_DDP/V_DD

P1.3

8

P0.12

P0.10

9

P1.2

10

11

12

13

14

P0.9

P1.1

P0.8

P0.7

P1.0

P0.0

P0.6

P0.5

P0.4

Figure 5

XMC1300 PG-TSSOP-28 Pin Configuration (top view)

P2.7/P2.8

P2.9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P2.6

P2.0

P0.15

P0.14

P0.9

P0.8

P0.7

P0.6

Top View

P2.10

P2.11

V

_SSP/V_SS

V_DDP/V_DD

P0.0

P0.5

Figure 6

XMC1300 PG-TSSOP-16 Pin Configuration (top view)

Data Sheet

19

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

18 17 16 15 14 13

P0.8

P0.9

12

P1.2

P1.3

19

20

11

10

9

21

22

V

P0.12

P0.13

P0.14

P0.15

_DDP/V _DD

_SSP/V _SS

V

8

23

24

P2.11

P2.10

7

1

2

3

4

5

6

Figure 7

XMC1300 PG-VQFN-24 Pin Configuration (top view)

Data Sheet

20

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

30 29 28 27 26 25 24 23 22 21

V_SSP

V_DDP

P1.2

P1.3

P1.4

P1.5

31

32

33

20

19

18

17

16

15

14

P0.8

P0.9

34

35

36

P1.6

V_DDP

P0.10

P0.11

P0.12

P0.13

P0.14

P0.15

37

38

39

40

V_DD

V_SS

13

12

11

P2.11

P2.10

1

2

3

4

5

6

7

8

9

10

Figure 8

XMC1300 PG-VQFN-40 Pin Configuration (top view)

Data Sheet

21

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

2.2.1

Package Pin Summary

The following general building block is used to describe each pin:

Table 5

Function

Px.y

Package Pin Mapping Description

Package A

Package B

...

Pad Type

N

Pad Class

The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),

followed by the supply pins.

The following columns, titled with the supported package variants, lists the package pin

number to which the respective function is mapped in that package.

The “Pad Type” indicates the employed pad type:

•

STD_INOUT(standard bi-directional pads)

STD_INOUT/AN (standard bi-directional pads with analog input)

High Current (high current bi-directional pads)

STD_IN/AN (standard input pads with analog input)

Power (power supply)

Details about the pad properties are defined in the Electrical Parameters.

Table 6

Package Pin Mapping

Function VQFN TSSOP TSSOP VQFN TSSOP Pad

Notes

40

38

28

24

16

Type

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

23

17

13

15

7

STD_IN

OUT

24

25

26

27

28

29

18

19

20

21

22

23

-

STD_IN

OUT

-

STD_IN

OUT

-

STD_IN

OUT

14

15

16

-

STD_IN

OUT

16

17

8

9

STD_IN

OUT

STD_IN

OUT

Data Sheet

22

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

Table 6

Package Pin Mapping (cont’d)

Function VQFN TSSOP TSSOP VQFN TSSOP Pad

Notes

40

38

28

24

16

Type

P0.7

P0.8

P0.9

P0.10

P0.11

P0.12

P0.13

P0.14

P0.15

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P2.0

30

24

17

18

10

STD_IN

OUT

33

34

35

36

37

38

39

40

22

21

20

19

18

17

16

1

27

28

29

30

31

32

33

34

16

15

14

13

12

11

-

18

19

20

-

19

20

-

11

12

-

STD_IN

OUT

STD_IN

OUT

STD_IN

OUT

-

STD_IN

OUT

21

22

23

24

12

11

10

9

21

22

23

24

14

13

12

11

-

STD_IN

OUT

-

STD_IN

OUT

13

14

-

STD_IN

OUT

STD_IN

OUT

High

Current

-

High

Current

-

High

Current

-

High

Current

-

High

Current

-

High

Current

-

STD_IN

OUT

35

25

1

15

STD_IN

OUT/AN

Data Sheet

23

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

Table 6

Package Pin Mapping (cont’d)

Function VQFN TSSOP TSSOP VQFN TSSOP Pad

Notes

40

38

28

24

16

Type

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

P2.9

P2.10

P2.11

VSS

2

36

26

2

-

STD_IN

OUT/AN

3

37

38

1

27

-

3

-

STD_IN/

AN

4

-

STD_IN/

AN

5

-

STD_IN/

AN

6

2

28

1

-

STD_IN/

AN

7

3

4

5

6

7

8

9

16

1

2

3

4

5

STD_IN/

AN

8

4

2

STD_IN/

AN

9

5

3

STD_IN/

AN

10

11

12

13

6

4

STD_IN/

AN

7

5

STD_IN

OUT/AN

8

6

STD_IN

OUT/AN

9

7

Power

Supply GND,

ADC reference

GND

VDD

14

15

10

8

10

6

Power

Supply VDD,

ADC reference

voltage/ ORC

reference voltage

VDDP

Power

When VDD is

supplied, VDDP

has to be

supplied with the

same voltage.

Data Sheet

24

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

Table 6

Package Pin Mapping (cont’d)

Function VQFN TSSOP TSSOP VQFN TSSOP Pad

Notes

40

31

32

38

25

26

-

28

-

24

-

16

-

Type

VSSP

VDDP

VSSP

Power

I/O port ground

I/O port supply

-

Exp.

Pad

-

Exp.

Pad

-

Exposed Die

Pad

The exposed die

pad is connected

internally to

VSSP. For proper

operation, it is

mandatory to

connect the

exposed pad to

the board ground.

For thermal

aspects, please

refer to the

Package and

Reliability

chapter.

2.2.2

Port I/O Function Description

The following general building block is used to describe the I/O functions of each PORT

pin:

Table 7

Port I/O Function Description

Outputs

Function

Inputs

ALT1

ALTn

Input

P0.0

Pn.y

MODA.OUT

MODC.INA

MODA.INA

MODA.OUT

MODC.INB

Data Sheet

25

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

Pn.y

XMC1000

Control Logic

PAD

V_DDP

Input 0

...

MODA.INA

Input n

HWI0

MODA

MODB

Pn.y

HWI1

SW

ALT1

MODB.OUT

...

ALTn

HWO0

HWO1

GND

Figure 9

Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it.

As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT

defines the output value.

Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port

pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective

module, with the pin characteristics controlled by the port registers (within the limits of

the connected pad).

The port pin input can be connected to multiple peripherals. Most peripherals have an

input multiplexer to select between different possible input sources.

The input path is also active while the pin is configured as output. This allows to feedback

an output to on-chip resources without wasting an additional external pin.

Please refer to the Port I/O Functions table for the complete Port I/O function mapping.

Data Sheet

26

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

General Device Information

2.2.3

Hardware Controlled I/O Function Description

The following general building block is used to describe the hardware I/O and pull control

functions of each PORT pin:

Table 8

Hardware Controlled I/O Function Description

Function

Outputs

HWO0

Inputs

Pull Control

HW0_PD

HWI0

HW0_PU

P0.0

Pn.y

MODB.OUT

MODB.INA

MODC.OUT

By Pn_HWSEL, it is possible to select between different hardware “masters”

(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).

Hardware control overrules settings in the respective port pin registers. Additional

hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the

peripherals can be used to control the pull devices of the pin.

Please refer to the Hardware Controlled I/O Functions table for the complete hardware

I/O and pull control function mapping.

Data Sheet

27

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Data Sheet

Ports, V2.3

2-28

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Data Sheet

Ports, V2.3

2-29

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Data Sheet

Ports, V2.3

2-30

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Data Sheet

Ports, V3.1

2-31

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Data Sheet

Ports, V3.1

2-32

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3

Electrical Parameters

This section provides the electrical parameters which are implementation-specific for the

XMC1300.

3.1

General Parameters

3.1.1

Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the XMC1300

and partly its requirements on the system. To aid interpreting the parameters easily

when evaluating them for a design, they are indicated by the abbreviations in the

“Symbol” column:

•

CC

Such parameters indicate Controller Characteristics, which are distinctive feature of

the XMC1300 and must be regarded for a system design.

SR

•

Such parameters indicate System Requirements, which must be provided by the

application system in which the XMC1300 is designed in.

Data Sheet

33

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.1.2

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 9

Absolute Maximum Rating Parameters

Symbol Values

Parameter

Unit Note /

Test Cond

Min Typ. Max.

.

ition

Junction temperature

Storage temperature

T_J

SR -40

–

115

125

6

°C

V

–

T_ST

Voltage on power supply pin V_DDPSR -0.3

with respect to V_SSP

Voltage on digital pins with

respect to V_SSP

V_IN

SR -0.5

–

V

_DDP+ 0.5

V

whichever

is lower

1)

or max. 6

Voltage on P2 pins with

V_INP2SR -0.3

V_DDP+ 0.3

V

–

2)

respect to V_SSP

Voltage on analog input pins V_AIN

with respect to V_SSP

-0.5

V_DDP+ 0.5

V

whichever

is lower

V_AREFSR

or max. 6

10

Input current on any pin

during overload condition

I_IN

SR -10

mA

–

Absolute maximum sum of all ΣI_INSR -50

inputcurrentsduringoverload

condition

+50

–

1) Excluding port pins P2.[1,2,6,7,8,9,11].

2) Applicable to port pins P2.[1,2,6,7,8,9,11].

Data Sheet

34

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.1.3

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience

overload currents and voltages that go beyond their own IO power supplies specification.

Table 10 defines overload conditions that will not cause any negative reliability impact if

all the following conditions are met:

•

full operation life-time is not exceeded

Operating Conditions are met for

– pad supply levels (V_DDP

)

– temperature

If a pin current is outside of the Operating Conditions but within the overload

conditions, then the parameters of this pin as stated in the Operating Conditions can no

longer be guaranteed. Operation is still possible in most cases but with relaxed

parameters.

Note: An overload condition on one or more pins does not require a reset.

Note: A series resistor at the pin to limit the current to the maximum permitted overload

current is sufficient to handle failure situations like short to battery.

Table 10

Overload Parameters

Symbol

Parameter

Values

Unit Note /

Test Condition

Min. Typ. Max.

Input current on any port pin I_OVSR -5

during overload condition

–

5

mA

Absolute sum of all input

circuit currents during

overload condition

I_OVSSR

–

25

Figure 10 shows the path of the input currents during overload via the ESD protection

structures. The diodes against V_DDPand ground are a simplified representation of these

ESD protection structures.

Data Sheet

35

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

V_DDP

Pn.y

I_OVx

GND

ESD

GND

Pad

Figure 10

Input Overload Current via ESD structures

Table 11 and Table 12 list input voltages that can be reached under overload conditions.

Note that the absolute maximum input voltages as defined in the Absolute Maximum

Ratings must not be exceeded during overload.

Table 11

PN-Junction Characterisitics for positive Overload

_OV= 5 mA

Pad Type

I

Standard, High-current,

AN/DIG_IN

V

_IN= V_DDP+ 0.5 V

_AIN= V_DDP+ 0.5 V

_AREF= V_DDP+ 0.5 V

P2.[1,2,6:9,11]

V

_INP2= V_DDP+ 0.3 V

Table 12

PN-Junction Characterisitics for negative Overload

_OV= 5 mA

Pad Type

I

Standard, High-current,

AN/DIG_IN

V

_IN= V_SS- 0.5 V

_AIN= V_SS- 0.5 V

_AREF= V_SS- 0.5 V

P2.[1,2,6:9,11]

V

_INP2= V_SS- 0.3 V

Data Sheet

36

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.1.4

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation and reliability of the XMC1300. All parameters specified in the following tables

refer to these operating conditions, unless noted otherwise.

Table 13

Operating Conditions Parameters

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

SR -40

-40

Digital supply voltage¹⁾V_DDPSR 1.8

Typ.

Max.

85

Ambient Temperature T_A

−

°C

V

Temp. Range F

Temp. Range X

105

5.5

MCLK Frequency

PCLK Frequency

f_MCLKCC

f_PCLKCC

−

33.2

66.4

MHz CPU clock

MHz Peripherals

clock

Short circuit current of I_SC

digital outputs

SR -5

−

5

mA

Absolute sum of short ΣI_{SC_D}SR

circuit currents of the

device

−

25

mA

1) See also the Supply Monitoring thresholds, Chapter 3.3.2.

Data Sheet

37

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2

DC Parameters

3.2.1

Input/Output Characteristics

Table 14 provides the characteristics of the input/output pins of the XMC1300.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Note: Unless otherwise stated, input DC and AC characteristics, including peripheral

timings, assume that the input pads operate with the standard hysteresis.

Table 14

Input/Output Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Output low voltage on

port pins

(with standard pads)

V_OLPCC

–

1.0

V

I

_OL= 11 mA (5 V)

_OL= 7 mA (3.3 V)

–

0.4

1.0

I

_OL= 5 mA (5 V)

_OL= 3.5 mA (3.3 V)

Output low voltage on

high current pads

V_OLP1CC

I

_OL= 50 mA (5 V)

_OL= 25 mA (3.3 V)

–

0.32

0.4

–

V

I

_OL= 10 mA (5 V)

_OL= 5 mA (3.3 V)

Output high voltage on V_OHPCC V_DDP

-

I

_OH= -10 mA (5 V)

_OH= -7 mA (3.3 V)

port pins

(with standard pads)

1.0

V_DDP

0.4

–

V

I

_OH= -4.5 mA (5 V)

_OH= -2.5 mA (3.3 V)

Output high voltage on V_OHP1CC V_DDP

I

_OH= -6 mA (5 V)

_OH= -8 mA (3.3 V)

_OH= -4 mA (3.3 V)

high current pads

0.32

V_DDP

1.0

V_DDP

0.4

Input low voltage on port V_ILPSSR

pins

–

0.19 × V

V_DDP

CMOS Mode

(5 V, 3.3 V & 2.2 V)

(Standard Hysteresis)

Data Sheet

38

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 14

Input/Output Characteristics (Operating Conditions apply) (cont’d)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Input high voltage on

port pins

V_IHPSSR 0.7 ×

–

V

CMOS Mode

(5 V, 3.3 V & 2.2 V)

V_DDP

(Standard Hysteresis)

Input low voltage on port V_ILPLSR

pins

–

0.08 × V

V_DDP

CMOS Mode

(5 V, 3.3 V & 2.2 V)¹⁸⁾

(Large Hysteresis)

Input high voltage on

port pins

V_IHPLSR 0.85 ×

–

V

CMOS Mode

V_DDP

(5 V, 3.3 V & 2.2 V)¹⁸⁾

(Large Hysteresis)

Rise time on High

Current Pad¹⁾

t_HCPRCC

–

9

ns

50 pF @ 5 V²⁾

50 pF @ 3.3 V³⁾

50 pF @ 1.8 V⁴⁾

12

25

Fall time on High

Current Pad¹⁾

t_HCPFCC

–

9

ns

50 pF @ 5 V²⁾

50 pF @ 3.3 V³⁾

50 pF @ 1.8 V⁴⁾

12

25

Rise time on Standard t_R

CC

–

12

15

31

ns

50 pF @ 5 V⁵⁾

50 pF @ 3.3 V⁶⁾

50 pF @ 1.8 V⁷⁾

Pad¹⁾

Fall time on Standard

Pad¹⁾

t_F

–

12

15

31

ns

50 pF @ 5 V⁵⁾

50 pF @ 3.3 V⁶⁾

50 pF @ 1.8 V⁷⁾

Data Sheet

39

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 14

Input/Output Characteristics (Operating Conditions apply) (cont’d)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Input Hysteresis⁸⁾

HYS CC 0.08 ×

–

V

CMOS Mode (5 V),

Standard Hysteresis

V_DDP

0.03 ×

V_DDP

–

CMOS Mode (3.3 V),

Standard Hysteresis

0.02 ×

V_DDP

CMOS Mode (2.2 V),

Standard Hysteresis

0.5 ×

V_DDPV_DDP

0.75 × V

CMOS Mode(5 V),

Large Hysteresis

0.4 ×

V_DDPV_DDP

CMOS Mode(3.3 V),

Large Hysteresis

0.2 ×

V_DDPV_DDP

0.65 × V

CMOS Mode(2.2 V),

Large Hysteresis

Pin capacitance (digital C_IO

inputs/outputs)

CC

–

10

50

1

pF

Pull-up resistor on port R_PUPCC 20

pins

kohm V_IN= V_SSP

kohm V_IN= V_DDP

Pull-down resistor on

port pins

Input leakage current⁹⁾I_OZP

R_PDPCC 20

CC -1

SR

SR -10

μA

V

0 < V_IN< V_DDP

T_A≤ 105 °C

,

10)

Voltage on any pin

during V_DDPpower off

V_PO

I_MP

–

0.3

11

Maximum current per

pin (excluding P1, V_DDP

and V_SS)

mA

–

Maximum current per

high currrent pins

I_MP1ASR -10

50

mA

–

18)

Maximum current into

I_MVDD1SR

–

130

V

_DDP(TSSOP16,

VQFN24)

18)

Maximum current into

I_MVDD2SR

260

mA

V

_DDP(TSSOP38,

VQFN40)

Data Sheet

40

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 14

Input/Output Characteristics (Operating Conditions apply) (cont’d)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

18)

Maximum current out of I_MVSS1SR

_SS(TSSOP16,

VQFN24)

–

130

mA

V

Maximum current out of I_MVSS2SR

–

260

V

_SS(TSSOP38,

VQFN40)

1) Rise/Fall time parameters are taken with 10% - 90% of supply.

2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage.

3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.

4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.

5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage.

6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.

7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.

8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot

be guaranteed that it suppresses switching due to external system noise.

9) An additional error current (I_INJ) will flow if an overload current flows through an adjacent pin.

10) However, for applications with strict low power-down current requirements, it is mandatory that no active

voltage source is supplied at any GPIO pin when V_DDPis powered off.

Data Sheet

41

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2.2

Analog to Digital Converters (ADC)

Table 15 shows the Analog to Digital Converter (ADC) characteristics.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 15

ADC Characteristics (Operating Conditions apply)¹⁾

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

_{DD_int}SR 2.0

Typ. Max.

Supply voltage range

(internal reference)

V

–

3.0

V

SHSCFG.AREF = 11_B

CALCTR.CALGNSTC

= 0C_H

3.0

–

5.5

V

SHSCFG.AREF = 10_B

SHSCFG.AREF = 00_B

Supply voltage range V_{DD_ext}

(external reference)

SR

Analog input voltage

range

V_AINSR

V_SSP

- 0.05

–

V_DDP

+

V

0.05

Auxiliary analog

reference ground

V_REFGND

SR

V_SSP

- 0.05

–

1.0

0.2

V

G0CH0

G1CH0

V_SSP

- 0.05

Internal reference

voltage (full scale

value)

V_REFINT

CC

5

Switched capacitance C_AINSCC

of an analog input

–

1.2

4.5

–

2

pF

GNCTRxz.GAINy=00_B

(unity gain)

2

GNCTRxz.GAINy=01_B

(gain g1)

6

GNCTRxz.GAINy=10_B

(gain g2)

6

GNCTRxz.GAINy=11_B

(gain g3)

Total capacitance of

an analog input

C_AINTCC

10

Total capacitance of

the reference input

C_AREFT

CC

–

Data Sheet

42

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 15

ADC Characteristics (Operating Conditions apply)¹⁾(cont’d)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ. Max.

Gain settings

G_INCC

1

–

GNCTRxz.GAINy=00_B

(unity gain)

3

GNCTRxz.GAINy=01_B

(gain g1)

6

GNCTRxz.GAINy=10_B

(gain g2)

12

GNCTRxz.GAINy=11_B

(gain g3)

Sample Time

t

_sampleCC 3

3

–

1 /

f_ADC

V

_DD= 5.0 V

_DD= 3.3 V

_DD= 2.0 V

1 /

f_ADC

30

20

1 /

f_ADC

Sigma delta loop hold t_{SD_hold}

time

μs

Residual charge stored

in an active sigma delta

loop remains available

2)

CC

Conversion time

in fast compare mode

t

_CFCC

9

1 /

f_ADC

2)

Conversion time

in 12-bit mode

_C12CC

20

–

1 /

f_ADC

Maximum sample rate f_C12CC

–

f_ADC/ –

1 sample

pending

in 12-bit mode ³⁾

42.5

–

f_ADC/ –

2 samples

pending

2)

62.5

Conversion time

in 10-bit mode

t

_C10CC

18

–

1 /

f_ADC

Maximum sample rate f_C10CC

–

f

_ADC/ –

40.5

_ADC/ –

58.5

1 sample

pending

in 10-bit mode ³⁾

–

f

2 samples

pending

2)

Conversion time

in 8-bit mode

t

_C8CC

16

1 /

f_ADC

Data Sheet

43

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 15

ADC Characteristics (Operating Conditions apply)¹⁾(cont’d)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ. Max.

Maximum sample rate f_C8CC

–

f

_ADC/ –

1 sample

pending

in 8-bit mode ³⁾

38.5

–

f

_ADC/ –

2 samples

pending

54.5

RMS noise ⁴⁾

EN_RMS

1.5

–

LSB DC input,

CC

12

V_DD= 5.0 V,

V_{AIN = 2.5 V}

,

25°C

DNL error

INL error

EA_DNLCC –

±2.0 –

±4.0 –

±0.5 –

±3.6 –

LSB

12

EA_INLCC

–

LSB

12

Gain error with

external reference

EA_GAIN

CC

%

SHSCFG.AREF = 00_B

(calibrated)

Gain error with internal EA_GAIN

%

SHSCFG.AREF = 1X_B

(calibrated),

-40°C - 105°C

reference ⁵⁾

CC

–

±2.0 –

±8.0 –

%

SHSCFG.AREF = 1X_B

(calibrated),

0°C - 85°C

Offset error

EA_OFFCC –

mV Calibrated,

_DD= 5.0 V

V

1) The parameters are defined for ADC clock frequency f_SH= 32MHz, SHSCFG.DIVS = 0000_B. Usage of any

other frequencies may affect the ADC performance.

2) No pending samples assumed, excluding sampling time and calibration.

3) Includes synchronization and calibration (average of gain and offset calibration).

4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(A_MAXeff/ N_RMS).

With A_MAXeff= 2^N/ 2, SNR[dB] = 20 × log ( 2048 / N_RMS) [N = 12].

N_RMS= 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.

5) Includes error from the reference voltage.

Data Sheet

44

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

CH7

V_AIN

.

SAR

Converter

:

CH0

V_REF

V_REFGND

V_REFINT

V_AREF

VSS

VDD

Internal

Reference

V_DDint

V_DDext

/

CHNR

REFSEL

AREF

MC_VADC_AREFPATHS

Figure 11

ADC Voltage Supply

Data Sheet

45

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2.3

Out of Range Comparator (ORC) Characteristics

The Out-of-Range Comparator (ORC) triggers on analog input voltages (V_AIN) above the

V_DDPon selected input pins (ORCx.AIN) and generates a service request trigger

(ORCx.OUT).

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 16

Out of Range Comparator (ORC) Characteristics (Operating

Conditions apply; V_DDP= 3.0 V - 5.5 V; C_L= 0.25 pF)

Parameter

Symbol

Values

Unit Note / Test Condition

Min. Typ. Max.

DC Switching Level V_ODCCC 54

−

183 mV VAIN ≥ V_DDP+ V_ODC

Hysteresis

V_OHYSCC 15

t_OPDDCC 103

88

54

-

mV

ns

Always detected

Overvoltage Pulse

V_AIN≥ V_DDP+ 150 mV

V_AIN≥ V_DDP+ 350 mV

V_AIN≥ V_DDP+ 150 mV

V_AIN≥ V_DDP+ 350 mV

V_AIN≥ V_DDP+ 150 mV

V_AIN≥ V_DDP+ 350 mV

-

Never detected

Overvoltage Pulse

t_OPDNCC

−

21

11

Detection Delay of a t_ODDCC 39

132 ns

121 ns

persistent

Overvoltage

31

Release Delay

t_ORDCC 44

57

−

240 ns

340 ns

300 ns

V_AIN≤ V_DDP; V_DDP= 5 V

V_AIN≤ V_DDP; V_DDP= 3.3 V

ORCCTRL.ENORCx = 1

Enable Delay

t_OEDCC −

V_DDP

ORCx.AIN

V_SS

ORCx.OUT

t_ODD

t_ORD

Figure 12

ORCx.OUT Trigger Generation

Data Sheet

46

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

V_AIN(V)

T > t_OPDD

t_OPDN< T < t_OPDD

T < t_OPDN

V_DDP+ 350 mV

V_DDP+ 150 mV

t_OPDN< T < t_OPDD

T > t_OPDD

T < t_OPDN

T > t_OPDD

V_DDP+ 60 mV

V_DDP

Never

detected

Overvoltage

Pulse

Never

detected

Overvoltage

Pulse

Overvoltage

may be

detected

Never

detected

Overvoltage

Pulse

Overvoltage

may be

detected

Always detected

Overvoltage Pulse

Always detected

Overvoltage Pulse

Overvoltage

may be

detected

(long enough,

level uncertain

(Too low)

(Too short)

)

V_SSA

Figure 13

ORC Detection Ranges

Data Sheet

47

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2.4

Analog Comparator Characteristics

Table 17 below shows the Analog Comparator characteristics.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 17

Analog Comparator Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Notes/

Test Conditions

Min. Typ. Max.

Input Voltage

Input Offset

V_CMP

SR -0.05

–

V_DDP

0.05

+

V

V_CMPOFFCC

–

+/-3

–

mV High power mode

Δ V_CMP< 200 mV

+/-20 –

mV Low power mode

Δ V_CMP< 200 mV

Propagation

Delay¹⁾

t_PDELAY

CC

25

–

ns

μA

High power mode,

Δ V_CMP= 100 mV

80

High power mode,

Δ V_CMP= 25 mV

250

700

100

Low power mode,

Δ V_CMP= 100 mV

Low power mode,

Δ V_CMP= 25 mV

Current

Consumption

I_ACMP

CC

First active ACMP in

high power mode,

ΔV_CMP> 30 mV

–

66

–

μA

Each additional

ACMP in high power

mode, ΔV_CMP> 30 mV

–

10

6

–

μA

First active ACMP in

low power mode

Each additional

ACMP in low power

mode

Input Hysteresis V_HYS

Filter Delay¹⁾

t_FDELAY

CC

–

+/-15 –

mV

ns

5

–

1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.

Data Sheet

48

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2.5

Temperature Sensor Characteristics

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 18

Temperature Sensor Characteristics

Parameter

Symbol

Values

Unit Note /

Test Condition

Min. Typ. Max.

Measurement time

t_MCC

−

10

ms

Temperature sensor range

Sensor Accuracy¹⁾

T

_SRSR

-40

−

115 °C

_TSALCC -6

-10

–

6

°C

T_J> 20°C

–

10

–

0°C ≤ T_J≤ 20°C

T_J< 0°C

−

-/+8

Start-up time after enabling

t

_TSSTESR −

−

15

μs

1) The temperature sensor accuracy is independent of the supply voltage.

Data Sheet

49

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2.6

Power Supply Current

The total power supply current defined below consists of a leakage and a switching

component.

Application relevant values are typically lower than those given in the following tables,

and depend on the customer's system operating conditions (e.g. thermal connection or

used application configurations).

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 19

Power Supply Parameters; V_DDP= 5V

Parameter

Symbol

Values

Unit

Note /

Min Typ.¹⁾Max.

.

Test Condition

Active mode current

Peripherals enabled

f_MCLK/ f_PCLKin MHz²⁾

I

_DDPAECC −

9.2

8.1

6.6

5.5

4

12

-

mA

32 / 64

24 / 48

16 / 32

8 / 16

1 / 1

−

-

−

-

−

-

Active mode current

Peripherals disabled

f_MCLK/ f_PCLKin MHz³⁾

_DDPADCC −

4.8

4.1

3.3

2.7

1.5

7.3

6.3

5.2

4.2

3.3

6.6

5.8

5.1

4.4

3.7

-

32 / 64

24 / 48

16 / 32

8 / 16

1 / 1

−

-

−

-

−

-

−

-

Active mode current

_DDPARCC −

-

32 / 64

24 / 48

16 / 32

8 / 16

1 / 1

Code execution from RAM

Flash is powered down

f_MCLK/ f_PCLKin MHz

−

-

−

-

−

-

Sleep mode current

_DDPSECC −

-

32 / 64

24 / 48

16 / 32

8 / 16

1 / 1

Peripherals clock enabled

-

f_MCLK/ f_PCLKin MHz⁴⁾

-

Data Sheet

50

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 19

Power Supply Parameters; V_DDP= 5V

Parameter

Symbol

Values

Unit

Note /

Min Typ.¹⁾Max.

.

Test Condition

Sleep mode current

Peripherals clock disabled

Flash active

I

_DDPSDCC −

_DDPSRCC −

_DDPDSCC −

1.8

1.7

1.6

1.5

1.4

1.2

1.1

1.0

0.8

0.7

0.24

6

-

mA

cycles

32 / 64

24 / 48

16 / 32

8 / 16

1 / 1

f_MCLK/ f_PCLKin MHz⁵⁾

Sleep mode current

32 / 64

24 / 48

16 / 32

8 / 16

1 / 1

Peripherals clock disabled

Flash powered down

f_MCLK/ f_PCLKin MHz⁶⁾

Deep Sleep mode current⁷⁾

Wake-up time from Sleep to t_SSACC

−

Active mode⁸⁾

Wake-up time from Deep

Sleep to Active mode⁹⁾

t

_DSACC

−

280

-

μsec

1) The typical values are measured at T_A= + 25 °C and VDDP = 5 V.

2) CPU and all peripherals clock enabled, Flash is in active mode.

3) CPU enabled, all peripherals clock disabled, Flash is in active mode.

4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.

5) CPU in sleep, Flash is in active mode.

6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.

7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.

8) CPU in sleep, Flash is in active mode during sleep mode.

9) CPU in sleep, Flash is in powered down mode during deep sleep mode.

Data Sheet

51

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Figure 14 shows typical graphs for active mode supply current for V_DDP= 5V, V_DDP

=

3.3V, V_DDP= 1.8V across different clock frequencies.

10

9

8

7

6

IDDPA E 5V/3.3V

IDDPA E 1.8V

5

4

3

2

1

0

I (mA)

IDDPA D 5V/3.3V/1.8V

1/1

8/16

16/32 24/48 32/64

MCLK / PCLK (MHz)

Condition:

1. TA = +25° C

Figure 14

Active mode, a) peripherals clocks enabled, b) peripherals clocks

disabled: Supply current I_DDPAover supply voltage V_{DDP for different clock}

frequencies

Data Sheet

52

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Figure 15 shows typical graphs for sleep mode current for V_DDP= 5V, V_DDP= 3.3V, V_DDP

= 1.8V across different clock frequencies.

1 .4

1 .2

1

0 .8

I (m A)

0 .6

ID DPS R

5 V/3.3V/1.8V

0 .4

0 .2

0

1 /1

8 /1 6 1 6 /32 2 4 /48 3 2 /64

M CLK / P CL K (M Hz)

C o n d itio n :

1 . T A = + 2 5 ° C

Figure 15

Sleep mode, peripherals clocks disabled, Flash powered down:

Supply current I_DDPSRover supply voltage V_{DDP for different clock frequencies}

Data Sheet

53

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 20 provides the active current consumption of some modules operating at 5 V

power supply at 25° C. The typical values shown are used as a reference guide on the

current consumption when these modules are enabled.

Table 20

Typical Active Current Consumption

Active Current

Consumption

Symbol

Limit

Values

Unit

Test Condition

Typ.

Baseload current I_CPUDDC

5.04

mA

Modules including Core, SCU,

PORT, memories, ANATOP¹⁾

VADC and SHS

USIC0

I_ADCDDC

3.4

mA

Set CGATCLR0.VADC to 1²⁾

Set CGATCLR0.USIC0 to 1³⁾

Set CGATCLR0.CCU40 to 1⁴⁾

Set CGATCLR0.CCU80 to 1⁵⁾

Set CGATCLR0.POSIF0 to 1⁶⁾

Set CGATCLR0.BCCU0 to 1⁷⁾

Set CGATCLR0.MATH to 1⁸⁾

Set CGATCLR0.WDT to 1⁹⁾

Set CGATCLR0.RTC to 1¹⁰⁾

I_USIC0DDC0.87

I_CCU40DDC0.94

I_CCU80DDC0.42

CCU40

CCU80

POSIF0

BCCU0

MATH

I_PIF0DDC

0.26

I_BCCU0DDC0.24

I_MATHDDC0.35

WDT

I_WDTDDC

I_RTCDDC

0.03

0.01

RTC

1) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop

in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.

2) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode

3) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms

4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching

from 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle

5) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU8 slice with PWM frequency

at 1500Hz and a period match interrupt used to toggle duty cycle between 10% and 90%

6) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, hall sensor mode

7) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, FCLK=0.8MHz, Normal

mode (BCCU Clk = FCLK/4), 3 BCCU Channels and 1 Dimming Engine, change color or dim every 1s

8) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, tangent calculation in while

loop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11

9) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =

0x00008000; WDT serviced every 1s

10) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled

Data Sheet

54

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.2.7

Flash Memory Parameters

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 21

Flash Memory Parameters

Symbol

Parameter

Values

Unit

Note /

Test Condition

Min. Typ. Max.

Erase Time per

page / sector

t

_ERASECC

_PSERCC

_WUCC

6.8 7.1 7.6

ms

Program time per

block

102 152 204

μs

Wake-Up time

−

32.2

50

−

μs

Read time per word

Data Retention Time

t_aCC

_RETCC

−

ns

t

10

years Max. 100 erase /

program cycles

Flash Wait States ¹⁾

N

_WSFLASHCC 0

0

1

2

1

f_MCLK= 8 MHz

f_MCLK= 16 MHz

f_MCLK= 32 MHz

0

1

0

1

1.3

0

Fixed Flash Wait

States configured in

bit

N_FWSFLASH

SR

NVM_CONFIG1.FI

XWS = 1_B,

f_MCLK≤ 16 MHz

NVM_NVMCONF.WS

1

NVM_CONFIG1.FI

XWS = 1_B,

16 MHz < f_MCLK

≤

32 MHz

Erase Cycles

N

_ECYCCC

−

5*10⁴cycles Sum of page and

sector erase cycles

2*10⁶cycles

Total Erase Cycles

N_TECYCCC

1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical

values are calculated from the execution of the Dhrystone benchmark program.

Data Sheet

55

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3

AC Parameters

3.3.1

Testing Waveforms

V_DDP

90%

10%

V_SS

t_R

t_F

Figure 16

Rise/Fall Time Parameters

V_DDP

V_DDP/ 2

Test Points

V_SS

Figure 17

Testing Waveform, Output Delay

V_LOAD+ 0.1V

V_OH- 0.1V

V_OL+ 0.1V

Timing

Reference

Points

V_LOAD- 0.1V

Figure 18

Testing Waveform, Output High Impedance

Data Sheet

56

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3.2

Power-Up and Supply Monitoring Characteristics

Table 22 provides the characteristics of the power-up and supply monitoring in

XMC1300.

The guard band between the lowest valid operating voltage and the brownout reset

threshold provides a margin for noise immunity and hysteresis. The electrical

parameters may be violated while V_DDPis outside its operating range.

The brownout detection triggers a reset within the defined range. The prewarning

detection can be used to trigger an early warning and issue corrective and/or fail-safe

actions in case of a critical supply voltage drop.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 22

Power-Up and Supply Monitoring Parameters (Operating Conditions

apply)

Parameter

Symbol

Values

Typ. Max.

Unit Note /

Test Condition

Min.

V

_DDPramp-up time

_DDPslew rate

t

_RAMPUPSR V_DDP

/

−

10⁷

0.1

10

μs

S_VDDPrise

S

_VDDPOPSR

0

V/μs Slope during

normal operation

S_VDDP10SR

0

V/μs Slope during fast

transient within +/-

10% of V_DDP

S

_VDDPriseSR

−

10

V/μs Slope during

power-on or

restart after

brownout event

S_VDDPfall¹⁾SR 0

0.25 V/μs Slope during

supply falling out

of the +/-10%

limits²⁾

V

_DDPprewarning

V

_DDPPWCC 2.1

2.85

4.2

2.25 2.4

V

ANAVDEL.VDEL_

SELECT = 00_B

voltage

3

3.15

4.6

ANAVDEL.VDEL_

SELECT = 01_B

4.4

ANAVDEL.VDEL_

SELECT = 10_B

Data Sheet

57

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 22

Power-Up and Supply Monitoring Parameters (Operating Conditions

apply) (cont’d)

Parameter

Symbol

Values

Typ. Max.

1.62 1.75

Unit Note /

Test Condition

Min.

_DDPBOCC 1.55

V

_DDPbrownout reset

V

calibrated, before

user code starts

running

voltage

V

_DDPvoltage to

_DDPPACC

−

1.0

−

–

V

ensure defined pad

states

Start-up time from

power-on reset

t

_SSWSR

320

8.25

μs

ms

Time to the first

user code

instruction³⁾

BMI program time

_BMISR

Time taken from a

user-triggered

system reset after

BMI installation is

is requested

1) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated

for this parameter.

2) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to

the chip. A larger capacitor value has to be chosen if the power source sink a current.

3) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz

and the clocks to peripheral as specified in register CGATSTAT0 are gated.

5.0V

V_DDPPW

}

VDDP

V_DDPBO

Figure 19

Supply Threshold Parameters

Data Sheet

58

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3.3

On-Chip Oscillator Characteristics

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 23 provides the characteristics of the 64 MHz clock output from the digital

controlled oscillator, DCO1 in XMC1300.

Table 23

64 MHz DCO1 Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Conditions

Min. Typ. Max.

Nominal frequency f_NOMCC

–

64

–

MHz under nominal

conditions¹⁾after

trimming

Accuracy²⁾

Δf_LTCC -1.7

–

3.4

4.0

%

with respect to f_NOM(typ),

over temperature

(T_A= 0 °C to 85 °C)

-3.9

–

%

with respect to f_NOM(typ),

over temperature

(T_A= -40 °C to 105 °C)

1) The deviation is relative to the factory trimmed frequency at nominal V_DDCand T_A= + 25 °C.

2) The accuracy can be further improved through alternative methods, refer to XMC1000 Oscillator Handling

Application Note.

Data Sheet

59

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Figure 20 shows the typical curves for the accuracy of DCO1, with and without

calibration based on temperature sensor, respectively.

4.00

3.00

2.00

Without calibration based

on temperature sensor

1.00

With calibration based on

temperature sensor

0.00

-1.00

-2.00

-3.00

-4.00

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100 110 120

°

Temperature [ C]

Figure 20

Typical DCO1 accuracy over temperature

Table 24 provides the characteristics of the 32 kHz clock output from digital controlled

oscillators, DCO2 in XMC1300.

Table 24

32 kHz DCO2 Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Conditions

Min. Typ. Max.

Nominal frequency

Accuracy

f_NOMCC –

32.75 –

kHz under nominal

conditions¹⁾after trimming

Δf_LTCC -1.7

–

3.4

%

with respect to f_NOM(typ),

over temperature

(0 °C to 85 °C)

-3.9

4.0

with respect to f_NOM(typ),

over temperature

(-40 °C to 105 °C)

1) The deviation is relative to the factory trimmed frequency at nominal V_DDCand T_A= + 25 °C.

Data Sheet

60

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3.4

Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP

interface.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 25

SWD Interface Timing Parameters(Operating Conditions apply)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

50

Typ. Max.

SWDCLK high time

SWDCLK low time

t1 SR

t₂SR

t3 SR

–

500000 ns

–

50

SWDIO input setup

10

–

ns

to SWDCLK rising edge

SWDIO input hold

t₄SR

10

–

ns

–

after SWDCLK rising edge

SWDIO output valid time t₅CC

after SWDCLK rising edge

–

4

–

68

62

–

ns

C_L= 50 pF

C_L= 30 pF

SWDIO output hold time t₆CC

from SWDCLK rising edge

t₁

t₂

SWDCLK

t₆

SWDIO

(Output)

t₅

t₃

t₄

SWDIO

(Input )

Figure 21

SWD Timing

Data Sheet

61

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3.5

SPD Timing Requirements

The optimum SPD decision time between 0_Band 1_Bis 0.75 µs. With this value the

system has maximum robustness against frequency deviations of the sampling clock on

tool and on device side. However it is not always possible to exactly match this value

with the given constraints for the sample clock. For instance for a oversampling rate of

4, the sample clock will be 8 MHz and in this case the closest possible effective decision

time is 5.5 clock cycles (0.69 µs).

Table 26

Optimum Number of Sample Clocks for SPD

Sample Effective Remark

Sample Sampling Sample

Freq.

Factor

Clocks 0_BClocks 1_BDecision

Time¹⁾

8 MHz

4

1 to 5

6 to 12

0.69 µs

The other closest option

(0.81 µs) for the effective

decision time is less robust.

1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0_Bsample clocks)

For a balanced distribution of the timing robustness of SPD between tool and device, the

timing requirements for the tool are:

•

Frequency deviation of the sample clock is +/- 5%

Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal

sample frequency)

Data Sheet

62

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3.6

Peripheral Timings

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note: Operating Conditions apply.

Table 27

USIC SSC Master Mode Timing

Symbol Values

Typ. Max.

Parameter

Unit Note /

Test Condition

Min.

_CLKCC 62.5

SCLKOUT master clock

period

t

−

ns

Slave select output SELO t₁CC 80

active to first SCLKOUT

transmit edge

−

Slave select output SELO t₂CC

inactive after last

0

−

ns

SCLKOUT receive edge

Data output DOUT[3:0]

valid time

t₃CC -10

t₄SR 80

−

10

ns

Receive data input

−

DX0/DX[5:3] setup time to

SCLKOUT receive edge

Data input DX0/DX[5:3]

hold time from SCLKOUT

receive edge

t₅SR

0

−

ns

Data Sheet

63

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 28

USIC SSC Slave Mode Timing

Parameter

Symbol

Min.

Values

Unit Note /

Test Condition

Typ. Max.

DX1 slave clock period

t_CLKSR 125

t₁₀SR 10

−

ns

Select input DX2 setup to

first clock input DX1 transmit

edge¹⁾

Select input DX2 hold after t₁₁SR 10

last clock input DX1 receive

edge¹⁾

−

ns

Receive data input

t₁₂SR 10

−

DX0/DX[5:3] setup time to

shift clock receive edge¹⁾

Data input DX0/DX[5:3] hold t₁₃SR 10

time from clock input DX1

receive edge¹⁾

−

Data output DOUT[3:0] valid t₁₄CC -

80

time

1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and

receive data input (bits DXnCR.DSEN = 0).

Data Sheet

64

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Master Mode Timing

t₁

t₂

Select Output

SELOx

Inactive

Active

Clock Output

SCLKOUT

Receive

Edge

Last Receive

Edge

First Transmit

Edge

Transmit

Edge

t₃

Data Output

DOUT[3:0]

t₄

t₅

Data Input

DX0/DX[5:3]

Data

valid

Data

valid

Slave Mode Timing

t₁₀

t₁₁

Select Input

DX2

Inactive

Active

Inactive

Clock Input

DX1

Receive

Edge

Last Receive

Edge

First Transmit

Edge

Transmit

Edge

t₁₂

t₁₃

Data Input

DX0/DX[5:3]

Data

valid

Data

valid

t₁₄

Data Output

DOUT[3:0]

Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.

Receive Edge: with this clock edge, receive data at receive data input is latched.

Drawn for BRGH.SCLKCFG = 00_B. Also valid for for SCLKCFG = 01_Bwith inverted SCLKOUT signal.

USIC_SSC_TMGX.VSD

Figure 22

USIC - SSC Master/Slave Mode Timing

Note: This timing diagram shows a standard configuration, for which the slave select

signal is low-active, and the serial clock signal is not shifted and not inverted.

Data Sheet

65

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

3.3.6.2 Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.

Note: Operating Conditions apply.

Table 29

USIC IIC Standard Mode Timing¹⁾

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Fall time of both SDA and t₁

-

300

ns

µs

ns

µs

SCL

CC/SR

Rise time of both SDA and t₂

-

1000

SCL

CC/SR

Data hold time

t₃

0

-

CC/SR

Data set-up time

t₄

250

4.7

4.0

4.7

4.0

4.7

CC/SR

LOW period of SCL clock t₅

CC/SR

HIGH period of SCL clock t₆

CC/SR

t₇

CC/SR

Hold time for (repeated)

START condition

Set-up time for repeated t₈

START condition

CC/SR

Set-up time for STOP

condition

t₉

CC/SR

Bus free time between a t₁₀

STOP and START

CC/SR

condition

Capacitive load for each

bus line

C_bSR

-

400

pF

1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines

need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,

approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

Data Sheet

66

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

Table 30

USIC IIC Fast Mode Timing¹⁾

Parameter

Symbol

Min.

Values

Typ.

-

Unit Note /

Test Condition

Max.

Fall time of both SDA and t₁

20 +

300

ns

SCL CC/SR 0.1*C_b

2)

Rise time of both SDA and t₂

20 +

-

300

ns

µs

ns

µs

SCL

CC/SR 0.1*C_b

Data hold time

t₃

0

-

CC/SR

Data set-up time

t₄

100

1.3

0.6

1.3

CC/SR

LOW period of SCL clock t₅

CC/SR

HIGH period of SCL clock t₆

CC/SR

t₇

CC/SR

Hold time for (repeated)

START condition

Set-up time for repeated t₈

START condition

CC/SR

Set-up time for STOP

condition

t₉

CC/SR

Bus free time between a t₁₀

STOP and START

CC/SR

condition

Capacitive load for each

bus line

C_bSR

-

400

pF

1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines

need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,

approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

2) C_brefers to the total capacitance of one bus line in pF.

Data Sheet

67

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

t₁

t₂

t₄

70%

30%

SDA

SCL

t₁

t₃

t₂

t₆

9^th

clock

t₇

t₅

t₁₀

S

SDA

SCL

t₈

t₇

t₉

9^th

clock

Sr

P

S

Figure 23

USIC IIC Stand and Fast Mode Timing

3.3.6.3 Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.

Note: Operating Conditions apply.

Table 31

USIC IIS Master Transmitter Timing

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

Clock period

t₁CC

2/f_MCLK

4/f_MCLK

-

ns

V_DDP≥ 3 V

V_DDP< 3 V

Clock HIGH

Clock Low

t₂CC

t₃CC

0.35 x

t_1min

0.35 x

t_1min

-

ns

Hold time

t₄CC

t₅CC

0

-

ns

Clock rise time

0.15 x ns

t_1min

Data Sheet

68

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Electrical Parameters

t₁

t₂

t₅

t₄

t₃

SCK

WA/

DOUT

Figure 24

USIC IIS Master Transmitter Timing

USIC IIS Slave Receiver Timing

Table 32

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

Clock period

Clock HIGH

t₆SR

t7 SR

4/f_MCLK

-

ns

0.35 x

t_6min

Clock Low

Set-up time

Hold time

t8 SR

t9 SR

0.35 x

t₆min

-

ns

0.2 x

t₆min

t10 SR 10

t₆

t₇

t₈

t₉

SCK

t₁₀

WA/

DIN

Figure 25

USIC IIS Slave Receiver Timing

Data Sheet

69

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

4

Package and Reliability

The XMC1300 is a member of the XMC1000 Family of microcontrollers. It is also

compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight

differences between packages of the same pin-count but for different device types. In

particular, the size of the exposed die pad may vary.

If different device types are considered or planned for an application, it must be ensured

that the board layout fits all packages under consideration.

4.1

Package Parameters

Table 33 provides the thermal characteristics of the packages used in XMC1300.

Table 33

Thermal Characteristics of the Packages

Parameter

Symbol

Limit Values

Min. Max.

Unit

Package Types

Exposed Die Pad

Dimensions

Ex × Ey

CC

-

2.7 × 2.7 mm

3.7 × 3.7 mm

PG-VQFN-24-19

PG-VQFN-40-13

PG-TSSOP-16-8¹⁾

PG-TSSOP-28-16¹⁾

PG-TSSOP-38-9¹⁾

PG-VQFN-24-19¹⁾

PG-VQFN-40-13¹⁾

Thermal resistance

Junction-Ambient

R_ΘJACC -

104.6

83.2

70.3

46.0

38.4

K/W

-

1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.

Note: For electrical reasons, it is required to connect the exposed pad to the board

ground V_SSP, independent of EMC and thermal requirements.

4.1.1

Thermal Considerations

When operating the XMC1300 in a system, the total heat generated in the chip must be

dissipated to the ambient environment to prevent overheating and the resulting thermal

damage.

The maximum heat that can be dissipated depends on the package and its integration

into the target board. The “Thermal resistance R_ΘJA” quantifies these parameters. The

power dissipation must be limited so that the average junction temperature does not

exceed 115 °C.

Data Sheet

70

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

The difference between junction temperature and ambient temperature is determined by

ΔT = (P_INT+ P_IOSTAT+ P_IODYN) × R_ΘJA

The internal power consumption is defined as

P

_INT= V_DDP× I_DDP(switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

_IOSTAT= Σ((V_DDP-V_OH) × I_OH) + Σ(V_OL× I_OL)

P

The dynamic external power consumption caused by the output drivers (P_IODYN) depends

on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit,

countermeasures must be taken to ensure proper system operation:

•

Reduce V_DDP, if possible in the system

Reduce the system frequency

Reduce the number of output pins

Reduce the load on active output drivers

Data Sheet

71

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

4.2

Package Outlines

Figure 26

PG-TSSOP-38-9

Data Sheet

72

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

Figure 27

PG-TSSOP-28-16

Data Sheet

73

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

Figure 28

PG-TSSOP-16-8

Data Sheet

74

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

Figure 29

PG-VQFN-24-19

Data Sheet

75

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Package and Reliability

Figure 30

PG-VQFN-40-13

All dimensions in mm.

Data Sheet

76

V2.0, 2017-10

XMC1300 AB-Step

XMC1000 Family

Quality Declaration

5

Quality Declaration

Table 34 shows the characteristics of the quality parameters in the XMC1300.

Table 34

Quality Parameters

Symbol Limit Values

Parameter

Unit Notes

Min.

Max.

ESD susceptibility

according to Human Body SR

Model (HBM)

V_HBM

-

2000

V

Conforming to

EIA/JESD22-

A114-B

ESD susceptibility

V_CDM

-

500

Conforming to

according to Charged

Device Model (CDM) pins

SR

JESD22-C101-C

Moisture sensitivity level

MSL

CC

-

3

-

JEDEC

J-STD-020D

Soldering temperature

T_SDR

SR

260

°C

Profile according

to JEDEC

J-STD-020D

Data Sheet

77

V2.0, 2017-10

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	XMC1302-T028X0128 AB
厂家：	Infineon
描述：	32-bit XMC1000 Industrial Microcontroller ARM® Cortex®-M0 微控制器
文件：	总78页 (文件大小：2710K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XMC1302-T028X0128 AB [INFINEON]

相关型号：

XMC1302-T028X0200 AB

XMC1302-T038

XMC1302-T038X0016

XMC1302-T038X0032

XMC1302-T038X0064

XMC1302-T038X0128

XMC1302-T038X0200

XMC1302-T038X0200AA

XMC1302-T038X0200AA_15

XMC1302T016X0032ABXUMA1

XMC1302T038X0016ABXUMA1

XMC1302T038X0032ABXUMA1