XMC4100/XMC4200 [INFINEON]
32-bit XMC1000 Industrial Microcontroller ARM® Cortex®-M0;
| 型号： | XMC4100/XMC4200 |
| 厂家： | 
Infineon |
| 描述： | 32-bit XMC1000 Industrial Microcontroller ARM® Cortex®-M0 微控制器 |
| 文件： | 总91页 (文件大小：2166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XMC4100 / XMC4200
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Data Sheet
V1.5 2023-04
Microcontrollers
Edition 2023-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2023 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
XMC4100 / XMC4200
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Data Sheet
V1.5 2023-04
Microcontrollers
XMC4100 / XMC4200
XMC4000 Family
XMC4[12]00 Data Sheet
Revision History: V1.5 2023-04
Previous Versions:
V1.4 2018-09
V1.3 2015-10
V1.2 2014-06
V1.1 2014-03
V1.0 2013-10
V0.6 2012-11
Page
Subjects
V1.5 2023-04
86
Deleted package details: PG-LQFP-64-19 and PG-VQFN-48-53.
Added package details: PG-TQFP-64-21.
88
89
Deleted Table 56 and 57.
Added package diagram: PG-TQFP-64-21.
Deleted package diagram: PG-LQFP-64-19.
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1
1.2
1.3
1.4
1.5
1.6
2
2.1
2.2
2.2.1
2.2.2
2.2.2.1
2.3
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3
3.1
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 34
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Digital to Analog Converters (DACx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
High Resolution PWM (HRPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
HRC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CMP and 10-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 51
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low Power Analog Comparator (LPAC) . . . . . . . . . . . . . . . . . . . . . . . . 55
Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
USB Device Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 57
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.5.1
3.2.5.2
3.2.5.3
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.3
3.3.1
3.3.2
3.3.3
Data Sheet
5
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Table of Contents
3.3.4
3.3.5
3.3.6
3.3.7
Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . 72
Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 73
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 77
Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 78
Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 83
USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.3.8
3.3.8.1
3.3.8.2
3.3.8.3
3.3.9
4
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1
4.1.1
4.2
5
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Data Sheet
6
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
About this Document
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC4[12]00 series devices.
The document describes the characteristics of a superset of the XMC4[12]00 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4[12]00 throughout this manual.
XMC4000 Family User Documentation
The set of user documentation includes:
•
Reference Manual
– describes the functionality of the superset of devices.
Data Sheets
•
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•
Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
Data Sheet
7
V1.4, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
1
Summary of Features
The XMC4[12]00 devices are members of the XMC4000 Family of microcontrollers
based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high
performance and energy efficient microcontrollers optimized for Industrial Connectivity,
Industrial Control, Power Conversion, Sense & Control.
Figure 1
System Block Diagram
CPU Subsystem
•
CPU Core
– High Performance 32-bit ARM Cortex-M4 CPU
– 16-bit and 32-bit Thumb2 instruction set
– DSP/MAC instructions
– System timer (SysTick) for Operating System support
Floating Point Unit
Memory Protection Unit
Nested Vectored Interrupt Controller
One General Purpose DMA with up-to 8 channels
Event Request Unit (ERU) for programmable processing of external and internal
service requests
•
•
•
•
•
•
Flexible CRC Engine (FCE) for multiple bit error detection
Data Sheet
8
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Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
On-Chip Memories
•
•
•
•
16 KB on-chip boot ROM
up to 16 KB on-chip high-speed program memory
up to 24 KB on-chip high speed data memory
up to 256 KB on-chip Flash Memory with 1 KB instruction cache
Communication Peripherals
•
•
Universal Serial Bus, USB 2.0 device, with integrated PHY
Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with two nodes,
64 message objects (MO), data rate up to 1 MBit/s
•
•
Four Universal Serial Interface Channels (USIC), providing four serial channels,
usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
Analog Frontend Peripherals
•
Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
•
Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals
•
•
•
•
•
•
•
•
Two Capture/Compare Units 4 (CCU4) for use as general purpose timers
One Capture/Compare Units 8 (CCU8) for motor control and power conversion
Four High Resoultion PWM (HRPWM) channels
One Position Interface (POSIF) for servo motor positioning
Window Watchdog Timer (WDT) for safety sensitive applications
Die Temperature Sensor (DTS)
Real Time Clock module with alarm support
System Control Unit (SCU) for system configuration and control
Input/Output Lines
•
•
•
•
•
Programmable port driver control module (PORTS)
Individual bit addressability
Tri-stated in input mode
Push/pull or open drain output mode
Boundary scan test support over JTAG interface
On-Chip Debug Support
•
•
Full support for debug features: 8 breakpoints, CoreSight, trace
Various interfaces: ARM-JTAG, SWD, single wire trace
Data Sheet
9
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
1.1
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
•
•
<DDD> the derivatives function set
<Z> the package variant
– E: LFBGA
– F: LQFP, TQFP
– Q: VQFN
•
•
<PPP> package pin count
<T> the temperature range:
– F: -40°C to 85°C
– K: -40°C to 125°C
•
<FFFF> the Flash memory size.
For ordering codes for the XMC4[12]00 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4100 and XMC4200 series,
some descriptions may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4[12]00 is used for all derivatives throughout this document.
1.2
Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XMC4[12]00 Device Types
Derivative1)
Package
Flash Kbytes
SRAM Kbytes
XMC4200-F64x256
XMC4200-Q48x256
XMC4100-F64x128
XMC4100-Q48x128
XMC4104-F64x64
XMC4104-Q48x64
XMC4104-F64x128
XMC4104-Q48x128
XMC4108-F64x64
XMC4108-Q48x64
PG-yQFP-642)
PG-VQFN-48
PG-yQFP-642)
PG-VQFN-48
PG-yQFP-642)
PG-VQFN-48
PG-yQFP-642)
PG-VQFN-48
PG-yQFP-642)
PG-VQFN-48
256
256
128
128
64
40
40
20
20
20
20
20
20
20
20
64
128
128
64
64
1) x is a placeholder for the supported temperature range.
2) y is a placeholder for the QFP package variant, LQFP or TQFP depending on the stepping, see Section 1.3.
Data Sheet
10
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
1.3
Package Variants
Different markings of the XMC4[12]00 use different package variants. Details of those
packages are given in the “Package Parameters” section of the Data Sheet.
Table 2
XMC4[12]00 Package Variants
Package Variant
XMC4[12]00-F64
XMC4[12]00-Q48
XMC4[12]00-F64
XMC4[12]00-Q48
Marking
Package
EES-AA, ES-AA, ES-AB, AB
PG-LQFP-64-19
PG-VQFN-48-53
PG-TQFP-64-19
PG-VQFN-48-71
BA
1.4
Device Type Features
The following table lists the available features per device type.
Table 3
Features of XMC4[12]00 Device Types
Derivative1)
LEDTS Intf.
USB Intf.
USIC Chan. MultiCAN
Nodes, MO
XMC4200-F64x256
XMC4200-Q48x256
XMC4100-F64x128
XMC4100-Q48x128
1
1
1
1
1
1
1
1
2 x 2
2 x 2
2 x 2
2 x 2
N0, N1
MO[0..63]
N0, N1
MO[0..63]
N0, N1
MO[0..63]
N0, N1
MO[0..63]
XMC4104-F64x64
XMC4104-Q48x64
XMC4104-F64x128
XMC4104-Q48x128
XMC4108-F64x64
XMC4108-Q48x64
1
1
1
1
2 x 2
2 x 2
2 x 2
2 x 2
2 x 2
2 x 2
N0, MO[0..31]
N0, MO[0..31]
1) x is a placeholder for the supported temperature range.
Data Sheet
11
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Table 4
Features of XMC4[12]00 Device Types
Derivative1)
ADC
Chan.
DAC
Chan.
CCU4
Slice
CCU8
Slice
POSIF
Intf.
HRPWM
Intf.
XMC4200-F64x256
XMC4200-Q48x256
XMC4100-F64x128
XMC4100-Q48x128
XMC4104-F64x64
XMC4104-Q48x64
XMC4104-F64x128
XMC4104-Q48x128
XMC4108-F64x64
XMC4108-Q48x64
10
9
2
2
2
2
2
2
2
2
2
2
2 x 4
2 x 4
2 x 4
2 x 4
2 x 4
2 x 4
2 x 4
2 x 4
2 x 4
2 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1 x 4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
9
10
9
10
9
10
9
1) x is a placeholder for the supported temperature range.
1.5
Definition of Feature Variants
The XMC4[12]00 types are offered with several memory sizes and number of available
VADC channels. Table 5 describes the location of the available Flash memory, Table 6
describes the location of the available SRAMs, Table 7 the available VADC channels.
Table 5
Flash Memory Ranges
Total Flash Size
Cached Range
Uncached Range
256 Kbytes
0800 0000H
0C00 0000H
0803 FFFFH
0C03 FFFFH
128 Kbytes
64 Kbytes
0800 0000H
0801 FFFFH
0C00 0000H
0C01 FFFFH
0800 0000H
0C00 0000H
0800 FFFFH
0C00 FFFFH
Data Sheet
12
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Table 6
SRAM Memory Ranges
Total SRAM Size
Program SRAM
System Data SRAM
40 Kbytes
1FFF C000H
2000 0000H
1FFF FFFFH
2000 5FFFH
20 Kbytes
1FFF E000H
2000 0000H
1FFF FFFFH
2000 2FFFH
Table 7
ADC Channels1)
Package
VADC G0
VADC G1
LQFP-64, TQFP-64
PG-VQFN-48
CH0, CH3..CH7
CH0, CH3..CH7
CH0, CH1, CH3, CH6
CH0, CH1, CH3
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function table.
1.6
Identification Registers
The identification registers allow software to identify the marking.
Table 8 XMC4200 Identification Registers
Register Name
SCU_IDCHIP
SCU_IDCHIP
SCU_IDCHIP
JTAG IDCODE
JTAG IDCODE
JTAG IDCODE
Value
Marking
0004 2001H
0004 2002H
0004 2003H
101D D083H
201D D083H
301D D083H
EES-AA, ES-AA
ES-AB, AB
BA
EES-AA, ES-AA
ES-AB, AB
BA
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
Summary of Features
Table 9
XMC4100 Identification Registers
Register Name
SCU_IDCHIP
SCU_IDCHIP
SCU_IDCHIP
JTAG IDCODE
JTAG IDCODE
JTAG IDCODE
Value
Marking
0004 2001H
0004 2002H
0004 1003H
101D D083H
201D D083H
301D D083H
EES-AA, ES-AA
ES-AB, AB
BA
EES-AA, ES-AA
ES-AB, AB
BA
Data Sheet
14
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
2
General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1
Logic Symbols
Figure 2
XMC4[12]00 Logic Symbol PG-LQFP-64 and PG-TQFP-64
Data Sheet
15
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
Figure 3
XMC4[12]00 Logic Symbol PG-VQFN-48
Data Sheet
16
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
2.2
Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
Figure 4
XMC4[12]00 PG-LQFP-64 and PG-TQFP-64 Pin Configuration
(top view)
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
Figure 5
XMC4[12]00 PG-VQFN-48 Pin Configuration (top view)
Data Sheet
18
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
2.2.1
Package Pin Summary
The following general scheme is used to describe each pin:
Table 10
Function
Package Pin Mapping Description
Package A
Package B
...
Pad
Notes
Type
Name
N
Ax
...
A1+
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the respective pin/function is given, i.e. deviations
from the default configuration after reset. Per default the regular Port pins are configured
as direct input with no internal pull device active.
Table 11
Function
Package Pin Mapping
LQFP-64
TQFP-64
VQFN-48
Pad Type
Notes
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
2
2
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
1
1
64
63
62
61
60
58
48
47
46
45
44
43
After a system reset, via
HWSEL this pin selects the
DB.TDI function.
P0.8
57
42
A1+
After a system reset, via
HWSEL this pin selects the
DB.TRST function, with a
weak pull-down active.
P0.9
4
3
-
-
A1+
A1+
P0.10
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
Table 11
Function
Package Pin Mapping (cont’d)
LQFP-64
TQFP-64
VQFN-48
Pad Type
Notes
P0.11
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.7
P1.8
P1.9
P1.15
P2.0
P2.1
59
52
51
50
49
48
47
55
54
53
46
34
33
-
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
A1+
40
39
38
37
36
35
-
-
-
-
26
25
After a system reset, via
HWSEL this pin selects the
DB.TDO function.
P2.2
32
31
30
29
36
35
28
27
26
25
5
24
23
22
21
-
A1+
P2.3
A1+
P2.4
A1+
P2.5
A1+
P2.6
A1+
P2.7
-
A1+
P2.8
-
A1+
P2.9
-
A1+
P2.14
P2.15
P3.0
-
A1+
-
A1+
-
A1+
P14.0
P14.3
P14.4
P14.5
P14.6
P14.7
P14.8
20
19
18
17
16
15
24
16
15
14
13
12
11
20
AN/DIG_IN
AN/DIG_IN
AN/DIG_IN
AN/DIG_IN
AN/DIG_IN
AN/DIG_IN
AN/DAC/DIG_IN
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
Table 11
Function
Package Pin Mapping (cont’d)
LQFP-64
TQFP-64
VQFN-48
Pad Type
Notes
P14.9
23
14
7
19
-
AN/DAC/DIG_IN
AN/DIG_IN
special
P14.14
USB_DP
USB_DM
HIB_IO_0
4
6
3
special
10
7
A1 special
At the first power-up and with
every reset of the hibernate
domain this pin is configured
as open-drain output and
drives "0".
As output the medium driver
mode is active.
TCK
TMS
45
44
34
33
A1
Weak pull-down active.
A1+
Weak pull-up active.
As output the strong-soft
driver mode is active.
PORST
43
32
special
Strong pull-down controlled
by EVR.
Weak pull-up active while
strong pull-down is not active.
XTAL1
39
40
11
12
13
29
30
8
clock_IN
clock_O
clock_IN
clock_O
Power
XTAL2
RTC_XTAL1
RTC_XTAL2
VBAT
9
10
When VDDP is supplied
VBAT has to be supplied as
well.
VDDA/VAREF 22
VSSA/VAGND 21
18
17
AN_Power/AN_ Shared analog supply and
Ref reference voltage pin.
AN_Power/AN_ Shared analog supply and
Ref
reference ground pin.
VDDC
VDDC
VDDP
VDDP
VDDP
VSS
9
6
Power
Power
Power
Power
Power
Power
42
8
31
5
38
56
37
28
41
27
Data Sheet
21
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
Table 11
Function
Package Pin Mapping (cont’d)
LQFP-64
TQFP-64
VQFN-48
Pad Type
Notes
VSSO
VSS
41
-
Power
Power
Exp. Pad
Exp. Pad
Exposed Die Pad
The exposed die pad is
connected internally to VSS.
For proper operation, it is
mandatory to connect the
exposed pad directly to the
common ground on the
board.
For thermal aspects, please
refer to the Data Sheet.
Board layout examples are
given in an application note.
Data Sheet
22
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
General Device Information
2.2.2
Port I/O Functions
The following general scheme is used to describe each PORT pin:
Table 12
Function
Port I/O Function Description
Outputs
Inputs
Input
ALT1
ALTn
HWO0
HWI0
Input
P0.0
Pn.y
MODA.OUT MODB.OUT MODB.INA MODC.INA
MODA.INA MODC.INB
MODA.OUT
Figure 6
Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly driven by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Data Sheet
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Data Sheet
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Data Sheet
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Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
2.3
Power Connection Scheme
Figure 7 shows a reference power connection scheme for the XMC4[12]00.
Figure 7
Power Connection Scheme
Every power supply pin needs to be connected. Different pins of the same supply need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 μF capacitor is connected to the VDDP nets and
an additional 4.7uF capacitor to the VDDC nets.
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
The XMC4[12]00 has a common ground concept, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
There are no dedicated connections for the analog reference VAREF and VAGND. Instead,
they share the same pins as the analog supply pins VDDA and VSSA.Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP
.
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3
Electrical Parameters
3.1
General Parameters
3.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the
XMC4[12]00 and partly its requirements on the system. To aid interpreting the
parameters easily when evaluating them for a design, they are marked with an two-letter
abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics, which are a distinctive feature
of the XMC4[12]00 and must be regarded for system design.
SR
•
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4[12]00 is designed in.
Data Sheet
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V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.1.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 14
Absolute Maximum Rating Parameters
Symbol Values
Min. Typ. Max.
Parameter
Unit Note /
Test Con
dition
Storage temperature
Junction temperature
TST SR -65
TJ SR -40
–
–
150
150
4.3
C
°C
V
–
–
–
Voltage at 3.3 V power supply VDDP SR
pins with respect to VSS
–
Voltage on any Class A and VIN
dedicated input pin with
respect to VSS
SR -1.0
–
V
DDP + 1.0
V
whichever
is lower
or max. 4.3
Voltage on any analog input VAIN
-1.0
–
–
–
V
DDP + 1.0
V
whichever
is lower
pin with respect to VAGND
VAREF SR
or max. 4.3
Input current on any pin
during overload condition
IIN
SR -10
+10
mA
mA
Absolute maximum sum of all IIN SR -25
input circuit currents for one
port group during overload
condition1)
+25
Absolute maximum sum of all IIN SR -100 –
input circuit currents during
+100
mA
overload condition
1) The port groups are defined in Table 18.
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 8 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in “Pin Reliability in Overload".
Figure 8
Absolute Maximum Input Voltage Ranges
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.1.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 15 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time is not exceeded
“Operating Conditions" are met for
– pad supply levels (VDDP or VDDA
)
– temperature
If a pin current is outside of the “Operating Conditions" but within the overload
parameters, then the parameters functionality of this pin as stated in the Operating
Conditions can no longer be guaranteed. Operation is still possible in most cases but
with relaxed parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
Table 15
Overload Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin IOV SR -5
during overload condition
–
–
–
–
5
mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
IOVG SR
–
–
–
20
20
80
mA IOVx|, for all
IOVx 0 mA
mA IOVx|, for all
IOVx 0 mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR
mA IOVG
1) The port groups are defined in Table 18.
Figure 9 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Data Sheet
32
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 9
Input Overload Current via ESD structures
Table 16 and Table 17 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the “Absolute Maximum
Ratings" must not be exceeded during overload.
Table 16
Pad Type
A1 / A1+
PN-Junction Characterisitics for positive Overload
OV = 5 mA, TJ = -40 °C OV = 5 mA, TJ = 150 °C
I
I
V
V
IN = VDDP + 1.0 V
IN = VDDP + 1.0 V
V
V
IN = VDDP + 0.75 V
IN = VDDP + 0.75 V
AN/DIG_IN
Table 17
Pad Type
A1 / A1+
PN-Junction Characterisitics for negative Overload
OV = 5 mA, TJ = -40 °C OV = 5 mA, TJ = 150 °C
I
I
V
V
IN = VSS - 1.0 V
IN = VDDP - 1.0 V
V
V
IN = VSS - 0.75 V
IN = VDDP - 0.75 V
AN/DIG_IN
Table 18
Port Groups for Overload and Short-Circuit Current Sum
Parameters
Group
Pins
1
2
3
4
P0.[12:0], P3.0
P14.[8:0]
P2.[15:0]
P1.[15:0]
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.1.4
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the “Input/Output
Pins".
Table 19
Pad Driver and Pad Classes Overview
Class Power Type
Supply
Sub-Class
Speed
Grade
Load Termination
A
3.3 V
LVTTL A1
6 MHz
100 pF No
I/O,
(e.g. GPIO)
LVTTL
outputs
A1+
(e.g. serial I/Os)
25 MHz
50 pF Series termination
recommended
Figure 10
Output Slopes with different Pad Driver Modes
Figure 10 is a qualitative display of the resulting output slope performance with
different output driver modes. The detailed input and output characteristics are listed in
“Input/Output Pins".
Data Sheet
34
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.1.5
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4[12]00. All parameters specified in the following
tables refer to these operating conditions, unless noted otherwise.
Table 20
Operating Conditions Parameters
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
Typ.
Max.
85
Ambient Temperature
TA SR -40
°C
°C
V
Temp. Range F
Temp. Range K
-40
125
3.632)
Digital supply voltage
Core Supply Voltage
V
DDP SR 3.131) 3.3
VDDC
CC
1)
1.3
V
Generated
internally
Digital ground voltage
VSS SR 0
DDA SR 3.0
3.62)
V
V
ADC analog supply
voltage
V
3.3
Analog ground voltage for VSSA SR -0.1
0
0.1
V
V
VDDA
Battery Supply Voltage
for Hibernate Domain3)
V
BAT SR 1.954)
3.63
When VDDP is
supplied VBAT
has to be
supplied as well.
System Frequency
fSYS SR
80
5
MHz
mA
Short circuit current of
digital outputs
ISC SR -5
Absolute sum of short
circuit currents per pin
group5)
ISC_PG
SR
20
mA
mA
Absolute sum of short
circuit currents of the
device
ISC_D
SR
100
1) See also the Supply Monitoring thresholds, Section 3.3.2.
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 s and the cumulated sum of the pulses does not exceed 1 h over lifetime.
3) Different limits apply for LPAC operation, Section 3.2.6.
4) To start the hibernate domain it is required that VBAT 2.1 V, for a reliable start of the oscillation of RTC_XTAL
in crystal mode it is required that VBAT 3.0 V.
5) The port groups are defined in Table 18.
Data Sheet
35
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.2
DC Parameters
3.2.1
Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
The pull-up characteristics (IPUH) and the input high and low voltage levels (VIH and VIL)
of the PORST pin are identical to the respective values of the standard digital
input/output pins.
Table 21
Standard Pad Parameters
Parameter
Symbol
Min.
Values
Max.
Unit Note / Test Condition
Pin capacitance (digital CIO CC
10
pF
inputs/outputs)
1)
Pull-down current
Pull-up current
|IPDL
SR
|
150
A
A
A
A
V
V
V
V
V
0.6 VDDP
0.36 VDDP
0.6 VDDP
0.36 VDDP
IN
IN
IN
IN
2)
2)
1)
10
10
|IPUH
SR
|
100
Input Hysteresis for
HYSA
0.1
VDDP
pads of all A classes3) CC
PORST spike filter
always blocked pulse
duration
t
SF1 CC
10
ns
ns
PORST spike filter
pass-through pulse
duration
t
SF2 CC 100
PORST pull-down
current
|IPPD
CC
|
13
mA Vi 1.0 V
1) Current required to override the pull device with the opposite logic level (“force current”).
With active pull device, at load currents between force and keep current the input state is undefined.
2) Load current at which the pull device still maintains the valid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet
36
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 11
Pull Device Input Characteristics
Figure 11 visualizes the input characteristics with an active internal pull device:
•
•
in the cases “A” the internal pull device is overridden by a strong external driver;
in the cases “B” the internal pull device defines the input logical state against a weak
external load.
Data Sheet
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 22
Standard Pads Class_A1
Parameter
Symbol
Min.
Values
Max.
500
Unit Note /
Test Condition
Input leakage current
Input high voltage
Input low voltage
I
OZA1 CC -500
nA
V
0 V VIN VDDP
V
V
IHA1 SR 0.6 VDDP
V
DDP + 0.3
max. 3.6 V
ILA1 SR -0.3
0.36 VDDP
V
Output high voltage,
POD1) = weak
VOHA1
CC
V
DDP - 0.4
V
IOH -400 A
IOH -500 A
IOH -1.4 mA
IOH -2 mA
2.4
V
Output high voltage,
POD1) = medium
V
DDP - 0.4
V
2.4
V
Output low voltage
Fall time
VOLA1
CC
0.4
V
IOL 500 A;
POD1) = weak
0.4
150
50
V
IOL 2 mA;
POD1) = medium
t
t
FA1 CC
ns
ns
ns
ns
CL = 20 pF;
POD1) = weak
CL = 50 pF;
POD1) = medium
Rise time
RA1 CC
150
50
CL = 20 pF;
POD1) = weak
CL = 50 pF;
POD1) = medium
1) POD = Pin Out Driver
Table 23
Standard Pads Class_A1+
Parameter
Symbol
Min.
Values
Unit Note /
Test Condition
Max.
Input leakage current
Input high voltage
Input low voltage
I
OZA1+ CC -1
1
A
V
0 V VIN VDDP
V
V
IHA1+ SR 0.6 VDDP
V
DDP + 0.3
max. 3.6 V
ILA1+ SR -0.3
0.36 VDDP
V
Data Sheet
38
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 23
Standard Pads Class_A1+
Parameter
Symbol
Min.
Values
Max.
Unit Note /
Test Condition
Output high voltage, VOHA1+
V
DDP - 0.4
V
V
V
V
V
V
V
IOH -400 A
IOH -500 A
IOH -1.4 mA
IOH -2 mA
POD1) = weak
CC
2.4
Output high voltage,
POD1) = medium
V
DDP - 0.4
2.4
Output high voltage,
POD1) = strong
V
DDP - 0.4
IOH -1.4 mA
IOH -2 mA
2.4
Output low voltage
VOLA1+
0.4
IOL 500 A;
CC
POD1) = weak
0.4
0.4
150
50
V
IOL 2 mA;
POD1) = medium
V
IOL 2 mA;
POD1) = strong
Fall time
t
FA1+ CC
ns
ns
ns
CL = 20 pF;
POD1) = weak
CL = 50 pF;
POD1) = medium
28
CL = 50 pF;
POD1) = strong;
edge = slow
16
ns
CL = 50 pF;
POD1) = strong;
edge = soft;
Rise time
t
RA1+ CC
150
50
ns
ns
ns
CL = 20 pF;
POD1) = weak
CL = 50 pF;
POD1) = medium
28
CL = 50 pF;
POD1) = strong;
edge = slow
16
ns
CL = 50 pF;
POD1) = strong;
edge = soft
1) POD = Pin Out Driver
Data Sheet
39
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 24
HIB_IO Class_A1 special Pads
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Max.
Input leakage current
Input high voltage
Input low voltage
IOZHIB
CC
-500
500
nA
V
0 V VIN VBAT
VIHHIB
SR
0.6 VBAT
V
BAT + 0.3
max. 3.6 V
VILHIB
-0.3
0.36 VBAT
V
SR
Input Hysteresis for
HIB_IO pins1)
HYSHIB 0.1 VBAT
V
V
VBAT 3.13 V
VBAT 3.13 V
CC
0.06
VBAT
Output high voltage,
POD1) = medium
VOHHIB
CC
V
BAT - 0.4
V
IOH -1.4 mA
IOL 2 mA
Output low voltage
VOLHIB
CC
0.4
50
V
Fall time
t
t
FHIB CC
ns
ns
ns
ns
VBAT 3.13 V
CL = 50 pF
100
50
VBAT 3.13 V
CL = 50 pF
Rise time
RHIB CC
VBAT 3.13 V
CL = 50 pF
100
VBAT 3.13 V
CL = 50 pF
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet
40
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.2.2
Analog to Digital Converters (ADCx)
Table 25
ADC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
Analog reference voltage VAREF
V
VAREF = VDDA
SR
shared analog
supply and
reference input
pin
Alternate reference
voltage5)
VAREF
SR
VAGND
+ 1
VDDA
V
V
0.051)
Analog reference ground VAGND
VAGND = VSSA
SR
shared analog
supply and
reference input
pin
Alternate reference
voltage range2)5)
VAREF
VAGND
SR
-
1
VDDA
0.1
V
Analog input voltage
V
AIN SR VAGND
VDDA
V
Input leakage at analog
inputs3)
I
OZ1 CC -100
200
nA
0.03 VDDA
VAIN 0.97 VDDA
-500
100
500
nA
nA
0 V VAIN 0.03
VDDA
-100
0.97 VDDA
VAIN VDDA
Internal ADC clock
f
ADCI CC
2
30
MHz VDDA = 3.3 V
Switched capacitance at CAINSW
4
6.5
pF
the analog voltage inputs4) CC
Total capacitance of an
analog input
CAINTOT
CC
12
15
20
30
pF
pF
Switched capacitance at CAREFSW
the alternate reference
CC
voltage input5)6)
Data Sheet
41
V1.5, 2023-04
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 25
ADC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
Total capacitance of the
alternate reference
inputs5)
CAREFTOT
CC
20
40
pF
Total Unadjusted Error
TUE CC -6
6
LSB 12-bit resolution;
V
V
DDA = 3.3 V;
AREF = VDDA
Differential Non-Linearity EADNL
-4.5
4.5
LSB
7)
Error8)
CC
Gain Error8)
EAGAIN
-6
6
LSB
CC
Integral Non-Linearity8)
Offset Error8)
EAINLCC -4.5
4.5
6
LSB
LSB
EAOFF
-6
CC
RMS Noise9)
ENRMS
1
210)11) LSB
CC
Worst case ADC VDDA
power supply current per CC
active converter
IDDAA
1.5
2
mA during conversion
VDDP = 3.6 V,
TJ = 150 oC
Charge consumption on
alternate reference per
conversion5)
QCONV
CC
30
pC
0 V VAREF
VDDA
12)
ON resistance of the
analog input path
R
AIN CC
600 1 200 Ohm
550 900 Ohm
ON resistance for the ADC RAIN7T
test (pull down for AIN7) CC
180
1) A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).
2) If the analog reference voltage is below VDDA, then the ADC converter errors increase. If the reference voltage
is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k.
3) The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step function (see Figure 14).
4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements, the voltage measured at AINx can deviate from VAREF/2.
5) Applies to AINx, when used as alternate reference input.
6) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead, smaller capacitances are successively switched to the reference voltage.
7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16.
Never less than ±1 LSB.
Data Sheet
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XMC4000 Family
Electrical Parameters
8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.
9) This parameter is valid for soldered devices and requires careful analog board design.
10) Resulting worst case combined error is arithmetic combination of TUE and ENRMS.
11) Value is defined for one sigma Gauss distribution.
12) The resulting current for a conversion can be calculated with IAREF = QCONV / tc.
The fastest 12-bit post-calibrated conversion of tc = 566 ns results in a typical average current of
I
AREF = 53 μA.
Figure 12
VADC Reference Voltage Range
Data Sheet
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Electrical Parameters
The power-up calibration of the ADC requires a maximum number of 4 352 fADCI cycles.
Figure 13
ADCx Input Circuits
Figure 14
ADCx Analog Input Leakage Current
Data Sheet
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XMC4000 Family
Electrical Parameters
Conversion Time
Table 26
Conversion Time (Operating Conditions apply)
Parameter
Symbol Values
Unit Note
Conversion
time
tC CC 2 TADC
+
s
N = 8, 10, 12 for
N-bit conversion
(2 + N + STC + PC +DM) TADCI
T
T
ADC = 1 / fPERIPH
ADCI = 1 / fADCI
•
•
•
STC defines additional clock cycles to extend the sample time
PC adds two cycles if post-calibration is enabled
DM adds one cycle for an extended conversion time of the MSB
Conversion Time Examples
System assumptions (max. fADC):
fADC = 80 MHz i.e. tADC = 12.5 ns, DIVA = 2, fADCI = 26.7 MHz i.e. tADCI = 37.5 ns
According to the given formulas the following minimum conversion times can be
achieved (STC = 0, DM = 0):
12-bit post-calibrated conversion (PC = 2):
t
CN12C = (2 + 12 + 2) tADCI + 2 tADC = 16 37.5 ns + 2 12.5 ns = 625 ns
12-bit uncalibrated conversion:
CN12 = (2 + 12) tADCI + 2 tADC = 14 37.5 ns + 2 12.5 ns = 550 ns
10-bit uncalibrated conversion:
CN10 = (2 + 10) tADCI + 2 tADC = 12 37.5 ns + 2 12.5 ns = 475 ns
8-bit uncalibrated:
CN8 = (2 + 8) tADCI + 2 tADC = 10 37.5 ns + 2 12.5 ns = 400 ns
t
t
t
System assumptions (max. fADCI):
ADC = 60 MHz i.e. tADC = 16.67 ns, DIVA = 1, fADCI = 30 MHz i.e. tADCI = 33.33 ns
12-bit post-calibrated conversion (PC = 2):
CN12C = (2 + 12 + 2) tADCI + 2 tADC = 16 33.33 ns + 2 16.67 ns = 566 ns
f
t
Data Sheet
45
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.2.3
Digital to Analog Converters (DACx)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 27
DAC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ. Max.
RMS supply current IDD
CC
2.5
4
mA
per active DAC
channel,
without load
currents of DAC
outputs
Resolution
RES
CC
12
Bit
Update rate
fURATE_ACC
2
Msam data rate, where
ple/s DAC can follow
64 LSB code jumps
to ± 1LSB accuracy
Update rate
Settling time
Slew rate
f
URATE_F CC
5
2
Msam data rate, where
ple/s DAC can follow
64 LSB code jumps
to ± 4 LSB accuracy
tSETTLE CC
1
s
at full scale jump,
output voltage
reaches target
value ± 20 LSB
SR
CC
2
5
V/s
Minimum output
voltage
VOUT_MIN
CC
0.3
V
code value
unsigned: 000H;
signed: 800H
Maximum output
voltage
VOUT_MAX
CC
2.5
V
code value
unsigned: FFFH;
signed: 7FFH
Integral non-
linearity1)
INL
CC -5.5
±2.5 5.5
±1
LSB
LSB
RL 5 kOhm,
CL 50 pF
Differential non-
linearity
DNL CC -2
2
RL 5 kOhm,
CL 50 pF
Data Sheet
46
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 27
DAC Parameters (Operating Conditions apply) (cont’d)
Parameter
Symbol
Values
Typ. Max.
±20
Unit
Note /
Test Condition
Min.
Offset error
Gain error
EDOFF CC
mV
%
EDG_IN CC -5
0
5
Startup time
tSTARTUP CC
15
30
s
time from output
enabling till code
valid ±16 LSB
3dB Bandwidth of
Output Buffer
fC1
CC 2.5
5
MHz verified by design
Output sourcing
current
IOUT_SOURCE
CC
-30
0.6
mA
mA
Output sinking
current
IOUT_SINK
CC
Output resistance
Load resistance
Load capacitance
ROUT CC
5
50
Ohm
kOhm
pF
RL
CL
SR
SR
50
Signal-to-Noise
Ratio
SNR CC
THD CC
PSRR CC
70
dB
dB
dB
examination
bandwidth < 25 kHz
Total Harmonic
Distortion
70
56
examination
bandwidth < 25 kHz
Power Supply
Rejection Ratio
to VDDA
verified by design
1) According to best straight line method.
Conversion Calculation
Unsigned:
DACxDATA = 4095 (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN
)
Signed:
DACxDATA = 4095 (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
Data Sheet
47
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Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 15
DAC Conversion Examples
Data Sheet
48
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Electrical Parameters
3.2.4
Out-of-Range Comparator (ORC)
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service
request trigger (GxORCOUTy).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The parameters in Table 28 apply for the maximum reference voltage
V
AREF = VDDA + 50 mV.
Table 28
ORC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
DC Switching Level VODC CC 100
Typ. Max.
125
200
mV Ax-marking devices
VAIN VAREF + VODC
Hysteresis
VOHYS CC 50
VODC mV
Detection Delay of a tODD CC 55
450
ns
Ax-marking devices
persistent
VAIN VAREF + 200 mV
Overvoltage
45
105
ns
ns
VAIN VAREF + 400 mV
Always detected
tOPDD CC 440
Ax-marking devices
Overvoltage Pulse
VAIN VAREF + 200 mV
90
ns
ns
VAIN VAREF + 400 mV
Never detected
tOPDN CC
49
Ax-marking devices
Overvoltage Pulse
VAIN VAREF + 200 mV
30
ns
ns
ns
VAIN VAREF + 400 mV
VAIN VAREF
Release Delay
Enable Delay
tORD CC 65
tOED CC
105
200
100
1) Always the standard VADC reference, alternate references do not apply to the ORC.
Data Sheet
49
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XMC4100 / XMC4200
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Electrical Parameters
Figure 16
GxORCOUTy Trigger Generation
Figure 17
ORC Detection Ranges
Data Sheet
50
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Electrical Parameters
3.2.5
High Resolution PWM (HRPWM)
The following chapters describe the operating conditions, characteristics and timing
requirements, for all the components inside the HRPWM module. Each description is
given for just one sub unit, e.g., one CSG or one HRC.
All the timing information is related to the module clock, fhrpwm
.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.2.5.1 HRC characteristics
Table 29 summarizes the characteristics of the HRC units.
Table 29
HRC characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Min.
Max.
High resolution step
size1)2)
tHRS CC –
150
–
ps
Startup time (after reset
release)
tstart CC –
–
2
s
1) The step size for clock frequencies equal to 180, 120 and 80 MHz is 150 ps.
2) The step size for clock frequencies different from 180, 120 and 80 MHz but within the range from 180 to 64
MHz can be between 118 to 180 ps (fixed over process and operating conditions)
3.2.5.2 CMP and 10-bit DAC characteristics
The Table 30 summarizes the characteristics of the CSG unit.
The specified characteristics require that the setup of the HRPWM follows the
initialization sequence as documented in the Reference Manual.
Table 30
CMP and 10-bit DAC characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
10
Unit Note /
Test Condition
Min.
Max.
DAC Resolution
RES
bits
CC
DAC differential
nonlinearity
DNL
CC
-1
–
–
1.5
3
LSB Monotonic
behavior
See Figure 18
DAC integral nonlinearity INL CC -3
LSB See Figure 18
Data Sheet
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XMC4000 Family
Electrical Parameters
Table 30
CMP and 10-bit DAC characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Min.
Max.
CSG Output Jitter
DCSG
–
1
clk
CC
Bias startup time
tstart CC –
–
–
98
us
Bias supply current
IDDbias
–
400
A
CC
CSGy startup time
Input operation current1)
High Speed Mode
tCSGS
CC
–
–
–
2
s
IDDCIN
CC
-10
33
A
See Figure 19
DAC output voltage range VDOUT
VSS
–
–
–
–
VDDP
80
V
CC
DAC propagation delay - tFShs
ns
ns
See Figure 20
See Figure 20
Full scale
CC
InputSelectorpropagation tDhs CC
–
100
delay - Full scale
Comparator bandwidth
DAC CLK frequency
Supply current
tDhs CC 20
–
–
–
–
ns
fclk SR
–
–
30
940
MHz
A
IDDhs
CC
Low Speed Mode
DAC output voltage range VDOUT
0.1
VDDP
–
–
–
VDDP
160
200
V
2)
CC
DAC propagation delay - tFSls CC –
Full Scale
ns
ns
See Figure 20
See Figure 20
InputSelectorpropagation tDls CC
–
delay - Full Scale
Comparator bandwidth
DAC CLK frequency
Supply current
tDls CC 20
–
–
–
–
ns
fclk SR
–
–
30
300
MHz
A
IDDls
CC
1) Typical input resistance RCIN = 100kOhm.
2) The INL error increases for DAC output voltages below this limit.
Data Sheet
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Electrical Parameters
Figure 18
CSG DAC INL and DNL example
Figure 19
Input operation current
Data Sheet
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Electrical Parameters
Figure 20
DAC and Input Selector Propagation Delay
3.2.5.3 Clocks
HRPWM DAC Conversion Clock
The DAC conversion clock can be generated internally or it can be controlled via a
HRPWM module pin.
Table 31
External DAC conversion trigger operating conditions
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Con
dition
Min.
Frequency
ON time
fetrg SR
–
–
–
–
302)
–
MHz
ns
1)2)
1)2)
tonetrg SR 2Tccu
toffetrg SR 2Tccu
OFF time
–
ns
1) 50% duty cycle is not obligatory
2) Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)
CSG External Clock
It is possible to select an external source, that can be used as a clock for the slope
generation, HRPWMx.ECLKy. This clock is synchronized internally with the module
clock and therefore the external clock needs to meet the criterion described on Table 32.
Data Sheet
54
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 32
External clock operating conditions
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Con
Min.
dition
Frequency
ON time
feclk SR
–
–
–
–
fhrpwm/4 MHz
1)2)
1)2)
toneclk SR 2Tccu
toffeclk SR 2Tccu
–
–
ns
ns
OFF time
Only the
rising
edge is
used
1) 50% duty cycle is not obligatory
2) Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)
3.2.6
Low Power Analog Comparator (LPAC)
The Low Power Analog Comparator (LPAC) triggers a wake-up event from Hibernate
state or an interrupt trigger during normal operation. It does so by comparing VBAT or
another external sensor voltage VLPS with a pre-programmed threshold voltage.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 33
Low Power Analog Comparator Parameters
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
V
BAT supply voltage range for VBAT SR 2.1
3.6
V
V
LPAC operation
Sensor voltage range
VLPCS
0
1.2
CC
Threshold step size
Threshold trigger accuracy
Conversion time
Vth CC
Vth CC
18.75
mV
%
±10
for Vth > 0.4 V
tLPCC CC
250
15
s
Average current consumption ILPCAC
over time
A conversion
CC
interval 10 ms1)
1)
Current consumption during
conversion
I
LPCC CC
150
A
1) Single channel conversion, measuring VBAT = 3.3 V, 8 cycles settling time
Data Sheet
55
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Electrical Parameters
3.2.7
Die Temperature Sensor
The Die Temperature Sensor (DTS) measures the junction temperature TJ.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 34
Die Temperature Sensor Parameters
Symbol Values
Min. Typ. Max.
Parameter
Unit Note /
Test Condition
Temperature sensor range
TSR SR -40
TLE CC
150
°C
°C
Linearity Error
(to the below defined formula)
±1
per TJ 30 °C
Offset Error
TOE CC
±6
°C TOE = TJ - TDTS
VDDP 3.3 V1)
Measurement time
tM
CC
100
10
s
s
Start-up time after reset
inactive
tTSST SR
1) At VDDP_max = 3.63 V the typical offset error increases by an additional TOE = ±1 °C.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [°C]
This formula and the values defined in Table 34 apply with the following calibration
values:
•
•
DTSCON.BGTRIM = 8H
DTSCON.REFTRIM = 4H
Data Sheet
56
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Electrical Parameters
3.2.8
USB Device Interface DC Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification.
High-Speed Mode is not supported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 35
USB Device Data Line (USB_DP, USB_DM) Parameters (Operating
Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
Input low voltage
VIL SR
0.8
V
V
Input high voltage
(driven)
VIH SR 2.0
VIHZ SR 2.7
VDIS CC 0.2
VCM CC 0.8
VOL CC 0.0
VOH CC 2.8
Input high voltage
(floating) 1)
3.6
V
Differential input
sensitivity
V
Differential common
mode range
2.5
V
Output low voltage
0.3
V
1.5 kOhm pull-
up to 3.6 V
Output high voltage
3.6
V
15 kOhm pull-
down to 0 V
DP pull-up resistor (idle RPUI CC 900
bus)
1 575
3 090
Ohm
Ohm
DP pull-up resistor
(upstream port
receiving)
RPUA CC 1 425
ZINP CC 300
Input impedance DP,
DM
kOhm 0 V VIN VDDP
Driver output resistance ZDRV CC 28
44
Ohm
DP, DM
1) Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at B-
connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.
Data Sheet
57
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XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.2.9
Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The oscillator pins can be operated with an external crystal (see Figure 21) or in direct
input mode (see Figure 22).
Figure 21
Oscillator in Crystal Mode
Data Sheet
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Electrical Parameters
Figure 22
Oscillator in Direct Input Mode
Data Sheet
59
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XMC4100 / XMC4200
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Electrical Parameters
Table 36
OSC_XTAL Parameters
Parameter
Symbol
Min.
Values
Typ.
Unit Note /
Test Condition
Max.
Input frequency
f
OSC SR
4
4
40
MHz Direct Input Mode
selected
25
10
MHz External Crystal
Mode selected
Oscillator start-up
time1)2)
tOSCS
ms
CC
Input voltage at XTAL1 VIX SR -0.5
VDDP
0.5
+
+
+
V
Input amplitude (peak-
to-peak) at XTAL12)3)
V
V
V
PPX SR 0.4
VDDP
1.0
V
VDDP
Input high voltage at
XTAL14)
IHBXSR 1.0
ILBX SR -0.5
VDDP
0.5
V
Input low voltage at
XTAL14)
0.4
V
Input leakage current at IILX1 CC -100
XTAL1
100
nA
Oscillator power
down
0 V VIX VDDP
1)
tOSCS is defined from the moment the oscillator is enabled wih SCU_OSCHPCTRL.MODE until the oscillations
reach an amplitude at XTAL1 of 0.4 * VDDP
.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) If the shaper unit is enabled and not bypassed.
4) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
Data Sheet
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Electrical Parameters
Table 37
RTC_XTAL Parameters
Symbol
Parameter
Values
Typ.
Unit Note /
Test Condition
Min.
fOSC SR
Max.
Input frequency
32.768
kHz
s
Oscillator start-up
time1)2)3)
tOSCS
5
CC
Input voltage at
RTC_XTAL1
VIX SR -0.3
VBAT
0.3
+
+
V
V
Input amplitude (peak-
to-peak) at
V
PPX SR 0.4
RTC_XTAL12)4)
Input high voltage at
RTC_XTAL15)
V
V
IHBXSR 0.6
VBAT
0.3
V
V
VBAT
Input low voltage at
RTC_XTAL15)
ILBX SR -0.3
0.36
VBAT
Input Hysteresis for
RTC_XTAL13)6)
VHYSX
CC
0.1
VBAT
V
3.0 V
V
BAT < 3.6 V
0.03
V
V
BAT < 3.0 V
VBAT
Input leakage current at IILX1 CC -100
RTC_XTAL1
100
nA
Oscillator power
down
0 V VIX VBAT
1)
tOSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the
oscillations reach an amplitude at RTC_XTAL1 of 400 mV.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) For a reliable start of the oscillation in crystal mode it is required that VBAT 3.0 V. A running oscillation is
maintained across the full VBAT voltage range.
4) If the shaper unit is enabled and not bypassed.
5) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
6) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet
61
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.2.10
Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
If not stated otherwise, the operating conditions for the parameters in the following table
are:
V
DDP = 3.3 V, TA = 25 oC
Table 38
Power Supply Parameters
Symbol
Parameter
Values
Min. Typ. Max.
Unit
Note /
Test Condition
Active supply current1)
Peripherals enabled
Frequency:
IDDPA CC
80
75
73
59
50
24
19
mA
80 / 80 / 80
80 / 40 / 40
40 / 40 / 80
24 / 24 / 24
1 / 1 / 1
fCPU / fPERIPH / fCCU in MHz
IDDPA CC
Active supply current
Code execution from RAM
Flash in Sleep mode
Frequency:
mA
mA
80 / 80 / 80
80 / 40 / 40
fCPU / fPERIPH / fCCU in MHz
Active supply current2)
Peripherals disabled
Frequency:
IDDPA CC
63
62
60
54
50
80 / 80 / 80
80 / 40 / 40
40 / 40 / 80
24 / 24 / 24
1 / 1 / 1
fCPU / fPERIPH in MHz
Data Sheet
62
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 38
Power Supply Parameters
Symbol
Parameter
Values
Min. Typ. Max.
Unit
Note /
Test Condition
Sleep supply current3)
Peripherals enabled
Frequency:
IDDPS CC
76
73
70
56
47
46
59
58
57
51
46
46
6.9
4.3
3.8
mA
80 / 80 / 80
80 / 40 / 40
40 / 40 / 80
24 / 24 / 24
1 / 1 / 1
fCPU / fPERIPH / fCCU in MHz
fCPU / fPERIPH / fCCU in kHz
100 / 100 / 100
80 / 80 / 80
80 / 40 / 40
40 / 40 / 80
24 / 24 / 24
1 / 1 / 1
Sleep supply current4)
Peripherals disabled
Frequency:
IDDPS CC
mA
mA
fCPU / fPERIPH / fCCU in MHz
fCPU / fPERIPH / fCCU in kHz
100 / 100 / 100
24 / 24 / 24
4 / 4 / 4
Deep Sleep supply
current5)
Flash in Sleep mode
Frequency:
IDDPD CC
1 / 1 / 1
fCPU / fPERIPH / fCCU in MHz
fCPU / fPERIPH / fCCU in kHz
4.5
100 / 100 / 100
6)
Hibernate supply current
RTC on7)
IDDPH CC
10.8
8.0
6.8
10.3
7.5
6.3
A
A
V
V
V
V
V
V
BAT = 3.3 V
BAT = 2.4 V
BAT = 2.0 V
BAT = 3.3 V
BAT = 2.4 V
BAT = 2.0 V
Hibernate supply current
RTC off8)
IDDPH CC
Worst case active supply
current9)
IDDPA CC
140 mA
VDDP = 3.6 V,
TJ = 150 oC
10)
V
DDA power supply current IDDA CC
DDP current at PORST Low IDDP_PORST
CC
11)
mA
mA
I
24
VDDP = 3.6 V,
TJ = 150 oC
Data Sheet
63
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 38
Power Supply Parameters
Symbol
Parameter
Values
Min. Typ. Max.
Unit
Note /
Test Condition
Power Dissipation
PDISS CC
6
1
W
VDDP = 3.6 V,
TJ = 150 oC
Wake-uptimefromSleepto tSSA CC
Active mode
cycles
ms
Wake-up time from Deep
Sleep to Active mode
Defined by the
wake-up of the
Flash module,
see
Section 3.2.11
Wake-up time from
Hibernate mode
ms
Wake-up via
power-on reset
event, see
Section 3.3.2
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash. USB and CCU clock off.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU 1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) Test Power Loop: fSYS = 80 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer mode,
all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in 500kHz
internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE, DTS
measurements and FPU calculations.
The power consumption of each customer application will most probably be lower than this value, but must be
evaluated separately.
10) IDDP decreases typically by 3.5 mA when fSYS decreases by 10 MHz, at constant TJ
11) Sum of currents of all active converters (ADC and DAC)
Data Sheet
64
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Peripheral Idle Currents
Test conditions:
•
•
•
f
V
sys and derived clocks at 80 MHz
DDP = 3.3 V, Ta =25 °C
all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit
of the SCU)
•
the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control
Unit of the SCU
•
•
no I/O activity
the given values are a result of differential measurements with asserted and
deasserted peripheral reset and enabled clock of the peripheral under test
The tested peripheral is left in the state after the peripheral reset is deasserted, no further
initialisation or configuration is done. E.g. no timer is running in the CCUs, no
communication active in the USICs, etc.
Table 39
Peripheral Idle Currents
Parameter
Symbol
Min.
Values
Typ.
Unit
Note /
Test Condition
Max.
PORTS
USB
I
PER CC
0.3
mA
FCE
WDT
POSIFx1)
MultiCAN
ERU
1.0
LEDTSCU0
CCU4x1)
CCU8x1)
DAC (digital)2)
1.3
3.0
4.5
6.0
USICx
VADC (digital)2)
DMAx
1) Enabling the fCCU clock for the POSIFx/CCU4x/CCU8x modules adds approximately IPER = 1.8 mA,
disregarding which and how many of those peripherals are enabled.
2) The current consumption of the analog components are given in the dedicated Data Sheet sections of the
respective peripheral.
Data Sheet
65
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.2.11
Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 40
Flash Memory Parameters
Parameter
Symbol
Min.
Values
Typ.
5
Unit
Note /
Test Condition
Max.
Erase Time per 256
Kbyte Sector
tERP CC
5.5
s
s
s
Erase Time per 64 Kbyte tERP CC
Sector
1.2
0.3
1.4
0.4
Erase Time per 16 Kbyte tERP CC
Logical Sector
Program time per page1)
t
PRP CC
5.5
11
15
ms
ms
Erase suspend delay
tFL_ErSusp
CC
Wait time after margin
change
tFL_Margin 10
Del CC
s
Wake-up time
t
WU CC
270
s
Read access time
ta CC
20
ns
For operation
with 1 / fCPU < ta
waitstatesmust
be configured2)
Data Retention Time,
Physical Sector3)4)
t
RET CC 20
RETL CC 20
years Max. 1000
erase/program
cycles
Data Retention Time,
Logical Sector3)4)
t
years Max. 100
erase/program
cycles
Data Sheet
66
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 40
Flash Memory Parameters
Parameter
Symbol
Min.
Values
Unit Note /
Test Condition
Typ. Max.
Data Retention Time,
UserConfigurationBlock
(UCB)3)4)
tRTU CC 20
years Max. 4
erase/program
cycles per UCB
Endurance on 64 Kbyte NEPS4
Physical Sector PS4 CC
10000
cycles BA-marking
devices only!
Cycling
distributed over
life time5)
1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes an additional time of 5.5 ms.
2) The following formula applies to the wait state configuration: FCON.WSPFLASH (1 / fCPU) ta.
3) Storage and inactive time included.
4) Values given are valid for an average weighted junction temperature of TJ = 110°C.
5) Only valid with robust EEPROM emulation algorithm, equally cycling the logical sectors. For more details see
the Reference Manual.
Data Sheet
67
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3
AC Parameters
3.3.1
Testing Waveforms
Figure 23
Rise/Fall Time Parameters
Figure 24
Testing Waveform, Output Delay
Figure 25
Testing Waveform, Output High Impedance
Data Sheet
68
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.2
Power-Up and Supply Monitoring
PORST is always asserted when VDDP and/or VDDC violate the respective thresholds.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 26
PORST Circuit
Table 41
Supply Monitoring Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min. Typ. Max.
3)
Digital supply voltage reset VPOR CC 2.791)
threshold
3.052)
1.17
V
V
V
Core supply voltage reset VPV CC
threshold
V
DDP voltage to ensure
VDDPPA
1.0
defined pad states
CC
PORST rise time
tPR SR
2
s
Startup time from power-on tSSW CC
reset with code execution
from Flash
2.5
3.5
ms
Time to the first
user code
instruction
V
DDC ramp up time
tVCR CC
550
s
Ramp up after
power-on or
after a reset
triggered by a
violation of
V
POR or VPV
1) Minimum threshold for reset assertion.
Data Sheet
69
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
2) Maximum threshold for reset deassertion.
3) The VDDP monitoring has a typical hysteresis of VPORHYS = 180 mV.
Figure 27
3.3.3
Power-Up Behavior
Power Sequencing
While starting up and shutting down as well as when switching power modes of the
system it is important to limit the current load steps. A typical cause for such load steps
is changing the CPU frequency fCPU. Load steps exceeding the below defined values
may cause a power on reset triggered by the supply monitor.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Data Sheet
70
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 42
Power Sequencing Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min. Typ. Max.
Positive Load Step Current IPLS SR
-
-
-
50
mA Load increase
on VDDP
t 10 ns
Negative Load Step
Current
INLS SR
VLS CC
150
±100
mA Load decrease
on VDDP
t 10 ns
V
DDC Voltage Over-
mV For maximum
positive or
/ Undershoot from Load
Step
negative load
step
Positive Load Step Settling tPLSS SR 50
Time
-
s
s
Negative Load Step
Settling Time
tNLSS SR 100
-
External Buffer Capacitor CEXT SR
3
4.7
6
F
In addition
on VDDC
C = 100 nF
capacitor on
each VDDC pin
Positive Load Step Examples
System assumptions:
fCPU = fSYS, target frequency fCPU = 80 MHz, main PLL fVCO = 480 MHz, stepping done by
K2 divider, tPLSS between individual steps:
24 MHz - 48 MHz - 80 MHz (K2 steps 20 - 10 - 6)
24 MHz - 60 MHz - 80 MHz (K2 steps 20 - 8 - 6)
Data Sheet
71
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.4
Phase Locked Loop (PLL) Characteristics
Main and USB PLL
Table 43
PLL Parameters
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Min.
Max.
Accumulated Jitter
Duty Cycle1)
DP CC
±5
ns
%
accumulated
over 300 cycles
fSYS = 80 MHz
D
DC CC 46
50
54
Low pulse to
total period,
assuming an
idealinputclock
source
PLL base frequency
fPLLBASE 30
140
MHz
CC
VCO input frequency
VCO frequency range
PLL lock-in time
f
REF CC
4
16
MHz
MHz
s
fVCO CC 260
520
400
tL CC
1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.
Data Sheet
72
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.5
Internal Clock Source Characteristics
Fast Internal Clock Source
Table 44
Fast Internal Clock Parameters
Parameter
Symbol
Values
Typ.
36.5
24
Unit Note /
Test Condition
Min.
Max.
Nominal frequency
Accuracy
fOFINC
CC
MHz not calibrated
MHz calibrated
fOFI
CC
-0.5
0.5
%
automatic
calibration1)2)
-15
15
%
factory
calibration,
V
DDP = 3.3 V
no calibration,
DDP = 3.3 V
-25
-7
25
7
%
%
V
Variation over
voltage range3)
3.13 V VDDP
3.63 V
Start-up time
tOFIS CC
50
s
1) Error in addition to the accuracy of the reference clock.
2) Automatic calibration compensates variations of the temperature and in the VDDP supply voltage.
3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory
calibrated oscillator frequency.
Data Sheet
73
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Slow Internal Clock Source
Table 45
Slow Internal Clock Parameters
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Min.
Max.
Nominal frequency
Accuracy
fOSI CC
32.768
kHz
fOSI
CC
-4
4
%
VBAT = const.
0 °C TA
85 °C
-5
5
%
VBAT = const.
TA 0 °C or
TA 85 °C
-5
5
%
%
2.4 V VBAT
TA = 25 °C
,
-10
10
1.95 V
V
BAT < 2.4 V,
TA = 25 °C
Start-up time
tOSIS CC
50
s
Data Sheet
74
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.6
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Table 46
JTAG Interface Timing Parameters
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
Typ.
Max.
TCK clock period
TCK clock period
t1 SR 30
–
–
ns
ns
For CL = 20 pF
on TDO
t1 SR 40
–
–
For CL = 50 pF
on TDO
TCK high time
t2 SR 10
t3 SR 10
–
–
–
–
–
–
–
4
4
–
ns
ns
ns
ns
ns
TCK low time
TCK clock rise time
TCK clock fall time
t4 SR
t5 SR
t6 SR
–
–
6
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
t7 SR
6
–
–
ns
after TCK rising edge
TDO valid after TCK falling t8 CC
–
3
2
–
–
–
17
–
ns
ns
ns
CL = 50 pF
CL = 20 pF
edge1) (propagation delay)
TDO hold after TCK falling t18 CC
–
edge1)
TDO high imped. to valid t9 CC
–
–
–
–
14
ns
ns
CL = 50 pF
CL = 50 pF
from TCK falling edge1)2)
TDO valid to high imped. t10 CC
13.5
from TCK falling edge1)
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
75
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 28
Test Clock Timing (TCK)
Figure 29
JTAG Timing
Data Sheet
76
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.7
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Table 47
SWD Interface Timing Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
SWDCLK clock period
tSC SR 25
40
–
–
–
–
–
–
–
ns
ns
CL = 30 pF
CL = 50 pF
SWDCLK high time
SWDCLK low time
t1 SR 10
t2 SR 10
500000 ns
500000 ns
SWDIO input setup
t3 SR
6
–
ns
to SWDCLK rising edge
SWDIO input hold
t4 SR
6
–
–
ns
after SWDCLK rising edge
SWDIO output valid time t5 CC
after SWDCLK rising edge
–
–
3
–
–
–
17
13
–
ns
ns
ns
CL = 50 pF
CL = 30 pF
SWDIO output hold time t6 CC
from SWDCLK rising edge
Figure 30
SWD Timing
Data Sheet
77
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.8
Peripheral Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 48
USIC SSC Master Mode Timing
Symbol Values
Typ. Max.
Parameter
Unit Note /
Test Condition
Min.
CLK CC 40
SCLKOUT master clock
period
t
ns
ns
Slave select output SELO t1 CC tSYS
active to first SCLKOUT
-
6.51)
transmit edge
Slave select output SELO t2 CC tSYS
inactive after last
-
ns
8.51)
SCLKOUT receive edge
Data output DOUT[3:0]
valid time
t3 CC -6
t4 SR 23
8
ns
ns
Receive data input
DX0/DX[5:3] setup time to
SCLKOUT receive edge
Data input DX0/DX[5:3]
hold time from SCLKOUT
receive edge
t5 SR
1
ns
1)
tSYS = 1 / fPB
Data Sheet
78
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 49
USIC SSC Slave Mode Timing
Parameter
Symbol
Min.
Values
Unit Note /
Test Condition
Typ. Max.
DX1 slave clock period
tCLK SR 66.6
t10 SR 3
ns
ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
Select input DX2 hold after t11 SR 4
last clock input DX1 receive
edge1)
ns
ns
ns
ns
Receive data input
t12 SR 6
DX0/DX[5:3] setup time to
shift clock receive edge1)
Data input DX0/DX[5:3] hold t13 SR 4
time from clock input DX1
receive edge1)
Data output DOUT[3:0] valid t14 CC 0
24
time
1) These input timing are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
79
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 31
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet
80
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.8.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 50
USIC IIC Standard Mode Timing1)
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
Typ.
Max.
Fall time of both SDA and t1
-
-
300
ns
ns
μs
ns
μs
μs
μs
μs
μs
μs
SCL
CC/SR
Rise time of both SDA and t2
-
-
-
-
-
-
-
-
-
-
1000
SCL
CC/SR
Data hold time
t3
0
-
-
-
-
-
-
-
-
CC/SR
Data set-up time
t4
250
4.7
4.0
4.0
4.7
4.0
4.7
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet
81
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Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Table 51
USIC IIC Fast Mode Timing1)
Parameter
Symbol
Min.
Values
Typ.
-
Unit Note /
Test Condition
Max.
Fall time of both SDA and t1
SCL CC/SR 0.1*Cb
20 +
300
ns
ns
2)
Rise time of both SDA and t2
20 +
-
300
SCL
CC/SR 0.1*Cb
2)
Data hold time
Data set-up time
t3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
μs
ns
μs
μs
μs
μs
μs
μs
CC/SR
t4
100
1.3
0.6
0.6
0.6
0.6
1.3
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
82
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 32
USIC IIC Stand and Fast Mode Timing
3.3.8.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 52
USIC IIS Master Transmitter Timing
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Clock period
t1 CC
t2 CC
33.3
ns
ns
Clock high time
0.35 x
t1min
Clock low time
t3 CC
0.35 x
t1min
ns
Hold time
t4 CC
t5 CC
0
ns
Clock rise time
0.15 x ns
t1min
Data Sheet
83
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
Figure 33
USIC IIS Master Transmitter Timing
USIC IIS Slave Receiver Timing
Table 53
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Clock period
t6 SR
t7 SR
66.6
ns
ns
Clock high time
0.35 x
t6min
Clock low time
Set-up time
Hold time
t8 SR
t9 SR
0.35 x
t6min
ns
ns
ns
0.2 x
t6min
t10 SR
0
Figure 34
USIC IIS Slave Receiver Timing
Data Sheet
84
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Electrical Parameters
3.3.9
USB Interface Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification.
High-Speed Mode is not supported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 54
USB Timing Parameters (operating conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
Rise time
Fall time
tR
tF
CC
CC
4
4
–
–
–
–
20
ns
ns
%
V
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
20
Rise/Fall time matching tR/tF
Crossover voltage VCRS
CC 90
CC 1.3
111.11
2.0
Figure 35
USB Signal Timing
Data Sheet
85
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
4
Package and Reliability
The XMC4[12]00 is a member of the XMC4000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Die Pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1
Package Parameters
Table 55 provides the thermal characteristics of the packages used in XMC4[12]00. The
availability of different packages for different markings is listed in Table 2.
Table 55
Thermal Characteristics of the Packages
Limit Values
Parameter
Symbol
Unit
Package Types
Min. Max.
PG-TQFP-64-19
PG-TQFP-64-21
-
5.7 5.7 mm
5.2 5.2 mm
Exposed Die Pad
Dimensions
Ex Ey
CC
-
-
-
-
PG-VQFN-48-71
PG-TQFP-64-191)
23.4
34.8
K/W
K/W
Thermal resistance
Junction-Ambient
RJA
CC
PG-TQFP-64-211)
PG-VQFN-48-711)
Package thickness
1.0±0.05mm
PG-TQFP-64-19
PG-TQFP-64-21
-
1.2 Max mm
1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
Data Sheet
86
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
4.1.1
Thermal Considerations
When operating the XMC4[12]00 in a system, the total heat generated in the chip must
be dissipated to the ambient environment to prevent overheating and the resulting
thermal damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
T = (PINT + PIOSTAT + PIODYN) RJA
The internal power consumption is defined as
P
INT = VDDP IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
IOSTAT = ((VDDP-VOH) IOH) + (VOL IOL
P
)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
87
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
4.2
Package Outlines
The availability of different packages for different devices types is listed in Table 1,
specific packages for different device markings are listed in Table 2.
+0.07
15 x 0.5 = 7.5
-0.04
H
0.5
0.15
0.6
0.08
64x
C
C
SEATING PLANE COPLANARITY
2)
+0.07
-0.03
0.2
M
0.08 A-B D C 64x
12
10
0.2 A-B D 64x
1)
D
5.7
4.9
0.2 A-B D H 4x
Exposed Diepad
A
B
64
64
1
1
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
PG-TQFP-64-19-PO V02
Figure 36
PG-TQFP-64-19 (Plastic Green Thin Profile Quad Flat Package)
Data Sheet
88
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Package and Reliability
PG-TQFP-64-21
Figure 37
PG-TQFP-64-21 (Plastic Green Thin Profile Quad Flat Package)
11 x 0.5
0.5
= 5.5
7
0.9 MAX.
(0.2)
A
0.1 A
C
2x
B
25
36
24
0.1 C
48x
37
48
0.05 C
COPLANARITY
0.05
5.2
M
0.05
A
B
C
A
13
12
1
Index Marking
0.1 B
Index Marking
C
2x
+0.05
-0.07
48x
0.25
0.05
0.4
M
C
0.1
0.05
B
C
C
0.05 MAX.
STANDOFF
M
PG-VQFN-48-71-PO V02
Figure 38
PG-VQFN-48-71 (Plastic Green Very Thin Profile Flat Non Leaded
Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet
89
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
XMC4100 / XMC4200
XMC4000 Family
Quality Declarations
5
Quality Declarations
The qualification of the XMC4[12]00 is executed according to the JEDEC standard
JESD47H.
Note: For automotive applications refer to the Infineon automotive microcontrollers.
Table 56
Quality Parameters
Symbol
Values
Note /
Test Condition
Parameter
Unit
Min. Typ. Max.
TJ 109°C,
devicepermanent
on
Operation lifetime
tOP CC 20
a
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
EIA/JESD22-
A114-B
2 000
V
SR
ESD susceptibility
according to Charged
Device Model (CDM)
VCDM
SR
Conforming to
JESD22-C101-C
500
3
V
MSL
JEDEC
J-STD-020D
Moisture sensitivity level
CC
Profile according
to JEDEC
J-STD-020D
TSDR
SR
Soldering temperature
260
°C
Data Sheet
90
V1.5, 2023-04
Subject to Agreement on the Use of Product Information
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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