XMC7200-E272K8384AA [INFINEON]
The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores.;
| 型号： | XMC7200-E272K8384AA |
| 厂家： | 
Infineon |
| 描述： | The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores. |
| 文件： | 总189页 (文件大小：2067K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XMC7200
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
General description
XMC7200 is a family of XMC7000 microcontrollers targeted at industrial applications. XMC7200 has two
Arm® Cortex®-M7 CPUs for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and security
processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data
rate (CAN FD) and Gigabit Ethernet. XMC7200 devices are manufactured on an advanced 40-nm process. XMC7200
incorporates Infineon’s low-power flash memory, multiple high-performance analog and digital peripherals, and
enables the creation of a secure computing platform.
Features
• CPU subsystem
- One or two 350-MHz 32-bit Arm® Cortex®-M7 CPUs, each with
• Single-cycle multiply
• Single/double-precision floating point unit (FPU)
• 16-KB data cache, 16-KB instruction cache
• Memory Protection Unit (MPU)
• 16-KB instruction and 16-KB data Tightly-Coupled Memories (TCM)
- 100-MHz 32-bit Arm® Cortex® M0+ CPU with
• Single-cycle multiply
• Memory Protection Unit
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0, DW0) with 143 channels
• Peripheral DMA controller #1 (P-DMA1, DW1) with 65 channels
• Memory DMA controller (M-DMA0, DMAC0) with 8 channels
• Integrated memories
- 8384 KB of code-flash with an additional 256 KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- 1024-KB of SRAM with selectable retention granularity
• Cryptography engine
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve
(ECC)
- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)
• Safety for application
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page1
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detection (BOD)
- Overvoltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)
• Low-power 2.7-V to 5.5-V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup
- Up to two pins to wake from Hibernate mode
- Up to 220 GPIO pins to wake from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clocks
- Internal Main Oscillator (IMO)
- Internal Low-Speed Oscillator (ILO)
- External Crystal Oscillator (ECO)
- Watch Crystal Oscillator (WCO)
- Phase-Locked Loop (PLL)
- Frequency-Locked Loop (FLL)
• Communication interfaces
- Up to 10 CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant to ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to 11 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,
or UART
- Up to two 10/100/1000 Mbps Ethernet MAC interfaces conforming to IEEE-802.3az
• Supports the following PHY interfaces:
Media-independent interface (MII)
Reduced media-independent interface (RMII)
Reduced gigabit media-independent interface (RGMII)
• Compliant with IEEE-802.1BA Audio Video Bridging (AVB)
• Compliant with IEEE-1588 Precision Time Protocol (PTP)
• External memory interface
- One SPI (Single, Dual, Quad, or Octal) or HYPERBUS™ interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
• SDHC interface
- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure
Digital (SD), or SDIO (Secure Digital Input Output)
• Compliant to eMMC 5.1, SD 6.0, and SDIO 4.10 specifications
- Data rates up to SD High Speed 50 MHz, or eMMC 52 MHz DDR
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
• Audio interface
- Three Inter-IC Sound (I2S) Interfaces for connecting digital audio devices
- I2S, left justified, or Time Division Multiplexed (TDM) audio formats
- Independent transmit or receive operation, each in master or slave mode
• Timers
- Up to 102 16-bit and 16 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks
• Up to 15 16-bit counters for motor control
• Up to 87 16-bit counters and 16 32-bit counters for regular operations
• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time
(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,
and so on)
• Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
• I/O
- Up to 220 Programmable I/Os
- Three I/O types
• GPIO Standard (GPIO_STD)
• GPIO Enhanced (GPIO_ENH)
• High-Speed I/O Standard (HSIO_STD)
• Regulators
- Generates a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Three regulators:
• DeepSleep
• Core internal
• Core external
• Programmable analog
- Three SAR A/D converters with up to 99 external channels (96 I/Os + 3 I/Os for motor control)
• Each ADC supports 32 logical channels, with 32 + 1 physical connections. Any external channel can be
connected to any logical channel in the respective SAR.
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports six internal analog inputs like
• Bandgap reference to establish absolute voltage levels
• Calibrated diode for junction temperature calculations
• Two AMUXBUS inputs and two direct connections to monitor supply levels
- Each ADC supports addressing of external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
• Smart I/O
- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36 I/Os (GPIO_STD) supported
• Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (Serial Wire Debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
• Data trace using SWD
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
• Instruction and data trace using JTAG
• Industry advanced development tools
- Infineon IDE ModusToolbox™ software for code development and debugging
• Packages
- 176-TEQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch
- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Table of contents
Table of contents
General description .......................................................................................................................... 1
Features .......................................................................................................................................... 1
Table of contents.............................................................................................................................. 5
1 Features list .................................................................................................................................. 7
1.1 Communication peripheral instance list .............................................................................................................. 9
2 Blocks and functionality................................................................................................................10
Block diagram.................................................................................................................................10
3 Functional description ..................................................................................................................11
3.1 CPU subsystem .................................................................................................................................................... 11
3.1.1 CPU.................................................................................................................................................... 11
3.1.2 DMA controllers.................................................................................................................................. 11
3.1.3 Flash................................................................................................................................................... 11
3.1.4 SRAM................................................................................................................................................. 11
3.1.5 ROM................................................................................................................................................... 11
3.1.6 Cryptography accelerator for security ................................................................................................ 11
3.2 System resources................................................................................................................................................. 12
3.2.1 Power system..................................................................................................................................... 12
3.2.2 Regulators.......................................................................................................................................... 12
3.2.3 Clock system...................................................................................................................................... 14
3.2.4 Reset.................................................................................................................................................. 15
3.2.5 Watchdog timer .................................................................................................................................. 15
3.2.6 Power modes ..................................................................................................................................... 15
3.3 Peripherals ........................................................................................................................................................... 16
3.3.1 Peripheral clock dividers .................................................................................................................... 16
3.3.2 Peripheral protection unit ................................................................................................................... 16
3.3.3 12-bit SAR ADC ................................................................................................................................. 16
3.3.4 Timer/counter/PWM block (TCPWM)................................................................................................. 17
3.3.5 Serial communication blocks (SCB)................................................................................................... 17
3.3.6 CAN FD.............................................................................................................................................. 18
3.3.7 Ethernet MAC..................................................................................................................................... 18
3.3.8 External memory interface ................................................................................................................. 18
3.3.9 SDHC interface .................................................................................................................................. 18
3.3.10 Audio interface ................................................................................................................................. 18
3.3.11 One-time-programmable (OTP) eFuse ............................................................................................ 18
3.3.12 Event generator................................................................................................................................ 18
3.3.13 Trigger multiplexer............................................................................................................................ 19
3.4 I/Os........................................................................................................................................................................ 19
3.4.1 Port nomenclature.............................................................................................................................. 19
3.4.2 GPIO standard (GPIO_STD).............................................................................................................. 19
3.4.3 GPIO enhanced (GPIO_ENH)............................................................................................................ 19
3.4.4 HSIO standard (HSIO_STD) .............................................................................................................. 20
3.4.5 Smart I/O............................................................................................................................................ 20
4 XMC7200 address map...................................................................................................................21
5 Flash base address map.................................................................................................................23
6 Peripheral I/O map........................................................................................................................24
7 XMC7200 clock diagram.................................................................................................................26
8 XMC7200 CPU start-up sequence ....................................................................................................27
9 Pin assignment .............................................................................................................................28
10 High-speed I/O matrix connections...............................................................................................31
11 Package pin list and alternate functions .......................................................................................32
12 Power pin assignments................................................................................................................40
13 Alternate function pin assignments ..............................................................................................41
13.1 Pin function description .................................................................................................................................... 49
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Table of contents
14 Interrupts and wake-up assignments............................................................................................51
15 Core interrupt types....................................................................................................................64
16 Trigger multiplexer .....................................................................................................................65
17 Triggers group inputs ..................................................................................................................67
18 Triggers group outputs................................................................................................................71
19 Triggers one-to-one.....................................................................................................................72
20 Peripheral clocks ........................................................................................................................77
21 Faults.........................................................................................................................................81
22 Peripheral protection unit fixed structure pairs.............................................................................84
23 Bus masters..............................................................................................................................100
24 Miscellaneous configuration ......................................................................................................101
25 Development support................................................................................................................103
25.1 Documentation ................................................................................................................................................ 103
25.1.1 Software user guide ....................................................................................................................... 103
25.1.2 Technical reference manual........................................................................................................... 103
25.2 Tools ................................................................................................................................................................. 103
26 Electrical specifications.............................................................................................................104
26.1 Absolute maximum ratings ............................................................................................................................. 104
26.2 Device-level specifications .............................................................................................................................. 109
26.3 DC specifications.............................................................................................................................................. 110
26.4 Reset specifications ......................................................................................................................................... 117
26.5 I/O ..................................................................................................................................................................... 118
26.6 Analog peripherals........................................................................................................................................... 124
26.6.1 SAR ADC ....................................................................................................................................... 124
26.6.2 Calculating the impact of neighboring pins..................................................................................... 126
26.6.3 Temperature sensor....................................................................................................................... 129
26.6.4 Voltage divider accuracy ................................................................................................................ 129
26.7 AC specifications.............................................................................................................................................. 131
26.8 Digital peripherals............................................................................................................................................ 132
26.9 Memory............................................................................................................................................................. 141
26.10 System resources........................................................................................................................................... 143
26.10.1 SWD interface ............................................................................................................................. 152
26.11 Clock specifications ....................................................................................................................................... 153
26.12 Clock timing diagrams................................................................................................................................. 160
26.13 Ethernet specifications.................................................................................................................................. 162
26.14 SDHC specifications....................................................................................................................................... 166
26.15 Audio subsystem specifications.................................................................................................................... 168
26.16 Serial memory interface specifications ........................................................................................................ 171
27 Ordering information ................................................................................................................177
28 Packaging ................................................................................................................................178
29 Appendix..................................................................................................................................181
29.1 Bootloading or end-of-line programming ...................................................................................................... 181
29.2 External IP revisions......................................................................................................................................... 182
30 Acronyms .................................................................................................................................183
31 Errata ......................................................................................................................................185
Revision History ............................................................................................................................188
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features list
1
Features list
Table 1-1
XMC7200 feature list for all packages
Packages
Features
176-TEQFP
272-BGA
CPU
One or two 32-bit Arm® Cortex®-M7 CPUs and a 32-bit Arm® Cortex®
M0+ CPU
Core
Operating voltage
2.7 V to 5.5 V
Operating voltage for HSIO_STD
Core voltage
Not supported
2.7 V to 3.6 V
1.05 V to 1.15 V
Arm® Cortex®-M7 350 MHz (max for each) and Arm® Cortex®-M0+ 100
MHz (max)
Operating frequency
MPU, PPU
Supported
FPU
Supports both single (32-bit) and double (64-bit) precision
Supported by Arm® Cortex®-M7 CPUs
DSP-MUL/DIV/MAC
TCM
16-KB instruction and 16-KB data for each Cortex-M7 CPU
Memory
Code-flash
Work-flash
SRAM (configurable for retention)
ROM
8384 KB (8128 KB + 256 KB)
256 KB (192 KB + 64 KB)
1024 KB
64 KB
Communication interfaces
CAN0 (CAN-FD: Up to 8 Mbps)
CAN1 (CAN-FD: Up to 8 Mbps)
CAN RAM
5 ch
5 ch
40 KB per instance (5 ch), 80 KB in total
Serial communication Block (SCB/UART)
Serial communication Block (SCB/I2C)
Serial communication Block (SCB/SPI)
10 ch
10 ch
10 ch
11 ch
11 ch
11 ch
1 ch × 10/100
2 ch (option) × 10/100/1000
Ethernet MAC
ETH0: MII/RMII on GPIO_STD,
ETH1: RGMII on HSIO_STD
ETH0: MII/RMII on GPIO_STD
Memory interfaces
1 ch (GPIO_STD at 26 MHz)
1 ch (GPIO_STD at 32 MHz)
1 ch (HSIO_STD at 50 MHz, GPIO_STD at 26 MHz)
1 ch (HSIO_STD at 100 MHz, GPIO_STD at 32 MHz)
eMMC/SD
Single SPI/ Dual SPI/ Quad SPI/ OctalSPI
/ HYPERBUS™
Timers
RTC
1 ch
TCPWM (16-bit) (Motor Control)
TCPWM (16-bit)
TCPWM (32-bit)
External interrupts
15 ch (TCPWM0/3, TCPWM1/12)
87 ch (TCPWM0/3, TCPWM1/84)
16 ch (TCPWM0/3, TCPWM1/13)
220
148
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features list
Table 1-1
Analog
XMC7200 feature list for all packages (continued)
Features
Packages
176-TEQFP
272-BGA
3 Units (SAR0/32, SAR1/32, SAR2/32 logical channels)
81 external channels
96 external channels
(SAR0/24 ch,
12-bit, 1 Msps SAR ADC
(each SAR supports 32 ch)
SAR1/32 ch, SAR2/25 ch)
18 ch (6 per ADC) Internal sampling
Motor Control Input
3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security
Flash Security (program/work read pro-
tection)
Supported
Flash Chip erase enable
eSHE / HSM
Audio
Configurable
By separate firmware[1]
I2S / TDM
Tx 3 ch, Rx 3 ch
System
P-DMA0 with 143 channels (16 general purpose), P-DMA1 with 65
channels
DMA Controller
(8 general purpose), and M-DMA0 with 8 channels
Internal Main Oscillator
8 MHz
Internal Low speed Oscillator
32.768 kHz (nominal)
PLL
FLL
Input: 3.988 to 33.34 MHz, PLL output: up to 350 MHz
Input: 0.25 to 80 MHz, FLL output: up to 100 MHz
Watchdog Timer and Multi-counter
Watchdog Timer
Supported
Clock Supervisor
Cyclic wakeup from DeepSleep
GPIO_STD
GPIO_ENH
HSIO_STD
Supported
Supported
144
187
29
4
Not supported
Smart I/O (Blocks)
Low-Voltage Detect
Maximum Ambient Temperature
Debug Interface
5 blocks, mapped through 36 I/Os
Two, 26 selectable levels
125 °C
SWD/JTAG
Debug Trace
Arm® Cortex®-M7 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB
Note
1. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features list
1.1
Communication peripheral instance list
The following table lists the instances supported under each package for communication peripherals, based on
the minimum pins needed for the functionality.
Table 1-2
Module
CAN0
Communication peripheral instance list
176-TEQFP
0/1/2/3/4
0/1/2/3/4
0 to 9
272-BGA
0/1/2/3/4
0/1/2/3/4
0 to 10
Minimum Pin Functions
TX, RX
TX, RX
TX, RX
SCL, SDA
CAN1
SCB/UART
SCB/I2C
SCB/SPI
0 to 9
0 to 10
0 to 9
0 to 10
MISO, MOSI, SCK, SELECT0
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Blocks and functionality
2
Blocks and functionality
Block diagram
CPU subsystem
ITCM
DTCM
DTCM
16 KB
ITCM
XMC7200
MXS40-HT
16 KB
SWJ/ETM/ITM/CTI
SWJ/MTB/CTI
7
eCT flash
SRAM0
512 KB
SRAM1
SRAM2
256 KB
CRYPTO
AES,SHA,CRC,
TRNG,RSA,ECC
ROM
64 KB
Arm® Cortex®-M7
Arm®
Cortex® M0+
100 MHz
8384 KB Code-flash
+ 256 KB Work-flash
256 KB
350 MHz
FPU
(SP/DP)
D$
16 KB
I$
B
SRAM
controller
SRAM
controller
SRAM
controller
8 KB $
FLASH controller
System Resources
16 KB
BS
Initiator/MMIO
ROM controller
MUL, NVIC, MPU
NVIC, MPU, AXI
AHBP
AHBS
Power
Sleep control
POR
OVD
BOD
LVD
System interconnect (multilayer AXI/AHB, IPC, MPU/SMPU)
Peripheral interconnect (MMIO,PPU)
REF
PWRSYS-HT
LDO
PCLK
Clock
Clock control
Prog.
analog
SAR ADC
(12-bit)
2xILO
WDT
3x MCWDT
IMO
FLL
ECO
CSV
4xPLL
Reset
Reset control
XRES
x3
Test
TestMode entry
Digital DFT
Analog DFT
SARMUX
96 ch
WCO
RTC
Power modes
High-Speed I/O Matrix, Smart I/O, Boundary Scan
5x Smart IO
Active/sleep
Low-power active/sleep
Up to 187x GPIO_STD,4x GPIO_ENH, 29x HSIO_STD
Deep sleep
Hibernate
I/O subsystem
The Block diagram shows the XMC7200 architecture, giving a simplified view of the interconnection between
subsystems and blocks. XMC7200 has four major subsystems: CPU, system resources, peripherals, and I/O[2, 3, 4]
The color-coding shows the lowest power mode where the particular block is still functional.
.
XMC7200 provides extensive support for programming, testing, debugging, and tracing of both hardware and
firmware.
Debug-on-chip functionality enables in-system debugging using the production device. It does not require
special interfaces, debugging pods, simulators, or emulators.
The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.
The debug circuits are enabled by default.
XMC7200 provides a high level of security with robust flash protection and the ability to disable features such as
debug.
Additionally, each device interface can be permanently disabled for applications concerned with phishing
attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are disabled when maximum device
security is enabled.
Notes
2. GPIO_STD supports 2.7 V to 5.5 V VDDIO range.
3. GPIO_ENH supports 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
4. HSIO_STD supports 2.7 V to 3.6 V VDDIO range with high-speed signaling and programmable drive strength.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3
Functional description
3.1
CPU subsystem
3.1.1
CPU
The XMC7200 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and two 32-bit Arm® Cortex®-M7
CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This subsystem also
includes P-/M-DMA controllers, a cryptographic accelerator, 8384 KB of code-flash, 256 KB of work-flash, 1024 KB
of SRAM, and 64 KB of ROM.
The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following
completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,
SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by
an inter-processor communication (IPC) mechanism using hardware semaphores.
Each Cortex-M7 CPU has 16 KB of instruction and 16 KB of data TCM with programmable read wait states. Each
TCM is clocked by the associated Cortex-M7 CPU clock.
3.1.2
DMA controllers
XMC7200 has three DMA controllers: P-DMA0 with 16 general purpose and 127 dedicated channels, P-DMA1 with
8 general purpose and 57 dedicated channels, and M-DMA0 with eight channels. P-DMA is used for
peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of
channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.
General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables
demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)
to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high
memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each
channel. They support independent accesses to peripherals using the AHB multi-layer bus.
3.1.3
Flash
XMC7200 has 8384 KB (8128 KB with a 32-KB sector size, and 256 KB with an 8-KB sector size) of code-flash with
an additional work-flash of 256 KB (192 KB with a 2-KB sector size, and 64 KB with a 128-B sector size). Work-flash
is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)
operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support
dual-bank operation for over-the-air (OTA) programming.
3.1.4
SRAM
XMC7200 has 1024 KB of SRAM with three independent controllers. SRAM0 provides DeepSleep retention in 32-KB
increments while SRAM1/2 are selectable between fully retained and not retained.
3.1.5
ROM
XMC7200 has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and
authentication of user flash to guarantee a secure system.
3.1.6
Cryptography accelerator for security
The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy
check, pseudo random number generation, true random number generation, galois/counter mode, and a vector
unit to support asymmetric key cryptography such as RSA and ECC.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.2
System resources
Power system
3.2.1
The power system ensures that the supply voltage levels meet the requirements of each power mode, and
provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip
reset during the initial power ramp.
Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD is initially
enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the
external supplies VDDD and VDDA, BOD circuits are software-configurable with two settings; a 2.7-V minimum
voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for all I/O
specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a
robust detector.
Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and
overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and
VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.
Two voltage detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising
levels, each configurable for one of the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.
The BOD and OVD circuits on VDDA can be configured to generate either a reset, or a fault.
3.2.2
Regulators
XMC7200 contains three regulators that provide power to the low-voltage core transistors: DeepSleep, core
internal, and core external. These regulators accept a 2.7-V to 5.5-V VDDD supply and provide a low-noise 1.1-V
supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and
firmware when switching between power modes. The core internal and core external regulators operate in Active
mode, and provide power to the CPU subsystem and associated peripherals.
3.2.2.1 DeepSleep
The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode.
These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other
configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal
regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is
disabled.
3.2.2.2 Core internal
The core internal regulator supports load currents up to 300 mA, and is operational during device start-up
(boot process), and in Active/Sleep modes.
3.2.2.3 Core external[5]
To support worst-case loading, with both M7 CPUs and the M0+ CPU at their maximum clock frequency and all
integrated peripherals operating, a core external regulator is required, capable of load currents up to 600 mA.
While the control and monitor circuits for the core external regulator are internal to XMC7200, the power
regulating element (NPN pass transistor, PMIC, or LDO) is external. This reduces the overall power dissipation
within the XMC7200 package, while maintaining a well-regulated core supply.
The core external regulator may be implemented with either an external NPN pass transistor, PMIC, or linear
regulator (LDO). Each implementation requires different external components on the PCB, and different
connections to XMC7200 for both regulation and control.
Note
5. When XMC7200 is in Hibernate mode, the GPIO used to control the core external regulator are High-Z. This may require an external
pull-up or pull-down resistor to disable the external regulator and configure it for minimum operating current.
Datasheet
12
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
Vpwr
(2.7-5.5V)
XMC7000
10 uF
VDDD
NPN transistor
Emitter Follower
ZXT849K
etc
DRV_VOUT
EXT_PS_CTL0
EXT_PS_CTL1
0.1Ω
1/4W
1%
Core supply rail
VCCD
CS1
Figure 3-1
Sample core external regulator with NPN transistor
2.7V – 5.5V Power rail
VDDD
Vin
Core supply rail
Switching node
VCCD
XMC7000
External
PMIC
CS1
R1
R2
Enable
(EN)
Feedback
(FB)
DRV_VOUT
VDDD or
EXT_PS_CTL1
Power Good
Power Good
(PG)
EXT_PS_CTL0
EXT_PS_CTL1
- PMIC EN pin polarity is HIGH for enable. PMIC PG pin polarity is HIGH for power good.
- If EN pin of PMIC does not have the internal pull-down resistor, an external pull-down resistor must be placed to keep the PMIC disabled during power-on reset.
- See the Electrical Specifications section for more information on CS1.
- Output voltage setting resistors (R1, R2) are needed according to the selected PMIC.
Figure 3-2
Sample core external regulator with PMIC/LDO
Both the core internal and core external regulators require an external bulk storage capacitor connected to the
VCCD pin. This capacitor provides charge under the dynamic loads of the low-voltage core transistors.
Datasheet
13
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.2.3
Clock system
The XMC7200 clock system provides clocks to all subsystems that require them, and glitch-free switching
between different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for XMC7200 consists of the 8-MHz IMO, two ILOs, four watchdog timers, four PLLs, an FLL, five
clock supervisors (CSV), a 8- to 33.34-MHz ECO, and a 32.768-kHz WCO.
The clock system supports three main clock domains: CLK_HF, CLK_SLOW, and CLK_LF.
• CLK_HFx are the Active mode clocks. Each can use any of the high frequency clock sources including IMO,
EXT_CLK, ECO, FLL, or PLL
• CLK_SLOW provides a reference clock for the Cortex-CM0+ CPU, CRYPTO, P-/M-DMA, and other slow infra-
structure blocks of CPU subsystem
• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The
reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO.
Table 3-1
Name
CLK_HF destinations
Description
CPUSS (Memories, CLK_SLOW, Peripherals)
CPUSS (Cortex-M7 CPU 0, 1)
CAN FD, TCPWM, SCB, SAR
Event Generator
Ethernet
Audio Subsystem (I2S)
SDHC Interface, SMIF
CLK_HF0
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
CLK_HF6
3.2.3.1 IMO Clock Source
The IMO is the frequency reference in XMC7200 when no external reference is available or enabled. The IMO
operates at a frequency of around 8 MHz.
3.2.3.2 ILO Clock Source
An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in
DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven
counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-
vision.
3.2.3.3 PLL and FLL
A PLL (one of the two 200 MHz and two 400 MHz) or FLL may be used to generate high-speed clocks from the IMO,
ECO, or an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 45 µs) in exchange for a
small amount (±2%) of frequency error[6]. The 400-MHz PLL supports spread spectrum clock generation (SSCG)
with down spreading.
3.2.3.4 Clock Supervisor
Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).
Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the
frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the
frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an
abnormal state is signaled and either a reset or an interrupt is generated.
Note
6. Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency
error.
Datasheet
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.2.3.5 EXT_CLK
One of three GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be used
as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.
3.2.3.6 ECO
The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.
It supports fundamental mode (non-overtone) quartz crystals, in the range of 8 to 33.34 MHz. When used in
conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO
accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the
available I/O functions.
3.2.3.7 WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external
32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock
reference for CLK_LF, which is the clock source for the MCWDT and RTC.
3.2.4
Reset
XMC7200 can be reset from a variety of sources, including software. Most reset events are asynchronous and
guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT,
software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and
allows software to determine the cause of the reset. An XRES_L pin is available for external reset.
3.2.5
Watchdog timer
XMC7200 has one watchdog timer (WDT) and three multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from
Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT
timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause
register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are
only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used
separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.
3.2.6
Power modes
XMC7200 has six power modes.
• Active – all peripherals are available
• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are
available, but with limited capability
• Sleep – all peripherals except the CPUs are available
• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are
available, but with limited capability
• DeepSleep – only peripherals which work with CLK_LF are available
• Hibernate – the device and I/O states are frozen; the device resets on wakeup
Datasheet
15
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3
Peripherals
3.3.1
Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-2
Clock dividers - CPUSS Group (Nr. 0)
Instances
Divider Type
div_8
div_16
Description
4
3
1
Integer divider, 8 bits
Integer divider, 16 bits
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
div_24_5
Table 3-3
Clock dividers - COMM Group (Nr. 1)
Instances
Divider Type
div_8
div_16
Description
19
20
21
Integer divider, 8 bits
Integer divider, 16 bits
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
div_24_5
3.3.2
Peripheral protection unit
The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,
P-/M-DMA, CRYPTO, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on
the bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address
range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).
3.3.3
12-bit SAR ADC
XMC7200 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit
result in 26 clock cycles. The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and
VREFL[7]
.
XMC7200 supports up to 117 logical ADC channels, and external inputs from up to 99 I/Os. Each ADC also supports
six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and
package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with
zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1
Msps whether it is for a single channel or distributed over several channels). The sequencer switching is
controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the
appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates
subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32
GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal
signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports
synchronous sampling of one motor-sense channel on each of the three ADCs.
XMC7200 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be
sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading
into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, you can have different sample times
programmed for each channel. Each ADC also supports range comparison, which allows fast detection of
out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate
the measurement for out-of-range values.
The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input
reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA
.
Note
7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces
or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.
Datasheet
16
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3.4
Timer/counter/PWM block (TCPWM)
The TCPWM block consists of 16-bit (102 channels) and 32-bit (16 channels) counters with user-programmable
period. Fifteen of the 16-bit counters are optimized for motor-control operations. Each TCPWM counter contains
a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload
the counter when its count is equal to the period register), and compare registers to generate signals that are
used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,
PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with
features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead
times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to
allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the
PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems
when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time
for software intervention).
3.3.5
Serial communication blocks (SCB)
XMC7200 contains 11 serial communication blocks, each configurable to support I2C, UART, or SPI.
3.3.5.1 I2C interface
An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave
interface. Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus) and has flexible
buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO
buffering for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the
need for clock stretching. The I2C interface is compatible with Standard, Fast-mode, and Fast-mode Plus
devices as specified in the NXP I2C-bus specification and user manual (UM10204). The I2C-bus I/O is
implemented with GPIO in open-drain modes[8, 9]
.
3.3.5.2 UART interface
When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined
by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and
SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit
multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.
Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.
FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.
3.3.5.3 SPI interface
The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start
pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The
SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports
EZSPI[10] mode.
SCB0 supports the following additional features:
• Operable as a slave in DeepSleep mode
• I2C slave EZ (EZI2C[11]) mode with up to 256-B data buffer for multi-byte communication without CPU
intervention
• I2C slave externally-clocked operations
• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention
Notes
8. This is not 100% compliant with the I2C-bus specification; I/Os are not overvoltage-tolerant, do not support the 20-mA sink require-
ment of Fast-mode Plus, and violate the leakage specification when no power is applied.
9. Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.
10.The Easy SPI (EZSPI) protocol is based on the Motorola SPI protocol operating in any mode (0, 1, 2, or 3). It allows communication
between master and slave while reducing the need for CPU intervention.
11.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Infineon. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU
intervention.
12.Only 10/100 Mbps is available in the 176-TEQFP packaged devices.
Datasheet
17
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3.6
CAN FD
XMC7200 contains two CAN FD controller blocks, each supporting five CAN FD channels. All CAN FD controllers
are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements
the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in
hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx
handler manages message acceptance filtering, transfer of received messages from the CAN core to a message
RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages
from the message RAM to the CAN core, and provides transmit-message status.
3.3.7
Ethernet MAC
XMC7200 supports two Ethernet channels with transfer rates of 10, 100, or 1000 Mbps[12]. The input/output
frames and flow control are complaint to the Ethernet/IEEE 802.3az standard and also IEEE-1588 precision-time
protocol (PTP). XMC7200 supports half/full-duplex data transport using external PHY devices. The MAC supports
glue-free connection to PHYs through IEEE standard MII, RMII, and RGMII interfaces. The device also supports
Audio-Video Bridging (AVB). The MAC supports standard 6-byte programmable addresses.
3.3.8
External memory interface
In addition to the internal flash memory, XMC7200 supports direct connection to as much as 128-MB of external
flash or RAM memory. This connection is made through either a HYPERBUS™ or serial peripheral interface (SPI).
HYPERBUS™ allows connection to HYPERFLASH™ and HYPERRAM™ devices, while SPI (single, dual, quad, or octal
SPI at up to 80 MHz) can connect with serial flash memory. Code stored in memory connected through this
interface allows execute-in-place (XIP) operation, which does not require the instructions to be first copied to
internal memory, and on-the-fly encryption and decryption for environments requiring secure external data and
code.
3.3.9
SDHC interface
XMC7200 supports one Secure Digital High Capacity (SDHC) interface, which conforms to Secure Digital (SD) 6.0,
Secure Digital Input Output (SDIO) 4.10, and Embedded Multimedia Card (eMMC) 5.1 specifications, along with
Host Control Interface (HCI) 4.2 specification. The interface supports System DMA (SDMA), Advance DMA (ADMA2,
ADMA3), and command queuing (CQ) features. This interface supports data rates of SD DS (Default Speed, 4-bits
at 25 MHz), SD HS (High Speed, 4-bits at 50 MHz, and eMMC 52-MHz DDR (8-bits at 52-MHz card clock).
3.3.10
Audio interface
XMC7200 supports three instances of Inter-IC Sound Bus (I2S) interface to connect to digital audio devices. It also
supports standard I2S, Left Justified (LJ), and eight-channel Time Division Multiplexed (TDM) digital audio
interface formats in both master and slave modes with independent operations in receive and transmit
directions.
3.3.11
One-time-programmable (OTP) eFuse
XMC7200 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable
identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,
programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available
for user purposes.
3.3.12
Event generator
The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep
mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a
SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide
CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing
overall power consumption and processing overhead.
Datasheet
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3.13
Trigger multiplexer
XMC7200 supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral
of the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other
peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers
provide active logic functionality and are typically supported in Active mode.
3.4
I/Os
XMC7200 has up to 220 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on and
reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service
routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-4. The associated supply determines the VOH, VOL, VIH, and VIL
levels when configured for CMOS and industrial thresholds.
Table 3-4
I/O Port power source
Supply Pins
VDDD
Ports
P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P28, P29, P30, P31
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
P6, P7, P8, P9, P32
P10, P11, P12, P13, P14, P15
P24, P25
P26, P27
3.4.1
Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
XMC7200 has three types of programmable I/Os: GPIO Standard, GPIO Enhanced, and HSIO Standard.
3.4.2
GPIO standard (GPIO_STD)
Supports standard industrial signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple
configurable drive levels, drive modes, and selectable input levels.
3.4.3
GPIO enhanced (GPIO_ENH)
Supports extended functionality industrial signaling across the 2.7-V to 5.5-V VDDIO range with higher currents at
lower voltages (full I2C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or industrial)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)
Datasheet
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.4.4
HSIO standard (HSIO_STD)
These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep
operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIO_STD supports high-speed
peripherals such as QSPI, HYPERBUS™, Ethernet, and SDHC controller. HSIO_STD also supports programmable
drive strength. These I/Os are available only in Active mode and retain state in DeepSleep mode.
3.4.5
Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. XMC7200 has five Smart I/O blocks. Operation can be synchronous or asynchronous and
the blocks operate in all device power modes except for Hibernate.
Datasheet
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7200 address map
4
XMC7200 address map
The XMC7200 microcontroller supports the memory spaces shown in Figure 4-1.
• 8384 KB (8128 KB + 256 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in
the flash control register
- Single-bank mode: 8384 KB
- Dual-bank mode: 4192 KB per bank
• 256 KB (192 KB + 64 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register
- Single-bank mode: 256 KB
- Dual-bank mode: 128 KB per bank
• 64 KB of secure ROM
• 1024 KB of SRAM (First 2 KB is reserved for internal usage)
• 16 KB of Instruction TCM for each Cortex-M7 CPU
• 16 KB of Data TCM for each Cortex-M7 CPU
• 128 MB SMIF XIP
Datasheet
21
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7200 address map
0xFFFF FFFF
Arm System
Space
CPU & Debug Registers
0xE000 0000
Reserved
16 KB
0xA011 3FFF
0xA011 0000
Core CM7_1 Data TCM
CM7_1 DTCM
CM7_1 ITCM
CM7_0 DTCM
CM7_0 ITCM
Reserved
16 KB
0xA010 3FFF
0xA010 0000
Core CM7_1 Instruction TCM
Core CM7_0 Data TCM
Reserved
16 KB
Reserved
16 KB
0xA001 3FFF
0xA001 0000
0xA000 3FFF
0xA000 0000
Core CM7_0 Instruction TCM
Reserved
0x67FF FFFF
SMIF_XIP
Serial Memory Interface XIP
128 MB
0x6000 0000
0x43FF FFFF
Reserved
Peripheral
Mainly used for on-chip peripherals;
e.g., AHB or APB peripherals
Interconnect or
Memory map
0x4000 0000
0x280F FFFF
Reserved
256 KB
SRAM2
SRAM1
0x280C 0000
0x280B FFFF
General purpose RAM,
mainly used for data
256 KB
0x2808 0000
0x2807 FFFF
510 KB
2 KB
SRAM0
0x2800 0800
0x2800 0000
Reserved
CM7 internal address map for its
Data TCM
0x2000 3FFF
0x2000 0000
16 KB
CM7 DTCM
Reserved
Used to store manufacture specific
data like flash protection settings, trim
settings, device addresses, serial numbers,
calibration data, etc.
Alternate Flash
Supervisory
0x1780 7FFF
0x1780 0000
32 KB
Reserved
32 KB
Reserved
0x1700 7FFF
0x1700 0000
Flash Supervisory
Work flash
0x1403 FFFF
64 KB
(128B Small Sectors)
0x1403 0000
0x1402 FFFF
Work flash used for long
term data retention
192 KB
(2 KB Large Sectors)
0x1400 0000
0x1082 FFFF
Reserved
256 KB
(8 KB Small Sectors)
0x107F 0000
0x107E FFFF
Code flash
ROM Mirror
Mainly used for user program code
8128 KB
(32 KB Large
Sectors)
0x1000 0000
Reserved
64 KB
Reserved
64 KB
Secured Boot ROM to set user specified
protection levels, trim and configuration
data, code authentication, jump to user mode, etc.
0x0100 FFFF
0x0100 0000
0x0000 FFFF
ROM
0x0000 0000
CM7 internal address map for its instruction TCM.
The address overlaps with portion of ROM region.
0x0000 3FFF
16 KB
CM7 ITCM
0x0000 0000
Figure 4-1
XMC7200 address map[13, 14]
Notes
13.The size representation is not up to scale.
14.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32-KB block of SRAM0 in enabled or retained in
all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.
Datasheet
22
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1
Code-flash address mapping in single-bank mode
Code-flash Size Large Sectors Small Sectors
Large Sector Base Address Small Sector Base Address
(KB)
(LS)
(SS)
8384
32 KB × 254
8 KB × 32
0x1000 0000
0x107F 0000
Table 5-2
Work-flash address mapping in single-bank mode
Work-flash Size
(KB)
Large Sectors Small Sectors Large Sector Base Address Small Sector Base Address
256
2 KB × 96
128 B × 512
0x1400 0000
0x1403 0000
Table 5-3
Code-flash address mapping in dual-bank mode (mapping A)
Second
Half
Second
First Half First Half
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
Half SS
Base
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
8384
32 KB × 127 8 KB × 16 32 KB × 127 8 KB × 16
0x1000
0000
0x103F
8000
0x1200
0000
0x123F
8000
Table 5-4
Code-flash address mapping in dual-bank mode (mapping B)
Second
Half
Second
Half SS
Base
First Half First Half
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
8384
32 KB × 127 8 KB × 16 32 KB × 127 8 KB × 16
0x1200
0000
0x123F
8000
0x1000
0000
0x103F
8000
Table 5-5
Work-flash address mapping in dual-bank mode (mapping A)
Second
Half
Second
Half SS
Base
First Half First Half
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
256
2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1400
0000
0x1401
8000
0x1500
0000
0x1501
8000
Table 5-6
Work-flash address mapping in dual-bank mode (mapping B)
Second
Half
Second
Half SS
Base
First Half First Half
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
256
2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1500
0000
0x1501
8000
0x1400
0000
0x1401
8000
Datasheet
23
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral I/O map
6
Peripheral I/O map
Table 6-1
XMC7200 peripheral I/O map
Base
Instance
Size
Section
Description
Instances
Group Slave
Address
Peripheral interconnect
Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9)
Peripheral trigger group
0x4000 0000
0x4000 4000
0x4000 8000
0x4000 C000
9
13
14
0x40
0x400
0x400
PERI
0
0
Peripheral 1:1 trigger group
Peripheral interconnect, master interface 0x4002 0000
PERI_MS
PERI Programmable PPU
PERI Fixed PPU
0x4002 0000
0x4002 0800
0x4004 0000
0x4010 0000
0x4020 0000
0x4021 0000
0x4021 0000
0x4022 0000
0x4022 0000
0x4022 1000
0x4023 0000
10[15]
700
2
0x40
0x40
0
1
PERI_PCLK Peripheral Clock Groups
0x2000
0
1
2
2
0
0
CRYPTO
CPUSS
Cryptography component
CPU subsystem (CPUSS)
Fault structure subsystem
Fault structures
FAULT
2
1
4
0x100
Inter process communication
IPC structures
IPC
8
8
0x20
0x20
2
2
IPC interrupt structures
Protection
PROT
Shared memory protection unit structures 0x4023 2000
16
16
0x40
0x400
2
2
3
4
Memory protection unit structures
Flash controller
0x4023 4000
0x4024 0000
FLASHC
System Resources Sub-System Core
Registers
0x4026 0000
Clock Supervision High Frequency
Clock Supervision Reference Frequency
Clock Supervision Low Frequency
Clock Supervision Internal Low Frequency 0x4026 1730
Clock PLL 400 MHz
Multi Counter WDT
Free Running WDT
SRSS Backup Domain/RTC
Backup Register
P-DMA0 Controller
P-DMA0 channel structures
P-DMA1 Controller
P-DMA1 channel structures
M-DMA0 Controller
M-DMA0 channels
eFUSE Customer Data (192 bits)
0x4026 1400
0x4026 1710
0x4026 1720
8
1
1
1
2
3
1
0x10
SRSS
2
5
0x4026 1900
0x4026 8000
0x4026 C000
0x4027 0000
0x4027 1000
0x4028 0000
0x4028 8000
0x4029 0000
0x4029 8000
0x402A 0000
0x402A 1000
0x402C 0868
0x10
0x100
BACKUP
P-DMA
2
2
2
6
7
8
4
0x04
0x40
0x40
143
65
M-DMA
2
2
9
8
6
0x100
0x04
eFUSE
10
Note
15.These Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the
device-specific TRM to know more about the configuration of these programmable PPUs.
Datasheet
24
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral I/O map
Table 6-1
Section
XMC7200 peripheral I/O map (continued)
Base
Instance
Size
Description
Instances
Group Slave
Address
HSIOM
GPIO
High-Speed I/O Matrix (HSIOM)
GPIO port control/configuration
Programmable I/O configuration
SMARTIO port configuration
Timer/Counter/PWM 0 (TCPWM0)
TCPWM0 Group #0 (16-bit)
0x4030 0000
0x4031 0000
0x4032 0000
0x4032 0C00
0x4038 0000
0x4038 0000
35
35
0x10
0x80
3
3
0
1
SMARTIO
3
2
5
0x100
3
3
3
0x80
0x80
0x80
TCPWM
3
3
TCPWM0 Group #1 (16-bit, Motor control) 0x4038 8000
TCPWM0 Group #2 (32-bit)
Event generator 0 (EVTGEN0)
Event generator 0 comparator structures
Serial Memory Interface 0 (SMIF0)
SMIF0 Devices
Secure Digital High Capacity 0 (SDHC0)
SDHC0 Wrap
SDHC0 Core
Ethernet 0 (ETH0)
CAN0 controller
Message RAM CAN0
CAN1 controller
Message RAM CAN1
Timer/Counter/PWM 1 (TCPWM1)
TCPWM1 Group #0 (16-bit)
TCPWM1 Group #1 (16-bit, Motor control) 0x4058 8000
TCPWM1 Group #2 (32-bit)
0x4039 0000
0x403F 0000
0x403F 0800
0x4042 0000
0x4042 0800
0x4046 0000
0x4046 0000
0x4046 1000
0x4048 0000
0x4052 0000
0x4053 0000
0x4054 0000
0x4055 0000
0x4058 0000
0x4058 0000
EVTGEN
SMIF
3
4
4
0
16
1
0x20
0x80
SDHC
ETH
4
1
2
5
0x10000
0x200
0x9FFF
0x200
4
5
2
1
TTCANFD
TCPWM
5
5
5
2
4
0x9FFF
84
12
13
0x80
0x80
0x80
0x4059 0000
0x4060 0000
0x4080 0000
Serial Communications Block
SCB
I2S
11
3
0x10000
0x1000
6
8
0-10
0-2
(SPI/UART/I2C)
I2S Audio SubSystem
Programmable Analog Subsystem (PASS0) 0x4090 0000
SAR0 channel controller
SAR1 channel controller
SAR2 channel controller
SAR0 channel structures
SAR1 channel structures
SAR2 channel structures
0x4090 0000
0x4090 1000
0x4090 2000
0x4090 0800
0x4090 1800
0x4090 2800
SAR PASS
9
0
32
32
32
0x40
0x40
0x40
Datasheet
25
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7200 clock diagram
7
XMC7200 clock diagram
EXT_CLK ECO
IMO
WCO
LS
ILO0
LS
ILO1
LS
ECO
Prescaler
LS
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
FLL
MUX
PLL400#0
MUX
PLL400#1
MUX
PLL#2
MUX
PLL#3
MUX
MUX
LS
CLK_ILO0
CLK_
PATH0
CLK_
PATH1
CLK_
PATH2
CLK_
PATH3
CLK_
PATH4
CLK_
PATH5
CLK_REF_HF
WDT
RTC
MUX
CLK_BAK
CLK_LF
CSV
CLK_ILO0
MCWDT
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
CLK_HF0
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
CLK_HF6
CLK_HF7
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CLK_ILO0
CLK_LF
CLK_REF_HF
SDHC
AUDIOSS
I2S External Clock
Ethernet
Tx_CLK, Rx_CLK and REF_CLK to Ethernet PHY
Event Generator
CAN FD
CLK_GR5
Divider
(1-256)
TCPWM[1]
CLK_GR6
CLK_GR9
Divider
(1-256)
SCB[*]
SCB[0]
Serial Interface Clock
Divider
(1-256)
SAR ADC
PCLK_CANFD[x]_CLOCK_CAN[y]
Peripheral
Clock Dividers #1
PCLK_TCPWM1_CLOCKS[x]
PCLK_SCB[x]_CLOCK
PCLK_PASS_CLOCK_SAR[x]
CLK_FAST_0
CLK_FAST_1
Divider
(1-256)
CM7_0
CM7_1
Divider
(1-256)
SMIF
CLK_MEM
Divider
(1-256)
ROM/SRAM/FLASH
CPUSS Fast Infrastructure
CLK_SLOW
Divider
(1-256)
CM0+
LEGEND 1:
Active Domain
CPUSS Slow Infrastructure
P-DMA / M-DMA
CRYPTO
DeepSleep Domain
Hibernate Domain
CLK_PERI
CLK_GR3
LEGEND 2:
Relationship of Monitored Clock and
Reference Clock
Divider
(1-256)
Divider
(1-256)
Monitored Clock
PERI
CLK_GR4
CLK_GR8
Divider
(1-256)
SRSS
Reference Clock
CSV
Divider
(1-256)
EFUSE
LEGEND 3:
One Clock Line
Multiple Clock Lines
IOSS
TCPWM[0]
Peripheral
Clock Dividers #0
CPUSS(DEBUG)
TCK/SWDCLK from a Debugger
CLK_TRC_DBG
Divider
(1-256)
PCLK_SMARTIO[x]_CLOCK
PCLK_TCPWM0_CLOCKS[x]
PCLK_CPUSS_CLOCK_TRACE_IN
Figure 7-1
XMC7200 clock diagram
Datasheet
26
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7200 CPU start-up sequence
8
XMC7200 CPU start-up sequence
The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2. CM0+ executes ROM boot (@0x0000 0004)
i. Applies trims
ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory
flash
iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
i. Debug pins are configured based on the SWD/JTAG spec[16]
ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000)
iii.CM0+ branches to its Reset handler
4. CM0+ starts execution of application
i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
i. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 (CLK_HF2)
ii. Sets CM7_0 (CM7_0_VECTOR_TABLE_BASE @0x4020 0200) and CM7_1 (CM7_1_VECTOR_TABLE_BASE
@0x4020 0600) vector tables to the respective locations, also and mentioned in flash (specified in the linker
definition file)
iii.Enables the power for both the CPU cores CM7_0 and CM7_1
iv.Disables CPU_WAIT to allow accesses from the debugger
v. Releases CM7_0 and/or CM7_1 from reset
vi.Continues execution of CM0+ user application
5. CM7_0 and/or CM7_1 executes directly from either code-flash or SRAM
i. CM7_0/CM7_1 branches to its Reset handler
ii. Continues execution of the user application
Note
16.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer to
Table 11-1 for pin assignments.
Datasheet
27
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
9
Pin assignment
Note: Thermal pad needs to be connected to VSSD.
VSSD
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
VDDD
VSSD
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VDDD
VDDIO_1
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.7
P17.6
P17.5
P17.4
P17.3
P17.2
P17.1
P17.0
P16.3
VSSD
VCCD
VCCD
VCCD
VDDD
P15.3
P15.2
P15.1
P15.0
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-TEQFP
98
97
96
95
94
93
92
91
90
89
Figure 9-1
176-TEQFP pin assignment
Datasheet
28
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
VSSD
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
2
P18.7 PWM1_50/PWM1_51_N/TC1_50_TR0/TC1_51_TR1/TC0_M_2_TR1/ETH0_TXD_3/PWM1_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_23
P18.6 PWM1_51/PWM1_52_N/TC1_51_TR0/TC1_52_TR1/TC0_M_2_TR0/ETH0_TXD_2/PWM1_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_22
P18.5 PWM1_52/PWM1_53_N/TC1_52_TR0/TC1_53_TR1/PWM0_M_2_N/ETH0_TXD_1/PWM1_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_21
P18.4 PWM1_53/PWM1_54_N/TC1_53_TR0/TC1_54_TR1/PWM0_M_2/ETH0_TXD_0/PWM1_H_2/SCB1_SEL1/SCB3_SEL0/TRACE_DATA_0/ADC[2]_20
P18.3 PWM1_54/PWM1_55_N/TC1_54_TR0/TC1_55_TR1/ETH0_TX_CLK/PWM1_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_19
P18.2 PWM1_55/PWM1_M_7_N/TC1_55_TR0/TC1_M_7_TR1/ETH0_TX_ER/PWM1_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB3_MOSI/ADC[2]_18
P18.1 PWM1_M_7/PWM1_M_6_N/TC1_M_7_TR0/TC1_M_6_TR1/ETH0_TX_CTL/PWM1_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ADC[2]_17
P18.0 PWM1_M_6/PWM1_M_5_N/TC1_M_6_TR0/TC1_M_5_TR1/ETH0_REF_CLK/PWM1_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_16
P17.7 PWM1_M_5/PWM1_M_4_N/TC1_M_5_TR0/TC1_M_4_TR1/ADC[2]_15
PWM1_18/PWM1_22_N/TC1_18_TR0/TC1_22_TR1/PWM0_H_0/SCB0_RX/SCB7_SDA/SCB0_MISO P0.0
PWM1_17/PWM1_18_N/TC1_17_TR0/TC1_18_TR1/PWM0_H_0_N/SCB0_TX/SCB7_SCL/SCB0_MOSI P0.1
PWM1_14/PWM1_17_N/TC1_14_TR0/TC1_17_TR1/TC0_H_0_TR0/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/CAN0_1_TX P0.2
PWM1_13/PWM1_14_N/TC1_13_TR0/TC1_14_TR1/TC0_H_0_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX P0.3
PWM1_12/PWM1_13_N/TC1_12_TR0/TC1_13_TR1/PWM1_H_4/SCB0_SCL/SCB0_MISO/SCB4_CLK P1.0
PWM1_11/PWM1_12_N/TC1_11_TR0/TC1_12_TR1/PWM1_H_5/SCB0_SDA/SCB0_MOSI/SCB4_SEL0 P1.1
PWM1_10/PWM1_11_N/TC1_10_TR0/TC1_11_TR1/PWM1_H_6/SCB0_CLK/TRIG_IN[0] P1.2
3
4
5
6
7
8
PWM1_8/PWM1_10_N/TC1_8_TR0/TC1_10_TR1/PWM1_H_7/SCB0_SEL0/TRIG_IN[1] P1.3
9
PWM1_7/PWM1_8_N/TC1_7_TR0/TC1_8_TR1/TC1_H_4_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM1_6/PWM1_7_N/TC1_6_TR0/TC1_7_TR1/TC1_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/CAN0_0_RX/TRIG_IN[3] P2.1
PWM1_5/PWM1_6_N/TC1_5_TR0/TC1_6_TR1/ETH0_RX_ER/TC1_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK//TRIG_IN[4] P2.2
PWM1_4/PWM1_5_N/TC1_4_TR0/TC1_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC1_H_7_TR0/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3
PWM1_3/PWM1_4_N/TC1_3_TR0/TC1_4_TR1/PWM1_H_4_N/SCB7_SEL1/TRIG_IN[6] P2.4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P17.6 PWM1_M_4/PWM1_56_N/TC1_M_4_TR0/TC1_56_TR1/PWM1_H_2_N/SCB3_SEL2/ADC[2]_14
P17.5 PWM1_56/PWM1_57_N/TC1_56_TR0/TC1_57_TR1/PWM1_H_2//SCB3_SEL1/ADC[2]_13
P17.4 PWM1_57/PWM1_58_N/TC1_57_TR0/TC1_58_TR1/PWM1_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]/ADC[2]_12
P17.3 PWM1_58/PWM1_59_N/TC1_58_TR0/TC1_59_TR1/PWM1_H_3/SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]/ADC[2]_11
P17.2 PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/SCB3_TX/SCB3_SDA/ADC[2]_10
PWM1_2/PWM1_3_N/TC1_2_TR0/TC1_3_TR1/PWM1_H_5_N/SCB7_SEL2/TRIG_IN[7] P2.5
PWM1_1/PWM1_2_N/TC1_1_TR0/TC1_2_TR1/ETH0_MDIO/PWM1_H_6_N/SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0] P3.0
PWM1_0/PWM1_1_N/TC1_0_TR0/TC1_1_TR1/ETH0_MDC/PWM1_H_7_N/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1] P3.1
PWM1_M_3/PWM1_0_N/TC1_M_3_TR0/TC1_0_TR1/TC1_H_4_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK P3.2
PWM1_M_2/PWM1_M_3_N/TC1_M_2_TR0/TC1_M_3_TR1/TC1_H_5_TR1/SCB6_CTS/SCB6_SEL0 P3.3
PWM1_M_1/PWM1_M_2_N/TC1_M_1_TR0/TC1_M_2_TR1/TC1_H_6_TR1/SCB6_SEL1 P3.4
P17.1 PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/SCB3_RX/CAN1_1_RX/ADC[2]_9
P17.0 PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/CAN1_1_TX/ADC[2]_8
P16.3 PWM1_62/PWM1_62_N/TC1_62_TR0/TC1_62_TR1/PWM1_H_1_N/ADC[2]_3
VSSD
VCCD
PWM1_M_0/PWM1_M_1_N/TC1_M_0_TR0/TC1_M_1_TR1/TC1_H_7_TR1/SCB6_SEL2 P3.5
VCCD
VDDD
VCCD
176-TEQFP
VSSD
VDDD
PWM1_4/PWM1_M_0_N/TC1_4_TR0/TC1_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/SCB5_MISO/TRIG_IN[10] P4.0
PWM1_5/PWM1_4_N/TC1_5_TR0/TC1_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/SCB5_MOSI/TRIG_IN[11] P4.1
PWM1_6/PWM1_5_N/TC1_6_TR0/TC1_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/SCB5_CLK/TRIG_IN[12] P4.2
PWM1_7/PWM1_6_N/TC1_7_TR0/TC1_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/CAN0_1_TX/TRIG_IN[13] P4.3
PWM1_8/PWM1_7_N/TC1_8_TR0/TC1_7_TR1/SCB5_SEL1/CAN0_1_RX P4.4
P15.3 PWM1_59/PWM1_58_N/TC1_59_TR0/TC1_58_TR1/AUDIOSS2_RX_SDI/TC1_H_7_TR1/SCB9_CTS/SCB9_SEL0/ADC[1]_31
P15.2 PWM1_58/PWM1_57_N/TC1_58_TR0/TC1_57_TR1/AUDIOSS2_RX_WS/TC1_H_7_TR0/SCB9_RTS/SCB9_SCL/SCB9_CLK/ADC[1]_30
P15.1 PWM1_57/PWM1_56_N/TC1_57_TR0/TC1_56_TR1/AUDIOSS2_RX_SCK/TC1_H_6_TR1/SCB9_TX/SCB9_SDA/SCB9_MOSI/CAN1_3_RX/ADC[1]_29
P15.0 PWM1_56/PWM1_55_N/TC1_56_TR0/TC1_55_TR1/AUDIOSS2_CLK_I2S_IF/TC1_H_6_TR0/SCB9_RX/SCB9_MISO/CAN1_3_TX/ADC[1]_28
P14.7 PWM1_55/PWM1_54_N/TC1_55_TR0/TC1_54_TR1/TC1_H_5_TR1/TRIG_IN[25]/ADC[1]_27
PWM1_9/PWM1_8_N/TC1_9_TR0/TC1_8_TR1/PWM0_M_0/PWM1_H_10/SCB5_SEL2/TRIG_IN[38] P5.0
PWM1_10/PWM1_9_N/TC1_10_TR0/TC1_9_TR1/PWM0_M_0_N/PWM1_H_10_N/SCB9_SEL3/TRIG_IN[39] P5.1
PWM1_11/PWM1_10_N/TC1_11_TR0/TC1_10_TR1/TC0_M_0_TR0/TC1_H_10_TR0 P5.2
P14.6 PWM1_54/PWM1_53_N/TC1_54_TR0/TC1_53_TR1/TC1_H_5_TR0/TRIG_IN[24]/ADC[1]_26
P14.5 PWM1_53/PWM1_52_N/TC1_53_TR0/TC1_52_TR1/AUDIOSS2_TX_SDO/TC1_H_4_TR1/SCB2_SEL2/ADC[1]_25
P14.4 PWM1_52/PWM1_51_N/TC1_52_TR0/TC1_51_TR1/AUDIOSS2_TX_WS/TC1_H_4_TR0/SCB2_SEL1/ADC[1]_24
P14.3 PWM1_51/PWM1_50_N/TC1_51_TR0/TC1_50_TR1/TC0_M_1_TR1/PWM1_H_7_N/SCB2_SEL0/SCB2_CTS/ADC[1]_23
P14.2 PWM1_50/PWM1_49_N/TC1_50_TR0/TC1_49_TR1/TC0_M_1_TR0/PWM1_H_7/SCB2_CLK/SCB2_SCL/SCB2_RTS/ADC[1]_22
P14.1 PWM1_49/PWM1_48_N/TC1_49_TR0/TC1_48_TR1/PWM0_M_1_N/AUDIOSS2_TX_SCK/PWM1_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21
P14.0 PWM1_48/PWM1_47_N/TC1_48_TR0/TC1_47_TR1/PWM0_M_1/AUDIOSS2_MCLK/PWM1_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20
P13.7 PWM1_47/PWM1_M_11_N/TC1_47_TR0/TC1_M_11_TR1/AUDIOSS1_RX_SDI/PWM1_H_5_N/TRIG_IN[23]/ADC[1]_19
P13.6 PWM1_M_11/PWM1_46_N/TC1_M_11_TR0/TC1_46_TR1/AUDIOSS1_RX_WS/PWM1_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18
P13.5 PWM1_46/PWM1_M_10_N/TC1_46_TR0/TC1_M_10_TR1/AUDIOSS1_RX_SCK/PWM1_H_4_N/SCB3_SEL2/ADC[1]_17
P13.4 PWM1_M_10/PWM1_45_N/TC1_M_10_TR0/TC1_45_TR1/AUDIOSS1_CLK_I2S_IF/PWM1_H_4/SCB3_SEL1/ADC[1]_16
P13.3 PWM1_45/PWM1_M_9_N/TC1_45_TR0/TC1_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM1_M_9/PWM1_44_N/TC1_M_9_TR0/TC1_44_TR1/PWM0_2/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM1_44/PWM1_M_8_N/TC1_44_TR0/TC1_M_8_TR1/PWM0_2_N/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 PWM1_M_8/PWM1_43_N/TC1_M_8_TR0/TC1_43_TR1/TC0_2_TR0/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
VSSD
PWM1_12/PWM1_11_N/TC1_12_TR0/TC1_11_TR1/TC0_M_0_TR1/TC1_H_10_TR1 P5.3
PWM1_13/PWM1_12_N/TC1_13_TR0/TC1_12_TR1/PWM1_H_11 P5.4
PWM1_14/PWM1_13_N/TC1_14_TR0/TC1_13_TR1/PWM1_H_11_N P5.5
PWM1_M_0/PWM1_14_N/TC1_M_0_TR0/TC1_14_TR1/PWM0_0/TC1_H_11_TR0/SCB4_RX/SCB4_MISO/ADC[0]_0 P6.0
PWM1_0/PWM1_M_0_N/TC1_0_TR0/TC1_M_0_TR1/TC1_H_11_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ADC[0]_1 P6.1
PWM1_M_1/PWM1_0_N/TC1_M_1_TR0/TC1_0_TR1/PWM0_0_N/SDHC_CARD_MECH_WRITE_PROT/PWM1_H_12/SCB4_RTS/SCB4_SCL/SCB4_CLK/CAN0_2_TX/ADC[0]_2 P6.2
PWM1_1/PWM1_M_1_N/TC1_1_TR0/TC1_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/PWM1_H_12_N/SCB4_CTS/SCB4_SEL0//CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM1_M_2/PWM1_1_N/TC1_M_2_TR0/TC1_1_TR1/TC0_0_TR0/SPIHB_RWDS/SDHC_CLK_CARD/TC1_H_12_TR0/SCB4_SEL1/ADC[0]_4 P6.4
PWM1_2/PWM1_M_2_N/TC1_2_TR0/TC1_M_2_TR1/TC0_0_TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/TC1_H_12_TR1/SCB4_SEL2/ADC[0]_5 P6.5
PWM1_M_3/PWM1_2_N/TC1_M_3_TR0/TC1_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6 P6.6
98
97
96
95
94
93
92
PWM1_3/PWM1_M_3_N/TC1_3_TR0/TC1_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7
91
VDDD
90
VDDIO_1
89
Figure 9-2
176-TEQFP pin assignment with alternate functions (Preliminary)
Datasheet
29
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VSSD
P6.5
P6.2
P31.2 P31.0
P5.0
P4.4
P4.0
P29.5 P29.1 P29.0
P3.1
P3.2
P3.3
P3.4
P3.0
P2.4
P2.5
P2.6
P2.0
P2.1
P2.2
P2.3
P1.1
P1.2
P1.3
P1.4
P1.0
P0.2
VSSD
A
B
C
D
E
F
P6.7
P6.6
P6.3
P6.4
P6.0
P6.1
P31.1
P5.4
P5.5
P5.1
P5.2
P5.3
P30.0
P30.1
P30.2
P4.1
P4.2
P4.3
P29.6 P29.2
P29.7 P29.3
VSSD P29.4
P3.5
P3.6
P3.7
P0.3
P0.1
P0.0
P32.0 P32.1
P28.7 P28.6 P28.5
P28.4 P28.3 P28.2
P32.2 P32.3 P32.4 P32.5
P7.0
P7.2
P7.6
P9.0
P9.2
P7.1
P7.3
P7.7
P9.1
P9.3
P32.6 P32.7
P28.1 P28.0 P23.7 P23.6
P23.5 P23.4 P23.3 P22.3
P23.1 P23.0 P22.7 P22.2
P22.6 P22.5 P22.4 P22.1
VDDIO
_1
VDDIO VDDIO
P7.4
P8.0
P8.3
P7.5
P8.1
P8.4
VCCD P30.3 VDDD
P2.7
VCCD
_1
_1
P8.2
VSSD
VSSD P23.2
VDDD
G
H
J
VDDIO
_3
VSSIO
_3
VSSD VSSD VSSD
VSSD VSSD VSSD
DRV_
VSSD P21.7 P21.6
VOUT
VDDIO
_3
VSSIO
_3
VDDD
P24.0 P24.1
XRES_
P24.2 P24.3 P24.4 P25.0
P25.1 P25.2 P25.3 P25.4
P10.0 P25.5 P25.6 P25.7
P10.1 P10.2 P10.3 P10.4
P10.5 P10.6 P10.7 P11.1
VREFH
VDDA
VREFL VSSD VSSD VSSD
VDDD
P20.7 P20.6 P21.5
L
K
L
VSSD
_1
VSSD
_2
VSSIO VSSIO
_4 _4
VDDD
VSSA
P20.5 P20.4 P21.4
P11.0 VSSD
VCCD P14.5
VSSD P20.3
P20.2 P20.1 P21.2 P21.3
M
N
P
R
T
VDDIO
_2
VDDIO VDDIO
_4 _4
VDDD P16.7 VCCD
P19.4 P20.0 P21.0 P21.1
VSSD
_2
P18.7 P19.3 P19.2
P12.0 P12.1 P12.2 P11.2 VSSD P14.4 P14.7 P26.1 P26.5 P27.1 P27.5 P27.7 P16.5 VSSD P18.6 P18.5 P19.1 P19.0
P12.3 P12.4 P12.5 P13.5 P13.7 P14.3 P14.6 P26.0 P26.4 P27.0 P27.4 P27.6 P16.4 P16.6 P17.4 P18.4 P18.3 P18.2
P12.6 P12.7 P13.2 P13.4 P13.6 P14.2 P15.1 P15.3 P26.3 P26.7 P27.3 P16.1 P16.3 P17.1 P17.3 P17.6 P18.1 P18.0
VSSD P13.0 P13.1 P13.3 P14.0 P14.1 P15.0 P15.2 P26.2 P26.6 P27.2 P16.0 P16.2 P17.0 P17.2 P17.5 P17.7 VSSD
U
V
Figure 9-3
272-BGA ball map
Datasheet
30
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
High-speed I/O matrix connections
10
High-speed I/O matrix connections
Table 10-1
HSIOM connections reference
Name
Number
0
Description
HSIOM_SEL_GPIO
HSIOM_SEL_GPIO_DSI
HSIOM_SEL_DSI_DSI
HSIOM_SEL_DSI_GPIO
HSIOM_SEL_AMUXA
HSIOM_SEL_AMUXB
HSIOM_SEL_AMUXA_DSI
HSIOM_SEL_AMUXB_DSI
HSIOM_SEL_ACT_0
HSIOM_SEL_ACT_1
HSIOM_SEL_ACT_2
HSIOM_SEL_ACT_3
HSIOM_SEL_DS_0
HSIOM_SEL_DS_1
HSIOM_SEL_DS_2
HSIOM_SEL_DS_3
HSIOM_SEL_ACT_4
HSIOM_SEL_ACT_5
HSIOM_SEL_ACT_6
HSIOM_SEL_ACT_7
HSIOM_SEL_ACT_8
HSIOM_SEL_ACT_9
HSIOM_SEL_ACT_10
HSIOM_SEL_ACT_11
HSIOM_SEL_ACT_12
HSIOM_SEL_ACT_13
HSIOM_SEL_ACT_14
HSIOM_SEL_ACT_15
HSIOM_SEL_DS_4
HSIOM_SEL_DS_5
HSIOM_SEL_DS_6
HSIOM_SEL_DS_7
GPIO controls 'out'
Reserved
1
2
3
4
5
6
7
8
Analog multiplexer bus B, DSI control
Active functionality 0
9
Active functionality 1
Active functionality 2
Active functionality 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DeepSleep functionality 0
DeepSleep functionality 1
DeepSleep functionality 2
DeepSleep functionality 3
Active functionality 4
Active functionality 5
Active functionality 6
Active functionality 7
Active functionality 8
Active functionality 9
Active functionality 10
Active functionality 11
Active functionality 12
Active functionality 13
Active functionality 14
Active functionality 15
DeepSleep functionality 4
DeepSleep functionality 5
DeepSleep functionality 6
DeepSleep functionality 7
Datasheet
31
002-33522 Rev. *B
2022-10-21
11
Package pin list and alternate functions
Most pins have alternate functionality, as specified in Table 11-1.
Port 11 has the following additional features,
• Ability to pass full-level analog signals to the SAR without clipping to VDDIO in cases where VDDIO < VDDA
• Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
• Lower noise, for the most sensitive sensors
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
2
DS #1
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
B18
B17
A17
B16
A16
A15
B15
C15
D15
NA
SCB0_MISO
SCB0_MOSI
SCB0_CLK
SCB0_SEL0
SCB0_MISO
SCB0_MOSI
SCB0_CLK
SCB0_SEL0
3
4
SCB0_SCL
SCB0_SDA
SCB0_SCL
SCB0_SDA
5
6
7
8
9
NA
NA
NA
10
11
12
13
14
15
NA
NA
16
NA
A14
B14
C14
D14
B13
C13
D13
F12
A13
SWJ_TRSTN
SCB0_SEL1
SCB0_SEL2
SCB0_SEL3
Notes
17.HCon refers to High Speed I/O matrix connection reference as per Table 10-1.
18.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles the individual alternate function assignment.
19.All port pin functions available in DeepSleep mode are also available in Active mode.
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
A12
B12
C12
D12
B11
C11
D11
A8
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
17
18
19
20
21
NA
NA
24
25
26
27
28
NA
NA
29
30
31
32
33
34
35
36
37
38
39
40
41
42
48
49
50
DS #1
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
B8
C8
D8
A7
NA
NA
A6
B6
C6
D6
C5
D5
B4
ADC[0]_0
ADC[0]_1
ADC[0]_2
ADC[0]_3
ADC[0]_4
ADC[0]_5
ADC[0]_6
ADC[0]_7
ADC[0]_16
ADC[0]_17
ADC[0]_18
C4
A3
B3
C3
A2
B2
B1
E1
E2
F1
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
F2
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
80
81
82
83
84
85
DS #1
P7.3
P7.4
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
ADC[0]_19
ADC[0]_20
ADC[0]_21
ADC[0]_22
ADC[0]_23
F3
P7.5
F4
P7.6
G1
G2
G3
G4
G6
H3
H4
H1
H2
J1
P7.7
P8.0
P8.1
ADC[0]_24
ADC[0]_25
ADC[0]_26
ADC[0]_27
ADC[0]_28
ADC[0]_29
ADC[0]_30
ADC[0]_31
P8.2
P8.3
P8.4
P9.0
P9.1
P9.2
P9.3
J2
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
M1
N1
N2
N3
N4
P1
ADC[1]_0
ADC[1]_1
ADC[1]_2
ADC[1]_3
ADC[0]_M
ADC[1]_M
ADC[2]_M
ADC[1]_4
ADC[1]_5
ADC[1]_6
ADC[1]_7
ADC[1]_8
ADC[1]_9
P2
P3
M6
P4
R4
R1
SMARTIO12_0
SMARTIO12_1
SMARTIO12_2
SMARTIO12_3
SMARTIO12_4
SMARTIO12_5
R2
R3
T1
T2
T3
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
U1
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
86
DS #1
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P14.0
P14.1
P14.2
P14.3
P14.4
P14.5
P14.6
P14.7
P15.0
P15.1
P15.2
P15.3
P16.0
P16.1
P16.2
P16.3
P16.4
P16.5
P16.6
P16.7
P17.0
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
ADC[1]_10
ADC[1]_11
ADC[1]_12
ADC[1]_13
ADC[1]_14
ADC[1]_15
ADC[1]_16
ADC[1]_17
ADC[1]_18
ADC[1]_19
ADC[1]_20
ADC[1]_21
ADC[1]_22
ADC[1]_23
ADC[1]_24
ADC[1]_25
ADC[1]_26
ADC[1]_27
ADC[1]_28
ADC[1]_29
ADC[1]_30
ADC[1]_31
ADC[2]_0
ADC[2]_1
ADC[2]_2
ADC[2]_3
ADC[2]_4
ADC[2]_5
ADC[2]_6
ADC[2]_7
ADC[2]_8
SMARTIO12_6
SMARTIO12_7
SMARTIO13_0
SMARTIO13_1
SMARTIO13_2
SMARTIO13_3
SMARTIO13_4
SMARTIO13_5
SMARTIO13_6
SMARTIO13_7
SMARTIO14_0
SMARTIO14_1
SMARTIO14_2
SMARTIO14_3
SMARTIO14_4
SMARTIO14_5
SMARTIO14_6
SMARTIO14_7
SMARTIO15_0
SMARTIO15_1
SMARTIO15_2
SMARTIO15_3
U2
87
V2
90
V3
91
U3
92
V4
93
U4
94
T4
95
U5
96
T5
97
V5
98
V6
99
U6
100
101
102
103
104
105
106
107
108
109
NA
NA
NA
115
NA
NA
NA
NA
116
T6
R6
N7
T7
R7
V7
U7
V8
U8
V12
U12
V13
U13
T13
R13
T14
N12
V14
SMARTIO17_0
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
DS #1
P17.1
P17.2
P17.3
P17.4
P17.5
P17.6
P17.7
P18.0
P18.1
P18.2
P18.3
P18.4
P18.5
P18.6
P18.7
P19.0
P19.1
P19.2
P19.3
P19.4
P20.0
P20.1
P20.2
P20.3
P20.4
P20.5
P20.6
P20.7
P21.0
P21.1
P21.2
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
U14
V15
U15
T15
V16
U16
V17
U18
U17
T18
T17
T16
R16
R15
P15
R18
R17
P17
P16
N15
N16
M16
M15
M13
L16
ADC[2]_9
ADC[2]_10
ADC[2]_11
ADC[2]_12
ADC[2]_13
ADC[2]_14
ADC[2]_15
ADC[2]_16
ADC[2]_17
ADC[2]_18
ADC[2]_19
ADC[2]_20
ADC[2]_21
ADC[2]_22
ADC[2]_23
ADC[2]_24
ADC[2]_25
ADC[2]_26
ADC[2]_27
ADC[2]_28
ADC[2]_29
ADC[2]_30
ADC[2]_31
SMARTIO17_1
SMARTIO17_2
SMARTIO17_3
SMARTIO17_4
SMARTIO17_5
SMARTIO17_6
SMARTIO17_7
L15
K16
K15
N17
N18
M17
WCO_IN[20]
WCO_OUT[20]
ECO_IN[20]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
150
151
DS #1
P21.3
P21.4
GPIO_STD
GPIO_STD
M18
ECO_OUT[20]
HIBER-
L17
NATE_WAKEUP[0][2
1]
P21.5
P21.6
P21.7
P22.1
P22.2
P22.3
P22.4
P22.5
P22.6
P22.7
P23.0
P23.1
P23.2
P23.3
P23.4
P23.5
P23.6
P23.7
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
K17
J17
J16
H18
G18
F18
H17
H16
H15
G17
G16
G15
G13
F17
F16
F15
E18
E17
157
158
159
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
RTC_CAL
EXT_PS_CTL0
EXT_PS_CTL1
EXT_PS_CTL2
SWJ_SWO_TDO
SWJ_SWCLK_TCLK
SWJ_SWDIO_TMS
SWJ_SWDOE_TDI
HIBER-
NATE_WAKEUP[1]
P24.0
P24.1
P24.2
P24.3
P24.4
P25.0
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
J3
J4
K1
K2
K3
K4
NA
NA
NA
NA
NA
NA
Notes
20.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.
21.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
L1
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
DS #1
P25.1
P25.2
P25.3
P25.4
P25.5
P25.6
P25.7
P26.0
P26.1
P26.2
P26.3
P26.4
P26.5
P26.6
P26.7
P27.0
P27.1
P27.2
P27.3
P27.4
P27.5
P27.6
P27.7
P28.0
P28.1
P28.2
P28.3
P28.4
P28.5
P28.6
P28.7
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
L2
L3
L4
M2
M3
M4
T8
R8
V9
U9
T9
R9
V10
U10
T10
R10
V11
U11
T11
R11
T12
R12
E16
E15
D18
D17
D16
C18
C17
C16
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, analog, smart I/O (continued)
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
272-BGA
Pin
A11
A10
B10
C10
D10
A9
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
DS #1
P29.0
P29.1
P29.2
P29.3
P29.4
P29.5
P29.6
P29.7
P30.0
P30.1
P30.2
P30.3
P31.0
P31.1
P31.2
P32.0
P32.1
P32.2
P32.3
P32.4
P32.5
P32.6
P32.7
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
B9
C9
B7
C7
D7
F7
A5
B5
A4
C1
ADC[0]_8
ADC[0]_9
C2
D1
ADC[0]_10
ADC[0]_11
ADC[0]_12
ADC[0]_13
ADC[0]_14
ADC[0]_15
D2
D3
D4
E3
E4
12
Power pin assignments
Table 12-1
Pin Name
VDDD
Power pin assignments[22]
Package
272-BGA
Remarks
176-TEQFP
176, 153, 132, 110, 43, 22
F8, H13, J13, K13, L13, N11
Main digital supply
Main digital ground
A1, A18, D9, G7, G12, H9, H10, H11, J9, J10, J11, 155, 154, 133, 114, 89, 45, 23, 1
J15, K9, K10, K11, M7, M12, R5, R14, V1, V18
VSSD
VSSD_1
VSSD_2
VDDIO_1
L11
NA
NA
44
Digital Ground
L18, P18
F9, F10, F11
Noise guard for ECO inputs
I/O supply (except analog I/Os on VDDA
I/O supply (except analog I/Os on VDDA
)
)
N8
88
VDDIO_2
VDDIO_3
VDDIO_4
VSSIO_3
VSSIO_4
H6, J6
NA
I/O supply for high speed domain#0 (HSIO_STD), P24, P25
I/O supply for high speed domain#1 (HSIO_STD), P26, P27
HSIO ground
N9, N10
NA
H8, J8
NA
L9, L10
NA
HSIO ground
F6, F13, N6, N13
46, 47, 111, 112, 113, 156
Main regulated supply. Driven by LDO regulator (either internal LDO or external
LDO/PMIC)
VCCD[22]
VREFH
VREFL
VDDA
K6
K8
L6
79
High reference voltage for SAR ADCs
Low reference voltage for SAR ADCs
Main analog supply for SAR ADCs
Main analog ground
76
78
VSSA
L8
77
XRES_L
K18
152
160
Active LOW external reset input
Dedicated external supply control pin
DRV_VOUT J18
Note
22.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 26.3).
13
Table 13-1
Alternate function pin assignments
Alternate pin functions in Active mode [19, 25]
Active Mapping
Pin
[23]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
HCon#18
HCon#19
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[24]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #5
ACT #6
ACT #7
ACT #10
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P1.4
P2.0
P2.1
P2.2
P2.3
PWM1_18
PWM1_17
PWM1_14
PWM1_13
PWM1_12
PWM1_11
PWM1_10
PWM1_8
PWM1_71
PWM1_7
PWM1_6
PWM1_5
PWM1_4
PWM1_22_N
TC1_18_TR0
TC1_22_TR1
SCB0_RX
SCB7_SDA
PWM0_H_0
PWM1_18_N
PWM1_17_N
PWM1_14_N
PWM1_13_N
PWM1_12_N
PWM1_11_N
PWM1_10_N
PWM1_70_N
PWM1_8_N
PWM1_7_N
PWM1_6_N
PWM1_5_N
TC1_17_TR0
TC1_14_TR0
TC1_13_TR0
TC1_12_TR0
TC1_11_TR0
TC1_10_TR0
TC1_8_TR0
TC1_71_TR0
TC1_7_TR0
TC1_6_TR0
TC1_5_TR0
TC1_4_TR0
TC1_18_TR1
TC1_17_TR1
TC1_14_TR1
TC1_13_TR1
TC1_12_TR1
TC1_11_TR1
TC1_10_TR1
TC1_70_TR1
TC1_8_TR1
TC1_7_TR1
TC1_6_TR1
TC1_5_TR1
SCB0_TX
SCB7_SCL
PWM0_H_0_N
TC0_H_0_TR0
TC0_H_0_TR1
SCB0_RTS
SCB0_CTS
SCB4_MISO
SCB4_MOSI
SCB4_CLK
SCB4_MISO
CAN0_1_TX
CAN0_1_RX
PWM1_H_4
PWM1_H_5
PWM1_H_6
PWM1_H_7
TRIG_IN[0]
TRIG_IN[1]
SCB8_RX
SCB7_RX
SCB7_TX
SCB7_RTS
SCB7_CTS
SCB8_MISO
SCB7_MISO
SCB7_MOSI
SCB7_CLK
SCB7_SEL0
TC1_H_4_TR0
TC1_H_5_TR0
TC1_H_6_TR0
TC1_H_7_TR0
CAN0_0_TX
CAN0_0_RX
TRIG_IN[2]
TRIG_IN[3]
TRIG_IN[4]
TRIG_IN[5]
SCB7_SDA
SCB7_SCL
ETH0_RX_ER
ETH0_ETH_TSU_TIM-
ER_CMP_VAL
P2.4
P2.5
P2.6
P2.7
P3.0
PWM1_3
PWM1_2
PWM1_72
PWM1_73
PWM1_1
PWM1_4_N
PWM1_3_N
PWM1_71_N
PWM1_72_N
PWM1_2_N
TC1_3_TR0
TC1_2_TR0
TC1_72_TR0
TC1_73_TR0
TC1_1_TR0
TC1_4_TR1
TC1_3_TR1
TC1_71_TR1
TC1_72_TR1
TC1_2_TR1
PWM1_H_4_N
PWM1_H_5_N
SCB7_SEL1
SCB7_SEL2
SCB8_SEL0
SCB8_SEL1
SCB6_MISO
TRIG_IN[6]
TRIG_IN[7]
SCB8_CTS
PWM1_H_6_N
PWM1_H_7_N
SCB6_RX
SCB6_TX
CAN0_3_TX
CAN0_3_RX
ETH0_MDIO
ETH0_MDC
TRIG_DBG[
0]
P3.1
PWM1_0
PWM1_1_N
TC1_0_TR0
TC1_1_TR1
SCB6_SDA
SCB6_SCL
SCB6_MOSI
TRIG_DBG[
1]
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PWM1_M_3 PWM1_0_N
TC1_M_3_TR0
TC1_0_TR1
TC1_H_4_TR1
TC1_H_5_TR1
TC1_H_6_TR1
TC1_H_7_TR1
SCB6_RTS
SCB6_CTS
SCB6_CLK
SCB6_SEL0
SCB6_SEL1
SCB6_SEL2
SCB8_SEL2
PWM1_M_2 PWM1_M_3_N TC1_M_2_TR0
PWM1_M_1 PWM1_M_2_N TC1_M_1_TR0
PWM1_M_0 PWM1_M_1_N TC1_M_0_TR0
TC1_M_3_TR1
TC1_M_2_TR1
TC1_M_1_TR1
TC1_73_TR1
TC1_74_TR1
PWM1_74
PWM1_75
PWM1_73_N
PWM1_74_N
TC1_74_TR0
TC1_75_TR0
CAN1_2_TX
CAN1_2_RX
Notes
23.High Speed I/O matrix connection (HCon) reference as per Table 10-1.
24.Active Mode ordering (ACT #0, ACT #1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.
25.Refer to Table 13-2 for more information on pin multiplexer abbreviations used.
26.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
HCon#16
HCon#17
HCon#18
HCon#19
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
HCon#27
ACT #15
[24]
Name ACT #0
ACT #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #14
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
PWM1_4
PWM1_5
PWM1_6
PWM1_7
PWM1_8
PWM1_9
PWM1_10
PWM1_11
PWM1_12
PWM1_13
PWM1_14
PWM1_M_0_N TC1_4_TR0
TC1_M_0_TR1
EXT_MUX[0]_0
SCB5_RX
SCB5_MISO
TRIG_IN[10]
PWM1_4_N
PWM1_5_N
PWM1_6_N
PWM1_7_N
PWM1_8_N
PWM1_9_N
PWM1_10_N
PWM1_11_N
PWM1_12_N
PWM1_13_N
TC1_5_TR0
TC1_6_TR0
TC1_7_TR0
TC1_8_TR0
TC1_9_TR0
TC1_10_TR0
TC1_11_TR0
TC1_12_TR0
TC1_13_TR0
TC1_14_TR0
TC1_M_0_TR0
TC1_4_TR1
TC1_5_TR1
TC1_6_TR1
TC1_7_TR1
TC1_8_TR1
TC1_9_TR1
TC1_10_TR1
TC1_11_TR1
TC1_12_TR1
TC1_13_TR1
TC1_14_TR1
TC1_M_0_TR1
TC1_0_TR1
EXT_MUX[0]_1
EXT_MUX[0]_2
SCB5_TX
SCB5_SDA
SCB5_SCL
SCB5_MOSI
SCB5_CLK
SCB5_SEL0
SCB5_SEL1
SCB5_SEL2
SCB9_SEL3
TRIG_IN[11]
TRIG_IN[12]
TRIG_IN[13]
SCB5_RTS
EXT_MUX[0]_EN SCB5_CTS
CAN0_1_TX
CAN0_1_RX
PWM1_H_10
PWM0_M_0
TRIG_IN[38]
TRIG_IN[39]
PWM1_H_10_N
TC1_H_10_TR0
TC1_H_10_TR1
PWM1_H_11
PWM0_M_0_N
TC0_M_0_TR0
TC0_M_0_TR1
PWM1_H_11_N
PWM1_M_0 PWM1_14_N
PWM1_0 PWM1_M_0_N TC1_0_TR0
PWM1_M_1 PWM1_0_N TC1_M_1_TR0
TC1_H_11_TR0
TC1_H_11_TR1
PWM1_H_12
SCB4_RX
SCB4_TX
SCB4_RTS
SCB4_MISO
SCB4_MOSI
SCB4_CLK
PWM0_0
SCB4_SDA
SCB4_SCL
CAN0_2_TX
CAN0_2_RX
PWM0_0_N
SDHC_CARD_-
MECH_WRITE_PR
OT
P6.3
P6.4
P6.5
PWM1_1
PWM1_M_2 PWM1_1_N
PWM1_2 PWM1_M_2_N TC1_2_TR0
PWM1_M_3 PWM1_2_N TC1_M_3_TR0
PWM1_3 PWM1_M_3_N TC1_3_TR0
PWM1_M_4 PWM1_3_N TC1_M_4_TR0
PWM1_M_1_N TC1_1_TR0
TC1_M_1_TR1
TC1_1_TR1
PWM1_H_12_N
TC1_H_12_TR0
TC1_H_12_TR1
SCB4_CTS
SCB4_SEL0
SCB4_SEL1
SCB4_SEL2
SCB4_SEL3
SPIHB_CLK
SDHC_-
CAL_SUP_
NZ
CARD_CMD
TC1_M_2_TR0
TC0_0_TR0
TC0_0_TR1
SPIHB_RWD
S
SDHC_CLK_CARD
TC1_M_2_TR1
SPIHB_SEL0
SDHC_CARD_DE-
TECT_N
P6.6
P6.7
P7.0
TC1_2_TR1
TC1_M_3_TR1
TC1_3_TR1
TRIG_IN[8]
TRIG_IN[9]
SCB5_RX
SCB5_MISO
PWM0_1
SPIHB_SEL1
SDHC_-
CARD_IF_P-
WR_EN
P7.1
P7.2
P7.3
P7.4
P7.5
PWM1_15
PWM1_M_5 PWM1_15_N
PWM1_16 PWM1_M_5_N TC1_16_TR0
PWM1_M_6 PWM1_16_N TC1_M_6_TR0
PWM1_17 PWM1_M_6_N TC1_17_TR0
PWM1_M_7 PWM1_17_N TC1_M_7_TR0
PWM1_M_7_N TC1_18_TR0
PWM1_18_N TC1_19_TR0
PWM1_M_4_N TC1_15_TR0
TC1_M_4_TR1
TC1_15_TR1
TC1_M_5_TR1
TC1_16_TR1
TC1_M_6_TR1
SCB5_TX
SCB5_SDA
SCB5_SCL
SCB5_MOSI
SCB5_CLK
SCB5_SEL0
SCB5_SEL1
SCB5_SEL2
SPIHB_-
DATA0
SDHC_CARD_-
DAT_3TO0_0
TC1_M_5_TR0
SCB5_RTS
SCB5_CTS
PWM0_1_N
TC0_1_TR0
TC0_1_TR1
PWM0_H_2
SPIHB_-
DATA1
SDHC_CARD_-
DAT_3TO0_1
CAN0_4_TX
CAN0_4_RX
SPIHB_-
DATA2
SDHC_CARD_-
DAT_3TO0_2
SPIHB_-
DATA3
SDHC_CARD_-
DAT_3TO0_3
SPIHB_-
DATA4
SDHC_CARD_-
DAT_7TO4_0
P7.6
P7.7
P8.0
TC1_17_TR1
TC1_M_7_TR1
TC1_18_TR1
TRIG_IN[16]
TRIG_IN[17]
PWM1_18
PWM1_19
PWM1_H_8
CAN0_0_TX
PWM0_H_2_N
SPIHB_-
DATA5
SDHC_CARD_-
DAT_7TO4_1
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
HCon#17
ACT #5
HCon#18
HCon#19
HCon#20
ACT #8
HCon#21
HCon#22
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
HCon#27
ACT #15
[24]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #4
ACT #6
ACT #7
ACT #9
ACT #10
ACT #14
P8.1
P8.2
P8.3
P8.4
PWM1_20
PWM1_21
PWM1_22
PWM1_23
PWM1_19_N
TC1_20_TR0
TC1_19_TR1
PWM1_H_8_N
CAN0_0_RX
TC0_H_2_TR0
SPIHB_-
DATA6
SDHC_CARD_-
DAT_7TO4_2
TRIG_IN[14]
PWM1_20_N
PWM1_21_N
PWM1_22_N
TC1_21_TR0
TC1_22_TR0
TC1_23_TR0
TC1_20_TR1
TC1_21_TR1
TC1_22_TR1
TC1_H_8_TR0
TC1_H_8_TR1
TC0_H_2_TR1
SPIHB_-
DATA7
SDHC_CARD_-
DAT_7TO4_3
TRIG_IN[15]
TRIG_DBG[
0]
TRIG_DBG[
1]
P9.0
P9.1
P9.2
P9.3
PWM1_24
PWM1_25
PWM1_26
PWM1_27
PWM1_23_N
PWM1_24_N
PWM1_25_N
PWM1_26_N
PWM1_27_N
PWM1_28_N
PWM1_29_N
PWM1_30_N
PWM1_31_N
PWM1_32_N
PWM1_33_N
PWM1_34_N
PWM1_62_N
PWM1_61_N
TC1_24_TR0
TC1_25_TR0
TC1_26_TR0
TC1_27_TR0
TC1_28_TR0
TC1_29_TR0
TC1_30_TR0
TC1_31_TR0
TC1_32_TR0
TC1_33_TR0
TC1_23_TR1
TC1_24_TR1
TC1_25_TR1
TC1_26_TR1
TC1_27_TR1
TC1_28_TR1
TC1_29_TR1
TC1_30_TR1
TC1_31_TR1
TC1_32_TR1
TC1_33_TR1
TC1_34_TR1
TC1_62_TR1
TC1_61_TR1
PWM1_H_9
PWM1_H_9_N
TC1_H_9_TR0
TC1_H_9_TR1
PWM1_H_10
P10.0 PWM1_28
P10.1 PWM1_29
P10.2 PWM1_30
P10.3 PWM1_31
P10.4 PWM1_32
P10.5 PWM1_33
P10.6
SCB4_RX
SCB4_TX
SCB4_RTS
SCB4_CTS
SCB4_MISO
SCB4_MOSI
SCB4_CLK
TRIG_IN[18]
TRIG_IN[19]
PWM1_H_10_N
TC1_H_10_TR0
TC1_H_10_TR1
PWM1_H_11
SCB4_SDA
SCB4_SCL
SCB4_SEL0
SCB4_SEL1
SCB4_SEL2
TC1_34_TR0
PWM1_H_11_N
TC1_H_11_TR0
TC1_H_11_TR1
PWM1_34
P10.7 PWM1_35
P11.0 PWM1_61
P11.1 PWM1_60
TC1_35_TR0
TC1_61_TR0
TC1_60_TR0
AUDIOSS0_MCLK
AUDIOSS0_TX_SC
K
P11.2 PWM1_59
P12.0 PWM1_36
P12.1 PWM1_37
P12.2 PWM1_38
P12.3 PWM1_39
P12.4 PWM1_40
PWM1_60_N
TC1_59_TR0
TC1_36_TR0
TC1_37_TR0
TC1_38_TR0
TC1_39_TR0
TC1_40_TR0
TC1_60_TR1
AUDIOSS0_TX_W
S
SCB8_RX
SCB8_TX
TC1_35_TR SCB8_MISO
1
CAN0_2_TX
CAN0_2_RX
PWM0_H_1
PWM1_35_
N
AUDIOSS0_TX_SD TRIG_IN[20]
O
PWM1_36_N
PWM1_37_N
PWM1_38_N
PWM1_39_N
TC1_36_TR1
TC1_37_TR1
TC1_38_TR1
TC1_39_TR1
SCB8_SDA
SCB8_MOSI
SCB8_CLK
SCB8_SEL0
SCB8_SEL1
PWM0_H_1_N
TC0_H_1_TR0
TC0_H_1_TR1
TC0_2_TR1
AUDIOSS0_-
CLK_I2S_IF
TRIG_IN[21]
EXT_MUX[1]_EN SCB8_RTS
SCB8_SCL
AUDIOSS0_RX_SC
K
EXT_MUX[1]_0
EXT_MUX[1]_1
EXT_MUX[1]_2
SCB8_CTS
AUDIOSS0_RX_W
S
CAN1_1_TX
CAN1_1_RX
AUDIOSS0_RX_SD
I
P12.5 PWM1_41
P12.6 PWM1_42
P12.7 PWM1_43
PWM1_40_N
PWM1_41_N
PWM1_42_N
TC1_41_TR0
TC1_42_TR0
TC1_43_TR0
TC1_M_8_TR0
TC1_40_TR1
TC1_41_TR1
TC1_42_TR1
TC1_43_TR1
P13.0 PWM1_M_8 PWM1_43_N
EXT_MUX[2]_0
SCB3_RX
SCB3_MISO
TC0_2_TR0
AUDIOSS1_MCLK
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
HCon#16
HCon#17
HCon#18
HCon#19
HCon#20
ACT #8
HCon#21
HCon#22
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[24]
Name ACT #0
ACT #3
ACT #4
ACT #5
ACT #6
ACT #7
ACT #9
ACT #10
P13.1 PWM1_44
PWM1_M_8_N TC1_44_TR0
TC1_M_9_TR0
PWM1_M_9_N TC1_45_TR0
TC1_M_8_TR1
EXT_MUX[2]_1
SCB3_TX
SCB3_SDA
SCB3_MOSI
PWM0_2_N
AUDIOSS1_TX_SC
K
P13.2 PWM1_M_9 PWM1_44_N
TC1_44_TR1
EXT_MUX[2]_2
SCB3_RTS
SCB3_SCL
SCB3_CLK
SCB3_SEL0
SCB3_SEL1
SCB3_SEL2
SCB3_SEL3
PWM0_2
AUDIOSS1_TX_W
S
P13.3 PWM1_45
TC1_M_9_TR1
EXT_MUX[2]_EN SCB3_CTS
PWM1_H_4
AUDIOSS1_TX_SD
O
P13.4 PWM1_M_1 PWM1_45_N
0
TC1_M_10_TR0 TC1_45_TR1
TC1_M_11_TR0 TC1_46_TR1
AUDIOSS1_-
CLK_I2S_IF
P13.5 PWM1_46
PWM1_M_10_ TC1_46_TR0
TC1_M_10_TR1 PWM1_H_4_N
AUDIOSS1_RX_SC
K
N
P13.6 PWM1_M_1 PWM1_46_N
1
PWM1_H_5
AUDIOSS1_RX_W TRIG_IN[22]
S
P13.7 PWM1_47
PWM1_M_11_ TC1_47_TR0
TC1_M_11_TR1 PWM1_H_5_N
AUDIOSS1_RX_SD TRIG_IN[23]
I
N
P14.0 PWM1_48
P14.1 PWM1_49
PWM1_47_N
TC1_48_TR0
TC1_49_TR0
TC1_47_TR1
TC1_48_TR1
PWM1_H_6
SCB2_MISO
SCB2_MOSI SCB2_SDA
SCB2_RX
SCB2_TX
CAN1_0_TX
CAN1_0_RX
PWM0_M_1
AUDIOSS2_MCLK
PWM1_48_N
PWM1_H_6_N
PWM0_M_1_N
AUDIOSS2_TX_SC
K
P14.2 PWM1_50
P14.3 PWM1_51
P14.4 PWM1_52
PWM1_49_N
PWM1_50_N
PWM1_51_N
TC1_50_TR0
TC1_51_TR0
TC1_52_TR0
TC1_49_TR1
TC1_50_TR1
TC1_51_TR1
PWM1_H_7
SCB2_CLK
SCB2_SEL0
SCB2_SEL1
SCB2_SCL
SCB2_RTS
SCB2_CTS
TC0_M_1_TR0
TC0_M_1_TR1
PWM1_H_7_N
TC1_H_4_TR0
AUDIOSS2_TX_W
S
P14.5 PWM1_53
PWM1_52_N
TC1_53_TR0
TC1_52_TR1
TC1_H_4_TR1
SCB2_SEL2
AUDIOSS2_TX_SD
O
P14.6 PWM1_54
P14.7 PWM1_55
P15.0 PWM1_56
PWM1_53_N
PWM1_54_N
PWM1_55_N
TC1_54_TR0
TC1_55_TR0
TC1_56_TR0
TC1_53_TR1
TC1_54_TR1
TC1_55_TR1
TC1_H_5_TR0
TC1_H_5_TR1
TC1_H_6_TR0
TRIG_IN[24]
TRIG_IN[25]
SCB9_RX
SCB9_TX
SCB9_RTS
SCB9_CTS
SCB9_MISO
SCB9_MOSI
SCB9_CLK
SCB9_SEL0
CAN1_3_TX
CAN1_3_RX
AUDIOSS2_-
CLK_I2S_IF
P15.1 PWM1_57
P15.2 PWM1_58
P15.3 PWM1_59
PWM1_56_N
PWM1_57_N
PWM1_58_N
TC1_57_TR0
TC1_58_TR0
TC1_59_TR0
TC1_56_TR1
TC1_57_TR1
TC1_58_TR1
TC1_H_6_TR1
TC1_H_7_TR0
TC1_H_7_TR1
SCB9_SDA
SCB9_SCL
AUDIOSS2_RX_SC
K
AUDIOSS2_RX_W
S
AUDIOSS2_RX_SD
I
P16.0 PWM1_60
P16.1 PWM1_61
P16.2 PWM1_62
P16.3 PWM1_62
P16.4 PWM1_68
P16.5 PWM1_67
P16.6 PWM1_66
P16.7 PWM1_65
P17.0 PWM1_61
PWM1_59_N
PWM1_60_N
PWM1_61_N
PWM1_62_N
PWM1_69_N
PWM1_68_N
PWM1_67_N
PWM1_66_N
PWM1_62_N
TC1_60_TR0
TC1_61_TR0
TC1_62_TR0
TC1_62_TR0
TC1_68_TR0
TC1_67_TR0
TC1_66_TR0
TC1_65_TR0
TC1_61_TR0
TC1_59_TR1
TC1_60_TR1
TC1_61_TR1
TC1_62_TR1
TC1_69_TR1
TC1_68_TR1
TC1_67_TR1
TC1_66_TR1
TC1_62_TR1
PWM1_H_0
SCB9_SEL1
SCB9_SEL2
SCB9_SEL3
PWM1_H_0_N
PWM1_H_1
PWM1_H_1_N
CAN1_1_TX
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
HCon#18
HCon#19
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[24]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #5
ACT #6
ACT #7
ACT #9
P17.1 PWM1_60
PWM1_61_N
TC1_60_TR0
TC1_61_TR1
SCB3_RX
CAN1_1_RX
P17.2 PWM1_59
P17.3 PWM1_58
P17.4 PWM1_57
P17.5 PWM1_56
PWM1_60_N
PWM1_59_N
PWM1_58_N
PWM1_57_N
TC1_59_TR0
TC1_58_TR0
TC1_57_TR0
TC1_56_TR0
TC1_M_4_TR0
TC1_60_TR1
TC1_59_TR1
TC1_58_TR1
TC1_57_TR1
TC1_56_TR1
TC1_M_4_TR1
TC1_M_5_TR1
SCB3_TX
SCB3_RTS
SCB3_CTS
SCB3_SDA
SCB3_SCL
PWM1_H_3
SCB3_CLK
SCB3_SEL0
SCB3_SEL1
SCB3_SEL2
TRIG_IN[26]
TRIG_IN[27]
PWM1_H_3_N
PWM1_H_2
P17.6 PWM1_M_4 PWM1_56_N
PWM1_H_2_N
P17.7 PWM1_M_5 PWM1_M_4_N TC1_M_5_TR0
P18.0 PWM1_M_6 PWM1_M_5_N TC1_M_6_TR0
PWM1_H_0
SCB1_RX
SCB1_TX
SCB1_MISO
SCB1_MOSI
ETH0_REF_CLK
ETH0_TX_CTL
FAULT_OU
T_0
P18.1 PWM1_M_7 PWM1_M_6_N TC1_M_7_TR0
TC1_M_6_TR1
PWM1_H_0_N
SCB1_SDA
SCB1_SCL
SCB3_MISO
FAULT_OU
T_1
P18.2 PWM1_55
P18.3 PWM1_54
PWM1_M_7_N TC1_55_TR0
TC1_M_7_TR1
TC1_55_TR1
PWM1_H_1
SCB1_RTS
SCB1_CTS
SCB1_CLK
SCB1_SEL0
SCB3_MOSI
SCB3_CLK
ETH0_TX_ER
ETH0_TX_CLK
PWM1_55_N
PWM1_54_N
PWM1_53_N
PWM1_52_N
PWM1_51_N
TC1_54_TR0
TC1_53_TR0
TC1_52_TR0
TC1_51_TR0
TC1_50_TR0
TC1_M_3_TR0
PWM1_H_1_N
TRACE_-
CLOCK
P18.4 PWM1_53
P18.5 PWM1_52
P18.6 PWM1_51
P18.7 PWM1_50
TC1_54_TR1
TC1_53_TR1
TC1_52_TR1
TC1_51_TR1
TC1_50_TR1
TC1_M_3_TR1
PWM1_H_2
SCB1_SEL1
SCB1_SEL2
SCB1_SEL3
SCB3_SEL0
PWM0_M_2
ETH0_TXD_0
ETH0_TXD_1
ETH0_TXD_2
ETH0_TXD_3
ETH0_RXD_0
ETH0_RXD_1
TRACE_-
DATA_0
PWM1_H_2_N
PWM1_H_3
PWM0_M_2_N
TC0_M_2_TR0
TC0_M_2_TR1
TRACE_-
DATA_1
CAN1_2_TX
CAN1_2_RX
CAN1_3_TX
CAN1_3_RX
TRACE_-
DATA_2
PWM1_H_3_N
TC1_H_0_TR0
TC1_H_0_TR1
TRACE_-
DATA_3
P19.0 PWM1_M_3 PWM1_50_N
SCB2_MISO
SCB2_RX
SCB2_TX
FAULT_OU
T_2
P19.1 PWM1_26
PWM1_M_3_N TC1_26_TR0
SCB2_MOSI SCB2_SDA
FAULT_OU
T_3
P19.2 PWM1_27
P19.3 PWM1_28
P19.4 PWM1_29
P20.0 PWM1_30
P20.1 PWM1_49
P20.2 PWM1_48
P20.3 PWM1_47
P20.4 PWM1_46
P20.5 PWM1_45
P20.6 PWM1_44
P20.7 PWM1_43
P21.0 PWM1_42
PWM1_26_N
PWM1_27_N
PWM1_28_N
PWM1_29_N
PWM1_30_N
PWM1_49_N
PWM1_48_N
PWM1_47_N
PWM1_46_N
PWM1_45_N
PWM1_44_N
PWM1_43_N
TC1_27_TR0
TC1_28_TR0
TC1_29_TR0
TC1_30_TR0
TC1_49_TR0
TC1_48_TR0
TC1_47_TR0
TC1_46_TR0
TC1_45_TR0
TC1_44_TR0
TC1_43_TR0
TC1_42_TR0
TC1_26_TR1
TC1_27_TR1
TC1_28_TR1
TC1_29_TR1
TC1_30_TR1
TC1_49_TR1
TC1_48_TR1
TC1_47_TR1
TC1_46_TR1
TC1_45_TR1
TC1_44_TR1
TC1_43_TR1
TC1_H_1_TR0
TC1_H_1_TR1
TC1_H_2_TR0
TC1_H_2_TR1
TC1_H_3_TR0
TC1_H_3_TR1
SCB2_CLK
SCB2_SEL0
SCB2_SEL1
SCB2_SEL2
SCB2_SCL
SCB2_RTS
SCB2_CTS
ETH0_RXD_2
ETH0_RXD_3
TRIG_IN[28]
TRIG_IN[29]
SCB1_RX
SCB1_TX
SCB1_RTS
SCB1_CTS
SCB1_MISO
SCB1_MOSI
SCB1_CLK
SCB1_SEL0
SCB1_SEL1
SCB1_SEL2
CAN1_2_TX
CAN1_2_RX
SCB1_SDA
SCB1_SCL
CAN1_4_TX
CAN1_4_RX
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[24]
Name ACT #0
ACT #1
ACT #2
ACT #3
P21.1 PWM1_41
PWM1_42_N
TC1_41_TR0
TC1_42_TR1
P21.2 PWM1_40
PWM1_41_N
TC1_40_TR0
TC1_41_TR1
EXT_CLK
TRIG_DBG[
1]
P21.3 PWM1_39
P21.4 PWM1_38
P21.5 PWM1_37
PWM1_40_N
PWM1_39_N
PWM1_38_N
TC1_39_TR0
TC1_38_TR0
TC1_37_TR0
TC1_40_TR1
TC1_39_TR1
TC1_38_TR1
TC1_35_TR TC1_34_TR0
1
CAN1_1_TX
CAN1_1_RX
PWM1_34
PWM1_35_ ETH0_RX_CTL
N
TRACE_-
DATA_0
P21.6 PWM1_36
P21.7 PWM1_35
PWM1_37_N
PWM1_36_N
TC1_36_TR0
TC1_35_TR0
TC1_37_TR1
TC1_36_TR1
SCB6_RX
SCB6_TX
SCB6_RTS
SCB6_CTS
SCB6_MISO
CAL_SUP_
NZ
P22.1 PWM1_33
P22.2 PWM1_32
P22.3 PWM1_31
P22.4 PWM1_30
PWM1_34_N
PWM1_33_N
PWM1_32_N
PWM1_31_N
TC1_33_TR0
TC1_32_TR0
TC1_31_TR0
TC1_30_TR0
TC1_34_TR1
TC1_33_TR1
TC1_32_TR1
TC1_31_TR1
SCB6_SDA
SCB6_SCL
SCB6_MOSI
SCB6_CLK
SCB6_SEL0
SCB6_SEL1
SCB6_SEL2
TRACE_-
DATA_1
TRACE_-
DATA_2
TRACE_-
DATA_3
TRACE_-
CLOCK
P22.5 PWM1_29
P22.6 PWM1_28
P22.7 PWM1_27
PWM1_30_N
PWM1_29_N
PWM1_28_N
TC1_29_TR0
TC1_28_TR0
TC1_27_TR0
TC1_M_8_TR0
TC1_30_TR1
TC1_29_TR1
TC1_28_TR1
TC1_27_TR1
PWM1_H_8
PWM1_H_8_N
TC1_H_8_TR0
TC1_H_8_TR1
P23.0 PWM1_M_8 PWM1_27_N
SCB7_RX
SCB7_MISO
SCB7_MOSI
SCB7_CLK
SCB7_SEL0
SCB7_SEL1
SCB7_SEL2
CAN1_0_TX
CAN1_0_RX
FAULT_OU
T_0
P23.1 PWM1_M_9 PWM1_M_8_N TC1_M_9_TR0
TC1_M_8_TR1
SCB7_TX
SCB7_SDA
SCB7_SCL
FAULT_OU
T_1
P23.2 PWM1_M_1 PWM1_M_9_N TC1_M_10_TR0 TC1_M_9_TR1
0
SCB7_RTS
SCB7_CTS
SCB2_MISO
FAULT_OU
T_2
P23.3 PWM1_M_1 PWM1_M_10_ TC1_M_11_TR0 TC1_M_10_TR1
ETH0_RX_CLK
TRIG_IN[30] FAULT_OU
T_3
1
N
P23.4 PWM1_25
PWM1_M_11_ TC1_25_TR0
N
TC1_M_11_TR1 PWM1_H_9
TRIG_IN[31] TRIG_DBG[
0]
P23.5 PWM1_24
P23.6 PWM1_23
P23.7 PWM1_22
PWM1_25_N
PWM1_24_N
PWM1_23_N
TC1_24_TR0
TC1_23_TR0
TC1_22_TR0
TC1_25_TR1
TC1_24_TR1
TC1_23_TR1
PWM1_H_9_N
TC1_H_9_TR0
TC1_H_9_TR1
SCB2_MOSI
SCB2_CLK
SCB2_SEL0
EXT_CLK
EXT_CLK
CAL_SUP_
NZ
P24.0
P24.1
SDHC_CARD_DE-
TECT_N
SPIHB_CLK
SDHC_CARD_-
MECH_WRITE_PR
OT
P24.2
P24.3
P24.4
SPIHB_RWD
S
SDHC_CLK_CARD
SPIHB_SEL0
SDHC_-
CARD_CMD
SPIHB_SEL1
SDHC_-
CARD_IF_P-
WR_EN
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[24]
Name ACT #0
ACT #7
P25.0
SPIHB_-
DATA0
SDHC_CARD_-
DAT_3TO0_0
P25.1
P25.2
P25.3
P25.4
P25.5
P25.6
P25.7
P26.0
P26.1
P26.2
P26.3
P26.4
P26.5
P26.6
P26.7
P27.0
P27.1
P27.2
P27.3
P27.4
P27.5
SPIHB_-
DATA1
SDHC_CARD_-
DAT_3TO0_1
SPIHB_-
DATA2
SDHC_CARD_-
DAT_3TO0_2
SPIHB_-
DATA3
SDHC_CARD_-
DAT_3TO0_3
SPIHB_-
DATA4
SDHC_CARD_-
DAT_7TO4_0
SPIHB_-
DATA5
SDHC_CARD_-
DAT_7TO4_1
SPIHB_-
DATA6
SDHC_CARD_-
DAT_7TO4_2
SPIHB_-
DATA7
SDHC_CARD_-
DAT_7TO4_3
ETH1_REF
_CLK
ETH1_TX_
CTL
ETH1_TX_
CLK
ETH1_TXD
_0
ETH1_TXD
_1
ETH1_TXD
_2
ETH1_TXD
_3
ETH1_RXD
_0
ETH1_RXD
_1
ETH1_RXD
_2
ETH1_RXD
_3
ETH1_RX_
CTL
ETH1_RX_
CLK
ETH1_MDI
O
P27.6
P27.7
ETH1_MDC
ETH1_ETH
_TSU_TIM-
ER_CMP_V
AL
P28.0 PWM1_63
P28.1 PWM1_64
PWM1_65_N
PWM1_63_N
TC1_63_TR0
TC1_64_TR0
TC1_65_TR1
TC1_63_TR1
PWM1_H_12
SCB10_RX
SCB10_TX
SCB10_MISO
PWM1_H_12_N
SCB10_SDA SCB10_MOSI
[19, 25]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[23]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[24]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #4
P28.2 PWM1_65
PWM1_64_N
TC1_65_TR0
TC1_64_TR1
TC1_H_12_TR0
SCB10_RTS SCB10_SCL SCB10_CLK
P28.3 PWM1_66
P28.4 PWM1_67
P28.5 PWM1_68
P28.6 PWM1_69
P28.7 PWM1_70
P29.0 PWM1_76
P29.1 PWM1_77
P29.2 PWM1_78
P29.3 PWM1_79
P29.4 PWM1_80
P29.5 PWM1_81
P29.6 PWM1_82
P29.7 PWM1_83
P30.0 PWM1_83
P30.1 PWM1_82
P30.2 PWM1_81
P30.3 PWM1_80
P31.0 PWM1_79
P31.1 PWM1_78
P31.2 PWM1_77
P32.0 PWM1_76
P32.1 PWM1_75
P32.2 PWM1_74
P32.3 PWM1_73
P32.4 PWM1_72
P32.5 PWM1_71
P32.6 PWM1_70
P32.7 PWM1_69
PWM1_65_N
PWM1_66_N
PWM1_67_N
PWM1_68_N
PWM1_69_N
PWM1_75_N
PWM1_76_N
PWM1_77_N
PWM1_78_N
PWM1_79_N
PWM1_80_N
PWM1_81_N
PWM1_82_N
PWM1_83_N
PWM1_83_N
PWM1_82_N
PWM1_81_N
PWM1_80_N
PWM1_79_N
PWM1_78_N
PWM1_77_N
PWM1_76_N
PWM1_75_N
PWM1_74_N
PWM1_73_N
PWM1_72_N
PWM1_71_N
PWM1_70_N
TC1_66_TR0
TC1_67_TR0
TC1_68_TR0
TC1_69_TR0
TC1_70_TR0
TC1_76_TR0
TC1_77_TR0
TC1_78_TR0
TC1_79_TR0
TC1_80_TR0
TC1_81_TR0
TC1_82_TR0
TC1_83_TR0
TC1_83_TR0
TC1_82_TR0
TC1_81_TR0
TC1_80_TR0
TC1_79_TR0
TC1_78_TR0
TC1_77_TR0
TC1_76_TR0
TC1_75_TR0
TC1_74_TR0
TC1_73_TR0
TC1_72_TR0
TC1_71_TR0
TC1_70_TR0
TC1_69_TR0
TC1_65_TR1
TC1_66_TR1
TC1_67_TR1
TC1_68_TR1
TC1_69_TR1
TC1_75_TR1
TC1_76_TR1
TC1_77_TR1
TC1_78_TR1
TC1_79_TR1
TC1_80_TR1
TC1_81_TR1
TC1_82_TR1
TC1_83_TR1
TC1_83_TR1
TC1_82_TR1
TC1_81_TR1
TC1_80_TR1
TC1_79_TR1
TC1_78_TR1
TC1_77_TR1
TC1_76_TR1
TC1_75_TR1
TC1_74_TR1
TC1_73_TR1
TC1_72_TR1
TC1_71_TR1
TC1_70_TR1
TC1_H_12_TR1
SCB10_CTS
SCB10_SEL0
SCB10_SEL1
SCB10_SEL2
SCB10_SEL3
SCB9_RTS
SCB9_CTS
SCB9_SCL
SCB9_CLK
SCB9_SEL0
SCB9_SEL1
SCB9_SEL2
TRIG_IN[34]
TRIG_IN[35]
TRIG_IN[36]
TRIG_IN[37]
CAN1_3_TX
CAN1_3_RX
SCB10_RX
SCB10_TX
SCB10_MISO
TRIG_IN[40]
TRIG_IN[41]
TRIG_IN[42]
TRIG_IN[43]
TRIG_IN[44]
TRIG_IN[45]
TRIG_IN[46]
TRIG_IN[47]
SCB10_SDA SCB10_MOSI
SCB10_RTS SCB10_SCL SCB10_CLK
SCB10_CTS
SCB10_SEL0
SCB10_SEL1
SCB10_SEL2
SCB10_SEL3
CAN1_4_TX
CAN1_4_RX
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Alternate function pin assignments
13.1
Pin function description
Table 13-2
Pin function description
Sl.
No.
Pin
Module
Description
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line out, x-TCPWM
block, y-counter number
1
PWMx_y
TCPWM
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR complementary line
out (N), x-TCPWM block, y-counter number
2
3
4
PWMx_y_N
PWMx_M_y
PWMx_M_y_N
TCPWM
TCPWM
TCPWM
TCPWM 16-bit PWM with motor control line out, x-TCPWM block, y-counter number
TCPWM 16-bit PWM with motor control complementary line out (N), x-TCPWM block,
y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM block, y-counter
number
5
6
7
8
9
PWMx_H_y
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out (N), x-TCPWM
block, y-counter number
PWMx_H_y_N
TCx_y_TRz
TCPWM 16-bit dedicated counter input triggers, x-TCPWM block, y-counter number,
z-trigger number
TCPWM 16-bit dedicated counter input triggers with motor control, x-TCPWM block,
y-counter number, z-trigger number
TCx_M_y_TRz
TCx_H_y_TRz
TCPWM 32-bit dedicated counter input triggers, x-TCPWM block, y-counter number,
z-trigger number
10 SCBx_RX
SCB
SCB
UART Receive, x-SCB block
11 SCBx_TX
UART Transmit, x-SCB block
12 SCBx_RTS
13 SCBx_CTS
14 SCBx_SDA
15 SCBx_SCL
16 SCBx_MISO
17 SCBx_MOSI
18 SCBx_CLK
19 SCBx_SELy
23 CANx_y_TX
24 CANx_y_RX
25 SPIHB_CLK
26 SPIHB_RWDS
27 SPIHB_SELx
28 SPIHB_DATAx
29 ETHx_RX_ER
SCB
UART Request to Send (Handshake), x-SCB block
UART Clear to Send (Handshake), x-SCB block
I2C Data line, x-SCB block
SCB
SCB
SCB
I2C Clock line, x-SCB block
SCB
SPI Master Input Slave Output, x-SCB block
SPI Master Output Slave Input, x-SCB block
SPI Serial Clock, x-SCB block
SCB
SCB
SCB
SPI Slave Select, x-SCB block, y-select line
CAN Transmit line, x-CAN block, y-channel number
CAN Receive line, x-CAN block, y-channel number
SMIF interface clock
CANFD
CANFD
SMIF
SMIF
SMIF
SMIF
Ethernet
Ethernet
SMIF (SPI/HYPERBUS™) read-write-data-strobe line
SMIF (SPI/HYPERBUS™) memory select line, x-select line number
SMIF (SPI/HYPERBUS™) memory data read and write line, x-0 to 7 data lines
Ethernet receive error indication line, x-ETH module number
Ethernet time stamp unit timer compare indication line, x-ETH module number
30 ETHx_ETH_TSU_TIMER_CMP_VAL
31 ETHx_MDIO
Ethernet management data input/output (MDIO) interface to PHY, x-ETH module
number
Ethernet
32 ETHx_MDC
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
SDHC
Ethernet management data clock (MDC) line, x-ETH module number
Ethernet reference clock line, x-ETH module number
Ethernet transmit control line, x-ETH module number
Ethernet transmit error indication line, x-ETH module number
Ethernet transmit clock line, x-ETH module number
Ethernet transmit data line, x-ETH module number, y-transmit channel number
Ethernet receive data line, x-ETH module number, y-receive channel number
Ethernet receive control line, x-ETH module number
Ethernet receive clock line, x-ETH module number
SDHC mechanical write protect
33 ETHx_REF_CLK
34 ETHx_TX_CTL
35 ETHx_TX_ER
36 ETHx_TX_CLK
37 ETHx_TXD_y
38 ETHx_RXD_y
39 ETHx_RX_CTL
40 ETHx_RX_CLK
41 SDHC_CARD_MECH_WRITE_PROT
42 SDHC_CARD_CMD
SDHC
SDHC command line
Datasheet
49
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Alternate function pin assignments
Table 13-2
Pin function description (continued)
Sl.
No.
Pin
Module
Description
43 SDHC_CLK_CARD
44 SDHC_CARD_DETECT_N
45 SDHC_CARD_IF_PWR_EN
46 SDHC_CARD_DAT_3TO0_x
47 SDHC_CARD_DAT_7TO4_x
48 AUDIOSSx_MCLK
49 AUDIOSSx_TX_SCK
50 AUDIOSSx_TX_WS
51 AUDIOSSx_TX_SDO
52 AUDIOSSx_CLK_I2S_IF
53 AUDIOSSx_RX_SCK
54 AUDIOSSx_RX_WS
55 AUDIOSSx_RX_SDI
59 CAL_SUP_NZ
SDHC
SDHC
SDHC clock line
SDHC interface insertion or removal detection line
SDHC interface power cycle line
SDHC
SDHC
SDHC lower 4-bits of the data
SDHC
SDHC upper 4-bits of the data in 8-bit mode
AudioSS master clock out, x-AudioSS block
I2S serial clock for transmitter, x-AudioSS block
I2S word select for transmitter, x-AudioSS block
I2S serial data output for transmitter, x-AudioSS block
I2S clock supplied from external I2S bus host, x-AudioSS block
I2S serial clock for receiver, x-AudioSS block
I2S word select for receiver, x-AudioSS block
I2S serial data input for receiver, x-AudioSS block
ETAS Calibration support line
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
System
SRSS
60 FAULT_OUT_x
Fault output line x-0 to 3
61 TRACE_DATA_x
SRSS
Trace dataout line x-0 to 3
62 TRACE_CLOCK
SRSS
Trace clock line
63 RTC_CAL
SRSS RTC
SRSS
RTC calibration clock input
64 SWJ_TRSTN
JTAG Test reset line (Active low)
65 SWJ_SWO_TDO
SRSS
JTAG Test data output/SWO (Serial Wire Output)
JTAG Test clock/SWD clock (Serial Wire Clock)
JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
JTAG Test data input
66 SWJ_SWCLK_TCLK
67 SWJ_SWDIO_TMS
68 SWJ_SWDOE_TDI
69 HIBERNATE_WAKEUP[x]
70 EXT_CLK
SRSS
SRSS
SRSS
SRSS
Hibernate wakeup line x-0 to 3
SRSS
External clock input
REGHC control line, Transistor mode/Positive terminal of the current sense resistor,
PMIC mode/Power good input from PMIC
71 EXT_PS_CTL0
72 EXT_PS_CTL1
73 EXT_PS_CTL2
SRSS REGHC
SRSS REGHC
SRSS REGHC
REGHC control line, Transistor mode/Negative terminal of the current sense
resistor, PMIC mode/Enable output for PMIC
REGHC control line, Transistor mode/unused, PMIC mode/Reset threshold
adjustment for some PMICs
74 ADC[x]_y
PASS SAR
PASS SAR
PASS SAR
PASS SAR
SAR, channel, x-SAR number, y-channel number
SAR motor control input, x-SAR number
75 ADC[x]_M
76 EXT_MUX[x]_y
77 EXT_MUX[x]_EN
External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
External SAR MUX enable line
Datasheet
50
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
14
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources
Interrupt
Source
Power mode
Description
0
1
2
3
4
5
6
7
8
cpuss_interrupts_ipc_0_IRQn
cpuss_interrupts_ipc_1_IRQn
cpuss_interrupts_ipc_2_IRQn
cpuss_interrupts_ipc_3_IRQn
cpuss_interrupts_ipc_4_IRQn
cpuss_interrupts_ipc_5_IRQn
cpuss_interrupts_ipc_6_IRQn
cpuss_interrupts_ipc_7_IRQn
cpuss_interrupts_fault_0_IRQn
cpuss_interrupts_fault_1_IRQn
cpuss_interrupts_fault_2_IRQn
cpuss_interrupts_fault_3_IRQn
srss_interrupt_backup_IRQn
srss_interrupt_mcwdt_0_IRQn
srss_interrupt_mcwdt_1_IRQn
srss_interrupt_mcwdt_2_IRQn
srss_interrupt_wdt_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #0
DeepSleep CPUSS Inter Process Communication Interrupt #1
DeepSleep CPUSS Inter Process Communication Interrupt #2
DeepSleep CPUSS Inter Process Communication Interrupt #3
DeepSleep CPUSS Inter Process Communication Interrupt #4
DeepSleep CPUSS Inter Process Communication Interrupt #5
DeepSleep CPUSS Inter Process Communication Interrupt #6
DeepSleep CPUSS Inter Process Communication Interrupt #7
DeepSleep CPUSS Fault Structure #0 Interrupt
DeepSleep CPUSS Fault Structure #1 Interrupt
DeepSleep CPUSS Fault Structure #2 Interrupt
DeepSleep CPUSS Fault Structure #3 Interrupt
DeepSleep BACKUP domain Interrupt
DeepSleep Multi Counter Watchdog Timer #0 interrupt
DeepSleep Multi Counter Watchdog Timer #1 interrupt
DeepSleep Multi Counter Watchdog Timer #2 interrupt
DeepSleep Hardware Watchdog Timer interrupt
DeepSleep Other combined Interrupts for SRSS (LVD, CLKCAL)
DeepSleep SCB0 interrupt (DeepSleep capable)
9
10
11
12
13
14
15
16
17
18
19
20
srss_interrupt_IRQn
scb_0_interrupt_IRQn
evtgen_0_interrupt_dpslp_IRQn
ioss_interrupt_vdd_IRQn
DeepSleep Event gen DeepSleep domain interrupt
DeepSleep I/O Supply (V
, V , V ) state change Interrupt
DDIO DDA DDD
Consolidated Interrupt for GPIO_STD and
GPIO_ENH, All Ports
21
ioss_interrupt_gpio_dpslp_IRQn
DeepSleep
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ioss_interrupts_gpio_dpslp_0_IRQn
ioss_interrupts_gpio_dpslp_1_IRQn
ioss_interrupts_gpio_dpslp_2_IRQn
ioss_interrupts_gpio_dpslp_3_IRQn
ioss_interrupts_gpio_dpslp_4_IRQn
ioss_interrupts_gpio_dpslp_5_IRQn
ioss_interrupts_gpio_dpslp_6_IRQn
ioss_interrupts_gpio_dpslp_7_IRQn
ioss_interrupts_gpio_dpslp_8_IRQn
ioss_interrupts_gpio_dpslp_9_IRQn
ioss_interrupts_gpio_dpslp_10_IRQn
ioss_interrupts_gpio_dpslp_11_IRQn
ioss_interrupts_gpio_dpslp_12_IRQn
ioss_interrupts_gpio_dpslp_13_IRQn
ioss_interrupts_gpio_dpslp_14_IRQn
ioss_interrupts_gpio_dpslp_15_IRQn
ioss_interrupts_gpio_dpslp_16_IRQn
ioss_interrupts_gpio_dpslp_17_IRQn
ioss_interrupts_gpio_dpslp_18_IRQn
DeepSleep GPIO_ENH Port #0 Interrupt
DeepSleep GPIO_STD Port #1 Interrupt
DeepSleep GPIO_STD Port #2 Interrupt
DeepSleep GPIO_STD Port #3 Interrupt
DeepSleep GPIO_STD Port #4 Interrupt
DeepSleep GPIO_STD Port #5 Interrupt
DeepSleep GPIO_STD Port #6 Interrupt
DeepSleep GPIO_STD Port #7 Interrupt
DeepSleep GPIO_STD Port #8 Interrupt
DeepSleep GPIO_STD Port #9 Interrupt
DeepSleep GPIO_STD Port #10 Interrupt
DeepSleep GPIO_STD Port #11 Interrupt
DeepSleep GPIO_STD Port #12 Interrupt
DeepSleep GPIO_STD Port #13 Interrupt
DeepSleep GPIO_STD Port #14 Interrupt
DeepSleep GPIO_STD Port #15 Interrupt
DeepSleep GPIO_STD Port #16 Interrupt
DeepSleep GPIO_STD Port #17 Interrupt
DeepSleep GPIO_STD Port #18 Interrupt
Datasheet
51
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Source
Power mode
Description
ioss_interrupts_gpio_dpslp_19_IRQn
ioss_interrupts_gpio_dpslp_20_IRQn
ioss_interrupts_gpio_dpslp_21_IRQn
ioss_interrupts_gpio_dpslp_22_IRQn
ioss_interrupts_gpio_dpslp_23_IRQn
ioss_interrupts_gpio_dpslp_28_IRQn
ioss_interrupts_gpio_dpslp_29_IRQn
ioss_interrupts_gpio_dpslp_30_IRQn
ioss_interrupts_gpio_dpslp_31_IRQn
ioss_interrupts_gpio_dpslp_32_IRQn
ioss_interrupts_gpio_act_IRQn
ioss_interrupts_gpio_act_24_IRQn
ioss_interrupts_gpio_act_25_IRQn
ioss_interrupts_gpio_act_26_IRQn
ioss_interrupts_gpio_act_27_IRQn
cpuss_interrupt_crypto_IRQn
cpuss_interrupt_fm_IRQn
cpuss_interrupts_cm7_0_fp_IRQn
cpuss_interrupts_cm7_1_fp_IRQn
cpuss_interrupts_cm0_cti_0_IRQn
cpuss_interrupts_cm0_cti_1_IRQn
cpuss_interrupts_cm7_0_cti_0_IRQn
cpuss_interrupts_cm7_0_cti_1_IRQn
cpuss_interrupts_cm7_1_cti_0_IRQn
cpuss_interrupts_cm7_1_cti_1_IRQn
evtgen_0_interrupt_IRQn
canfd_0_interrupt0_IRQn
canfd_0_interrupt1_IRQn
canfd_1_interrupt0_IRQn
canfd_1_interrupt1_IRQn
canfd_0_interrupts0_0_IRQn
canfd_0_interrupts0_1_IRQn
canfd_0_interrupts0_2_IRQn
canfd_0_interrupts0_3_IRQn
canfd_0_interrupts0_4_IRQn
canfd_0_interrupts1_0_IRQn
canfd_0_interrupts1_1_IRQn
canfd_0_interrupts1_2_IRQn
canfd_0_interrupts1_3_IRQn
canfd_0_interrupts1_4_IRQn
canfd_1_interrupts0_0_IRQn
canfd_1_interrupts0_1_IRQn
DeepSleep GPIO_STD Port #19 Interrupt
DeepSleep GPIO_STD Port #20 Interrupt
DeepSleep GPIO_STD Port #21 Interrupt
DeepSleep GPIO_STD Port #22 Interrupt
DeepSleep GPIO_STD Port #23 Interrupt
DeepSleep GPIO_STD Port #28 Interrupt
DeepSleep GPIO_STD Port #29 Interrupt
DeepSleep GPIO_STD Port #30 Interrupt
DeepSleep GPIO_STD Port #31 Interrupt
DeepSleep GPIO_STD Port #32 Interrupt
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Consolidated Interrupt for HSIO_STD, All Ports
HSIO_STD Port #24 Interrupt
HSIO_STD Port #25 Interrupt
HSIO_STD Port #26 Interrupt
HSIO_STD Port #27 Interrupt
CRYPTO Accelerator Interrupt
Flash Macro Interrupt
CM7_0 Floating Point operation fault
CM7_1 Floating Point operation fault
CM0+ CTI (Cross Trigger Interface) #0
CM0+ CTI #1
CM7_0 CTI #0
CM7_0 CTI #1
CM7_1 CTI #0
CM7_1 CTI #1
Event gen Active domain Interrupt
CAN0, Consolidated Interrupt #0 for all five channels
CAN0, Consolidated Interrupt #1for all five channels
CAN1, Consolidated Interrupt #0for all five channels
CAN1, Consolidated Interrupt #1for all five channels
CAN0, Interrupt #0, Channel #0
CAN0, Interrupt #0, Channel #1
CAN0, Interrupt #0, Channel #2
CAN0, Interrupt #0, Channel #3
CAN0, Interrupt #0, Channel #4
CAN0, Interrupt #1, Channel #0
CAN0, Interrupt #1, Channel #1
CAN0, Interrupt #1, Channel #2
CAN0, Interrupt #1, Channel #3
CAN0, Interrupt #1, Channel #4
CAN1, Interrupt #0, Channel #0
CAN1, Interrupt #0, Channel #1
CAN1, Interrupt #0, Channel #2
CAN1, Interrupt #0, Channel #3
canfd_1_interrupts0_2_IRQn
canfd_1_interrupts0_3_IRQn
Datasheet
52
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
87
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CAN1, Interrupt #0, Channel #4
CAN1, Interrupt #1, Channel #0
CAN1, Interrupt #1, Channel #1
CAN1, Interrupt #1, Channel #2
CAN1, Interrupt #1, Channel #3
CAN1, Interrupt #1, Channel #4
SCB1 Interrupt
SCB2 Interrupt
SCB3 Interrupt
SCB4 Interrupt
SCB5 Interrupt
canfd_1_interrupts0_4_IRQn
canfd_1_interrupts1_0_IRQn
canfd_1_interrupts1_1_IRQn
canfd_1_interrupts1_2_IRQn
canfd_1_interrupts1_3_IRQn
canfd_1_interrupts1_4_IRQn
scb_1_interrupt_IRQn
scb_2_interrupt_IRQn
scb_3_interrupt_IRQn
scb_4_interrupt_IRQn
scb_5_interrupt_IRQn
88
89
90
91
92
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
scb_6_interrupt_IRQn
scb_7_interrupt_IRQn
scb_8_interrupt_IRQn
scb_9_interrupt_IRQn
SCB6 Interrupt
SCB7 Interrupt
SCB8 Interrupt
SCB9 Interrupt
scb_10_interrupt_IRQn
SCB10 Interrupt
pass_0_interrupts_sar_0_IRQn
pass_0_interrupts_sar_1_IRQn
pass_0_interrupts_sar_2_IRQn
pass_0_interrupts_sar_3_IRQn
pass_0_interrupts_sar_4_IRQn
pass_0_interrupts_sar_5_IRQn
pass_0_interrupts_sar_6_IRQn
pass_0_interrupts_sar_7_IRQn
pass_0_interrupts_sar_8_IRQn
pass_0_interrupts_sar_9_IRQn
pass_0_interrupts_sar_10_IRQn
pass_0_interrupts_sar_11_IRQn
pass_0_interrupts_sar_12_IRQn
pass_0_interrupts_sar_13_IRQn
pass_0_interrupts_sar_14_IRQn
pass_0_interrupts_sar_15_IRQn
pass_0_interrupts_sar_16_IRQn
pass_0_interrupts_sar_17_IRQn
pass_0_interrupts_sar_18_IRQn
pass_0_interrupts_sar_19_IRQn
pass_0_interrupts_sar_20_IRQn
pass_0_interrupts_sar_21_IRQn
pass_0_interrupts_sar_22_IRQn
pass_0_interrupts_sar_23_IRQn
pass_0_interrupts_sar_24_IRQn
pass_0_interrupts_sar_25_IRQn
pass_0_interrupts_sar_26_IRQn
pass_0_interrupts_sar_27_IRQn
SAR0, Logical Channel #0 Interrupt
SAR0, Logical Channel #1 Interrupt
SAR0, Logical Channel #2 Interrupt
SAR0, Logical Channel #3 Interrupt
SAR0, Logical Channel #4 Interrupt
SAR0, Logical Channel #5 Interrupt
SAR0, Logical Channel #6 Interrupt
SAR0, Logical Channel #7 Interrupt
SAR0, Logical Channel #8 Interrupt
SAR0, Logical Channel #9 Interrupt
SAR0, Logical Channel #10 Interrupt
SAR0, Logical Channel #11 Interrupt
SAR0, Logical Channel #12 Interrupt
SAR0, Logical Channel #13 Interrupt
SAR0, Logical Channel #14 Interrupt
SAR0, Logical Channel #15 Interrupt
SAR0, Logical Channel #16 Interrupt
SAR0, Logical Channel #17 Interrupt
SAR0, Logical Channel #18 Interrupt
SAR0, Logical Channel #19 Interrupt
SAR0, Logical Channel #20 Interrupt
SAR0, Logical Channel #21 Interrupt
SAR0, Logical Channel #22 Interrupt
SAR0, Logical Channel #23 Interrupt
SAR0, Logical Channel #24 Interrupt
SAR0, Logical Channel #25 Interrupt
SAR0, Logical Channel #26 Interrupt
SAR0, Logical Channel #27 Interrupt
Datasheet
53
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
SAR0, Logical Channel #28 Interrupt
SAR0, Logical Channel #29 Interrupt
SAR0, Logical Channel #30 Interrupt
SAR0, Logical Channel #31 Interrupt
SAR1, Logical Channel #0 Interrupt
SAR1, Logical Channel #1 Interrupt
SAR1, Logical Channel #2 Interrupt
SAR1, Logical Channel #3 Interrupt
SAR1, Logical Channel #4 Interrupt
SAR1, Logical Channel #5 Interrupt
SAR1, Logical Channel #6 Interrupt
SAR1, Logical Channel #7 Interrupt
SAR1, Logical Channel #8 Interrupt
SAR1, Logical Channel #9 Interrupt
SAR1, Logical Channel #10 Interrupt
SAR1, Logical Channel #11 Interrupt
SAR1, Logical Channel #12 Interrupt
SAR1, Logical Channel #13 Interrupt
SAR1, Logical Channel #14 Interrupt
SAR1, Logical Channel #15 Interrupt
SAR1, Logical Channel #16 Interrupt
SAR1, Logical Channel #17 Interrupt
SAR1, Logical Channel #18 Interrupt
SAR1, Logical Channel #19 Interrupt
SAR1, Logical Channel #20 Interrupt
SAR1, Logical Channel #21 Interrupt
SAR1, Logical Channel #22 Interrupt
SAR1, Logical Channel #23 Interrupt
SAR1, Logical Channel #24 Interrupt
SAR1, Logical Channel #25 Interrupt
SAR1, Logical Channel #26 Interrupt
SAR1, Logical Channel #27 Interrupt
SAR1, Logical Channel #28 Interrupt
SAR1, Logical Channel #29 Interrupt
SAR1, Logical Channel #30 Interrupt
SAR1, Logical Channel #31 Interrupt
SAR2, Logical Channel #0 Interrupt
SAR2, Logical Channel #1 Interrupt
SAR2, Logical Channel #2 Interrupt
SAR2, Logical Channel #3 Interrupt
SAR2, Logical Channel #4 Interrupt
SAR2, Logical Channel #5 Interrupt
SAR2, Logical Channel #6 Interrupt
SAR2, Logical Channel #7 Interrupt
pass_0_interrupts_sar_28_IRQn
pass_0_interrupts_sar_29_IRQn
pass_0_interrupts_sar_30_IRQn
pass_0_interrupts_sar_31_IRQn
pass_0_interrupts_sar_32_IRQn
pass_0_interrupts_sar_33_IRQn
pass_0_interrupts_sar_34_IRQn
pass_0_interrupts_sar_35_IRQn
pass_0_interrupts_sar_36_IRQn
pass_0_interrupts_sar_37_IRQn
pass_0_interrupts_sar_38_IRQn
pass_0_interrupts_sar_39_IRQn
pass_0_interrupts_sar_40_IRQn
pass_0_interrupts_sar_41_IRQn
pass_0_interrupts_sar_42_IRQn
pass_0_interrupts_sar_43_IRQn
pass_0_interrupts_sar_44_IRQn
pass_0_interrupts_sar_45_IRQn
pass_0_interrupts_sar_46_IRQn
pass_0_interrupts_sar_47_IRQn
pass_0_interrupts_sar_48_IRQn
pass_0_interrupts_sar_49_IRQn
pass_0_interrupts_sar_50_IRQn
pass_0_interrupts_sar_51_IRQn
pass_0_interrupts_sar_52_IRQn
pass_0_interrupts_sar_53_IRQn
pass_0_interrupts_sar_54_IRQn
pass_0_interrupts_sar_55_IRQn
pass_0_interrupts_sar_56_IRQn
pass_0_interrupts_sar_57_IRQn
pass_0_interrupts_sar_58_IRQn
pass_0_interrupts_sar_59_IRQn
pass_0_interrupts_sar_60_IRQn
pass_0_interrupts_sar_61_IRQn
pass_0_interrupts_sar_62_IRQn
pass_0_interrupts_sar_63_IRQn
pass_0_interrupts_sar_64_IRQn
pass_0_interrupts_sar_65_IRQn
pass_0_interrupts_sar_66_IRQn
pass_0_interrupts_sar_67_IRQn
pass_0_interrupts_sar_68_IRQn
pass_0_interrupts_sar_69_IRQn
pass_0_interrupts_sar_70_IRQn
pass_0_interrupts_sar_71_IRQn
Datasheet
54
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
pass_0_interrupts_sar_72_IRQn
pass_0_interrupts_sar_73_IRQn
pass_0_interrupts_sar_74_IRQn
pass_0_interrupts_sar_75_IRQn
pass_0_interrupts_sar_76_IRQn
pass_0_interrupts_sar_77_IRQn
pass_0_interrupts_sar_78_IRQn
pass_0_interrupts_sar_79_IRQn
pass_0_interrupts_sar_80_IRQn
pass_0_interrupts_sar_81_IRQn
pass_0_interrupts_sar_82_IRQn
pass_0_interrupts_sar_83_IRQn
pass_0_interrupts_sar_84_IRQn
pass_0_interrupts_sar_85_IRQn
pass_0_interrupts_sar_86_IRQn
pass_0_interrupts_sar_87_IRQn
pass_0_interrupts_sar_88_IRQn
pass_0_interrupts_sar_89_IRQn
pass_0_interrupts_sar_90_IRQn
pass_0_interrupts_sar_91_IRQn
pass_0_interrupts_sar_92_IRQn
pass_0_interrupts_sar_93_IRQn
pass_0_interrupts_sar_94_IRQn
pass_0_interrupts_sar_95_IRQn
cpuss_interrupts_dmac_0_IRQn
cpuss_interrupts_dmac_1_IRQn
cpuss_interrupts_dmac_2_IRQn
cpuss_interrupts_dmac_3_IRQn
cpuss_interrupts_dmac_4_IRQn
cpuss_interrupts_dmac_5_IRQn
cpuss_interrupts_dmac_6_IRQn
cpuss_interrupts_dmac_7_IRQn
cpuss_interrupts_dw0_0_IRQn
cpuss_interrupts_dw0_1_IRQn
cpuss_interrupts_dw0_2_IRQn
cpuss_interrupts_dw0_3_IRQn
cpuss_interrupts_dw0_4_IRQn
cpuss_interrupts_dw0_5_IRQn
cpuss_interrupts_dw0_6_IRQn
cpuss_interrupts_dw0_7_IRQn
cpuss_interrupts_dw0_8_IRQn
cpuss_interrupts_dw0_9_IRQn
cpuss_interrupts_dw0_10_IRQn
cpuss_interrupts_dw0_11_IRQn
SAR2, Logical Channel #8 Interrupt
SAR2, Logical Channel #9 Interrupt
SAR2, Logical Channel #10 Interrupt
SAR2, Logical Channel #11 Interrupt
SAR2, Logical Channel #12 Interrupt
SAR2, Logical Channel #13 Interrupt
SAR2, Logical Channel #14 Interrupt
SAR2, Logical Channel #15 Interrupt
SAR2, Logical Channel #16 Interrupt
SAR2, Logical Channel #17 Interrupt
SAR2, Logical Channel #18 Interrupt
SAR2, Logical Channel #19 Interrupt
SAR2, Logical Channel #20 Interrupt
SAR2, Logical Channel #21 Interrupt
SAR2, Logical Channel #22 Interrupt
SAR2, Logical Channel #23 Interrupt
SAR2, Logical Channel #24 Interrupt
SAR2, Logical Channel #25 Interrupt
SAR2, Logical Channel #26 Interrupt
SAR2, Logical Channel #27 Interrupt
SAR2, Logical Channel #28 Interrupt
SAR2, Logical Channel #29 Interrupt
SAR2, Logical Channel #30 Interrupt
SAR2, Logical Channel #31 Interrupt
CPUSS M-DMA0, Channel #0 Interrupt
CPUSS M-DMA0, Channel #1 Interrupt
CPUSS M-DMA0, Channel #2 Interrupt
CPUSS M-DMA0, Channel #3 Interrupt
CPUSS M-DMA0, Channel #4 Interrupt
CPUSS M-DMA0, Channel #5 Interrupt
CPUSS M-DMA0, Channel #6 Interrupt
CPUSS M-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #0 Interrupt
CPUSS P-DMA0, Channel #1 Interrupt
CPUSS P-DMA0, Channel #2 Interrupt
CPUSS P-DMA0, Channel #3 Interrupt
CPUSS P-DMA0, Channel #4 Interrupt
CPUSS P-DMA0, Channel #5 Interrupt
CPUSS P-DMA0, Channel #6 Interrupt
CPUSS P-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #8 Interrupt
CPUSS P-DMA0, Channel #9 Interrupt
CPUSS P-DMA0, Channel #10 Interrupt
CPUSS P-DMA0, Channel #11 Interrupt
Datasheet
55
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw0_12_IRQn
cpuss_interrupts_dw0_13_IRQn
cpuss_interrupts_dw0_14_IRQn
cpuss_interrupts_dw0_15_IRQn
cpuss_interrupts_dw0_16_IRQn
cpuss_interrupts_dw0_17_IRQn
cpuss_interrupts_dw0_18_IRQn
cpuss_interrupts_dw0_19_IRQn
cpuss_interrupts_dw0_20_IRQn
cpuss_interrupts_dw0_21_IRQn
cpuss_interrupts_dw0_22_IRQn
cpuss_interrupts_dw0_23_IRQn
cpuss_interrupts_dw0_24_IRQn
cpuss_interrupts_dw0_25_IRQn
cpuss_interrupts_dw0_26_IRQn
cpuss_interrupts_dw0_27_IRQn
cpuss_interrupts_dw0_28_IRQn
cpuss_interrupts_dw0_29_IRQn
cpuss_interrupts_dw0_30_IRQn
cpuss_interrupts_dw0_31_IRQn
cpuss_interrupts_dw0_32_IRQn
cpuss_interrupts_dw0_33_IRQn
cpuss_interrupts_dw0_34_IRQn
cpuss_interrupts_dw0_35_IRQn
cpuss_interrupts_dw0_36_IRQn
cpuss_interrupts_dw0_37_IRQn
cpuss_interrupts_dw0_38_IRQn
cpuss_interrupts_dw0_39_IRQn
cpuss_interrupts_dw0_40_IRQn
cpuss_interrupts_dw0_41_IRQn
cpuss_interrupts_dw0_42_IRQn
cpuss_interrupts_dw0_43_IRQn
cpuss_interrupts_dw0_44_IRQn
cpuss_interrupts_dw0_45_IRQn
cpuss_interrupts_dw0_46_IRQn
cpuss_interrupts_dw0_47_IRQn
cpuss_interrupts_dw0_48_IRQn
cpuss_interrupts_dw0_49_IRQn
cpuss_interrupts_dw0_50_IRQn
cpuss_interrupts_dw0_51_IRQn
cpuss_interrupts_dw0_52_IRQn
cpuss_interrupts_dw0_53_IRQn
cpuss_interrupts_dw0_54_IRQn
cpuss_interrupts_dw0_55_IRQn
CPUSS P-DMA0, Channel #12 Interrupt
CPUSS P-DMA0, Channel #13 Interrupt
CPUSS P-DMA0, Channel #14 Interrupt
CPUSS P-DMA0, Channel #15 Interrupt
CPUSS P-DMA0, Channel #16 Interrupt
CPUSS P-DMA0, Channel #17 Interrupt
CPUSS P-DMA0, Channel #18 Interrupt
CPUSS P-DMA0, Channel #19 Interrupt
CPUSS P-DMA0, Channel #20 Interrupt
CPUSS P-DMA0, Channel #21 Interrupt
CPUSS P-DMA0, Channel #22 Interrupt
CPUSS P-DMA0, Channel #23 Interrupt
CPUSS P-DMA0, Channel #24 Interrupt
CPUSS P-DMA0, Channel #25 Interrupt
CPUSS P-DMA0, Channel #26 Interrupt
CPUSS P-DMA0, Channel #27 Interrupt
CPUSS P-DMA0, Channel #28 Interrupt
CPUSS P-DMA0, Channel #29 Interrupt
CPUSS P-DMA0, Channel #30 Interrupt
CPUSS P-DMA0, Channel #31 Interrupt
CPUSS P-DMA0, Channel #32 Interrupt
CPUSS P-DMA0, Channel #33 Interrupt
CPUSS P-DMA0, Channel #34 Interrupt
CPUSS P-DMA0, Channel #35 Interrupt
CPUSS P-DMA0, Channel #36 Interrupt
CPUSS P-DMA0, Channel #37 Interrupt
CPUSS P-DMA0, Channel #38 Interrupt
CPUSS P-DMA0, Channel #39 Interrupt
CPUSS P-DMA0, Channel #40 Interrupt
CPUSS P-DMA0, Channel #41 Interrupt
CPUSS P-DMA0, Channel #42 Interrupt
CPUSS P-DMA0, Channel #43 Interrupt
CPUSS P-DMA0, Channel #44 Interrupt
CPUSS P-DMA0, Channel #45 Interrupt
CPUSS P-DMA0, Channel #46 Interrupt
CPUSS P-DMA0, Channel #47 Interrupt
CPUSS P-DMA0, Channel #48 Interrupt
CPUSS P-DMA0, Channel #49 Interrupt
CPUSS P-DMA0, Channel #50 Interrupt
CPUSS P-DMA0, Channel #51 Interrupt
CPUSS P-DMA0, Channel #52 Interrupt
CPUSS P-DMA0, Channel #53 Interrupt
CPUSS P-DMA0, Channel #54 Interrupt
CPUSS P-DMA0, Channel #55 Interrupt
Datasheet
56
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw0_56_IRQn
cpuss_interrupts_dw0_57_IRQn
cpuss_interrupts_dw0_58_IRQn
cpuss_interrupts_dw0_59_IRQn
cpuss_interrupts_dw0_60_IRQn
cpuss_interrupts_dw0_61_IRQn
cpuss_interrupts_dw0_62_IRQn
cpuss_interrupts_dw0_63_IRQn
cpuss_interrupts_dw0_64_IRQn
cpuss_interrupts_dw0_65_IRQn
cpuss_interrupts_dw0_66_IRQn
cpuss_interrupts_dw0_67_IRQn
cpuss_interrupts_dw0_68_IRQn
cpuss_interrupts_dw0_69_IRQn
cpuss_interrupts_dw0_70_IRQn
cpuss_interrupts_dw0_71_IRQn
cpuss_interrupts_dw0_72_IRQn
cpuss_interrupts_dw0_73_IRQn
cpuss_interrupts_dw0_74_IRQn
cpuss_interrupts_dw0_75_IRQn
cpuss_interrupts_dw0_76_IRQn
cpuss_interrupts_dw0_77_IRQn
cpuss_interrupts_dw0_78_IRQn
cpuss_interrupts_dw0_79_IRQn
cpuss_interrupts_dw0_80_IRQn
cpuss_interrupts_dw0_81_IRQn
cpuss_interrupts_dw0_82_IRQn
cpuss_interrupts_dw0_83_IRQn
cpuss_interrupts_dw0_84_IRQn
cpuss_interrupts_dw0_85_IRQn
cpuss_interrupts_dw0_86_IRQn
cpuss_interrupts_dw0_87_IRQn
cpuss_interrupts_dw0_88_IRQn
cpuss_interrupts_dw0_89_IRQn
cpuss_interrupts_dw0_90_IRQn
cpuss_interrupts_dw0_91_IRQn
cpuss_interrupts_dw0_92_IRQn
cpuss_interrupts_dw0_93_IRQn
cpuss_interrupts_dw0_94_IRQn
cpuss_interrupts_dw0_95_IRQn
cpuss_interrupts_dw0_96_IRQn
cpuss_interrupts_dw0_97_IRQn
cpuss_interrupts_dw0_98_IRQn
cpuss_interrupts_dw0_99_IRQn
CPUSS P-DMA0, Channel #56 Interrupt
CPUSS P-DMA0, Channel #57 Interrupt
CPUSS P-DMA0, Channel #58 Interrupt
CPUSS P-DMA0, Channel #59 Interrupt
CPUSS P-DMA0, Channel #60 Interrupt
CPUSS P-DMA0, Channel #61 Interrupt
CPUSS P-DMA0, Channel #62 Interrupt
CPUSS P-DMA0, Channel #63 Interrupt
CPUSS P-DMA0, Channel #64 Interrupt
CPUSS P-DMA0, Channel #65 Interrupt
CPUSS P-DMA0, Channel #66 Interrupt
CPUSS P-DMA0, Channel #67 Interrupt
CPUSS P-DMA0, Channel #68 Interrupt
CPUSS P-DMA0, Channel #69 Interrupt
CPUSS P-DMA0, Channel #70 Interrupt
CPUSS P-DMA0, Channel #71 Interrupt
CPUSS P-DMA0, Channel #72 Interrupt
CPUSS P-DMA0, Channel #73 Interrupt
CPUSS P-DMA0, Channel #74 Interrupt
CPUSS P-DMA0, Channel #75 Interrupt
CPUSS P-DMA0, Channel #76 Interrupt
CPUSS P-DMA0, Channel #77 Interrupt
CPUSS P-DMA0, Channel #78 Interrupt
CPUSS P-DMA0, Channel #79 Interrupt
CPUSS P-DMA0, Channel #80 Interrupt
CPUSS P-DMA0, Channel #81 Interrupt
CPUSS P-DMA0, Channel #82 Interrupt
CPUSS P-DMA0, Channel #83 Interrupt
CPUSS P-DMA0, Channel #84 Interrupt
CPUSS P-DMA0, Channel #85 Interrupt
CPUSS P-DMA0, Channel #86 Interrupt
CPUSS P-DMA0, Channel #87 Interrupt
CPUSS P-DMA0, Channel #88 Interrupt
CPUSS P-DMA0, Channel #89 Interrupt
CPUSS P-DMA0, Channel #90 Interrupt
CPUSS P-DMA0, Channel #91 Interrupt
CPUSS P-DMA0, Channel #92 Interrupt
CPUSS P-DMA0, Channel #93 Interrupt
CPUSS P-DMA0, Channel #94 Interrupt
CPUSS P-DMA0, Channel #95 Interrupt
CPUSS P-DMA0, Channel #96 Interrupt
CPUSS P-DMA0, Channel #97 Interrupt
CPUSS P-DMA0, Channel #98 Interrupt
CPUSS P-DMA0, Channel #99 Interrupt
Datasheet
57
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw0_100_IRQn
cpuss_interrupts_dw0_101_IRQn
cpuss_interrupts_dw0_102_IRQn
cpuss_interrupts_dw0_103_IRQn
cpuss_interrupts_dw0_104_IRQn
cpuss_interrupts_dw0_105_IRQn
cpuss_interrupts_dw0_106_IRQn
cpuss_interrupts_dw0_107_IRQn
cpuss_interrupts_dw0_108_IRQn
cpuss_interrupts_dw0_109_IRQn
cpuss_interrupts_dw0_110_IRQn
cpuss_interrupts_dw0_111_IRQn
cpuss_interrupts_dw0_112_IRQn
cpuss_interrupts_dw0_113_IRQn
cpuss_interrupts_dw0_114_IRQn
cpuss_interrupts_dw0_115_IRQn
cpuss_interrupts_dw0_116_IRQn
cpuss_interrupts_dw0_117_IRQn
cpuss_interrupts_dw0_118_IRQn
cpuss_interrupts_dw0_119_IRQn
cpuss_interrupts_dw0_120_IRQn
cpuss_interrupts_dw0_121_IRQn
cpuss_interrupts_dw0_122_IRQn
cpuss_interrupts_dw0_123_IRQn
cpuss_interrupts_dw0_124_IRQn
cpuss_interrupts_dw0_125_IRQn
cpuss_interrupts_dw0_126_IRQn
cpuss_interrupts_dw0_127_IRQn
cpuss_interrupts_dw0_128_IRQn
cpuss_interrupts_dw0_129_IRQn
cpuss_interrupts_dw0_130_IRQn
cpuss_interrupts_dw0_131_IRQn
cpuss_interrupts_dw0_132_IRQn
cpuss_interrupts_dw0_133_IRQn
cpuss_interrupts_dw0_134_IRQn
cpuss_interrupts_dw0_135_IRQn
cpuss_interrupts_dw0_136_IRQn
cpuss_interrupts_dw0_137_IRQn
cpuss_interrupts_dw0_138_IRQn
cpuss_interrupts_dw0_139_IRQn
cpuss_interrupts_dw0_140_IRQn
cpuss_interrupts_dw0_141_IRQn
cpuss_interrupts_dw0_142_IRQn
cpuss_interrupts_dw1_0_IRQn
CPUSS P-DMA0, Channel #100 Interrupt
CPUSS P-DMA0, Channel #101 Interrupt
CPUSS P-DMA0, Channel #102 Interrupt
CPUSS P-DMA0, Channel #103 Interrupt
CPUSS P-DMA0, Channel #104 Interrupt
CPUSS P-DMA0, Channel #105 Interrupt
CPUSS P-DMA0, Channel #106 Interrupt
CPUSS P-DMA0, Channel #107 Interrupt
CPUSS P-DMA0, Channel #108 Interrupt
CPUSS P-DMA0, Channel #109 Interrupt
CPUSS P-DMA0, Channel #110 Interrupt
CPUSS P-DMA0, Channel #111 Interrupt
CPUSS P-DMA0, Channel #112 Interrupt
CPUSS P-DMA0, Channel #113 Interrupt
CPUSS P-DMA0, Channel #114 Interrupt
CPUSS P-DMA0, Channel #115 Interrupt
CPUSS P-DMA0, Channel #116 Interrupt
CPUSS P-DMA0, Channel #117 Interrupt
CPUSS P-DMA0, Channel #118 Interrupt
CPUSS P-DMA0, Channel #119 Interrupt
CPUSS P-DMA0, Channel #120 Interrupt
CPUSS P-DMA0, Channel #121 Interrupt
CPUSS P-DMA0, Channel #122 Interrupt
CPUSS P-DMA0, Channel #123 Interrupt
CPUSS P-DMA0, Channel #124 Interrupt
CPUSS P-DMA0, Channel #125 Interrupt
CPUSS P-DMA0, Channel #126 Interrupt
CPUSS P-DMA0, Channel #127 Interrupt
CPUSS P-DMA0, Channel #128 Interrupt
CPUSS P-DMA0, Channel #129 Interrupt
CPUSS P-DMA0, Channel #130 Interrupt
CPUSS P-DMA0, Channel #131 Interrupt
CPUSS P-DMA0, Channel #132 Interrupt
CPUSS P-DMA0, Channel #133 Interrupt
CPUSS P-DMA0, Channel #134 Interrupt
CPUSS P-DMA0, Channel #135 Interrupt
CPUSS P-DMA0, Channel #136 Interrupt
CPUSS P-DMA0, Channel #137 Interrupt
CPUSS P-DMA0, Channel #138 Interrupt
CPUSS P-DMA0, Channel #139 Interrupt
CPUSS P-DMA0, Channel #140 Interrupt
CPUSS P-DMA0, Channel #141 Interrupt
CPUSS P-DMA0, Channel #142 Interrupt
CPUSS P-DMA1, Channel #0 Interrupt
Datasheet
58
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw1_1_IRQn
cpuss_interrupts_dw1_2_IRQn
cpuss_interrupts_dw1_3_IRQn
cpuss_interrupts_dw1_4_IRQn
cpuss_interrupts_dw1_5_IRQn
cpuss_interrupts_dw1_6_IRQn
cpuss_interrupts_dw1_7_IRQn
cpuss_interrupts_dw1_8_IRQn
cpuss_interrupts_dw1_9_IRQn
cpuss_interrupts_dw1_10_IRQn
cpuss_interrupts_dw1_11_IRQn
cpuss_interrupts_dw1_12_IRQn
cpuss_interrupts_dw1_13_IRQn
cpuss_interrupts_dw1_14_IRQn
cpuss_interrupts_dw1_15_IRQn
cpuss_interrupts_dw1_16_IRQn
cpuss_interrupts_dw1_17_IRQn
cpuss_interrupts_dw1_18_IRQn
cpuss_interrupts_dw1_19_IRQn
cpuss_interrupts_dw1_20_IRQn
cpuss_interrupts_dw1_21_IRQn
cpuss_interrupts_dw1_22_IRQn
cpuss_interrupts_dw1_23_IRQn
cpuss_interrupts_dw1_24_IRQn
cpuss_interrupts_dw1_25_IRQn
cpuss_interrupts_dw1_26_IRQn
cpuss_interrupts_dw1_27_IRQn
cpuss_interrupts_dw1_28_IRQn
cpuss_interrupts_dw1_29_IRQn
cpuss_interrupts_dw1_30_IRQn
cpuss_interrupts_dw1_31_IRQn
cpuss_interrupts_dw1_32_IRQn
cpuss_interrupts_dw1_33_IRQn
cpuss_interrupts_dw1_34_IRQn
cpuss_interrupts_dw1_35_IRQn
cpuss_interrupts_dw1_36_IRQn
cpuss_interrupts_dw1_37_IRQn
cpuss_interrupts_dw1_38_IRQn
cpuss_interrupts_dw1_39_IRQn
cpuss_interrupts_dw1_40_IRQn
cpuss_interrupts_dw1_41_IRQn
cpuss_interrupts_dw1_42_IRQn
cpuss_interrupts_dw1_43_IRQn
cpuss_interrupts_dw1_44_IRQn
CPUSS P-DMA1, Channel #1 Interrupt
CPUSS P-DMA1, Channel #2 Interrupt
CPUSS P-DMA1, Channel #3 Interrupt
CPUSS P-DMA1, Channel #4 Interrupt
CPUSS P-DMA1, Channel #5 Interrupt
CPUSS P-DMA1, Channel #6 Interrupt
CPUSS P-DMA1, Channel #7 Interrupt
CPUSS P-DMA1, Channel #8 Interrupt
CPUSS P-DMA1, Channel #9 Interrupt
CPUSS P-DMA1, Channel #10 Interrupt
CPUSS P-DMA1, Channel #11 Interrupt
CPUSS P-DMA1, Channel #12 Interrupt
CPUSS P-DMA1, Channel #13 Interrupt
CPUSS P-DMA1, Channel #14 Interrupt
CPUSS P-DMA1, Channel #15 Interrupt
CPUSS P-DMA1, Channel #16 Interrupt
CPUSS P-DMA1, Channel #17 Interrupt
CPUSS P-DMA1, Channel #18 Interrupt
CPUSS P-DMA1, Channel #19 Interrupt
CPUSS P-DMA1, Channel #20 Interrupt
CPUSS P-DMA1, Channel #21 Interrupt
CPUSS P-DMA1, Channel #22 Interrupt
CPUSS P-DMA1, Channel #23 Interrupt
CPUSS P-DMA1, Channel #24 Interrupt
CPUSS P-DMA1, Channel #25 Interrupt
CPUSS P-DMA1, Channel #26 Interrupt
CPUSS P-DMA1, Channel #27 Interrupt
CPUSS P-DMA1, Channel #28 Interrupt
CPUSS P-DMA1, Channel #29 Interrupt
CPUSS P-DMA1, Channel #30 Interrupt
CPUSS P-DMA1, Channel #31 Interrupt
CPUSS P-DMA1, Channel #32 Interrupt
CPUSS P-DMA1, Channel #33 Interrupt
CPUSS P-DMA1, Channel #34 Interrupt
CPUSS P-DMA1, Channel #35 Interrupt
CPUSS P-DMA1, Channel #36 Interrupt
CPUSS P-DMA1, Channel #37 Interrupt
CPUSS P-DMA1, Channel #38 Interrupt
CPUSS P-DMA1, Channel #39 Interrupt
CPUSS P-DMA1, Channel #40 Interrupt
CPUSS P-DMA1, Channel #41 Interrupt
CPUSS P-DMA1, Channel #42 Interrupt
CPUSS P-DMA1, Channel #43 Interrupt
CPUSS P-DMA1, Channel #44 Interrupt
Datasheet
59
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw1_45_IRQn
cpuss_interrupts_dw1_46_IRQn
cpuss_interrupts_dw1_47_IRQn
cpuss_interrupts_dw1_48_IRQn
cpuss_interrupts_dw1_49_IRQn
cpuss_interrupts_dw1_50_IRQn
cpuss_interrupts_dw1_51_IRQn
cpuss_interrupts_dw1_52_IRQn
cpuss_interrupts_dw1_53_IRQn
cpuss_interrupts_dw1_54_IRQn
cpuss_interrupts_dw1_55_IRQn
cpuss_interrupts_dw1_56_IRQn
cpuss_interrupts_dw1_57_IRQn
cpuss_interrupts_dw1_58_IRQn
cpuss_interrupts_dw1_59_IRQn
cpuss_interrupts_dw1_60_IRQn
cpuss_interrupts_dw1_61_IRQn
cpuss_interrupts_dw1_62_IRQn
cpuss_interrupts_dw1_63_IRQn
cpuss_interrupts_dw1_64_IRQn
tcpwm_1_interrupts_0_IRQn
tcpwm_1_interrupts_1_IRQn
tcpwm_1_interrupts_2_IRQn
tcpwm_1_interrupts_3_IRQn
tcpwm_1_interrupts_4_IRQn
tcpwm_1_interrupts_5_IRQn
tcpwm_1_interrupts_6_IRQn
tcpwm_1_interrupts_7_IRQn
tcpwm_1_interrupts_8_IRQn
tcpwm_1_interrupts_9_IRQn
tcpwm_1_interrupts_10_IRQn
tcpwm_1_interrupts_11_IRQn
tcpwm_1_interrupts_12_IRQn
tcpwm_1_interrupts_13_IRQn
tcpwm_1_interrupts_14_IRQn
tcpwm_1_interrupts_15_IRQn
tcpwm_1_interrupts_16_IRQn
tcpwm_1_interrupts_17_IRQn
tcpwm_1_interrupts_18_IRQn
tcpwm_1_interrupts_19_IRQn
tcpwm_1_interrupts_20_IRQn
tcpwm_1_interrupts_21_IRQn
tcpwm_1_interrupts_22_IRQn
tcpwm_1_interrupts_23_IRQn
CPUSS P-DMA1, Channel #45 Interrupt
CPUSS P-DMA1, Channel #46 Interrupt
CPUSS P-DMA1, Channel #47 Interrupt
CPUSS P-DMA1, Channel #48 Interrupt
CPUSS P-DMA1, Channel #49 Interrupt
CPUSS P-DMA1, Channel #50 Interrupt
CPUSS P-DMA1, Channel #51 Interrupt
CPUSS P-DMA1, Channel #52 Interrupt
CPUSS P-DMA1, Channel #53 Interrupt
CPUSS P-DMA1, Channel #54 Interrupt
CPUSS P-DMA1, Channel #55 Interrupt
CPUSS P-DMA1, Channel #56 Interrupt
CPUSS P-DMA1, Channel #57 Interrupt
CPUSS P-DMA1, Channel #58 Interrupt
CPUSS P-DMA1, Channel #59 Interrupt
CPUSS P-DMA1, Channel #60 Interrupt
CPUSS P-DMA1, Channel #61 Interrupt
CPUSS P-DMA1, Channel #62 Interrupt
CPUSS P-DMA1, Channel #63 Interrupt
CPUSS P-DMA1, Channel #64 Interrupt
TCPWM1 Group #0, Counter #0 Interrupt
TCPWM1 Group #0, Counter #1 Interrupt
TCPWM1 Group #0, Counter #2 Interrupt
TCPWM1 Group #0, Counter #3 Interrupt
TCPWM1 Group #0, Counter #4 Interrupt
TCPWM1 Group #0, Counter #5 Interrupt
TCPWM1 Group #0, Counter #6 Interrupt
TCPWM1 Group #0, Counter #7 Interrupt
TCPWM1 Group #0, Counter #8 Interrupt
TCPWM1 Group #0, Counter #9 Interrupt
TCPWM1 Group #0, Counter #10 Interrupt
TCPWM1 Group #0, Counter #11 Interrupt
TCPWM1 Group #0, Counter #12 Interrupt
TCPWM1 Group #0, Counter #13 Interrupt
TCPWM1 Group #0, Counter #14 Interrupt
TCPWM1 Group #0, Counter #15 Interrupt
TCPWM1 Group #0, Counter #16 Interrupt
TCPWM1 Group #0, Counter #17 Interrupt
TCPWM1 Group #0, Counter #18 Interrupt
TCPWM1 Group #0, Counter #19 Interrupt
TCPWM1 Group #0, Counter #20 Interrupt
TCPWM1 Group #0, Counter #21 Interrupt
TCPWM1 Group #0, Counter #22 Interrupt
TCPWM1 Group #0, Counter #23 Interrupt
Datasheet
60
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
tcpwm_1_interrupts_24_IRQn
tcpwm_1_interrupts_25_IRQn
tcpwm_1_interrupts_26_IRQn
tcpwm_1_interrupts_27_IRQn
tcpwm_1_interrupts_28_IRQn
tcpwm_1_interrupts_29_IRQn
tcpwm_1_interrupts_30_IRQn
tcpwm_1_interrupts_31_IRQn
tcpwm_1_interrupts_32_IRQn
tcpwm_1_interrupts_33_IRQn
tcpwm_1_interrupts_34_IRQn
tcpwm_1_interrupts_35_IRQn
tcpwm_1_interrupts_36_IRQn
tcpwm_1_interrupts_37_IRQn
tcpwm_1_interrupts_38_IRQn
tcpwm_1_interrupts_39_IRQn
tcpwm_1_interrupts_40_IRQn
tcpwm_1_interrupts_41_IRQn
tcpwm_1_interrupts_42_IRQn
tcpwm_1_interrupts_43_IRQn
tcpwm_1_interrupts_44_IRQn
tcpwm_1_interrupts_45_IRQn
tcpwm_1_interrupts_46_IRQn
tcpwm_1_interrupts_47_IRQn
tcpwm_1_interrupts_48_IRQn
tcpwm_1_interrupts_49_IRQn
tcpwm_1_interrupts_50_IRQn
tcpwm_1_interrupts_51_IRQn
tcpwm_1_interrupts_52_IRQn
tcpwm_1_interrupts_53_IRQn
tcpwm_1_interrupts_54_IRQn
tcpwm_1_interrupts_55_IRQn
tcpwm_1_interrupts_56_IRQn
tcpwm_1_interrupts_57_IRQn
tcpwm_1_interrupts_58_IRQn
tcpwm_1_interrupts_59_IRQn
tcpwm_1_interrupts_60_IRQn
tcpwm_1_interrupts_61_IRQn
tcpwm_1_interrupts_62_IRQn
tcpwm_1_interrupts_63_IRQn
tcpwm_1_interrupts_64_IRQn
tcpwm_1_interrupts_65_IRQn
tcpwm_1_interrupts_66_IRQn
tcpwm_1_interrupts_67_IRQn
TCPWM1 Group #0, Counter #24 Interrupt
TCPWM1 Group #0, Counter #25 Interrupt
TCPWM1 Group #0, Counter #26 Interrupt
TCPWM1 Group #0, Counter #27 Interrupt
TCPWM1 Group #0, Counter #28 Interrupt
TCPWM1 Group #0, Counter #29 Interrupt
TCPWM1 Group #0, Counter #30 Interrupt
TCPWM1 Group #0, Counter #31 Interrupt
TCPWM1 Group #0, Counter #32 Interrupt
TCPWM1 Group #0, Counter #33 Interrupt
TCPWM1 Group #0, Counter #34 Interrupt
TCPWM1 Group #0, Counter #35 Interrupt
TCPWM1 Group #0, Counter #36 Interrupt
TCPWM1 Group #0, Counter #37 Interrupt
TCPWM1 Group #0, Counter #38 Interrupt
TCPWM1 Group #0, Counter #39 Interrupt
TCPWM1 Group #0, Counter #40 Interrupt
TCPWM1 Group #0, Counter #41 Interrupt
TCPWM1 Group #0, Counter #42 Interrupt
TCPWM1 Group #0, Counter #43 Interrupt
TCPWM1 Group #0, Counter #44 Interrupt
TCPWM1 Group #0, Counter #45 Interrupt
TCPWM1 Group #0, Counter #46 Interrupt
TCPWM1 Group #0, Counter #47 Interrupt
TCPWM1 Group #0, Counter #48 Interrupt
TCPWM1 Group #0, Counter #49 Interrupt
TCPWM1 Group #0, Counter #50 Interrupt
TCPWM1 Group #0, Counter #51 Interrupt
TCPWM1 Group #0, Counter #52 Interrupt
TCPWM1 Group #0, Counter #53 Interrupt
TCPWM1 Group #0, Counter #54 Interrupt
TCPWM1 Group #0, Counter #55 Interrupt
TCPWM1 Group #0, Counter #56 Interrupt
TCPWM1 Group #0, Counter #57 Interrupt
TCPWM1 Group #0, Counter #58 Interrupt
TCPWM1 Group #0, Counter #59 Interrupt
TCPWM1 Group #0, Counter #60 Interrupt
TCPWM1 Group #0, Counter #61 Interrupt
TCPWM1 Group #0, Counter #62 Interrupt
TCPWM1 Group #0, Counter #63 Interrupt
TCPWM1 Group #0, Counter #64 Interrupt
TCPWM1 Group #0, Counter #65 Interrupt
TCPWM1 Group #0, Counter #66 Interrupt
TCPWM1 Group #0, Counter #67 Interrupt
Datasheet
61
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
tcpwm_1_interrupts_68_IRQn
tcpwm_1_interrupts_69_IRQn
tcpwm_1_interrupts_70_IRQn
tcpwm_1_interrupts_71_IRQn
tcpwm_1_interrupts_72_IRQn
tcpwm_1_interrupts_73_IRQn
tcpwm_1_interrupts_74_IRQn
tcpwm_1_interrupts_75_IRQn
tcpwm_1_interrupts_76_IRQn
tcpwm_1_interrupts_77_IRQn
tcpwm_1_interrupts_78_IRQn
tcpwm_1_interrupts_79_IRQn
tcpwm_1_interrupts_80_IRQn
tcpwm_1_interrupts_81_IRQn
tcpwm_1_interrupts_82_IRQn
tcpwm_1_interrupts_83_IRQn
tcpwm_0_interrupts_0_IRQn
tcpwm_0_interrupts_1_IRQn
tcpwm_0_interrupts_2_IRQn
tcpwm_1_interrupts_256_IRQn
tcpwm_1_interrupts_257_IRQn
tcpwm_1_interrupts_258_IRQn
tcpwm_1_interrupts_259_IRQn
tcpwm_1_interrupts_260_IRQn
tcpwm_1_interrupts_261_IRQn
tcpwm_1_interrupts_262_IRQn
tcpwm_1_interrupts_263_IRQn
tcpwm_1_interrupts_264_IRQn
tcpwm_1_interrupts_265_IRQn
tcpwm_1_interrupts_266_IRQn
tcpwm_1_interrupts_267_IRQn
tcpwm_0_interrupts_256_IRQn
tcpwm_0_interrupts_257_IRQn
tcpwm_0_interrupts_258_IRQn
tcpwm_1_interrupts_512_IRQn
tcpwm_1_interrupts_513_IRQn
tcpwm_1_interrupts_514_IRQn
tcpwm_1_interrupts_515_IRQn
tcpwm_1_interrupts_516_IRQn
tcpwm_1_interrupts_517_IRQn
tcpwm_1_interrupts_518_IRQn
tcpwm_1_interrupts_519_IRQn
tcpwm_1_interrupts_520_IRQn
tcpwm_1_interrupts_521_IRQn
TCPWM1 Group #0, Counter #68 Interrupt
TCPWM1 Group #0, Counter #69 Interrupt
TCPWM1 Group #0, Counter #70 Interrupt
TCPWM1 Group #0, Counter #71 Interrupt
TCPWM1 Group #0, Counter #72 Interrupt
TCPWM1 Group #0, Counter #73 Interrupt
TCPWM1 Group #0, Counter #74 Interrupt
TCPWM1 Group #0, Counter #75 Interrupt
TCPWM1 Group #0, Counter #76 Interrupt
TCPWM1 Group #0, Counter #77 Interrupt
TCPWM1 Group #0, Counter #78 Interrupt
TCPWM1 Group #0, Counter #79 Interrupt
TCPWM1 Group #0, Counter #80 Interrupt
TCPWM1 Group #0, Counter #81 Interrupt
TCPWM1 Group #0, Counter #82 Interrupt
TCPWM1 Group #0, Counter #83 Interrupt
TCPWM0 Group #0, Counter #0 Interrupt
TCPWM0 Group #0, Counter #1 Interrupt
TCPWM0 Group #0, Counter #2 Interrupt
TCPWM1 Group #1, Counter #0 Interrupt
TCPWM1 Group #1, Counter #1 Interrupt
TCPWM1 Group #1, Counter #2 Interrupt
TCPWM1 Group #1, Counter #3 Interrupt
TCPWM1 Group #1, Counter #4 Interrupt
TCPWM1 Group #1, Counter #5 Interrupt
TCPWM1 Group #1, Counter #6 Interrupt
TCPWM1 Group #1, Counter #7 Interrupt
TCPWM1 Group #1, Counter #8 Interrupt
TCPWM1 Group #1, Counter #9 Interrupt
TCPWM1 Group #1, Counter #10 Interrupt
TCPWM1 Group #1, Counter #11 Interrupt
TCPWM0 Group #1, Counter #0 Interrupt
TCPWM0 Group #1, Counter #1 Interrupt
TCPWM0 Group #1, Counter #2 Interrupt
TCPWM1 Group #2, Counter #0 Interrupt
TCPWM1 Group #2, Counter #1 Interrupt
TCPWM1 Group #2, Counter #2 Interrupt
TCPWM1 Group #2, Counter #3 Interrupt
TCPWM1 Group #2, Counter #4 Interrupt
TCPWM1 Group #2, Counter #5 Interrupt
TCPWM1 Group #2, Counter #6 Interrupt
TCPWM1 Group #2, Counter #7 Interrupt
TCPWM1 Group #2, Counter #8 Interrupt
TCPWM1 Group #2, Counter #9 Interrupt
Datasheet
62
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
547
548
549
550
551
552
555
556
557
558
559
560
561
562
563
564
565
566
Source
Power mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
TCPWM1 Group #2, Counter #10 Interrupt
TCPWM1 Group #2, Counter #11 Interrupt
TCPWM1 Group #2, Counter #12 Interrupt
TCPWM0 Group #2, Counter #0 Interrupt
TCPWM0 Group #2, Counter #1 Interrupt
TCPWM0 Group #2, Counter #2 Interrupt
SMIF0 (QSPI) interrupt
tcpwm_1_interrupts_522_IRQn
tcpwm_1_interrupts_523_IRQn
tcpwm_1_interrupts_524_IRQn
tcpwm_0_interrupts_512_IRQn
tcpwm_0_interrupts_513_IRQn
tcpwm_0_interrupts_514_IRQn
smif_0_interrupt_IRQn
eth_0_interrupt_eth_IRQn
Ethernet0 interrupt
eth_0_interrupt_eth_q2_IRQn
eth_0_interrupt_eth_q1_IRQn
eth_1_interrupt_eth_IRQn
eth_1_interrupt_eth_q2_IRQn
eth_1_interrupt_eth_q1_IRQn
sdhc_0_interrupt_general_IRQn
sdhc_0_interrupt_wakeup_IRQn
audioss_0_interrupt_i2s_IRQn
audioss_1_interrupt_i2s_IRQn
audioss_2_interrupt_i2s_IRQn
Ethernet0 interrupt for dma_priority_queue2
Ethernet0 interrupt for dma_priority_queue1
Ethernet1 interrupt
Ethernet1 interrupt for dma_priority_queue2
Ethernet1 interrupt for dma_priority_queue1
SDHC0 general interrupt
SDHC0 wakeup interrupt
2
AUDIOSS I S0 interrupt
2
AUDIOSS I S1 interrupt
2
AUDIOSS I S2 interrupt
Datasheet
63
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Core interrupt types
15
Core interrupt types
Table 15-1
Core interrupt types
Interrupt
Source
CPUIntIdx0_IRQn[27]
CPUIntIdx1_IRQn[27]
CPUIntIdx2_IRQn
CPUIntIdx3_IRQn
CPUIntIdx4_IRQn
CPUIntIdx5_IRQn
CPUIntIdx6_IRQn
CPUIntIdx7_IRQn
Internal0_IRQn
Internal1_IRQn
Internal2_IRQn
Internal3_IRQn
Internal4_IRQn
Internal5_IRQn
Internal6_IRQn
Internal7_IRQn
Power mode
DeepSleep
Description
CPU User Interrupt #0
CPU User Interrupt #1
CPU User Interrupt #2
CPU User Interrupt #3
CPU User Interrupt #4
CPU User Interrupt #5
CPU User Interrupt #6
CPU User Interrupt #7
Internal Software Interrupt #0
Internal Software Interrupt #1
Internal Software Interrupt #2
Internal Software Interrupt #3
Internal Software Interrupt #4
Internal Software Interrupt #5
Internal Software Interrupt #6
Internal Software Interrupt #7
0
1
2
3
4
5
6
7
8
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Active
Active
Active
Active
9
10
11
12
13
14
15
Active
Active
Active
Note
27.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM7 application.
Datasheet
64
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Trigger multiplexer
16
Trigger multiplexer
Green number in mux means Mux TriggerGroupNr.
[0:31]
[0:15]
[0:7]
[0:4]
[0:4]
1
[1:32]
[33:48]
[49:56]
[57:61]
[62:66]
[67]
P-DMA0: PDMA0_TR_OUT[0:142]
P-DMA1: PDMA1_TR_OUT[0:64]
M-DMA: MDMA_TR_OUT[0:7]
[0:16]
P-DMA0: PDMA0_TR_IN[0:15]
0
[0:23]
[0:3]
[68:91]
[92:95]
HSIOM: HSIOM_IO_INPUT[0:47]
CPUSS: FAULT_TR_OUT[0:3]
[0:2]
[0:2]
[1:3]
[4:6]
TCPWM[0]16: TCPWM0_16_TR_OUT0[0:2]
TCPWM[0]16M: TCPWM0_16M_TR_OUT0[0:2]
TCPWM[0]32: TCPWM0_32_TR_OUT0[0:2]
TCPWM[1]16: TCPWM1_16_TR_OUT0[0:83]
TCPWM[1]16M: TCPWM1_16M_TR_OUT0[0:11]
TCPWM[1]32: TCPWM1_32_TR_OUT0[0:12]
PASS: PASS_GEN_TR_OUT[0:5]
[0:2]
[7:9]
[0:29]
[0:11]
[0:12]
[0:5]
[10:39]
[40:51]
[52:64]
[65:70]
[71:72]
[73:76]
[0:16]
P-DMA0: PDMA0_TR_IN[16:31]
1
[0:1]
CPUSS: CTI_TR_OUT[0:1]
[0:3]
EVTGEN: EVTGEN_TR_OUT[0:15]
[0:15]
[0:31]
[1:16]
[17:48]
[0:16]
[0:7]
P-DMA1: PDMA1_TR_IN[0:15]
M-DMA: MDMA_TR_IN[0:7]
[30:83]
[24:47]
[49:102]
[103:126]
2
3
[0:2]
[0:2]
[1:3]
[4:6]
[0:31]
[0:15]
[0:7]
[0:2]
[0:2]
[0:2]
[0:15]
[0:5]
[0:6]
1
[1:32]
[33:48]
[49:56]
[57:59]
[60:62]
[63:65]
[66:81]
[82:87]
[88:94]
[95]
[0:11]
TCPWM[0]: TCPWM0_ALL_CNT_TR_IN[0:11]
4
SMIF: SMIF_TX_TR_OUT
SMIF: SMIF_RX_TR_OUT
1
[96]
AUDIOSS[0]: I2S0_TX_TR_OUT
AUDIOSS[0]: I2S0_RX_TR_OUT
:
[0],[0],...,[2],[2]
[97:102]
AUDIOSS[2]: I2S2_TX_TR_OUT
AUDIOSS[2]: I2S2_RX_TR_OUT
[0:2]
[0:2]
[0:2]
[0:83]
[0:11]
[0:12]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
1
[1:3]
[4:6]
[7:9]
[10:93]
[94:105]
[106:118]
[119:123]
[124:128]
[129:133]
[134:138]
[139:143]
[144:148]
[149:153]
[154:158]
[159]
CAN[0]: CAN0_DBG_TR_OUT[0:4]
CAN[0]: CAN0_FIFO0_TR_OUT[0:4]
CAN[0]: CAN0_FIFO1_TR_OUT[0:4]
CAN[1]: CAN1_DBG_TR_OUT[0:4]
CAN[1]: CAN1_FIFO0_TR_OUT[0:4]
CAN[1]: CAN1_FIFO1_TR_OUT[0:4]
CAN[0]: CAN0_TT_TR_OUT[0:4]
CAN[1]: CAN1_TT_TR_OUT[0:4]
[0:11]
TCPWM[1]: TCPWM1_ALL_CNT_TR_IN[0:11]
5
[4:11]
[160:167]
[0:15]
[1:16]
[17]
1
1
SCB[0]: SCB_TX_TR_OUT[0]
SCB[0]: SCB_RX_TR_OUT[0]
SCB[0]: SCB_I2C_SCL_TR_OUT[0]
(repeat from [1] to [9])
[18]
1
[19]
27
[20:46]
[47]
1
SCB[10]: SCB_TX_TR_OUT[10]
SCB[10]: SCB_RX_TR_OUT[10]
SCB[10]: SCB_I2C_SCL_TR_OUT[10]
1
[48]
[0:28]
TCPWM[1]: TCPWM1_ALL_CNT_TR_IN[12:40]
1
[49]
6
1
[50]
1
[51]
[0:5]
[0:47]
[0:1]
[0:3]
[52:57]
[58:105]
[106:107]
[108:111]
[0:31]
[0:11]
[0:12]
[0:7]
[1:32]
[33:44]
[45:57]
[58:65]
[66:68]
[0:11]
7
8
PASS: PASS_GEN_TR_IN[0:11]
[12:14]
[0:4]
[0:4]
1
[1:5]
[6:10]
[11]
[0:4]
[5:9]
CAN[0]: CAN0_TT_TR_IN[0:4]
CAN[1]: CAN1_TT_TR_IN[0:4]
[0]
[1]
HSIOM: HSIOM_IO_OUTPUT[0]
HSIOM: HSIOM_IO_OUTPUT[1]
[2:3]
[4]
CPUSS: CTI_TR_IN[0:1]
PERI: PERI_DEBUG_FREEZE_TR_IN
[1:5]
[6:10]
[5]
TR_GROUP10_OUTPUT[0:4]
TR_GROUP11_OUTPUT[0:4]
TR_GROUP12_OUTPUT[0:4]
PASS: PASS_DEBUG_FREEZE_TR_IN
SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[2]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[1]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0]
TCPWM[0]: TCPWM0_DEBUG_FREEZE_TR_IN
TCPWM[1]: TCPWM1_DEBUG_FREEZE_TR_IN
[6]
9
[11:15]
[7]
[8]
[9]
[10]
[11]
[0:142]
[0:10]
[0:10]
[0:10]
[0:4]
[1:143]
[144:154]
[155:165]
[166:176]
[177:181]
[182:186]
[187:191]
[192:196]
[197:201]
[202:206]
[207:211]
[212:216]
[217:218]
[219:222]
[223:238]
[0:4]
[0:4]
[0:4]
[0:4]
TR_GROUP9_INPUT[1:5]
10
[0:4]
[0:4]
[0:4]
[0:4]
[0:1]
[0:3]
[0:15]
[0:12]
[1:13]
[14:16]
[17:28]
[29:31]
[32:115]
[116:118]
[119]
[0:2]
[0:11]
[0:2]
[0:83]
[0:2]
1
[0:4]
TR_GROUP9_INPUT[6:10]
11
1
[120]
1
[121]
1
1
[122]
[123]
[0],[0],...,[2],[2]
[0:47]
[124:129]
[130:177]
[0:64]
[0:7]
[1:65]
[66:73]
[0:2]
[74:76]
TCPWM[0]16: TCPWM0_16_TR_OUT1[0:2]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[0:2]
TCPWM[0]32: TCPWM0_32_TR_OUT1[0:2]
TCPWM[1]16: TCPWM1_16_TR_OUT1[0:84]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[0:11]
TCPWM[1]32: TCPWM1_32_TR_OUT1[0:13]
[0:2]
[77:79]
[0:2]
[80:82]
[0:4]
12
TR_GROUP9_INPUT[11:15]
[0:83]
[0:11]
[0:12]
[0:5]
[83:166]
[167:178]
[179:191]
[192:197]
Figure 16-1
Trigger multiplexer group[28]
Note
28.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula
TRIG_{PREFIX(IN/OUT)}_{MUX_x}_{TRIG_LABEL} and the information provided in Table 17-1 on page 67, and Table 18-1 on
Datasheet
65
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Trigger multiplexer
One-To-One TriggerGroupNr = 0
P-DMA0: PDMA0_TR_IN[32]
CAN[0]: CAN0_DBG_TR_OUT[0]
CAN[0]: CAN0_FIFO0_TR_OUT[0]
CAN[0]: CAN0_FIFO1_TR_OUT[0]
CAN[0]: CAN0_DBG_TR_OUT[1]
CAN[0]: CAN0_FIFO0_TR_OUT[1]
CAN[0]: CAN0_FIFO1_TR_OUT[1]
CAN[0]: CAN0_DBG_TR_OUT[2]
CAN[0]: CAN0_FIFO0_TR_OUT[2]
CAN[0]: CAN0_FIFO1_TR_OUT[2]
CAN[0]: CAN0_DBG_TR_OUT[3]
CAN[0]: CAN0_FIFO0_TR_OUT[3]
CAN[0]: CAN0_FIFO1_TR_OUT[3]
CAN[0]: CAN0_DBG_TR_OUT[4]
CAN[0]: CAN0_FIFO0_TR_OUT[4]
CAN[0]: CAN0_FIFO1_TR_OUT[4]
P-DMA0: PDMA0_TR_IN[33]
P-DMA0: PDMA0_TR_IN[34]
P-DMA0: PDMA0_TR_IN[35]
P-DMA0: PDMA0_TR_IN[36]
P-DMA0: PDMA0_TR_IN[37]
P-DMA0: PDMA0_TR_IN[38]
P-DMA0: PDMA0_TR_IN[39]
P-DMA0: PDMA0_TR_IN[40]
P-DMA0: PDMA0_TR_IN[41]
P-DMA0: PDMA0_TR_IN[42]
P-DMA0: PDMA0_TR_IN[43]
P-DMA0: PDMA0_TR_IN[44]
P-DMA0: PDMA0_TR_IN[45]
P-DMA0: PDMA0_TR_IN[46]
One-To-One TriggerGroupNr = 1
PASS[0]: PASS0_CH_DONE_TO_PDMA0[0:31]
PASS[0]: PASS0_CH_DONE_TO_PDMA0[32:63]
PASS[0]: PASS0_CH_DONE_TO_PDMA0[64:95]
P-DMA0: PDMA0_TR_IN[47:78]
P-DMA0: PDMA0_TR_IN[79:110]
P-DMA0: PDMA0_TR_IN[111:142]
One-To-One TriggerGroupNr = 2
SCB[0]: SCB0_TX_TR_OUT
SCB[0]: SCB0_RX_TR_OUT
…
P-DMA1: PDMA1_TR_IN[16]
P-DMA1: PDMA1_TR_IN[17]
…
…
…
SCB[10]: SCB10_TX_TR_OUT
SCB[10]: SCB10_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[36]
P-DMA1: PDMA1_TR_IN[37]
One-To-One TriggerGroupNr = 3
SMIF: SMIF_TX_TR_OUT
SMIF: SMIF_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[53]
P-DMA1: PDMA1_TR_IN[54]
One-To-One TriggerGroupNr = 4
CAN[1]: CAN1_DBG_TR_OUT[0]
CAN[1]: CAN1_FIFO0_TR_OUT[0]
CAN[1]: CAN1_FIFO1_TR_OUT[0]
CAN[1]: CAN1_DBG_TR_OUT[1]
CAN[1]: CAN1_FIFO0_TR_OUT[1]
CAN[1]: CAN1_FIFO1_TR_OUT[1]
CAN[1]: CAN1_DBG_TR_OUT[2]
CAN[1]: CAN1_FIFO0_TR_OUT[2]
CAN[1]: CAN1_FIFO1_TR_OUT[2]
CAN[1]: CAN1_DBG_TR_OUT[3]
CAN[1]: CAN1_FIFO0_TR_OUT[3]
CAN[1]: CAN1_FIFO1_TR_OUT[3]
CAN[1]: CAN1_DBG_TR_OUT[4]
CAN[1]: CAN1_FIFO0_TR_OUT[4]
CAN[1]: CAN1_FIFO1_TR_OUT[4]
P-DMA1: PDMA1_TR_IN[38]
P-DMA1: PDMA1_TR_IN[39]
P-DMA1: PDMA1_TR_IN[40]
P-DMA1: PDMA1_TR_IN[41]
P-DMA1: PDMA1_TR_IN[42]
P-DMA1: PDMA1_TR_IN[43]
P-DMA1: PDMA1_TR_IN[44]
P-DMA1: PDMA1_TR_IN[45]
P-DMA1: PDMA1_TR_IN[46]
P-DMA1: PDMA1_TR_IN[47]
P-DMA1: PDMA1_TR_IN[48]
P-DMA1: PDMA1_TR_IN[49]
P-DMA1: PDMA1_TR_IN[50]
P-DMA1: PDMA1_TR_IN[51]
P-DMA1: PDMA1_TR_IN[52]
One-To-One TriggerGroupNr = 5
AUDIO: AUDIO0_TX_TR_OUT
AUDIO: AUDIO0_RX_TR_OUT
AUDIO: AUDIO1_TX_TR_OUT
AUDIO: AUDIO1_RX_TR_OUT
AUDIO: AUDIO2_TX_TR_OUT
AUDIO: AUDIO2_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[55]
P-DMA1: PDMA1_TR_IN[56]
P-DMA1: PDMA1_TR_IN[57]
P-DMA1: PDMA1_TR_IN[58]
P-DMA1: PDMA1_TR_IN[59]
P-DMA1: PDMA1_TR_IN[60]
One-To-One TriggerGroupNr = 6
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[0:3]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[4:31]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[32:35]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[36:63]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[64:67]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[68:95]
TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[0,3,6,9]
TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[0:27]
TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[1,4,7,10]
TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[28:55]
TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[2,5,8,11]
TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[56:83]
One-To-One TriggerGroupNr = 7
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[0,3,6,9]
TCPWM[1]16: TCPWM1_16_TR_OUT1[0:27]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[1,4,7,10]
TCPWM[1]16: TCPWM1_16_TR_OUT1[28:55]
PASS[0]: PASS0_CH_TR_IN[0..3]
PASS[0]: PASS0_CH_TR_IN[4:31]
PASS[0]: PASS0_CH_TR_IN[32:35]
PASS[0]: PASS0_CH_TR_IN[36:63]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[2,5,8,11]
TCPWM[1]16: TCPWM1_16_TR_OUT1[56:83]
PASS[0]: PASS0_CH_TR_IN[64:67]
PASS[0]: PASS0_CH_TR_IN[68:95]
One-To-One TriggerGroupNr = 8
P-DMA1: PDMA1_TR_OUT[38]
P-DMA1: PDMA1_TR_OUT[41]
P-DMA1: PDMA1_TR_OUT[44]
P-DMA1: PDMA1_TR_OUT[47]
P-DMA1: PDMA1_TR_OUT[50]
CAN[1]: CAN1_DBG_TR_ACK[0]
CAN[1]: CAN1_DBG_TR_ACK[1]
CAN[1]: CAN1_DBG_TR_ACK[2]
CAN[1]: CAN1_DBG_TR_ACK[3]
CAN[1]: CAN1_DBG_TR_ACK[4]
One-To-One TriggerGroupNr = 9
P-DMA0: PDMA0_TR_OUT[32]
P-DMA0: PDMA0_TR_OUT[35]
P-DMA0: PDMA0_TR_OUT[38]
P-DMA0: PDMA0_TR_OUT[41]
P-DMA0: PDMA0_TR_OUT[44]
CAN[0]: CAN0_DBG_TR_ACK[0]
CAN[0]: CAN0_DBG_TR_ACK[1]
CAN[0]: CAN0_DBG_TR_ACK[2]
CAN[0]: CAN0_DBG_TR_ACK[3]
CAN[0]: CAN0_DBG_TR_ACK[4]
One-To-One TriggerGroupNr = 12
P-DMA1: PDMA1_TR_OUT[61]
P-DMA1: PDMA1_TR_OUT[62]
P-DMA1: PDMA1_TR_IN[63]
P-DMA1: PDMA1_TR_IN[64]
Figure 16-2
Triggers one-to-one[29]
Note
29.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula TRIG_{PREFIX(IN_1TO1/OUT_1-
TO1)}_{x}_{TRIG_LABEL} and the information provided in Table 19-1 on page 72.
Datasheet
66
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
17
Triggers group inputs
Table 17-1
Input
Trigger inputs
Trigger
Description
MUX Group 0: P-DMA0 trigger multiplexer
1:32[30] PDMA0_TR_OUT[0:31]
Allow P-DMA0 to chain to itself. Channels 0 - 31 are dedicated for
chaining
33:48
PDMA1_TR_OUT[0:15]
Cross connections from P-DMA1 to P-DMA0, Channels 0-15 are
used
49:56
57:61
62:66
68:91
92:95
MDMA_TR_OUT[0:7]
CAN0_TT_TR_OUT[0:4]
CAN1_TT_TR_OUT[0:4]
HSIOM_IO_INPUT[0:23]
FAULT_TR_OUT[0:3]
Cross connections from M-DMA0 to P-DMA0
CAN0 Time Trigger Sync Outputs
CAN1 Time Trigger Sync Outputs
I/O Inputs
Fault events
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
1:3
TCPWM0_16_TR_OUT0[0:2]
16-bit TCPWM0 counters
4:6
TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
7:9
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16_TR_OUT0[0:29]
TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
TCPWM1_32_TR_OUT0[0:12]
PASS_GEN_TR_OUT[0:5]
CTI_TR_OUT[0:1]
32-bit TCPWM0 counters
16-bit TCPWM1 counters
10:39
40:51
52:64
65:70
71:72
73:76
32-bit TCPWM1 counters
PASS SAR events
Trace events
EVTGEN_TR_OUT[0:3]
Event generator triggers
MUX Group 2: P-DMA1 trigger multiplexer
1:16
PDMA1_TR_OUT[0:15]
Allow P-DMA1 to chain to itself. Channels 0–15 are dedicated for
chaining
17:48
PDMA0_TR_OUT[0:31]
Cross connections from P-DMA0 to P-DMA1, channels 0–31 are
used.
49:102 TCPWM1_16_TR_OUT0[30:83] 16-bit TCPWM1 counters
103:126 HSIOM_IO_INPUT[24:47]
I/O Inputs
MUX Group 3: M-DMA0 trigger multiplexer
1:3
4:6
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
16-bit TCPWM0 counters
MUX Group 4: TCPWM0 Loop back trigger multiplexer
1:32
PDMA0_TR_OUT[0:31]
PDMA1_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
General-purpose P-DMA0 triggers
General-purpose P-DMA1 triggers
M-DMA0 triggers
33:48
49:56
57:59
60:62
63:65
66:81
16-bit TCPWM0 counters
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16_TR_OUT0[0:15]
32-bit TCPWM0 counters
16-bit TCPWM1 counters
Note
30.“x:y” depicts a range starting from ‘x’ through ‘y’.
Datasheet
67
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Trigger
TCPWM1_16M_TR_OUT0[0:5] 16-bit Motor enhanced TCPWM1 counters
Input
82:87
88:94
95
96
97
98
99
100
101
102
Description
TCPWM1_32_TR_OUT0[0:6]
SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
I2S0_TX_TR_OUT
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
I2S2_RX_TR_OUT
32-bit TCPWM1 counters
SMIF0 TX trigger
SMIF0 RX trigger
I2S0 TX trigger
I2S0 RX trigger
I2S1 TX trigger
I2S1 RX trigger
I2S2 TX trigger
I2S2 RX trigger
MUX Group 5: TCPWM1 Loop back trigger multiplexer
1:3
4:6
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
16-bit TCPWM0 counters
7:9
10:93
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16_TR_OUT0[0:83]
32-bit TCPWM0 counters
16-bit TCPWM1 counters
94:105 TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
106:118 TCPWM1_32_TR_OUT0[0:12]
119:123 CAN0_DBG_TR_OUT[0:4]
124:128 CAN0_FIFO0_TR_OUT[0:4]
129:133 CAN0_FIFO1_TR_OUT[0:4]
134:138 CAN1_DBG_TR_OUT[0:4]
139:143 CAN1_FIFO0_TR_OUT[0:4]
144:148 CAN1_FIFO1_TR_OUT[0:4]
149:153 CAN0_TT_TR_OUT[0:4]
154:158 CAN1_TT_TR_OUT[0:4]
160:167 EVTGEN_TR_OUT[4:11]
MUX Group 6: TCPWM1 trigger Multiplexer
32-bit TCPWM1 counters
CAN0 M-DMA0 events
CAN0 FIFO0 events
CAN0 FIFO1 events
CAN1 M-DMA0 events
CAN1 FIFO0 events
CAN1 FIFO1 events
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
Event generator triggers
1:16
17
18
19
20
21
22
23
24
25
26
27
28
29
TCPWM1_16_TR_OUT1[0:15]
SCB_TX_TR_OUT[0]
SCB_RX_TR_OUT[0]
SCB_I2C_SCL_TR_OUT[0]
SCB_TX_TR_OUT[1]
SCB_RX_TR_OUT[1]
SCB_I2C_SCL_TR_OUT[1]
SCB_TX_TR_OUT[2]
SCB_RX_TR_OUT[2]
SCB_I2C_SCL_TR_OUT[2]
SCB_TX_TR_OUT[3]
SCB_RX_TR_OUT[3]
16-bit TCPWM1 counters
SCB0 TX trigger
SCB0 RX trigger
SCB0 I2C trigger
SCB1 TX trigger
SCB1 RX trigger
SCB1 I2C trigger
SCB2 TX trigger
SCB2 RX trigger
SCB2 I2C trigger
SCB3 TX trigger
SCB3 RX trigger
SCB3 I2C trigger
SCB4 TX trigger
SCB_I2C_SCL_TR_OUT[3]
SCB_TX_TR_OUT[4]
Datasheet
68
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Input
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Trigger
SCB_RX_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[4]
SCB_TX_TR_OUT[5]
SCB_RX_TR_OUT[5]
SCB_I2C_SCL_TR_OUT[5]
SCB_TX_TR_OUT[6]
SCB_RX_TR_OUT[6]
SCB_I2C_SCL_TR_OUT[6]
SCB_TX_TR_OUT[7]
SCB_RX_TR_OUT[7]
SCB_I2C_SCL_TR_OUT[7]
SCB_TX_TR_OUT[8]
SCB_RX_TR_OUT[8]
SCB_I2C_SCL_TR_OUT[8]
SCB_TX_TR_OUT[9]
SCB_RX_TR_OUT[9]
SCB_I2C_SCL_TR_OUT[9]
SCB_TX_TR_OUT[10]
SCB_RX_TR_OUT[10]
SCB_I2C_SCL_TR_OUT[10]
PASS_GEN_TR_OUT[0:5]
Description
SCB4 RX trigger
SCB4 I2C trigger
SCB5 TX trigger
SCB5 RX trigger
SCB5 I2C trigger
SCB6 TX trigger
SCB6 RX trigger
SCB6 I2C trigger
SCB7 TX trigger
SCB7 RX trigger
SCB7 I2C trigger
SCB8 TX trigger
SCB8 RX trigger
SCB8 I2C trigger
SCB9 TX trigger
SCB9 RX trigger
SCB9 I2C trigger
SCB10 TX trigger
SCB10 RX trigger
SCB10 I2C trigger
PASS SAR ADC events
I/O Inputs
46
47
48
49
52:57
58:105 HSIOM_IO_INPUT[0:47]
106:107 CTI_TR_IN[0:1]
108:111 FAULT_TR_OUT[0:3]
MUX Group 7: PASS trigger multiplexer
CPUSS CTI Trace events
Fault events
1:31
PDMA0_TR_OUT[0:31]
General purpose P-DMA0 triggers
32:44
45:57
58:65
66:68
TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
TCPWM1_32_TR_OUT0[0:12]
HSIOM_IO_INPUT[0:7]
32-bit TCPWM1 counters
I/O Inputs
EVTGEN_TR_OUT[12:14]
Event generator triggers
MUX Group 8: CAN TT Sync
1:5
6:10
CAN0_TT_TR_OUT[0:4]
CAN1_TT_TR_OUT[0:4]
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
MUX Group 9: Debug multiplexer
1:5
6:10
11:15
TR_GROUP10_OUTPUT[0:4]
TR_GROUP11_OUTPUT[0:4]
TR_GROUP12_OUTPUT[0:4]
Output from debug reduction multiplexer #1
Output from debug reduction multiplexer #2
Output from debug reduction multiplexer #3
MUX Group 10: Debug Reduction #1
1:143 PDMA0_TR_OUT[0:142]
144:154 SCB_TX_TR_OUT[0:10]
155:165 SCB_RX_TR_OUT[0:10]
General purpose P-DMA0 triggers
SCB TX triggers
SCB RX triggers
Datasheet
69
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
Table 17-1
Input
Trigger inputs (continued)
Trigger
Description
166:176 SCB_I2C_SCL_TR_OUT[0:10]
177:181 CAN0_DBG_TR_OUT[0:4]
182:186 CAN0_FIFO0_TR_OUT[0:4]
187:191 CAN0_FIFO1_TR_OUT[0:4]
192:196 CAN0_TT_TR_OUT[0:4]
197:201 CAN1_DBG_TR_OUT[0:4]
202:206 CAN1_FIFO0_TR_OUT[0:4]
207:211 CAN1_FIFO1_TR_OUT[0:4]
212:216 CAN1_TT_TR_OUT[0:4]
217:218 CTI_TR_OUT[0:1]
SCB I2C triggers
CAN0 M-DMA0
CAN0 FIFO0
CAN0 FIFO1
CAN0 TT Sync Outputs
CAN1 M-DMA0
CAN1 FIFO0
CAN1 FIFO1
CAN1 TT Sync Outputs
CPUSS CTI Trace events
Fault events
219:222 FAULT_TR_OU[0:3]
223:238 EVTGEN_TR_OUT[0:15]
MUX Group 11: Debug Reduction #2
EVTGEN Triggers
1:13
14:16
17:28
29:31
TCPWM1_32_TR_OUT0[0:12]
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
32-bit TCPWM1 counters
32-bit TCPWM0 counters
32:115 TCPWM1_16_TR_OUT0[0:83]
116:118 TCPWM0_16_TR_OUT0[0:2]
16-bit TCPWM1 counters
16-bit TCPWM0 counters
SMIF TX trigger
SMIF RX trigger
I2S0 TX trigger
119
120
124
125
126
127
128
129
SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
I2S0_TX_TR_OUT
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
I2S2_RX_TR_OUT
I2S0 RX trigger
I2S1 TX trigger
I2S1 RX trigger
I2S2 TX trigger
I2S2 RX trigger
130:177 HSIOM_IO_INPUT[0:47]
I/O inputs
MUX Group 12: Debug Reduction #3
1:65
PDMA1_TR_OUT[0:64]
MDMA_TR_OUT[0:7]
TCPWM0_16_TR_OUT1[0:2]
TCPWM0_16M_TR_OUT1[0:2] 16-bit Motor enhanced TCPWM0 counters
TCPWM0_32_TR_OUT1[0:2]
General purpose P-DMA1 triggers
M-DMA0 triggers
16-bit TCPWM0 counters
66:73
74:76
77:79
80:82
32-bit TCPWM0 counters
16-bit TCPWM1 counters
83:166 TCPWM1_16_TR_OUT1[0:83]
167:178 TCPWM1_16M_TR_OUT1[0:11] 16-bit Motor enhanced TCPWM1 counters
179:191 TCPWM1_32_TR_OUT1[0:12]
192:197 PASS_GEN_TR_OUT[0:5]
32-bit TCPWM1 counters
PASS SAR ADC events
Datasheet
70
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group outputs
18
Triggers group outputs
Table 18-1
Trigger outputs
Output
MUX Group 0: P-DMA0 trigger multiplexer
0:15 PDMA0_TR_IN[0:15]
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
0:15 PDMA0_TR_IN[16:31]
MUX Group 2: P-DMA1 trigger multiplexer
0:15 PDMA1_TR_IN[0:15]
MUX Group 3: M-DMA0 trigger multiplexer
0:7 M-DMA_TR_IN[0:7]
MUX Group 4: TCPWM0 Loop back trigger multiplexer
0:11 TCPWM0_ALL_CNT_TR_IN[0:11]
MUX Group 5: TCPWM1 Loop back trigger multiplexer
0:11 TCPWM1_ALL_CNT_TR_IN[0:11]
MUX Group 6: TCPWM1 trigger Multiplexer
Trigger
Description
Triggers to P-DMA0[0:15]
Triggers to P-DMA0[16:31]
Triggers to P-DMA1
Triggers to M-DMA0
Triggers to TCPWM0
Triggers to TCPWM1
Triggers to TCPWM1
Triggers to PASS SAR ADCs
0:28
TCPWM1_ALL_CNT_TR_IN[12:40]
MUX Group 7: PASS trigger multiplexer
0:11
PASS_GEN_TR_IN[0:11]
MUX Group 8: CAN TT Sync
0:4
5:9
CAN0_TT_TR_IN[0:4]
CAN1_TT_TR_IN[0:4]
CAN0 TT Sync Inputs
CAN1 TT Sync Inputs
MUX Group 9: Debug multiplexer
0
1
HSIOM_IO_OUTPUT[0]
HSIOM_IO_OUTPUT[1]
To HSIOM as an output
To HSIOM as an output
2:3
4
5
CTI_TR_IN[0:1]
To the Cross Trigger system
Signal to Freeze PERI operation
Signal to Freeze SAR ADC operation
Signal to Freeze WDT operation
PERI_DEBUG_FREEZE_TR_IN
PASS_DEBUG_FREEZE_TR_IN
SRSS_WDT_DEBUG_FREEZE_TR_IN
6
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[2]
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[1]
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[0]
7
8
9
Signal to Freeze MCWDT2 operation
Signal to Freeze MCWDT1 operation
Signal to Freeze MCWDT0 operation
10
11
TCPWM0_DEBUG_FREEZE_TR_IN
TCPWM1_DEBUG_FREEZE_TR_IN
Signal to Freeze TCPWM0 operation
Signal to Freeze TCPWM1 operation
MUX Group 10: Debug Reduction #1
0:4
TR_GROUP9_INPUT[1:5]
To main debug multiplexer
To main debug multiplexer
To main debug multiplexer
MUX Group 11: Debug Reduction #2
0:4
TR_GROUP9_INPUT[6:10]
MUX Group 12: Debug Reduction #3
0:4
TR_GROUP9_INPUT[11:15]
Datasheet
71
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
19
Triggers one-to-one
Table 19-1
Triggers 1:1
Input
Trigger In
Trigger Out
Description
MUX Group 0: CAN0 to P-DMA0 Triggers
0
1
CAN0_DBG_TR_OUT[0]
CAN0_FIFO0_TR_OUT[0]
CAN0_FIFO1_TR_OUT[0]
CAN0_DBG_TR_OUT[1]
CAN0_FIFO0_TR_OUT[1]
CAN0_FIFO1_TR_OUT[1]
CAN0_DBG_TR_OUT[2]
CAN0_FIFO0_TR_OUT[2]
CAN0_FIFO1_TR_OUT[2]
CAN0_DBG_TR_OUT[3]
CAN0_FIFO0_TR_OUT[3]
CAN0_FIFO1_TR_OUT[3]
CAN0_DBG_TR_OUT[4]
CAN0_FIFO0_TR_OUT[4]
CAN0_FIFO1_TR_OUT[4]
PDMA0_TR_IN[32]
CAN0, Channel #0 P-DMA0 trigger
PDMA0_TR_IN[33]
PDMA0_TR_IN[34]
PDMA0_TR_IN[35]
PDMA0_TR_IN[36]
PDMA0_TR_IN[37]
PDMA0_TR_IN[38]
PDMA0_TR_IN[39]
PDMA0_TR_IN[40]
PDMA0_TR_IN[41]
PDMA0_TR_IN[42]
PDMA0_TR_IN[43]
PDMA0_TR_IN[44]
PDMA0_TR_IN[45]
PDMA0_TR_IN[46]
CAN0, Channel #0 FIFO0 trigger
CAN0, Channel #0 FIFO1 trigger
CAN0, Channel #1 P-DMA0 trigger
CAN0, Channel #1 FIFO0 trigger
CAN0, Channel #1 FIFO1 trigger
CAN0, Channel #2 P-DMA0 trigger
CAN0, Channel #2 FIFO0 trigger
CAN0, Channel #2 FIFO1 trigger
CAN0, Channel #3 P-DMA0 trigger
CAN0, Channel #3 FIFO0 trigger
CAN0, Channel #3 FIFO1 trigger
CAN0, Channel #4 P-DMA0 trigger
CAN0, Channel #4 FIFO0 trigger
CAN0, Channel #4 FIFO1 trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
MUX Group 1: PASS SARx to P-DMA0 direct connect
0:31
32:63
64:95
PASS0_CH_DONE_TR_OUT[0:31]
PASS0_CH_DONE_TR_OUT[32:63]
PASS0_CH_DONE_TR_OUT[64:95]
PDMA0_TR_IN[47:78]
PDMA0_TR_IN[79:110]
PDMA0_TR_IN[111:142]
PASS SAR0 [0:31] to P-DMA0 direct connect
PASS SAR1 [0:31] to P-DMA0 direct connect
PASS SAR2 [0:31] to P-DMA0 direct connect
MUX Group 2: SCBx to P-DMA1 Triggers
0
1
SCB0_TX_TR_OUT
SCB0_RX_TR_OUT
SCB1_TX_TR_OUT
SCB1_RX_TR_OUT
SCB2_TX_TR_OUT
SCB2_RX_TR_OUT
SCB3_TX_TR_OUT
SCB3_RX_TR_OUT
SCB4_TX_TR_OUT
SCB4_RX_TR_OUT
SCB5_TX_TR_OUT
SCB5_RX_TR_OUT
SCB6_TX_TR_OUT
SCB6_RX_TR_OUT
SCB7_TX_TR_OUT
SCB7_RX_TR_OUT
SCB8_TX_TR_OUT
SCB8_RX_TR_OUT
SCB9_TX_TR_OUT
SCB9_RX_TR_OUT
SCB10_TX_TR_OUT
SCB10_RX_TR_OUT
PDMA1_TR_IN[16]
PDMA1_TR_IN[17]
PDMA1_TR_IN[18]
PDMA1_TR_IN[19]
PDMA1_TR_IN[20]
PDMA1_TR_IN[21]
PDMA1_TR_IN[22]
PDMA1_TR_IN[23]
PDMA1_TR_IN[24]
PDMA1_TR_IN[25]
PDMA1_TR_IN[26]
PDMA1_TR_IN[27]
PDMA1_TR_IN[28]
PDMA1_TR_IN[29]
PDMA1_TR_IN[30]
PDMA1_TR_IN[31]
PDMA1_TR_IN[32]
PDMA1_TR_IN[33]
PDMA1_TR_IN[34]
PDMA1_TR_IN[35]
PDMA1_TR_IN[36]
PDMA1_TR_IN[37]
SCB0 to P-DMA1 Trigger
SCB0 to P-DMA1 Trigger
SCB1 to P-DMA1 Trigger
SCB1 to P-DMA1 Trigger
SCB2 to P-DMA1 Trigger
SCB2 to P-DMA1 Trigger
SCB3 to P-DMA1 Trigger
SCB3 to P-DMA1 Trigger
SCB4 to P-DMA1 Trigger
SCB4 to P-DMA1 Trigger
SCB5 to P-DMA1 Trigger
SCB5 to P-DMA1 Trigger
SCB6 to P-DMA1 Trigger
SCB6 to P-DMA1 Trigger
SCB7 to P-DMA1 Trigger
SCB7 to P-DMA1 Trigger
SCB8 to P-DMA1 Trigger
SCB8 to P-DMA1 Trigger
SCB9 to P-DMA1 Trigger
SCB9 to P-DMA1 Trigger
SCB10 to P-DMA1 Trigger
SCB10 to P-DMA1 Trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Datasheet
72
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
MUX Group 3: SMIF0 to P-DMA1 Triggers
0
1
SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
PDMA1_TR_IN[53]
SMIF0 to P-DMA1 Trigger
SMIF0 to P-DMA1 Trigger
PDMA1_TR_IN[54]
MUX Group 4: CAN1 to P-DMA1 triggers
0
1
CAN1_DBG_TR_OUT[0]
CAN1_FIFO0_TR_OUT[0]
CAN1_FIFO1_TR_OUT[0]
CAN1_DBG_TR_OUT[1]
CAN1_FIFO0_TR_OUT[1]
CAN1_FIFO1_TR_OUT[1]
CAN1_DBG_TR_OUT[2]
CAN1_FIFO0_TR_OUT[2]
CAN1_FIFO1_TR_OUT[2]
CAN1_DBG_TR_OUT[3]
CAN1_FIFO0_TR_OUT[3]
CAN1_FIFO1_TR_OUT[3]
CAN1_DBG_TR_OUT[4]
CAN1_FIFO0_TR_OUT[4]
PDMA1_TR_IN[38]
PDMA1_TR_IN[39]
PDMA1_TR_IN[40]
PDMA1_TR_IN[41]
PDMA1_TR_IN[42]
PDMA1_TR_IN[43]
PDMA1_TR_IN[44]
PDMA1_TR_IN[45]
PDMA1_TR_IN[46]
PDMA1_TR_IN[47]
PDMA1_TR_IN[48]
PDMA1_TR_IN[49]
PDMA1_TR_IN[50]
PDMA1_TR_IN[51]
PDMA1_TR_IN[52]
CAN1 Channel #0 P-DMA1 trigger
CAN1 Channel #0 FIFO0 trigger
CAN1 Channel #0 FIFO1 trigger
CAN1 Channel #1 P-DMA1 trigger
CAN1 Channel #1 FIFO0 trigger
CAN1 Channel #1 FIFO1 trigger
CAN1 Channel #2 P-DMA1 trigger
CAN1 Channel #2 FIFO0 trigger
CAN1 Channel #2 FIFO1 trigger
CAN1 Channel #3 P-DMA1 trigger
CAN1 Channel #3 FIFO0 trigger
CAN1 Channel #3 FIFO1 trigger
CAN1 Channel #4 P-DMA1 trigger
CAN1 Channel #4 FIFO0 trigger
CAN1 Channel #4 FIFO1 trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
CAN1_FIFO1_TR_OUT[4]
2
MUX Group 5: I Sx to P-DMA1 Triggers
2
0
1
2
3
4
5
AUDIO0_TX_TR_OUT
AUDIO0_RX_TR_OUT
AUDIO1_TX_TR_OUT
AUDIO1_RX_TR_OUT
AUDIO2_TX_TR_OUT
AUDIO2_RX_TR_OUT
PDMA1_TR_IN[55]
PDMA1_TR_IN[56]
PDMA1_TR_IN[57]
PDMA1_TR_IN[58]
PDMA1_TR_IN[59]
PDMA1_TR_IN[60]
I S0 TX to P-DMA1 trigger
2
I S0 RX to P-DMA1 trigger
2
I S1 TX to P-DMA1 trigger
2
I S1 RX to P-DMA1 trigger
2
I S2 TX to P-DMA1 trigger
2
I S2 RX to P-DMA1 trigger
MUX Group 6: PASS SARx to TCPWM1 direct connect
[31]
0
1
PASS0_CH_RANGEVIO_TR_OUT[0]
PASS0_CH_RANGEVIO_TR_OUT[1]
PASS0_CH_RANGEVIO_TR_OUT[2]
PASS0_CH_RANGEVIO_TR_OUT[3]
PASS0_CH_RANGEVIO_TR_OUT[4]
PASS0_CH_RANGEVIO_TR_OUT[5]
PASS0_CH_RANGEVIO_TR_OUT[6]
PASS0_CH_RANGEVIO_TR_OUT[7]
PASS0_CH_RANGEVIO_TR_OUT[8]
PASS0_CH_RANGEVIO_TR_OUT[9]
PASS0_CH_RANGEVIO_TR_OUT[10]
PASS0_CH_RANGEVIO_TR_OUT[11]
PASS0_CH_RANGEVIO_TR_OUT[12]
PASS0_CH_RANGEVIO_TR_OUT[13]
PASS0_CH_RANGEVIO_TR_OUT[14]
TCPWM1_16M_ONE_CNT_TR_IN[0]
TCPWM1_16M_ONE_CNT_TR_IN[3]
TCPWM1_16M_ONE_CNT_TR_IN[6]
TCPWM1_16M_ONE_CNT_TR_IN[9]
TCPWM1_16_ONE_CNT_TR_IN[0]
TCPWM1_16_ONE_CNT_TR_IN[1]
TCPWM1_16_ONE_CNT_TR_IN[2]
TCPWM1_16_ONE_CNT_TR_IN[3]
TCPWM1_16_ONE_CNT_TR_IN[4]
TCPWM1_16_ONE_CNT_TR_IN[5]
TCPWM1_16_ONE_CNT_TR_IN[6]
TCPWM1_16_ONE_CNT_TR_IN[7]
TCPWM1_16_ONE_CNT_TR_IN[8]
TCPWM1_16_ONE_CNT_TR_IN[9]
TCPWM1_16_ONE_CNT_TR_IN[10]
SAR0 ch#0 , range violation to TCPWM1 Group #1 Counter #00 trig = 2
SAR0 ch#1, range violation to TCPWM1 Group #1 Counter #03 trig = 2
SAR0 ch#2, range violation to TCPWM1 Group #1 Counter #06 trig = 2
SAR0 ch#3, range violation to TCPWM1 Group #1 Counter #09 trig = 2
SAR0 ch#4, range violation to TCPWM1 Group #0 Counter #00 trig = 2
SAR0 ch#5, range violation to TCPWM1 Group #0 Counter #01 trig = 2
SAR0 ch#6, range violation to TCPWM1 Group #0 Counter #02 trig = 2
SAR0 ch#7, range violation to TCPWM1 Group #0 Counter #03 trig = 2
SAR0 ch#8, range violation to TCPWM1 Group #0 Counter #04 trig = 2
SAR0 ch#9, range violation to TCPWM1 Group #0 Counter #05 trig = 2
SAR0 ch#10, range violation to TCPWM1 Group #0 Counter #06 trig = 2
SAR0 ch#11, range violation to TCPWM1 Group #0 Counter #07 trig = 2
SAR0 ch#12, range violation to TCPWM1 Group #0 Counter #08 trig = 2
SAR0 ch#13, range violation to TCPWM1 Group #0 Counter #09 trig = 2
SAR0 ch#14, range violation to TCPWM1 Group #0 Counter #10 trig = 2
2
3
4
5
6
7
8
9
10
11
12
13
14
Note
31.Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to max 31)
Datasheet
73
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
PASS0_CH_RANGEVIO_TR_OUT[15]
PASS0_CH_RANGEVIO_TR_OUT[16]
TCPWM1_16_ONE_CNT_TR_IN[11]
SAR0 ch#15, range violation to TCPWM1 Group #0 Counter #11 trig = 2
TCPWM1_16_ONE_CNT_TR_IN[12]
TCPWM1_16_ONE_CNT_TR_IN[13]
TCPWM1_16_ONE_CNT_TR_IN[14]
TCPWM1_16_ONE_CNT_TR_IN[15]
TCPWM1_16_ONE_CNT_TR_IN[16]
TCPWM1_16_ONE_CNT_TR_IN[17]
TCPWM1_16_ONE_CNT_TR_IN[18]
TCPWM1_16_ONE_CNT_TR_IN[19]
TCPWM1_16_ONE_CNT_TR_IN[20]
TCPWM1_16_ONE_CNT_TR_IN[21]
TCPWM1_16_ONE_CNT_TR_IN[22]
TCPWM1_16_ONE_CNT_TR_IN[23]
TCPWM1_16_ONE_CNT_TR_IN[24]
TCPWM1_16_ONE_CNT_TR_IN[25]
TCPWM1_16_ONE_CNT_TR_IN[26]
TCPWM1_16_ONE_CNT_TR_IN[27]
TCPWM1_16M_ONE_CNT_TR_IN[1]
TCPWM1_16M_ONE_CNT_TR_IN[4]
TCPWM1_16M_ONE_CNT_TR_IN[7]
TCPWM1_16M_ONE_CNT_TR_IN[10]
TCPWM1_16_ONE_CNT_TR_IN[28]
TCPWM1_16_ONE_CNT_TR_IN[29]
TCPWM1_16_ONE_CNT_TR_IN[30]
TCPWM1_16_ONE_CNT_TR_IN[31]
TCPWM1_16_ONE_CNT_TR_IN[32]
TCPWM1_16_ONE_CNT_TR_IN[33]
TCPWM1_16_ONE_CNT_TR_IN[34]
TCPWM1_16_ONE_CNT_TR_IN[35]
TCPWM1_16_ONE_CNT_TR_IN[36]
TCPWM1_16_ONE_CNT_TR_IN[37]
TCPWM1_16_ONE_CNT_TR_IN[38]
TCPWM1_16_ONE_CNT_TR_IN[39]
TCPWM1_16_ONE_CNT_TR_IN[40]
TCPWM1_16_ONE_CNT_TR_IN[41]
TCPWM1_16_ONE_CNT_TR_IN[42]
TCPWM1_16_ONE_CNT_TR_IN[43]
TCPWM1_16_ONE_CNT_TR_IN[44]
TCPWM1_16_ONE_CNT_TR_IN[45]
TCPWM1_16_ONE_CNT_TR_IN[46]
TCPWM1_16_ONE_CNT_TR_IN[47]
TCPWM1_16_ONE_CNT_TR_IN[48]
TCPWM1_16_ONE_CNT_TR_IN[49]
TCPWM1_16_ONE_CNT_TR_IN[50]
TCPWM1_16_ONE_CNT_TR_IN[51]
SAR0 ch#16, range violation to TCPWM1 Group #0 Counter #12 trig = 2
SAR0 ch#17, range violation to TCPWM1 Group #0 Counter #13 trig = 2
SAR0 ch#18, range violation to TCPWM1 Group #0 Counter #14 trig = 2
SAR0 ch#19, range violation to TCPWM1 Group #0 Counter #15 trig = 2
SAR0 ch#20, range violation to TCPWM1 Group #0 Counter #16 trig = 2
SAR0 ch#21, range violation to TCPWM1 Group #0 Counter #17 trig = 2
SAR0 ch#22, range violation to TCPWM1 Group #0 Counter #18 trig = 2
SAR0 ch#23, range violation to TCPWM1 Group #0 Counter #19 trig = 2
SAR0 ch#24, range violation to TCPWM1 Group #0 Counter #20 trig = 2
SAR0 ch#25, range violation to TCPWM1 Group #0 Counter #21 trig = 2
SAR0 ch#26, range violation to TCPWM1 Group #0 Counter #22 trig = 2
SAR0 ch#27, range violation to TCPWM1 Group #0 Counter #23 trig = 2
SAR0 ch#28, range violation to TCPWM1 Group #0 Counter #24 trig = 2
SAR0 ch#29, range violation to TCPWM1 Group #0 Counter #25 trig = 2
SAR0 ch#30, range violation to TCPWM1 Group #0 Counter #26 trig = 2
SAR0 ch#31, range violation to TCPWM1 Group #0 Counter #27 trig = 2
SAR1 ch#0, range violation to TCPWM1 Group #1 Counter #01 trig = 2
SAR1 ch#1, range violation to TCPWM1 Group #1 Counter #04 trig = 2
SAR1 ch#2, range violation to TCPWM1 Group #1 Counter #07 trig = 2
SAR1 ch#3, range violation to TCPWM1 Group #1 Counter #10 trig = 2
SAR1 ch#4, range violation to TCPWM1 Group #0 Counter #28 trig = 2
SAR1 ch#5, range violation to TCPWM1 Group #0 Counter #29 trig = 2
SAR1 ch#6, range violation to TCPWM1 Group #0 Counter #30 trig = 2
SAR1 ch#7, range violation to TCPWM1 Group #0 Counter #31 trig = 2
SAR1 ch#8, range violation to TCPWM1 Group #0 Counter #32 trig = 2
SAR1 ch#9, range violation to TCPWM1 Group #0 Counter #33 trig = 2
SAR1 ch#10, range violation to TCPWM1 Group #0 Counter #34 trig = 2
SAR1 ch#11, range violation to TCPWM1 Group #0 Counter #35 trig = 2
SAR1 ch#12, range violation to TCPWM1 Group #0 Counter #36 trig = 2
SAR1 ch#13, range violation to TCPWM1 Group #0 Counter #37 trig = 2
SAR1 ch#14, range violation to TCPWM1 Group #0 Counter #38 trig = 2
SAR1 ch#15, range violation to TCPWM1 Group #0 Counter #39 trig = 2
SAR1 ch#16, range violation to TCPWM1 Group #0 Counter #40 trig = 2
SAR1 ch#17, range violation to TCPWM1 Group #0 Counter #41 trig = 2
SAR1 ch#18, range violation to TCPWM1 Group #0 Counter #42 trig = 2
SAR1 ch#19, range violation to TCPWM1 Group #0 Counter #43 trig = 2
SAR1 ch#20, range violation to TCPWM1 Group #0 Counter #44 trig = 2
SAR1 ch#21, range violation to TCPWM1 Group #0 Counter #45 trig = 2
SAR1 ch#22, range violation to TCPWM1 Group #0 Counter #46 trig = 2
SAR1 ch#23, range violation to TCPWM1 Group #0 Counter #47 trig = 2
SAR1 ch#24, range violation to TCPWM1 Group #0 Counter #48 trig = 2
SAR1 ch#25, range violation to TCPWM1 Group #0 Counter #49 trig = 2
SAR1 ch#26, range violation to TCPWM1 Group #0 Counter #50 trig = 2
SAR1 ch#27, range violation to TCPWM1 Group #0 Counter #51 trig = 2
PASS0_CH_RANGEVIO_TR_OUT[17]
PASS0_CH_RANGEVIO_TR_OUT[18]
PASS0_CH_RANGEVIO_TR_OUT[19]
PASS0_CH_RANGEVIO_TR_OUT[20]
PASS0_CH_RANGEVIO_TR_OUT[21]
PASS0_CH_RANGEVIO_TR_OUT[22]
PASS0_CH_RANGEVIO_TR_OUT[23]
PASS0_CH_RANGEVIO_TR_OUT[24]
PASS0_CH_RANGEVIO_TR_OUT[25]
PASS0_CH_RANGEVIO_TR_OUT[26]
PASS0_CH_RANGEVIO_TR_OUT[27]
PASS0_CH_RANGEVIO_TR_OUT[28]
PASS0_CH_RANGEVIO_TR_OUT[29]
PASS0_CH_RANGEVIO_TR_OUT[30]
PASS0_CH_RANGEVIO_TR_OUT[31]
PASS0_CH_RANGEVIO_TR_OUT[32]
PASS0_CH_RANGEVIO_TR_OUT[33]
PASS0_CH_RANGEVIO_TR_OUT[34]
PASS0_CH_RANGEVIO_TR_OUT[35]
PASS0_CH_RANGEVIO_TR_OUT[36]
PASS0_CH_RANGEVIO_TR_OUT[37]
PASS0_CH_RANGEVIO_TR_OUT[38]
PASS0_CH_RANGEVIO_TR_OUT[39]
PASS0_CH_RANGEVIO_TR_OUT[40]
PASS0_CH_RANGEVIO_TR_OUT[41]
PASS0_CH_RANGEVIO_TR_OUT[42]
PASS0_CH_RANGEVIO_TR_OUT[43]
PASS0_CH_RANGEVIO_TR_OUT[44]
PASS0_CH_RANGEVIO_TR_OUT[45]
PASS0_CH_RANGEVIO_TR_OUT[46]
PASS0_CH_RANGEVIO_TR_OUT[47]
PASS0_CH_RANGEVIO_TR_OUT[48]
PASS0_CH_RANGEVIO_TR_OUT[49]
PASS0_CH_RANGEVIO_TR_OUT[50]
PASS0_CH_RANGEVIO_TR_OUT[51]
PASS0_CH_RANGEVIO_TR_OUT[52]
PASS0_CH_RANGEVIO_TR_OUT[53]
PASS0_CH_RANGEVIO_TR_OUT[54]
PASS0_CH_RANGEVIO_TR_OUT[55]
PASS0_CH_RANGEVIO_TR_OUT[56]
PASS0_CH_RANGEVIO_TR_OUT[57]
PASS0_CH_RANGEVIO_TR_OUT[58]
PASS0_CH_RANGEVIO_TR_OUT[59]
Datasheet
74
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
PASS0_CH_RANGEVIO_TR_OUT[60]
PASS0_CH_RANGEVIO_TR_OUT[61]
TCPWM1_16_ONE_CNT_TR_IN[52]
SAR1 ch#28, range violation to TCPWM1 Group #0 Counter #52 trig = 2
TCPWM1_16_ONE_CNT_TR_IN[53]
TCPWM1_16_ONE_CNT_TR_IN[54]
TCPWM1_16_ONE_CNT_TR_IN[55]
TCPWM1_16M_ONE_CNT_TR_IN[2]
TCPWM1_16M_ONE_CNT_TR_IN[5]
TCPWM1_16M_ONE_CNT_TR_IN[8]
TCPWM1_16M_ONE_CNT_TR_IN[11]
TCPWM1_16_ONE_CNT_TR_IN[56]
TCPWM1_16_ONE_CNT_TR_IN[57]
TCPWM1_16_ONE_CNT_TR_IN[58]
TCPWM1_16_ONE_CNT_TR_IN[59]
TCPWM1_16_ONE_CNT_TR_IN[60]
TCPWM1_16_ONE_CNT_TR_IN[61]
TCPWM1_16_ONE_CNT_TR_IN[62]
TCPWM1_16_ONE_CNT_TR_IN[63]
TCPWM1_16_ONE_CNT_TR_IN[64]
TCPWM1_16_ONE_CNT_TR_IN[65]
TCPWM1_16_ONE_CNT_TR_IN[66]
TCPWM1_16_ONE_CNT_TR_IN[67]
TCPWM1_16_ONE_CNT_TR_IN[68]
TCPWM1_16_ONE_CNT_TR_IN[69]
TCPWM1_16_ONE_CNT_TR_IN[70]
TCPWM1_16_ONE_CNT_TR_IN[71]
TCPWM1_16_ONE_CNT_TR_IN[72]
TCPWM1_16_ONE_CNT_TR_IN[73]
TCPWM1_16_ONE_CNT_TR_IN[74]
TCPWM1_16_ONE_CNT_TR_IN[75]
TCPWM1_16_ONE_CNT_TR_IN[76]
TCPWM1_16_ONE_CNT_TR_IN[77]
TCPWM1_16_ONE_CNT_TR_IN[78]
TCPWM1_16_ONE_CNT_TR_IN[79]
TCPWM1_16_ONE_CNT_TR_IN[80]
TCPWM1_16_ONE_CNT_TR_IN[81]
TCPWM1_16_ONE_CNT_TR_IN[82]
TCPWM1_16_ONE_CNT_TR_IN[83]
SAR1 ch#29, range violation to TCPWM1 Group #0 Counter #53 trig = 2
SAR1 ch#30, range violation to TCPWM1 Group #0 Counter #54 trig = 2
SAR1 ch#31, range violation to TCPWM1 Group #0 Counter #55 trig = 2
SAR2 ch#0, range violation to TCPWM1 Group #1 Counter #02 trig = 2
SAR2 ch#1, range violation to TCPWM1 Group #1 Counter #05 trig = 2
SAR2 ch#2, range violation to TCPWM1 Group #1 Counter #08 trig = 2
SAR2 ch#3, range violation to TCPWM1 Group #1 Counter #11 trig = 2
SAR2 ch#4, range violation to TCPWM1 Group #0 Counter #56 trig = 2
SAR2 ch#5, range violation to TCPWM1 Group #0 Counter #57 trig = 2
SAR2 ch#6, range violation to TCPWM1 Group #0 Counter #58 trig = 2
SAR2 ch#7, range violation to TCPWM1 Group #0 Counter #59 trig = 2
SAR2 ch#8, range violation to TCPWM1 Group #0 Counter #60 trig = 2
SAR2 ch#9, range violation to TCPWM1 Group #0 Counter #61 trig = 2
SAR2 ch#10, range violation to TCPWM1 Group #0 Counter #62 trig = 2
SAR2 ch#11, range violation to TCPWM1 Group #0 Counter #63 trig = 2
SAR2 ch#12, range violation to TCPWM1 Group #0 Counter #64 trig = 2
SAR2 ch#13, range violation to TCPWM1 Group #0 Counter #65 trig = 2
SAR2 ch#14, range violation to TCPWM1 Group #0 Counter #66 trig = 2
SAR2 ch#15, range violation to TCPWM1 Group #0 Counter #67 trig = 2
SAR2 ch#16, range violation to TCPWM1 Group #0 Counter #68 trig = 2
SAR2 ch#17, range violation to TCPWM1 Group #0 Counter #69 trig = 2
SAR2 ch#18, range violation to TCPWM1 Group #0 Counter #70 trig = 2
SAR2 ch#19, range violation to TCPWM1 Group #0 Counter #71 trig = 2
SAR2 ch#20, range violation to TCPWM1 Group #0 Counter #72 trig = 2
SAR2 ch#21, range violation to TCPWM1 Group #0 Counter #73 trig = 2
SAR2 ch#22, range violation to TCPWM1 Group #0 Counter #74 trig = 2
SAR2 ch#23, range violation to TCPWM1 Group #0 Counter #75 trig = 2
SAR2 ch#24, range violation to TCPWM1 Group #0 Counter #76 trig = 2
SAR2 ch#25, range violation to TCPWM1 Group #0 Counter #77 trig = 2
SAR2 ch#26, range violation to TCPWM1 Group #0 Counter #78 trig = 2
SAR2 ch#27, range violation to TCPWM1 Group #0 Counter #79 trig = 2
SAR2 ch#28, range violation to TCPWM1 Group #0 Counter #80 trig = 2
SAR2 ch#29, range violation to TCPWM1 Group #0 Counter #81 trig = 2
SAR2 ch#30, range violation to TCPWM1 Group #0 Counter #82 trig = 2
SAR2 ch#31, range violation to TCPWM1 Group #0 Counter #83 trig = 2
PASS0_CH_RANGEVIO_TR_OUT[62]
PASS0_CH_RANGEVIO_TR_OUT[63]
PASS0_CH_RANGEVIO_TR_OUT[64]
PASS0_CH_RANGEVIO_TR_OUT[65]
PASS0_CH_RANGEVIO_TR_OUT[66]
PASS0_CH_RANGEVIO_TR_OUT[67]
PASS0_CH_RANGEVIO_TR_OUT[68]
PASS0_CH_RANGEVIO_TR_OUT[69]
PASS0_CH_RANGEVIO_TR_OUT[70]
PASS0_CH_RANGEVIO_TR_OUT[71]
PASS0_CH_RANGEVIO_TR_OUT[72]
PASS0_CH_RANGEVIO_TR_OUT[73]
PASS0_CH_RANGEVIO_TR_OUT[74]
PASS0_CH_RANGEVIO_TR_OUT[75]
PASS0_CH_RANGEVIO_TR_OUT[76]
PASS0_CH_RANGEVIO_TR_OUT[77]
PASS0_CH_RANGEVIO_TR_OUT[78]
PASS0_CH_RANGEVIO_TR_OUT[79]
PASS0_CH_RANGEVIO_TR_OUT[80]
PASS0_CH_RANGEVIO_TR_OUT[81]
PASS0_CH_RANGEVIO_TR_OUT[82]
PASS0_CH_RANGEVIO_TR_OUT[83]
PASS0_CH_RANGEVIO_TR_OUT[84]
PASS0_CH_RANGEVIO_TR_OUT[85]
PASS0_CH_RANGEVIO_TR_OUT[86]
PASS0_CH_RANGEVIO_TR_OUT[87]
PASS0_CH_RANGEVIO_TR_OUT[88]
PASS0_CH_RANGEVIO_TR_OUT[89]
PASS0_CH_RANGEVIO_TR_OUT[90]
PASS0_CH_RANGEVIO_TR_OUT[91]
PASS0_CH_RANGEVIO_TR_OUT[92]
PASS0_CH_RANGEVIO_TR_OUT[93]
PASS0_CH_RANGEVIO_TR_OUT[94]
PASS0_CH_RANGEVIO_TR_OUT[95]
MUX Group 7: TCPWM1 to PASS SARx
0
1
TCPWM1_16M_TR_OUT1[0]
TCPWM1_16M_TR_OUT1[3]
TCPWM1_16M_TR_OUT1[6]
TCPWM1_16M_TR_OUT1[9]
TCPWM1_16_TR_OUT1[0:27]
PASS0_CH_TR_IN[0]
PASS0_CH_TR_IN[1]
PASS0_CH_TR_IN[2]
PASS0_CH_TR_IN[3]
PASS0_CH_TR_IN[4:31]
TCPWM1 Group #1 Counter #00 (PWM1_M_0) to SAR0 ch#0
TCPWM1 Group #1 Counter #03 (PWM1_M_3) to SAR0 ch#1
TCPWM1 Group #1 Counter #06 (PWM1_M_6) to SAR0 ch#2
TCPWM1 Group #1 Counter #09 (PWM1_M_9) to SAR0 ch#3
2
3
4:31
TCPWM1 Group #0 Counter #00 through 27 (PWM1_0 to PWM1_27) to
SAR0 ch#4 through SAR0 ch#31
32
33
34
TCPWM1_16M_TR_OUT1[1]
TCPWM1_16M_TR_OUT1[4]
TCPWM1_16M_TR_OUT1[7]
PASS0_CH_TR_IN[32]
PASS0_CH_TR_IN[33]
PASS0_CH_TR_IN[34]
TCPWM1 Group #1 Counter #01 (PWM1_M_1) to SAR1 ch#0
TCPWM1 Group #1 Counter #04 (PWM1_M_4) to SAR1 ch#1
TCPWM1 Group #1 Counter #07 (PWM1_M_7) to SAR1 ch#2
Datasheet
75
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
PASS0_CH_TR_IN[35]
Description
35
TCPWM1_16M_TR_OUT1[10]
TCPWM1_16_TR_OUT1[28:55]
TCPWM1 Group #1 Counter #10 (PWM1_M_10) to SAR1 ch#3
36:63
PASS0_CH_TR_IN[36:63]
TCPWM1 Group #0 Counter #28 through 55 (PWM1_28 to PWM1_55) to
SAR1 ch#4 through SAR1 ch#31
64
65
TCPWM1_16M_TR_OUT1[2]
TCPWM1_16M_TR_OUT1[5]
TCPWM1_16M_TR_OUT1[8]
TCPWM1_16M_TR_OUT1[11]
TCPWM1_16_TR_OUT1[56:83]
PASS0_CH_TR_IN[64]
PASS0_CH_TR_IN[65]
PASS0_CH_TR_IN[66]
PASS0_CH_TR_IN[67]
PASS0_CH_TR_IN[68:95]
TCPWM1 Group #1 Counter #02 (PWM1_M_2) to SAR2 ch#0
TCPWM1 Group #1 Counter #05 (PWM1_M_5) to SAR2 ch#1
TCPWM1 Group #1 Counter #08 (PWM1_M_8) to SAR2 ch#2
TCPWM1 Group #1 Counter #11 (PWM1_M_11) to SAR2 ch#3
66
67
68:95
TCPWM1 Group #1 Counter #56 through 83 (PWM1_56 to PWM1_83) to
SAR2 ch#4 through SAR2 ch#31
MUX Group 8: Acknowledge triggers from P-DMA1 to CAN1
0
1
2
3
4
PDMA1_TR_OUT[38]
PDMA1_TR_OUT[41]
PDMA1_TR_OUT[44]
PDMA1_TR_OUT[47]
PDMA1_TR_OUT[50]
CAN1_DBG_TR_ACK[0]
CAN1_DBG_TR_ACK[1]
CAN1_DBG_TR_ACK[2]
CAN1_DBG_TR_ACK[3]
CAN1_DBG_TR_ACK[4]
CAN1 Channel#0 P-DMA1 acknowledge
CAN1 Channel#1 P-DMA1 acknowledge
CAN1 Channel#2 P-DMA1 acknowledge
CAN1 Channel#3 P-DMA1 acknowledge
CAN1 Channel#4 P-DMA1 acknowledge
MUX Group 9: Acknowledge triggers from P-DMA0 to CAN0
0
1
2
3
4
PDMA0_TR_OUT[32]
PDMA0_TR_OUT[35]
PDMA0_TR_OUT[38]
PDMA0_TR_OUT[41]
PDMA0_TR_OUT[44]
CAN0_DBG_TR_ACK[0]
CAN0_DBG_TR_ACK[1]
CAN0_DBG_TR_ACK[2]
CAN0_DBG_TR_ACK[3]
CAN0_DBG_TR_ACK[4]
CAN0 Channel#0 P-DMA0 acknowledge
CAN0 Channel#1 P-DMA0 acknowledge
CAN0 Channel#2 P-DMA0 acknowledge
CAN0 Channel#3 P-DMA0 acknowledge
CAN0 Channel#4 P-DMA0 acknowledge
MUX Group 12: P-DMA1 TO P-DMA1 triggers
0
1
PDMA1_TR_OUT[61]
PDMA1_TR_OUT[62]
PDMA1_TR_IN[63]
PDMA1_TR_IN[64]
P-DMA1 to P-DMA1
P-DMA1 to P-DMA1
Datasheet
76
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
20
Peripheral clocks
Table 20-1
Output
Peripheral clock assignments
Destination
Description
CPUSS root clocks (Group 0)
0
1
2
3
4
5
6
7
8
PCLK_CPUSS_CLOCK_TRACE_IN
Trace clock
PCLK_SMARTIO12_CLOCK
PCLK_SMARTIO13_CLOCK
PCLK_SMARTIO14_CLOCK
PCLK_SMARTIO15_CLOCK
PCLK_SMARTIO17_CLOCK
PCLK_TCPWM0_CLOCKS0
PCLK_TCPWM0_CLOCKS1
PCLK_TCPWM0_CLOCKS2
PCLK_TCPWM0_CLOCKS256
PCLK_TCPWM0_CLOCKS257
PCLK_TCPWM0_CLOCKS258
PCLK_TCPWM0_CLOCKS512
PCLK_TCPWM0_CLOCKS513
PCLK_TCPWM0_CLOCKS514
Smart I/O #12
Smart I/O #13
Smart I/O #14
Smart I/O #15
Smart I/O #17
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #1
TCPWM0 Group #2, Counter #2
9
10
11
12
13
14
COMM root clocks (Group 1)
0
1
2
3
4
5
6
7
8
PCLK_CANFD0_CLOCK_CAN0
CAN0, Channel #0
CAN0, Channel #1
CAN0, Channel #2
CAN0, Channel #3
CAN0, Channel #4
CAN1, Channel #0
CAN1, Channel #1
CAN1, Channel #2
CAN1, Channel #3
CAN1, Channel #4
SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SCB8
PCLK_CANFD0_CLOCK_CAN1
PCLK_CANFD0_CLOCK_CAN2
PCLK_CANFD0_CLOCK_CAN3
PCLK_CANFD0_CLOCK_CAN4
PCLK_CANFD1_CLOCK_CAN0
PCLK_CANFD1_CLOCK_CAN1
PCLK_CANFD1_CLOCK_CAN2
PCLK_CANFD1_CLOCK_CAN3
PCLK_CANFD1_CLOCK_CAN4
PCLK_SCB0_CLOCK
PCLK_SCB1_CLOCK
PCLK_SCB2_CLOCK
PCLK_SCB3_CLOCK
PCLK_SCB4_CLOCK
PCLK_SCB5_CLOCK
PCLK_SCB6_CLOCK
PCLK_SCB7_CLOCK
PCLK_SCB8_CLOCK
9
30
31
32
33
34
35
36
37
38
39
40
42
PCLK_SCB9_CLOCK
PCLK_SCB10_CLOCK
PCLK_PASS0_CLOCK_SAR0
SCB9
SCB10
SAR0
Datasheet
77
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Destination
PCLK_PASS0_CLOCK_SAR1
PCLK_PASS0_CLOCK_SAR2
PCLK_TCPWM1_CLOCKS0
PCLK_TCPWM1_CLOCKS1
PCLK_TCPWM1_CLOCKS2
PCLK_TCPWM1_CLOCKS3
PCLK_TCPWM1_CLOCKS4
PCLK_TCPWM1_CLOCKS5
PCLK_TCPWM1_CLOCKS6
PCLK_TCPWM1_CLOCKS7
PCLK_TCPWM1_CLOCKS8
PCLK_TCPWM1_CLOCKS9
PCLK_TCPWM1_CLOCKS10
PCLK_TCPWM1_CLOCKS11
PCLK_TCPWM1_CLOCKS12
PCLK_TCPWM1_CLOCKS13
PCLK_TCPWM1_CLOCKS14
PCLK_TCPWM1_CLOCKS15
PCLK_TCPWM1_CLOCKS16
PCLK_TCPWM1_CLOCKS17
PCLK_TCPWM1_CLOCKS18
PCLK_TCPWM1_CLOCKS19
PCLK_TCPWM1_CLOCKS20
PCLK_TCPWM1_CLOCKS21
PCLK_TCPWM1_CLOCKS22
PCLK_TCPWM1_CLOCKS23
PCLK_TCPWM1_CLOCKS24
PCLK_TCPWM1_CLOCKS25
PCLK_TCPWM1_CLOCKS26
PCLK_TCPWM1_CLOCKS27
PCLK_TCPWM1_CLOCKS28
PCLK_TCPWM1_CLOCKS29
PCLK_TCPWM1_CLOCKS30
PCLK_TCPWM1_CLOCKS31
PCLK_TCPWM1_CLOCKS32
PCLK_TCPWM1_CLOCKS33
PCLK_TCPWM1_CLOCKS34
PCLK_TCPWM1_CLOCKS35
PCLK_TCPWM1_CLOCKS36
PCLK_TCPWM1_CLOCKS37
PCLK_TCPWM1_CLOCKS38
Description
SAR1
SAR2
TCPWM1 Group #0, Counter #0
TCPWM1 Group #0, Counter #1
TCPWM1 Group #0, Counter #2
TCPWM1 Group #0, Counter #3
TCPWM1 Group #0, Counter #4
TCPWM1 Group #0, Counter #5
TCPWM1 Group #0, Counter #6
TCPWM1 Group #0, Counter #7
TCPWM1 Group #0, Counter #8
TCPWM1 Group #0, Counter #9
TCPWM1 Group #0, Counter #10
TCPWM1 Group #0, Counter #11
TCPWM1 Group #0, Counter #12
TCPWM1 Group #0, Counter #13
TCPWM1 Group #0, Counter #14
TCPWM1 Group #0, Counter #15
TCPWM1 Group #0, Counter #16
TCPWM1 Group #0, Counter #17
TCPWM1 Group #0, Counter #18
TCPWM1 Group #0, Counter #19
TCPWM1 Group #0, Counter #20
TCPWM1 Group #0, Counter #21
TCPWM1 Group #0, Counter #22
TCPWM1 Group #0, Counter #23
TCPWM1 Group #0, Counter #24
TCPWM1 Group #0, Counter #25
TCPWM1 Group #0, Counter #26
TCPWM1 Group #0, Counter #27
TCPWM1 Group #0, Counter #28
TCPWM1 Group #0, Counter #29
TCPWM1 Group #0, Counter #30
TCPWM1 Group #0, Counter #31
TCPWM1 Group #0, Counter #32
TCPWM1 Group #0, Counter #33
TCPWM1 Group #0, Counter #34
TCPWM1 Group #0, Counter #35
TCPWM1 Group #0, Counter #36
TCPWM1 Group #0, Counter #37
TCPWM1 Group #0, Counter #38
Datasheet
78
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
84
Destination
PCLK_TCPWM1_CLOCKS39
PCLK_TCPWM1_CLOCKS40
PCLK_TCPWM1_CLOCKS41
PCLK_TCPWM1_CLOCKS42
PCLK_TCPWM1_CLOCKS43
PCLK_TCPWM1_CLOCKS44
PCLK_TCPWM1_CLOCKS45
PCLK_TCPWM1_CLOCKS46
PCLK_TCPWM1_CLOCKS47
PCLK_TCPWM1_CLOCKS48
PCLK_TCPWM1_CLOCKS49
PCLK_TCPWM1_CLOCKS50
PCLK_TCPWM1_CLOCKS51
PCLK_TCPWM1_CLOCKS52
PCLK_TCPWM1_CLOCKS53
PCLK_TCPWM1_CLOCKS54
PCLK_TCPWM1_CLOCKS55
PCLK_TCPWM1_CLOCKS56
PCLK_TCPWM1_CLOCKS57
PCLK_TCPWM1_CLOCKS58
PCLK_TCPWM1_CLOCKS59
PCLK_TCPWM1_CLOCKS60
PCLK_TCPWM1_CLOCKS61
PCLK_TCPWM1_CLOCKS62
PCLK_TCPWM1_CLOCKS63
PCLK_TCPWM1_CLOCKS64
PCLK_TCPWM1_CLOCKS65
PCLK_TCPWM1_CLOCKS66
PCLK_TCPWM1_CLOCKS67
PCLK_TCPWM1_CLOCKS68
PCLK_TCPWM1_CLOCKS69
PCLK_TCPWM1_CLOCKS70
PCLK_TCPWM1_CLOCKS71
PCLK_TCPWM1_CLOCKS72
PCLK_TCPWM1_CLOCKS73
PCLK_TCPWM1_CLOCKS74
PCLK_TCPWM1_CLOCKS75
PCLK_TCPWM1_CLOCKS76
PCLK_TCPWM1_CLOCKS77
PCLK_TCPWM1_CLOCKS78
PCLK_TCPWM1_CLOCKS79
Description
TCPWM1 Group #0, Counter #39
TCPWM1 Group #0, Counter #40
TCPWM1 Group #0, Counter #41
TCPWM1 Group #0, Counter #42
TCPWM1 Group #0, Counter #43
TCPWM1 Group #0, Counter #44
TCPWM1 Group #0, Counter #45
TCPWM1 Group #0, Counter #46
TCPWM1 Group #0, Counter #47
TCPWM1 Group #0, Counter #48
TCPWM1 Group #0, Counter #49
TCPWM1 Group #0, Counter #50
TCPWM1 Group #0, Counter #51
TCPWM1 Group #0, Counter #52
TCPWM1 Group #0, Counter #53
TCPWM1 Group #0, Counter #54
TCPWM1 Group #0, Counter #55
TCPWM1 Group #0, Counter #56
TCPWM1 Group #0, Counter #57
TCPWM1 Group #0, Counter #58
TCPWM1 Group #0, Counter #59
TCPWM1 Group #0, Counter #60
TCPWM1 Group #0, Counter #61
TCPWM1 Group #0, Counter #62
TCPWM1 Group #0, Counter #63
TCPWM1 Group #0, Counter #64
TCPWM1 Group #0, Counter #65
TCPWM1 Group #0, Counter #66
TCPWM1 Group #0, Counter #67
TCPWM1 Group #0, Counter #68
TCPWM1 Group #0, Counter #69
TCPWM1 Group #0, Counter #70
TCPWM1 Group #0, Counter #71
TCPWM1 Group #0, Counter #72
TCPWM1 Group #0, Counter #73
TCPWM1 Group #0, Counter #74
TCPWM1 Group #0, Counter #75
TCPWM1 Group #0, Counter #76
TCPWM1 Group #0, Counter #77
TCPWM1 Group #0, Counter #78
TCPWM1 Group #0, Counter #79
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
Datasheet
79
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Destination
PCLK_TCPWM1_CLOCKS80
PCLK_TCPWM1_CLOCKS81
PCLK_TCPWM1_CLOCKS82
PCLK_TCPWM1_CLOCKS83
PCLK_TCPWM1_CLOCKS256
PCLK_TCPWM1_CLOCKS257
PCLK_TCPWM1_CLOCKS258
PCLK_TCPWM1_CLOCKS259
PCLK_TCPWM1_CLOCKS260
PCLK_TCPWM1_CLOCKS261
PCLK_TCPWM1_CLOCKS262
PCLK_TCPWM1_CLOCKS263
PCLK_TCPWM1_CLOCKS264
PCLK_TCPWM1_CLOCKS265
PCLK_TCPWM1_CLOCKS266
PCLK_TCPWM1_CLOCKS267
PCLK_TCPWM1_CLOCKS512
PCLK_TCPWM1_CLOCKS513
PCLK_TCPWM1_CLOCKS514
PCLK_TCPWM1_CLOCKS515
PCLK_TCPWM1_CLOCKS516
PCLK_TCPWM1_CLOCKS517
PCLK_TCPWM1_CLOCKS518
PCLK_TCPWM1_CLOCKS519
PCLK_TCPWM1_CLOCKS520
PCLK_TCPWM1_CLOCKS521
PCLK_TCPWM1_CLOCKS522
PCLK_TCPWM1_CLOCKS523
PCLK_TCPWM1_CLOCKS524
Description
TCPWM1 Group #0, Counter #80
TCPWM1 Group #0, Counter #81
TCPWM1 Group #0, Counter #82
TCPWM1 Group #0, Counter #83
TCPWM1 Group #1, Counter #0
TCPWM1 Group #1, Counter #1
TCPWM1 Group #1, Counter #2
TCPWM1 Group #1, Counter #3
TCPWM1 Group #1, Counter #4
TCPWM1 Group #1, Counter #5
TCPWM1 Group #1, Counter #6
TCPWM1 Group #1, Counter #7
TCPWM1 Group #1, Counter #8
TCPWM1 Group #1, Counter #9
TCPWM1 Group #1, Counter #10
TCPWM1 Group #1, Counter #11
TCPWM1 Group #2, Counter #0
TCPWM1 Group #2, Counter #1
TCPWM1 Group #2, Counter #2
TCPWM1 Group #2, Counter #3
TCPWM1 Group #2, Counter #4
TCPWM1 Group #2, Counter #5
TCPWM1 Group #2, Counter #6
TCPWM1 Group #2, Counter #7
TCPWM1 Group #2, Counter #8
TCPWM1 Group #2, Counter #9
TCPWM1 Group #2, Counter #10
TCPWM1 Group #2, Counter #11
TCPWM1 Group #2, Counter #12
Datasheet
80
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Faults
21
Faults
Table 21-1
Fault assignments
Fault
Source
Description
CM0+ SMPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
0
CPUSS_MPU_VIO_0
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1
2
CPUSS_MPU_VIO_1
CRYPTO SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
SDHC MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Ethernet0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Ethernet1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM7_1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM7_0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CPUSS_MPU_VIO_2
CPUSS_MPU_VIO_3
CPUSS_MPU_VIO_4
CPUSS_MPU_VIO_5
CPUSS_MPU_VIO_9
CPUSS_MPU_VIO_10
CPUSS_MPU_VIO_13
CPUSS_MPU_VIO_14
CPUSS_MPU_VIO_15
3
4
5
9
10
13
14
15
Correctable ECC error in CM7_1 TCM memory
DATA0[23:2]: Violating address.
16
17
18
CPUSS_CM7_1_TCM_C_ECC
CPUSS_CM7_1_TCM_NC_ECC
CPUSS_CM7_0_CACHE_C_ECC
DATA1[7:0]: Syndrome of code word (at address offset 0x0).
DATA1[31:30]: 0= ITCM, 2=D0TCM, 3=D1TCM
Non Correctable ECC error in CM7_1 TCM memory.
See CPUSS_CM7_1_TCM_C_ECC description.
Correctable ECC error in CM7_0 Cache memories
DATA0[16:2]: location information: Tag/Data SRAM, Way, Index and line Offset, see CM7 UGRM
IEBR0/DEBR0 description for details.
DATA0[31]: 0=Instruction cache, 1= Data cache
Non Correctable ECC error in CM7_0 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
19
20
21
25
CPUSS_CM7_0_CACHE_NC_ECC
CPUSS_CM7_1_CACHE_C_ECC
CPUSS_CM7_1_CACHE_NC_ECC
PERI_MS_VIO_4
Correctable ECC error in CM7_1 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
Non Correctable ECC error in CM7_1 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
P-DMA1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Peripheral protection SRAM correctable ECC violation
DATA0[10:0]: Violating address.
26
27
PERI_PERI_C_ECC
PERI_PERI_NC_ECC
DATA1[7:0]: Syndrome of SRAM word.
Peripheral protection SRAM non-correctable ECC violation
CM0+ Peripheral Master Interface PPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
28
PERI_MS_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other:
undefined.
CM7_0 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
29
30
PERI_MS_VIO_1
PERI_MS_VIO_2
CM7_1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Datasheet
81
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Faults
Table 21-1
Fault assignments (continued)
Fault
Source
Description
P-DMA0 Peripheral Master Interface PPU_3 violation.
See PERI_MS_VIO_0 description.
31
PERI_MS_VIO_3
Peripheral Group #0 violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
32
PERI_GROUP_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
33
34
35
36
37
38
40
41
PERI_GROUP_VIO_1
PERI_GROUP_VIO_2
PERI_GROUP_VIO_3
PERI_GROUP_VIO_4
PERI_GROUP_VIO_5
PERI_GROUP_VIO_6
PERI_GROUP_VIO_8
PERI_GROUP_VIO_9
Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #4 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #8 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
Flash controller main flash bus error
FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive
32-bit system address.
48
CPUSS_FLASHC_MAIN_BUS_ERR
FAULT_DATA1[11:8]: Master identifier.
Flash controller main flash correctable ECC violation.
DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).
DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).
DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).
DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
49
CPUSS_FLASHC_MAIN_C_ECC
Flash controller main flash non-correctable ECC violation.
See CPUSS_FLASHC_MAIN_C_ECC description.
50
51
CPUSS_FLASHC_MAIN_NC_ECC
CPUSS_FLASHC_WORK_BUS_ERR
Flash controller work-flash bus error.
See CPUSS_FLASHC_MAIN_BUS_ERR description.
Flash controller work-flash non-correctable ECC violation.
DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
52
53
CPUSS_FLASHC_WORK_C_ECC
CPUSS_FLASHC_WORK_NC_ECC
DATA1[6:0]: Syndrome of 32-bit word.
Flash controller work-flash cache non-correctable ECC violation.
See CPUSS_FLASHC_WORK_C_ECC description.
Flash controller CM0+ cache correctable ECC violation.
DATA0[26:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).
DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).
DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
54
CPUSS_FLASHC_CM0_CA_C_ECC
Flash controller CM0+ cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
55
56
57
CPUSS_FLASHC_CM0_CA_NC_ECC
CPUSS_CM7_0_TCM_C_ECC
CPUSS_CM7_0_TCM_NC_ECC
CPU CM7_0 TCM memory correctable ECC violation.
See CPUSS_CM7_1_TCM_C_ECC description.
CPU CM7_0 TCM memory non-correctable ECC violation.
See CPUSS_CM7_1_TCM_C_ECC description.
System memory controller 0 correctable ECC violation:
DATA0[31:0]: Violating address.
58
CPUSS_RAMC0_C_ECC
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
System memory controller 0 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
59
60
61
CPUSS_RAMC0_NC_ECC
CPUSS_RAMC1_C_ECC
CPUSS_RAMC1_NC_ECC
System memory controller 1 correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
System memory controller 1 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
Datasheet
82
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Faults
Table 21-1
Fault assignments (continued)
Fault
Source
Description
System memory controller 2 correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
62
63
CPUSS_RAMC2_C_ECC
System memory controller 2 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
CPUSS_RAMC2_NC_ECC
Crypto memory correctable ECC violation.
DATA0[31:0]: Violating address.
64
65
70
CPUSS_CRYPTO_C_ECC
CPUSS_CRYPTO_NC_ECC
CPUSS_DW0_C_ECC
DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM.
DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.
CRYPTO memory non-correctable ECC violation.
See CPUSS_CRYPTO_C_ECC description.
P-DMA0 memory correctable ECC violation:
DATA0[11:0]: Violating DW SRAM address
(word address, assuming byte addressable).
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
P-DMA0 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
71
72
73
CPUSS_DW0_NC_ECC
CPUSS_DW1_C_ECC
CPUSS_DW1_NC_ECC
P-DMA1 memory correctable ECC violation.
See CPUSS_DW0_C_ECC description.
P-DMA1 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
Flash code storage SRAM memory correctable ECC violation:
DATA0[15:0]: Address location in the eCT Flash SRAM.
DATA1[6:0]: Syndrome of 32-bit SRAM word.
74
75
CPUSS_FM_SRAM_C_ECC
CPUSS_FM_SRAM_NC_ECC
Flash code storage SRAM memory non-correctable ECC violation:
See CPUSS_FM_SRAMC_C_ECC description.
CAN0 message buffer correctable ECC violation:
DATA0[15:0]: Violating address.
80
81
CANFD_0_CAN_C_ECC
CANFD_0_CAN_NC_ECC
DATA0[22:16]: ECC violating data[38:32] from MRAM.
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA1[31:0]: ECC violating data[31:0] from MRAM.
CAN0 message buffer non-correctable ECC violation:
DATA0[15:0]: Violating address.
DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error).
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA0[30]: Write access, only possible for Address Error
DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE
DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).
CAN1 message buffer correctable ECC violation.
See CANFD_0_CAN_C_ECC description.
82
83
CANFD_1_CAN_C_ECC
CANFD_1_CAN_NC_ECC
CAN1 message buffer non-correctable ECC violation.
See CANFD_0_CAN_NC_ECC description.
Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[15:0]: CLK_HF* root CSV violation flags.
DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs)
DATA0[25]: CLK_LF CSV violation flag
90
91
92
SRSS_FAULT_CSV
SRSS_FAULT_SSV
SRSS_FAULT_MCWDT0
DATA0[26]: CLK_HVILO CSV violation flag
Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[0]: BOD on VDDA
DATA[1]: OVD on VDDA
DATA[16]: LVD/HVD #1
DATA0[17]: LVD/HVD #2
Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the same
time.
DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT
DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT
DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT
DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT
Fault output for MCWDT1 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
93
94
SRSS_FAULT_MCWDT1
SRSS_FAULT_MCWDT2
Fault output for MCWDT2 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
Datasheet
83
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
22
Peripheral protection unit fixed structure pairs
Protection pair is a pair PPU structures, a master, and a slave structure. The master structure protects the slave
structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.
Table 22-1
PPU fixed structure pairs
Pair No.
PPU fixed structure pair
Address
Size
Description
0
PERI_MS_PPU_FX_PERI_MAIN
PERI_MS_PPU_FX_PERI_SECURE
0x40000200
0x40002000
0x40004010
0x40004050
0x40004090
0x400040C0
0x40004100
0x40004140
0x40004180
0x40004200
0x40004240
0x40004020
0x40004060
0x400040A0
0x400040E0
0x40004120
0x40004160
0x400041A0
0x40004220
0x40004260
0x40008000
0x40030000
0x40040000
0x40100000
0x40101000
0x40102000
0x40102100
0x40102120
0x40108000
0x40200000
0x40200400
0x40201000
0x40202000
0x40208000
0x4020A000
0x4020C000
0x40210000
0x40210100
0x40210200
0x40210300
0x40220000
0x00000040 Peripheral Interconnect main
0x00000004 Peripheral interconnect secure
0x00000004 Peripheral Group #0 main
0x00000004 Peripheral Group #1 main
0x00000004 Peripheral Group #2 main
0x00000020 Peripheral Group #3 main
0x00000020 Peripheral Group #4 main
0x00000020 Peripheral Group #5 main
0x00000020 Peripheral Group #6 main
0x00000020 Peripheral Group #8 main
0x00000020 Peripheral Group #9 main
0x00000004 Peripheral Group #0 boot
0x00000004 Peripheral Group #1 boot
0x00000004 Peripheral Group #2 boot
0x00000004 Peripheral Group #3 boot
0x00000004 Peripheral Group #4 boot
0x00000004 Peripheral Group #5 boot
0x00000004 Peripheral Group #6 boot
0x00000004 Peripheral Group #8 boot
0x00000004 Peripheral Group #9 boot
0x00008000 Peripheral trigger multiplexer
0x00001000 Peripheral master slave boot
0x00004000 Peripheral clock main
0x00000400 Crypto main
1
2
PERI_MS_PPU_FX_PERI_GR0_GROUP
PERI_MS_PPU_FX_PERI_GR1_GROUP
PERI_MS_PPU_FX_PERI_GR2_GROUP
PERI_MS_PPU_FX_PERI_GR3_GROUP
PERI_MS_PPU_FX_PERI_GR4_GROUP
PERI_MS_PPU_FX_PERI_GR5_GROUP
PERI_MS_PPU_FX_PERI_GR6_GROUP
PERI_MS_PPU_FX_PERI_GR8_GROUP
PERI_MS_PPU_FX_PERI_GR9_GROUP
PERI_MS_PPU_FX_PERI_GR0_BOOT
PERI_MS_PPU_FX_PERI_GR1_BOOT
PERI_MS_PPU_FX_PERI_GR2_BOOT
PERI_MS_PPU_FX_PERI_GR3_BOOT
PERI_MS_PPU_FX_PERI_GR4_BOOT
PERI_MS_PPU_FX_PERI_GR5_BOOT
PERI_MS_PPU_FX_PERI_GR6_BOOT
PERI_MS_PPU_FX_PERI_GR8_BOOT
PERI_MS_PPU_FX_PERI_GR9_BOOT
PERI_MS_PPU_FX_PERI_TR
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PERI_MS_PPU_FX_PERI_MS_BOOT
PERI_MS_PPU_FX_PERI_PCLK_MAIN
PERI_MS_PPU_FX_CRYPTO_MAIN
PERI_MS_PPU_FX_CRYPTO_CRYPTO
PERI_MS_PPU_FX_CRYPTO_BOOT
PERI_MS_PPU_FX_CRYPTO_KEY0
PERI_MS_PPU_FX_CRYPTO_KEY1
PERI_MS_PPU_FX_CRYPTO_BUF
0x00000800 Crypto MMIO (Memory Mapped I/O)
0x00000100 Crypto boot
0x00000004 Crypto Key #0
0x00000004 Crypto Key #1
0x00002000 Crypto buffer
PERI_MS_PPU_FX_CPUSS_CM7_0
PERI_MS_PPU_FX_CPUSS_CM7_1
PERI_MS_PPU_FX_CPUSS_CM0
0x00000400 CM7_0 CPU core
0x00000400 CM7_1 CPU core
0x00001000 CM0+ CPU core
PERI_MS_PPU_FX_CPUSS_BOOT[32]
PERI_MS_PPU_FX_CPUSS_CM0_INT
PERI_MS_PPU_FX_CPUSS_CM7_0_INT
PERI_MS_PPU_FX_CPUSS_CM7_1_INT
PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN
PERI_MS_PPU_FX_IPC_STRUCT0_IPC
0x00000200 CPUSS boot
0x00001000 CPUSS CM0+ interrupts
0x00001000 CPUSS CM7_0 interrupts
0x00001000 CPUSS CM7_1 interrupts
0x00000100 CPUSS Fault Structure #0 main
0x00000100 CPUSS Fault Structure #1 main
0x00000100 CPUSS Fault Structure #2 main
0x00000100 CPUSS Fault Structure #3 main
0x00000020 CPUSS IPC Structure #0
Datasheet
84
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
PERI_MS_PPU_FX_IPC_STRUCT1_IPC
PERI_MS_PPU_FX_IPC_STRUCT2_IPC
PERI_MS_PPU_FX_IPC_STRUCT3_IPC
PERI_MS_PPU_FX_IPC_STRUCT4_IPC
PERI_MS_PPU_FX_IPC_STRUCT5_IPC
PERI_MS_PPU_FX_IPC_STRUCT6_IPC
PERI_MS_PPU_FX_IPC_STRUCT7_IPC
PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR
PERI_MS_PPU_FX_PROT_SMPU_MAIN
PERI_MS_PPU_FX_PROT_MPU0_MAIN
PERI_MS_PPU_FX_PROT_MPU5_MAIN
PERI_MS_PPU_FX_PROT_MPU9_MAIN
PERI_MS_PPU_FX_PROT_MPU10_MAIN
PERI_MS_PPU_FX_PROT_MPU13_MAIN
PERI_MS_PPU_FX_PROT_MPU14_MAIN
PERI_MS_PPU_FX_PROT_MPU15_MAIN
PERI_MS_PPU_FX_FLASHC_MAIN
0x40220020
0x40220040
0x40220060
0x40220080
0x402200A0
0x402200C0
0x402200E0
0x40221000
0x40221020
0x40221040
0x40221060
0x40221080
0x402210A0
0x402210C0
0x402210E0
0x40230000
0x40234000
0x40235400
0x40236400
0x40236800
0x40237400
0x40237800
0x40237C00
0x40240000
0x40240008
0x40240200
0x40240400
0x402404E0
0x40240560
0x40240580
0x40240600
0x40240680
0x40240700
0x40240780
0x4024F000
0x4024F400
0x4024F500
0x40260000
0x40261000
0x40262000
0x40268000
0x40268100
0x40268200
0x00000020 CPUSS IPC Structure #1
0x00000020 CPUSS IPC Structure #2
0x00000020 CPUSS IPC Structure #3
0x00000020 CPUSS IPC Structure #4
0x00000020 CPUSS IPC Structure #5
0x00000020 CPUSS IPC Structure #6
0x00000020 CPUSS IPC Structure #7
0x00000010 CPUSS IPC Interrupt Structure #0
0x00000010 CPUSS IPC Interrupt Structure #1
0x00000010 CPUSS IPC Interrupt Structure #2
0x00000010 CPUSS IPC Interrupt Structure #3
0x00000010 CPUSS IPC Interrupt Structure #4
0x00000010 CPUSS IPC Interrupt Structure #5
0x00000010 CPUSS IPC Interrupt Structure #6
0x00000010 CPUSS IPC Interrupt Structure #7
0x00000040 Peripheral protection SMPU main
0x00000004 Peripheral protection MPU #0 main
0x00000400 Peripheral protection MPU #5 main
0x00000400 Peripheral protection MPU #9 main
0x00000400 Peripheral protection MPU #10 main
0x00000004 Peripheral protection MPU #13 main
0x00000004 Peripheral protection MPU #14 main
0x00000400 Peripheral protection MPU #15 main
0x00000008 Flash controller main
PERI_MS_PPU_FX_FLASHC_CMD
0x00000004 Flash controller command
0x00000100 Flash controller tests
PERI_MS_PPU_FX_FLASHC_DFT
PERI_MS_PPU_FX_FLASHC_CM0
0x00000080 Flash controller CM0+
PERI_MS_PPU_FX_FLASHC_CM7_0
PERI_MS_PPU_FX_FLASHC_CM7_1
PERI_MS_PPU_FX_FLASHC_CRYPTO
PERI_MS_PPU_FX_FLASHC_DW0
0x00000004 Flash controller CM7_0
0x00000004 Flash controller CM7_1
0x00000004 Flash controller Crypto
0x00000004 Flash controller P-DMA0
0x00000004 Flash controller P-DMA1
0x00000004 Flash controller M-DMA0
0x00000004 Flash External AHB-Lite Master 0
0x00000080 Flash management
PERI_MS_PPU_FX_FLASHC_DW1
PERI_MS_PPU_FX_FLASHC_DMAC
PERI_MS_PPU_FX_FLASHC_SLOW0
PERI_MS_PPU_FX_FLASHC_FlashMgmt[32]
PERI_MS_PPU_FX_FLASHC_MainSafety
PERI_MS_PPU_FX_FLASHC_WorkSafety
PERI_MS_PPU_FX_SRSS_GENERAL
PERI_MS_PPU_FX_SRSS_MAIN
0x00000008 Flash controller code-flash safety
0x00000004 Flash controller work-flash safety
0x00000400 SRSS General
0x00001000 SRSS main
PERI_MS_PPU_FX_SRSS_SECURE
0x00002000 SRSS secure
PERI_MS_PPU_FX_MCWDT0_CONFIG
PERI_MS_PPU_FX_MCWDT1_CONFIG
PERI_MS_PPU_FX_MCWDT2_CONFIG
0x00000080 MCWDT #0 configuration
0x00000080 MCWDT #1 configuration
0x00000080 MCWDT #2 configuration
Note
32.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.
Datasheet
85
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
84
85
PERI_MS_PPU_FX_MCWDT0_MAIN
PERI_MS_PPU_FX_MCWDT1_MAIN
0x40268080
0x40268180
0x40268280
0x4026C000
0x4026C040
0x40270000
0x40280000
0x40290000
0x40280100
0x40290100
0x40288000
0x40288040
0x40288080
0x402880C0
0x40288100
0x40288140
0x40288180
0x402881C0
0x40288200
0x40288240
0x40288280
0x402882C0
0x40288300
0x40288340
0x40288380
0x402883C0
0x40288400
0x40288440
0x40288480
0x402884C0
0x40288500
0x40288540
0x40288580
0x402885C0
0x40288600
0x40288640
0x40288680
0x402886C0
0x40288700
0x40288740
0x40288780
0x402887C0
0x40288800
0x40288840
0x40288880
0x00000040 MCWDT #0 main
0x00000040 MCWDT #1 main
0x00000040 MCWDT #2 main
0x00000020 System WDT configuration
0x00000020 System WDT main
0x00010000 SRSS backup
86
PERI_MS_PPU_FX_MCWDT2_MAIN
87
PERI_MS_PPU_FX_WDT_CONFIG
88
PERI_MS_PPU_FX_WDT_MAIN
89
PERI_MS_PPU_FX_BACKUP_BACKUP
90
PERI_MS_PPU_FX_DW0_DW
0x00000100 P-DMA0 main
91
PERI_MS_PPU_FX_DW1_DW
0x00000100 P-DMA1 main
92
PERI_MS_PPU_FX_DW0_DW_CRC
0x00000080 P-DMA0 CRC
93
PERI_MS_PPU_FX_DW1_DW_CRC
0x00000080 P-DMA1 CRC
94
PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH
0x00000040 P-DMA0 Channel #0
0x00000040 P-DMA0 Channel #1
0x00000040 P-DMA0 Channel #2
0x00000040 P-DMA0 Channel #3
0x00000040 P-DMA0 Channel #4
0x00000040 P-DMA0 Channel #5
0x00000040 P-DMA0 Channel #6
0x00000040 P-DMA0 Channel #7
0x00000040 P-DMA0 Channel #8
0x00000040 P-DMA0 Channel #9
0x00000040 P-DMA0 Channel #10
0x00000040 P-DMA0 Channel #11
0x00000040 P-DMA0 Channel #12
0x00000040 P-DMA0 Channel #13
0x00000040 P-DMA0 Channel #14
0x00000040 P-DMA0 Channel #15
0x00000040 P-DMA0 Channel #16
0x00000040 P-DMA0 Channel #17
0x00000040 P-DMA0 Channel #18
0x00000040 P-DMA0 Channel #19
0x00000040 P-DMA0 Channel #20
0x00000040 P-DMA0 Channel #21
0x00000040 P-DMA0 Channel #22
0x00000040 P-DMA0 Channel #23
0x00000040 P-DMA0 Channel #24
0x00000040 P-DMA0 Channel #25
0x00000040 P-DMA0 Channel #26
0x00000040 P-DMA0 Channel #27
0x00000040 P-DMA0 Channel #28
0x00000040 P-DMA0 Channel #29
0x00000040 P-DMA0 Channel #30
0x00000040 P-DMA0 Channel #31
0x00000040 P-DMA0 Channel #32
0x00000040 P-DMA0 Channel #33
0x00000040 P-DMA0 Channel #34
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Datasheet
86
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH
0x402888C0
0x40288900
0x40288940
0x40288980
0x402889C0
0x40288A00
0x40288A40
0x40288A80
0x40288AC0
0x40288B00
0x40288B40
0x40288B80
0x40288BC0
0x40288C00
0x40288C40
0x40288C80
0x40288CC0
0x40288D00
0x40288D40
0x40288D80
0x40288DC0
0x40288E00
0x40288E40
0x40288E80
0x40288EC0
0x40288F00
0x40288F40
0x40288F80
0x40288FC0
0x40289000
0x40289040
0x40289080
0x402890C0
0x40289100
0x40289140
0x40289180
0x402891C0
0x40289200
0x40289240
0x40289280
0x402892C0
0x40289300
0x40289340
0x40289380
0x402893C0
0x00000040 P-DMA0 Channel #35
0x00000040 P-DMA0 Channel #36
0x00000040 P-DMA0 Channel #37
0x00000040 P-DMA0 Channel #38
0x00000040 P-DMA0 Channel #39
0x00000040 P-DMA0 Channel #40
0x00000040 P-DMA0 Channel #41
0x00000040 P-DMA0 Channel #42
0x00000040 P-DMA0 Channel #43
0x00000040 P-DMA0 Channel #44
0x00000040 P-DMA0 Channel #45
0x00000040 P-DMA0 Channel #46
0x00000040 P-DMA0 Channel #47
0x00000040 P-DMA0 Channel #48
0x00000040 P-DMA0 Channel #49
0x00000040 P-DMA0 Channel #50
0x00000040 P-DMA0 Channel #51
0x00000040 P-DMA0 Channel #52
0x00000040 P-DMA0 Channel #53
0x00000040 P-DMA0 Channel #54
0x00000040 P-DMA0 Channel #55
0x00000040 P-DMA0 Channel #56
0x00000040 P-DMA0 Channel #57
0x00000040 P-DMA0 Channel #58
0x00000040 P-DMA0 Channel #59
0x00000040 P-DMA0 Channel #60
0x00000040 P-DMA0 Channel #61
0x00000040 P-DMA0 Channel #62
0x00000040 P-DMA0 Channel #63
0x00000040 P-DMA0 Channel #64
0x00000040 P-DMA0 Channel #65
0x00000040 P-DMA0 Channel #66
0x00000040 P-DMA0 Channel #67
0x00000040 P-DMA0 Channel #68
0x00000040 P-DMA0 Channel #69
0x00000040 P-DMA0 Channel #70
0x00000040 P-DMA0 Channel #71
0x00000040 P-DMA0 Channel #72
0x00000040 P-DMA0 Channel #73
0x00000040 P-DMA0 Channel #74
0x00000040 P-DMA0 Channel #75
0x00000040 P-DMA0 Channel #76
0x00000040 P-DMA0 Channel #77
0x00000040 P-DMA0 Channel #78
0x00000040 P-DMA0 Channel #79
Datasheet
87
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT89_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT90_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT91_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT92_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT93_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT94_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT95_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT96_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT97_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT98_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT99_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT100_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT101_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT102_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT103_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT104_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT105_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT106_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT107_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT108_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT109_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT110_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT111_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT112_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT113_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT114_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT115_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT116_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT117_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT118_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT119_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT120_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT121_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT122_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT123_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT124_CH
0x40289400
0x40289440
0x40289480
0x402894C0
0x40289500
0x40289540
0x40289580
0x402895C0
0x40289600
0x40289640
0x40289680
0x402896C0
0x40289700
0x40289740
0x40289780
0x402897C0
0x40289800
0x40289840
0x40289880
0x402898C0
0x40289900
0x40289940
0x40289980
0x402899C0
0x40289A00
0x40289A40
0x40289A80
0x40289AC0
0x40289B00
0x40289B40
0x40289B80
0x40289BC0
0x40289C00
0x40289C40
0x40289C80
0x40289CC0
0x40289D00
0x40289D40
0x40289D80
0x40289DC0
0x40289E00
0x40289E40
0x40289E80
0x40289EC0
0x40289F00
0x00000040 P-DMA0 Channel #80
0x00000040 P-DMA0 Channel #81
0x00000040 P-DMA0 Channel #82
0x00000040 P-DMA0 Channel #83
0x00000040 P-DMA0 Channel #84
0x00000040 P-DMA0 Channel #85
0x00000040 P-DMA0 Channel #86
0x00000040 P-DMA0 Channel #87
0x00000040 P-DMA0 Channel #88
0x00000040 P-DMA0 Channel #89
0x00000040 P-DMA0 Channel #90
0x00000040 P-DMA0 Channel #91
0x00000040 P-DMA0 Channel #92
0x00000040 P-DMA0 Channel #93
0x00000040 P-DMA0 Channel #94
0x00000040 P-DMA0 Channel #95
0x00000040 P-DMA0 Channel #96
0x00000040 P-DMA0 Channel #97
0x00000040 P-DMA0 Channel #98
0x00000040 P-DMA0 Channel #99
0x00000040 P-DMA0 Channel #100
0x00000040 P-DMA0 Channel #101
0x00000040 P-DMA0 Channel #102
0x00000040 P-DMA0 Channel #103
0x00000040 P-DMA0 Channel #104
0x00000040 P-DMA0 Channel #105
0x00000040 P-DMA0 Channel #106
0x00000040 P-DMA0 Channel #107
0x00000040 P-DMA0 Channel #108
0x00000040 P-DMA0 Channel #109
0x00000040 P-DMA0 Channel #110
0x00000040 P-DMA0 Channel #111
0x00000040 P-DMA0 Channel #112
0x00000040 P-DMA0 Channel #113
0x00000040 P-DMA0 Channel #114
0x00000040 P-DMA0 Channel #115
0x00000040 P-DMA0 Channel #116
0x00000040 P-DMA0 Channel #117
0x00000040 P-DMA0 Channel #118
0x00000040 P-DMA0 Channel #119
0x00000040 P-DMA0 Channel #120
0x00000040 P-DMA0 Channel #121
0x00000040 P-DMA0 Channel #122
0x00000040 P-DMA0 Channel #123
0x00000040 P-DMA0 Channel #124
Datasheet
88
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
PERI_MS_PPU_FX_DW0_CH_STRUCT125_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT126_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT127_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT128_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT129_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT130_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT131_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT132_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT133_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT134_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT135_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT136_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT137_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT138_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT139_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT140_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT141_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT142_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH
0x40289F40
0x40289F80
0x40289FC0
0x4028A000
0x4028A040
0x4028A080
0x4028A0C0
0x4028A100
0x4028A140
0x4028A180
0x4028A1C0
0x4028A200
0x4028A240
0x4028A280
0x4028A2C0
0x4028A300
0x4028A340
0x4028A380
0x40298000
0x40298040
0x40298080
0x402980C0
0x40298100
0x40298140
0x40298180
0x402981C0
0x40298200
0x40298240
0x40298280
0x402982C0
0x40298300
0x40298340
0x40298380
0x402983C0
0x40298400
0x40298440
0x40298480
0x402984C0
0x40298500
0x40298540
0x40298580
0x402985C0
0x40298600
0x40298640
0x40298680
0x00000040 P-DMA0 Channel #125
0x00000040 P-DMA0 Channel #126
0x00000040 P-DMA0 Channel #127
0x00000040 P-DMA0 Channel #128
0x00000040 P-DMA0 Channel #129
0x00000040 P-DMA0 Channel #130
0x00000040 P-DMA0 Channel #131
0x00000040 P-DMA0 Channel #132
0x00000040 P-DMA0 Channel #133
0x00000040 P-DMA0 Channel #134
0x00000040 P-DMA0 Channel #135
0x00000040 P-DMA0 Channel #136
0x00000040 P-DMA0 Channel #137
0x00000040 P-DMA0 Channel #138
0x00000040 P-DMA0 Channel #139
0x00000040 P-DMA0 Channel #140
0x00000040 P-DMA0 Channel #141
0x00000040 P-DMA0 Channel #142
0x00000040 P-DMA1 Channel #0
0x00000040 P-DMA1 Channel #1
0x00000040 P-DMA1 Channel #2
0x00000040 P-DMA1 Channel #3
0x00000040 P-DMA1 Channel #4
0x00000040 P-DMA1 Channel #5
0x00000040 P-DMA1 Channel #6
0x00000040 P-DMA1 Channel #7
0x00000040 P-DMA1 Channel #8
0x00000040 P-DMA1 Channel #9
0x00000040 P-DMA1 Channel #10
0x00000040 P-DMA1 Channel #11
0x00000040 P-DMA1 Channel #12
0x00000040 P-DMA1 Channel #13
0x00000040 P-DMA1 Channel #14
0x00000040 P-DMA1 Channel #15
0x00000040 P-DMA1 Channel #16
0x00000040 P-DMA1 Channel #17
0x00000040 P-DMA1 Channel #18
0x00000040 P-DMA1 Channel #19
0x00000040 P-DMA1 Channel #20
0x00000040 P-DMA1 Channel #21
0x00000040 P-DMA1 Channel #22
0x00000040 P-DMA1 Channel #23
0x00000040 P-DMA1 Channel #24
0x00000040 P-DMA1 Channel #25
0x00000040 P-DMA1 Channel #26
Datasheet
89
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT33_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT57_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT58_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT59_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT60_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT64_CH
PERI_MS_PPU_FX_DMAC_TOP
0x402986C0
0x40298700
0x40298740
0x40298780
0x402987C0
0x40298800
0x40298840
0x40298880
0x402988C0
0x40298900
0x40298940
0x40298980
0x402989C0
0x40298A00
0x40298A40
0x40298A80
0x40298AC0
0x40298B00
0x40298B40
0x40298B80
0x40298BC0
0x40298C00
0x40298C40
0x40298C80
0x40298CC0
0x40298D00
0x40298D40
0x40298D80
0x40298DC0
0x40298E00
0x40298E40
0x40298E80
0x40298EC0
0x40298F00
0x40298F40
0x40298F80
0x40298FC0
0x40299000
0x402A0000
0x402A1000
0x402A1100
0x402A1200
0x402A1300
0x402A1400
0x402A1500
0x00000040 P-DMA1 Channel #27
0x00000040 P-DMA1 Channel #28
0x00000040 P-DMA1 Channel #29
0x00000040 P-DMA1 Channel #30
0x00000040 P-DMA1 Channel #31
0x00000040 P-DMA1 Channel #32
0x00000040 P-DMA1 Channel #33
0x00000040 P-DMA1 Channel #34
0x00000040 P-DMA1 Channel #35
0x00000040 P-DMA1 Channel #36
0x00000040 P-DMA1 Channel #37
0x00000040 P-DMA1 Channel #38
0x00000040 P-DMA1 Channel #39
0x00000040 P-DMA1 Channel #40
0x00000040 P-DMA1 Channel #41
0x00000040 P-DMA1 Channel #42
0x00000040 P-DMA1 Channel #43
0x00000040 P-DMA1 Channel #44
0x00000040 P-DMA1 Channel #45
0x00000040 P-DMA1 Channel #46
0x00000040 P-DMA1 Channel #47
0x00000040 P-DMA1 Channel #48
0x00000040 P-DMA1 Channel #49
0x00000040 P-DMA1 Channel #50
0x00000040 P-DMA1 Channel #51
0x00000040 P-DMA1 Channel #52
0x00000040 P-DMA1 Channel #53
0x00000040 P-DMA1 Channel #54
0x00000040 P-DMA1 Channel #55
0x00000040 P-DMA1 Channel #56
0x00000040 P-DMA1 Channel #57
0x00000040 P-DMA1 Channel #58
0x00000040 P-DMA1 Channel #59
0x00000040 P-DMA1 Channel #60
0x00000040 P-DMA1 Channel #61
0x00000040 P-DMA1 Channel #62
0x00000040 P-DMA1 Channel #63
0x00000040 P-DMA1 Channel #64
0x00000010 M-DMA0 main
PERI_MS_PPU_FX_DMAC_CH0_CH
0x00000100 M-DMA0 Channel #0
0x00000100 M-DMA0 Channel #1
0x00000100 M-DMA0 Channel #2
0x00000100 M-DMA0 Channel #3
0x00000100 M-DMA0 Channel #4
0x00000100 M-DMA0 Channel #5
PERI_MS_PPU_FX_DMAC_CH1_CH
PERI_MS_PPU_FX_DMAC_CH2_CH
PERI_MS_PPU_FX_DMAC_CH3_CH
PERI_MS_PPU_FX_DMAC_CH4_CH
PERI_MS_PPU_FX_DMAC_CH5_CH
Datasheet
90
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
PERI_MS_PPU_FX_DMAC_CH6_CH
PERI_MS_PPU_FX_DMAC_CH7_CH
0x402A1600
0x402A1700
0x402C0000
0x402C0800
0x402F0000
0x40300000
0x40300010
0x40300020
0x40300030
0x40300040
0x40300050
0x40300060
0x40300070
0x40300080
0x40300090
0x403000A0
0x403000B0
0x403000C0
0x403000D0
0x403000E0
0x403000F0
0x40300100
0x40300110
0x40300120
0x40300130
0x40300140
0x40300150
0x40300160
0x40300170
0x40300180
0x40300190
0x403001A0
0x403001B0
0x403001C0
0x403001D0
0x403001E0
0x403001F0
0x40300200
0x40300210
0x40300220
0x40302000
0x40302200
0x40302240
0x40310000
0x40310080
0x00000100 M-DMA0 Channel #6
0x00000100 M-DMA0 Channel #7
0x00000200 EFUSE control
0x00000200 EFUSE data
PERI_MS_PPU_FX_EFUSE_CTL
PERI_MS_PPU_FX_EFUSE_DATA
PERI_MS_PPU_FX_BIST
0x00001000 Built-in self test
0x00000008 HSIOm Port #0
0x00000008 HSIOm Port #1
0x00000008 HSIOm Port #2
0x00000008 HSIOm Port #3
0x00000008 HSIOm Port #4
0x00000008 HSIOm Port #5
0x00000008 HSIOm Port #6
0x00000008 HSIOm Port #7
0x00000008 HSIOm Port #8
0x00000008 HSIOm Port #9
0x00000008 HSIOm Port #10
0x00000008 HSIOm Port #11
0x00000008 HSIOm Port #12
0x00000008 HSIOm Port #13
0x00000008 HSIOm Port #14
0x00000008 HSIOm Port #15
0x00000008 HSIOm Port #16
0x00000008 HSIOm Port #17
0x00000008 HSIOm Port #18
0x00000008 HSIOm Port #19
0x00000008 HSIOm Port #20
0x00000008 HSIOm Port #21
0x00000008 HSIOm Port #22
0x00000008 HSIOm Port #23
0x00000008 HSIOm Port #24
0x00000008 HSIOm Port #25
0x00000008 HSIOm Port #26
0x00000008 HSIOm Port #27
0x00000008 HSIOm Port #28
0x00000008 HSIOm Port #29
0x00000008 HSIOm Port #30
0x00000008 HSIOm Port #31
0x00000008 HSIOm Port #32
0x00000008 HSIOm Port #33
0x00000008 HSIOm Port #34
0x00000010 HSIOm Analog multiplexer
0x00000010 HSIOm monitor
0x00000004 HSIOm Alternate JTAG
0x00000040 GPIO_ENH Port #0
0x00000040 GPIO_STD Port #1
PERI_MS_PPU_FX_HSIOM_PRT0_PRT
PERI_MS_PPU_FX_HSIOM_PRT1_PRT
PERI_MS_PPU_FX_HSIOM_PRT2_PRT
PERI_MS_PPU_FX_HSIOM_PRT3_PRT
PERI_MS_PPU_FX_HSIOM_PRT4_PRT
PERI_MS_PPU_FX_HSIOM_PRT5_PRT
PERI_MS_PPU_FX_HSIOM_PRT6_PRT
PERI_MS_PPU_FX_HSIOM_PRT7_PRT
PERI_MS_PPU_FX_HSIOM_PRT8_PRT
PERI_MS_PPU_FX_HSIOM_PRT9_PRT
PERI_MS_PPU_FX_HSIOM_PRT10_PRT
PERI_MS_PPU_FX_HSIOM_PRT11_PRT
PERI_MS_PPU_FX_HSIOM_PRT12_PRT
PERI_MS_PPU_FX_HSIOM_PRT13_PRT
PERI_MS_PPU_FX_HSIOM_PRT14_PRT
PERI_MS_PPU_FX_HSIOM_PRT15_PRT
PERI_MS_PPU_FX_HSIOM_PRT16_PRT
PERI_MS_PPU_FX_HSIOM_PRT17_PRT
PERI_MS_PPU_FX_HSIOM_PRT18_PRT
PERI_MS_PPU_FX_HSIOM_PRT19_PRT
PERI_MS_PPU_FX_HSIOM_PRT20_PRT
PERI_MS_PPU_FX_HSIOM_PRT21_PRT
PERI_MS_PPU_FX_HSIOM_PRT22_PRT
PERI_MS_PPU_FX_HSIOM_PRT23_PRT
PERI_MS_PPU_FX_HSIOM_PRT24_PRT
PERI_MS_PPU_FX_HSIOM_PRT25_PRT
PERI_MS_PPU_FX_HSIOM_PRT26_PRT
PERI_MS_PPU_FX_HSIOM_PRT27_PRT
PERI_MS_PPU_FX_HSIOM_PRT28_PRT
PERI_MS_PPU_FX_HSIOM_PRT29_PRT
PERI_MS_PPU_FX_HSIOM_PRT30_PRT
PERI_MS_PPU_FX_HSIOM_PRT31_PRT
PERI_MS_PPU_FX_HSIOM_PRT32_PRT
PERI_MS_PPU_FX_HSIOM_PRT33_PRT
PERI_MS_PPU_FX_HSIOM_PRT34_PRT
PERI_MS_PPU_FX_HSIOM_AMUX
PERI_MS_PPU_FX_HSIOM_MON
PERI_MS_PPU_FX_HSIOM_ALTJTAG
PERI_MS_PPU_FX_GPIO_PRT0_PRT
PERI_MS_PPU_FX_GPIO_PRT1_PRT
Datasheet
91
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
PERI_MS_PPU_FX_GPIO_PRT2_PRT
PERI_MS_PPU_FX_GPIO_PRT3_PRT
0x40310100
0x40310180
0x40310200
0x40310280
0x40310300
0x40310380
0x40310400
0x40310480
0x40310500
0x40310580
0x40310600
0x40310680
0x40310700
0x40310780
0x40310800
0x40310880
0x40310900
0x40310980
0x40310A00
0x40310A80
0x40310B00
0x40310B80
0x40310C00
0x40310C80
0x40310D00
0x40310D80
0x40310E00
0x40310E80
0x40310F00
0x40310F80
0x40311000
0x40311080
0x40311100
0x40310040
0x403100C0
0x40310140
0x403101C0
0x40310240
0x403102C0
0x40310340
0x403103C0
0x40310440
0x403104C0
0x40310540
0x403105C0
0x00000040 GPIO_STD Port #2
0x00000040 GPIO_STD Port #3
PERI_MS_PPU_FX_GPIO_PRT4_PRT
PERI_MS_PPU_FX_GPIO_PRT5_PRT
PERI_MS_PPU_FX_GPIO_PRT6_PRT
PERI_MS_PPU_FX_GPIO_PRT7_PRT
PERI_MS_PPU_FX_GPIO_PRT8_PRT
PERI_MS_PPU_FX_GPIO_PRT9_PRT
PERI_MS_PPU_FX_GPIO_PRT10_PRT
PERI_MS_PPU_FX_GPIO_PRT11_PRT
PERI_MS_PPU_FX_GPIO_PRT12_PRT
PERI_MS_PPU_FX_GPIO_PRT13_PRT
PERI_MS_PPU_FX_GPIO_PRT14_PRT
PERI_MS_PPU_FX_GPIO_PRT15_PRT
PERI_MS_PPU_FX_GPIO_PRT16_PRT
PERI_MS_PPU_FX_GPIO_PRT17_PRT
PERI_MS_PPU_FX_GPIO_PRT18_PRT
PERI_MS_PPU_FX_GPIO_PRT19_PRT
PERI_MS_PPU_FX_GPIO_PRT20_PRT
PERI_MS_PPU_FX_GPIO_PRT21_PRT
PERI_MS_PPU_FX_GPIO_PRT22_PRT
PERI_MS_PPU_FX_GPIO_PRT23_PRT
PERI_MS_PPU_FX_GPIO_PRT24_PRT
PERI_MS_PPU_FX_GPIO_PRT25_PRT
PERI_MS_PPU_FX_GPIO_PRT26_PRT
PERI_MS_PPU_FX_GPIO_PRT27_PRT
PERI_MS_PPU_FX_GPIO_PRT28_PRT
PERI_MS_PPU_FX_GPIO_PRT29_PRT
PERI_MS_PPU_FX_GPIO_PRT30_PRT
PERI_MS_PPU_FX_GPIO_PRT31_PRT
PERI_MS_PPU_FX_GPIO_PRT32_PRT
PERI_MS_PPU_FX_GPIO_PRT33_PRT
PERI_MS_PPU_FX_GPIO_PRT34_PRT
PERI_MS_PPU_FX_GPIO_PRT0_CFG
PERI_MS_PPU_FX_GPIO_PRT1_CFG
PERI_MS_PPU_FX_GPIO_PRT2_CFG
PERI_MS_PPU_FX_GPIO_PRT3_CFG
PERI_MS_PPU_FX_GPIO_PRT4_CFG
PERI_MS_PPU_FX_GPIO_PRT5_CFG
PERI_MS_PPU_FX_GPIO_PRT6_CFG
PERI_MS_PPU_FX_GPIO_PRT7_CFG
PERI_MS_PPU_FX_GPIO_PRT8_CFG
PERI_MS_PPU_FX_GPIO_PRT9_CFG
PERI_MS_PPU_FX_GPIO_PRT10_CFG
PERI_MS_PPU_FX_GPIO_PRT11_CFG
0x00000040 GPIO_STD Port #4
0x00000040 GPIO_STD Port #5
0x00000040 GPIO_STD Port #6
0x00000040 GPIO_STD Port #7
0x00000040 GPIO_STD Port #8
0x00000040 GPIO_STD Port #9
0x00000040 GPIO_STD Port #10
0x00000040 GPIO_STD Port #11
0x00000040 GPIO_STD Port #12
0x00000040 GPIO_STD Port #13
0x00000040 GPIO_STD Port #14
0x00000040 GPIO_STD Port #15
0x00000040 GPIO_STD Port #16
0x00000040 GPIO_STD Port #17
0x00000040 GPIO_STD Port #18
0x00000040 GPIO_STD Port #19
0x00000040 GPIO_STD Port #20
0x00000040 GPIO_STD Port #21
0x00000040 GPIO_STD Port #22
0x00000040 GPIO_STD Port #23
0x00000040 HSIO_STD Port #24
0x00000040 HSIO_STD Port #25
0x00000040 HSIO_STD Port #26
0x00000040 HSIO_STD Port #27
0x00000040 GPIO_STD Port #28
0x00000040 GPIO_STD Port #29
0x00000040 GPIO_STD Port #30
0x00000040 GPIO_STD Port #31
0x00000040 GPIO_STD Port #32
0x00000040 HSIO_STD Port #33
0x00000040 HSIO_STD Port #34
0x00000020 GPIO_ENH Port #0 configuration
0x00000020 GPIO_STD Port #1 configuration
0x00000020 GPIO_STD Port #2 configuration
0x00000020 GPIO_STD Port #3 configuration
0x00000020 GPIO_STD Port #4 configuration
0x00000020 GPIO_STD Port #5 configuration
0x00000020 GPIO_STD Port #6 configuration
0x00000020 GPIO_STD Port #7 configuration
0x00000020 GPIO_STD Port #8 configuration
0x00000020 GPIO_STD Port #9 configuration
0x00000020 GPIO_STD Port #10 configuration
0x00000020 GPIO_STD Port #11 configuration
Datasheet
92
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
PERI_MS_PPU_FX_GPIO_PRT12_CFG
PERI_MS_PPU_FX_GPIO_PRT13_CFG
PERI_MS_PPU_FX_GPIO_PRT14_CFG
PERI_MS_PPU_FX_GPIO_PRT15_CFG
PERI_MS_PPU_FX_GPIO_PRT16_CFG
PERI_MS_PPU_FX_GPIO_PRT17_CFG
PERI_MS_PPU_FX_GPIO_PRT18_CFG
PERI_MS_PPU_FX_GPIO_PRT19_CFG
PERI_MS_PPU_FX_GPIO_PRT20_CFG
PERI_MS_PPU_FX_GPIO_PRT21_CFG
PERI_MS_PPU_FX_GPIO_PRT22_CFG
PERI_MS_PPU_FX_GPIO_PRT23_CFG
PERI_MS_PPU_FX_GPIO_PRT24_CFG
PERI_MS_PPU_FX_GPIO_PRT25_CFG
PERI_MS_PPU_FX_GPIO_PRT26_CFG
PERI_MS_PPU_FX_GPIO_PRT27_CFG
PERI_MS_PPU_FX_GPIO_PRT28_CFG
PERI_MS_PPU_FX_GPIO_PRT29_CFG
PERI_MS_PPU_FX_GPIO_PRT30_CFG
PERI_MS_PPU_FX_GPIO_PRT31_CFG
PERI_MS_PPU_FX_GPIO_PRT32_CFG
PERI_MS_PPU_FX_GPIO_PRT33_CFG
PERI_MS_PPU_FX_GPIO_PRT34_CFG
PERI_MS_PPU_FX_GPIO_GPIO
0x40310640
0x403106C0
0x40310740
0x403107C0
0x40310840
0x403108C0
0x40310940
0x403109C0
0x40310A40
0x40310AC0
0x40310B40
0x40310BC0
0x40310C40
0x40310CC0
0x40310D40
0x40310DC0
0x40310E40
0x40310EC0
0x40310F40
0x40310FC0
0x40311040
0x403110C0
0x40311140
0x40314000
0x40315000
0x40320C00
0x40320D00
0x40320E00
0x40320F00
0x40321100
0x40380000
0x40380080
0x40380100
0x40388000
0x40388080
0x40388100
0x40390000
0x40390080
0x40390100
0x40580000
0x40580080
0x40580100
0x40580180
0x40580200
0x40580280
0x00000020 GPIO_STD Port #12 configuration
0x00000020 GPIO_STD Port #13 configuration
0x00000020 GPIO_STD Port #14 configuration
0x00000020 GPIO_STD Port #15 configuration
0x00000020 GPIO_STD Port #16 configuration
0x00000020 GPIO_STD Port #17 configuration
0x00000020 GPIO_STD Port #18 configuration
0x00000020 GPIO_STD Port #19 configuration
0x00000020 GPIO_STD Port #20 configuration
0x00000020 GPIO_STD Port #21 configuration
0x00000020 GPIO_STD Port #22 configuration
0x00000020 GPIO_STD Port #23 configuration
0x00000020 HSIO_STD Port #24 configuration
0x00000020 HSIO_STD Port #25 configuration
0x00000020 HSIO_STD Port #26 configuration
0x00000020 HSIO_STD Port #27 configuration
0x00000020 GPIO_STD Port #28 configuration
0x00000020 GPIO_STD Port #29 configuration
0x00000020 GPIO_STD Port #30 configuration
0x00000020 GPIO_STD Port #31 configuration
0x00000020 GPIO_STD Port #32 configuration
0x00000020 HSIO_STD Port #33 configuration
0x00000020 HSIO_STD Port #34 configuration
0x00000040 GPIO main
PERI_MS_PPU_FX_GPIO_TEST
0x00000008 GPIO test
PERI_MS_PPU_FX_SMARTIO_PRT12_PRT
PERI_MS_PPU_FX_SMARTIO_PRT13_PRT
PERI_MS_PPU_FX_SMARTIO_PRT14_PRT
PERI_MS_PPU_FX_SMARTIO_PRT15_PRT
PERI_MS_PPU_FX_SMARTIO_PRT17_PRT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT3_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT4_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT5_CNT
0x00000100 SMART I/O #12
0x00000100 SMART I/O #13
0x00000100 SMART I/O #14
0x00000100 SMART I/O #15
0x00000100 SMART I/O #17
0x00000080 TCPWM0 Group #0, Counter #0
0x00000080 TCPWM0 Group #0, Counter #1
0x00000080 TCPWM0 Group #0, Counter #2
0x00000080 TCPWM0 Group #1, Counter #0
0x00000080 TCPWM0 Group #1, Counter #1
0x00000080 TCPWM0 Group #1, Counter #2
0x00000080 TCPWM0 Group #2, Counter #0
0x00000080 TCPWM0 Group #2, Counter #1
0x00000080 TCPWM0 Group #2, Counter #2
0x00000080 TCPWM1 Group #0, Counter #0
0x00000080 TCPWM1 Group #0, Counter #1
0x00000080 TCPWM1 Group #0, Counter #2
0x00000080 TCPWM1 Group #0, Counter #3
0x00000080 TCPWM1 Group #0, Counter #4
0x00000080 TCPWM1 Group #0, Counter #5
Datasheet
93
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT6_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT7_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT8_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT9_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT10_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT11_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT12_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT13_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT14_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT15_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT16_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT17_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT18_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT19_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT20_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT21_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT22_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT23_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT24_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT25_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT26_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT27_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT28_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT29_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT30_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT31_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT32_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT33_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT34_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT35_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT36_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT37_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT38_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT39_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT40_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT41_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT42_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT43_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT44_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT45_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT46_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT47_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT48_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT49_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT50_CNT
0x40580300
0x40580380
0x40580400
0x40580480
0x40580500
0x40580580
0x40580600
0x40580680
0x40580700
0x40580780
0x40580800
0x40580880
0x40580900
0x40580980
0x40580A00
0x40580A80
0x40580B00
0x40580B80
0x40580C00
0x40580C80
0x40580D00
0x40580D80
0x40580E00
0x40580E80
0x40580F00
0x40580F80
0x40581000
0x40581080
0x40581100
0x40581180
0x40581200
0x40581280
0x40581300
0x40581380
0x40581400
0x40581480
0x40581500
0x40581580
0x40581600
0x40581680
0x40581700
0x40581780
0x40581800
0x40581880
0x40581900
0x00000080 TCPWM1 Group #0, Counter #6
0x00000080 TCPWM1 Group #0, Counter #7
0x00000080 TCPWM1 Group #0, Counter #8
0x00000080 TCPWM1 Group #0, Counter #9
0x00000080 TCPWM1 Group #0, Counter #10
0x00000080 TCPWM1 Group #0, Counter #11
0x00000080 TCPWM1 Group #0, Counter #12
0x00000080 TCPWM1 Group #0, Counter #13
0x00000080 TCPWM1 Group #0, Counter #14
0x00000080 TCPWM1 Group #0, Counter #15
0x00000080 TCPWM1 Group #0, Counter #16
0x00000080 TCPWM1 Group #0, Counter #17
0x00000080 TCPWM1 Group #0, Counter #18
0x00000080 TCPWM1 Group #0, Counter #19
0x00000080 TCPWM1 Group #0, Counter #20
0x00000080 TCPWM1 Group #0, Counter #21
0x00000080 TCPWM1 Group #0, Counter #22
0x00000080 TCPWM1 Group #0, Counter #23
0x00000080 TCPWM1 Group #0, Counter #24
0x00000080 TCPWM1 Group #0, Counter #25
0x00000080 TCPWM1 Group #0, Counter #26
0x00000080 TCPWM1 Group #0, Counter #27
0x00000080 TCPWM1 Group #0, Counter #28
0x00000080 TCPWM1 Group #0, Counter #29
0x00000080 TCPWM1 Group #0, Counter #30
0x00000080 TCPWM1 Group #0, Counter #31
0x00000080 TCPWM1 Group #0, Counter #32
0x00000080 TCPWM1 Group #0, Counter #33
0x00000080 TCPWM1 Group #0, Counter #34
0x00000080 TCPWM1 Group #0, Counter #35
0x00000080 TCPWM1 Group #0, Counter #36
0x00000080 TCPWM1 Group #0, Counter #37
0x00000080 TCPWM1 Group #0, Counter #38
0x00000080 TCPWM1 Group #0, Counter #39
0x00000080 TCPWM1 Group #0, Counter #40
0x00000080 TCPWM1 Group #0, Counter #41
0x00000080 TCPWM1 Group #0, Counter #42
0x00000080 TCPWM1 Group #0, Counter #43
0x00000080 TCPWM1 Group #0, Counter #44
0x00000080 TCPWM1 Group #0, Counter #45
0x00000080 TCPWM1 Group #0, Counter #46
0x00000080 TCPWM1 Group #0, Counter #47
0x00000080 TCPWM1 Group #0, Counter #48
0x00000080 TCPWM1 Group #0, Counter #49
0x00000080 TCPWM1 Group #0, Counter #50
Datasheet
94
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT51_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT52_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT53_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT54_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT55_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT56_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT57_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT58_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT59_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT60_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT61_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT62_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT63_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT64_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT65_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT66_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT67_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT68_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT69_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT70_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT71_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT72_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT73_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT74_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT75_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT76_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT77_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT78_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT79_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT80_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT81_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT82_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT83_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT3_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT4_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT5_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT6_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT7_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT8_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT9_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT10_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT11_CNT
0x40581980
0x40581A00
0x40581A80
0x40581B00
0x40581B80
0x40581C00
0x40581C80
0x40581D00
0x40581D80
0x40581E00
0x40581E80
0x40581F00
0x40581F80
0x40582000
0x40582080
0x40582100
0x40582180
0x40582200
0x40582280
0x40582300
0x40582380
0x40582400
0x40582480
0x40582500
0x40582580
0x40582600
0x40582680
0x40582700
0x40582780
0x40582800
0x40582880
0x40582900
0x40582980
0x40588000
0x40588080
0x40588100
0x40588180
0x40588200
0x40588280
0x40588300
0x40588380
0x40588400
0x40588480
0x40588500
0x40588580
0x00000080 TCPWM1 Group #0, Counter #51
0x00000080 TCPWM1 Group #0, Counter #52
0x00000080 TCPWM1 Group #0, Counter #53
0x00000080 TCPWM1 Group #0, Counter #54
0x00000080 TCPWM1 Group #0, Counter #55
0x00000080 TCPWM1 Group #0, Counter #56
0x00000080 TCPWM1 Group #0, Counter #57
0x00000080 TCPWM1 Group #0, Counter #58
0x00000080 TCPWM1 Group #0, Counter #59
0x00000080 TCPWM1 Group #0, Counter #60
0x00000080 TCPWM1 Group #0, Counter #61
0x00000080 TCPWM1 Group #0, Counter #62
0x00000080 TCPWM1 Group #0, Counter #63
0x00000080 TCPWM1 Group #0, Counter #64
0x00000080 TCPWM1 Group #0, Counter #65
0x00000080 TCPWM1 Group #0, Counter #66
0x00000080 TCPWM1 Group #0, Counter #67
0x00000080 TCPWM1 Group #0, Counter #68
0x00000080 TCPWM1 Group #0, Counter #69
0x00000080 TCPWM1 Group #0, Counter #70
0x00000080 TCPWM1 Group #0, Counter #71
0x00000080 TCPWM1 Group #0, Counter #72
0x00000080 TCPWM1 Group #0, Counter #73
0x00000080 TCPWM1 Group #0, Counter #74
0x00000080 TCPWM1 Group #0, Counter #75
0x00000080 TCPWM1 Group #0, Counter #76
0x00000080 TCPWM1 Group #0, Counter #77
0x00000080 TCPWM1 Group #0, Counter #78
0x00000080 TCPWM1 Group #0, Counter #79
0x00000080 TCPWM1 Group #0, Counter #80
0x00000080 TCPWM1 Group #0, Counter #81
0x00000080 TCPWM1 Group #0, Counter #82
0x00000080 TCPWM1 Group #0, Counter #83
0x00000080 TCPWM1 Group #1, Counter #0
0x00000080 TCPWM1 Group #1, Counter #1
0x00000080 TCPWM1 Group #1, Counter #2
0x00000080 TCPWM1 Group #1, Counter #3
0x00000080 TCPWM1 Group #1, Counter #4
0x00000080 TCPWM1 Group #1, Counter #5
0x00000080 TCPWM1 Group #1, Counter #6
0x00000080 TCPWM1 Group #1, Counter #7
0x00000080 TCPWM1 Group #1, Counter #8
0x00000080 TCPWM1 Group #1, Counter #9
0x00000080 TCPWM1 Group #1, Counter #10
0x00000080 TCPWM1 Group #1, Counter #11
Datasheet
95
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
573
574
575
576
577
578
579
580
581
582
583
584
585
586
588
589
590
591
592
593
594
595
596
597
598
599
600
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT1_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT3_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT4_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT5_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT6_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT7_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT8_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT9_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT10_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT11_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT12_CNT
PERI_MS_PPU_FX_EVTGEN0
0x40590000
0x40590080
0x40590100
0x40590180
0x40590200
0x40590280
0x40590300
0x40590380
0x40590400
0x40590480
0x40590500
0x40590580
0x40590600
0x403F0000
0x40420000
0x40460000
0x40480000
0x40490000
0x40520000
0x40520200
0x40520400
0x40520600
0x40520800
0x40540000
0x40540200
0x40540400
0x40540600
0x40540800
0x40521000
0x40541000
0x40530000
0x40550000
0x40600000
0x40610000
0x40620000
0x40630000
0x40640000
0x40650000
0x40660000
0x40670000
0x40680000
0x40690000
0x406A0000
0x40800000
0x40801000
0x00000080 TCPWM1 Group #2, Counter #0
0x00000080 TCPWM1 Group #2, Counter #1
0x00000080 TCPWM1 Group #2, Counter #2
0x00000080 TCPWM1 Group #2, Counter #3
0x00000080 TCPWM1 Group #2, Counter #4
0x00000080 TCPWM1 Group #2, Counter #5
0x00000080 TCPWM1 Group #2, Counter #6
0x00000080 TCPWM1 Group #2, Counter #7
0x00000080 TCPWM1 Group #2, Counter #8
0x00000080 TCPWM1 Group #2, Counter #9
0x00000080 TCPWM1 Group #2, Counter #10
0x00000080 TCPWM1 Group #2, Counter #11
0x00000080 TCPWM1 Group #2, Counter #12
0x00001000 Event generator #0
0x00010000 Serial Memory Interface #0
0x00010000 Secure Digital High Capacity #0
0x00010000 Ethernet0
PERI_MS_PPU_FX_SMIF0
PERI_MS_PPU_FX_SDHC0
PERI_MS_PPU_FX_ETH0
PERI_MS_PPU_FX_ETH1
0x00010000 Ethernet1
PERI_MS_PPU_FX_CANFD0_CH0_CH
PERI_MS_PPU_FX_CANFD0_CH1_CH
PERI_MS_PPU_FX_CANFD0_CH2_CH
PERI_MS_PPU_FX_CANFD0_CH3_CH
PERI_MS_PPU_FX_CANFD0_CH4_CH
PERI_MS_PPU_FX_CANFD1_CH0_CH
PERI_MS_PPU_FX_CANFD1_CH1_CH
PERI_MS_PPU_FX_CANFD1_CH2_CH
PERI_MS_PPU_FX_CANFD1_CH3_CH
PERI_MS_PPU_FX_CANFD1_CH4_CH
PERI_MS_PPU_FX_CANFD0_MAIN
PERI_MS_PPU_FX_CANFD1_MAIN
PERI_MS_PPU_FX_CANFD0_BUF
PERI_MS_PPU_FX_CANFD1_BUF
PERI_MS_PPU_FX_SCB0
0x00000200 CAN0, Channel #0
0x00000200 CAN0, Channel #1
0x00000200 CAN0, Channel #2
0x00000200 CAN0, Channel #3
0x00000200 CAN0, Channel #4
0x00000200 CAN1, Channel #0
0x00000200 CAN1, Channel #1
0x00000200 CAN1, Channel #2
0x00000200 CAN1, Channel #3
0x00000200 CAN1, Channel #4
0x00000100 CAN0 main
0x00000100 CAN1 main
0x00010000 CAN0 buffer
0x00010000 CAN1 buffer
0x00010000 SCB0
PERI_MS_PPU_FX_SCB1
0x00010000 SCB1
PERI_MS_PPU_FX_SCB2
0x00010000 SCB2
PERI_MS_PPU_FX_SCB3
0x00010000 SCB3
PERI_MS_PPU_FX_SCB4
0x00010000 SCB4
PERI_MS_PPU_FX_SCB5
0x00010000 SCB5
PERI_MS_PPU_FX_SCB6
0x00010000 SCB6
PERI_MS_PPU_FX_SCB7
0x00010000 SCB7
PERI_MS_PPU_FX_SCB8
0x00010000 SCB8
PERI_MS_PPU_FX_SCB9
0x00010000 SCB9
PERI_MS_PPU_FX_SCB10
0x00010000 SCB10
PERI_MS_PPU_FX_I2S0
0x00001000 AUDIOSS I2S0
PERI_MS_PPU_FX_I2S1
0x00001000 AUDIOSS I2S1
Datasheet
96
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
PERI_MS_PPU_FX_I2S2
0x40802000
0x40900000
0x40901000
0x40902000
0x40900800
0x40900840
0x40900880
0x409008C0
0x40900900
0x40900940
0x40900980
0x409009C0
0x40900A00
0x40900A40
0x40900A80
0x40900AC0
0x40900B00
0x40900B40
0x40900B80
0x40900BC0
0x40900C00
0x40900C40
0x40900C80
0x40900CC0
0x40900D00
0x40900D40
0x40900D80
0x40900DC0
0x40900E00
0x40900E40
0x40900E80
0x40900EC0
0x40900F00
0x40900F40
0x40900F80
0x40900FC0
0x40901800
0x40901840
0x40901880
0x409018C0
0x40901900
0x40901940
0x40901980
0x409019C0
0x40901A00
0x00001000 AUDIOSS I2S2
PERI_MS_PPU_FX_PASS0_SAR0_SAR
0x00000400 PASS SAR0
PERI_MS_PPU_FX_PASS0_SAR1_SAR
0x00000400 PASS SAR1
PERI_MS_PPU_FX_PASS0_SAR2_SAR
0x00000400 PASS SAR2
PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH
0x00000040 SAR0, Channel #0
0x00000040 SAR0, Channel #1
0x00000040 SAR0, Channel #2
0x00000040 SAR0, Channel #3
0x00000040 SAR0, Channel #4
0x00000040 SAR0, Channel #5
0x00000040 SAR0, Channel #6
0x00000040 SAR0, Channel #7
0x00000040 SAR0, Channel #8
0x00000040 SAR0, Channel #9
0x00000040 SAR0, Channel #10
0x00000040 SAR0, Channel #11
0x00000040 SAR0, Channel #12
0x00000040 SAR0, Channel #13
0x00000040 SAR0, Channel #14
0x00000040 SAR0, Channel #15
0x00000040 SAR0, Channel #16
0x00000040 SAR0, Channel #17
0x00000040 SAR0, Channel #18
0x00000040 SAR0, Channel #19
0x00000040 SAR0, Channel #20
0x00000040 SAR0, Channel #21
0x00000040 SAR0, Channel #22
0x00000040 SAR0, Channel #23
0x00000040 SAR0, Channel #24
0x00000040 SAR0, Channel #25
0x00000040 SAR0, Channel #26
0x00000040 SAR0, Channel #27
0x00000040 SAR0, Channel #28
0x00000040 SAR0, Channel #29
0x00000040 SAR0, Channel #30
0x00000040 SAR0, Channel #31
0x00000040 SAR1, Channel #0
0x00000040 SAR1, Channel #1
0x00000040 SAR1, Channel #2
0x00000040 SAR1, Channel #3
0x00000040 SAR1, Channel #4
0x00000040 SAR1, Channel #5
0x00000040 SAR1, Channel #6
0x00000040 SAR1, Channel #7
0x00000040 SAR1, Channel #8
Datasheet
97
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH21_CH
0x40901A40
0x40901A80
0x40901AC0
0x40901B00
0x40901B40
0x40901B80
0x40901BC0
0x40901C00
0x40901C40
0x40901C80
0x40901CC0
0x40901D00
0x40901D40
0x40901D80
0x40901DC0
0x40901E00
0x40901E40
0x40901E80
0x40901EC0
0x40901F00
0x40901F40
0x40901F80
0x40901FC0
0x40902800
0x40902840
0x40902880
0x409028C0
0x40902900
0x40902940
0x40902980
0x409029C0
0x40902A00
0x40902A40
0x40902A80
0x40902AC0
0x40902B00
0x40902B40
0x40902B80
0x40902BC0
0x40902C00
0x40902C40
0x40902C80
0x40902CC0
0x40902D00
0x40902D40
0x00000040 SAR1, Channel #9
0x00000040 SAR1, Channel #10
0x00000040 SAR1, Channel #11
0x00000040 SAR1, Channel #12
0x00000040 SAR1, Channel #13
0x00000040 SAR1, Channel #14
0x00000040 SAR1, Channel #15
0x00000040 SAR1, Channel #16
0x00000040 SAR1, Channel #17
0x00000040 SAR1, Channel #18
0x00000040 SAR1, Channel #19
0x00000040 SAR1, Channel #20
0x00000040 SAR1, Channel #21
0x00000040 SAR1, Channel #22
0x00000040 SAR1, Channel #23
0x00000040 SAR1, Channel #24
0x00000040 SAR1, Channel #25
0x00000040 SAR1, Channel #26
0x00000040 SAR1, Channel #27
0x00000040 SAR1, Channel #28
0x00000040 SAR1, Channel #29
0x00000040 SAR1, Channel #30
0x00000040 SAR1, Channel #31
0x00000040 SAR2, Channel #0
0x00000040 SAR2, Channel #1
0x00000040 SAR2, Channel #2
0x00000040 SAR2, Channel #3
0x00000040 SAR2, Channel #4
0x00000040 SAR2, Channel #5
0x00000040 SAR2, Channel #6
0x00000040 SAR2, Channel #7
0x00000040 SAR2, Channel #8
0x00000040 SAR2, Channel #9
0x00000040 SAR2, Channel #10
0x00000040 SAR2, Channel #11
0x00000040 SAR2, Channel #12
0x00000040 SAR2, Channel #13
0x00000040 SAR2, Channel #14
0x00000040 SAR2, Channel #15
0x00000040 SAR2, Channel #16
0x00000040 SAR2, Channel #17
0x00000040 SAR2, Channel #18
0x00000040 SAR2, Channel #19
0x00000040 SAR2, Channel #20
0x00000040 SAR2, Channel #21
Datasheet
98
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU fixed structure pair
Address
Size
Description
691
692
693
694
695
696
697
698
699
700
701
PERI_MS_PPU_FX_PASS0_SAR2_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH31_CH
PERI_MS_PPU_FX_PASS0_TOP
0x40902D80
0x40902DC0
0x40902E00
0x40902E40
0x40902E80
0x40902EC0
0x40902F00
0x40902F40
0x40902F80
0x40902FC0
0x409F0000
0x00000040 SAR2, Channel #22
0x00000040 SAR2, Channel #23
0x00000040 SAR2, Channel #24
0x00000040 SAR2, Channel #25
0x00000040 SAR2, Channel #26
0x00000040 SAR2, Channel #27
0x00000040 SAR2, Channel #28
0x00000040 SAR2, Channel #29
0x00000040 SAR2, Channel #30
0x00000040 SAR2, Channel #31
0x00001000 PASS0 SAR main
Datasheet
99
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Bus masters
23
Bus masters
The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus
master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC function-
ality.
Table 23-1
ID No.
Bus masters for access and protection control
Master ID
Description
Master ID for CM0+
0
1
2
3
4
5
9
CPUSS_MS_ID_CM0
Master ID for Crypto
CPUSS_MS_ID_CRYPTO
CPUSS_MS_ID_DW0
CPUSS_MS_ID_DW1
CPUSS_MS_ID_DMAC
CPUSS_MS_ID_SLOW0
CPUSS_MS_ID_FAST0
Master ID for P-DMA0
Master ID for P-DMA1
Master ID for M-DMA0
Master ID for External AHB-Lite Master 0 (SDHC)
Master ID for External AXI Master 0 (ETH0)
Master ID for External AXI Master 1 (ETH1)
Master ID for CM7_1
10 CPUSS_MS_ID_FAST1
13 CPUSS_MS_ID_CM7_1
14 CPUSS_MS_ID_CM7_0
15 CPUSS_MS_ID_TC
Master ID for CM7_0
Master ID for DAP Tap Controller
Datasheet
100
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Miscellaneous configuration
24
Miscellaneous configuration
Table 24-1
Miscellaneous configuration for XMC7200 devices
Sl. No.
Configuration
Number/Instances
Description
Number of clock paths. One for each of FLL, PLL, Direct and CSV
Number of CLK_HFs present
0
1
SRSS_NUM_CLKPATH
7
8
SRSS_NUM_HFROOT
PERI_PC_NR
Number of protection contexts
2
8
Number of asynchronous PCLK groups
3
PERI_PERI_PCLK_PCLK_GROUP_NR
2
Group 0, Number of divide-by-8 clock dividers
Group 0, Number of divide-by-16 clock dividers
Group 0, Number of divide-by-24.5 clock dividers
Group 0, Number of programmable clocks [1, 256]
Group 1, Number of divide-by-8 clock dividers
Group 1, Number of divide-by-16 clock dividers
Group 1, Number of divide-by-24.5 clock dividers
Group 1, Number of programmable clocks [1, 256]
Number of MPU regions in CM0+
4
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT
CPUSS_CM0P_MPU_NR
4
5
3
6
1
7
15
19
20
21
154
8
8
9
10
11
12
CM7_0 Floating point unit configuration.
0 - No FPU
13
CPUSS_CM7_0_FPU_LVL
2
1 - Single precision FPU
2 - Single and Double precision FPU
Number of MPU regions in CM7_0
14
15
16
17
18
CPUSS_CM7_0_MPU_NR
16
16
16
16
16
CM7_0 Instruction cache (ICACHE) size in KB
CM7_0 Data cache size (DCACHE) in KB
CM7_0 Instruction TCM (ITCM) size in KB
CM7_0 Data TCM (DTCM) size in KB
CPUSS_CM7_0_ICACHE_SIZE
CPUSS_CM7_0_DCACHE_SIZE
CPUSS_CM7_0_ITCM_SIZE
CPUSS_CM7_0_DTCM_SIZE
CM7_1 Floating point unit configuration.
0 - No FPU
19
CPUSS_CM7_1_FPU_LVL
2
1 - Single precision FPU
2 - Single and Double precision FPU
Number of MPU regions in CM7_1
CM7_1 Instruction cache (ICACHE) size in KB
CM7_1 Data cache size (DCACHE) in KB
CM7_1 Instruction TCM (ITCM) size in KB
CM7_1 Data TCM (DTCM) size in KB
Number of P-DMA0 channels
20
21
22
23
24
25
26
27
CPUSS_CM7_1_MPU_NR
CPUSS_CM7_1_ICACHE_SIZE
CPUSS_CM7_1_DCACHE_SIZE
CPUSS_CM7_1_ITCM_SIZE
CPUSS_CM7_1_DTCM_SIZE
CPUSS_DW0_CH_NR
16
16
16
16
16
143
65
8
Number of P-DMA1 channels
CPUSS_DW1_CH_NR
Number of M-DMA0 controller channels
CPUSS_DMAC_CH_NR
Number of 32-bit words in the IP internal memory buffer (to allow
for a 256-B, 512-B, 1-KB, 2-KB, 4-KB, 8-KB, 16-KB, and 32-KB
memory buffer)
28
29
CPUSS_CRYPTO_BUFF_SIZE
CPUSS_FAULT_FAULT_NR
2048
4
Number of fault structures
Number of IPC structures
0 - Reserved for CM0+ access
1 - Reserved for CM7_0 access
2 - Reserved for CM7_1 access
3 - Reserved for DAP access
Remaining for user purposes
30
CPUSS_IPC_IPC_NR
8
Number of SMPU protection structures
31
32
CPUSS_PROT_SMPU_STRUCT_NR
SCB0_EZ_DATA_NR
16
Number of EZ memory bytes. This memory is used in EZ mode,
CMD_RESP mode and FIFO mode.
Note: Only SCB0 supports EZ mode
256
Number of input triggers per counter, routed to one counter
33
34
35
TCPWM0_TR_ONE_CNT_NR
TCPWM0_TR_ALL_CNT_NR
TCPWM0_GRP_NR
3
12
3
Number of input triggers routed to all counters, based on the pin
package
Number of TCPWM0 counter groups
Datasheet
101
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Miscellaneous configuration
Table 24-1
Miscellaneous configuration for XMC7200 devices (continued)
Sl. No.
Configuration
Number/Instances
Description
Number of counters per TCPWM0 Group #0
36
37
38
39
40
41
TCPWM0_GRP_NR0_GRP_GRP_CNT_NR
TCPWM0_GRP_NR0_CNT_GRP_CNT_WIDTH
TCPWM0_GRP_NR1_GRP_GRP_CNT_NR
TCPWM0_GRP_NR1_CNT_GRP_CNT_WIDTH
TCPWM0_GRP_NR2_GRP_GRP_CNT_NR
TCPWM0_GRP_NR2_CNT_GRP_CNT_WIDTH
3
Counter width in number of bits per TCPWM0
Group #0
16
3
Number of counters per TCPWM0 Group #1
Counter width in number of bits per TCPWM0
Group #1
16
3
Number of counters per TCPWM0 Group #2
Counter width in number of bits per TCPWM0
Group #2
32
Number of TCPWM1 counter groups
42
43
TCPWM1_GRP_NR
3
Number of counters per TCPWM1 Group #0
TCPWM1_GRP_NR0_GRP_GRP_CNT_NR
84
Counter width in number of bits per TCPWM1
Group #0
44
45
46
TCPWM1_GRP_NR0_CNT_GRP_CNT_WIDTH
TCPWM1_GRP_NR1_GRP_GRP_CNT_NR
TCPWM1_GRP_NR1_CNT_GRP_CNT_WIDTH
16
12
16
Number of counters per TCPWM1 Group #1
Counter width in number of bits per TCPWM1
Group #1
Number of counters per TCPWM1 Group #2
47
48
49
50
TCPWM1_GRP_NR2_GRP_GRP_CNT_NR
TCPWM1_GRP_NR2_CNT_GRP_CNT_WIDTH
CANFD0_MRAM_SIZE / CANFD1_MRAM_SIZE
EVTGEN_COMP_STRUCT_NR
13
32
40
16
Counter width in number of bits per TCPWM1 Group #2
Message RAM size in KB shared by all the channels
Number of Event Generator comparator structures
Datasheet
102
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Development support
25
Development support
XMC7200 has a rich set of documentation, programming tools, and online resources to assist during the devel-
opment process. Visit www.infineon.com to find out more.
25.1
Documentation
A suite of documentation supports XMC7200 to ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
25.1.1
Software user guide
A step-by-step guide for using the peripheral driver library along with Infineon IDE ModusToolbox™ software.
25.1.2
Technical reference manual
The Technical Reference Manual (TRM) contains all the technical detail needed to use a XMC7200 device,
including a complete description of all registers. The TRM is available in the documentation section at
www.infineon.com.
25.2
Tools
XMC7200 is supported on Infineon IDE ModusToolbox™ software that gives user experience with either a local or
GitHub-hosted set of software repos. XMC7200 is also supported by Infineon programming utilities for
programming, erasing, or reading using Infineon’s MiniProg4 or KitProg3. More details are available in the
documentation section at www.infineon.com.
Datasheet
103
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26
Electrical specifications
The specifications listed here are preliminary.
26.1
Absolute maximum ratings
Use of this device under conditions outside the Min and Max limits listed in Table 26-1 may cause permanent
damage to the device. Exposure to conditions within the limits of Table 26-1 but beyond those of normal
operation for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C
in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under condi-
tions within the limits of Table 26-1 but beyond those of normal operation, the device may not operate to speci-
fication.
Power considerations
The average chip-junction temperature, TJ, in °C, may be calculated using Equation 1:
TJ = TA + PD JA
Equation. 1
Where:
TA is the ambient temperature in °C.
θJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PIO (PD = PINT + PIO).
PINT is the chip internal power. (PINT = VDDD × IDD + VDDA × IA)
PIO represents the power dissipation on input and output pins; user determined.
For most applications, PIO < PINT and may be neglected.
On the other hand, PIO may be significant if the device is configured to continuously drive external modules
and/or memories.
WARNING:
• The recommended operating conditions are required to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are guaranteed when the device is operated under these
conditions.
• Operation under any conditions other than those mentioned in the respective “Details/Conditions” may
adversely affect reliability of the device and can result in device failure.
• No guarantee is made with respect to any use, operating conditions, or combinations not represented in this
datasheet. If you want to operate the device under any condition other than those listed herein, contact the
sales representatives.
Datasheet
104
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings
Details/
Conditions
Spec ID
Parameter
Description
Min
Typ
Max
Units
For ports 0, 1, 2, 3, 4, 5, 16, 17,
18, 19, 20, 21, 22, 23, 28, 29, 30,
31
[41]
SID10
V
V
power supply voltage
V
– 0.3
–
V
+ 6.0
V
DDD_ABS
DDD
SSD
SSD
[41]
[41]
[41]
[41]
SID10B
SID10C
SID10D
SID10E
SID11
V
V
V
V
V
V
V
V
V
V
power supply voltage
power supply voltage
power supply voltage
power supply voltage
V
V
– 0.3
– 0.3
–
–
–
–
–
V
V
+ 6.0
+ 6.0
V
V
V
V
V
For ports 6, 7, 8, 9, 32
For ports 10, 11, 12, 13, 14, 15
For ports 24, 25
DDIO_1_ABS
DDIO_2_ABS
DDIO_3_ABS
DDIO_4_ABS
DDA_ABS
DDIO_1
DDIO_2
DDIO_3
DDIO_4
SSD
SSD
SSD
SSD
V
V
– 0.3
– 0.3
V
V
+ 4.0
+ 4.0
SSIO_3
SSIO_4
SSIO_3
SSIO_4
For ports 26, 27
[41]
analog power supply voltage
V
V
– 0.3
V
V
V
+ 6.0
V
V
= V
DDIO_2 DDA
DDA
SSA
SSA
SSA
SSA
SSA
[41]
REFH
SID12
V
Analog reference voltage, HIGH
– 0.3
–
+ 6.0
V
REFH_ABS
(V
+ 0.3 V)
DDA
[41]
SID12A
SID13
V
V
Analog reference voltage, LOW
V
V
– 0.3
– 0.3
–
–
+ 0.3
V
V
REFL_ABS
CCD_ABS
SSA
[41]
V
Power supply voltage
V
+ 1.21
SSD
CCD
SSD
For ports 0, 1, 2, 3, 4, 5, 16, 17,
18, 19, 20, 21, 22, 23, 28, 29, 30,
31
[41]
SID15A
V
Input voltage
V
– 0.5
–
V + 0.5
DDD
V
I0_ABS
SSD
[41]
[41]
[41]
[41]
SID15B
SID15C
SID15D
SID15E
V
V
V
V
Input voltage
Input voltage
Input voltage
Input voltage
V
V
– 0.5
– 0.5
–
–
–
–
V
V
V
V
+ 0.5
+ 0.5
+ 0.5
+ 0.5
V
V
V
V
For ports 6, 7, 8, 9, 32
For ports 10, 11, 12, 13, 14, 15
For ports 24, 25
I1_ABS
I2_ABS
I3_ABS
I4_ABS
SSD
SSD
DDIO_1
DDIO_2
DDIO_3
DDIO_4
V
V
– 0.5
– 0.5
SSIO_3
SSIO_4
For ports 26, 27
For EXT_PS_CTL0 in external
PMIC/transistor mode,
EXT_PS_CTL1 in external
transistor mode.
[41]
SID15F
V
Input voltage
V
– 0.5
–
V + 0.5
DDD
V
I5_ABS
SSD
[41]
SID16
V
V
Analog input voltage
V
V
– 0.3
– 0.3
–
–
V
+ 0.3
+ 0.3
V
V
IA_ABS
SSA
DDA
For ports 0, 1, 2, 3, 4, 5, 16, 17,
18, 19, 20, 21, 22, 23, 28, 29, 30,
31
[41]
SID17A
Output voltage
V
O0_ABS
SSD
DDD
[41]
SID17B
SID17C
SID17D
SID17E
V
V
V
V
Output voltage
V
V
– 0.3
– 0.3
–
–
–
–
V
V
V
V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
V
V
V
V
For ports 6, 7, 8, 9, 32
For ports 10, 11, 12, 13, 14, 15
For ports 24, 25
O1_ABS
O2_ABS
O3_ABS
O5_ABS
SSD
SSD
DDIO_1
DDIO_2
DDIO_3
DDIO_4
[41]
Output voltage
[41]
Output voltage
V
V
– 0.3
– 0.3
SSIO_3
SSIO_4
[41]
Output voltage
For ports 26, 27
For EXT_PS_CTL1/2 in external
PMIC mode, DRV_VOUT in
external transistor mode
[41]
SID17F
SID18
V
|I
Output voltage
V
– 0.3
–
–
V + 0.3
DDD
V
O4_ABS
SSD
[42, 43, 44]
|
Maximum clamp current
–5
5
mA
CLAMP_ABS
Maximum positive clamp current per
I/O supply pin. Limit applies to I/O
supply pin closest to the B+ injected
I
+B injected DC current is not
allowed for Ports 11 and 21.
CLAMP_SUP-
PLY_POS_ABS
SID18A
–
–
10
mA
[45]
current
Maximum negative clamp current per
I/O ground pin. Limit applies to I/O
supply pin closest to the B+ injected
I
+B injected DC current is not
allowed for Ports 11 and 21.
CLAMP_SUP-
PLY_NEG_ABS
SID18B
SID18C
–
–
–
–
10
50
mA
mA
[45]
current.
Maximum positive clamp current per
I/O supply, if not limited by the per
supply pin (based on SID18A).
I
CLAMP_TO-
TAL_POS_ABS
Notes
41.These parameters are based on the condition that VSSD = VSSA = VSSIO_3 = VSSIO_4 = 0.0 V.
42.A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including during
power transients. Refer to Figure 26-1 for more information on the recommended circuit.
43.VDDD and VDDIO must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range by
the clamp current.
44.When the conditions of [42], [43] and SID18A/B/C/D are met, |ICLAMP_ABS| supersedes VIA_ABS and VI_ABS.
Datasheet
105
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Details/
Conditions
Spec ID
Parameter
Description
Min
Typ
Max
Units
Maximum negative clamp current per
I/O ground, if not limited by the per
supply pin (based on SID18B).
I
CLAMP_TO-
SID18D
–
–
50
mA
TAL_NEG_ABS
GPIO_STD, configured for
drive_sel<1:0>= 0b0X
GPIO_STD, configured for
drive_sel<1:0>= 0b10
GPIO_STD, configured for
drive_sel<1:0>= 0b11
GPIO_ENH, configured for
drive_sel<1:0>= 0b0X
GPIO_ENH, configured for
drive_sel<1:0>= 0b10
GPIO_ENH, configured for
drive_sel<1:0>= 0b11
HSIO, configured for
drive_sel<1:0>= 0b00
HSIO, configured for
drive_sel<1:0>= 0b01
[46]
SID20A
SID20B
SID20C
SID21A
SID21B
SID21C
SID22A
SID22B
SID22C
SID22D
I
I
I
I
I
I
I
I
I
I
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OL1A_ABS
OL1B_ABS
OL1C_ABS
OL2A_ABS
OL2B_ABS
OL2C_ABS
OL3A_ABS
OL3B_ABS
OL3C_ABS
OL3D_ABS
[46]
[46]
[46]
[46]
[46]
[46]
[46]
[46]
[46]
1
6
2
1
10
2
HSIO, configured for
drive_sel<1:0>= 0b10
HSIO, configured for
drive_sel<1:0>= 0b11
1
0.5
For pin EXT_PS_CTL1 in
external PMIC mode and
[46]
SID23A
I
Sink maximum current
–
–
4
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode
OL4A_ABS
For pin EXT_PS_CTL1 in
external PMIC mode and
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode
[47]
SID23B
SID23C
I
I
Sink average current
–
–
–
–
1
OL4B_ABS
For pin DRV_VOUT in external
transistor mode
[46]
Sink maximum current
25
mA
OL4C_ABS
[48]
SID26A
SID26B
∑I
∑I
LOW-level total output current
–
–
–
–
50
85
mA
mA
OL_ABS_GPIO
OL_ABS_HSIO
[49]
LOW-level total output current
GPIO_STD, configured for
mA
[46]
SID27A
SID27B
SID27C
SID28A
SID28B
SID28C
SID29A
SID29B
Notes
I
I
I
I
I
I
I
I
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–5
–2
–1
–5
–2
–1
–10
–2
OH1A_ABS
OH1B_ABS
OH1C_ABS
OH2A_ABS
OH2B_ABS
OH2C_ABS
OH3A_ABS
OH3B_ABS
drive_sel<1:0>= 0b0X
GPIO_STD, configured for
drive_sel<1:0>= 0b10
[46]
[46]
[46]
[46]
[46]
[46]
[46]
mA
GPIO_STD, configured for
drive_sel<1:0>= 0b11
mA
GPIO_ENH, configured for
drive_sel<1:0>= 0b0X
mA
GPIO_ENH, configured for
drive_sel<1:0>= 0b10
mA
GPIO_ENH, configured for
drive_sel<1:0>= 0b11
mA
HSIO, configured for
drive_sel<1:0>= 0b00
mA
HSIO, configured for
drive_sel<1:0>= 0b01
mA
45.The definition of “closer” depends on the package. In TEQFP packaging, “closest” is determined by counting pins. For example, in a 176-TE-
QFP package, P17.4 (pin 120) is closer to the V
on pin 110 than on pin 132. Ports 11 and 21 should not be used for injection currents. The
DDD
impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os. In BGA packaging, the following IO port groups are treated
as having separate supply pins: Ports 0, 1, 2, 22, 23, and 28; Ports 3, 4, 5, 29, 30, and 31; Ports 6, 7, 8, 9, and 32; Ports 10, 12, 13, 14, 15, 26, and
27; Ports 16 and 17; Ports 18, 19, and 20.
46.The maximum output current is the peak current flowing through any one I/O.
47.The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms
period. The average value is the operation current × the operation ratio. The operation current period over the average current spec should
be less than 100 ns.
Datasheet
106
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Details/
Spec ID
Parameter
Description
Min
–
Typ
–
Max
–1
Units
mA
Conditions
HSIO, configured for
drive_sel<1:0>= 0b10
HSIO, configured for
drive_sel<1:0>= 0b11
[46]
[46]
SID29C
SID29D
I
I
HIGH-level maximum output current
HIGH-level maximum output current
OH3C_ABS
OH3D_ABS
–
–
–0.5
mA
For pin EXT_PS_CTL1 in
external PMIC mode and
[46]
SID30A
SID30B
SID30C
SID30D
I
I
I
I
Source maximum current
–
–
–
–
–
–
–
–
–4
–25
–1
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode.
OH4A_ABS
OH4B_ABS
OH4C_ABS
OH4D_ABS
For pin DRV_VOUT in external
transistor mode.
For pin EXT_PS_CTL1 in
external PMIC mode and
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode.
[46]
Source maximum current
mA
[47]
Source average current
For pin DRV_VOUT in external
transistor mode.
[47]
Source average current
–12
mA
[48]
SID33A
SID33B
SID33D
∑I
∑I
PIO
HIGH-level total output current
HIGH-level total output current
Total output power dissipation
–
–
–
–
–
–
–50
–85
307
mA
mA
mW
OH_ABS_GPIO
OH_ABS_HSIO
[49]
[50]
Power dissipation for external
PMIC/transistor mode
Power dissipation for internal regulator
mode
SID34
P
P
–
–
–
–
1000
2000
mW
mW
T
T
should not exceed 150 °C
should not exceed 150 °C
D
D
J
J
SID34A
SID36
SID37
SID38
T
T
T
Ambient temperature
Storage temperature
Operating Junction temperature
–40
–55
–40
–
–
–
125
150
150
°C
°C
°C
A
STG
J
Electrostatic discharge human body
model
Electrostatic discharge charged device
model for corner pins
Electrostatic discharge charged device
model for all other pins
The maximum pin current the device
can tolerate before triggering a latch-up
SID39A
SID39B1
SID39B2
SID39C
V
V
V
2000
750
–
–
–
–
–
–
V
V
ESD_HBM
ESD_CDM1
ESD_CDM2
500
–
V
I
–100
100
mA
LU
Notes
48.The total output current is the maximum current flowing through all GPIO_STD and GPIO_ENH I/Os.
49.The total output current is the maximum current flowing through all HSIO_STD I/Os.
50.The total output power dissipation is the maximum power dissipation flowing through all I/Os. PIO = (VDDD,VDDIO_1,VDDIO_2) ×
(|∑IOH_ABS_GPIO| + |∑IOL_ABS_GPIO|) + (VDDIO_3, VDDIO_4) × (|∑IOH_ABS_HSIO| + |∑IOL_ABS_HSIO|).
Datasheet
107
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VDDIO
Protection
Diode
Current Limiting Resistor
+B input
Protection
Diode
VSS
Figure 26-1
Example of a recommended circuit[50]
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Note
50.+B is the positive battery voltage around 45 V.
Datasheet
108
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.2
Device-level specifications
Table 26-2
Recommended operating conditions
Description
Recommended operating conditions
Unit
s
Spec ID Parameter
Min
Typ
Max
Details/Conditions
VDDD, VDDA
,
SID40
VDDIO_1
VDDIO_2
,
,
Power supply voltage[51]
2.7[52]
–
5.5[53]
V
Power supply voltage for
eFuse programming[54]
SID40A
SID40B
VDDIO_1_EFP
3
–
–
5.5
3.6
V
V
VDDIO_3
VDDIO_4
,
Power supply voltage
2.7
External VCCD power
supply range when
externally supplying
VCCD
SID40C VCCD
SID41 CS1
External VCCD power supply
Smoothing capacitor[55, 56]
1.10 1.15
1.20
22
V
6.79
–
µF
VCCD
VREF_L
CS1
VSSD
VSSA
Single-point connection
between analog and
digital grounds
Figure 26-2
Smoothing capacitor
Smoothing capacitor should be placed as close as possible to the VCCD pin.
Datasheet
109
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.3
DC specifications
Table 26-3
DC specifications, CPU current, and transition time specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Active/Sleep Mode
Description
Min Typ Max Units
Details/Conditions
CM0+ and CM7_0 clocked at 8 MHz
with IMO.
CM7_1 powered off.
All peripherals are disabled. No IO
toggling. CPUs CM7_0 and CM0+
executing Dhrystone from flash
V
current in internal
DDD
regulator mode, LPACTIVE
mode
I
DD_VDDD_CM0
7_8_1
SID49C1
–
10
17
mA with cache enabled.
Typ: T = 25 °C,
(CM0+ and CM7_0 at8 MHz, all
peripherals are disabled)
A
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 25 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
CM0+ and CM7_0 clocked at 8 MHz
with IMO.
CM7_1 powered off.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity. CPUs
mA CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in internal
DDD
regulator mode, LPACTIVE
mode
I
DD_VDDD_CM0
7_8
SID49C
–
12
226
(CM0+ and CM7_0 at8 MHz, all
peripherals are enabled)
Typ: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 105 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
Notes
51.VDDD, VDDIO_1, VDDIO_2, VDDIO_3, VDDIO_4, and VDDA do not have any sequencing limitation and can establish in any order. These supplies
(except VDDA and VDDIO_2) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.
52.3.0 V ±10% is supported with a lower BOD setting option for VDDD and VDDA. This setting provides robust protection for internal timing
but BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with
down to 3.0 V) and guarantees that all operating conditions are met.
53.5.0 V ±10% is supported with a higher OVD setting option for VDDD and VDDA. This setting provides robust protection for internal and
interface timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available
(consistent with up to 5.0 V) and guarantees that all operating conditions are met.
54.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single CAN
channel on VDDD domain, no activity on VDDIO_1).
55.Smoothing capacitor, CS1 is required per chip (not per VCCD pin). The VCCD pins must be connected together to ensure a low-imped-
ance connection (see the requirement in Figure 26.3 and Table 26-3).
56.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC
power across them provide less than their target capacitance, and their capacitance is not constant across their working voltage
range. When selecting capacitors for use with this device, ensure that the selected components provide the required capacitance
under the specific operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally
found within a part’s catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component
datasheet or direct from the manufacturer. Use of components that do not provide the required capacitance under the actual oper-
ating conditions may cause the device to operate to less than datasheet specifications.
Datasheet
110
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
CM7_1 powered off.
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity. CPUs
V
current in external
CCD
PMIC/transistor mode, Active
mode (CM7_0 at
I
DD1_VC-
CD_CM7_350
SID49E1
–
155
431
mA CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
350 MHz, CM0+ at 100 MHz, all
peripherals are enabled)
Typ: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
CM7_1 powered off.
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity. CPUs
mA CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in external
DDD
PMIC/transistor mode, Active
mode (CM7_0 at
I
DD1_-
VDDD_CM7_350
SID49E2
–
7
9
350 MHz, CM0+ at 100 MHz, all
peripherals are enabled)
Typ: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity. CM7
CPUs and CM0+ executing
Dhrystone from flash with cache
enabled.
VCCD current in external
PMIC/transistor mode, Active
mode (CM7 CPUs at 350 MHz,
CM0+ at 100 MHz, all periph-
erals are enabled)
SID50A1
I
–
209
543
mA
DD1_VCCD_F
Typ: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
Datasheet
111
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity. CM7
CPUs and CM0+ executing
Dhrystone from flash with cache
enabled.
VDDD current in external
PMIC/transistor mode, Active
mode (CM7 CPUs at 350 MHz,
CM0+ at 100 MHz, all periph-
erals are enabled)
SID50A2
I
–
7
9.3
mA
DD1_VDDD_F
Typ: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
IMO clocked at 8 MHz.
All peripherals, PLL, FLL, peripheral
clocks, interrupts, CSV, DMA are
disabled. No IO toggling.
V
current in internal
DDD
Typ: T = 25 °C,
A
SID53A
I
regulator mode. CM7_1=OFF,
Other CPUs in Sleep.
–
7
218
mA
DD2_8_VDDD
V
= 5.0 V,
DDD
process typ (TT)
Max: T = 105 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
Datasheet
112
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
T = 25 °C, 64-KB SRAM retention,
A
Event generator operates with ILO0
in DeepSleep and LP Active, Smart
I/O operates with ILO0, CM0+,
CM7_0: Retained,
CM7_1: OFF.
Typ: V
= 5.0 V,
DDD
process typ (TT)
Max: V = 5.5 V,
DDD
process worst (FF)
This average current is achieved
under the following conditions.
1. MCU repetitively goes from
DeepSleep to LP Active with a
period of 32 ms.
Average current for cyclic
wake-up operation. This is
the average current for the
specified LPACTIVE mode and
DeepSleep mode (RTC, WDT,
and Event Generator
2. One of the I/Os is toggled using
SID58A
I
–
60
198
µA Smart I/O to activate an external
sensor connected to an analog
input of A/D in DeepSleep
DD_CWU2
operating).
3. After 200 µs delay, the CM7_0
wakes up by Event generator
trigger to LP Active mode with IMO
and A/D conversion is triggered by
software.
4. Group A/D conversion is
performed on 5 channels with the
sampling time of 1 µs each.
5. Once the group A/D conversion is
finished, and the results fit in the
window of the range comparator,
the I/O is toggled back by software
to de-activate the sensor and the
CM7_0 goes back to DeepSleep.
DeepSleep Mode
DeepSleep Mode (RTC, WDT, and
event generator operating, all other
peripherals are off except for
retention registers),
64-KB SRAM retention, ILO0
operation
CM0+, CM7_0: Retained
SID64A
I
I
–
–
50
176
µA
DD_DS64A
T = 25 °C
A
Typ: V
= 5.0 V,
DDD
process typ (TT)
Max: V
= 5.5 V,
DDD
process worst (FF)
DeepSleep Mode steady state at T
= 125 °C (RTC, WDT, and event
generator operating, all other
peripherals are off except for
retention registers),
A
64 KB SRAM retention, ILO0
operation
SID64C
1.4
5.5
mA
DD_DS64C
CM0+, CM7_0: Retained
Typ: V
= 5.0 V
DDD
process worst (TT)
Max: V = 5.5 V
DDD
process worst (FF)
Datasheet
113
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Hibernate Mode
Description
Min Typ Max Units
Details/Conditions
ILO0/WDT operating. All other
SID66
I
Hibernate Mode
–
–
8
–
–
µA peripherals and all CPUs are off. T
A
DD_HIB1
= 25 °C, V
= 5.0 V, process typ (TT)
DDD
ILO0/WDT operating. All other
peripherals, and all CPUs are off. T
A
SID66A
I
Hibernate Mode
180
µA
DD_HIB2
= 125 °C, V
(FF)
= 5.5 V, process worst
DDD
Power Mode Transition Times
When the IMO is already running
and all HFCLK roots are at least 8
Power down time from Active
to DeepSleep
SID69
t
–
–
2.5
µs MHz. HFCLK roots that are slower
than this will require additional
time to turn off.
ACT_DS
When using the 8-MHz IMO.
DeepSleep to Active
SID67
t
t
–
–
–
–
10
26
µs Measured from wakeup interrupt
DS_ACT
transition time (IMO clock)
[57]
during DeepSleep until wakeup.
When using the 8-MHz IMO.
DeepSleep to Active
transition time (IMO clock,
flash execution)
Measured from wakeup interrupt
during DeepSleep until flash
SID67C
µs
DS_ACT1
[57]
execution.
When using the FLL to generate
96 MHz from the 8-MHz IMO.
DeepSleep to Active
SID67A
SID67D
SID67B
SID68
t
t
t
t
t
–
–
–
–
–
–
–
–
–
–
15
26
µs Measured from wakeup interrupt
during DeepSleep until the FLL
DS_ACT_FLL
DS_ACT_FLL1
DS_ACT_PLL
HVR_ACT
transition time (FLL clock)
[57]
locks.
When using the FLL to generate
96 MHz from the 8-MHz IMO.
DeepSleep to Active
transition time (FLL clock,
flash execution)
µs Measured from wakeup interrupt
during DeepSleep until flash
[57]
execution.
When using the PLL to generate
96 MHz from the 8-MHz IMO.
DeepSleep to Active
60
µs Measured from wakeup interrupt
during DeepSleep until the PLL
transition time (PLL clock)
[57]
locks.
Release time from HV reset
(POR, BOD, OVD, OCD, WDT,
Hibernate wakeup, or
Without boot runtime, guaranteed
265
10
µs
by design
XRES_L) release until CM0+
begins executing ROM boot
Release time from LV reset
(Fault, Internal system reset,
MCWDT, or CSV) during
Without boot runtime.
µs
SID68A
SID68B
LVR_ACT
Guaranteed by design
Active/Sleep until CM0+
begins executing ROM boot
Release time from LV reset
(Fault, or MCWDT) during
DeepSleep until CM0+ begins
executing ROM boot
ROM boot startup time or
wakeup time from hibernate
in NORMAL protection state
Without boot runtime.
µs
t
t
–
–
–
–
15
LVR_DS
Guaranteed by design
Guaranteed by design,CM0+
µs clocked at 100 MHz (Flash boot
version 3.1.0.554 and later)
SID80A
1640
RB_N
Note
57.At cold temperature -5°C to-40°C, the DeepSleep to Active transition time can be higher than the max time indicated by as much as
20µs.
Datasheet
114
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
ROM boot startup time or
wakeup time from hibernate
in SECURE protection state
Guaranteed by design, CM0+
SID80B
SID81A
t
t
–
–
–
–
2330
80
µs clocked at 100 MHz (Flash boot
version 3.1.0.554 and later)
RB_S
Guaranteed by design,
TOC2_-FLAGS=0x2CF, CM0+
µs clocked at 100MHz (Flash boot
version 3.1.0.554 and later), Listen
window = 0 ms
Flash boot startup time or
wakeup time from hibernate
in NORMAL/SECURE
FB
protection state
Guaranteed by design, CM0+
µs clockedat 50 MHz (Flash boot
version earlierthan 3.1.0.554)
Guaranteed by design, CM0+
µs clockedat 50 MHz (Flash boot
version earlier than 3.1.0.554)
SID80A_2
SID80B_2
t
t
2640
3890
RB_N_2
RB_S_2
Guaranteed by design,
TOC2_-FLAGS=0x2CF, CM0+
µs clocked at 50MHz (Flash boot
version earlier than3.1.0.554),
Listen window = 0 ms
SID81A_2
t
200
FB_2
Guaranteed by design,
TOC2_-FLAGS=0x24F, CM0+
clocked at 50MHz (Flash boot
version earlier than 3.1.0.554),
Listen window = 0 ms,Public key
SID81B_2
t
10000
µs
FB_A_2
exponent e = 0x010001, App size is
64 KB with the last 256 bytes being
a digital signature in
RSASSA-PKCS1-v1.5. Valid for
RSA2K.
Guaranteed by design,
TOC2_-FLAGS=0x24F, CM0+
clocked at 100MHz (Flash boot
version 3.1.0.554 and later), Listen
µs window=0ms, Publickeyexponent
e = 0x010001, App size is 64 KB with
the last 256 bytes being a digital
signature in RSASSA-PKCS1-v1.5.
Valid for RSA2K.
Flash boot with app
authentication time in
NORMAL/SECURE protection
state
SID81B
t
–
–
5000
1.15
FB_A
Regulator Specifications
SID600
V
Core supply voltage
1.05 1.1
V
CCD
Regulator operating current
in Active/Sleep mode
Regulator operating current
in DeepSleep mode
SID601
I
I
–
–
900 1500
µA Guaranteed by design
DDD_ACT
SID602
SID603
1.5
–
20
µA Guaranteed by design
DDD_DPSLP
RUSH
Average VDDD current until Cs1
mA (connected to VCCD pin) is charged
after Active regulator is turned on
I
In-rush current
–
850
Internal regulator output
current for operation
High current regulator output
current for operation
SID604
SID605
I
I
–
–
–
–
300
600
mA
ILDOUT
mA Using an external pass transistor
HCROUT
Output voltage LOW level for
external PMIC enable output
(EXT_PS_CTL1)
SID606
V
–
–
0.5
V
I
= 1 mA
OL_HCR
OL
Datasheet
115
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
= –1 mA
Output voltage HIGH level for
external PMIC enable output
(EXT_PS_CTL1)
Input voltage HIGH threshold
for external PMIC power OK
input (EXT_PS_CTL0)
Input voltage LOW threshold
for external PMIC power OK
input (EXT_PS_CTL0)
V
DDD
SID606A
SID607
V
V
V
V
–
–
–
–
–
–
V
V
I
OH
OH_HCR
IH_HCR
– 0.5
0.7 ×
DDD
–
V
0.3 ×
DDD
SID607A
SID607B
SID608
–
V
IL_HCR
V
Hysteresis for external PMIC
power OK input
0.05 ×
DDD
–
V
HYS_HCR
DRV_VOUT
V
(EXT_PS_CTL0)
DRV_VOUT pin output
current to external NPN base
current
See Architecture TRM for external
NPN transistor selection
I
–
9
mA
Datasheet
116
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.4
Reset specifications
Table 26-4
XRES_L reset
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
XRES_L DC Specifications
MAX: TA = 125 °C,
VDDD = 5.5 V,
SID73
IIDD_XRES
IDD when XRES_L asserted
–
–
2.5
mA
VCCD = 1.15 V,
process worst (FF)
SID74
SID75
SID76
SID77
SID78
VIH
VIL
RPULLUP
CIN
VHYSXRES
Input voltage HIGH threshold 0.7 × VDDD
–
–
–
–
–
–
V
V
kΩ
pF
V
CMOS Input
CMOS Input
Input voltage LOW threshold
Pull-up resistor
–
7
0.3 × VDDD
20
5
–
Input capacitance
–
Input voltage hysteresis
0.05 × VDDD
XRES_L AC Specifications
Without boot
runtime,
XRES_L deasserted to Active
transition time
SID70
tXRES_ACT
–
–
265
µs
guaranteed by
design
SID71
SID72
tXRES_PW
tXRES_FT
XRES_L pulse width
Pulse suppression width
5
100
–
–
–
–
µs
ns
release
HV/LV reset
System clock
System reset
release
RESET
ACTIVE
4
Modes
1
2
3
1:
2:
3:
4:
SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
SID80A/80B: ROM boot code operation
SID81A/81B: Flash boot code operation
User code operation
Figure 26-3
Reset sequence
Datasheet
117
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.5
I/O
Table 26-5
I/O specifications
Spec ID
Parameter
Description
Min
–
Typ
–
Max
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
Units
Details/Conditions
GPIO_STD Specifications for ports P1 through P23, P28 to P32
I
= 6 mA
OL
drive_sel<1:0> = 0b0X,
4.5 V ≤ V or V
DDIO_2
SID650
SID650C
SID651
SID652
SID652C
SID653
SID653C
SID654
SID655
SID656
SID656C
SID657
SID657C
V
V
V
V
V
V
V
V
V
V
V
V
V
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
V
V
V
V
V
V
V
V
V
V
V
V
V
OL1_GPIO_STD
OL1C_GPIO_STD
OL2_GPIO_STD
OL3_GPIO_STD
OL3C_GPIO_STD
OL4_GPIO_STD
OL4C_GPIO_STD
OH1_GPIO_STD
OH2_GPIO_STD
OH3_GPIO_STD
OH3C_GPIO_STD
OH4_GPIO_STD
OH4C_GPIO_STD
or
or
or
or
or
or
or
or
or
DDD
DDIO_1
V
≤ 5.5 V
I
= 5 mA
OL
drive_sel<1:0> = 0b0X,
–
–
4.5 V ≤ V or V
DDIO_2
DDD
DDIO_1
V
≤ 5.5 V
I
= 2 mA
OL
drive_sel<1:0> = 0b0X,
2.7 V ≤ V or V
–
–
DDD
DDIO_1
V
< 4.5 V
DDIO_2
I
= 1 mA
OL
drive_sel<1:0> = 0b10,
2.7 V ≤ V or V
–
–
DDD
DDIO_1
V
< 4.5 V
DDIO_2
I
= 2 mA
OL
drive_sel<1:0> = 0b10,
–
–
4.5 V ≤ V or V
DDIO_2
DDD
DDIO_1
V
≤ 5.5 V
I
= 0.5 mA
OL
drive_sel<1:0> = 0b11,
2.7 V ≤ V or V
–
–
DDD
DDIO_1
V
< 4.5 V
DDIO_2
I
= 1 mA
OL
drive_sel<1:0> = 0b11,
4.5 V ≤ V or V
–
–
DDD
DDIO_1
V
≤ 5.5 V
DDIO_2
(V
,
I
= –2 mA
DDD
OH
V
V
V
V
V
V
, or
drive_sel<1:0> = 0b0X,
2.7 V ≤ V or V
DDIO_1
–
V
) –
DDIO_2
DDD
DDIO_1
0.5
V
< 4.5 V
DDIO_2
(V
,
I
= –5 mA
DDD
OH
, or
drive_sel<1:0> = 0b0X,
4.5 V ≤ V or V
DDIO_1
–
–
V
) –
DDIO_2
DDD
DDIO_1
0.5
V
≤ 5.5 V
DDIO_2
(V
,
I
= –1 mA
DDD
OH
, or
drive_sel<1:0> = 0b10,
2.7 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) < 4.5 V
DDIO_2
(V
,
I
= –2 mA
DDD
OH
, or
drive_sel<1:0> = 0b10,
4.5 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) ≤ 5.5 V
DDIO_2
(V
,
I
= –0.5 mA
DDD
OH
, or
drive_sel<1:0> = 0b11,
2.7 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) < 4.5 V
DDIO_2
(V
,
I
= –1 mA
DDD
OH
, or
drive_sel<1:0> = 0b11,
4.5 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) ≤ 5.5 V
DDIO_2
SID658
SID659
R
R
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
PD_GPIO_STD
PU_GPIO_STD
0.7×(V
,
DDD
Input voltage HIGH
SID660
SID661
SID662
V
V
V
V
, or
–
–
–
–
–
–
V
V
V
IH_CMOS_GPIO_STD
IH_TTL_GPIO_STD
IH_AUTO_GPIO_STD
DDIO_1
threshold in CMOS mode
V
)
DDIO_2
Input voltage HIGH
threshold in TTL mode
2.0
0.8×(V
,
DDD
Input voltage HIGH
threshold in AUTO mode
V
, or
DDIO_1
DDIO_2
V
)
Datasheet
118
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
0.3 ×
DDD
(V
,
Input voltage LOW threshold
in CMOS mode
SID663
SID664
SID665
V
–
–
V
,
V
IL_CMOS_GPIO_STD
DDIO_1
or
V
)
DDIO_2
Input voltage LOW threshold
in TTL mode
V
V
–
–
–
0.8
V
V
IL_TTL_GPIO_STD
0.5 ×
(V
,
DDD
Input voltage LOW threshold
in AUTO mode
–
V
,
IL_AUTO_GPIO_STD
DDIO_1
or
V
)
DDIO_2
0.05 ×
(V
,
DDD
SID666
V
V
Hysteresis in CMOS mode
–
–
V
HYST_CMOS_GPIO_STD
HYST_AUTO_GPIO_STD
V
V
, or
DDIO_1
V
)
DDIO_2
0.05 ×
(V
,
DDD
SID668
SID669
Hysteresis in AUTO mode
Input pin capacitance
–
–
–
5
V
, or
DDIO_1
V
)
DDIO_2
C
–
pF
For 10 MHz and 100 MHz
in_GPIO_STD
For GPIO_STD except P21.0,
P21.1, P21.2, P21.3, P21.4,
P22.1, P22.2, P22.3, P23.3,
P23.4.
V
= V
= V
= V
=
DDIO_1
DDIO_2
DDD
DDA
SID670
I
Input leakage current
–250
0.02
250
nA
IL_GPIO_STD
5.5 V,
< V < V , V , V
DDD DDIO_1 DDIO_2
V
SSD
I
–40 °C T 125 °C
A
Typ: T = 25 °C, V
= V
DDIO_2
A
DDIO_1
= V
= V
= 5.0 V
DDD
DDA
Only for P21.0, P21.1, P21.2,
P21.3, P21.4, P22.1, P22.2,
P22.3, P23.3, P23.4.
V
= V
= V
= V
=
DDIO_1
DDIO_2
DDD
DDA
SID670C
I
Input leakage current
–700
0.02
700
nA
5.5 V,
< V < V , V , V
DDD DDIO_1 DDIO_2
IL_GPIO_STD_B
V
SSD
I
–40 °C T 125 °C
A
Typ: T = 25 °C, V
= V
DDIO_2
A
DDIO_1
= V
= V
= 5.0 V
DDD
DDA
20-pF load, drive_sel<1:0> =
0b00
Rise time or fall time (10% to
SID671
SID672
SID673
SID674
SID675
t
t
t
t
t
or t (fast)
1
1
1
1
1
–
–
–
–
–
10
20
20
20
20
ns
ns
ns
ns
ns
R
R
F
_20_0_GPIO_STD
_50_0_GPIO_STD
90% of V
)
DDIO
50-pF load, drive_sel<1:0> =
0b00
Rise time or fall time (10% to
90% of V
or t (fast)
F
)
DDIO
20-pF load, drive_sel<1:0> =
0b01
Rise time or fall time (10% to
or t (fast)
R
R
R
F
_20_1_GPIO_STD
_10_2_GPIO_STD
_6_3_GPIO_STD
90% of V
)
DDIO
10-pF load, drive_sel<1:0> =
0b10
Rise time or fall time (10% to
90% of V
or t (fast)
F
)
DDIO
Rise time or fall time (10% to
90% of V
or t (fast)
6-pF load, drive_sel<1:0> = 0b11
F
)
DDIO
10-pF to 400-pF load, RPU = 767
Ω, drive_sel<1:0>= 0b00,
Freq = 100 kHz
Fall time (30% to 70% of
DDIO
SID676
SID677
t
t
(fast)
0.35
0.35
–
–
250
250
ns
ns
F
F
_100_GPIO_STD
V
)
10-pF to 400-pF load, RPU = 350
Ω, drive_sel<1:0>= 0b00,
Freq = 400 kHz
Fall time (30% to 70% of
(fast)
_400_GPIO_STD
V
)
DDIO
Datasheet
119
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-5
I/O specifications (continued)
Spec ID
Parameter
Description
Input frequency
Min
Typ
Max
Units
Details/Conditions
SID678
f
–
–
100
MHz
IN_GPIO_STD
20 pF load,
drive_sel<1:0>= 00,
SID679
f
f
f
f
f
f
f
f
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50
32
25
15
25
15
15
10
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
OUT_GPIO_STD0H
OUT_GPIO_STD0L
OUT_GPIO_STD1H
OUT_GPIO_STD1L
OUT_GPIO_STD2H
OUT_GPIO_STD2L
OUT_GPIO_STD3H
OUT_GPIO_STD3L
4.5 V ≤V
≤ 5.5 V
or V
or V
or V
or V
or V
or V
or V
or V
or V
DDD
DDIO_1
DDIO_2
DDIO_2
DDIO_2
DDIO_2
DDIO_2
DDIO_2
DDIO_2
DDIO_2
20 pF load,
drive_sel<1:0>= 00,
SID680
SID681
SID682
SID683
SID684
SID685
SID686
2.7 V ≤V
or V
DDD
DDIO_1
< 4.5 V
20 pF load,
drive_sel<1:0>= 01,
4.5 V ≤V
≤ 5.5 V
or V
DDD
DDIO_1
20 pF load,
drive_sel<1:0>= 01,
2.7 V ≤V
or V
DDD
DDIO_1
< 4.5 V
10 pF load,
drive_sel<1:0>= 10,
4.5 V ≤V
≤ 5.5 V
or V
DDD
DDIO_1
10 pF load,
drive_sel<1:0>= 10,
2.7 V ≤V
or V
DDD
DDIO_1
< 4.5 V
6 pF load,
drive_sel<1:0>= 11,
4.5 V ≤V
≤ 5.5 V
or V
DDD
DDIO_1
6 pF load,
drive_sel<1:0>= 11,
2.7 V ≤V
or V
DDD
DDIO_1
< 4.5 V
GPIO_ENH Specifications for P0
I
= 6 mA
OL
SID650A
SID650D
SID651A
SID652A
SID652D
SID653A
SID653D
V
V
V
V
V
V
V
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
V
drive_sel<1:0> = 0b0X,
2.7 V ≤ V ≤ 5.5 V
OL1_GPIO_ENH
OL1D_GPIO_ENH
OL2_GPIO_ENH
OL3_GPIO_ENH
OL3D_GPIO_ENH
OL4_GPIO_ENH
OL4D_GPIO_ENH
DDD
I
= 5 mA
OL
drive_sel<1:0> = 0b0X,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= 2 mA
OL
drive_sel<1:0> = 0b0X,
2.7 V ≤ V < 4.5 V
DDD
I
= 1 mA
OL
drive_sel<1:0> = 0b10,
2.7 V ≤ V < 4.5 V
DDD
I
= 2 mA
OL
drive_sel<1:0> = 0b10,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= 0.5 mA
OL
drive_sel<1:0> = 0b11,
2.7 V ≤ V < 4.5 V
DDD
I
= 1 mA
OL
drive_sel<1:0> = 0b11,
4.5 V ≤ V ≤ 5.5 V
DDD
Datasheet
120
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
– 0.5
Typ
Max
Units
Details/Conditions
= –2 mA
I
OH
SID654A
SID655A
SID656A
SID656D
SID657A
SID657D
V
Output voltage HIGH level
V
V
V
V
V
V
–
–
V
drive_sel<1:0> = 0b0X,
2.7 V ≤ V < 4.5 V
OH1_GPIO_ENH
DDD
DDD
DDD
DDD
DDD
DDD
DDD
I
= –5 mA
OH
V
V
V
V
V
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
drive_sel<1:0> = 0b0X,
4.5 V ≤ V ≤ 5.5 V
OH2_GPIO_ENH
OH3_GPIO_ENH
OH3D_GPIO_ENH
OH4_GPIO_ENH
OH4D_GPIO_ENH
DDD
I
= –1 mA
OH
drive_sel<1:0> = 0b10,
2.7 V ≤ V < 4.5 V
DDD
I
= –2 mA
OH
drive_sel<1:0> = 0b10,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= –0.5 mA
OH
drive_sel<1:0> = 0b11,
2.7 V ≤ V < 4.5 V
DDD
I
= –1 mA
OH
drive_sel<1:0> = 0b11,
4.5 V ≤ V ≤ 5.5 V
DDD
SID658A
SID659A
R
R
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
PD_GPIO_ENH
PU_GPIO_ENH
Input voltage HIGH
SID660A
SID661A
SID662A
SID663A
SID664A
SID665A
V
V
V
V
V
V
0.7 × V
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
IH_CMOS_GPIO_ENH
IH_TTL_GPIO_ENH
IH_AUTO_GPIO_ENH
IL_CMOS_GPIO_ENH
IL_TTL_GPIO_ENH
IL_AUTO_GPIO_ENH
DDD
DDD
threshold in CMOS mode
Input voltage HIGH
threshold in TTL mode
2.0
Input voltage HIGH
threshold in AUTO mode
0.8 × V
Input voltage LOW threshold
in CMOS mode
–
–
–
0.3 × V
0.8
DDD
Input voltage LOW threshold
in TTL mode
Input voltage LOW threshold
in AUTO mode
0.5 × V
DDD
SID666A
SID668A
SID669A
V
V
Hysteresis in CMOS mode
Hysteresis in AUTO mode
Input pin capacitance
0.05 × V
0.05 × V
–
–
–
–
–
–
5
V
V
HYST_CMOS_GPIO_ENH
HYST_AUTO_GPIO_ENH
DDD
DDD
C
pF
For 10 MHz and 100 MHz
in_GPIO_ENH
V
V
= V
= 5.5 V,
DDA
DDD
< V < V
SSD
I
DDD
SID670A
I
Input leakage current
–350
0.055
350
nA
–40 °C T 125 °C
IL_GPIO_ENH
A
Typ: T = 25 °C,
A
= V
V
= 5.0 V
DDD
DDA
20 pF load, drive_sel<1:0> =
0b00, slow = 0
Rise time or fall time (10% to
SID671A
SID672A
SID673A
SID674A
SID675A
t
t
t
t
t
or t (fast)
1
1
1
1
1
–
–
–
–
–
10
20
20
20
20
ns
ns
ns
ns
ns
R
R
R
R
R
F
_20_0_GPIO_ENH
_50_0_GPIO_ENH
_20_1_GPIO_ENH
_10_2_GPIO_ENH
_6_3_GPIO_ENH
90% of V
)
DDIO
50 pF load, drive_sel<1:0> =
0b00, slow = 0
Rise time or fall time (10% to
90% of V
or t (fast)
F
)
DDIO
20-pF load, drive_sel<1:0> =
0b01, slow = 0
Rise time or fall time (10% to
90% of V
or t (fast)
F
)
DDIO
10-pF load, drive_sel<1:0> =
0b10, slow = 0
Rise time or fall time (10% to
90% of V
or t (fast)
F
)
DDIO
6-pF load, drive_sel<1:0> =
0b11, slow = 0
Rise time or fall time (10% to
90% of V
or t (fast)
F
)
DDIO
10-pF to 400-pF load,
drive_sel<1:0> = 0b00,
Fall time (30% to 70% of
DDIO
20×(V
/
/
/
DDD
SID676A
SID677A
t
t
t
(slow)
–
–
250
160
ns
ns
F_I2C
_GPIO_ENH
V
)
5.5)
slow = 1, minimum R = 400 Ω
PU
20-pF load, drive_sel<1:0> =
0b00, slow = 1,
output frequency = 1 MHz
Rise time or fall time (10% to 20×(V
DDD
or t (slow)
R
R
F
_20_GPIO_ENH
90% of V
)
5.5)
DDIO
400-pF load, drive_sel<1:0> =
0b00, slow = 1,
output frequency = 400 kHz
Rise time or fall time (10% to 20×(V
90% of V
DDD
SID678A
SID679A
or t (slow)
–
–
250
100
ns
F
_400_GPIO_ENH
)
5.5)
DDIO
f
Input frequency
–
MHz
IN_GPIO_ENH
Datasheet
121
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
20 pF load,
MHz drive_sel<1:0>= 0b00,
4.5 V ≤ V ≤ 5.5 V
SID680A
SID681A
SID682A
SID683A
SID684A
SID685A
SID686A
SID687A
f
Output frequency
–
–
50
OUT_GPIO_ENH0H
DDD
20 pF load,
MHz drive_sel<1:0>= 0b00,
2.7 V ≤ V < 4.5 V
f
f
f
f
f
f
f
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
–
–
32
25
15
25
15
15
10
OUT_GPIO_ENH0L
OUT_GPIO_ENH1H
OUT_GPIO_ENH1L
OUT_GPIO_ENH2H
OUT_GPIO_ENH2L
OUT_GPIO_ENH3H
OUT_GPIO_ENH3L
DDD
20 pF load,
MHz drive_sel<1:0>= 0b01,
4.5 V ≤ V ≤ 5.5 V
DDD
20 pF load,
MHz drive_sel<1:0>= 0b01,
2.7 V ≤ V < 4.5 V
DDD
10 pF load,
MHz drive_sel<1:0>= 0b10,
4.5 V ≤ V ≤ 5.5 V
DDD
10 pF load,
MHz drive_sel<1:0>= 0b10,
2.7 V ≤ V < 4.5 V
DDD
6 pF load,
MHz drive_sel<1:0>= 0b11,
4.5 V ≤ V ≤ 5.5 V
DDD
6 pF load,
MHz drive_sel<1:0>= 0b11,
2.7 V ≤ V < 4.5 V
DDD
HSIO Specifications for ports P24 through P27
I
= 0.1 mA,
OL
SID651B
SID652B
SID653B
V
V
V
Output LOW voltage
Output LOW voltage
Output LOW voltage
–
–
–
–
–
–
0.2
V
V
V
OL_HB_HSSPI
OL_eMMC
OL_SD
drive_sel<1:0> = 0b00
I
= 0.1 mA,
0.125 ×
DDIO_3/4
OL
V
drive_sel<1:0> = 0b00
I
= 2 mA,
0.125 ×
DDIO_3/4
OL
V
drive_sel<1:0> = 0b00
I
= 10 mA,
OL
SID654B
SID655B
SID656B
SID656E
V
V
V
V
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output LOW voltage
–
–
–
–
–
–
–
–
0.4
V
V
V
V
drive_sel<1:0> = 0b00,
= 2.7 V
OL1
OL2
OL3
OL4
V
DDIO_3/4
I
= 2 mA,
OL
0.4
0.4
0.4
drive_sel<1:0> = 0b01,
= 2.7 V
V
DDIO_3/4
I
= 1 mA,
OL
drive_sel<1:0> = 0b10,
= 2.7 V
V
DDIO_3/4
I
= 0.5 mA,
OL
drive_sel<1:0> = 0b11,
V
= 2.7 V
DDIO_3/4
I
= –0.1 mA
V
V
–
–
OH
DDIO_3/4
SID658B
SID659B
V
V
Output HIGH voltage
Output HIGH voltage
–
–
–
–
V
V
OH_HB_HSSPI
OH_eMMC
0.2
drive_sel<1:0> = 0b00
DDIO_3/4
I
= –0.1 mA
OH
(0.25 ×
drive_sel<1:0> = 0b00
V
)
DDIO_3/4
V
–
DDIO_3/4
I
= –2 mA
OH
SID660B
SID661B
V
V
Output HIGH voltage
Output HIGH voltage
(0.25 ×
–
–
–
–
V
V
OH_SD
OH1
drive_sel<1:0> = 0b00
V
)
DDIO_3/4
I
= –10 mA
OH
V
–
DDIO_3/4
drive_sel<1:0> = 0b00,
= 2.7 V
0.5
V
DDIO_3/4
I
= –2 mA
OH
V
–
DDIO_3/4
SID662B
V
Output HIGH voltage
–
–
V
drive_sel<1:0> = 0b01,
= 2.7 V
OH2
0.5
V
DDIO_3/4
Datasheet
122
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
= –1 mA
I
OH
V
V
–
–
DDIO_3/4
SID663B
SID663E
V
Output HIGH voltage
–
–
V
drive_sel<1:0> = 0b10,
= 2.7 V
OH3
OH3
0.5
V
DDIO_3/4
I
= –0.5 mA
OH
DDIO_3/4
V
Output HIGH voltage
–
–
V
drive_sel<1:0> = 0b11,
= 2.7 V
0.5
V
DDIO_3/4
SID664B
SID665B
R
R
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
PD
PU
Input HIGH voltage for
HYPERBUS™ and HSSPI in
CMOS mode
0.7 ×
DDIO_3/4
SID666B
V
–
–
V
vtrip_sel<1:0>=0b00
IH_CMOS
V
Input HIGH voltage for RGMII
in CMOS mode
0.8 ×
DDIO_3/4
SID667B
SID668E
SID669B
SID669E
V
V
V
V
–
–
–
–
–
–
–
–
V
V
V
V
vtrip_sel<1:0>=0b00
vtrip_sel<1:0>=0b01
vtrip_sel<1:0>=0b00
IH_RGMII
IH_TTL
V
Input Voltage HIGH
2
threshold for TTL mode
Input HIGH voltage for SD
and eMMC in CMOS mode
0.625 ×
DDIO_3/4
IH_SD_eMMC
V
Input Voltage HIGH
threshold in AUTO mode
0.8 ×
IH_AUTO
IL_CMOS
V
DDIO_3/4
vtrip_sel<1:0>=0b10
vtrip_sel<1:0>=0b00
Input LOW voltage for
HYPERBUS™ and HSSPI in
CMOS mode
0.3 ×
DDIO_3/4
SID670B
V
–
–
V
V
V
Input LOW voltage for RGMII
in CMOS mode
0.2 ×
DDIO_3/4
SID671B
SID672E
SID673B
SID673E
SID674B
V
V
V
V
V
V
–
–
–
–
–
–
–
–
–
V
V
V
V
V
vtrip_sel<1:0>=0b00
vtrip_sel<1:0>=0b01
vtrip_sel<1:0>=0b00
vtrip_sel<1:0>=0b10
vtrip_sel<1:0>=0b00
IL_RGMII
Input Voltage LOW threshold
for TTL mode
0.8
IL_TTL
Input LOW voltage for SD and
eMMC in CMOS mode
0.25 ×
DDIO_3/4
0.5 ×
IL_SD_eMMC
IL_AUTO
V
V
Input Voltage LOW threshold
in AUTO mode
DDIO_3/4
0.05 ×
DDIO_3/4
0.05 ×
Hysteresis in CMOS mode
–
HYST_CMOS
HYST_AUTO
V
SID674F
SID675B
Hysteresis in AUTO mode
Input pin capacitance
–
–
–
5
V
vtrip_sel<1:0>=0b10
V
DDIO_3
C
–
pF
For 10 MHz and 100 MHz
IN
V
V
= 3.6 V,
DDIO_3/4
< V < V
SSIO_3/4
I
DDIO_3/4
SID676B
I
Input leakage current
–450
1.02
450
nA
–40 °C T 125 °C
IL
A
Typ: T = 25 °C,
A
V
= 3.3 V
DDIO_3/4
SID678B
SID679B
SID680B
SID681B
SID682B
SID683B
SID684B
SID685B
f
f
f
f
f
f
f
f
Input frequency
Input frequency
Input frequency
Input frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
125
100
52
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
IN_RGMII
IN_HB_HSSPI
IN_eMMC
50
IN_SD
125
100
52
OUT_RGMII
OUT_HB_HSSPI
OUT_eMMC
OUT_SD
50
GPIO Input Specifications
Analog glitch filter (pulse
suppression width)
[58]
SID98
SID99
t
t
–
–
–
50
ns
ns
One filter per port
FT
Minimum pulse width for
GPIO interrupt
160
–
INT
Note
58.If a longer pulse suppression width is necessary, use Smart I/O.
Datasheet
123
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.6
Analog peripherals
SAR ADC
26.6.1
0xFFF
Actual conversion
characteristics
1.5 LSb
0xFFE
0xFFD
1 LSb (N - 1) + 0.5 LSb
VNT
0x003
0x002
0x001
Actual conversion
characteristics
Ideal
characteristics
0.5 LSb
VREFH
VREFL
Analog input
[LSb]
[V]
Total error of digital output N = ( VNT {1 LSb × (N – 1) + 0.5 LSb} ) / 1 LSb
1 LSb (Ideal value) = (VREFH – VREFL) / 4096
N: A/D converter digital output value
VZT (Ideal value): VREFL + 0.5 LSb [V]
VFST (Ideal value): VREFH – 1.5 LSb [V]
VNT: Voltage at which the digital output changes from N – 1 to N
Figure 26-4
ADC characteristics and error descriptions
Datasheet
124
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-6
Spec ID
SID100 A_RES
SID101 A_VINS
SID102A A_VDDA
12-bit SAR ADC DC specifications
Parameter
Description
Min
–
Typ
–
–
Max
12
VREFH
5.5
Units Details/Conditions
bits
V
V
SAR ADC resolution
Input voltage range VREFL
[59]
VDDA voltage range
VREFH voltage range
2.7
2.7
–
ADC performance
degrades when high
SID102 A_VREFH
–
–
VDDA
V
reference is higher
than supply (VDDA
ADC performance
)
degrades when low
referenceislowerthan
ground
SID103 A_VREFL
SID103A Vband_gap
VREFL voltage range
VSSA
VSSA
V
V
Internal band gap
reference voltage
0.882 0.9
0.918
Ratio of current
collected on a pin to
the positive current
injected into a
CLAMP_COU-
SID19A
SID19B
–
–
0.1
%
PLING_RATIO_POS
neighboring pin
Ratio of current
collected on a pin to
the negative current
injected into a
CLAMP_COU-
–
–
–
–
1.2
50
%
PLING_RATIO_NEG
neighboring pin
Internal pin
SID19C RCLAMP_INTERNAL
resistance to current
collection point
Ω
Datasheet
125
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.6.2
Calculating the impact of neighboring pins
The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and
resulting ADC offset caused by injection current using the below formula:
ILEAK = IINJECTED × CLAMP_COUPLING_RATIO
VERROR = ILEAK × (RCLAMP_INTERNAL + RSOURCE)
Code Error = VERROR × 212 / VREF
Where:
I
I
INJECTED is the injected current in mA.
LEAK is the calculated leakage current in mA.
VERROR is the voltage error calculated due to leakage currents in V.
VREF is the ADC reference voltage in V.
Differential linearity error
Integral linearity error
0xFFF
Ideal
characteristics
Actual conversion
characteristics
N + 1
0xFFE
VFST
Actual conversion
characteristics
(Measured value)
(1 LSb [N - 1] + VZT)
0xFFD
N
VNT
(Measured value)
0x004
0x003
0x002
0x001
N - 1
Actual conversion
characteristics
V(N +
1)T
(Measured value)
VNT
(Measured value)
Ideal
characteristics
Actual conversion
characteristics
N -2
VZT
(Measured value)
VREFL
Analog input
VREFL
Analog input
VREFH
VREFH
Integral linearity error of digital output N = (VNT
–
{1 LSb × (N
–
1) + VZT}) / 1 LSb
[LSb]
[LSb]
[V]
Differential linearity error of digital output N = (V(N + 1)T – VNT
1 LSb = (VFST – VZT ) / 4094
– 1 LSb ) / 1 LSb
V
V
ZT: Voltage for which digital output changes from 0x000 to 0x001
FST: Voltage for which digital output changes from 0xFFE to 0xFFF.
Figure 26-5
Integral and differential linearity errors
Note
59.VDDD must be greater than 0.8 × VDDA when ADC[2] is enabled. VDDIO_1 must be greater than 0.8 × VDDA when ADC[0] is enabled.
Datasheet
126
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2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
EXTERNAL CIRCUIT
INTERNAL EQUIVALENT CIRCUIT
VDDIO
Channel selection MUX and ADC
REXT
RVIN
CVIN
CEXT
CIN
ESD Protection
R
C
C
R
C
EXT: Source impedance
EXT: On-PCB capacitance
IN: I/O pad or Input capacitance
VIN: ADC equivalent input resistance
VIN: ADC equivalent input capacitance
K: Constant for sampling accuracy, K = ln(abs(4096/LSbSAMPLE))
Sampling Time (tSAMPLE) requirement is shown in the following equation
tSAMPLE > K x { CVIN x ( RVIN + REXT ) + ( CIN + CEXT ) x (REXT) } [seconds]
K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at 12-bit (LSbSAMPLE = ±0.5)
Figure 26-6
ADC equivalent circuit for analog input
Datasheet
127
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-7
SAR ADC AC specifications
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDA = 2.7 V to 5.5 V,
SID104 VZT
SID105 VFST
Zero transition voltage
–20
–
20
mV –40 °C ≤ TA ≤ 125 °C
before offset adjustment
VDDA = 2.7 V to 5.5 V,
mV –40 °C ≤ TA ≤ 125 °C
before offset adjustment
Full-scale transition
voltage
–20
–
20
SID114 fADC_4P5
SID114A fADC_2P7
ADC operating frequency
ADC operating frequency
Analog input sample time
2
2
–
–
26.67
13.34
MHz 4.5 V ≤ VDDA ≤ 5.5 V
MHz 2.7 V ≤ VDDA ≤ 4.5 V
4.5 V ≤ VDDA ≤ 5.5 V,
SID113 tS_4P5
SID113A tS_2P7
412
600
–
–
–
–
ns
(4.5 V ≤ VDDA
)
guaranteed by design
Analog input sample time
(2.7 V ≤ VDDA
2.7 V ≤ VDDA ≤ 4.5 V,
ns
)
guaranteed by design
Analog input sample time
when input is from
4.5 V ≤ VDDA ≤ 5.5 V,
µs
SID113B tS_DR_4P5
SID113C tS_DR_2P7
SID106 tST_4P5
SID106A tST_2P7
2
2.5
–
–
–
–
–
–
–
diagnostic reference (4.5
guaranteed by design
V ≤ VDDA
)
Analog input sample time
when input is from
2.7 V ≤ VDDA ≤ 4.5 V,
µs
diagnostic reference (2.7
guaranteed by design
V ≤ VDDA
)
4.5 V ≤ VDDA ≤ 5.5 V,
Max Throughput
80 MHz / 3 = 26.67 MHz,
1
Msps
(samples per second)
11 sampling cycles,
15 conversion cycles
2.7 V ≤ VDDA < 4.5 V
Max Throughput
80 MHz / 6 = 13.3 MHz,
–
0.5
Msps
(samples per second)
11 sampling cycles,
15 conversion cycles
ADC input sampling
capacitance
Input path ON resistance
(4.5 V to 5.5 V)
Input path ON resistance
(2.7 V to 4.5 V)
Diagnostic path ON resis-
tance (4.5 V to 5.5 V)
SID107 CVIN
–
–
–
–
–
–
–
–
4.8
9.4
13.9
40
pF Guaranteed by design
SID108 RVIN1
SID108A RVIN2
SID108B RDREF1
SID108C RDREF2
SID119 ACC_RLAD
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
%
–
–
Diagnostic path ON resis-
tance (2.7 V to 4.5 V)
–
50
Diagnostic reference
–4
4
resistor ladder accuracy
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
SID109 A_TE
Total error
–5
–
5
LSb
Total Error after offset
and gain adjustment at
12-bit resolution mode
Datasheet
128
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-7
SAR ADC AC specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
SID109A A_TEB
Total error
–12
–
12
LSb
Total error before offset
and gain adjustment at
12 bit resolution mode
VDDA = 2.7 V to 5.5 V,
SID110 A_INL
SID111 A_DNL
Integral nonlinearity
–2.5
–
–
2.5
1.9
LSb
LSb
–40 °C ≤ TA ≤ 125 °C
VDDA = 2.7 V to 5.5 V,
Differential nonlinearity –0.99
Channel to channel
–40 °C ≤ TA ≤ 125 °C
VDDA = 2.7 V to 5.5 V,
SID112 A_CE
variation (for channels
connected to same ADC)
–1
–
1
LSb
–40 °C ≤ TA ≤ 125 °C
Analog input leakage
current
Diagnostic reference
current
When input pad is
SID115 IAIC
–350
–
70
–
350
70
nA
µA
selected for conversion
SID116 IDIAGREF
Analog power supply
current while ADC is
operating
Analog power supply
current while ADC is not
operating
Analog reference voltage
current while ADC is
operating
SID117 IVDDA
SID117A IVDDA_DS
SID118 IVREF
–
–
–
–
360
1
550
21
µA Per enabled ADC
µA Per enabled ADC
µA Per enabled ADC
µA Per enabled ADC
360
1.8
550
5
Analog reference voltage
SID118A IVREF_LEAK current while ADC is not
operating
26.6.3
Temperature sensor
Table 26-8
Temperature sensor specifications
Spec ID Parameter
Description
Min
Typ Max Units
Details/Conditions
–40 °C ≤ TJ < 150 °C
SID201 TSENSACC2
Temperature sensor
accuracy 2
–5
–
5
°C
This spec is valid when using ADC[0]
(VDDIO_1), ADC[1] (VDDIO_2) or ADC[2]
(VDDD) with the following conditions:
a. 3.0 V ≤VDDD, VDDIO_1 or VDDIO_2 = VDDA
= VREFH ≤ 3.6 V
or
b. 4.5 V ≤VDDD, VDDIO_1 or VDDIO_2 = VDDA
= VREFH ≤ 5.5 V
–40 °C ≤ TJ ≤ 150 °C
SID201A TSENSACC3
Temperature sensor
accuracy 3
–10
–
10
°C
This spec is valid when using ADC[0]
(VDDIO_1) or ADC[2] (VDDD) with the
following condition:
2.7 V ≤ VDDD or VDDIO_1 ≤ 5.5 V and
2.7 V ≤ VDDA = VREFH ≤ 5.5 V and
0.8 × VDDA < VDDD or VDDIO_1
26.6.4
Voltage divider accuracy
Table 26-9
Voltage divider accuracy
Spec ID Parameter
Description
Min
Typ Max Units
Details/Conditions
Datasheet
129
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-9
Voltage divider accuracy
Uncorrected monitor
voltage divider
Any HV supply pad within 2.7 V–
5.5 V operating range
SID202 VMONDIV
accuracy (measured
by ADC), compared to
ideal supply/2
–20
2
20
%
Datasheet
130
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.7
AC specifications
Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 26-7
Definition of rise / fall times
VDDD or VDDIO_x
80 %
80 %
20 %
20 %
VSSD or VSSD_x or VSSIO_x
tR
tF
Time Reference Point Definition
VDDD or VDDIO_x
0.5 x VDDD or VDDIO_x
VSSD or VSSD_x or VSSIO_x
Timing Reference Points
Figure 26-7
AC timings specifications
Datasheet
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002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.8
Digital peripherals
Table 26-10 Timer/counter/PWM (TCPWM) specifications
Unit
s
Spec ID Parameter
Description
Min Typ Max
Details/Conditions
SID120 fC
TCPWM operating frequency
–
–
100 MHz fC = peripheral clock
Trigger Events can be
Stop, Start, Reload,
Count, Capture, or Kill
Input trigger pulse width for all
trigger events
SID121 tPWMENEXT
2 / fC
–
–
–
ns
depending on which
mode of operation is
selected.
Minimum possible width
of Overflow, Underflow,
SID122 tPWMEXT
Output trigger pulse widths
2 / fC
–
ns and Counter = Compare
(CC) value trigger
outputs
Minimum time between
SID123 tCRES
Resolution of counter
PWM resolution
1 / fC
1 / fC
–
–
–
–
ns
successive counts
Minimum pulse width of
SID124 tPWMRES
ns
PWM output
Minimum pulse width
ns between Quadrature
phase inputs.
SID125 tQRES
Quadrature inputs resolution
2 / fC
–
–
TCPWM Timing Diagrams
VIH
VIL
Input Signal
1
1
2
VOH
VOL
Output Signal
2
1: tPWMENEXT, tQRES
2: tPWMEXT
Figure 26-8
TCPWM timing diagrams
Datasheet
132
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID129
f
SCB operating frequency
–
–
100
MHz
SCB
2
I C Interface-Standard-mode
SID130
SID131
SID132
SID133
SID134
SID135
SID136
SID138
SID139
f
SCL clock frequency
–
–
–
–
–
–
–
–
–
–
100
–
kHz
ns
ns
ns
ns
ns
ns
ns
ns
SCL
t
t
t
t
t
t
t
t
Hold time, START condition
Low period of SCL
4000
4700
4000
4700
0
HD;STA
LOW
–
High period of SCL
–
HIGH
Setup time for a repeated START
Data hold time, for receiver
Data setup time
–
SU;STA
HD;DAT
SU;DAT
F
–
250
–
–
Fall time of SCL and SDA
Setup time for STOP
300
–
Input and output
4000
SU;STO
Bus-free time between START and
STOP
SID140
SID141
SID142
SID143
SID144
t
4700
–
–
–
–
–
–
–
ns
pF
ns
ns
V
BUF
C
Capacitive load for each bus line
–
–
–
0
3
400
3450
3450
0.4
B
Time for data signal from SCL LOW
to SDA output
t
t
VD;DAT
VD;ACK
Data valid acknowledge time
LOW level output voltage
LOW level output current
Open-drain at 3 mA sink
current
V
OL
SID145
I
–
mA
V
= 0.4 V
OL
OL
2
I C Interface-Fast-mode
SID150
SID151
SID152
SID153
SID154
SID155
SID156
f
SCL clock frequency
–
–
–
–
–
–
–
–
400
–
kHz
ns
ns
ns
ns
ns
ns
SCL_F
t
t
t
t
t
t
Hold time, START condition
Low period of SCL
600
1300
600
600
0
HD;STA_F
LOW_F
–
High period of SCL
–
HIGH_F
Setup time for a repeated START
Data hold time, for receiver
Data setup time
–
SU;STA_F
HD;DAT_F
SU;DAT_F
–
100
20 ×
DDD
5.5)
–
Input and output,
GPIO_ENH: slow mode,
400 pF load
(V
/
SID158
t
Fall time of SCL and SDA
–
300
300
ns
F_F
Input and output
GPIO_STD:
drive_sel<1:0>= 0b00
MIN: 10 pF load,
RPU = 35.41 kΩ
Max: 400 pF load,
RPU = 350 Ω
SID158A t
Fall time of SCL and SDA
Setup time for STOP
0.35
–
ns
FA_F
SID159
SID160
SID161
SID162
SID163
t
t
600
–
–
–
–
–
–
ns
ns
pF
ns
ns
Input and output
SU;STO_F
BUF_F
Bus free time between START and
STOP
1300
–
C
Capacitive load for each bus line
–
–
–
400
900
900
B_F
Time for data signal from SCL LOW
to SDA output
t
t
VD;DAT_F
VD;ACK_F
Data valid acknowledge time
Datasheet
133
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Pulse width of spikes that must be
suppressed by the input filter
SID164
SID165
SID166
t
–
–
50
ns
SP_F
Open-drain at 3 mA sink
current
V
LOW level output voltage
LOW level output current
LOW level output current
0
3
6
–
–
–
0.4
–
V
OL_F
OL_F
I
I
mA
mA
V
V
= 0.4 V
= 0.6 V
OL
OL
[60]
SID167
–
OL2_F
2
I C Interface-Fast-Plus mode
SID170
SID171
SID172
SID173
SID174
SID175
SID176
f
SCL clock frequency
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
MHz
ns
SCL_FP
t
t
t
t
t
t
Hold time, START condition
Low period of SCL
260
500
260
260
0
HD;STA_FP
LOW_FP
ns
High period of SCL
ns
HIGH_FP
Setup time for a repeated START
Data hold time, for receiver
Data setup time
ns
SU;STA_FP
HD;DAT_FP
SU;DAT_FP
ns
50
ns
20 ×
Input and output
20-pF load
SID178
t
Fall time of SCL and SDA
Setup time for STOP
(V
/
–
160
ns
F_FP
DDD
5.5)
GPIO_ENH: slow mode
SID179
SID180
SID181
SID182
SID183
SID184
t
t
260
500
–
–
–
–
–
–
–
–
–
ns
ns
pF
ns
ns
ns
Input and output
SU;STO_FP
BUF_FP
Bus free time between START and
STOP
C
Capacitive load for each bus line
20
450
450
50
B_FP
Time for data signal from SCL LOW
to SDA output
t
t
t
–
VD;DAT_FP
VD;ACK_FP
SP_FP
Data valid acknowledge time
–
Pulse width of spikes that must be
suppressed by the input filter
–
Open-drain at 3 mA sink
current
SID186
SID187
V
LOW level output voltage
LOW level output current
0
–
–
0.4
–
V
OL_FP
OL_FP
[61]
[61]
I
3
mA
V
= 0.4 V
OL
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
Do not use half-clock
MHz mode:
LATE_MISO_SAMPLE = 0
SID190
f
SPI operating frequency
–
–
12.5
SPI
SPI Master: MOSI valid after SCLK
driving edge
SID191
SID192
SID193
t
t
t
–
40
0
–
–
–
15
–
ns
ns
ns
DMO
DSI
SPI Master: MISO valid before SCLK
capturing edge
SPI Master: Previous MOSI data
hold time
–
HMO
Notes
60.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL
.
61.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL. However, this device does not support it.
Datasheet
134
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Only for
SPI Master: Previous MOSI data
hold time
SID193A t
–3.5
–
–
ns
SCB4_MOSI/P0.3 and
SCB4_CLK/P1.0
HMOA
SPI Master: MISO hold time after
SCLK capturing edge
SID196
SID198
t
t
t
0
–
–
–
–
ns
ns
DHI
SSEL valid, before the first SCK
capturing edge
0.5 ×
Min is half clock period
Min is half clock period
EN_SETUP
EN_SHOLD
(1/f
)
)
SPI
SSEL hold, after the last SCK
capturing edge
0.5 ×
SID199
SID195
–
–
–
ns
pF
(1/f
SPI
C
SPI capacitive load
–
10
SPIM_MS
SPI Interface Slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205
f
SPI operating frequency
–
–
10
–
MHz
ns
SPI_INT
SPI Slave: MOSI Valid before Sclock
capturing edge
SID206
t
5
–
DMI_INT
DSO_INT
SPI Slave: MISO Valid after Sclock
driving edge, in the
SID207
t
–
–
62
ns
internal-clocked mode
SPI Slave: Previous MISO data hold
time
SID208
SID209
SID210
SID211
t
t
t
t
3
–
–
–
–
–
–
–
–
ns
ns
ns
ns
HSP
SPI Slave: SSEL valid to first SCK
valid edge
33
33
20
EN_SETUP_INT
EN_HOLD_INT
EN_SETUP_PRE
SPI Slave Select active (LOW) from
last SCLK hold
SPI Slave: from SSEL valid, to SCK
falling edge before the first data bit
SPI Slave: from SCK falling edge
before the first data bit, to SSEL
invalid
SID212
t
20
–
–
ns
EN_HOLD_PRE
SPI Slave: from SSEL valid, to SCK
falling edge in the first data bit
SID213
SID214
t
t
20
20
–
–
–
–
ns
ns
EN_SETUP_CO
EN_HOLD_CO
SPI Slave: from SCK falling edge in
the first data bit, to SSEL invalid
SID215
SID216
SID217
SID218
SID219
t
t
t
t
SPI Slave Select inactive time
SPI SCLK pulse width HIGH
SPI SCLK pulse width LOW
SPI MOSI hold from SCLK
SPI Capacitive Load
40
20
20
12
–
–
–
–
–
–
–
–
ns
ns
ns
ns
pF
W_DIS_INT
W_SCLKH_INT
W_SCLKL_INT
SIH_INT
–
–
C
10
SPIS_INT
SPI Interface Slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220
f
SPI operating frequency
–
–
12.5
–
MHz
ns
SPI_EXT
SPI Slave: MOSI Valid before Sclock
capturing edge
SID221
t
5
–
DMI_EXT
DSO_EXT
SPI Slave: MISO Valid after Sclock
driving edge, in the
SID222
t
–
–
32
ns
external-clocked mode
SPI Slave: Previous MISO data hold
time
SID223
SID224
t
t
3
–
–
–
–
ns
ns
HSO_EXT
SPI Slave: SSEL valid to first SCK
valid edge
40
EN_SETUP_EXT
Datasheet
135
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SPI Slave Select active (LOW) from
last SCLK hold
SID225
t
40
–
–
ns
EN_HOLD_EXT
SID226
SID227
SID228
SID229
SID230
t
t
t
t
SPI Slave Select inactive time
SPI SCLK pulse width HIGH
SPI SCLK pulse width LOW
SPI MOSI hold from SCLK
SPI Capacitive Load
80
34
34
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
pF
W_DIS_EXT
W_SCLKH_EXT
W_SCLKL_EXT
SIH_EXT
–
–
C
10
SPIS_EXT
SPI Slave: MISO valid after SSEL
falling edge (CPHA = 0)
SID231
t
–
–
33
10
ns
VSS_EXT
UART Interface
SID240
f
Data rate
–
–
Mbps
BPS
8
9
7
70%
70%
70%
70%
30%
6
SDA
SCL
30%
30%
30%
12
8
9
4
70%
70%
70%
70%
70%
30%
30%
30%
30%
30%
30%
30%
2
1
3
START condition
11
70%
30%
70%
30%
70%
70%
SDA
SCL
30%
70%
2
14
10
13
70%
70%
30%
9th clock
5
Repeated START
condition
STOP condition
START condition
1: SCL clock period = 1/fSCL
2: Hold time, START condition = tHD;STA
3: LOW period of SCL = tLOW
4: HIGH period of SCL = tHIGH
5: Setup time for a repeated START = tSU;STA
6: Data hold time, for receiver = tHD;DAT
7: Data setup time = tSU;DAT
8: Fall time of SCL and SDA = tF
9: Rise time of SCL and SDA = tR
10: Setup time for STOP = tSU;STO
11: Bus-free time between START and STOP = tBUF
12: Time for data signal from SCL LOW to SDA output = tVD;DAT
13: Data valid acknowledge time = tVD;ACK
14: Pulse width of spikes that must be suppressed by the input filter = tSP
Figure 26-9
I2C timing diagrams
Datasheet
136
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE = 1)
CPHA = 0
9
SSEL
VOL
2
1
3
VOH
SCLK
4
4
(CPOL = 0)
VOL
SCLK
VOH
(CPOL = 1)
VOL
5
6
MISO
(input)
VIH
VIL
7
8
MOSI
(output)
VOH
VOL
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tDHI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 26-10 SPI master timing diagrams with LOW clock phase
Datasheet
137
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE = 1)
CPHA = 1
9
SSEL
VOL
2
3
1
SCLK
(CPOL = 0)
VOH
VOL
4
4
SCLK
VOH
(CPOL = 1)
VOL
5
6
MISO
(input)
VIH
VIL
7
8
MOSI
(output)
VOH
VOL
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tHDI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 26-11 SPI master timing diagrams with HIGH clock phase
Datasheet
138
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI Slave Timing Diagrams
CPHA = 0
10
SSEL
VOL
2
1
3
VOH
SCLK
4
4
(CPOL = 0)
VOL
SCLK
VOH
(CPOL = 1)
VOL
8
7
9
MISO
(output)
VOH
VOL
5
6
MOSI
(input)
VIH
VIL
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data valid after SSEL falling edge (CPHA = 0) = tVSS_EXT
9: output data hold time = tHSO
10: SSEL high pulse width = tDIS_EXT
Figure 26-12 SPI slave timing diagrams with LOW clock phase
Datasheet
139
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI slave Timing Diagrams
CPHA = 1
9
SSEL
VOL
3
1
VOH
SCLK
4
(CPOL = 0)
VOL
SCLK
VOH
(CPOL = 1)
VOL
8
7
MISO
(output)
VOH
VOL
5
6
MOSI
(input)
VIH
VIL
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data hold time = tHSO
9: SSEL high pulse width = tDIS_EXT
Figure 26-13 SPI slave timing diagrams with HIGH clock phase
Datasheet
140
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-12 CAN FD specifications
Paramete
Unit
s
Spec ID
SID630
Description
Min
–
Typ Max
Details/Conditions
fCCLK ≤ fHCLK,
r
,
fHCLK
fCCLK
System clock frequency
CAN clock frequency
–
–
100 MHz
100 MHz
guaranteed by design
fCCLK ≤ fHCLK,
,
SID631
–
guaranteed by design
26.9
Memory
Table 26-13 Flash DC specifications
Spec ID Parameter
SID260A VPE
Description
Erase and program voltage
Min
2.7
Typ Max Units
5.5
Details/Conditions
Details/Conditions
–
V
Table 26-14 Flash AC specifications
Spec ID Parameter
Description
Min Typ Max Units
Zero wait access to
code-flash memory up to
Maximum flash memory
operation frequency
SID257 fFO
–
–
100 MHz 100 MHz
Zero wait access with
cache hit up to 350 MHz
Maximum time from erase
suspend command till erase
is indeed suspend
SID254 tERS_SUS
–
250
–
–
–
–
37.5
–
µs
Minimum time allowed from
SID255 tERS_RES_SUS erase resume to erase
suspend
µs Guaranteed by design
At 100 MHz, N ≥ 4 and
µs multiple of 4, excludes
system overhead time
Blank check time for N-bytes
10 +
SID258 tBC_WF
of work-flash
0.3 × N
Sector erase time
SID259 tSECTORERASE1
Includes internal
–
–
45
15
80
5
90
30
ms
(code-flash: 32 KB)
preprogramming time
Sector erase time
Includes internal
SID260 tSECTORERASE2
ms
(code-flash: 8 KB)
preprogramming time
Sector erase time
Includes internal
SID261 tSECTORERASE3
–
160
15
ms
(work-flash, 2 KB)
preprogramming time
Sector erase time
Includes internal
SID262 tSECTORERASE4
–
ms
(work-flash, 128 B)
preprogramming time
Excludes system overhead
SID263 tWRITE1
SID264 tWRITE2
SID265 tWRITE3
SID266 tWRITE4
SID267 tFRET1
64-bit write time (code-flash)
–
30
40
60
µs
time
256-bit write time
(code-flash)
Excludes system overhead
–
70
µs
time
4096-bit write time
Excludes system overhead
–
320 1200
µs
(code-flash)[62]
time
Excludes system overhead
32-bit write time (work-flash)
–
30
–
60
–
µs
time
Code-flash retention.
TA (power on and off) ≤ 85
20
years
1000 program/erase cycles
°C average
Note
62.The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall write
time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector]).
Datasheet
141
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-14 Flash AC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
Work-flash retention.
TA (power on and off) ≤ 85
SID268 tFRET3
20
10
–
–
–
–
years
years
125,000 program/erase cycles
°C average
Work-flash retention.
TA (power on and off) ≤ 85
SID269 tFRET4
250,000 program/erase cycles
°C average
Typ: TA = 25 °C, VDDD = 5.0
V, VCCD = 1.15 V, process
typ (TT)
Program operating VCCD
SID612 ICC_ACT2
–
–
–
–
7
7
8
8
58
52
10
16
mA Max: TA = 125 °C,
current (code or work-flash)
V
DDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0
V, VCCD = 1.15 V, process
typ (TT)
Erase operating VCCD current
(code- or work-flash)
SID613 ICC_ACT3
SID612A ICC_ACT2A
SID613A ICC_ACT3A
mA Max: TA = 125 °C,
V
DDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0
V, VCCD = 1.15 V, process
typ (TT)
Program operating VDDD
mA Max: TA = 125 °C,
current (code or work-flash)
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0
V, VCCD = 1.15 V, process
typ (TT)
Erase operating VDDD current
(code- or work-flash)
mA Max: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Datasheet
142
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.10
System resources
Table 26-15 System resources
Spec ID Parameter
Power-on reset specifications
Details/
Description
Min
Typ
Max Units
Conditions
VDDD rising voltage to de assert
POR
Guaranteed by
design
SID270 VPOR_D
1.5
–
2.35
V
SID276 VPOR_A
SID271 VPOR_H
VDDD falling voltage to assert POR 1.45
–
–
2.1
300
V
mV
Level detection hysteresis
20
Delay between VDDD rising
through
Guaranteed by
design
SID272 tDLY_POR
–
–
3
µs
2.3 V and internal deassertion of
POR
SID273 tPOFF
VDDD Power off time
100
–
–
–
–
µs VDDD < 1.45 V
This ramp
s
V
DDD power ramp rate with
mV/µ
SID274 POR_RR1
robust BOD (BOD operation is
guaranteed)
100
supports robust
BOD
This ramp does
not supportrobust
BOD
VDDD power ramp rate without
robust BOD
mV/µ
s
SID275 POR_RR2
–
–
1000
tPOFF must be
satisfied.
High-voltage BOD (HV BOD) specifications
HV BOD 2.7 V rising detection
SID500 VTR_2P7_R
SID501 VTR_2P7_F
SID502 VTR_3P0_R
SID503 VTR_3P0_F
SID505 HVBOD_RR_A
SID506 HVBOD_RR_DS
2.474
2.55 2.627
V
V
V
V
point for VDDD and VDDA (default)
HV BOD 2.7 V falling detection
point for VDDD and VDDA (default)
HV BOD 3.0 V rising detection
point for VDDD and VDDA
HV BOD 3.0 V falling detection
point for VDDD and VDDA
Power ramp rate: VDDD and VDDA
(Active)
2.449 2.525 2.601
2.765
2.74
–
2.85 2.936
2.825 2.91
mV/µ
s
mV/µ
s
–
–
100
10
Power ramp rate: VDDD and VDDA
(DeepSleep)
–
Active mode delay between VDDD
falling/rising through VTR_2P7_F/R
or VTR_3P0_F/R and an internal HV
BOD signal transitioning
Active mode delay between VDDA
falling/rising through VTR_2P7_F/R
or VTR_3P0_F/R and internal HV
BOD signal transitioning
Guaranteed by
design
SID507 tDLY_ACT_HVBOD
–
–
–
–
0.5
1
µs
µs
Guaranteed by
design
SID507A tDLY_ACT_HVBOD
DeepSleep mode delay between
VDDD/VDDA falling/rising through
VTR_2P7_F/R or VTR_3P0_F/R and an
internal HV BOD signal transi-
tioning
Guaranteed by
design
SID507B tDLY_DS_HVBOD
–
–
4
µs
Datasheet
143
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-15 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
Response time of HV BOD,
VDDD/VDDA supply. (For
Guaranteed by
design
SID508 tRES_HVBOD
falling-then-rising supply at max
ramp rate; threshold is VTR_2P7_F
100
–
–
ns
or VTR_3P0_F
)
Low-voltage BOD (LV BOD) specifications
LV BOD rising detection point for
SID510 VTR_R_LVBOD
SID511 VTR_F_LVBOD
0.917 0.945 0.973
0.892 0.920 0.948
V
V
VCCD
LV BOD falling detection point for
VCCD
Active delay between VCCD
falling/rising through
Guaranteed by
design
SID515 tDLY_ACT_LVBOD
SID515A tDLY_DS_LVBOD
SID516 tRES_LVBOD
–
–
–
–
–
1
12
–
µs
µs
ns
VTR_R/F_LVBOD and an internal LV
BOD signal transitioning
DeepSleep mode delay between
VCCD falling/rising through
VTR_R/F_LVBOD and an internal LV
BOD signal transitioning
Guaranteed by
design
Response time of LV BOD (for
falling-then-rising supply at max
ramp rate; threshold is
Guaranteed by
design
100
VTR_F_LVBOD
)
Low-voltage detector (LVD) DC specifications
LVD 2.8 V falling detection point
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
SID520 VTR_2P8_F
SID521 VTR_2P9_F
SID522 VTR_3P0_F
SID523 VTR_3P1_F
SID524 VTR_3P2_F
SID525 VTR_3P3_F
SID526 VTR_3P4_F
SID527 VTR_3P5_F
SID528 VTR_3P6_F
SID529 VTR_3P7_F
SID530 VTR_3P8_F
SID531 VTR_3P9_F
SID532 VTR_4P0_F
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
for VDDD
LVD 2.9 V falling detection point
for VDDD
LVD 3.0 V falling detection point
for VDDD
LVD 3.1 V falling detection point
for VDDD
LVD 3.2 V falling detection point
for VDDD
LVD 3.3 V falling detection point
for VDDD
LVD 3.4 V falling detection point
for VDDD
LVD 3.5 V falling detection point
for VDDD
LVD 3.6 V falling detection point
for VDDD
LVD 3.7 V falling detection point
for VDDD
LVD 3.8 V falling detection point
for VDDD
LVD 3.9 V falling detection point
for VDDD
LVD 4.0 V falling detection point
for VDDD
Typ –
4%
Typ +
4%
Datasheet
144
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-15 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
2825
2925
3025
3125
3225
3325
3425
3525
3625
3725
3825
Max Units
Conditions
LVD 4.1 V falling detection point
for VDDD
LVD 4.2 V falling detection point
for VDDD
LVD 4.3 V falling detection point
for VDDD
LVD 4.4 V falling detection point
for VDDD
LVD 4.5 V falling detection point
for VDDD
LVD 4.6 V falling detection point
for VDDD
LVD 4.7 V falling detection point
for VDDD
LVD 4.8 V falling detection point
for VDDD
LVD 4.9 V falling detection point
for VDDD
LVD 5.0 V falling detection point
for VDDD
LVD 5.1 V falling detection point
for VDDD
LVD 5.2 V falling detection point
for VDDD
LVD 5.3 V falling detection point
for VDDD
LVD 2.8 V rising detection point
for VDDD
LVD 2.9 V rising detection point
for VDDD
LVD 3.0 V rising detection point
for VDDD
LVD 3.1 V rising detection point
for VDDD
LVD 3.2 V rising detection point
for VDDD
LVD 3.3 V rising detection point
for VDDD
LVD 3.4 V rising detection point
for VDDD
LVD 3.5 V rising detection point
for VDDD
LVD 3.6 V rising detection point
for VDDD
LVD 3.7 V rising detection point
for VDDD
LVD 3.8 V rising detection point
for VDDD
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ +
mV
SID533 VTR_4P1_F
SID534 VTR_4P2_F
SID535 VTR_4P3_F
SID536 VTR_4P4_F
SID537 VTR_4P5_F
SID538 VTR_4P6_F
SID539 VTR_4P7_F
SID540 VTR_4P8_F
SID541 VTR_4P9_F
SID542 VTR_5P0_F
SID543 VTR_5P1_F
SID544 VTR_5P2_F
SID545 VTR_5P3_F
SID546 VTR_2P8_R
SID547 VTR_2P9_R
SID548 VTR_3P0_R
SID549 VTR_3P1_R
SID550 VTR_3P2_R
SID551 VTR_3P3_R
SID552 VTR_3P4_R
SID553 VTR_3P5_R
SID554 VTR_3P6_R
SID555 VTR_3P7_R
SID556 VTR_3P8_R
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
Same as VTR_2P8_F
+ 25 mV
Same as VTR_2P9_F
+ 25 mV
Same as VTR_3P0_F
+ 25 mV
Same as VTR_3P1_F
+ 25 mV
Same as VTR_3P2_F
+ 25 mV
Same as VTR_3P3_F
+ 25 mV
Same as VTR_3P4_F
+ 25 mV
Same as VTR_3P5_F
+ 25 mV
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
Same as VTR_3P6_F
+ 25 mV
Same as VTR_3P7_F
+ 25 mV
Same as VTR_3P8_F
+ 25 mV
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Datasheet
145
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-15 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
3925
4025
4125
4225
4325
4425
4525
4625
4725
4825
4925
5025
5125
5225
5325
–
Max Units
Conditions
LVD 3.9 V rising detection point
for VDDD
LVD 4.0 V rising detection point
for VDDD
LVD 4.1 V rising detection point
for VDDD
LVD 4.2 V rising detection point
for VDDD
LVD 4.3 V rising detection point
for VDDD
LVD 4.4 V rising detection point
for VDDD
LVD 4.5 V rising detection point
for VDDD
LVD 4.6 V rising detection point
for VDDD
LVD 4.7 V rising detection point
for VDDD
LVD 4.8 V rising detection point
for VDDD
LVD 4.9 V rising detection point
for VDDD
LVD 5.0 V rising detection point
for VDDD
LVD 5.1 V rising detection point
for VDDD
LVD 5.2 V rising detection point
for VDDD
LVD 5.3 V rising detection point
for VDDD
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ –
4%
Typ +
mV
Same as VTR_3P9_F
+ 25 mV
Same as VTR_4P0_F
+ 25 mV
Same as VTR_4P1_F
+ 25 mV
Same as VTR_4P2_F
+ 25 mV
Same as VTR_4P3_F
+ 25 mV
Same as VTR_4P4_F
+ 25 mV
Same as VTR_4P5_F
+ 25 mV
Same as VTR_4P6_F
+ 25 mV
Same as VTR_4P7_F
+ 25 mV
Same as VTR_4P8_F
+ 25 mV
Same as VTR_4P9_F
+ 25 mV
Same as VTR_5P0_F
+ 25 mV
Same as VTR_5P1_F
+ 25 mV
Same as VTR_5P2_F
+ 25 mV
Same as VTR_5P3_F
+ 25 mV
SID557 VTR_3P9_R
SID558 VTR_4P0_R
SID559 VTR_4P1_R
SID560 VTR_4P2_R
SID561 VTR_4P3_R
SID562 VTR_4P4_R
SID563 VTR_4P5_R
SID564 VTR_4P6_R
SID565 VTR_4P7_R
SID566 VTR_4P8_R
SID567 VTR_4P9_R
SID568 VTR_5P0_R
SID569 VTR_5P1_R
SID570 VTR_5P2_R
SID571 VTR_5P3_R
SID573 LVD_RR_A
SID574 LVD_RR_DS
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
mV/µ
Power ramp rate: VDDD (Active)
–
–
100
s
Power ramp rate: VDDD
(DeepSleep)
mV/µ
–
10
s
Active mode delay between VDDD
falling/rising through LVD
Guaranteed by
design
SID575 tDLY_ACT_LVD
SID575A tDLY_DS_LVD
SID576 tRES_LVD
–
–
–
–
–
1
4
–
µs
µs
ns
rising/falling point and an
internal LVD signal transitioning
DeepSleep mode delay between
VDDD falling/rising through LVD
rising/falling point and an
Guaranteed by
design
internal LVD signal transitioning
Response time of LVD, VDDD
supply. (For falling-then-rising
supply at max ramp rate;
Guaranteed by
design
100
threshold is LVD falling point)
Datasheet
146
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-15 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
High-voltage OVD specifications
HV OVD 5.0-V rising detection
point for VDDD and VDDA
HV OVD 5.0-V falling detection
point for VDDD and VDDA
SID580 VTR_5P0_R
SID581 VTR_5P0_F
SID582 VTR_5P5_R
SID583 VTR_5P5_F
SID585 HVOVD_RR_A
SID586 HVOVD_RR_DS
5.049 5.205 5.361
V
V
V
V
5.025
5.548
5.18 5.335
5.72 5.892
HV OVD 5.5-V rising detection
point for VDDD and VDDA (default)
HV OVD 5.5-V falling detection
point for VDDD and VDDA (default)
Power ramp rate: VDDD and VDDA
(Active)
Power ramp rate: VDDD and VDDA
(DeepSleep)
5.524 5.695 5.866
mV/µ
s
mV/µ
s
–
–
–
–
100
10
Active mode delay between VDDD
falling/rising through VTR_5P0_F/R
or VTR_5P5_F/R and an internal HV
OVD signal transitioning
Active mode delay between VDDA
falling/rising through VTR_5P0_F/R
or VTR_5P5_F/R and an internal HV
OVD signal transitioning
Guaranteed by
design
SID587 tDLY_ACT_HVOVD
–
–
–
–
1
µs
µs
Guaranteed by
design
SID587A tDLY_ACT_HVOVD_A
1.5
DeepSleep mode delay between
VDDD/VDDA falling/rising through
Guaranteed by
design
SID587B tDLY_DS_HVOVD
VTR_5P0_F/R or VTR_5P5_F/R and an
–
–
4
µs
ns
internal HV OVD signal transi-
tioning
Response time of HV OVD (for
rising-then-falling supply at max
ramp rate; threshold is VTR_5P0_R
Guaranteed by
design
SID588 tRES_HVOVD
100
–
–
or VTR_5P5_R
)
Low-voltage OVD specifications
LV OVD rising detection point for
VCCD
LV OVD falling detection point for
VCCD
SID590 VTR_R_LVOVD
SID591 VTR_F_LVOVD
1.261
1.3
1.339
V
V
1.237 1.275 1.313
Active mode delay between VCCD
falling/rising through VTR_F/R_LVOVD
and an internal LV OVD signal
transitioning
Guaranteed by
design
SID595 tDLY_ACT_LVOVD
SID595A tDLY_DS_LVOVD
SID596 tRES_LVOVD
–
–
–
–
–
1
12
–
µs
µs
ns
DeepSleep mode delay between
V
CCD falling/rising through
Guaranteed by
design
VTR_F/R_LVOVD and an internal LV OVD
signal transitioning
Response time of LV OVD. (For
rising-then-falling supply at max
ramp rate; threshold is
Guaranteed by
design
100
VTR_R_LVOVD
)
Datasheet
147
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-15 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
Overcurrent detection (OCD) specifications
Overcurrent detection range for
Guaranteed by
design
SID598A IOCD_LDO
SID598B IOCD_EXT
SID599 IOCD_DPSLP
312
675
18
–
–
–
630
825
72
mA
mA
mA
internal Active regulator
Overcurrent detection range for
external transistor mode
Overcurrent detection range for
internal DeepSleep regulator
Figure 26-14 Device operations supply range
Datasheet
148
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
2.3 V
VDDD
tDLY_POR
Internal reset by POR
VDDD
tPOFF
1.45 V
Figure 26-15 POR specifications
VDDD, VDDA
VTR_2P7_R or VTR_3P0_R
VTR_2P7_F or VTR_3P0_F
Internal HV BOD signal
tDLY_ACT/DS_HVBOD
tDLY_ACT/DS_HVBOD
VDDD, VDDA
tRES_HVBOD
VTR_2P7_F or VTR_3P0_F
Figure 26-16 High-voltage BOD specifications
Datasheet
149
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VCCD
VTR_R_LVBOD
VTR_F_LVBOD
Internal LV BOD signal
tDLY_ACT/DS_LVBOD
tDLY_ACT/DS_LVBOD
VCCD
tRES_LVBOD
VTR_F_LVBOD
Figure 26-17 Low-voltage BOD specifications
VTR_5P0_R or VTR_5P5_R
VTR_5P0_F or VTR_5P5_F
VDDD/VDDA
Internal HV OVD signal
tDLY_ACT/DS_HVOVD
tDLY_ACT/DS_HVOVD
VTR_5P0_R or VTR_5P5_R
tRES_HVOVD
VDDD/VDDA
Figure 26-18 High-voltage OVD specifications
Datasheet
150
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VTR_R_LVOVD
VTR_F_LVOVD
VCCD
Internal LV OVD signal
tDLY_ACT/DS_LVOVD
tDLY_ACT/DS_LVOVD
VTR_R_LVOVD
tRES_LVOVD
VCCD
Figure 26-19 Low-voltage OVD specifications
VDDD
LVD rising detection point
LVD falling detection point
Internal LVD signal
tDLY_ACT/DS_LVD
tDLY_ACT/DS_LVD
VDDD
tRES_LVD
LVD falling detection point
Figure 26-20 LVD specifications
Datasheet
151
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.10.1
SWD interface
Table 26-16 SWD interface specifications
Spec ID
SID300
Parameter
fSWDCLK
Description
SWD clock input frequency
Min
–
Typ
–
Max Units Details/Conditions
10
MHz 2.7 V ≤ VDDD ≤ 5.5 V
0.25 ×
T
0.25 ×
T
SID301
SID302
tSWDI_SETUP
SWDI setup time
SWDI hold time
–
–
–
ns T = 1 / fSWDCLK
tSWDI_HOLD
tSWDO_VALID
tSWDO_HOLD
–
ns T = 1 / fSWDCLK
SID303
SID304
SWDO valid time
SWDO hold time
–
1
–
–
0.5 × T
–
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
Table 26-17 JTAG AC specifications
Spec ID
SID620
SID621
SID622
SID623
SID624
SID625
SID626
SID627
Parameter
tJCKH
tJCKL
tJCP
tJSU
tJH
tJZX
tJXZ
tJCO
Description
TCK HIGH time
TCK LOW time
Min
30
30
66.7
12
12
–
Typ
–
–
–
–
–
–
–
–
Max Units Details/Conditions
–
–
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
TCK clock period
–
–
–
TDI/TMS setup time
TDI/TMS hold time
TDO High-Z to active
TDO active to High-Z
TDO clock to output
30
30
30
–
–
tJCKH
tJCKL
tJCP
TCK
tJH
tJSU
TDI/TMS
TDO
tJCO
tJXZ
tJZX
Figure 26-21 JTAG specifications
Table 26-18 Trace specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
SID1412A CTRACE
Trace Capacitive Load
–
–
30
pF
Trace clock cycle time
for 25 MHz
SID1412 tTRACE_CYC
Trace clock period
40
–
–
ns
SID1413 tTRACE_CLKL
SID1414 tTRACE_CLKH
SID1415A tTRACE_SETUP
SID1416A tTRACE_HOLD
Trace clock LOW pulse width
Trace clock HIGH pulse width
Trace data setup time
2
2
3
2
–
–
–
–
–
–
–
–
ns Clock low pulse width
ns Clock high pulse width
ns Trace data setup time
ns Trace data hold time
Trace data hold time
Datasheet
152
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.11
Clock specifications
Table 26-19 Root and intermediate clocks[63]
Max frequency
Clock
Source
Description
(MHz)
200
CLK_HF0
CLK_HF1
CLK_HF2
PLL200#0 Root clock for CPUSS, PERI
350
100
PLL400#0 CM7 CPU Core#0, CM7 CPU Core#1 clock
PLL200#1 Peripheral clock root other than CLK_PERI
Event generator (CLK_REF), clock output on EXT_CLK pins (when
CLK_HF3
CLK_HF4
CLK_HF5
100
125
PLL200#0
used as output)
PLL400#1 Ethernet Channel#0, Ethernet Channel#1 internal clock
I2S channel#0, I2S channel#1, I2S channel#2 interface clock,
196.608
PLL400#1
Ethernet Channel#0 TSU, Ethernet Channel#1 TSU
CLK_HF6
CLK_HF7
200
8
PLL200#0 Root clock for SDHC, SMIF interface clock
ILO
CSV
CLK_FAST_
350
350
200
100
100
NA
CM7 CPU Core#0, intermediate clock
0
CLK_FAST_
1
NA
NA
NA
NA
CM7 CPU Core#1, intermediate clock
Generated by clock gating CLK_HF0, intermediate clock for SMIF,
Flash, Ethernet
CLK_MEM
CLK_SLOW
CLK_PERI
Generated by clock gating CLK_MEM, intermediate clock for CM0+,
P-DMA, M-DMA, Crypto, SMIF, SDHC
Generated by clock gating CLK_HF0, intermediate clock for IOSS,
TCPWM0, CPU trace, SMIF
Table 26-20 Relation between CLK_HF0 and CLK_SLOW (Example)[64]
CLK_HF0 (MHz)
CLK_SLOW (MHz)
200
180
160
120
100
80
100
90
80
60
100
80
Table 26-21 IMO AC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID310
f
IMO operating frequency
7.68
8
8.32
MHz
IMOTOL
Start-up time to 90% of
final frequency
SID311
SID312
t
IMO start-up time
IMO current
–
–
–
7.5
22
µs
STARTIMO
I
13.5
µA
IMO_ACT
Table 26-22 ILO AC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID320
f
ILO operating frequency
30.47424 32.768 35.06176 kHz
ILOTRIM
Start-up time to 90% of
final frequency
SID321
SID323
t
ILO start-up time
ILO current
–
8
12
µs
STARTILO
IILO
–
500
2800
nA
Notes
63.Intermediate clocks that are not listed have the same limitations as that of their parent clock.
64.CLOCK_SLOW and CLK_HF0 are related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on).
Datasheet
153
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VDDD
MCU
ITrim
Rf
RTrim
ECO_IN: External crystal oscillator input pin
ECO_OUT: External crystal oscillator output pin
C1, C2: Load Capacitors
ECO_IN
VSSD
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
C4*
GTrim
VSSD
ECO_OUT
Rd
0R
Rd
FTrim
Figure 26-22 ECO connection scheme[66]
Table 26-23 ECO specifications
Spec ID Parameter
Description
Crystal frequency range
Min Typ Max Units Details/Conditions
SID330
SID332
fECO
RFDBK
8
100
–
–
33.34 MHz
Feedback resistor value.
400
2000
10
kΩ Guaranteed by design
Min: RTRIM = 3; Max: RTRIM = 0
with 100-kΩ step size on
RTRIM
Maximum operation
µA current with a 33-MHz
crystal, 18-pF load
SID333
SID334
IECO3
ECO current at TJ = 150 °C
–
–
–
–
Time from set
CLK_ECO_-CONFIG.EC
O_EN to 1 until-
tSTART_8M
8-MHz ECO start-up time[65]
ms CLK_ECO_STATUS.EC
O_READY is set to 1.
(See Clock Timing
Diagrams)
Time from set
CLK_ECO_-CONFIG.EC
O_EN to 1 until-
SID335
tSTART_33M
33-MHz ECO start-up time[65]
–
–
1
ms CLK_ECO_STATUS.EC
O_READY is set to 1.
(See Clock timing
diagrams)
Notes
65.Mainly depends on the external crystal.
66.Refer to the family-specific Architecture TRM for more information on crystal requirements (32-bit Arm Cortex -M7 Industrial Micro-
controller XMC7000 family).
Datasheet
154
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-24 PLL specifications
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
PLL (without SSCG and fractional divider) Specifications for 200 MHz
Time from stable reference
clock until PLL frequency is
within 0.1% of final value
and lock indicator is set
SID340
SID341
tPLL200_LOCK
Time to achieve PLL lock
–
–
–
35
µs
Output frequency from
PLL block
fPLL_OUT
11
200 MHz
For 125 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID342
SID343
SID344
PLL_LJIT1
PLL_LJIT2
PLL_LJIT3
Long term jitter
Long term jitter
Long term jitter
–0.25
–0.5
–
–
–
0.25
0.5
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 500 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 1000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
–0.5
0.5
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 10000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID345A1 PLL_LJIT5
Long term jitter
–0.75
–
–
0.75
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
SID346
SID347
fPLL_IN
PLL input frequency
PLL operating current
(fOUT = 200 MHz)
3.988
–
33.34 MHz
IPLL_200M
0.87 1.85 mA fOUT = 200 MHz
SID348C fPLL_VCO
SID349C fPLL_PFD
VCO frequency
PFD frequency
170
3.988
–
–
400 MHz
8
MHz
PLL (with SSCG and fractional divider) specifications for 400 MHz
Time from stable reference
clock until PLL frequency is
within 0.1% of final value
and lock indicator is set
SID340A tPLL400_LOCK
Time to achieve PLL lock
–
–
50
µs
Programmed output
frequency from PLL
Block (spreading off)
Programmed output
frequency from PLL
Block (spreading on)
SID341A fOUT
SID341B fOUT
25
25
–
–
350 MHz Spreading off
340 MHz Spreading on
Datasheet
155
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-24 PLL specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
For 125 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
SID342D1
Long term jitter
–0.25
–
0.25
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
PLL400_LJIT1
fOUT: 100 MHz to 350 MHz
Spread spectrum
modulation depth
Spread spectrum
modulation rate
SID343A
SID343B
For 500 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
SID343D1 PLL400_LJIT2 Long term jitter
SID344D1 PLL400_LJIT3 Long term jitter
SID345E1 PLL400_LJIT5 Long term jitter
–0.5
–1
–
–
–
0.5
1
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 1000 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 10000 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
–1.5
1.5
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
SID345A fVCO
SID346A fIN
VCO frequency
PLL input frequency
400
3.988
–
–
800 MHz
33.34 MHz
PLL operating current
(fOUT = 400 MHz)
PFD Frequency (fIN /
Reference divider)
PFD Frequency (fIN /
Reference divider)
SID347A IPLL_400M
SID348A fPFD_S
SID349A fPFD_F
–
3.988
8
1.4
–
2.2
20
20
mA fOUT = 400 MHz
MHz Spreading off/on
–
MHz Fractional operation
fPFD = 8 MHz,
fVCO = 400 MHz,
Output frequency from
PLL Block (spreading on)
fOUT = 100MHz, Modulation
SID341C fOUT_400_8S1
93
–
–
105 MHz
frequency:
fPFD / 512,
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100MHz, Modulation
frequency:
tPLL_C-
JIT400_8S1
Cycle to cycle jitter
(spreading on)
SID342C
–710
710
ps
fPFD / 512,
Modulation depth: 3%
Datasheet
156
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-24 PLL specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
fPFD = 8 MHz,
fVCO = 400 MHz,
Output frequency from
PLL Block (spreading on)
fOUT = 100MHz, Modulation
frequency:
SID341D fOUT_400_8S2
93
–
–
105 MHz
fPFD / 256,
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100MHz, Modulation
frequency:
tPLL_C-
JIT400_8S2
Cycle to cycle jitter
(spreading on)
SID342D
–710
710
ps
fPFD / 256,
Modulation depth: 3%
Table 26-25 FLL specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
Wakeup with < 10 °C
temperature change
while in DeepSleep.
fFLL_IN = 8 MHz,
SID350
tFLL_WAKE
FLL wake up time
–
–
5
µs
fFLL_OUT = 100 MHz, Time
from stable reference
clock until FLL frequency
is within 5% of final value
Output frequency from
FLL block
Output range of FLL
divided-by-2 output
SID351
fFLL_OUT
24
–
100
MHz
This is added to the error
of the source
SID352
SID353
FLL_CJIT
fFLL_IN
FLL frequency accuracy
Input frequency
–1
–
–
1
%
0.25
80
MHz
Reference clock: IMO,
CCO frequency: 200 MHz,
FLL frequency: 100 MHz,
guaranteed by design
SID354
IFLL
FLL operating current
–
250
360
µA
Datasheet
157
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-26 WCO specifications
Spec ID
SID360
SID361
Parameter
fWCO
WCO_DC
Description
Crystal frequency
Min
Typ
Max Units Details/Conditions
Maximum drive level:
–
32.768
–
kHz
0.5 µW
WCO duty cycle
WCO start-up time[67]
10
–
–
–
90
%
SID362E tSTART_WCOE
1400
ms
For Grade-E devices,
time from set
CTL.WCO_EN to 1
untiSTATUS.WCO_OK
is set to 1. (See Clock
timing diagrams)
SID363
IWCO
WCO current
–
1.4
–
µA
VDDD
MCU
Rf
WCO_IN: Watch crystal oscillator input pin
WCO_OUT: Watch crystal oscillator output pin
C1, C2: Load Capacitors
WCO_IN
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
C4*
VSSD
VSSD
WCO_OUT
Rd
0R
Figure 26-23 WCO connection scheme[68]
Note
67.Mainly depends on the external crystal.
68.Refer to the family-specific Architecture TRM for more information on crystal requirements (32-bit Arm Cortex -M7 Industrial Micro-
controller XMC7000 family).
Datasheet
158
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-27 External clock input specifications
Spec ID Parameter
Description
Min
0.25
45
Typ Max Units Details/Conditions
For EXT_CLK pin (all
input level settings:
External clock input
frequency
SID366
SID367
fEXT
–
–
80
55
MHz
%
CMOS, TTL, Indus-
trial)
EXT_DC
External clock duty cycle
Table 26-28 MCWDT timeout specifications
Spec ID
Parameter
Description
Min Typ Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID410
tMCWDT1
Minimum MCWDT timeout
57
–
–
–
–
µs
s
16-bit MCWDT counter
Guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
16-bit MCWDT counter
Guaranteed by design
SID411
tMCWDT2
Maximum MCWDT timeout
2.15
Table 26-29 WDT timeout specifications
Spec ID
Parameter
Description
Min Typ
Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID412
tWDT1
Minimum WDT timeout
57
–
–
–
–
µs
h
16-bit WDT counter,
guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
16-bit WDT counter,
guaranteed by design
SID413
SID414
tWDT2
Maximum WDT timeout
Default WDT timeout
39.15
When using the ILO
and 32-bit WDT
tWDT3
–
1000
–
ms counter at 0x8000
(default value).
Guaranteed by design.
Datasheet
159
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.12
Clock timing diagrams
ECO: 8 MHz
PLL: 160 MHz
FLL: 100 MHz
Active
CLK_ECO_CONFIG.ECO_EN
ECO_OUT
8 MHz
CLK_ECO_STATUS.ECO_READY
10 ms
CLK_PLL_CONFIG.ENABLE
CLK_PLL_STATUS.LOCKED
160 MHz
35 µs
PLL_OUTPUT
CLK_FLL_CONFIG.FLL_ENABLE
CCO is already up-and-running
CLK_FLL_STATUS.LOCKED
5 µs
100 MHz
FLL_OUTPUT
Figure 26-24 ECO to PLL or FLL diagram
Datasheet
160
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
WCO: 32.768 kHz
FLL: 100 MHz
Active
CTL.WCO_EN
WCO_OUT
32.768 kHz
STATUS.WCO_OK
1000 ms
CLK_FLL_CONFIG.FLL_ENABLE
CLK_FLL_STATUS.LOCKED
CCO is already up-and-running
5 µs
100 MHz
FLL_OUTPUT
Figure 26-25 WCO to FLL diagram
Datasheet
161
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.13
Ethernet specifications
Table 26-30 Ethernet specifications
Spec ID Parameter
Description
Min
Typ Max Units Details/Conditions
Ethernet general specifications
Guaranteed by
SID368
fSYS
System clock max frequency
AXI clock max frequency
–
–
–
100
MHz
design
Guaranteed by
design
For VDDD or VDDIO_4
SID369
SID370
fAXI
–
–
200
3.6
MHz
V
VETH
Ethernet MAC IO supply voltage 3.0
For MDIO all signals
between MAC and
PHY using GPIO_STD
and HSIO_STD
20% to 80%, for GMII
using HSIO_STD
SID364A CL_MD
SID365B tRF_G
SID365A tRF
Load capacitance
–
–
–
–
–
–
25
1
pF
ns
ns
Rise / fall time (for input and
output pins)
20% to 80%, for MII,
RMII, andMDIOusing
GPIO_STD and
Rise / fall time (for input pins)
2
HSIO_STD
Ethernet MII specifications for GPIO_STD
MII TX/RX_CLK Clock frequency
at 100 Mbps
SID375
SDI376
fTXRX_CLK
–100
35
25
–
100
65
MHz
%
DUTY_TX-
RX_CLK
TX/RX_CLK duty
MII Transmit data
(TXD,TX_CTL,TX_ER) valid after
TX_CLK
SID372
tSKEWT
0.5
–
25
ns
MII Receive data setup to
RX_CLK rising edge
MII Receive data hold to
RX_CLK rising edge
SID373
SID374
tSUR
10
10
–
–
–
–
ns
ns
tHOLDR
Ethernet RMII specifications for GPIO_STD
SID375A fREF_CLK
RMII reference Clock frequency –50
50
–
50
65
MHz External clock
%
Duty cycle of reference clock
SID376A DUTY_REF_C
LK
35
(input)
RXD[1:0], RX_CTL, RX_ER Data
SID377
SID378
tSU
4
–
–
–
–
ns
ns
Setup to REF_CLK rising edge
RXD[1:0], RX_CTL, RX_ER, Data
tHOLD
2
hold from REF_CLK rising edge
TX_EN,TXD[1:0], Data output
SID393
tTXOUT
delay from REF_CLK rising
edge
2
2
–
14
14
ns For GPIO_ST
ns For HSIO_STD
Data output delay from
REF_CLK rising edge
SID393A TX_CTL,TXD[1:0]
Ethernet GMII Specifications for HSIO_STD
SID379
fP_REFCLK
REF_CLK clock frequency
RX_CLK clock frequency
RX_CLK clock period
–
–
125
125
–
–
MHz
MHz
ns
50pp
m
8.5
SID380
fP_RXCLK
50ppm
SID380A tP_RXCLK
7.5
Datasheet
162
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-30 Ethernet specifications (continued)
Spec ID Parameter
SID380B tP_HL_RXCLK RX_CLK clock time HIGH/LOW
Description
Min
2.5
–
Typ Max Units Details/Conditions
–
–
ns
TX(GTX)_CLK frequency
100p
pm
SID389
fP_TXCLK
100pp 125
m
MHz
(External/Internal mode)
TX(GTX)_CLK clock period
(External/Internal mode)
TX(GTX)_CLK clock time
HIGH/LOW (External/Internal
mode)
SID389A tP_TXCLK
7.5
–
8.5
–
ns
ns
SID389B tP_HL_TXCLK
2.5
–
TX_CTL, TXD, TX_ER Setup to
TX(GTX)_CLK rising edge
TX_CTL, TXD, TX_ER hold from
TX(GTX)_CLK rising edge
RX_CTL, RXD, RX_ER setup to
RX_CLK rising edge
RX_CTL, RXD, RX_ER hold from
RX_CLK rising edge
SID381
SID382
SID383
SID384
tSETUPT
tHOLDT
tSETUPR
tHOLDR
2.5
0.5
2
–
–
–
–
–
–
–
–
ns
ns
ns
ns
0
Ethernet RGMII specifications for HSIO_STD
SID385
SID386
SID387
SID388
fCYC
REF_CLK clock frequency
Duty cycle for gigabit
Data to clock output skew
Data to clock input skew
–
45
–0.5
1
125
–
–
–
MHz
%
ns
DUTY_G
tSKEWT
tSKEWR
55
0.5
2.6
–
ns
Ethernet MDIO specifications for GPIO_STD/HSIO_STD
SID395
tMDCYC
MDC clock cycle
MDIO input setup time to MDC
rising edge
400
100
–
–
–
–
ns
ns
SID396
tMDIS
MDIO input hold time to MDC
rising edge
MDIO output skew from MDC
rising edge
SID397
SID398
tMDIH
tMDIO
0
–
–
–
ns
ns
10
390
Datasheet
163
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
1
VIH
RX_CLK
VIL
2
3
RXD, RX_CTL,
RX_ER
VIH
VIL
VIH
VIL
TX_CLK
4
VOH
VOL
TXD, TX_CTL,
TX_ER
1: RX_CLK or TX_CLK cycle = 1/fTXRX_CLK
2: MII receive data setup time to RX_CLK rising edge = tSUR
3: MII receive data hold time to RX_CLK rising edge = tHOLDR
4: MII transmit data valid after TX_CLK rising edge = tSKEWT
Figure 26-26 MII timing diagram
1
VOH
MDC
VOL
2
3
MDIO
VIH
VIL
VOH
VOL
MDC
4
VOH
VOL
MDIO
1: MDC clock cycle = tMDCCYC
2: MDIO input setup time to MDC rising edge = tMDIS
3: MDIO input hold time tp MDC rising edge = tMDIH
4: MDIO output skew from MDC rising edge = tMDIO
Figure 26-27 MDIO timing diagram
Datasheet
164
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
1
VOH
REF_CLK
VOL
2
3
RXD, RX_CTL,
RX_ER
VIH
VIL
4
VOH
VOL
TXD, TX_CTL
1: RMII reference clock cycle = 1/fREF_CLK
2: Data setup to REF_CLK rising edge = tSU
3: Data hold from REF_CLK rising edge = tHOLD
4: Data output delay from REF_CLK_rising edge = tTXOUT
Figure 26-28 RMII timing diagram
1
100 %
RX_CLK,
TX_CLK
50 %
0 %
TX_CTL,
RX_CTL, TXD,
RXD
100 %
50 %
0 %
2
2
2
2
1: TX_CLK and RX_CLK clock cycle = 1/fCYC
2: Data to clock output skew = tSKEWT
Figure 26-29 RGMII Tx timing diagram
1
100 %
RX_CLK,
TX_CLK
50 %
0 %
TX_CTL,
RX_CTL, TXD,
RXD
100 %
50 %
0 %
2
2
1: TX_CLK and RX_CLK clock cycle = 1/fCYC
2: Data to clock input skew = tSKEWR
Figure 26-30 RGMII Rx timing diagram
Datasheet
165
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.14
SDHC specifications
Table 26-31 SDHC specifications
Spec ID Parameter
Description
Min Typ Max Units Details/Conditions
SDHC and eMMC Specifications (The source clock must be divided by 2 or more in DDR modes)
SID801
SID802
SID803
VSDHC
IODS
tIT
SDHC IO supply voltage
2.7
–
–
–
3.6
V
For VDDIO_1 or VDDIO_3
drive_sel<1:0>= 0b00
for all modes
I/O drive select
8
8
mA
ns
Input transition time
0.7
3
SD: DS timing specifications for GPIO_STD/HSIO_STD
SID810
SID812
SID813
fLP
CD
CC
Interface clock period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
–
40
40
–
–
–
25
40
40
MHz 40-ns period
pF
pF
Output setup time of CMD/DAT
prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID814
SID815
SID816
SID818
tOS
5.5
5.5
24
0
–
–
–
–
–
–
–
–
ns
ns
tOH
tIS_LP
tIH
Clock period - Output
delay
ns
ns
SD: HS timing specifications for HSIO_STD
SID820
SID822
SID823
fLP_SD_HS
CD_SD_HS
CC_SD_HS
Interface clock period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
–
40
40
–
–
–
50
40
40
MHz 20-ns period
pF
pF
Output setup time of CMD/DAT
prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID824
SID825
SID826
SID828
tOS_SD_HS
tOH_SD_HS
tIS_LP_SD_HS
tIH_SD_HS
6.5
2.5
4
–
–
–
–
–
–
–
–
ns
ns
Clock period less
output delay
ns
ns
2.5
eMMC: BWC timing specifications for GPIO_STD/HSIO_STD
fLP_eM-
MC_BWC
CD_eM-
MC_BWC
CC_eM-
MC_BWC
tOS_eM-
MC_BWC
tOH_eM-
MC_BWC
tIS_LP_eM-
MC_BWC
tIH_eM-
SID870
SID872
SID873
SID874
SID875
SID876
SID878
Interface clock period
–
–
–
–
–
–
–
–
26
30
30
–
MHz 38.4-ns period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
30
pF
pF
ns
ns
30
Output setup time of CMD/DAT
prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
3.5
3.5
9.7
8.3
–
Clock period less
–
ns
output delay
–
ns
MC_BWC
Datasheet
166
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-31 SDHC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units Details/Conditions
eMMC: SDR timing specifications for HSIO_STD
SID880
SID882
SID883
fLP_eMMC_SDR Interface clock period
CD_eMMC_SDR I/O loading at DATA/CMD pins
CC_eMMC_SDR I/O loading at CLK pins
–
30
30
–
–
–
52
30
30
MHz 19.2-ns period
pF
pF
tOS_eM-
MC_SDR
tOH_eM-
MC_SDR
tIS_LP_eM-
MC_SDR
Output setup time of CMD/DAT
prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID884
SID885
SID886
SID888
3.5
3.5
3.5
2.5
–
–
–
–
–
–
–
–
ns
ns
Clock period less
ns
output delay
tIH_eMMC_SDR
ns
eMMC: DDR timing specifications for HSIO_STD
fLP_eM-
MC_DDR
SID890
Interface clock period
–
–
–
52
55
MHz 19.2-ns period
%
DUTY_-
SID892
CLK_eM-
Duty cycle of output CLK
45
MC_DDR
SID893
SID894
CD_eMMC_DDR I/O loading at DATA/CMD pins
CC_eMMC_DDR I/O loading at CLK pins
20
20
–
–
20
20
pF
pF
tOS_eM-
MC_DDR
tOH_eM-
MC_DDR
tIS_LP_eM-
MC_DDR
Output setup time of CMD/DAT
prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID895
SID896
SID897
SID899
2.6
2.6
2.4
1.5
–
–
–
–
–
–
–
–
ns
ns
Clock period less
ns
output delay
tIH_eMMC_DDR
ns
Datasheet
167
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.15
Audio subsystem specifications
Table 26-32 Audio subsystem specifications
Details/
Spec ID Parameter
SID770 fAUDIO
Description
Min
–
Typ
–
Max
200
3.6
Units
MHz
V
Conditions
Audio subsystem
frequency
Audio Sub System I/O
supply voltage
Guaranteed by
design
SID772 VAUDIO
3.0
–
For VDDIO_2
drive_sel<1:0>=
0b0X, Pull-up,
pull-down: off
drive_sel<1:0>=
0b0X, Pull-up,
pull-down: off
SID773 VOL_A
SID774 VOH_A
Output Voltage LOW level
Output Voltage HIGH level
–
–
–
0.4
–
V
V
VDDIO_2 – 0.5
Input Voltage HIGH
SID775 VIH_CMOS_A
SID776 VIL_CMOS_A
0.7 × VDDIO_2
–
–
–
–
V
V
threshold in CMOS mode
Input Voltage LOW
threshold in CMOS mode
0.3 × VDDIO_2
I2S/TDM word clock frequency
Guaranteed by
design
Guaranteed by
design
Guaranteed by
design
SID796 fWS_I2S
SID797 fWS_TDM
WS Clock Rate in I2S mode
8
–
8
–
–
–
192
96
kHz
kHz
bit
WS Clock Rate in TDM
mode
SID798 Word
Length of I2S Word
32
I2S/TDM master mode
Except TDM 96 kHz
mode, TX/RX_WS
output and
TX/RX_SCK output
withdrive_sel<1:0>
= 0b 01,
guaranteed by
design
Delay Time of TX/RX_WS
Output Transition from
Falling Edge of TX/RX_SCK
Output
SID740 tD_WS
–8
–
9
ns
TDM 96 kHz mode,
TX/RX_WS output
withdrive_sel<1:0>
= 0b01 and
Delay Time of TX/RX_WS
output Transition from
Falling Edge of TX/RX_SCK
output
SID740A tD_WS_TDM96A
–8
–8
–
–
11
ns TX/RX_SCK output
withdrive_sel<1:0>
= 0b00,
guaranteed by
design
TX_SDO and
TX_SCK output
withdrive_sel<1:0>
ns = 0b01 for except
TDM 96 kHz mode,
guaranteed by
Delay Time of TX_SDO
Transition from Falling
Edge of TX_SCK Output
SID741 tD_SDO
8
design
Datasheet
168
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-32 Audio subsystem specifications (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
TX_SDO with
drive_sel<1:0> =
0b01 and TX_SCK
output with
Delay Time of TX_SDO
SID741A tD_SDO_TDM96 Transition from Falling
Edge of TX_SCK Output
–8
–
8
ns drive_sel<1:0> =
0b00 for TDM
96 kHz mode,
guaranteed by
design
RX_SDI Setup Time to the
Following Rising Edge of
RX_SCK output
withdrive_sel<1:0>
SID742 tS_SDI
SID743 tH_SDI
SID744 tS_SDI1
SID745 tH_SDI1
RX_SCK Output
11
–
–
–
–
–
–
–
ns
= 0b00, guaranteed
by design
(RX_CTL.B_CLOCK_INV =
0)
RX_SDI Hold Time to the
Rising Edge of RX_SCK
Output
(RX_CTL.B_CLOCK_INV =
0)
RX_SDI Setup Time to the
Following Falling Edge of
RX_SCK Output
(RX_CTL.B_CLOCK_INV =
1)
RX_SDI Hold Time to the
Falling Edge of RX_SCK
Output
(RX_CTL.B_CLOCK_INV =
1)
RX_SCK output
withdrive_sel<1:0>
ns = 0b00,
tMCLK_SOC – 0.9
guaranteed by
design
RX_SCK output
withdrive_sel<1:0>
ns = 0b00,
11
guaranteed by
design
RX_SCK output
withdrive_sel<1:0>
tMCLK_SOC – 0.9
–
ns
= 0b00, guaranteed
by design
TX/RX_SCK Output Bit
Clock Duty Cycle
Guaranteed by
SID746 tSCKCY
45
–
–
55
%
design
Internal Fractional
196.608 MHz PLL, guaranteed by
design
MCLK input clock
frequency
SID748 fMCLK_SOC
1.024
MCLK input clock
frequency
SID748A fMCLK_SOC_E
SID749 tMCLK_SOC
SID750 tJITTER
1.024
5.086
–200
–
–
–
98.304
976.563
200
MHz External clock
Guaranteed by
design
MCLK input clock period
ns
MCLK Input clock jitter
tolerance
Guaranteed by
design
ps
MCLK output with
drive_sel<1:0> =
MHz 0b00
MCLK output clock
frequency
SID748B fMCLK
1.024
1.024
–
–
25
15
Guaranteed by
design
MCLK output with
drive_sel<1:0> =
MHz 0b01
MCLK output clock
frequency
SID748C fMCLK1
Guaranteed by
design
Datasheet
169
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-32 Audio subsystem specifications (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
Guaranteed by
design
SID749B fMCLK_DT
MCLK output clock duty
45
–
55
%
I2S/TDM slave mode
TX/RX_WSInputAlignment
Clock Setup Time to the
following Rising Edge of
TX/RX_SCK Input
TX/RX_WSInputAlignment
Clock Hold Time to the
Rising Edge of TX/RX_SCK
Input
Delay Time of TX_SDO
Transition from Falling
Edge of TX_SCK Input
(TX_CTL.B_CLOCK_INV = 0)
Guaranteed by
design
SID751 tS_WS
SID752 tH_WS
SID753 tD_SDO
5
–
–
–
–
ns
ns
ns
Guaranteed by
design
tMCLK_SOC + 5.0
–
TX_SDO with
drive_sel<1:0>=
0b00, guaranteed
by design
tMCLK_SOC + 15
–tMCLK_SOC + 5.0
Delay Time of TX_SDO
Transition from Rising
Edge of TX_SCK Input
(TX_CTL.B_CLOCK_INV = 1)
RX_SDI Setup Time to the
Following Rising Edge of
RX_SCK Input
TX_SDO with
drive_sel<1:0>=
0b00, guaranteed
by design
SID754 tD_SDO1
SID755 tS_SDI
tMCLK_SOC + 15
–tMCLK_SOC + 5.0
–
–
ns
ns
Guaranteed by
design
5
–
RX_SDI Hold Time to the
Rising Edge of RX_SCK
Input
TX/RX_SCK Input Bit Clock
Duty Cycle
Guaranteed by
design
SID756 tH_SDI
SID757 tSCKCY
tMCLK_SOC + 5.0
–
–
–
ns
%
Guaranteed by
design
45
55
Datasheet
170
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.16
Serial memory interface specifications
Table 26-33 SMIF specifications
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
SMIF DC specification
For VDDIO_1 or
VDDIO_3
SID785 VSMIF
SMIF I/O supply voltage
2.7
–
3.6
V
SMIF HSSPI(SDR) specification for HSIO_STD
SID760
CL_SDR_HSIO
SR_SDR_HSIO
fCK_SDR_HSIO
tCK_SDR_HSIO
DCK_SDR_HSIO Clock duty
CSR_SDR_HSIO Clock rise and fall slew rates
tCS_SDR_HSIO
Load capacitance
–
1.5
-
–
–
30
–
pF
Guaranteed by
design
SID761
Input rise and fall slew rates
V/ns
SID762
SID763
SID764
SID765
SID766
Clock frequency
Clock period
–
–
–
–
–
100
–
55
–
MHz
ns
%
V/ns
ns
1 / f
CK_SDR_HSIO
45
1.5
10
Chip select HIGH time
–
Chip select active setup
time
SID767
tCSS_SDR_HSIO
3
–
–
ns
SID768
SID769
SID780
SID781
SID782
tCSH_SDR_HSIO
tSU_SDR_HSIO
tHD_SDR_HSIO
tV_SDR_HSIO
Chip select active hold time
Data setup time
Data hold time
Clock LOW output valid
Input hold time
5
1.5
2
1.5
2
–
–
–
–
–
–
–
–
7.65
–
ns
ns
ns
ns
ns
tHO_SDR_HSIO
Guaranteed by
design
Guaranteed by
design
SID783
SID784
tDIS_SDR_HSIO
Input disable time
0
–
–
–
7.5
0.6
ns
ns
tIO_SKEW_S-
DR_HSIO
Data skew (first data bit to
last data bit)
SMIF HSSPI(SDR) specification for GPIO_STD
SID760A CL_SDR_GPIO
Load capacitance
–
1
–
–
–
30
–
pF
Guaranteed by
design
SID761A SR_SDR_GPIO
Input rise and fall slew rates
V/ns
SID762A fCK_SDR_GPIO
SID763A tCK_SDR_GPIO
SID764A DCK_SDR_GPIO Clock duty
SID765A CSR_SDR_GPIO
SID766A tCS_SDR_GPIO
Clock frequency
Clock period
–
–
–
–
–
32
–
55
–
MHz
ns
%
V/ns
ns
1 / f
CK_SDR_GPIO
45
1
30
Clock rise and fall slew rates
Chip select HIGH time
–
Chip select active setup
time
SID767A tCSS_SDR_GPIO
9
–
–
ns
SID768A tCSH_SDR_GPIO
SID769A tSU_SDR_GPIO
SID780A tHD_SDR_GPIO
SID781A tV_SDR_GPIO
SID782A tHO_SDR_GPIO
Chip select active hold time
Data setup time
Data hold time
Clock LOW output valid
Input hold time
15
4.5
6
4.5
2
–
–
–
–
–
–
–
–
9
–
ns
ns
ns
ns
ns
Guaranteed by
design
SID783A tDIS_SDR_GPIO
Input disable time
0
–
22.5
ns
Datasheet
171
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-33 SMIF specifications (continued)
Spec ID
Parameter
tIO_SKEW_S-
DR_GPIO
Description
Data skew (first data bit to
last data bit)
Min
Typ Max Units Details/Conditions
Guaranteed by
SID784A
–
–
1.8
ns
design
SMIF HSSPI(DDR) specification for HSIO_STD
SID760B CL_DDR_HSIO
Load capacitance
–
–
–
15
-
pF
Guaranteed by
design
SID761B SR_DDR_HSIO
Input rise and fall slew rates
1.5
V/ns
SID762B
fCK_DDR_HSIO
2
SID763B tCK_DDR_HSIO
SID764B DCK_DDR_HSIO Clock duty
SID765B CSR_DDR_HSIO Clock rise and fall slew rates
Clock frequency
Clock period
-
–
90
MHz
1 / f
–
–
–
–
–
55
–
ns
%
V/ns
ns
CK_DDR_HSIO
45
1.5
10
SID766B tCS_DDR_HSIO
Chip select HIGH time
–
Chip select active setup
time
SID767B tCSS_DDR_HSIO
4
–
–
ns
SID768B tCSH_DDR_HSIO
SID769B tSU_DDR_HSIO
SID780B tHD_DDR_HSIO
SID781B tV_DDR_HSIO
SID782B tHO_DDR_HSIO
Chip select active hold time
Data setup time
Data hold time
Clock LOW output valid
Input hold time
4
2
1.2
0
–
–
–
–
–
–
–
–
6.5
–
ns
ns
ns
ns
ns
1
Guaranteed by
design
Guaranteed by
design
SID783B tDIS_DDR_HSIO
Input disable time
–
–
–
–
7.5
0.6
ns
ns
tIO_SKEW_D-
SID784B
Data skew (first data bit to
last data bit)
DR_HSIO
SMIF HSSPI(DDR) specification for GPIO_STD
SID760C CL_DDR_GPIO
Load capacitance
–
1
–
–
–
15
–
pF
Guaranteed by
design
SID761C SR_DDR_GPIO
Input rise and fall slew rates
V/ns
SID762C fCK_DDR_GPIO
SID763C tCK_DDR_GPIO
SID764C DCK_DDR_GPIO Clock duty
SID765C CSR_DDR_GPIO Clock rise and fall slew rates
SID766C tCS_DDR_GPIO
Clock frequency
Clock period
–
–
–
–
–
32
-
55
–
MHz
ns
%
V/ns
ns
1 / f
CK_DDR_GPIO
45
1
30
Chip select HIGH time
–
Chip select active setup
time
SID767C tCSS_DDR_GPIO
5
–
–
ns
SID768C tCSH_DDR_GPIO
SID769C tSU_DDR_GPIO
SID780C tHD_DDR_GPIO
SID781C tV_DDR_GPIO
SID782C tHO_DDR_GPIO
Chip select active hold time
Data setup time
Data hold time
Clock LOW output valid
Input hold time
4
5
4.5
0
–
–
–
–
–
–
–
–
9
–
ns
ns
ns
ns
ns
3
Guaranteed by
design
Guaranteed by
design
SID783C tDIS_DDR_GPIO
Input disable time
–
–
–
–
22.5
1.8
ns
ns
tIO_SKEW_D-
SID784C
Data skew (first data bit to
last data bit)
DR_GPIO
Datasheet
172
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-33 SMIF specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
SMIF HYPERBUS™ Specification for HSIO_STD
SID788
SID786
CL_HB_HSIO
Load capacitance
–
1
–
–
20
–
pF
For all signals,
SRI_HB_HSIO
Input rise and fall slew rates
V/ns guaranteed by
design
Output rise and fall slew
rates
SID787
SRO_HB_HSIO
1
–
–
V/ns For all signals
Clock characteristics
SID700
SID701
SID702
fCK_HB_HSIO
Clock frequency
Clock period
–
–
–
–
100
–
MHz
ns
1 / fCK_H-
B_HSIO
45
tCK_HB_HSIO
DCK_HB_HSIO Clock duty
55
%
AC parameters
Chip select HIGH between
transactions
Chip select setup to next CK
rising edge
Guaranteed by
design
SID706
SID708
tCSHI_HB_HSIO
10
3
–
–
–
–
ns
tCSS_HB_HSIO
ns
SID709
SID710
SID711
SID715
SID718
tDSV_HB_HSIO
tOSU_HB_HSIO
tOH_HB_HSIO
tCKD_HB_HSIO
tCKDS_HB_HSIO
Data strobe valid
DQ output setup
DQ output hold
CK transition to DQ valid
CK transition to RWDS valid
–
1
1
1
1
–
–
–
–
–
12
–
–
5.5
5.5
ns
ns
ns
ns
ns
RWDS transitiontoinput DQ
valid
Input DQ invalid to RWDS
transition
Chip select hold after CK
falling edge
SID719
SID720
SID721
tDSS_HB_HSIO
tDSH_HB_HSIO
tCSH_HB_HSIO
–0.8
–0.8
0
–
–
–
0.8
0.8
-
ns
ns
ns
SMIF HYPERBUS™ specification for GPIO_STD
SID785A CL_HB_GPIO
Load capacitance
–
–
–
20
–
pF
For all signals,
V/ns guaranteed by
design
SID786A SRI_HB_GPIO
Input rise and fall slew rates
0.45
Output rise and fall slew
rates
SID787A SRO_HB_GPIO
0.45
–
–
V/ns For all signals
Clock characteristics
SID700A fCK_HB_GPIO
Clock frequency
Clock period
-
–
–
–
32
–
MHz
ns
1 / fCK_H-
B_GPIO
SID701A tCK_HB_GPIO
SID702A DCK_HB_GPIO Clock duty
45
55
%
AC parameters
Chip select HIGH between
transactions
Guaranteed by
design
SID706A tCSHI_HB_GPIO
30
–
–
ns
Datasheet
173
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-33 SMIF specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
Chip select setup to next CK
rising edge
SID708A tCSS_HB_GPIO
SID709A tDSV_HB_GPIO
9
–
–
–
ns
ns
Guaranteed by
design
Data strobe valid
–
36
SID710A tOSU_HB_GPIO
SID711A tOH_HB_GPIO
SID715A tCKD_HB_GPIO
SID718A tCKDS_HB_GPIO
DQ output setup
DQ output hold
CK transition to DQ valid
CK transition to RWDS valid
3
3
3
3
–
–
–
–
–
–
16.5
16.5
ns
ns
ns
ns
RWDS transitiontoinput DQ
valid
Input DQ invalid to RWDS
transition
Chip select hold after CK
falling edge
SID719A tDSS_HB_GPIO
SID720A tDSH_HB_GPIO
SID721A tCSH_HB_GPIO
–2.4
–2.4
0
–
–
–
2.4
2.4
–
ns
ns
ns
tCK
VDD IO_1
or
VDD IO_3
CK
VSSD
or
VSSIO_3
tSU
tHD
0.5 x VDDIO_1
or VDD IO_3
Data
Timing Reference Level
Figure 26-31 SDR write timing reference level
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tV
tV
0.5 x
Data
Timing Reference Level
VDDIO_1 or
VDDIO_3
Figure 26-32 SDR read timing reference level
Datasheet
174
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tSU
tHD
tSU
tHD
0.5 x VDDIO_1
or VDD IO_3
Data
Timing Reference Level
Figure 26-33 DDR write timing reference level
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
tV
VSSIO_3
0.5 x
Timing
VDDIO_1 or
Data
VDDIO_3
Reference Level
Figure 26-34 DDR read timing reference level
CK
1
6
Chip
select
2
3
8
4
5
LSB IN
LSB OUT
MSB IN
MSB OUT
Data
1: Chip select active setup time = tCSS
2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW output valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS
Figure 26-35 SDR write and read timing diagram
Datasheet
175
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
CK
7
1
Chip
select
4
5
4
8
2
3
2
3
MSB OUT
LSB OUT
MSB IN
LSB IN
Data
1: Chip select active setup time = tCSS
2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW output valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS
Figure 26-36 DDR write and read timing diagram
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tIS
tIH
tIS
tIH
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 26-37 HYPERBUS™ timing reference level
9
Chip
select
10
1
CK
2
5
RWDS
3
4
3
4
DQ[7:0]
(output)
Command Address
Host drives DQ[7:0] and RWDS
6
7
8
DQ[7:0]
(input)
Memory drives DQ[7:0] and RWDS
1: Chip select setup to next CK rising edge = tCSS
2: Data strobe valid = tDSV
3: DQ output setup = tOSU
4: DQ output hold = tOH
5: CK transition to RWDS valid = tCKDS
6: CK transition to DQ valid = tCKD
7: RWDS transition to input DQ valid= tDSS
8: Input DQ invalid to RWDS transition = tDSH
9: Chip select hold after CK falling edge = tCSH
10: Chip select HIGH between transactions = tCSHI
Figure 26-38 HYPERBUS™ timing diagram
Datasheet
176
002-33522 Rev. *B
2022-10-21
27
Ordering information
The XMC7200 microcontroller part numbers and features are listed in Table 27-1. The Arm® TAP JTAG ID is 0x6BA0 0477.
Table 27-1 XMC7200 ordering information
Code-flash
(KB)
Work-flash
(KB)
RAM
(KB)
ADC
SCB
Ethernet
channels
Temp
Grade
Ordering Code
Package
CM7 Cores
JTAG ID code
channels
channels
XMC7200-F176K8384
XMC7200D-F176K8384
XMC7200-E272K8384
XMC7200D-E272K8384
176-TEQFP
176-TEQFP
272-BGA
1
2
1
2
8384
8384
8384
8384
256
256
256
256
1024
1024
1024
1024
81
81
96
96
10
10
11
11
1
1
2
2
125°C
125°C
125°C
125°C
0x1E540069
0x1E541069
0x1E542069
0x1E543069
272-BGA
Table 27-2
Description
XMC prefix
Series name
Dual-core option
Ordering code nomenclature
Values
XMC
7200
D
Meaning
Comment
XMC prefix- industrial microcontroller
High-end XMC7000 series
Dual-core option based on both dies
Fixed
Optional. Omitting “D”
in part number means
single core version
Code-flash/
Work-flash/RAM
Density
8348
8348KB/256KB/1024KB
Fixed
PKG pin count
176
272
F
176-pin
272-pin
TEQFP
FBGA
PKG pin count options
Package option
Available package
options
E
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
28
Packaging
XMC7200 microcontroller is offered in the packages listed in the Table 28-1.
Table 28-1
Package information
Dimensions[69]
Contact/Lead
Pitch
Package
Coefficient of Thermal Expansion
I/O Pins
148
176-TEQFP 24 × 24 × 1.70 mm (max)
272-BGA 16 × 16 × 1.70 mm (max)
0.5-mm
a1[70] = 8.4 ppm/°C, a2[71] = 29.4 ppm/°C
a1[70] = 11.9 ppm/°C, a2[71] = 34.3
ppm/°C
0.8-mm
220
Table 28-2
Parameter
Package characteristics
Description
Conditions
Min
Typ
Max
Units
Operating ambient
temperature
TA
TJ
–
–
–40
–
125
°C
Operating junction
temperature
–
–
150
°C
176-TEQFP
272-BGA
–
–
–
–
–
–
–
–
–
–
–
–
16.4
22.4
11.96
13.5
7.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Package thermal resistance,
RθJA
RθJB
[72, 73]
junction to ambient θJA
176-TEQFP
272-BGA
Package θJB
176-TEQFP
272-BGA
Package thermal resistance,
RθJC
junction to case θJC
8.9
Table 28-3
Solder reflow peak temperature, package moisture sensitivity level (MSL), IPC/JEDEC
J-STD-2
Maximum peak temperature Maximum time at peak temperature
MSL
Package
(°C)
260
260
(seconds)
176-TEQFP
272-BGA
30
30
3
3
Notes
69.The dimensions (column 2) are valid for room temperature.
70.a1 = CTE (Coefficient of Thermal Expansion) value below Tg (ppm/°C) (Tg is glass transition temperature which is 131°C).
71.a2 = CTE value above Tg (ppm/°C).
72.Maximum value °C/Watt shown is for TA = 125 °C.
73.Board condition complies to JESD51-7(4 Layers).
Datasheet
178
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
002-25324 **
Figure 28-1
Package outline – 176-TEQFP
Datasheet
179
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
002-24865 *A
Figure 28-2
Package outline – 272-BGA
Datasheet
180
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Appendix
29
Appendix
29.1
Bootloading or end-of-line programming
• Triggered at device startup, if a trigger condition is applied
• CAN communication may be used
• Bootloader polls for the communication on CAN at the separate time frames, until the overall 300-second
timeout is reached
• If a bootloader command is received on either communication interface, the polling stops and bootloader starts
using this interface
150 ms
10 ms
10 ms
CAN,
100 Kbps
Polling
CAN,
500 Kbps
Polling
CAN,
100 Kbps
Polling
Bootloader
Stopped
Reserved
….
Overall bootloading time, if no communication ( 300 s)
Figure 29-1
Bootloading sequence
CAN interface details
Table 29-1
Sl. No.
CAN interface
Configuration
1
2
3
4
5
6
7
8
9
CAN Mode
CAN Instance
CAN TX
CAN RX
CAN Transceiver NSTB / EN (Low)
CAN Transceiver EN / EN (High)
CAN RX Message ID
Classic CAN
CAN0, Channel#1
P0.2 / CAN0_1_TX
P0.3 / CAN0_1_RX
P23.3 (optional)
P2.1 (optional)
0x1A1
CAN TX Message ID
Baud
0x1B1
100 or 500 kbps alternating
VSS
CAN
Transceiver
XMC7200
EN (Low)
NSTB
EN
EN (High)
TX
TX
RX
RX
Figure 29-2
MCU to CAN transceiver connections
Datasheet
181
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Appendix
29.2
External IP revisions
Table 29-2
IP revisions
Module
IP
mxsdhc
mxttcanfd
armcm0p
armcm7
Revision
Vendor
Synopsys
Bosch
Arm
Arm
Arm
SDHC
CANFD
version 1.70a
M_TTCAN IP revision: Rev.3.2.3
Cortex-M0+ AT590-r0p1-00rel0
CORTEX-M7-r1p1-00rel0
Arm® Cortex®-M0+
Arm® Cortex®-M7
Arm® Coresight
Ethernet
armcoresighttk CoreSight-SoC-TM100-r3p2-00rel0
mxeth
GEM_GXL r1p09
Cadence
Datasheet
182
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Acronyms
30
Acronyms
Table 30-1
Acronyms used in the document
Acronym
A/D
ABS
ADC
AES
Description
Analog to Digital
Absolute
Analog to Digital converter
Advanced encryption standard
Acronym
OVD
PASS
P-DMA
PLL
Description
Over voltage detection
Programmable Analog Subsystem
Peripheral-Direct Memory Access
Phase locked loop
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, Arm®
data transfer bus
POR
Power-on reset
Arm®
Advanced RISC machine, a CPU architecture PPU
PRNG
Brown-out detection PSoC
Controller Area Network with Flexible Data PWM
rate
Peripheral protection unit
Pseudo random number generator
Programmable system on chip
Pulse-width modulation
BOD
CAN FD
CMOS
CPU
CRC
Complementary metal-oxide-semiconductor MCU
Microcontroller Unit
Multi-counter watchdog timer
Memory-Direct Memory Access
Central Processing Unit
MCWDT
Cyclic redundancy check, an error-checking M-DMA
protocol
CSV
CTI
Clock supervisor
MISO
MMIO
MOSI
MPU
NVIC
RAM
RISC
ROM
RTC
Master-in slave-out
Memory mapped I/O
Master-out slave-in
Memory protection unit
Nested vectored interrupt controller
Random access memory
Reduced-instruction-set computing
Read only memory
Cross Trigger Interface
Data encryption standard
Error correcting code
External crystal oscillator
Embedded Trace Macrocell
Frequency Locked Loop
Floating point unit
Green hills tool chain with IDE
General purpose input/output
Hardware security module
Input/output
Inter-Integrated Circuit, a communications SDA
protocol
DES
ECC
ECO
ETM
FLL
FPU
GHS
GPIO
HSM
I/O
Real-time clock
SAR
SCB
SCL
Successive approximation register
Serial communication block
I2C serial clock
I2C
I2C serial data
I2S
Inter-Integrated Circuit Sound
Internal low-speed oscillator
Internal main oscillator
SHA
SHE
SMPU
SPI
Secure hash algorithm
Secure hardware extension
Shared memory protection unit
Serial peripheral interface, a communi-
cations protocol
ILO
IMO
IPC
Inter-processor communication
IrDA
IRQ
Infrared interface
Interrupt request
SRAM
SWD
Static random access memory
Single wire debug
JTAG
LVD
OTA
OTP
Joint test action group
Low voltage detection
Over-the-air programming
One-time programmable
TCM
TCPWM
TTL
Tightly Coupled Memory
Timer/Counter Pulse-width modulator
Transistor-transistor logic
True random number generator
TRNG
Datasheet
183
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Acronyms
Table 30-1
Acronyms used in the document
Acronym
UART
Description
Universal Asynchronous Transmitter
Receiver, a communications protocol
Acronym
XIP
Description
eXecute In Place
WCO
WDT
Watch crystal oscillator
Watchdog timer reset
XTAL
Crystal
Datasheet
184
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Errata
31
Errata
This section describes the errata for the XMC7200 product family. Details include trigger conditions, scope of
impact, available workaround, and silicon revision applicability. Contact your local Infineon Sales Represen-
tative if you have further questions.
Part numbers affected
Part Numbers
All XMC7200 parts
XMC7200 qualification status
Production samples
XMC7200 errata summary
The following table defines the errata applicability to available XMC7200 family devices.
Errata
ID
Silicon
Rev.
Items
XMC7200
Fix Status
[1] CAN FD RX FIFO top pointer feature
96
XMC7200-F176K8320
XMC7200D-F176K8320
XMC7200-E272K8320
XMC7200D-E272K8320
No silicon fix
planned.
does not function as expected
Use workaround.
[2] CAN FD debug message handling state
machine is not reset to Idle state when
CANFD_CH_CCCR.INIT is set
97
No silicon fix
planned.
Use workaround.
D
[3] Limitation of the memory hole in SCB
register space
124
128
No silicon fix
planned.
Use workaround.
[4] Limitation of the memory hole in
Ethernet (ETH) register space
No silicon fix
planned.
Use workaround.
1. CAN FD RX FIFO top pointer feature does not function as expected
Problem Definition
RX FIFO top pointer function calculates the address for received messages in Message
RAM by hardware. This address should restart back from the start address after reading
all messages of RX FIFO n size (n: 0 or 1). However, the address does not restart back
from the start address when RX FIFO n size is set to 1(CANFD_CH_RXFnC.FnS = 0x01).
This results in CPU/DMA reading messages from the wrong address in Message RAM.
Parameters Affected NA
Trigger Condition(s) The RX FIFO top pointer function is used when RX FIFO n size is set to 1 element
(CANFD_CH_RXFnC.FnS = 0x01).
Scope of Impact
Workaround
Received message cannot be correctly read by using the RX FIFO top pointer function,
when RX FIFO n size is set to 1 element.
Any of the following can be used as a workaround:
1) Set RX FIFO n size to 2 or more when using RX FIFO top pointer function.
2) Do not use the RX FIFO top pointer function when RX FIFO n size is set to 1 element.
Instead of RX FIFO top pointer, read received messages from the Message RAM directly.
Fix Status
No silicon fix planned. Use workaround.
Datasheet
185
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Errata
2.CAN FD debug message handling state machine is not reset to Idle state when CANFD_CH_CCCR.INIT is
set
Problem Definition
If either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN
module enters BusOff state, the debug message handling state machine stays in its
current state instead of being reset to Idle state. Configuring the bit
CANFD_CH_CCCR.CCE does not change CANFD_CH_RXF1S.DMS.
Parameters Affected NA
Trigger Condition(s) Either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module
enters BusOff state.
Scope of Impact
The errata is limited to the use case when the debug on CAN functionality is active.
Normal operation of the CAN module is not affected, in which case the debug message
handling state machine always remains in Idle state. In the described use case, the
debug message handling state machine is stopped and remains in the current state
signaled by the CANFD_CH_RXF1S.DMS bit. In case CANFD_CH_RXF1S.DMS is set to
0b11, the DMA request remains active.
Bosch classifies this as a non-critical error with low severity, there is no fix for the IP.
Bosch recommends the workaround listed here.
Workaround
Fix Status
In case the debug message handling state machine has stopped while
CANFD_CH_RXF1S.DMS is 0b01 or 0b10, it can be reset to Idle state by hardware reset
or by reception of debug messages after CANFD_CH_CCCR.INIT is reset to zero.
No silicon fix planned. Use workaround.
3.Limitation of the memory hole in SCB register space
Problem Definition The memory hole [offset address: 0x1000 to 0xFFFF] inside SCB register space is not
aligned to the below defined spec. The offset address bits [15:12] are ignored and
treated as 4’b0000, so write/read access to offset address [0x1000 to 0xFFFF], will
actually happen to [0x0000 to 0x0FFF].
- Access to address gaps in memory mapped space: writes are ignored and any read
returns a zero.
Parameters Affected NA
Trigger Condition(s) Access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
Scope of Impact
Workaround
Fix Status
The memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space is not aligned
to other IP registers.
Do not access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register
space.
No silicon fix planned.
Datasheet
186
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Block diagram
4.Limitation of the memory hole in Ethernet (ETH) register space
Problem Definition
The memory hole [offset address: 0x2000 to 0xFFFF] in ETH register space has the
below mentioned original spec. However, when accessing to address gaps within
[0x1000 to 0x1FFF], the offset address bits [15:13] are ignored and treated as 3’b000,
so write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to
0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will
actually happen to [0x1000 to 0x1FFF].
- Access to address gaps within [0x0000 to 0x0FFF]: writes are ignored and any read
returns a zero.
- Access to address gaps within [0x1000 to 0x1FFF]: returns AHB ERROR.
Parameters Affected NA
Trigger Condition(s) Access to the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000
to 0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF]
in ETH register space.
Scope of Impact
Workaround
Fix Status
Write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to
0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will
actually happen to [0x1000 to 0x1FFF].
Do not access to the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF,
0x7000 to 0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to
0xFFFF] in ETH register space.
No silicon fix planned.
Datasheet
187
002-33522 Rev. *B
2022-10-21
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Errata
Revision History
Document
Date
Description of changes
revision
**
2021-11-12
New datasheet.
Updated Features.
Updated System resources and Peripherals.
Updated I/Os.
Updated Figure 3-1.
Updated DMA controller names.
Corrected wake-up pin numbers
Updated High-speed I/O matrix connections.
Updated Peripheral interrupt assignments and wake-up sources.
Updated Fault assignments.
Removed Smoothing Capacitor Connections table.
Updated DC specifications.
Updated I/O specifications.
*A
2022-08-11
Updated Temperature sensor specifications.
Updated description for CLK_HF3.
Updated SID310.
Updated ECO specifications and PLL specifications.
Updated conditions for SID362E.
Updated typ value and conditions for SID414.
Updated Ethernet specifications.
Updated SMIF specifications.
Updated HYPERBUS™ timing diagram.
Updated Table 27-1.
Updated Block diagram.
Updated Ordering information.
*B
2022-10-21
Datasheet
188
002-33522 Rev. *B
2022-10-21
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
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Edition 2022-10-21
Published by
Infineon Technologies AG
81726 Munich, Germany
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002-33522 Rev. *B
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相关型号：
XMC7200-F176K8384AA
The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores.
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XMC7200D-E272K8384AA
The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores.
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XMC7200D-F176K8384AA
The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores.
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