CDP6805E2CE [INNOVASIC]
Microprocessor Unit; 微处理器单元
| 型号： | CDP6805E2CE |
| 厂家： | 
INNOVASIC, INC |
| 描述： | Microprocessor Unit |
| 文件： | 总31页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
FEATURES
·
Form, Fit, and Function Compatible with the Harris CDP6805E2CE and
Motorola MC146805E2
Internal 8-bit Timer with 7-Bit
Programmable Prescaler
On-chip Clock
Memory Mapped I/O
Versatile Interrupt Handling
True Bit Manipulation
Bit Test and Branch Instruction
Vectored Interrupts
Power-saving STOP and WAIT Modes
Fully Static Operation
·
·
·
·
·
·
·
·
·
·
112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
TM
replacement ICs using its MILES , or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
TM
with the original IC. MILES captures the design of a clone so it can be produced even as silicon
TM
technology advances. MILES also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable
timing.
Package Pinout
RESET_N
(1)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
VDD
OSC1
OSC2
TIMER
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
IA6805E2
40 Pin DIP
(2)
IRQ_N
LI
(3)
DS
(4)
RW_N
AS
(5)
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
(7)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
(6)
(8)
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A12
(7)
(9)
IA6805E2
(8)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
44 Pin LCC
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
B1
B1
B2
B2
NC
B3
A11
A10
B3
B4
A9
A8
B5
B6
VSS
B7
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Description
The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a
CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The
following paragraphs will further describe this system block diagram and design in more detail.
OSC1 OSC2
TIMER/
COUNTER
TIMER
PRESCALER
RESET_N
LI
TIMER CONTROL
OSCILLATOR
IRQ_N
PA0
B0
B1
B2
B3
B4
B5
B6
B7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ACCUMULATOR
CPU
CONTROL
8
8
5
6
5
8
A
MULTIPLEXED
ADDRESS
DATA
MUX
BUS
DRIVE
PORT
A
I/O
INDEX
REGISTER
PORT
A
REG
DATA
DIR
REG
X
BUS
LINES
CONDITION
CODE
REGISTER
CC
STACK
POINTER
CPU
SP
PROGRAM
COUNTER
HIGH
A8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PCH
A9
PROGRAM
COUNTER
LOW
ADDRESS
DRIVE
ADDRESS
BUS
A10
A11
A12
PORT
B
I/O
PCL
PORT
B
REG
DATA
DIR
REG
ALU
LINES
AS
ADDRESS STROBE
DATA STROBE
READ/WRITE
112x8
RAM
BUS
CONTROL
DS
RW_N
Figure 1. System Block Diagram
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
D E S C R I P T I O N
S I G N A L N A M E
a n d V
( P o w e r a n d G r o u n d )
I / O
S o u r c e : T h e s e t w o p i n s p r o v i d e p o w e r t o t h e c h i p . V D p r o v i d e s + 5 v o l t s ( ± 0 . 5 ) p o w e r
D
V
D D
S S
N / A
a n d
V
i s g r o u n d .
S S
T T L : I n p u t pin that c a n b e u s e d t o reset t h e M P U ' s i n t e r n a l state b y p u l l i n g t h e r e s e t _ n
p i n l o w .
R E S E T _ n
( R e s e t )
I
I
T T L : I n p u t pin t h a t is l e v e l a n d e d g e s e n s i t i v e . C a n b e u s e d t o r e q u e s t a n i n t e r r u p t
s e q u e n c e .
I R Q _ n
( I n t e r r u p t R e q u e s t )
T T L w i t h s l e w rate c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h a t
a n e x t o p c o d e f e t c h is in
p r o g r e s s . U s e d o n l y f o r certain d e b u g g i n g a n d test s y s t e m s . N o t c o n n e c t e d in n o r m a l
o p e r a t i o n . O v e r l a p s D a t a S t r o b e ( D S ) s i g n a l . T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e
s t a n d a r d T T L l o a d a n d 5 0 p F .
L I
O
( L o a d I n s t r u c t i o n )
T T L with s l e w r a t e c o n t r o l : O u t p u t pin u s e d to t r a n s f e r data t o o r f r o m
a p e r i p h e r a l o r
m e m o r y . D S o c c u r s a n y t i m e t h e M P U d o e s a d a t a r e a d o r w r i t e a n d d u r i n g d a t a t r a n s f e r
t o o r f r o m i n t e r n a l m e m o r y . D S is a v a i l a b l e a t f O S C ¸ 5 w h e n t h e M P U is n o t in t h e W A I T
o r S T O P m o d e . T h i s o u t p u t i s c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d 1 3 0 p F .
D S
O
O
( D a t a S t r o b e )
T T L w i t h s l e w rate c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h e d i r e c t i o n o f d a t a t r a n s f e r
f r o m i n t e r n a l m e m o r y , I / O r e g i s t e r s , a n d e x t e r n a l p e r i p h e r a l d e v i c e s a n d m e m o r i e s .
R W _ n
( R e a d / W r i t e )
I n d i c a t e s t o
a s e l e c t e d p e r i p h e r a l w h e t h e r t h e M P U is to r e a d ( R W _ n h i g h ) o r w r i t e
( R W _ n l o w ) data o n t h e n e x t data strobe. This o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
T T L l o a d a n d 1 3 0 p F .
T T L with s l e w rate c o n t r o l : O u t p u t s t r o b e u s e d to indicate t h e p r e s e n c e o f a n a d d r e s s
o n t h e 8 - b i t m u l t i p l e x e d b u s . T h e A S l i n e is u s e d to d e m u l t i p l e x t h e e i g h t least s i g n i f i c a n t
A S
a d d r e s s bits f r o m t h e data b u s . A S is a v a i l a b l e a t f O S C
¸ 5 w h e n t h e M P U is n o t in t h e
O
( A d d r e s s S t r o b e )
W A I T o r S T O P m o d e s . This o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L load a n d
1 3 0 p F .
T T L with s l e w rate c o n t r o l : T h e s e 1 6 l i n e s constitute I n p u t / O u t p u t p o r t s
E a c h l i n e is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r a n i n p u t o r o u t p u t u n d e r s o f t w a r e
c o n t r o l o f t h e D a t a D i r e c t i o n R e g i s t e r ( D D R ) a s s h o w n b e l o w in T a b l e a n d F i g u r e 2 .
T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t in t h e D D R to "1" f o r
o u t p u t a n d " 0 " f o r input. In t h e o u t p u t m o d e t h e b i t s a r e l a t c h e d a n d a p p e a r o n t h e
c o r r e s p o n d i n g o u t p u t p i n s . All t h e D D R ' s a r e initialized to " 0 " o n reset. T h e o u t p u t
A a n d B .
1
a
P A 0 - P A 7 / P B 0 - P B 7
( I n p u t / O u t p u t L i n e s )
a
I / O
a
p o r t registers a r e n o t initialized o n reset. E a c h o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
T T L l o a d a n d 5 0 p F .
T T L w i t h s l e w r a t e c o n t r o l : T h e s e f i v e o u t p u t s c o n s t i t u t e t h e h i g h e r o r d e r n o n -
m u l t i p l e x e d a d d r e s s l i n e s . E a c h o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d
1 3 0 p F .
A 8 - A 1 2
O
( H i g h O r d e r A d d r e s s L i n e s )
T T L with slew rate c o n t r o l : T h e s e b i - d i r e c t i o n a l l i n e s constitute t h e l o w e r o r d e r
a d d r e s s e s a n d d a t a . T h e s e l i n e s a r e m u l t i p l e x e d with a d d r e s s p r e s e n t a t a d d r e s s s t r o b e
t i m e a n d data p r e s e n t a t data s t r o b e t i m e . W h e n in t h e d a t a m o d e , t h e s e l i n e s a r e b i -
d i r e c t i o n a l , t r a n s f e r r i n g d a t a t o a n d f r o m m e m o r y a n d p e r i p h e r a l d e v i c e s a s i n d i c a t e d b y
t h e R W _ n p i n . A s o u t p u t s , t h e s e l i n e s are c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d
1 3 0 p F .
B 0 - B 7
( A d d r e s s / D a t a B u s )
I / O
T T L : I n p u t u s e d t o c o n t r o l t h e i n t e r n a l t i m e r / c o u n t e r c i r c u i t r y .
T i m e r
I
T T L O s c i l l a t o r i n p u t / o u t p u t : T h e s e p i n s p r o v i d e c o n t r o l i n p u t f o r t h e on-chip c l o c k
o s c i l l a t o r c i r c u i t s . E i t h e r a c r y s t a l o r e x t e r n a l clock is c o n n e c t e d to t h e s e p i n s to p r o v i d e
O S C 1 , O S C 2
a
s y s t e m c l o c k . T h e c r y s t a l c o n n e c t i o n is s h o w n in F i g u r e 3 . T h e O S C 1 to b u s
( S y s t e m C l o c k )
t r a n s i t i o n s f o r s y s t e m d e s i g n s u s i n g o s c i l l a t o r s s l o w e r t h a n 5 M H z i s s h o w n i n F i g u r e 4 .
T h e c i r c u i t s h o w n in F i g u r e
3 is r e c o m m e n d e d w h e n u s i n g a crystal. A n e x t e r n a l C M O S
I / O
o s c i l l a t o r is r e c o m m e n d e d w h e n u s i n g crystals o u t s i d e t h e s p e c i f i e d r a n g e s . T o m i n i m i z e
o u t p u t d i s t o r t i o n a n d s t a r t - u p s t a b i l i z a t i o n t i m e , t h e c r y s t a l a n d c o m p o n e n t s s h o u l d b e
m o u n t e d a s c l o s e t o t h e i n p u t p i n s a s p o s s i b l e .
C r y s t a l
W h e n a n e x t e r n a l c l o c k is u s e d , i t should b e a p p l i e d to t h e O S C 1 i n p u t w i t h t h e O S C 2
E x t e r n a l C l o c k
i n p u t n o t c o n n e c t e d , a s s h o w n i n F i g u r e 3 .
Table 1
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
I/O Pin Functions
R/W-n DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is
written into the output data latch.
0
1
Data is written into the output data latch and
output to the I/O pin.
1
1
0
1
The state of the I/O pin is read.
the I/O pin is in an output mode. The
output data latch is read.
I/O Port Circuitry and Register Configuration:
DATA DIRECTION
REGISTER
BIT
TO
AND
LATCHED
I/O
PIN
OUTPUT
DATA BIT
OUTPUT
FROM
CPU
INPUT
REG
BIT
INPUT
I/O
PIN
7
6
5
4
3
2
1
0
DATA DIRECTION
A(B)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
$0004 ($0005)
$0000 ($0001)
(DDB7) (DDB6) (DDB5) (DDB4) (DDB3) (DDB2) (DDB1) (DDB0)
REGISTER
PORT A(B)
REGISTER
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PIN
(PB7)
(PB6)
(PB5)
(PB4)
(PB3)
(PB2)
(PB1)
(PB0)
Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines)
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Crystal Parameters Representative Frequencies:
5.0 MHz 4.0 MHz 1.0 MHz
RS max
50W
75W
400W
C0
C1
Q
8 pF
0.02 pF
50 k
7 pF
0.012 pF
40 k
5 pF
0.008 pF
30 k
COSC1
COSC2
15-30 pF
15-25 pF
15-30 pF
15-25 pF
15-40 pF
15-30 pF
Oscillator Connections:
CRYSTAL CIRCUIT
CRYSTAL OSCILLATOR CONNECTIONS
ia6805E2
L
OSC1
39
C1
RS
OSC2
NC
38
38
39
10 MW
C0
OSC2
OSC1
38
OSC2
39
OSC1
IA6805E2
38
39
C
C
OSC1
OSC2
OSC2
OSC1
tOH
tOL
OSC1 PIN
t
tOLOL
Figure 3. OSC1, OSC2 (System Clock)
OSC1 to Bus Transitions Timing Waveforms:
OSC1
AS
DS
RW_n
A[12:8]
MPU
READ
DATA*
B[7:0]
MUX ADDR
MPU READ
B[7:0]
MUX ADDR
MPU WRITE DATA
MPU WRITE
*READ DATA "LATCHED" ON DS FALL
Figure 4. OSC1, OSC2 (System Clock)
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Functional Description
Memory:
The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations
are divided into internal memory space and external memory space as shown in Figure 5.
The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112
bytes of RAM. The MPU can read from or write to any of these locations. During program
reads from on chip locations, the MPU accepts data only from the addressed on chip
location. Any read data appearing on the input bus is ignored. The shared stack area is used
during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack
usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used
for data storage or temporary work locations, but care must be taken to prevent it from
being overwritten due to stacking from an interrupt or subroutine call.
0
1
2
3
4
5
6
0
$0000
PORT A DATA REGISTER
PORT B DATA REGISTER
I/O PORTS
TIMER RAM
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
TIMER DATA REGISTER
127
128
$007F
$0080
ACCESS VIA
PAGE 0
DIRECT
ADDRESS
7
8
255
256
$00FF
$0100
9
TIMER CONTROL REGISTER
10
EXTERNAL MEMORY SPACE
15
16
EXTERNAL MEMORY
SPACE (8064 BYTES)
63
64
RAM
(112 BYTES)
TIMER INTERRUPT FROM WAIT STATE ONLY $1FF6 - $1FF7
TIMER INTERRUPT
EXTERNAL INTERRUPT
SWI
$1FF8 - $1FF9
$1FFA - $1FFB
$1FFC - $1FFD
$1FFE - $1FFF
INTERRUPT
VECTORS
STACK
(64 BYTES MAX)
8191
RESET
127
Figure 5. Memory Map
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IA6805E2
Data Sheet
Microprocessor Unit
Registers:
As of Production Version 00
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
7
0
0
0
0
A
X
ACCUMULATOR
7
INDEX REGISTER
PROGRAM COUNTER
STACK POINTER
12
8
7
PCL
PCH
0
12
0
6
0
0
0
0
1
SP
CC
4
0
H
I
N
Z
C
CONDITION CODE REGISTER
CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
Figure 6. Programming Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
STACK
CONDITION CODE
I
1
1
1
REGISTER
R
E
T
U
R
N
N
T
ACCUMULATOR
E
R
R
U
P
T
DECREASING MEMORY
ADDRESSES
INDEX REGISTER
INCREASING MEMORY
ADDRESSES
0
0
0
PCH
PCL
UNSTACK
Figure 7. Interrupt Stacking Order
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
A(Accumulator):
The accumulator is an 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
X(Index Register):
The index register is an 8-bit register used during the indexed addressing mode. It contains
an 8-bit value used to create an effective address. The index register may also be used as a
temporary storage area when not performing addressing operations.
PC(Program Counter):
The program counter is a 13-bit register that holds the address of the next instruction to be
performed by the MPU.
SP(Stack Pointer):
The stack pointer is a 13-bit register that holds the address of the next free location on the
stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is
set to location $007f. The seven most significant bits of the stack pointer are permanently
set to 0000001. They are appended to the six least significant register bits to produce an
address range down to location $0040. The stack pointer gets decremented as data is pushed
onto the stack and incremented as data is removed from the stack. The stack area of RAM is
used to store the return address on subroutine calls and the machine state during interrupts.
The maximum number of locations for the stack pointer is 64 bytes. If the stack goes
beyond this limit the stack pointer wraps around and points to its upper limit thereby losing
the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and
interrupts use 5 bytes.
CC(Condition code Register):
The condition code register is a 5-bit register that indicates the results of the instruction just
executed. The bit is set if it is high. A program can individually test these bits and specific
actions can be taken as a result of their states. Following is an explanation of each bit.
C(Carry Bit):
The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU)
occurred during the last arithmetic instruction. This bit is also modified during bit test, shift,
rotate, and branch types of instructions.
Z(Zero Bit):
The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero.
N(Negative Bit):
The negative bit indicates the result to the last arithmetic, logical, or data manipulation was
negative (bit 7 in the result is high).
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
I(Interrupt Mask Bit)
The interrupt mask bit indicates that both the external interrupt and the timer interrupt are
disabled (masked). If an interrupt occurs while this bit is set, the interrupt is latched and is
processed as soon as the interrupt bit is cleared.
H(Half Carry Bit)
The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an
ADD or ADC operation.
Resets:
The MPU can be reset by initial power up or by the external reset pin (reset_n).
POR(Power On Reset)
Power on reset occurs on initial power up. It is strictly for power initialization conditions
and should not be used to detect drops in the power supply voltage. There is a 1920 tCYC
time out delay from the time the oscillator is detected. If the reset_n pin is still low at the
end of the delay, the MPU will remain in the reset state until the external pin goes high.
Reset_n
The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of tcyc
to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise
immunity capability.
Interrupts:
The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer
interrupt request, or the software interrupt instruction. When any of these interrupts occur,
normal processing is suspended at the end of the current instruction execution. The
processor registers are saved on the stack (stacking order shown in Figure 7) and the
interrupt mask (I) is set to prevent additional interrupts. Normal processing resumes after
the RTI instruction causes the register contents to be recovered from the stack. When the
current instruction is completed, the processor checks all pending hardware interrupts and if
unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. Masked interrupts are latched for later interrupt service. External
interrupts hold higher priority than timer interrupts. At the end of an instruction execution,
if both an external interrupt and timer interrupt are pending, the external interrupt is
serviced first. The SWI gets executed with the same priority as any other instruction if the
hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing
flowchart.
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Data Sheet
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RESET
SET
I BIT
?
CLEAR
STACK
PC, X, A, CC
I_CC <= 1
SP <= $007F
DDRs <= 0
CLEAR
IRQ_N
REQUEST
LATCH
IRQ_N
EDGE
?
Y
IRQ_N
CLR IRQ_N LOGIC
TIMER <= $FF
PRESCALER <= $7F
TCR <= $7f
N
I <= 1
TCR6=0
AND
TCR7=1?
Y
TIMER
LOAD PC FROM:
SWI: 1FFC/1FFD
IRQ_N: 1FFA/1FFB
TIMER: 1FF8/1FF9
TIMER WAIT:1FF6/
1FF7
PUT 1FFE,1FFF ON
ADDRESS BUS
N
FETCH
INSTRUCTION
IN
RESET
Y
?
RESET_N
PIN = LOW
N
RESET_N
PIN = LOW
IS FETCHED
INSTRUCTION
AN SWI?
Y
SWI
PC+1=>PC
LOAD PC
FROM
1FFE/1FFF
N
EXECUTE ALL
INSTRUCTION
CYCLES
Figure 8. Reset and Interrupt Processing Flowchart
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Data Sheet
Microprocessor Unit
As of Production Version 00
External Interrupt:
If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code
register is cleared, the external interrupt occurs. When the interrupt is recognized, the
current state of the machine is pushed onto the stack and the condition code register I-bit
gets set masking further interrupts until the present one is serviced. The program counter is
then loaded with the contents of the interrupt vector, which contains the location of the
interrupt service routine. The contents of $1FFA and $1FFB specify the address for this
service routine. A functional diagram of the external interrupt is shown in Figure 9 and a
mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows
two different treatments of the interrupt line (irq_n) to the processor. The first shows
several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt
line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The
second shows single pulses on the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of the interrupt service. After a
pulse occurs, the next pulse should not occur until an RTI has occurred. The time between
pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes
to complete the service routine including the RTI instruction.
VDD
EXTERNAL
D
C
Q
Q
INTERUPT
REQUEST
INTERRUPT PIN
I BIT (CCR)
R
POWER-ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED
Figure 9. Interrupt Functional Diagram
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Figure 10. Interrupt Mode Diagram
Timer Interrupt:
If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are
cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is
generated. When the interrupt is recognized, the current state of the machine is pushed onto
the stack and the condition code register I-bit gets set masking further interrupts until the
present one is serviced. The program counter is then loaded with the contents of the timer
interrupt vector, which contains the location of the timer interrupt service routine. The
contents of $1FF8 and $1FF9 specify the address for this service routine. If the MPU is in
the wait mode and a timer interrupt occurs, then the contents of $1FF6 and $1FF7 specify
the service routine. When the timer interrupt service routine is complete, the software
executes an RTI instruction to restore the machine state and starts executing the interrupt
program.
Software Interrupt:
Software interrupt is an executable instruction regardless of the state of the interrupt mask
bit (I) in the condition code register. SWI is similar to hardware interrupts. It executes after
the other interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD
specify the address for this service routine.
Low Power Modes:
The low power modes consist of the stop instruction and the wait instruction. The
following paragraphs explain these modes of operation.
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Stop Modes:
The stop instruction places the MPU in low power consumption mode. The stop instruction
disables clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and
TCR7) are altered to remove any pending timer interrupt requests and to disable any further
timer interrupts. The DS and AS output lines go “low” and the RW_n line goes “high”. The
multiplexed address/data bus goes to the data input state. The high order address lines
remain at the address of the next instruction. External interrupts are enabled by clearing the
I bit in the condition code register. All other registers, memory, and I/O remain unaltered.
Only an external interrupt or reset will bring the MPU out of the stop mode. Figure 11
shows a flowchart of the stop function.
STOP
TCR BIT 7 <= 0
TCR BIT 6 <= 1
CLEAR I BIT
N
RESET?
Y
N
EXTERNAL
INTERRUPT?
Y
FETCH EXTERNAL
INTERRUPT
OR RESET VECTOR
Figure 11. STOP Function Flowchart
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Wait Mode:
The wait instruction places the MPU in low power consumption mode. The wait instruction
disables clocking of most internal registers. The DS and AS output lines go “low” and the
RW_n line goes “high”. The multiplexed address/data bus goes to the data input state. The
high order address lines remain at the address of the next instruction. External interrupts are
enabled by clearing the I bit in the condition code register. All other registers, memory, and
I/O remain unaltered. Only an external interrupt, timer interrupt, or reset will bring the
MPU out of the wait mode. The timer may be enabled to allow a periodic exit from the wait
mode. If an external and a timer interrupt occur at the same time, the external interrupt is
serviced first. Then, if the timer interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MPU is
no longer in the wait mode. Figure 12 shows a flowchart of the wait function.
WAIT
OSCILLATOR
ACTIVE,
CLEAR I BIT,
TIMER CLOCK
ACTIVE,
N
RESET?
Y
EXTERNAL
INTERRUPT?
N
TIMER
INTERRUPT?
(TCR BIT7
= 1)
Y
N
N
Y
TCR
BIT 6 = 0?
Y
FETCH EXTERNAL
INTERRUPT, RESET,
OR TIMER
INTERRUPT (FROM
WAIT MODE ONLY)
Figure 12. WAIT Function Flowchart
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Timer:
The MPU contains a single 8-bit software programmable counter driven by a 7-bit software
programmable prescaler. The counter may be loaded under program control and decrements
to zero. When the counter decrements to zero, the timer interrupt request bit in the timer
control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer
mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an
interrupt request is generated. After completion of the current instruction, the current state
of the machine is pushed onto the stack. The timer interrupt vector address is then fetched
from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was
in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7
is fetched. Power-On-Reset causes the counter to set to $FF.
NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal
clock (AS) or external input.
2. Counter is written to during Data Strobe (DS) and counts down continuously.
TIMER
(PIN 37)
TIMER_n
EXT
CLK
PRESCALER
(7 BITS)
COUNTER
(8 BITS)
INTERRUPT
CONTROL
2 - TO - 1
MUX
INTERRUPT
READ WRITE
INT
CLK
ENABLE /
DISABLE_n
INTERNAL_n / EXTERNAL
INTERNAL
CLOCK
TCR4 TCR5
TCR3 TCR2 TCR1 TCR0
SETTING TCR3 CLEARS
PRESCALER TO ÷ 1
SOFTWARE FUNCTIONS
Figure 13. Timer Block Diagram
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The counter continues to count past zero, falling from $00 to $FF, and continues. The
processor may read the counter at any time without disturbing the count by reading the
timer data register (TDR). This allows a program to determine the length of time since a
timer interrupt has occurred. The timer interrupt request bit remains set until cleared by
software. The interrupt is lost if this happens before the timer interrupt is serviced.
The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits
0-2 are programmed to choose the appropriate prescaler output, which is used as the count
input. The prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation
errors. The processor cannot write to or read from the prescaler.
Timer Input Mode 1:
When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the
timer input is disabled. The internal clock mode can be used for periodic interrupt
generation as well as a reference for frequency and event measurement. The internal clock is
the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait
instruction where it goes low. During the wait instruction the internal clock to the timer
continues to run at its normal rate.
Timer Input Mode 2:
When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to
form the timer input. This mode can be used to measure external pulse widths. The external
pulse turns on the internal clock for the duration of the pulse. The count accuracy in this
mode is ±1 clock. Accuracy improves with longer input pulse widths.
Timer Input Mode 3:
When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled.
Timer Input Mode 4:
When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the
timer input then comes from the external TIMER pin. The external clock can be used to
count external events as well as to provide an external frequency for generating periodic
interrupts.
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TCR (Timer Control Register ($0009)):
An 8-bit register that controls functions such as configuring operation mode, setting ratio of
the prescaler, and generating timer interrupt request signals. All bits except bit 3 are
read/write. Bits TCR5 - TCR0 are unaffected by reset_n.
7
6
5
4
3
2
1
0
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Reset:
0
1
0
0
0
0
0
0
TCR7 – Timer Interrupt Request
Used to indicate the timer interrupt when it is logic one.
1 – Set when the counter decrements to zero or under program control.
0 – Cleared on external reset, POR, STOP instruction, or program control.
TCR6 – Timer Interrupt Mask
Used to inhibit the timer interrupt.
1 – Interrupt inhibited. Set on external reset, POR, STOP instruction, or program
control.
0 – Interrupt enabled.
TCR5 – External or Internal
Selects input clock source. Unaffected by reset.
1 – External clock selected.
0 – Internal clock selected (AS) (fOSC/5).
TCR4 – Timer External Enable
Used to enable external timer pin or to enable the internal clock. Unaffected by reset.
1 – Enables external timer pin.
0 – Disables external timer pin.
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TCR3 – Prescaler Clear
Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location
always indicates a zero. Unaffected by reset.
TCR2, TCR1, TCR0 – Prescaler select bits
Decoded to select one of eight outputs of the prescaler. Unaffected by reset.
Prescaler
TRC2
TRC1
TRC0
RESET
¸ 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
¸ 2
¸
4
¸ 8
¸ 16
¸ 32
¸
64
¸ 128
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Data Sheet
Microprocessor Unit
As of Production Version 00
Instruction Set Description
The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, read-
modify-write, branch, bit manipulation, and control.
Register/Memory Instructions:
Most of the following instructions use two operands. One is either the accumulator or the
index register and the other is obtained from memory. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register operand.
Function
Load A from memory
Load X from memory
Mnemonic
LDA
LDX
STA
Store A in memory
Store X in memory
STX
Add memory to A
Add memory and carry to A
Subtract memory
ADD
ADC
SUB
Subtract memory from A with Borrow
AND memory to A
OR memory with A
Exclusive OR memory with A
Arithmetic compare A with memory
Arithmetic compare X with memory
Bit test memory with A (logical compare)
Jump Unconditional
SBC
AND
O R A
EOR
CMP
CPX
BIT
JMP
Jump to subroutine
JSR
Read-Modify-Write Instructions:
These instructions read a memory or register location, modify or test its contents and then
write the modified value back to memory or the register.
Function
Increment
Mnemonic
INC
Decrement
Clear
DEC
CLR
Complement
COM
NEG
ROL
ROR
LSL
Negate (2's complement)
Rotate Left Thru Carry
Rotate Right Thru Carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
LSR
ASR
TST
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Bit Manipulation Instructions:
The MPU is capable of altering any bits residing in the first 256 bytes of memory. An
additional feature allows the software to test and branch on the state of any bit within these
locations. For test and branch instructions the value of the bit tested is placed in the carry bit
of the condition code register.
Mnemonic
Function
n = 0…7
Branch if bit n set
Branch if bit n clear
Set bit n
BRSET n
BRCLR n
BSET n
Clear bit n
BCLR n
Branch Instructions:
If a specific condition is met, the instruction branches. If not, no operation is performed.
Function
Branch always
Branch never
Mnemonic
BRA
BRN
BHI
Branch if higher
Branch if lower or same
Branch if carry clear
Branch if higher or same
Branch if carry set
BLS
BCC
BHS
BCS
Branch if lower
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
BLO
BNE
BEQ
BHCC
BHCS
BPL
Branch if minus
BMI
Branch if interrupt mask bit clear
Branch if interrupt mask bit set
Branch if interrupt line low
Branch if interrupt line high
Branch to subroutine
BMC
BMS
BIL
BIH
BSR
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Control Instructions:
Used to control processor operation during program execution. They are register reference
instructions.
Function
Transfer A to X
Transfer X to A
Set carry bit
Mnemonic
TAX
TXA
SEC
Clear carry bit
CLC
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-Operation
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Stop
Wait
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Data Sheet
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Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
BTB
BSC
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
Hi
0
1
2
4
5
6
8
9
C
D
Hi
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Low
Low
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
0
0
0000
0001
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
0000
3
3
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
1
1
BRCLR0
BCLR0
BRN
RTS
CMP
CMP
CMP
CMP
CMP
CMP
IX
0001
BTB 2
5
BSC 2
5
REL
3
1
INH
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
3
2
2
3
4
5
6
0010
0011
0100
0101
0110
BRSET1
BSET1
BHI
SBC
SBC
SBC
SBC
SBC
SBC
CPX
0010
3
3
3
BTB 2
5
BSC 2
5
REL
3
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
10
3
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
IX 1
SWI
INH
CPX
CPX
CPX
CPX
CPX
0011
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
4
BRSET2
BSET2
BCC
LSR
DIR 1
LSRA
INH 1
LSRX
INH 2
LSR
IX1 1
LSR
AND
AND
AND
AND
AND
AND
IX
0100
BTB 2
5
BSC 2
5
REL 2
3
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
3
5
BRCLR2
BCLR2
BCS
BIT
BIT
BIT
BIT
BIT
BIT
0101
3
BTB 2
5
BSC 2
5
REL
3
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
6
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
LDA
LDA
IX1 1
LDA
IX
0110
3
3
3
3
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
DIR 3
4
EXT 3
5
IX2 2
6
2
5
4
7
7
8
0111
1000
1001
1010
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
STA
STA
STA
0111
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
8
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
LSL
CLC
EOR
IMM 2
EOR
DIR 3
EOR
EXT 3
EOR
IX2 2
EOR
IX1 1
EOR
1000
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
INH 2
IX
3
5
5
3
5
3
3
6
2
2
3
4
5
4
9
9
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
SEC
ADC
ADC
ADC
ADC
ADC
ADC
1001
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
A
1010
A
BRSET5
BSET5
BPL
DEC
DIR 1
DECA
INH 1
DECX
INH 2
DEC
IX1 1
DEC
CLI
ORA
ORA
ORA
ORA
ORA
ORA
3
3
3
3
BTB 2
5
BSC 2
5
REL 2
3
IX
1
1
1
1
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
B
1011
B 1011
C 1100
BRCLR5
BCLR5
BMI
SEI
ADD
ADD
ADD
ADD
ADD
ADD
IX
BTB 2
BSC 2
REL
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
5
5
3
5
3
3
6
5
2
2
3
4
3
2
C
1100
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
TST
RSP
JMP
JMP
JMP
JMP
JMP
JSR
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
6
IX
4
INH
2
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
D
1101
D
1101
BRCLR6
BCLR6
BMS
TST
DIR 1
TSTA
INH 1
TSTX
INH 2
TST
IX1 1
NOP
BSR
JSR
JSR
JSR
JSR
BTB 2
5
BSC 2
5
REL 2
3
IX
INH 2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
E
1110
E 1110
BRSET7
BSET7
BIL
STOP
LDX
IMM 2
LDX
LDX
LDX
LDX
LDX
IX
3
3
BTB 2
5
BSC 2
5
REL
3
1
INH
2
2
2
DIR 3
4
EXT 3
5
IX2 2
6
IX1 1
5
5
3
3
6
5
4
F
1111
F
1111
BRCLR7
BTB 2
BCLR7
BSC 2
BIH
REL 2
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
WAIT
INH 1
TXA
INH
STX
STX
EXT 3
STX
IX2 2
STX
IX1 1
STX
IX1 1
IX 1
2
DIR 3
IX
REL
Relative
Bit set/clear
Bit test and branch
Indexed, no offset
Indexed, 1 byte offset
Indexed, 2 byte offset
Abbreviations for Address
Modes:
BSC
BTB
IX
IX1
IX2
Opcode in Hexade
Opcode in Binary
F
1111
INH
A
X
IMM
DIR
EXT
Inherent
3
0
0000
Mnemonic
Bytes
SUB
Accumulator
Index Register
Immediate
Direct
IX
1
# of Cycles
Address Mode
Legend:
Extended
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IA6805E2
Data Sheet
Microprocessor Unit
AC/DC Parameters
As of Production Version 00
Absolute maximum ratings:
Supply Voltage (VDD)........................….…...………….….………-0.3V to 6V
Input Pin Voltage (VIN)…………………………………...-0.3 to VDD+0.3V
Operating Temperature……………………………….……....-40°C to 85°C
Storage temperature Range (Tstg).................…........….…...…- 55°C to 150°C
ESD Protection (HBM)………………………………………………5000V
Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed
under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability
of the device.
DC Characteristics
(VDD=4.5 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified
DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Unit
V
VDD
Supply Voltage
4.5
5.5
0.4
-
V OL
V OH
IO L
-
3.5
-
V
Output Voltage, ILOAD £ 2mA
V
2
mA
mA
V
Output Current
IOH
V IH
V IL
IIH
-
-2
-
High Level input Voltage
Low Level input Voltage
High Level input Current
Low Level input Current
2
-
-
0.8
1
V
µA
µA
V
IIL
-
-1
Vt-
Vt+
Schmitt Negative Threshold
Schmitt Positive Threshold
Frequency of Operation
Crystal
1.1
-
-
1.87
V
fOSC
fOSC
-
5
5
MHz
MHz
External Clock
DC
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Control Timing
VSS=0V, TA=TL to TH
VDD = 5.0V ±10%
fOSC = 5MHz
Sym
Min Typ Max Unit
Parameters
I/O Port Timing – Input Setup Time
tPVASL
196
-
-
ns
(Figure 14)
Input Hold Time (Figure 14)
Output Delay Time (Figure 14)
Interrupt Setup Time (Figure 15)
Crystal Oscillator Startup Time
(Figure 16)
tASLPX
tASLPV
TILASL
tOXOV
0
-
0.4
-
-
-
-
0
-
ns
ns
ms
ms
-
5
100
Wait Recovery Startup Time (Figure
17)
Stop Recovery Startup Time
(Figure 18)
tIVASH
tILASH
-
-
-
-
2
2
ms
ms
Required Interrupt Release (Figure 15)
Timer Pulse Width (Figure 17)
Reset Pulse Width (Figure 16)
tDSLIH
tTH, tTL
tRL
-
-
-
-
1.0
-
-
ms
tCYC
ms
0.5
1.05
Timer Period (Figure 17)
Interrupt Pulse Width Low (Figure10)
Interrupt Pulse Period
tTLTL
tILIH
tILIL
1.0
1.0
*
-
-
-
-
-
-
tCYC
tCYC
tCYC
(Figure 10)
Oscillator Cycle Period
(1/5 of tCYC) (Figure 3)
tOLOL
200
-
-
ns
OSC1 Pulse Width High (Figure 3)
OSC1 Pulse Width Low (Figure 3)
tOH
tOL
75
75
-
-
-
-
ns
ns
*The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the
interrupt service routine plus 20 tCYC cycles.
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IA6805E2
Data Sheet
Microprocessor Unit
Bus Timing
As of Production Version 00
VSS=0V, TA=TL to TH (Figure 19)
VDD = 5.0V ±10%
fOSC = 5MHz
1 TTL, 100pF Load
Num
Parameters
Unit
Min
1000
587
403
-
9
97
-
-
18
0
-
Max
DC
-
-
4
-
-
40
11
-
1
2
3
4
8
9
11
16
17
18
19
21
23
24
25
26
27
28
Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Width, DS Low
Pulse Width, DS High
Clock Transition
RW_n
Non-Muxed Address Hold
RW_n Delay From DS Fall
Non-Muxed Address Delay From AS Rise
MPU Read Data Setup
Read Data Hold
MPU Data Delay, Write
Write Data Hold
Muxed Address Delay From AS Rise
Muxed Address Valid to AS Fall
Muxed Address Hold
Delay DS Fall to AS Rise
Pulse Width, AS High
Delay, AS Fall to DS Rise
0
-
26
-
-
-
-
-
204
-
185
103
190
203
185
VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10%
TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz
*NOTE
ADDRESS_STROBE
PORT_INPUT
tPVASL
tASLPX
tASLPV
PORT_OUTPUT
*Note: The address strobe of the first cycle of the next instruction.
Figure 14. I/O Port Timing
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
AS
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
DS
(NOTE)
TDSLIH
ADD_BUS_UNMUX[8:12]
1F (FF) 1F (FF)
NEXT OP CODE ADDRESS
INT ROUTINE
LAST ADDRESS
INT ROUTINE
STARTING ADDRESS
TILASL
IRQ_N__TCR7_N
SP-1
SP-2
SP-3
SP-4
NEW PCH
NEW PCL
MUX_ADD_DATA[0:7]
SP PCL
PCH
X
A
CC
80
NEXT OP CODE
FA (IRQ) FB (IRQ)
F8 (TIMER)F9 (TIMER) INT ROUTINE
1ST OP
RTI
OP CODE
RW_N
Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition
of the same interrupt.
Figure 15. IRQ_n and TCR7_N Interrupt Timing
Figure 16. Power-On-Reset and RESET_n Timing
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
TIMER
tTL
COUNTER=$00
tTH
tTLTL
INT_EXT_CLK
TCR7
tIVASH
AS
n0
n1
n2
n3
n4
n5
n6
n7
DS
OP CODE ADDR
A[12:8]
ADDRESS + 1
1F (FF) 1F (FF)
INT ROUTINE
STARTING
ADDRESS
OP CODE
ADDRESS
ADDR + 1
SP-1
SP-2
SP-3
SP-4
NEW PCH
NEW PCL
SP
B[7:0]
8F
PCL
PCH
X
A
CC F6
F7
WAIT OP CODE
1ST OP CODE
INT ROUTINE
RW_N
Figure 17. Timer Interrupt After WAIT Instruction Timing
TIMER
tTL
COUNTER=$00
tTH
tTLTL
INT_EXT_CLK
TCRB7
tIVASH
AS
n0
n1
n2
n3
n4
n5
n6
n7
DS
OP CODE ADDR
A[12:8]
ADDRESS + 1
1F (FF) 1F (FF)
INT ROUTINE
STARTING
ADDRESS
OP CODE
ADDRESS
ADDR + 1
SP-1
SP-2
SP-3
SP-4
NEW PCH
NEW PCL
SP
B[7:0]
8E
PCL
PCH
X
A
CC F6
F7
STOP OP CODE
1ST OP CODE
INT ROUTINE
RW_N
Figure 18. Interrupt Recovery From STOP Instruction Timing
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
4
4
4
27
26
AS
28
1
2
26
3
DS
4
8
4
4
8
RW_n
11
9
11
9
16
A[12:8]
23
21
25
19
21
B[7:0]
WRITE
VALID
ADDR
VALID WRITE
DATA
24
25
18
18
17
23
23
B[7:0]
READ
VALID
ADDR
VALID READ
DATA
Figure 19. Bus Timing
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Packaging Information
PDIP Packaging
TOP
E1
E
LEAD 1
IDENTIFIER
eA
C
1
eB
LEAD COUNT
DIRECTION
SIDE VIEW (WIDTH)
Lead Count
40 (in Inches)
A
D
Symbol
MIN
-
MAX
.200
-
A
A1
B
.015
.015
.040
.008
1.980
.580
.520
.020
.060
.012
2.065
.610
.560
A1
B1
C
L
D
E
B
B1
E1
e
e
.100 TYP
.100 MIN
SIDE VIEW (LENGTH)
eA
eB
L
.580
-
-
.686
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
PLCC Packaging
D
D1
PIN 1
IDENTIFIER & ZONE
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
LEAD COUNT
44 (in Millimeters)
Symbol
MIN
4.20
2.29
16.51
14.99
MAX
SEATING PLANE
A
A1
D1
D2
D3
E1
E2
E3
e
4.57
3.04
16.66
16.00
.10
e
.51 MIN.
12.70 BSC
16.51
14.99
16.66
16.00
.53 / .33
R 1.14 / .64
D2 / E2
12.70 BSC
1.27 BSC
SIDE VIEW
D
17.40
17.40
17.67
17.65
E
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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Ordering Information
The IA6805E2 is available in two package styles listed in the table below. Other packages and temperature
grades may be available for additional cost and lead time.
Package Type
40 Lead Plastic DIP, 600 mil wide
44 Lead Plastic Leaded Chip Carrier
Temperature Grade
Industrial
Order Number
IA6805E2-PDW40I
IA6805E2-PLC44I
Industrial
Cross Reference to Original Manufacturers
innovASIC Part Number
IA6805E2-PDW40I
MotorolaÒ Part Number
HarrisÒ Part Number
q
MC146805E2CP
MC146805E2P
q
q
CDP6805E2CE
CDP6805E2E
q
IA6805E2-PLC44I
q
q
MC146805E2CFN
MC146805E2FN
q
q
CDP6805E2CQ
CDP6805E2Q
Errata
Production Version 00
1. Functional differences between IA6805E2 and Harris and Motorola Versions: Stop mode on
IA6805E2 will not halt oscillator. Recovery from stop will be quicker.
2. Observations:
A. Original data sheets for Motorola and Harris are inconsistent when describing timer input mode 2.
Original parts and InnovASIC will AND together the timer input with the inverse of the internal
clock (AS).
B. Original Harris part would unpredictably “pre-increment” timer counter when writing to timer
registers. IA6805E2 will not.
C. Original Harris part displays incorrect address on external pins during intermediate cycles (not a
functional problem) of multi-cycle instructions when accessing memory at page boundaries.
IA6805E2 will not.
D. Execution of illegal op-codes on the IA6805E2 will force a system reset. On the original Harris
and Motorola parts, execution of illegal op-codes would produce unpredictable results.
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Page 31 of 31
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