TN82050 [INNOVASIC]
Asynchronous Serial Controller; 异步串行控制器
| 型号： | TN82050 |
| 厂家： | 
INNOVASIC, INC |
| 描述： | Asynchronous Serial Controller |
| 文件： | 总22页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
®
IA82050
Asynchronous Serial Controller
Data Sheet
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Data Sheet
Asynchronous Serial Controller
February 25, 2011
Copyright 2008 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
Intel is a registered trademark of Intel Corporation
MILES™ is a trademark of Innovasic Semiconductor, Inc.
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Data Sheet
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TABLE OF CONTENTS
List of Figures..................................................................................................................................4
List of Tables ...................................................................................................................................4
1.
2.
3.
Features...................................................................................................................................5
Description..............................................................................................................................7
Functional Overview ..............................................................................................................9
3.1 Transmitter ....................................................................................................................9
3.2 Receiver.........................................................................................................................9
3.3 Bus Interface .................................................................................................................9
3.4 Register Description....................................................................................................10
Register Descriptions............................................................................................................11
4.1 Baud Rate Generator A Divide Count, MSB and LSB (BAH/BAL)..........................11
4.2 General Interrupt Enable Register (GER) ...................................................................11
4.3 General Interrupt Register (GIR) ................................................................................11
4.4 Line Configure Register (LCR)...................................................................................11
4.5 Line Status Register (LSR) .........................................................................................12
4.6 Modem Control Register (MCR) ................................................................................12
4.7 Modem Status Register (MSR) ...................................................................................13
4.8 Receive Data Register (RXDATA).............................................................................13
4.9 Scratch Register (SCR) ...............................................................................................13
4.10 Transmit Data Register (TXDATA) ...........................................................................14
AC/DC Parameters ...............................................................................................................15
DC Characteristics................................................................................................................16
AC Characteristics................................................................................................................17
Packaging Information..........................................................................................................18
8.1 PDIP Package..............................................................................................................18
8.2 PLCC Package.............................................................................................................19
Innovasic Part Number Cross-Reference..............................................................................20
4.
5.
6.
7.
8.
9.
10. Revision History...................................................................................................................21
11. For Additional Information...................................................................................................22
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Data Sheet
Asynchronous Serial Controller
February 25, 2011
LIST OF FIGURES
Figure 1. Package Pinout ................................................................................................................6
Figure 2. Functional Block Diagram ..............................................................................................8
Figure 3. PDW Physical Package Dimensions .............................................................................18
Figure 4. PLCC Physical Package Dimensions ............................................................................19
LIST OF TABLES
Table 1. Register Summary...........................................................................................................10
Table 2. General Interrupt Enable Register ..................................................................................11
Table 3. General Interrupt Register ..............................................................................................11
Table 4. Line Configure Register..................................................................................................12
Table 5. Line Status Register........................................................................................................12
Table 6. Modem Control Register ................................................................................................13
Table 7. Modem Status Register...................................................................................................13
Table 8. AC/DC Parameters .........................................................................................................15
Table 9. DC Characteristics..........................................................................................................16
Table 10. AC Characteristics........................................................................................................17
Table 11. Innovasic Part Number Cross-Reference for the PDIP ................................................20
Table 12. Innovasic Part Number Cross-Reference for the PLCC...............................................20
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Data Sheet
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February 25, 2011
1.
Features
•
•
Form, Fit and Function Compatible with the Intel 82050
Packaging options available: 28-Pin Plastic DIP and 28-Lead Plastic Leaded Chip
Carrier (see Figure 1, Package Pinout)
•
•
•
•
Asynchronous Serial Channel Operation
Separate Transmit and Receive FIFOs with Programmable Threshold
Programmable Baud Rate Generator up to 288K Baud
Special Protocol Features
– Loopback Modes
– 5- to 8-Bit Character Format
The IA82050 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation"
while ensuring they are compatible with the original IC. MILESTM captures the design of a
clone so it can be produced even as silicon technology advances. MILESTM also verifies the
clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA82050 including functional
and I/O descriptions, electrical characteristics and applicable timing.
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D7
D5 D4 D3 D2 D1
D6
IA82050
D4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
D3
D5
D6
D2
28-Pin DIP
D1
(4) (3) (2) (1) (28) (27) (26)
D7
D0
(25)
D0
INT
TXD
(5)
(6)
(7)
(8)
(9)
INT
A2
(24)
A2
TXD
A1
IA82050
(23)
A1
VSS
VSS
A0
(22)
A0
X2 or OUT2n
X1 or CLK
X2 or OUT2n
X1 or CLK
VDD
RDn
28-Lead
LCC
(21)
VDD
(20)
SCLK or RIn
DSRn or TA or OUT0n
(10)
(11)
RDn
SCLK or RIn
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
RXD
(10)
(11)
(12)
(13)
(14)
(19)
(18)
(17)
(16)
(15)
WRn
(19)
WRn
CSn
RESET
RTSn
(12) (13) (14) (15) (16) (17) (18)
CTSn
DTRn or TB
Figure 1. Package Pinout
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2.
Description
The IA82050 is an asynchronous serial controller that provides a CPU interface to one transmit
and one receive channel. It is form, fit, and function compatible with the Intel® 82050 and
82510. Configuration registers are used to control the serial channel, interrupts, and modes of
operation. The CPU controls this device via address and data lines with read/write control. The
CPU also uses this interface to read and write data to receive and transmit data through the serial
channel. FIFOs and various serial modes can be used to help off-load the CPU from transmitting
and receiving data. An interrupt line provides an indication to the CPU that the device requires
servicing. The device can be configured for 8250A/16450 compatibility. See Figure 2,
Functional Block Diagram.
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Data Sheet
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February 25, 2011
A(2:0)
D(7:0)
TRANSMITTER
TXD
BUS INTERFACE
(Reset Logic,
Registers,
RDn
WRn
Interrupt Generation,
CSn
INT
RESET
RECEIVER
RXD
CTSn
RTSn
TIMING
(Baud Rate
PIN
Generators A & B,
CONFIGURATION
CONFIG., STATUS, RXDATA
Clocking
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
DTRn or TB
MODEM
X1 or CLK
X2 or OUT2n
SCLK or RIn
Figure 2. Functional Block Diagram
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3.
Functional Overview
3.1
Transmitter
The Transmit function consists of a one-character FIFO, and a Transmit Engine. The transmit
engine is responsible for reading the data out of the FIFO and placing it in the proper order on
the TXD pin. The transmit engine is highly configurable to be compatible with numerous
formats, including 16450 and 8250 modes of communication. Transmit Communication
parameters that can be programmed include:
•
•
•
Parity modes
Stop Bits
Character Length
For more details, see Chapter 5, Register Descriptions.
3.2
Receiver
The Receiver function consists of a one-character FIFO and a receive engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and
placing the data in the FIFO. The receive engine is highly configurable with parameters that
include:
•
•
•
Parity modes
Stop Bits
Character Length
For more details, see Chapter 5, Register Descriptions.
3.3
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82050 Registers. It consists of the following I/O lines:
•
•
•
•
•
•
•
A0, A1, A2 : 3-Bit Address
D0-D7 : 8-Bit Data
RDn:
WRn:
CSn:
INT:
Active Low Read Enable
Active Low Write Enable
Active Low Chip Select
Interrupt Output
RESET: Chip Reset
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3.4
Register Description
Table 1 presents the register summary.
Table 1. Register Summary
Register ADDR DLAB Mode
Default
BAH
BAL
GER
GIR
LCR
LSR
MCR
MSR
RXDATA
SCR
TXDATA
001
000
001
010
011
101
100
110
000
111
000
1
1
0
X
X
X
X
X
0
R/W 00000000
R/W 00000010
R/W 00000000
R
00000001
R/W 00000000
R/W 01100000
R/W 00000000
R/W 00000000
R
Unknown
R/W 00000000
N/A
X
0
W
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Data Sheet
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4.
Register Descriptions
4.1
Baud Rate Generator A Divide Count, MSB and LSB (BAH/BAL)
Baud Rate Generator A Divide Count (MSB and LSB) – When generating TXCLK or RXCLK,
the selected source clock will be divided by this value (ADDR 001/000, Mode R/W, Default
00000000/00000010).
4.2
General Interrupt Enable Register (GER)
Enables the general categories of interrupts when generating INT (ADDR 001, Mode R/W,
Default 00000000).
Table 2. General Interrupt Enable Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
MIE RXIE TFIE RFIE
MIE
Modem Interrupt Enable, 1=Enabled, 0=Disabled
Receive Interrupt Enable, 1=Enabled, 0=Disabled
Transmit FIF0 Interrupt Enable, 1=Enabled, 0=Disabled
Receive FIFO Interrupt Enable, 1=Enabled, 0=Disabled
RXIE
TFIE
RFIE
4.3
General Interrupt Register (GIR)
Read-only interrupt register containing priority encoded enabled interrupt vector and interrupt
pending flag. Writes to this register only affect Bank Pointer bits (ADDR 010, Mode R, Default
00000001).
Table 3. General Interrupt Register
Bit 7
0
Bit 6
BANK1 BANK0
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BI1 BI0 IPN
0
0
BANK1, BANK0 – Bank Pointer – not used in IA82050, user must ensure these bits are never written
BI1, BI0 – Interrupt Vector
11=Receive Interrupt (highest priority)
10=Receive FIFO Interrupt
01=Transmit FIF0 Interrupt
00=Modem Interrupt (lowest priority)
IPN – Interrupt Pending (1=no interrupt pending, 0=interrupt pending)
4.4
Line Configure Register (LCR)
Defines configuration of serial message (ADDR 011, Mode R/W, Default 00000000).
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Table 4. Line Configure Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DLAB SBK PM2 PM1 PM0 SBL0 CL1 CL0
DLAB – Divisor Latch Access Bit (see Register Summary table)
SBK – Set Break (0=normal TXD operation, 1=TXD held low – break condition)
PM2, PM1, PM0 – Parity Mode
XX0=No Parity
001=Odd Parity
011=Even Parity
101=High Parity
111=Low Parity
SBL0 – Stop Bit Length
0 = 1 stop bit
1 = 2 stop
CL1, CL0 – Character Length
00=5 Bits
01=6 Bits
10=7 Bits
11=8 Bits
4.5
Line Status Register (LSR)
Reports status of serial link (compatible with 8250). BKD, FE, PE, and OE are cleared when
read. Writing a zero to RFIR acknowledges the interrupt (ADDR 101, Mode R/W, Default
01100000).
Table 5. Line Status Register
Bit 7 Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PE OE RFIR
0
TXST TFST BKD FE
TXST Transmitter Status (1=TX idle or disabled, 0=TX busy)
TFST Transmit FIFO Status (1=TX FIFO empty, 0=full)
BKD
FE
PE
Break Detected (1=break detected, 0=no break detected)
Framing Error (1=framing error, 0=no framing error)
Parity Error (1=parity error, 0=no parity error)
OE
Overrun Error (1=overrun error, 0=no overrun error)
RFIR Receive FIFO Interrupt Request (1=RX FIFO full, 0=empty)
4.6
Modem Control Register (MCR)
Drives the general purpose outputs that may be used as modem control discretes. (ADDR 100,
Mode R/W;W, Default 00000000)
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Table 6. Modem Control Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2 Bit 1 Bit 0
0
0
0
LC OUT2 OUT1 RTS DTR
LC
Loopback Control (0=normal operation, 1=loopback mode)
OUT2 Output 2 State (1=OUT2N low, 0=OUT2N high)
OUT1 Output 1 State (1=OUT1N low, 0=OUT1N high)
RTS
DTR
Ready To Send State (1=RTSN low, 0=RTSN high)
Data Terminal Ready State (1=DTRN low, 0=DTRN high)
4.7
Modem Status Register (MSR)
Reports status of modem input pins DCDN, RIN, DSRN and CTSN. All but CTSN must be
enabled via the PMD register. The “delta” bits are cleared on a read. (ADDR 110, Mode R/W;R,
Default 00000000).
Table 7. Modem Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DCDC RIC DSRC CTSC DDCD DRI DDSR DCTS
DCDC
RIC
DCDN Complement (1=DCDN low, 0=DCDN high)
RIN Complement (1=RIN low, 0=RIN high)
DSRC
CTSC
DDCD
DRI
DDSR
DCTS
DSRN Complement (1=DSRN low, 0=DSRN high)
CTSN Complement (1=CTSN low, 0=CTSN high)
Delta DCDN (1=DCDN changed since last read, 0=no change)
Delta RIN (1=RIN transitioned low since last read, 0=no change or transition high)
Delta DSRN (1=DSRN changed since last read, 0=no change)
Delta CTSN (1=CTSN changed since last read, 0=no change)
4.8
Receive Data Register (RXDATA)
(ADDR 000, Mode R, Default Unknown)
Receive Data - A read from this location removes the data receive byte from the RX FIFO. The
LSB of RXDATA will correspond to the first bit received after the start bit of the serial
character. The MSB will correspond to the eighth data bit received after the start bit. If the
character length (LCR_CL) is less than eight, the unused RXDATA bits will be zero.
A read from RXDATA will be directly from the RX FIFO.
4.9
Scratch Register (SCR)
(ADDR 111, Mode R/W, Default 00000000)
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General purpose scratch pad register to be defined by user.
4.10 Transmit Data Register (TXDATA)
(ADDR 000, Mode W, Default N/A)
Transmit Data - A write to this location adds a data byte to the TX FIFO, and initiates the
transmit sequence.
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5.
AC/DC Parameters
Table 8. AC/DC Parameters
Parameters
Supply voltage, VDD
Absolute Maximum Ratings
-0.3V to +6.0V
Input voltage, VIN
-0.3V to VDD +0.3V
±10 mA, 25 C
-40 C to +85°C
-40°C to +85°C
- 55°C to +150°C
Input pin current, IIN
Operating temperature range
Ambient temperature under bias
Storage temperature
Lead temperature
+300°C, 10 sec.
Power dissipation
155 mW, 125°C, 25MHz, 15% Toggle
Caution: Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. Operating the device beyond
the conditions indicated in the “recommended operating conditions” section
is not recommended. Operation at the “absolute maximum ratings” may
adversely affect device reliability.
The input and output parametric values in section VII-B, parts 1, 2 and 3, are directly related to
ambient temperature and DC supply voltage. A temperature or supply voltage range other than
those specified in the operating conditions above will affect these values, making invalidating
Innovasic’s guarantee of part performance.
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6.
DC Characteristics
Table 9. DC Characteristics
Symbol
VIL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Notes
(1)
(1)
Min
-0.5
2.1
Max
0.3
VDD+.3
VDD+.3
0.4
Unit
V
V
V
V
V
VIH1
VIH2
VOL
VOH
ILI
(2)
2.1
(2),(8)
(3),(8)
(4)
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
2.4
1
10
1.12
-137
100
1.92
A
A
ILO
(5)
ICC
IPU
(6)
(12)
(9)
mA/MHz
A
-28.3
N/A
ISTBY
IOHR
IOLR
CIN
CIO
CXTAL
A
(10)
(11)
(7)
mA
mA
pF
pF
pF
5
6
6
I/O Capacitance
X1, X2 Load
(7)
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @IOL = 1.92 mA
3. @IOH = 1.92 mA
4. 0< VIN <VCC
5. 0.4V < VOUT < VCC – 0.4V
6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext.
1X CLK, IOL = IOH = 0
7. Freq. = 1 MHz
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output drive
requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured
to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW.
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V
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7.
AC Characteristics
Table 10. AC Characteristics
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
CLK Rise Time
Min
Max
250 ns
108 ns
Notes
Divide by Two
No Divide by
54 ns
54 ns
25 ns
25 ns
10 ns
10 ns
Divide by Two
Measured between 0.3 *
VDD and 0.7 * VDD
Divide by Two
CLK Fall Time
Measured between 0.3 *
VDD and 0.7 * VDD
No Divide by
CLK Rise Time
CLK Fall Time
15 ns
15 ns
No Divide by
Crystal Frequency
Reset Width
RTS/DTR Low Setup to
Reset inactive
1 Mhz
8 * Clock Period
6 * Clock Period
20 Mhz
RTS/DTR Low Hold after
Reset inactive
Clock Period
– 20 ns
RDn Active Width
2* clock period
+ 65 ns
Address/CSn Setup Time to
RDn Active
7 ns
Address/CSn Hold after
RDn Inactive
0 ns
RDn or WRn Inactive to
Active Delay
Clock Period +
15 ns
Data Out Float Delay after
RDn Inactive
40 ns
WRn Active Width
2 * Clock Period
+ 15 ns
Address CSn Setup Time to
WRn Active
7 ns
Address and CSn hold
Time after WRn
Data in Setup Time to WRn
Inactive
Data In Hold Time after
WRn Inactive
0 ns
90 ns
12 ns
SCLK Period
SCLK Period
RXD Setup Time to SCLK
High
216 ns
3500 ns
250 ns
16x Clocking Mode
1x Clocking Mode
RXD Hold Time after SCLK
High
250 ns
TXD Valid after SCLK Low
TXD Delay after RXD
170 ns
170 ns
Remote Loopback
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8.
Packaging Information
8.1
PDIP Package
E1
E
Pin
Identifier
eA
eB
Pin Count
Direction
1
C
Top
Side View (Width)
Legend:
A
D
28 (in Inches)
Symbol
A
Min
-
Max
0.200
-
0.020
0.070
0.012
0.610
0.560
A1
B
B1
C
E
E1
e
0.015
0.015
0.050
0.008
0.580
0.520
A1
0.100 TYP
eA
eB
L
B2
S
0.580
-
-
L
0.686
0.100 Min
B
-
-
-
-
B1
e
Side View (Length)
Figure 3. PDW Physical Package Dimensions
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8.2
PLCC Package
D
PIN 1
IDENTIFIER & ZONE
D1
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
Legend:
28 (in Millimeters)
Symbol
A
Min
4.20
2.29
11.43
9.91
7.62 BSC
11.43
9.91
Max
4.57
3.04
11.58
10.92
SEATING PLANE
A1
D1
D2
D3
E1
E2
E3
e
.10
e
.51 MIN.
11.58
10.92
.53 / .33
R 1.14 / .64
7.62 BSC
1.27 BSC
D2 / E2
D
E
12.32
12.32
12.57
12.57
SIDE VIEW
Figure 4. PLCC Physical Package Dimensions
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IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
9.
Innovasic Part Number Cross-Reference
Table 11. Innovasic Part Number Cross-Reference for the PDIP
Innovasic Part Number
IA82050-PDW28I-R-01
lead free (RoHS-compliant) TP82050
Intel Part Number
P82050
Package Type
Temperature Grades
Industrial
28-Pin Plastic Dual In-Line
Package (PDIP) (600 mils)
Table 12. Innovasic Part Number Cross-Reference for the PLCC
Innovasic Part Number
IA82050-PLC28IR2
lead free (RoHS-compliant) TN82050
Intel Part Number
N82050
Package Type
Temperature Grades
Industrial
28-Lead Plastic Leaded
Chip Carrier (PLCC)
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IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
10. Revision History
The table below presents the sequence of revisions to document IA211030617.
Date
Revision
06
Description
Page(s)
NA
August 19, 2008
Corrected control number and reformatted some
elements to meet publication standards.
October 15, 2008
07
Corrected part number on cover page, enlarged
1, 5, 6,
package pinout and functional block diagram figures,
corrected trademark references (p. 2), changed “pin” to
“lead” in LCC package pinout figure, changed “lead” to
“pin” in PDIP physical page dimensions figure and part
number table, formatted part cross-reference table to
meet publication standards, added “For Additional
Information” chapter.
17, 18,
20
February 25, 2011
08
Removed packaging options to support the elimination
of SnPb lead plating options.
20
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IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
11. For Additional Information
The IA82050 is a "plug-and-play" drop-in replacement for the original IC. This data sheet
documents all necessary engineering information about the IA82050 including functional and
I/O descriptions, electrical characteristics and applicable timing.
The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to
understand. Please feel free to contact our experts at Innovasic at any time with suggestions,
comments, or questions.
Innovasic Support Team
3737 Princeton NE
Suite 130
Albuquerque, NM 87107
(505) 883-5263
Fax: (505) 883-5477
Toll Free: (888) 824-4184
E-mail: support@innovasic.com
Website: www.Innovasic.com
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