TN82510 [INNOVASIC]
ASYNCHRONOUS SERIAL CONTROLLER; 异步串行控制器
| 型号： | TN82510 |
| 厂家： | 
INNOVASIC, INC |
| 描述： | ASYNCHRONOUS SERIAL CONTROLLER |
| 文件： | 总14页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
FEATURES
·
Form, Fit, and Function Compatible with the Intel 82510
·
Packaging options available: 28 Pin Plastic or Ceramic DIP, 28 Pin Plastic
Leaded Chip Carrier, 28 Pin Ceramic Leadless Chip Carrier
·
·
·
·
Asynchronous Serial Channel Operation
Separate Transmit and Receive FIFOs with Programmable Threshold
Programmable Baud Rate Generators up to 288K Baud
Special Protocol Features
- Control Character Recognition
- Auto Echo and Loopback Modes
- 9-Bit Protocol Support
- 5 to 9 Bit Character Format
The IA82510 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs
using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces
replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC.
MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM
also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA82510 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
Package Pinout
D7 D6 D5 D4 D3 D2 D1
IA82510
28 Pin DIP
D4
(1)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
D3
D5
(2)
D2
D6
(3)
D1
(4) (3) (2) (1) (28) (27) (26)
D7
(4)
D0
INT
TXD
(5)
(6)
(7)
(8)
(9)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
D0
INT
TXD
(5)
A2
A2
(6)
A1
IA82510
VSS
A1
VSS
(7)
A0
X2 or OUT2n
X1 or CLK
A0
X2 or OUT2n
X1 or CLK
(8)
VDD
RDn
WRn
CSn
RESET
RTSn
DTRn or TB
28 Pin LCC
VDD
RDn
WRn
(9)
SCLK or RIn
DSRn or TA or OUT0n
(10)
(11)
SCLK or RIn
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
RXD
(10)
(11)
(12)
(13)
(14)
(12) (13) (14) (15) (16) (17) (18)
CTSn
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
DESCRIPTION
The IA82510 is an asynchronous serial controller that provides a CPU interface to one transmit
and one receive channel. It is Form, Fit, and Function compatible with the Intel 82510.
Configuration registers are used to control the serial channel, interrupts, and modes of operation.
The CPU controls this device via address and data lines with read/write control. The CPU also
uses this interface to read and write data to receive and transmit data through the serial channel.
FIFOs and various serial modes can be used to help off-load the CPU from transmitting and
receiving data. An interrupt line provides an indication to the CPU that the device requires
servicing. The device can be configured for 8250A/16450 compatibility.
Functional Block Diagram
IA82510
A(2:0)
TRANSMITTER
D(7:0)
RDn
TXD
BUS INTERFACE
(Reset Logic,
Registers,
Interrupt Generation,
WRn
CSn
INT
RESET
RECEIVER
RXD
CTSn
RTSn
TIMING
(Baud Rate
PIN
Generators A & B,
Clocking
CONFIGURATION
CONFIG., STATUS, RXDATA
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
DTRn or TB
MODEM
X1 or CLK
X2 or OUT2n
SCLK or RIn
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
Functional Overview
Transmitter
The Transmit function consists of a 4 ´ 11 bit FIFO, and a Transmit Engine. The 4 ´ 11 FIFO is
configurable as any depth between one and four words inclusive. The transmit engine is
responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin.
The transmit engine is highly configurable to be compatible with numerous formats, including
16450 and 8250 modes of communication. Transmit Communication parameters that can be
programmed include:
·
·
·
·
·
·
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
RTS and CTS modes
See the Register Description for more details.
Receiver
The Receiver function consists of a 4 ´ 11 configurable FIFO and a Receive Engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing
the data in the FIFO. The receive engine is highly configurable with parameters that include:
·
·
·
·
·
·
·
·
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
Address Matching Options
Control Character Detection
RTS and CTS modes
See the Register Description for more details.
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82510 Registers. It consists of the following I/O lines:
·
·
·
·
·
·
·
A0, A1, A2 :
D0-D7 :
RDn:
WRn:
CSn:
3 Bit Address
8 Bit Data
Active Low Read Enable
Active Low Write Enable
Active Low Chip Select
Interrupt Output
Chip Reset
INT:
RESET:
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
Register Description
Table 1 – IA82510 Register Summary
Register
ACR0
ACR1
BACF
BAH
ADDR
111
101
001
001
000
010
011
001
000
000
100
001
001
010
111
111
100
011
101
100
100
101
110
110
100
101
110
111
101
000
Bank
00
10
11
00
00
X
11
11
11
11
01
10
00
X
01
01
10
00
00
00
01
11
00
01
11
01
10
10
01
00
01
01
01
01
10
11
01
00
01
01
DLAB
X
X
0
1
1
X
X
1
1
0
Mode
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R
W
R/W
R/W
R/W
R/W
W
R/W
R/W
R
R/W
W
R/W
R/W
R
Default
00000000
00000000
00000100
00000000
00000010
00000000
10000100
00000000
00000101
00000000
00000000
00000000
00000000
00000001
00010010
N/A
BAL
BANK
BBCF
BBH
BBL
CLCF
FLR
FMD
GER
GIR_BANK
GSR
ICM
IMD
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
00001100
00000000
01100000
00000000
LCR
LSR
MCR
MIE
MSR
00001111
00000000
PMD
RCM
RIE
RMD
RST
RXDATA
11111100
N/A
00011110
00000000
00000000
Unknown
R
RXF
TCM
001
110
011
011
110
011
000
R
W
W
R/W
R/W
R
Unknown
N/A
N/A
00000000
00000000
00110000
N/A
TMCR
TMD
TMIE
TMST
TXDATA
W
X
X
TXF
001
W
N/A
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
AC/DC Parameters
Absolute maximum ratings:
Supply Voltage, VDD…………………………….…-0.3V to +6.0V
Input Voltage, VIN…………………………………-0.3V to VDD +0.3V
Input Pin Current, IIN…………………………….±10 mA, 25° C
Operating Temperature Range……………………..-40° C to +85°C
Ambient temperature under bias........................……..-40°C to +85°C *
Storage temperature.......................................…........….- 55°C to +150°C
Lead Temperature………………………………….+300°C, 10 sec.
Power dissipation..............................................................155 mW, 125°C, 25MHz, 15% Toggle
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Operating the device beyond the conditions
indicated in the “recommended operating conditions” section is not recommended. Operation at the “absolute maximum ratings” may adversely affect
device reliability.
*
The input and output parametric values in section VII-B, parts 1, 2, and 3, are directly related to ambient
temperature and DC supply voltage. A temperature or supply voltage range other than those specified in the
Operating Conditions above will affect these values and part performance is not guaranteed by innovASIC.
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
DC Characteristics
Symbol
VIL
Parameter
Input Low Voltage
Notes
(1)
Min
-0.5
2.1
Max
0.7
Unit
V
VIH1
VIH2
VOL
VOH
ILI
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
(1)
VDD+.07
VDD+.07
0.4
V
(2)
2.1
V
(2),(8)
(3),(8)
(4)
V
2.4
V
±1
mA
mA
ILO
(5)
±1
ICC
(6)
1.12
-137
100
1.92
mA/MHz
IPU
(12)
(9)
-283
N/A
mA
mA
mA
mA
pF
ISTBY
IOHR
IOLR
CIN
(10)
(11)
(7)
5
6
6
CIO
I/O Capacitance
(7)
pF
CXTAL
X1, X2 Load
pF
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @IOL = 1.92 mA
3. @IOH = 1.92 mA
4. 0< VIN <VCC
5. 0.4V < VOUT < VCC – 0.4V
6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not
Tested), Ext. 1X CLK, IOL = IOH = 0
7. Freq. = 1 MHz
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output
drive requirements and is measured with the clocks stopped and all inputs tied to VDD or
VSS, configured to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for
logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for
logic LOW.
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
AC Characteristics
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
Min
Max
Notes
Divide by Two
No Divide by
54 ns
54 ns
25 ns
25 ns
250 ns
108 ns
10 ns
10 ns
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
CLK Rise Time
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
CLK Fall Time
CLK Rise Time
15 ns
No Divide by
CLK Fall Time
15 ns
No Divide by
Crystal Frequency
Reset Width
RTS/DTR Low Setup
to Reset inactive
RTS/DTR Low Hold
after Reset inactive
1 Mhz
8 * Clock Period
6 * Clock Period
20 Mhz
Clock Period – 20 ns
2* clock period +
65 ns
7 ns
RDn Active Width
Address/CSn Setup
Time to RDn Active
Address/CSn Hold
after RDn Inactive
RDn or WRn Inactive
to Active Delay
0 ns
Clock Period +
15 ns
Data Out Float Delay
after RDn Inactive
40 ns
2 * Clock Period
+ 15 ns
7 ns
WRn Active Width
Address CSn Setup
Time to WRn Active
Address and CSn
hold Time after WRn
Data in Setup Time
to WRn Inactive
Data In Hold Time
after WRn Inactive
SCLK Period
0 ns
90 ns
12 ns
216 ns
3500 ns
250 ns
16x Clocking Mode
1x Clocking Mode
SCLK Period
RXD Setup Time to
SCLK High
RXD Hold Time after
SCLK High
250 ns
TXD Valid after SCLK
Low
TXD Delay after RXD
170 ns
170 ns
Remote Loopback
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
Packaging Information
PLCC Package
D
PIN 1
IDENTIFIER & ZONE
D1
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
LEAD COUNT
28 (in Millimeters)
MIN
4.20
2.29
11.43
9.91
MAX
4.57
SEATING PLANE
A
A1
D1
D2
D3
E1
E2
E3
e
3.04
11.58
10.92
.10
e
7.62 BSC
.51 MIN.
11.43
9.91
11.58
10.92
.53 / .33
R 1.14 / .64
7.62 BSC
1.27 BSC
12.32
12.32
D2 / E2
SIDE VIEW
D
12.57
12.57
E
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
PDIP Package
TOP
E1
E
LEAD 1
IDENTIFIER
eA
eB
C
1
LEAD COUNT
DIRECTION
SIDE VIEW (WIDTH)
Lead Count
28 (in Inches)
A
D
MIN
-
MAX
.200
-
A
A1
B
.015
.015
.050
.008
1.380
.580
.520
.020
.070
.012
1.470
.610
.560
A1
B1
C
L
D
E
B
B1
E1
e
e
.100 TYP
eA
eB
L
.580
-
-
SIDE VIEW (LENGTH)
.686
.100 MIN
B2
S
-
-
-
-
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
Ordering Information
The IA82510 may be ordered per the tables below.
Production Version -01
Order Number
IA82510-PDW28I-01
IA82510-PLC28I-01
Environment
Package Type
Industrial 28 Lead Plastic DIP, 600 mil wide
Industrial 28 Lead Plastic Leaded Chip Carrier
OEM Part Number Cross-Reference
The following table identifies which OEM Part Number is compatible with the corresponding
InnovASIC Part Number
innovASIC Part Number
IA82510-PLC28I
Intel Part Number
q
q
N82510
TN82510
IA82510-PDW28I
q
q
P82510
TP82510
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
ERRATA
PLEASE NOTE:
· When using the -01 version of the IA82510, please refer to the errata section,
"Production Version -01, Errata".
· When using the -00 version of the IA82510, please refer to the errata section,
"Production Version -00, Errata".
Production Version -01, Errata
The following errata are known problems with the -01 version of the IA82510. This is inclusive of
all package types and environment grades. A workaround to the identified problem has been
provided where possible. ALL ERRATA LISTED IN PRODUCTION VERION -00 HAVE
BEEN FIXED IN THIS VERSION OF THE DEVICE UNLESS OTHERWISE NOTED.
-00 Errata not fixed in this Production Version:
1. Problem: Device does not operate at 8 MHz in divide-by-one mode
Analysis: System testing revealed this operational deficiency.
Workaround: Switch to divide-by-two mode using 2X clock input
New Errata for Production Version -01:
2. Problem: RX FIFO locks up unexpectedly just after configuration and before starting
reception.
Analysis: An RCM command is executed with data of xB8. This is an “enable RX”, “flush RX
machine”, “flush RX FIFO”, and “lock RX FIFO” command done in a single instruction. The
“flush RX machine” should unlock the RX FIFO, creating a conflict with the simultaneous
“lock RX FIFO” command. The original Intel device apparently ignores or gives the “lock RX
FIFO” command lower priority in this case. The IA82510 has this priority reversed.
Apparently, the application software in this case expected the “lock RX FIFO” command to
fail.
Workaround: Do not execute a “flush RX FIFO” and “lock RX FIFO” command
simultaneously. Break up into separate RCM commands.
3. Problem: Unreliable transmits in AUTO TX mode.
Analysis: Many systems use the RTS output to activate the line transceiver. When the
Transmit Mode field in the TMD register is set to semi-auto or automatic mode, RTS is
controlled by the TX state machine. On the first character, RTS asserts at the same time as
the start bit on the TXD output, whereas the original Intel device asserts RTS a full bit time
before assertion of the start bit on TXD. At full temperature range, the width of the start bit
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
can be altered to the point of confusing the downstream receiver.
Workaround: Change firmware to Manual TX mode to control RTS vs. start of character.
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
Production Version -00, Errata
The following errata are known problems with the -00 version of the IA82510. This is inclusive of
all package types and environment grades. A workaround to the identified problem has been
provided where possible.
1. Problem: Scrambled data during boot code shuts down UART, however device works for
application code
Analysis: The RX FIFO is locked, configuration of all registers is done, then the RX FIFO is
unlocked just before entering loopback mode in both boot and application code before normal
operations begin. Boot code additionally does a blind block read of all registers before normal
operations including two reads from the unwritten RX Data FIFO. RX unlock command is
inadvertently incrementing the write pointer. For boot code, the two reads of RX data cause
the read/write pointers to be permanently out of sync. For application code, the pointers end
up synched to the same location, only because the code waits for four characters before
reading. This ends up causing an RX overrun, but to our favor because the pointers are now
synched.
Workaround: Execute a “Flush RX FIFO” command (via RCM register) after configuration
and block read is complete.
2. Problem: Device does not operate at 8 MHz in divide-by-one mode
Analysis: System testing revealed this operational deficiency.
Workaround: Switch to divide-by-two mode using 2X clock input
3. Problem: Setting CLCF to x30, which effectively generates the TX clock from the incoming
SCLK signal, kills all transmits.
Analysis: Configuration of PMD inadvertently set so RI function is selected instead of SCLK
function. Original Intel device allows SCLK through anyway, IA82510 suppresses it.
Workaround: Set correct configuration for PMD allows TX clock generation
4. Problem: Receiving streamed data has many framing errors and corrupt data when connected
to some modems.
Analysis: Shortened stop bit followed immediately by next start bit does not correctly detect
that start bit.
Workaround: Configure external modem to transmit two stop bits
5. Problem: Transmission of streamed data does not return interrupt.
Analysis: Stray read of GIR sets TX FIFO interrupt hold logic, but this logic does not reset
when GER[1] is de-asserted..
Workaround: Reset logic with write to TX data or avoid stray reads of GIR
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IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
6. Problem: Receiving streamed data has many framing errors at fast baud rates (divisor=6)
through bad modem lines.
Analysis: DPLL is not robust for RXD signal with more than 1/16 bit time of variation.
Workaround: None
7. Problem: Difficulty starting oscillator with crystal.
Analysis: No internal feedback resistor between X1 and X2.
Workaround: Install external 1-10Mohm resistor
8. Problem: Intermittent and temperature sensitive crystal oscillator operation when cycling
power.
Analysis: Strapping state elements apparently transparent latches instead of flip flops. If flip
flop powers up to wrong state, crystal oscillator is disabled while reset is active. OK after first
reset following power-up.
Workaround: None
9. Problem: Auto-acknowledge of interrupts via writing of LSR does not work.
Analysis: Writing LSR directly sets/resets bits 4 through 0. Also writing 0 to LSR(0) – RX
FIFO – clears the RX FIFO level as seen by FLR. Writing zero to any other LSR bits clears the
corresponding LSR/RST flag, but also corrupts the FIFO location the write pointer is set to,
then increments both the write and read pointers.
Workaround: Use other means to service interrupts, such as read of RST or RXD
10. Problem: ICM Status Clear command does not clear LSR/RST overrun error
Analysis: ICM Status Clear command should clear everything in RST/LSR, MSR, and TMST
except RST/LSR(0). Overrun error was missed.
Workaround: Use other means to service interrupts
11. Problem: In semi-automatic/uLAN mode, the RX FIFO is only opened when an address
character matches the ACR1 or ACR0 registers (like full auto mode).
Analysis: In semi-auto mode, the RX FIFO should open on any address character.
Workaround: None
12. Problem: Device fails to reset interrupt signal in auto acknowledge mode when character is
read from RX FIFO.
Analysis: RD strobe is outside the CS enable, which is outside of the Intel datasheet, but
apparently still works in the Intel device. Such a bus cycle allows the read data out, but fails to
generate the necessary internal strobe to change pointers. The same problem is found on write
accesses.
Workaround: Force bus interface to bracket RD strobe inside the CS enable
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相关型号：
TN8259A
8086; 8088; MCS-80; MCS-85 COMPATIBLE, INTERRUPT CONTROLLER, PQCC28, PLASTIC, LCC-28
ROCHESTER
TN8259A
Interrupt Controller, 8086; 8088; MCS-80; MCS-85 Compatible, NMOS, PQCC28, PLASTIC, LCC-28
INTEL
TN8259A-2
Interrupt Controller, 8086; 8088; MCS-80; MCS-85 Compatible, NMOS, PQCC28, PLASTIC, LCC-28
INTEL
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