IN74ACT573N

更新时间:2024-09-18 02:21:08
品牌:INTEGRAL
描述:OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH

IN74ACT573N 概述

OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH 八路三态同相透明锁存器 触发器/锁存器

IN74ACT573N 规格参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

IN74ACT573N 数据手册

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IN74ACT573  
OCTAL 3-STATE NONINVERTING  
TRANSPARENT LATCH  
High-Performance Silicon-Gate CMOS  
The IN74ACT573 is identical in pinout to the LS/ALS573,  
HC/HCT573. The IN74ACT573 may be used as a level converter  
for interfacing TTL or NMOS outputs to High Speed CMOS inputs.  
These latches appear transparent to data (i.e., the outputs  
change asynchronously) when Latch Enable is high. When Latch  
Enable goes low, data meeting the setup and hold time becomes  
latched.  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
ORDERING INFORMATION  
Outputs Source/Sink 24 mA  
IN74ACT573N Plastic  
IN74ACT573DW SOIC  
TA = -40° to 85° C for all  
packages  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
PIN 20=VCC  
PIN 10 = GND  
FUNCTION TABLE  
Inputs  
Latch  
Output  
Q
Output  
D
Enable Enable  
L
L
L
H
H
L
H
L
X
H
L
no  
change  
Z
H
X
X
X = don’t care  
Z = high impedance  
1
IN74ACT573  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +7.0  
-0.5 to VCC +0.5  
-0.5 to VCC +0.5  
±20  
Unit  
V
VCC  
VIN  
VOUT  
IIN  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
V
V
mA  
mA  
mA  
mW  
IOUT  
DC Output Sink/Source Current, per Pin  
DC Supply Current, VCC and GND Pins  
±50  
ICC  
PD  
±50  
750  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
500  
Tstg  
TL  
Storage Temperature  
-65 to +150  
°C  
°C  
Lead Temperature, 1 mm from Case for 10  
Seconds  
260  
(Plastic DIP or SOIC Package)  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min  
4.5  
0
Max  
5.5  
Unit  
V
DC Supply Voltage (Referenced to GND)  
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to  
GND)  
VCC  
V
TJ  
TA  
IOH  
IOL  
tr, tf  
Junction Temperature (PDIP)  
Operating Temperature, All Package Types  
Output Current - High  
140  
+85  
°C  
°C  
mA  
mA  
ns/V  
-40  
-24  
24  
Output Current - Low  
*
Input Rise and Fall Time  
(except Schmitt Inputs)  
VCC =4.5  
CC =5.5 V  
V
0
0
10  
V
8.0  
* VIN from 0.8 V to 2.0 V  
This device contains protection circuitry to guard against damage due to high static  
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage  
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and  
V
OUT should be constrained to the range GND(VIN or VOUT)VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or  
VCC). Unused outputs must be left open.  
2
IN74ACT573  
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)  
VCC  
Guaranteed  
Limits  
25 °C -40°C to  
85°C  
Symbol  
VIH  
Parameter  
Test Conditions  
V
Unit  
V
Minimum  
Level  
High- VOUT=0.1 V or VCC-0.1 V 4.5  
Input 5.5  
2.0  
2.0  
2.0  
2.0  
Voltage  
VIL  
Maximum Low - VOUT=0.1 V or VCC-0.1 V 4.5  
0.8  
0.8  
0.8  
0.8  
V
V
Level  
Input  
5.5  
Voltage  
Minimum  
Level  
VOH  
High-  
4.5  
5.5  
4.4  
5.4  
4.4  
5.4  
I
OUT -50 µA  
Output  
Voltage  
*VIN=VIH  
or  
or  
VIL  
IOH=-24  
mA 4.5  
5.5  
3.86  
4.86  
0.1  
3.76  
4.76  
0.1  
IOH=-24 mA  
OUT 50 µA  
VOL  
Maximum  
Level  
Low-  
4.5  
V
I
Output  
5.5  
0.1  
0.1  
Voltage  
*VIN=VIH  
IOL=24  
VIL  
mA 4.5  
5.5  
0.36  
0.36  
±0.1  
0.44  
0.44  
±1.0  
IOL=24 mA  
IIN  
Maximum Input VIN=VCC or GND  
Leakage Current  
Additional Max. VIN=VCC - 2.1 V  
ICC/Input  
5.5  
µA  
5.5  
1.5  
mA  
ICCT  
IOZ  
Maximum Three- VIN (OE)= VIH or VIL 5.5  
±0.5  
±5.0  
µA  
mA  
mA  
State  
Leakage VIN =VCC or GND  
Current  
V
V
OUT =VCC or GND  
OLD=1.65 V Max  
IOLD  
IOHD  
ICC  
+Minimum  
Dynamic Output  
Current  
5.5  
5.5  
5.5  
75  
+Minimum  
Dynamic Output  
Current  
V
OHD=3.85 V Min  
-75  
80  
Maximum  
VIN=VCC or GND  
8.0  
µA  
Quiescent Supply  
Current  
(per Package)  
* All outputs loaded; thresholds on input associated with output under test.  
+Maximum test duration 2.0 ms, one output loaded at a time.  
3
IN74ACT573  
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)  
Guaranteed Limits  
Symbol  
Parameter  
Unit  
25 °C  
-40°C to  
85°C  
Min Max Min  
Max  
12  
tPLH  
tPHL  
tPLH  
Propagation Delay, Input D to Q (Figure 1) 2.5 10.5 2.0  
Propagation Delay, Input D to Q (Figure 1) 2.5 10.5 2.0  
ns  
ns  
ns  
12  
Propagation Delay,Latch Enableto  
(Figure 2)  
Q
3.0 10.5 2.5  
12  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
CIN  
Propagation Delay,Latch Enableto  
(Figure 2)  
Q
2.5  
9.5  
10  
2.0  
1.5  
1.5  
1.5  
1.0  
10.5  
11  
ns  
ns  
ns  
ns  
ns  
pF  
Propagation Delay, Output Enable to Q 2.0  
(Figure 3)  
Propagation Delay, Output Enable to Q 1.5  
(Figure 3)  
9.5  
11  
10.5  
12.5  
9.5  
Propagation Delay, Output Enable to Q 2.5  
(Figure 3)  
Propagation Delay, Output Enable to Q 1.5  
(Figure 3)  
8.5  
Maximum Input Capacitance  
5.0  
5.0  
Typical @25°C,VCC=5.0 V  
CPD  
Power Dissipation Capacitance  
25  
pF  
TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)  
Guaranteed Limit  
Symbol  
tSU  
Parameter  
Unit  
ns  
25°C  
-40°C to 85°C  
Minimum Setup Time, Input D to Latch  
Enable (Figure 4)  
3.0  
3.5  
th  
Minimum Hold Time, Latch Enable to  
Input D (Figure 4)  
Minimum Pulse Width, Latch Enable  
(Figure 2)  
0
0
ns  
ns  
tw  
3.5  
4.0  
4
IN74ACT573  
Figure 1. Switching Waveforms  
Figure 2. Switching Waveforms  
Figure 3. Switching Waveforms  
Figure 4. Switching Waveforms  
EXPANDED LOGIC DIAGRAM  
5

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