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IN74HC174AD

更新时间：2024-09-18 02:21:08

品牌：INTEGRAL

描述：Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS

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规格参数
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IN74HC174AD 概述

Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS 六路D触发器与普通时钟和复位高性能硅栅CMOS 触发器/锁存器

IN74HC174AD 规格参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

IN74HC174AD 数据手册

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TECHNICAL DATA

IN74HC174A

Hex D Flip-Flop with

Common Clock and Reset

High-Performance Silicon-Gate CMOS

The IN74HC174A is identical in pinout to the LS/ALS174. The

device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device consists of six D flip-flops with common Clock and

Reset inputs. Each flip-flop is loaded with a low-to-high transition of

the Clock input. Reset is asynchronous and active-low.

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 mA

ORDERING INFORMATION

IN74HC174AN Plastic

IN74HC174AD SOIC

IZ74HC174A Chip

High Noise Immunity Characteristic of CMOS Devices

T_A= -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Output

Reset

PIN 16=V_CC

PIN 8 = GND

no change

X = Don’t care

L = LOW voltage level

H = HIGH voltage level

INTEGRAL

IN74HC174A

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +7.0

-1.5 to V_CC+1.5

-0.5 to V_CC+0.5

±20

Unit

V_CC

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

V_OUT

I_IN

I_OUT

I_CC

DC Output Current, per Pin

±25

DC Supply Current, V_CCand GND Pins

±50

P_D

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1,5 mm from Case for 4 Seconds

(Plastic DIP or SOIC Package)

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

Parameter

Min

2.0

Max

6.0

Unit

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

V , V_OUT

V_CC

T_A

-55

+125

°C

t_r, t_f

Input Rise and Fall Time (Figure 1)

V_CC=2.0 V

V_CC=4.5 V

V_CC=6.0 V

1000

500

400

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages

to this high-impedance circuit. For proper operation, V and V_OUTshould be constrained to the range GND£(V or

V_OUT)£V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused

outputs must be left open.

INTEGRAL

IN74HC174A

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

V_CC

Guaranteed Limit

Symbol

Parameter

Test Conditions

-55°C

£85

°C

£125

°C

Unit

25°C

Minimum High-Level

Input Voltage

V_OUT³ V_CC-0.1 V

or £0.1 V

êI_OUTê£ 20 mA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

Maximum Low -Level

Input Voltage

V_OUT£0.1 V

or ³ V_CC-0.1 V

êI_OUTê £ 20 mA

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V_OH

Minimum High-Level

Output Voltage

V =V or V

êI_OUTê £ 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V =V or V

êI_OUTê £ 4.0 mA

êI_OUTê £ 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

V_OL

Maximum Low-Level

Output Voltage

V = V or V

êI_OUTê £ 20 mA

2.0

4.5

6.0

0.1

V = V or V

êI_OUTê £ 4.0 mA

êI_OUTê £ 5.2 mA

4.5

6.0

0.26

0.33

0.4

I_IN

Maximum Input

Leakage Current

V =V_CCor GND

6.0

±0.1

±1.0

I_CC

Maximum Quiescent

Supply Current

(per Package)

V =V_CCor GND

6.0

4.0

160

I_OUT=0mA

INTEGRAL

IN74HC174A

AC ELECTRICAL CHARACTERISTICS(C_L=50pF, Input t_r=t_f=6.0 ns, V = 0 V, V =Vcc)

V_CC

Guaranteed Limit

Symbol

f_max

Parameter

-55°C

£85°C

£125°C

Unit

MHz

25°C

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

4.8

4.0

t_PLH, t_PHLMaximum Propagation Delay, Clock to Q (Figures

1 and 4)

2.0

4.5

6.0

110

140

165

t_PHL

Maximum Propagation Delay , Reset to Q

(Figures 2 and 4)

2.0

4.5

6.0

110

140

160

t_TLH, t_THLMaximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

110

C_IN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Enabled

Output)

Typical @25°C,V_CC=5.0 V

C_PD

Used to determine the no-load dynamic power

consumption: P_D=C_PDV_CC²f+I_CCV_CC

TIMING REQUIREMENTS (C_L=50pF,Input t_r=t_f=6.0 ns, V = 0 V, V =Vcc)

V_CC

Guaranteed Limit

Symbol

t_SU

Parameter

-55 °C to

25°C

£85°C

£125°C

Unit

Minimum Setup Time, Data to

Clock (Figure 3)

2.0

4.5

6.0

t_h

t_rec

t_w

Minimum Hold Time, Clock to

Data (Figure 3)

2.0

4.5

6.0

Minimum Recovery Time,

Reset Inactive to Clock (Figure

2.0

4.5

6.0

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

110

t_w

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

110

t_r,t_f

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

INTEGRAL

IN74HC174A

t_w

V_CC

RESET

50%

V_CC

90%

50%

10%

GND

CLOCK

t_PHL

GND

t_w

50%

1/f

max

t_PLH

t_PHL

t_rec

90%

50%

10%

V_CC

CLOCK

50%

GND

t_TLH

t_THL

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

TEST POINT

VALID

V_CC

DATA

50%

DEVICE

UNDER

TEST

OUTPUT

GND

t_su

t_h

V_CC

CLOCK

50%

GND

Figure 3. Switching Waveforms

Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

INTEGRAL

IN74HC174A

CHIP PAD DIAGRAM

Chip marking

1.6 + 0.03

Chip marking :15HC174

Location of marking (mm): left lower corner x = 0.110, y = 0.870; right lower corner x = 0.240, y = 0.900

Chip thickness: 0.46 ± 0.02 mm

PAD LOCATION

Pad No

Pad size, mm

Symbol

Location (left lower corner), mm

Reset

GND

Clock

Vcc

0.115

0.325

0.580

0.850

1.145

1.345

1.370

1.365

1.355

1.155

0.880

0.620

0.320

0.125

0.115

0.340

0.140

0.115

0.140

0.355

0.815

1.045

1.065

1.045

0.660

0.12´ 0.12

0.12´ 0.16

0.12´ 0.12

0.12´ 0.19

Note: Location is given as per passivation layer

INTEGRAL

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