IZ74LV240 [INTEGRAL]
OCTAL BUFFER/LINE DRIVE; 3-STATE; 八路缓冲器/线路驱动器; 3 -STATE型号: | IZ74LV240 |
厂家: | INTEGRAL CORP. |
描述: | OCTAL BUFFER/LINE DRIVE; 3-STATE |
文件: | 总5页 (文件大小:48K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TECHNICAL DATA
IN74LV240
OCTAL BUFFER/LINE DRIVE; 3-STATE
The IN74LV240 is a low-voltage Si-gate CMOS device and is pin and
function compatible with IN74HC/HCT240.
The IN74LV240 is an octal non-inverting buffer/line driver with 3-
state outputs. The 3-state outputs are controlled by the output enable
inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a
high impedance OFF-state.
N SUFFIX
PLASTIC DIP
20
1
DW SUFFIX
SO
The IN74LV240 is identical to the IN74LV244 but has inverting
outputs.
20
1
·
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 1.2 to 3.6 V
Low Input Current: 1.0 mA, 0.1 mÀ at Ò = 25 °Ñ
Output Current: 8 mA at VCC = 3.0 V
ORDERING INFORMATION
IN74LV240N
IN74LV240DW
IZ74LV240
Plastic DIP
SOIC
chip
High Noise Immunity Characteristic of CMOS Devices
TA = -40° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
2
18
16
14
12
9
1Y
1Y
1A
0
1
0
1OE
1
20
19
VCC
2OE
4
1A
1A0
2Y3
2
1
3
18 1Y0
17 2A3
16 1Y1
6
1Y
1Y
2Y
2Y
1A
1A
2
3
0
1
2
3
0
1
1A1
4
8
2Y2
5
INVERTING
OUTPUTS
DATA
INPUTS
1A2
6
15
2A2
11
13
15
17
2A
2A
2Y1
7
14 1Y2
13 2A1
12 1Y3
1A3
8
7
2Y0
9
5
2Y
2Y
2A
0
1
10
GND
11
2A0
0
3
2A
1
1
1OE
2OE
FUNCTION TABLE
OUTPUT
ENABLES
19
Input
Output
nOE
nAn
L
nYn
H
L
L
H
L
PIN 20=VCC
H
X
Z
PIN 10 = GND
H= high level
L = low level
X = don’t care
Z = high impedance
INTEGRAL
1
IN74LV240
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +5.0
±20
Unit
V
VCC
DC supply voltage
1
IIK
*
DC Input diode current
DC Output diode current
mA
mA
mA
mA
mA
mW
2
IOK
*
±50
IO *3
DC Output source or sink current
DC VCC current
±35
ICC
±70
IGND
PD
DC GND current
±70
Power dissipation per package: *4
Plastic DIP
SO
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*1 V < -0.5 V or V > VCC + 0.5 V.
I
I
*2 VO < -0.5 V or VO > VCC + 0.5 V.
*3 -0.5 V < VO < VCC + 0.5 V.
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.2
0
Max
3.6
Unit
V
VCC
DC Supply Voltage
Input Voltage
V
I
VCC
V
VO
TA
Output Voltage
0
VCC
V
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
-40
+125
°C
ns
tr, tf
VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
0
0
0
0
1000
700
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or
IN
IN
VOUT)£VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
INTEGRAL
2
IN74LV240
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Test
VCC
V
Guaranteed Limit
Symbol
Parameter
conditions
25°C
-40°C to 85°C
125°C
Unit
min max min
max
min
max
V
IH
HIGH level input
voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
V
V
LOW level input
voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
V
V
IL
VOH
HIGH level output V = V or V
IL
voltage
1.2
2.0
3.0
3.6
1.1
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
I
IH
IO = -50 mÀ
1.92
2.92
3.52
V = V or V
IL
3.0
2.48
-
2.34
-
2.20
-
V
V
I
IH
IO = -8 mÀ
LOW level output V = V or V
IL
VOL
1.2
2.0
3.0
3.6
-
-
-
-
0.09
0.09
0.09
0.09
-
-
-
-
0.1
0.1
0.1
0.1
-
-
-
-
0.1
0.1
0.1
0.1
I
IH
voltage
IO = 50 mÀ
V = V or V
IL
3.0
-
0.33
-
0.4
-
0.5
V
I
IH
IO = 8 mÀ
V = VCC or 0 V
II
Input current
*
-
-
±0.1
±0.5
-
-
±1.0
±5
-
-
±1.0
±10
mÀ
mÀ
I
IOZ
Three state leakage 3-state outputs
1.2
*
current
V (01,19) = V
I
IH
VO =VCC or 0 V
ICC
Supply current
V =VCC or 0 V
I
*
-
8.0
-
80
-
160
mÀ
IO = 0 mÀ
* VCC = 3.3 ± 0.3 V
INTEGRAL
3
IN74LV240
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns)
Test
VCC
V
Guaranteed Limit
Symbol
Parameter
conditions
25°C
-40°C to
85°C
125°C
Unit
min max min
max
min
max
tPHL, tPLH Propagation delay , 1An V = 0 V or VCC
1.2
2.0
*
-
-
-
100
24
15
-
-
-
125
30
19
-
-
-
150
36
23
ns
ns
ns
ns
I
to 1Yn, 2An to 2Yn
Figure 1 and 3
tPHZ tPLZ Propagation delay, 1OE to V = 0 V or VCC
1.2
2.0
*
-
-
-
140
30
20
-
-
-
175
35
24
-
-
-
210
41
28
I
1Yn, 2OE to 2Yn
Figure 2 and 4
tPZH tPZL Propagation delay, 1OE to V = 0 V or VCC
1.2
2.0
*
-
-
-
140
32
20
-
-
-
175
40
25
-
-
-
210
48
30
I
1Yn, 2OE to 2Yn
Figure 2 and 4
tTHL, tTLH Output Transition Time,
Any Output
V = 0 V or VCC
Figure 1 and 3
1.2
2.0
*
-
-
-
60
16
10
-
-
-
75
20
13
-
-
-
90
24
15
I
CI
Input capacitance
3.0
-
-
7.0
50
-
-
7.0
-
-
-
7.0
-
pF
pF
CPD
Power dissipation
capacitance (per one
channel)
V = 0 V or VCC
I
* VCC = 3.3 ± 0.3 V
VCC
t
t
f
r
50%
VCC
1OE or 2OE
90%
50%
1An or 2An
GND
10%
tPZL
tPLZ
GND
tPLH
tPHL
VCC
VOL
50%
50%
1Yn or 2Yn
1Ynor 2Yn
90%
1Ynor 2Yn
50%
10%
tPHZ
tPZH
VOH
GND
tTHL
tTLH
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
TEST POINT
TEST POINT
Connect to V when
CC
and t
PZL
DEVICE
UNDER
TEST
1 k
OUTPUT
testing t
OUTPUT
PLZ
DEVICE
UNDER
TEST
Connect to GND when
testing t and t
*
*
L
PHZ
PZH
C
C
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
INTEGRAL
4
IN74LV240
CHIP PAD DIAGRAM
Chip marking
ÊÁLV240
13
18
17
19
16 15
14
12
11
20
10
09
01
02
05
06
04
07 08
03
Y
(0,0)
X
1.9 + 0.03
Location of marking (mm): left lower corner x=1.539, y=1.433.
Chip thickness: 0.46 ± 0.02 mm.
PAD LOCATION
Location (left lower corner), mm
Pad No
Symbol
Pad size, mm
X
Y
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
1OE
1A0
0.115
0.55
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.108 x0.108
0.1075
0.3215
0.76
0.246
0.131
0.131
0.131
0.131
0.131
0.131
0.43
0.643
1.0855
1.266
1.4345
1.4345
1.4345
1.4345
1.4345
1.4345
1.1385
0.949
2Y
3
1A1
2Y
0.9285
1.2115
1.4615
1.674
1.674
1.685
1.674
1.6795
1.674
1.0525
0.7545
0.586
0.293
0.112
0.112
0.112
2
2A2
2Y
1
2A3
2Y
0
GND
2A0
1Y
3
2A1
1Y
2
2A2
1Y
1
2A3
1Y
0
2OE
VCC
Note: Pad location is given as per metallization layer
INTEGRAL
5
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