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Cyclone V Device Datasheet

2015.12.04

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This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Cyclone^®V

devices.

Cyclone V devices are offered in commercial and industrial grades. Commercial devices are offered in –C6 (fastest), –C7, and –C8 speed grades.

Industrial grade devices are offered in the –I7 speed grade. Automotive devices are offered in the –A7 speed grade.

Related Information

Cyclone V Device Overview

Provides more information about the densities and packages of devices in the Cyclone V family.

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Cyclone V devices.

Operating Conditions

Cyclone V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Cyclone

V devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Cyclone V devices. The values are based on experiments conducted with the devices

and theoretical modeling of breakdown and damage mechanisms.

The functional operation of the device is not implied for these conditions.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent

and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera

warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without

notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are

advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

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101 Innovation Drive, San Jose, CA 95134

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Absolute Maximum Ratings

Caution: Conditions outside the range listed in the following table may cause permanent damage tothe device. Additionally, device operation at

the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 1: Absolute Maximum Ratings for Cyclone V Devices

Symbol

Description

Minimum

–0.5

Maximum

1.43

Unit

V

V_CC

Core voltage and periphery circuitry power supply

Configuration pins power supply

Auxiliary supply

V_CCPGM

V_{CC_AUX}

V_CCBAT

–0.5

3.90

V

–0.5

3.25

V

Battery back-up power supply for design security volatile key

register

–0.5

3.90

V

V_CCPD

I/O pre-driver power supply

I/O power supply

–0.5

–25

3.90

3.25

1.50

3.80

1.43

3.90

3.25

40

V

V_CCIO

V_{CCA_FPLL}

V_{CCH_GXB}

V_{CCE_GXB}

V_{CCL_GXB}

V_I

Phase-locked loop (PLL) analog power supply

Transceiver high voltage power

Transceiver power

V

Transceiver clock network power

DC input voltage

V

V_{CC_HPS}

HPS core voltage and periphery circuitry power supply

HPS I/O pre-driver power supply

HPS I/O power supply

V

V_{CCPD_HPS}

V_{CCIO_HPS}

V_{CCRSTCLK_HPS}

V_{CCPLL_HPS}

V_{CC_AUX_SHARED}

I_OUT

V

HPS reset and clock input pins power supply

HPS PLL analog power supply

HPS auxiliary power supply

V

(1)

V

DC output current per pin

mA

(1)

V_{CC_AUX_SHARED}must be powered by the same source as V_{CC_AUX}for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6

devices.

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Maximum Allowed Overshoot and Undershoot Voltage

Symbol

Description

Minimum

–55

Maximum

125

Unit

°C

T_J

Operating junction temperature

Storage temperature (no bias)

T_STG

–65

150

°C

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than

100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to

100% duty cycle.

For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this

amounts to 1.5 years.

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Recommended Operating Conditions

Table 2: Maximum Allowed Overshoot During Transitions for Cyclone V Devices

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

Symbol

Description

Condition (V)

Overshoot Duration as % of High Time

Unit

%

3.8

100

68

45

28

15

13

11

9

3.85

3.9

3.95

4

4.05

4.1

4.15

4.2

Vi (AC)

AC input voltage

8

4.25

4.3

7

5.4

3.2

1.9

1.1

0.6

0.4

0.2

4.35

4.4

4.45

4.5

4.55

4.6

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Cyclone V devices.

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Recommended Operating Conditions

Table 3: Recommended Operating Conditions for Cyclone V Devices

This table lists the steady-state voltage values expected from Cyclone V devices. Power supply ramps must all be strictly monotonic, without plateaus.

Symbol

Description

Condition

Minimum⁽²⁾

Typical

Maximum⁽²⁾

Unit

Devices without

internal scrubbing

feature

1.07

1.1

1.13

V

Core voltage, periphery circuitry power

supply, transceiver physical coding

sublayer (PCS) power supply, and

transceiver PCI Express^®(PCIe^®) hard IP

digital power supply

V_CC

Devices with internal

scrubbing feature (with

SC suffix) ⁽³⁾

1.12

1.15

1.18

V

V_{CC_AUX}

Auxiliary supply

—

2.375

3.135

2.85

2.5

3.3

3.0

2.5

2.625

3.465

3.15

V

3.3 V

3.0 V

2.5 V

(4)

V_CCPD

I/O pre-driver power supply

2.375

2.625

(2)

(3)

(4)

The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.

Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device

availability and ordering, contact your local Altera sales representatives.

V_CCPDmust be 2.5 V when V_CCIOis 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. V_CCPDmust be 3.0 V when V_CCIOis 3.0 V. V_CCPDmust be 3.3 V when V_CCIOis

3.3 V.

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Recommended Operating Conditions

Symbol

Description

Condition

3.3 V

3.0 V

2.5 V

1.8 V

1.5 V

1.35 V

1.25 V

1.2 V

3.3 V

3.0 V

2.5 V

1.8 V

—

Minimum⁽²⁾

3.135

2.85

Typical

3.3

Maximum⁽²⁾

3.465

3.15

Unit

V

3.0

2.375

1.71

2.5

2.625

1.89

1.8

V_CCIO

I/O buffers power supply

1.425

1.283

1.19

1.5

1.575

1.418

1.31

1.35

1.25

1.2

1.14

1.26

3.135

2.85

3.3

3.465

3.15

3.0

V_CCPGM

Configuration pins power supply

2.375

1.71

2.5

2.625

1.89

1.8

(5)

V_{CCA_FPLL}

PLL analog voltage regulator power

supply

2.375

2.5

2.625

(6)

V_CCBAT

—

1.2

—

3.0

V

Battery back-up power supply

(For design security volatile key register)

V_I

DC input voltage

Output voltage

—

–0.5

0

—

3.6

V

V_O

VCCIO

(2)

The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.

Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

(5)

(6)

PLL digital voltage is regulated from V_{CCA_FPLL}

.

If you do not use the design security feature in Cyclone V devices, connect V_CCBATto a 1.5-V, 2.5-V, or 3.0-V power supply. Cyclone V power-on

reset (POR) circuitry monitors V_CCBAT. Cyclone V devices do not exit POR if V_CCBATis not powered up.

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Transceiver Power Supply Operating Conditions

Symbol

Description

Condition

Commercial

Industrial

Minimum⁽²⁾

0

Typical

—

Maximum⁽²⁾

85

Unit

°C

—

T_J

Operating junction temperature

–40

—

100

Automotive

Standard POR

Fast POR

–40

—

125

200µs

—

100ms

4ms

(7)

t_RAMP

Power supply ramp time

—

Transceiver Power Supply Operating Conditions

Table 4: Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices

Symbol

Description

Minimum⁽⁸⁾

2.375

Typical

2.5

Maximum⁽⁸⁾

Unit

V_{CCH_GXBL}

Transceiver high voltage power (left side)

Transmitter and receiver power (left side)

Clock network power (left side)

2.625

V

(9)(10)

V_{CCE_GXBL}

1.07/1.17

1.1/1.2

1.13/1.23

(9)(10)

V_{CCL_GXBL}

(2)

(7)

(8)

(9)

The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.

Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMPspecifications for standard POR when HPS_PORSEL = 0 and t_RAMP

specifications for fast POR when HPS_PORSEL = 1.

The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.

Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which

require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended

in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.

Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specifica‐

tion at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144Gbps ( Cyclone V GT and ST devices only). For more information about the

maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configura‐

tions in Cyclone V Devices chapter.

(10)

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HPS Power Supply Operating Conditions

Related Information

•

PCIe Supported Configurations and Placement Guidelines

Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full

compliance to the PCIe Gen2 transmit jitter specification.

•

6.144-Gbps Support Capability in Cyclone V GT Devices

Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.

HPS Power Supply Operating Conditions

Table 5: HPS Power Supply Operating Conditions for Cyclone V SX and ST Devices

This table lists the steady-state voltage and current values expected from Cyclone V system-on-a-chip (SoC) devices with ARM^®-based hard processor

system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Cyclone V Devices

table for the steady-state voltage values expected from the FPGA portion of the Cyclone V SoC devices.

Symbol

Description

Condition

Minimum⁽¹¹⁾

Typical

Maximum⁽¹¹⁾

Unit

V_{CC_HPS}

HPS core voltage and periphery circuitry

power supply

—

1.07

1.1

1.13

V

3.3 V

3.0 V

2.5 V

3.135

2.85

3.3

3.0

2.5

3.465

3.15

V

(12)

V_{CCPD_HPS}

HPS I/O pre-driver power supply

2.375

2.625

(11)

(12)

The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.

Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

V_{CCPD_HPS}must be 2.5 V when V_{CCIO_HPS}is 2.5, 1.8, 1.5, or 1.2 V. V_{CCPD_HPS}must be 3.0 V when V_{CCIO_HPS}is 3.0 V. V_{CCPD_HPS}must be 3.3 V

when V_{CCIO_HPS}is 3.3 V.

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HPS Power Supply Operating Conditions

Symbol

Description

Condition

3.3 V

3.0 V

2.5 V

1.8 V

1.5 V

1.35 V ⁽¹³⁾

1.2 V

3.3 V

3.0 V

2.5 V

1.8 V

—

Minimum⁽¹¹⁾

3.135

2.85

Typical

3.3

Maximum⁽¹¹⁾

3.465

3.15

Unit

V

3.0

V

2.375

1.71

2.5

2.625

1.89

V

V_{CCIO_HPS}

HPS I/O buffers power supply

1.8

V

1.425

1.283

1.14

1.5

1.575

1.418

1.26

V

1.35

1.2

V

3.135

2.85

3.3

3.465

3.15

V

3.0

V

HPS reset and clock input pins power

supply

V_{CCRSTCLK_HPS}

2.375

1.71

2.5

2.625

1.89

V

1.8

V

V_{CCPLL_HPS}

HPS PLL analog voltage regulator power

supply

2.375

2.5

2.625

V

V_{CC_AUX_}

HPS auxiliary power supply

—

2.375

2.5

2.625

V

(14)

SHARED

Related Information

Recommended Operating Conditions on page 5

Provides the steady-state voltage values for the FPGA portion of the device.

(11)

The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.

Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

V_{CCIO_HPS}1.35 V is supported for HPS row I/O bank only.

V_{CC_AUX_SHARED}must be powered by the same source as V_{CC_AUX}for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6

devices.

(13)

(14)

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DC Characteristics

Supply Current and Power Consumption

Altera offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Quartus^®Prime PowerPlay Power

Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the

device power because these currents vary greatly with the resources you use.

The Quartus Prime PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-

route. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when

combined with detailed circuit models, yields very accurate power estimates.

Related Information

•

PowerPlay Early Power Estimator User Guide

Provides more information about power estimation tools.

PowerPlay Power Analysis chapter, Quartus Prime Handbook

Provides more information about power estimation tools.

•

I/O Pin Leakage Current

Table 6: I/O Pin Leakage Current for Cyclone V Devices

Symbol

Description

Condition

V_I= 0 V to V_CCIOMAX

V_O= 0 V to V_CCIOMAX

Min

–30

Typ

—

Max

30

Unit

µA

I_I

Input pin

Tri-stated I/O pin

I_OZ

—

30

µA

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Bus Hold Specifications

Table 7: Bus Hold Parameters for Cyclone V Devices

The bus-hold trip points are based on calculated input voltages from the JEDEC standard.

V_CCIO(V)

Parameter

Symbol Condition

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Bus-hold,

low,

I_SUSL

I_SUSH

I_ODL

8

—

12

—

30

—

50

—

70

—

70

—

µA

V

_IN> V_IL

(max)

sustaining

current

Bus-hold,

high,

–8

—

125

–125

0.9

–12

—

–30

—

–50

—

300

–300

1.7

–70

—

500

–500

2

–70

—

500

–500

2

µA

V

V_IN< V_IH

(min)

sustaining

current

Bus-hold,

low,

0 V < V_IN

< V_CCIO

175

200

–200

1.07

overdrive

current

Bus-hold,

high,

I_ODH

0 V <V_IN

<V_CCIO

—

–175

—

overdrive

current

Bus-hold

trip point

V_TRIP

—

0.3

0.375 1.125

0.68

0.7

0.8

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration

block.

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OCT Calibration Accuracy Specifications

Table 8: OCT Calibration Accuracy Specifications for Cyclone V Devices

Calibration accuracy for the calibrated on-chip series termination (R_SOCT) and on-chip parallel termination (R_TOCT) are applicable at the moment of

calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

Calibration Accuracy

Symbol

Description

Condition (V)

Unit

–C6

–I7, –C7

–C8, –A7

25-Ω R_S

Internal series termination with V_CCIO= 3.0, 2.5, 1.8, 1.5,

calibration (25-Ω setting) 1.2

15

%

50-Ω R_S

Internal series termination with V_CCIO= 3.0, 2.5, 1.8, 1.5,

calibration (50-Ω setting) 1.2

15

%

34-Ω and 40-Ω R_S

Internal series termination with V_CCIO= 1.5, 1.35, 1.25,

calibration (34-Ω and 40-Ω

setting)

1.2

48-Ω, 60-Ω, and 80- Internal series termination with V_CCIO= 1.2

15

%

Ω R_S

calibration (48-Ω, 60-Ω, and

80-Ω setting)

50-Ω R_T

Internal parallel termination

with calibration (50-Ω setting)

V_CCIO= 2.5, 1.8, 1.5, 1.2

V_CCIO= 1.5, 1.35, 1.25

–10 to +40

%

20-Ω, 30-Ω, 40-Ω,60- Internal parallel termination

Ω, and 120-Ω R_T

with calibration (20-Ω, 30-Ω,

40-Ω, 60-Ω, and 120-Ω setting)

60-Ω and 120-Ω R_TInternal parallel termination

with calibration (60-Ω and 120-

Ω setting)

V_CCIO= 1.2

–10 to +40

15

–10 to +40

15

–10 to +40

15

%

25-Ω R_{S_left_shift}

Internal left shift series

V_CCIO= 3.0, 2.5, 1.8, 1.5,

1.2

termination with calibration

(25-Ω R_{S_left_shift}setting)

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OCT Without Calibration Resistance Tolerance Specifications

Table 9: OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices

This table lists the Cyclone V OCT without calibration resistance tolerance to PVT changes.

ResistanceTolerance

Symbol

Description

Condition (V)

Unit

–C6

–I7, –C7

–C8, –A7

25-Ω R_S

Internal series termination without V_CCIO= 3.0, 2.5

calibration (25-Ω setting)

30

40

%

25-Ω R_S

50-Ω R_S

100-Ω R_D

Internal series termination without V_CCIO= 1.8, 1.5

calibration (25-Ω setting)

30

35

30

35

25

40

50

40

50

40

50

40

50

40

%

Internal series termination without V_CCIO= 1.2

calibration (25-Ω setting)

Internal series termination without V_CCIO= 3.0, 2.5

calibration (50-Ω setting)

Internal series termination without V_CCIO= 1.8, 1.5

calibration (50-Ω setting)

Internal series termination without V_CCIO= 1.2

calibration (50-Ω setting)

Internal differential termination

(100-Ω setting)

V_CCIO= 2.5

Figure 1: Equation for OCT Variation Without Recalibration

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OCT Variation after Power-Up Calibration

The definitions for the equation are as follows:

•

The R_OCTvalue calculated shows the range of OCT resistance with the variation of temperature and V_CCIO

R_SCALis the OCT resistance value at power-up.

.

ΔT is the variation of temperature with respect to the temperature at power up.

ΔV is the variation of voltage with respect to the V_CCIOat power up.

dR/dT is the percentage change of R_SCALwith temperature.

dR/dV is the percentage change of R_SCALwith voltage.

OCT Variation after Power-Up Calibration

Table 10: OCT Variation after Power-Up Calibration for Cyclone V Devices

This table lists OCT variation with temperature and voltage after power-up calibration. The OCT variation is valid for a V_CCIOrange of 5% and a

temperature range of 0°C to 85°C.

Symbol

Description

V_CCIO(V)

Value

0.100

0.150

0.189

0.208

0.266

0.273

0.200

0.317

Unit

3.0

2.5

1.8

dR/dV

OCT variation with voltage without recalibration

1.5

%/mV

1.35

1.25

1.2

3.0

2.5

1.8

OCT variation with temperature without

recalibration

dR/dT

1.5

%/°C

1.35

1.25

1.2

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Pin Capacitance

Table 11: Pin Capacitance for Cyclone V Devices

Symbol

Description

Value

Unit

pF

C_IOTB

C_IOLR

Input capacitance on top and bottom I/O pins

6

Input capacitance on left and right I/O pins

pF

C_OUTFB

Input capacitance on dual-purpose clock output and feedback pins

pF

Hot Socketing

Table 12: Hot Socketing Specifications for Cyclone V Devices

Symbol

Description

Maximum

300

Unit

μA

I_{IOPIN (DC)}

DC current per I/O pin

I_{IOPIN (AC)}

AC current per I/O pin

8⁽¹⁵⁾

mA

I_{XCVR-TX (DC)}

I_{XCVR-RX (DC)}

DC current per transceiver transmitter (TX) pin

DC current per transceiver receiver (RX) pin

100

50

Internal Weak Pull-Up Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.

(15)

The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew

rate.

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I/O Standard Specifications

Table 13: Internal Weak Pull-Up Resistor Values for Cyclone V Devices

Symbol

Description

Condition (V)⁽¹⁶⁾

Value⁽¹⁷⁾

25

Unit

kΩ

V_CCIO= 3.3 5%

V_CCIO= 3.0 5%

V_CCIO= 2.5 5%

V_CCIO= 1.8 5%

V_CCIO= 1.5 5%

V_CCIO= 1.35 5%

V_CCIO= 1.25 5%

V_CCIO= 1.2 5%

25

Value of the I/O pin pull-up resistor before and during

configuration, as well as user mode if you have enabled the

programmable pull-up resistor option.

25

R_PU

25

Related Information

Cyclone V Device Family Pin Connection Guidelines

Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.

I/O Standard Specifications

Tables in this section list the input voltage (V_IHand V_IL), output voltage (V_OHand V_OL), and current drive characteristics (I_OHand I_OL) for various

I/O standards supported by Cyclone V devices.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

(16)

(17)

Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO

Valid with 10% tolerances to cover changes over PVT.

.

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Single-Ended I/O Standards

Table 14: Single-Ended I/O Standards for Cyclone V Devices

V_CCIO(V)

Typ

V_IL(V)

V_IH(V)

V_OL(V)

Max

V_OH(V)

(18)

I_OL

I/O Standard

I_OH⁽¹⁸⁾(mA)

(mA)

Min

Max

Min

Max

Min

Max

Min

3.3-V

3.135

3.3

3.465

–0.3

0.8

1.7

3.6

0.45

2.4

4

–4

LVTTL

3.3-V

3.135

2.85

3.3

3

3.465

3.15

–0.3

0.8

1.7

3.6

0.2

0.4

0.2

V_CCIO– 0.2

2.4

2

–2

LVCMOS

3.0-V

LVTTL

3.0-V

3

V_CCIO– 0.2

0.1

–0.1

LVCMOS

3.0-V PCI

2.85

3

3.15

—

0.3 × V_CCIO0.5 × V_CCIOV_CCIO+ 0.3 0.1 × V_CCIO0.9 × V_CCIO

0.35 × V_CCIO0.5 × V_CCIOV_CCIO+ 0.3 0.1 × V_CCIO0.9 × V_CCIO

1.5

–0.5

3.0-V

PCI-X

2.5 V

1.8 V

1.5 V

1.2 V

2.375

1.71

2.5

1.8

1.5

1.2

2.625

1.89

–0.3

0.7

1.7

3.6

0.4

2

1

2

–1

–2

0.35 × V_CCIO0.65 × V_CCIOV_CCIO+ 0.3

0.45

V_CCIO– 0.45

1.425

1.14

1.575

1.26

0.35 × V_CCIO0.65 × V_CCIOV_CCIO+ 0.3 0.25 × V_CCIO0.75 × V_CCIO

(18)

To meet the I_OLand I_OHspecifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification

(4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the I_OLand I_OHspecifications in the

datasheet.

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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 15: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Cyclone V Devices

V_CCIO(V)

Typ

V_REF(V)

Typ

V_TT(V)

Typ

I/O Standard

Min

Max

Min

Max

Min

Max

SSTL-2

2.375

2.5

2.625

0.49 × V_CCIO

0.5 × V_CCIO

0.51 × V_CCIO

V_REF– 0.04

V_REF

V_REF+ 0.04

Class I, II

SSTL-18

1.71

1.425

1.283

1.19

1.8

1.5

1.89

1.575

1.418

1.26

1.89

1.575

1.26

1.3

0.833

0.9

0.969

V_REF– 0.04

V_REF

V_REF+ 0.04

Class I, II

SSTL-15

0.49 × V_CCIO

0.85

0.5 × V_CCIO

0.9

0.51 × V_CCIO0.49 × V_CCIO

0.5 × V_CCIO

V_CCIO/2

—

0.51 × V_CCIO

Class I, II

SSTL-135

Class I, II

1.35

1.25

1.8

0.51 × V_CCIO

SSTL-125

Class I, II

0.51 × V_CCIO

HSTL-18

Class I, II

1.71

0.95

0.9

—

HSTL-15

Class I, II

1.425

1.14

1.5

0.68

0.75

HSTL-12

Class I, II

1.2

0.47 × V_CCIO

0.49 × V_CCIO

0.5 × V_CCIO

0.53 × V_CCIO

0.51 × V_CCIO

HSUL-12

1.14

1.2

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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 16: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices

V_IL(DC)(V)

Max

V_IH(DC)(V)

V_IL(AC)(V)

Max

V_IH(AC)(V)

Min

V_OL(V)

Max

V_OH(V)

Min

(19)

I_OL

I/O Standard

I_OH⁽¹⁹⁾(mA)

(mA)

Min

Max

SSTL-2

Class I

–0.3

V_REF– 0.15 V_REF+ 0.15 V_CCIO+ 0.3 V_REF– 0.31 V_REF+ 0.31 V_TT– 0.608 V_TT+ 0.608

V_REF– 0.15 V_REF+ 0.15 V_CCIO+ 0.3 V_REF– 0.31 V_REF+ 0.31 V_TT– 0.81 V_TT+ 0.81

V_REF– 0.125 V_REF+ 0.125 V_CCIO+ 0.3 V_REF– 0.25 V_REF+ 0.25 V_TT– 0.603 V_TT+ 0.603

V_REF– 0.125 V_REF+ 0.125 V_CCIO+ 0.3 V_REF– 0.25 V_REF+ 0.25 0.28 V_CCIO– 0.28

8.1

–8.1

SSTL-2

Class II

–0.3

—

16.2

6.7

13.4

8

–16.2

–6.7

–13.4

–8

SSTL-18

Class I

SSTL-18

Class II

SSTL-15

Class I

V_REF– 0.1

V_REF+ 0.1

—

V_REF– 0.175 V_REF+ 0.175 0.2 × V_CCIO0.8 × V_CCIO

SSTL-15

Class II

—

16

–16

SSTL-135

SSTL-125

—

V_REF– 0.09 V_REF+ 0.09

V_REF– 0.85 V_REF+ 0.85

—

V_REF– 0.16 V_REF+ 0.16 0.2 × V_CCIO0.8 × V_CCIO

V_REF– 0.15 V_REF+ 0.15 0.2 × V_CCIO0.8 × V_CCIO

—

8

—

–8

HSTL-18

Class I

V_REF– 0.1

V_REF+ 0.1

V_REF– 0.2

V_REF+ 0.2

0.4

V_CCIO– 0.4

HSTL-18

Class II

—

16

8

–16

–8

HSTL-15

Class I

(19)

To meet the I_OLand I_OHspecifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8

mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OLand I_OHspecifications in the

datasheet.

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Differential SSTL I/O Standards

V_IL(DC)(V)

V_IH(DC)(V)

V_IL(AC)(V)

Max

V_IH(AC)(V)

Min

V_OL(V)

Max

V_OH(V)

Min

(19)

I_OL

I/O Standard

I_OH⁽¹⁹⁾(mA)

(mA)

Min

Max

Min

Max

HSTL-15

Class II

—

V_REF– 0.1

V_REF+ 0.1

—

V_REF– 0.2

V_REF+ 0.2

0.4

V_CCIO– 0.4

16

–16

HSTL-12

Class I

–0.15

—

V_REF– 0.08 V_REF+ 0.08 V_CCIO+ 0.15 V_REF– 0.15 V_REF+ 0.15 0.25 × V_CCIO0.75 × V_CCIO

8

–8

–16

—

HSTL-12

Class II

16

—

HSUL-12

V_REF– 0.13 V_REF+ 0.13

—

V_REF– 0.22 V_REF+ 0.22 0.1 × V_CCIO0.9 × V_CCIO

Differential SSTL I/O Standards

Table 17: Differential SSTL I/O Standards for Cyclone V Devices

V_CCIO(V)

Typ

V_SWING(DC)(V)

V_X(AC)(V)

V_SWING(AC)(V)

I/O Standard

Min

Max

Min

Max

Min

Typ

Max

Min

Max

SSTL-2

2.375

2.5

2.625

0.3

0.25

0.2

V_CCIO+ 0.6

V_CCIO/2 –

0.2

—

V_CCIO/2 +

0.2

0.62

V_CCIO+ 0.6

Class I, II

SSTL-18

1.71

1.425

1.283

1.8

1.5

1.89

1.575

1.45

V_CCIO+ 0.6

V_CCIO/2 –

0.175

—

V_CCIO/2 +

0.175

0.5

V_CCIO+ 0.6

2(V_IL(AC)– V_REF

2(V_IL(AC)– V_REF)

Class I, II

(20)

SSTL-15

V_CCIO/2 –

0.15

V_CCIO/2 +

0.15

2(V_IH(AC)

–

)

Class I, II

V_REF)

(20)

SSTL-135

1.35

0.18

V_CCIO/2 –

0.15

V_CCIO/2

V_CCIO/2 +

0.15

2(V_IH(AC)

V_REF

)

(19)

To meet the I_OLand I_OHspecifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8

mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OLand I_OHspecifications in the

datasheet.

The maximum value for V_SWING(DC)is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC)

and V_IL(DC)).

(20)

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Differential HSTL and HSUL I/O Standards

V_SWING(AC)(V)

V_CCIO(V)

Typ

V_SWING(DC)(V)

V_X(AC)(V)

Typ

I/O Standard

Min

Max

Min

Max

Min

Max

Min

Max

(20)

SSTL-125

1.19

1.25

1.31

0.18

V_CCIO/2 –

0.15

V_CCIO/2

V_CCIO/2 +

0.15

2(V_IH(AC)

–

2(V_IL(AC)– V_REF)

V_REF

)

Differential HSTL and HSUL I/O Standards

Table 18: Differential HSTL and HSUL I/O Standards for Cyclone V Devices

V_CCIO(V)

Typ

V_DIF(DC)(V)

V_X(AC)(V)

Typ

V_CM(DC)(V)

V_DIF(AC)(V)

I/O Standard

Min

Max

Min

Max

Min

Max

Min

Typ

Max

Min

Max

HSTL-18 1.71

Class I, II

1.8

1.89

0.2

—

0.78

—

1.12

0.9

—

0.78

—

1.12

0.4

—

HSTL-15 1.425

Class I, II

1.5

1.2

1.575

1.26

1.3

0.2

—

0.68

—

0.68

—

0.9

0.4

0.3

—

HSTL-12 1.14

Class I, II

0.16

0.26

V_CCIO

0.3

+

0.5 ×

0.4 ×

0.5 ×

0.6 ×

V_CCIO+ 0.48

0.44

V_CCIO

HSUL-12 1.14

0.26

0.5 ×

V_CCIO

0.12

0.5 ×

V_CCIO

0.12

0.4 ×

0.5 ×

0.6 ×

0.44

–

V_CCIO

+

V_CCIO

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Differential I/O Standard Specifications

Table 19: Differential I/O Standard Specifications for Cyclone V Devices

Differential inputs are powered by V_CCPDwhich requires 2.5 V.

V_CCIO(V)

V_ID(mV)⁽²¹⁾

V_ICM(DC)(V)

Condition

V_OD(V)⁽²²⁾

Typ

V_OCM(V)^(22)(23)

Min Typ Max

I/O Standard

Min

Typ

Max

Min

Condition

Max

Min

Max

Min

Max

PCML

Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver,

and reference clock I/O pin specifications, refer to Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices table.

0.05

1.05

—

D_MAX

≤

1.80

1.55

—

700 Mbps

2.5 V

V_CM

=

2.375

2.5

2.625

100

—

0.247

—

0.6

1.125 1.25

1.375

LVDS⁽²⁴⁾

1.25 V

D_MAX

>

700 Mbps

—

BLVDS⁽²⁵⁾

2.375

2.5

2.625

100

200

—

0.2

—

0.6

—

0.5

1

—

1.2

—

1.4

(26)

RSDS

V_CM

=

0.25

0.300

—

1.45

0.1

(HIO)⁽²⁷⁾

1.25 V

—

Mini-LVDS 2.375

(HIO)⁽²⁸⁾

600

1.425 0.25

(21)

(22)

(23)

(24)

The minimum V_IDvalue is applicable over the entire common mode range, V_CM

R_Lrange: 90 ≤ R_L≤ 110 Ω.

.

This applies to default pre-emphasis setting only.

For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to

1.85 V for data rate below 700 Mbps.

(25)

(26)

There are no fixed V_ICM, V_OD, and V_OCMspecifications for BLVDS. They depend on the system topology.

For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interface in Supported Altera

Device Families.

(27)

(28)

For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.

For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.

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Switching Characteristics

V_OCM(V)^(22)(23)

V_CCIO(V)

Typ

V_ID(mV)⁽²¹⁾

Condition

V_ICM(DC)(V)

Condition

V_OD(V)⁽²²⁾

Typ

I/O Standard

Min

—

Max

Min

Max

Min

Max

Min

Max

Min

Typ

Max

0.60

D_MAX

≤

1.80

700 Mbps

LVPECL⁽²⁹⁾

SLVS

—

300

—

1.00

0.05

D_MAX

>

1.60

1.80

700 Mbps

—

2.375

2.5

2.625

100

V_CM

=

—

1.25 V

Sub-LVDS 2.375

HiSpi 2.375

V_CM

=

—

1.25 V

V_CM

=

1.25 V

Related Information

•

AN522: Implementing Bus LVDS Interface in Supported Altera Device Families

Provides more information about BLVDS interface support in Altera devices.

•

Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices on page 24

Provides the specifications for transmitter, receiver, and reference clock I/O pin.

Switching Characteristics

This section provides performance characteristics of Cyclone V core and periphery blocks.

(21)

The minimum V_IDvalue is applicable over the entire common mode range, V_CM

R_Lrange: 90 ≤ R_L≤ 110 Ω.

.

(22)

(23)

(29)

This applies to default pre-emphasis setting only.

For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45

V to 1.95 V for data rate below 700 Mbps.

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Transceiver Performance Specifications

Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Table 20: Reference Clock Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Min Typ Max

Transceiver Speed Grade 6

Min Typ Max

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Supported I/O

standards

1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL⁽³¹⁾, HCSL, and LVDS

Input frequency

from REFCLK input

pins⁽³²⁾

—

27

—

550

400

27

—

550

400

27

—

550

400

MHz

ps

Rise time

Fall time

Duty cycle

Measure at 60

mV of differential

signal⁽³³⁾

Measure at 60

mV of differential

signal⁽³³⁾

ps

—

45

—

55

45

—

55

45

—

55

%

Peak-to-peak

differential input

voltage

200

2000

200

2000

200

2000

mV

Spread-spectrum

modulating clock

frequency

PCIe

30

—

33

30

—

33

30

—

33

kHz

(30)

Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.

(31)

(32)

Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.

The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information

about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.

REFCLK performance requires to meet transmitter REFCLK phase noise specification.

(33)

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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Spread-spectrum

downspread

PCIe

—

0 to –

0.5%

—

0 to –

0.5%

—

0 to –

0.5%

—

On-chip termina‐

tion resistors

—

100

—

100

—

100

—

Ω

V_ICM(AC coupled)

V_{CCE_GXBL}supply^(34)(35)

V_{CCE_GXBL}supply

V

V_ICM(DC coupled) HCSL I/O standard

for the PCIe

250

—

550

250

—

550

250

—

550

mV

reference clock

10 Hz

—

–50

–80

—

–50

–80

—

–50

–80

dBc/Hz

Ω

100 Hz

1 KHz

10 KHz

100 KHz

≥1 MHz

—

–110

–120

–130

—

–110

–120

–130

—

–110

–120

–130

—

Transmitter REFCLK

phase noise⁽³⁶⁾

R_REF

2000

1%

2000

1%

2000

1%

(30)

Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.

(34)

Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which

require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended

in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.

Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter

specification at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144 Gbps ( Cyclone V GT and ST devices only). For more information about the

maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol

Configurations in Cyclone V Devices chapter.

(35)

(36)

The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10^-12

.

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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Table 21: Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

fixedclk clock

PCIe Receiver

Detect

—

125

—

125

—

125

—

MHz

frequency

Transceiver Reconfi‐

guration Controller

IP (mgmt_clk_clk)

clock frequency

—

75

—

100/

75

—

100/

75

—

100/

MHz

125⁽³⁷⁾

Table 22: Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Min Typ Max

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Supported I/O

standards

1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS

Data rate⁽³⁸⁾

—

614

—

5000/

614

—

3125

1.2

—

614

—

2500

1.2

—

Mbps

V

6144⁽³⁵⁾

Absolute V_MAXfor a

receiver pin⁽³⁹⁾

1.2

—

Absolute V_MINfor a

receiver pin

–0.4

—

–0.4

—

–0.4

—

V

Maximum peak-to-

peak differential

1.6

V

input voltage V_ID

(diff p-p) before

device configuration

(37)

The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.

To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.

The device cannot tolerate prolonged operation at this absolute maximum.

(38)

(39)

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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Maximum peak-to-

peak differential

input voltage V_ID

(diff p-p) after

—

2.2

—

2.2

—

2.2

V

device configuration

Minimum differen‐

tial eye opening at

the receiver serial

input pins⁽⁴⁰⁾

—

110

—

110

—

110

—

mV

85-Ω setting

100-Ω setting

120-Ω setting

150-Ω setting

—

85

—

85

—

85

—

Ω

V

100

120

150

100

120

150

100

120

150

Differential on-chip

termination resistors

2.5 V PCML,

LVPECL, and

LVDS

V_{CCE_GXBL}supply^(34)(35)

V_{CCE_GXBL}supply

V_ICM(AC coupled)

1.5 V PCML

0.65⁽⁴¹⁾/0.8

V

µs

(42)

t_LTR

—

10

4

—

10

4

—

10

4

(43)

t_LTD

(44)

t_{LTD_manual}

4

(40)

The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable

the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

The AC coupled V_ICMis 650 mV for PCIe mode only.

t_LTRis the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset.

t_LTDis time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

t_{LTD_manual}is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is

functioning in the manual mode.

(41)

(42)

(43)

(44)

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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

(45)

t_{LTR_LTD_manual}

—

15

—

15

—

15

—

µs

Programmable ppm

detector⁽⁴⁶⁾

62.5, 100, 125, 200, 250, 300, 500, and 1000

ppm

Run length

—

200 200

—

200

UI

dB

Programmable

equalization AC and

DC gain

Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC

Gain for Cyclone V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25

Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices

diagrams.

AC gain setting =

0 to 3 ⁽⁴⁷⁾

DC gain setting =

0 to 1

Table 23: Transmitter Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Supported I/O

standards

1.5 V PCML

Data rate

—

614

—

5000/

614

—

3125

614

—

2500

Mbps

6144⁽³⁵⁾

V_OCM(AC coupled)

—

650

85

—

650

85

—

650

85

—

mV

Ω

85-Ω setting

100-Ω setting

120-Ω setting

150-Ω setting

100

120

150

100

120

150

100

120

150

Ω

Differential on-chip

termination resistors

Ω

(45)

t_{LTR_LTD_manual}is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the

CDR is functioning in the manual mode.

(46)

(47)

The rate matcher supports only up to 300 parts per million (ppm).

The Quartus Prime software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.

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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Intra-differential

pair skew

TX V_CM= 0.65 V

and slew rate of 15

ps

—

15

—

15

—

15

ps

Intra-transceiver

block transmitter

channel-to-channel

skew

×6 PMA bonded

mode

—

180

500

—

180

500

—

180

500

ps

Inter-transceiver

block transmitter

channel-to-channel

skew

×N PMA bonded

mode

Table 24: CMU PLL Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Supported data

range

—

614

—

5000/

614

—

3125

614

—

2500

Mbps

6144⁽³⁵⁾

fPLL supported data

range

—

614

—

3125

614

—

3125

614

—

2500

Mbps

Table 25: Transceiver-FPGA Fabric Interface Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Speed Grade 5⁽³⁰⁾

Transceiver Speed Grade 6

Transceiver Speed Grade 7

Symbol/Description

Condition

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Interface speed

—

25

—

187.5

25

—

187.5

25

—

163.84

MHz

(single-width mode)

Interface speed

(double-width

mode)

—

25

—

163.84

25

—

163.84

25

—

156.25

MHz

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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Related Information

•

CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 31

CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 32

PCIe Supported Configurations and Placement Guidelines

Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full

compliance to the PCIe Gen2 transmit jitter specification.

•

6.144-Gbps Support Capability in Cyclone V GT Devices

Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.

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CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC...

CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain

Figure 2: Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V

GX, GT, SX, and ST Devices

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CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC...

CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain

Figure 3: CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices

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Typical TX VOD Setting for Cyclone V Transceiver Channels with...

Typical TX V_ODSetting for Cyclone V Transceiver Channels with termination of 100 Ω

Table 26: Typical TX V_ODSetting for Cyclone V Transceiver Channels with termination of 100 Ω

Symbol

V_ODSetting⁽⁴⁸⁾

V_ODValue (mV)

120

V_ODSetting⁽⁴⁸⁾

V_ODValue (mV)

680

6⁽⁴⁹⁾

7⁽⁴⁹⁾

8⁽⁴⁹⁾

9

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

140

700

160

720

180

740

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

200

760

220

780

240

800

260

820

280

840

V_ODdifferential peak-to-peak

typical

300

860

320

880

340

900

360

920

380

940

400

960

420

980

440

1000

1020

1040

460

480

(48)

Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls.

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Transmitter Pre-Emphasis Levels

Symbol

V_ODSetting⁽⁴⁸⁾

V_ODValue (mV)

V_ODSetting⁽⁴⁸⁾

V_ODValue (mV)

1060

25

26

27

28

29

30

31

32

33

500

520

540

560

580

600

620

640

660

53

54

55

56

57

58

59

60

1080

1100

1120

1140

1160

1180

1200

Transmitter Pre-Emphasis Levels

The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions:

•

Low-frequency data pattern—five 1s and five 0s

Data rate—2.5 Gbps

The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the pre-emphasis levels may change

with data pattern and data rate.

Cyclone V devices only support 1st post tap pre-emphasis with the following conditions:

•

The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = V_ODsetting with termination value, R_TERM= 100 Ω and |C| = 1st

post tap pre-emphasis setting.

•

|B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps.

(V_MAX/V_MIN– 1)% < 600%, where V_MAX= |B| + |C| and V_MIN= |B| – |C|.

(48)

(49)

Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls.

Only valid for data rates ≤ 5 Gbps.

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Transmitter Pre-Emphasis Levels

Exception for PCIe Gen2 design:

•

V_ODsetting = 50 and pre-emphasis setting = 22 are allowed for PCIe Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp =

1’b0) using Altera PCIe Hard IP and PIPE IP cores.

•

V_ODsetting = 50 and pre-emphasis setting = 12 are allowed for PCIe Gen2 design with transmit de-emphasis –3.5dB setting (pipe_txdeemp =

1’b1) using Altera PCIe Hard IP and PIPE IP cores.

For example, when V_OD= 800 mV, the corresponding V_ODvalue setting is 40. The following conditions show that the 1st post tap pre-emphasis

setting = 2 is valid:

•

|B| + |C| ≤ 60→ 40 + 2 = 42

|B| – |C| > 5→ 40 – 2 = 38

(V_MAX/V_MIN– 1)% < 600%→ (42/38 – 1)% = 10.52%

To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Cyclone V HSSI HSPICE models.

Table 27: Transmitter Pre-Emphasis Levels for Cyclone V Devices

Quartus Prime 1st

Post Tap Pre-

Emphasis Setting

Quartus Prime V_ODSetting

Unit

10 (200 mV)

20 (400 mV)

30 (600 mV)

35 (700 mV)

40 (800 mV)

45 (900 mV) 50 (1000 mV)

0

1

0

dB

1.97

3.58

5.35

7.27

—

0.88

1.67

2.48

3.31

4.19

5.08

5.99

6.92

7.92

9.04

10.2

0.43

0.95

1.49

2

0.32

0.76

1.2

0.24

0.61

1

0.19

0.5

0.13

0.41

0.69

0.96

1.26

1.56

1.87

2.11

2.46

2.77

—

2

3

0.83

1.14

1.49

1.83

2.18

2.48

2.87

3.23

3.61

4

1.63

2.1

1.36

1.76

2.17

2.58

2.93

3.38

3.79

4.23

5

2.55

3.11

3.71

4.22

4.86

5.46

6.09

6

—

2.56

3.06

3.47

4

7

—

8

—

9

—

10

11

—

4.51

5.01

—

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Transmitter Pre-Emphasis Levels

Quartus Prime 1st

Post Tap Pre-

Emphasis Setting

Quartus Prime V_ODSetting

Unit

10 (200 mV)

20 (400 mV)

30 (600 mV)

35 (700 mV)

40 (800 mV)

45 (900 mV) 50 (1000 mV)

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

—

11.56

12.9

14.44

—

6.74

7.44

8.12

8.87

9.56

10.43

11.23

12.18

13.17

14.2

15.38

—

5.51

6.1

4.68

5.12

5.57

6.06

6.49

7.02

7.52

8.02

8.59

—

3.97

4.36

4.76

5.14

—

dB

6.64

7.21

7.73

8.39

9.03

9.7

—

10.34

11.1

11.87

12.67

13.48

14.37

—

Related Information

SPICE Models for Altera Devices

Provides the Cyclone V HSSI HSPICE models.

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Transceiver Compliance Specification

The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Cyclone V GX, GT, SX,

and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Altera Sales Representa‐

tive.

Table 28: Transceiver Compliance Specification for All Supported Protocol for Cyclone V GX, GT, SX, and ST Devices

Protocol

Sub-protocol

PCIe Gen1

Data Rate (Mbps)

2,500

PCIe

PCIe Gen2⁽⁵⁰⁾

5,000

PCIe Cable

2,500

XAUI

XAUI 2135

3,125

SRIO 1250 SR

SRIO 1250 LR

SRIO 2500 SR

SRIO 2500 LR

SRIO 3125 SR

SRIO 3125 LR

SRIO 5000 SR

SRIO 5000 MR

SRIO 5000 LR

1,250

2,500

Serial RapidIO^®(SRIO)

3,125

5,000

(50)

For PCIe Gen2 sub-protocol, Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for Cyclone V GT and

ST FPGA systems which ensure full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex

channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V

Devices chapter.

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Transceiver Compliance Specification

Protocol

Sub-protocol

CPRI E6LV

Data Rate (Mbps)

614.4

CPRI E6HV

CPRI E6LVII

CPRI E12LV

CPRI E12HV

CPRI E12LVII

CPRI E24LV

CPRI E24LVII

CPRI E30LV

CPRI E30LVII

CPRI E48LVII⁽⁵¹⁾

CPRI E60LVII⁽⁵¹⁾

GbE 1250

614.4

1,228.8

2,457.6

3,072

Common Public Radio Interface (CPRI)

3,072

4,915.2

6,144

Gbps Ethernet (GbE)

OBSAI

1,250

OBSAI 768

768

OBSAI 1536

OBSAI 3072

SDI 270 SD

1,536

3,072

270

Serial digital interface (SDI)

VbyOne

SDI 1485 HD

SDI 2970 3G

VbyOne 3750

1,485

2,970

3,750

(51)

For CPRI E48LVII and E60LVII, Altera recommends increasing the V_{CCE_GXBL}and V_{CCL_GXBL}typical value from 1.1 V to 1.2 V for full compliance

to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144 Gbps ( Cyclone V GT and ST devices only). For more

information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver

Protocol Configurations in Cyclone V Devices chapter.

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Core Performance Specifications

Protocol

Sub-protocol

Data Rate (Mbps)

HiGig+

HIGIG 3750

3,750

Related Information

•

PCIe Supported Configurations and Placement Guidelines

Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full

compliance to the PCIe Gen2 transmit jitter specification.

•

6.144-Gbps Support Capability in Cyclone V GT Devices

Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.

Core Performance Specifications

Clock Tree Specifications

Table 29: Clock Tree Specifications for Cyclone V Devices

Performance

–C7, –I7

550

Parameter

Unit

–C6

–C8, –A7

460

Global clock and Regional clock

Peripheral clock

550

155

MHz

155

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PLL Specifications

Table 30: PLL Specifications for Cyclone V Devices

This table lists the Cyclone V PLL block specifications. Cyclone V PLL block does not include HPS PLL.

Symbol

Parameter

Condition

Min

Typ

—

Max

Unit

–C6 speed grade

5

670⁽⁵²⁾

622⁽⁵²⁾

MHz

–C7, –I7 speed

grades

5

—

f_IN

Input clock frequency

–C8, –A7 speed

grades

5

—

500⁽⁵²⁾

325

MHz

%

f_INPFD

Integer input clock frequency to the

phase frequency detector (PFD)

—

f_FINPFD

Fractional input clock frequency to the

PFD

—

50

600

40

—

160

–C6, –C7, –I7 speed

grades

1600

1300

60

PLL voltage-controlled oscillator

(VCO) operating range

(53)

f_VCO

–C8, –A7 speed

grades

t_EINDUTY

Input clock or external feedback clock

input duty cycle

—

–C6, –C7, –I7 speed

grades

550⁽⁵⁴⁾

460⁽⁵⁴⁾

MHz

Output frequency for internal global or

regional clock

f_OUT

–C8, –A7 speed

grades

(52)

(53)

(54)

This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O

standard.

The VCO frequency reported by the Quartus Prime software takes into consideration the VCO post-scale counter K value. Therefore, if the counter K

has a value of 2, the frequency reported can be lower than the f_VCOspecification.

This specification is limited by the lower of the two: I/O f_MAXor F_OUTof the PLL.

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PLL Specifications

Max Unit

Symbol

Parameter

Condition

Min

Typ

–C6, –C7, –I7 speed

grades

—

667⁽⁵⁴⁾

533⁽⁵⁴⁾

55

MHz

%

Output frequency for external clock

output

f_{OUT_EXT}

–C8, –A7 speed

grades

—

45

—

50

—

t_OUTDUTY

t_FCOMP

t_DYCONFIGCLK

t_LOCK

Duty cycle for external clock output

(when set to 50%)

—

External feedback clock compensation

time

10

ns

Dynamic configuration clock for mgmt_

clk and scanclk

100

1

MHz

ms

Time required to lock from end-of-

device configuration or deassertion of

areset

t_DLOCK

Time required to lock dynamically

(after switchover or reconfiguring any

non-post-scale counters/delays)

—

1

ms

Low

Medium

High⁽⁵⁵⁾

—

10

0.3

1.5

4

—

50

—

MHz

ps

f_CLBW

PLL closed-loop bandwidth

Accuracy of PLL phase shift

t_{PLL_PSERR}

t_ARESET

—

Minimum pulse width on the areset

—

ns

signal

F_REF≥ 100 MHz

F_REF< 100 MHz

—

0.15

750

UI (p-p)

ps (p-p)

(56)(57)

t_INCCJ

Input clock cycle-to-cycle jitter

(55)

High bandwidth PLL settings are not supported in external feedback mode.

(56)

A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120

ps.

(57)

F_REFis f_IN/N, specification applies when N = 1.

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PLL Specifications

Symbol

Parameter

Condition

Min

—

Typ

—

Max

Unit

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

300

ps (p-p)

Period jitter for dedicated clock output

in integer PLL

(58)

t_{OUTPJ_DC}

30

mUI (p-p)

ps (p-p)

425⁽⁶¹⁾, 300⁽⁵⁹⁾

42.5⁽⁶¹⁾, 30⁽⁵⁹⁾

Period jitter for dedicated clock output

in fractional PLL

(58)

t_{FOUTPJ_DC}

mUI (p-p)

ps (p-p)

300

Cycle-to-cycle jitter for dedicated clock

output in integer PLL

t_{OUTCCJ_DC}

30

mUI (p-p)

ps (p-p)

425⁽⁶¹⁾, 300⁽⁵⁹⁾

42.5⁽⁶¹⁾, 30⁽⁵⁹⁾

Cycle-to-cycle jitter for dedicated clock

output in fractional PLL

(58)

t_{FOUTCCJ_DC}

mUI (p-p)

ps (p-p)

650

65

Period jitter for clock output on a

regular I/O in integer PLL

(58)(60)

t_{OUTPJ_IO}

mUI (p-p)

ps (p-p)

650

65

Period jitter for clock output on a

regular I/O in fractional PLL

(58)(60)(61)

t_{FOUTPJ_IO}

mUI (p-p)

ps (p-p)

650

65

Cycle-to-cycle jitter for clock output on

regular I/O in integer PLL

(58)(60)

t_{OUTCCJ_IO}

mUI (p-p)

ps (p-p)

650

65

Cycle-to-cycle jitter for clock output on

regular I/O in fractional PLL

(58)(60)(61)

t_{FOUTCCJ_IO}

mUI (p-p)

ps (p-p)

300

30

Period jitter for dedicated clock output

in cascaded PLLs

(58)(62)

t_{CASC_OUTPJ_DC}

mUI (p-p)

(58)

Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the

intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different

measurement method and are available in Memory Output Clock Jitter Specification for Cyclone V Devices table.

(59)

(60)

This specification only covers fractional PLL for low bandwidth. The f_VCOfor fractional value range 0.20–0.80 must be ≥ 1200 MHz.

External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter

Specification for Cyclone V Devices table.

This specification only covers fractional PLL for low bandwidth. The f_VCOfor fractional value range 0.05–0.95 must be ≥ 1000 MHz.

(61)

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PLL Specifications

Symbol

Parameter

Condition

Min

Typ

Max

Unit

t_DRIFT

Frequency drift after PFDENA is disabled

—

10

%

for a duration of 100 µs

dK_BIT

Bit number of Delta Sigma Modulator

(DSM)

—

8

24

32

Bits

k_VALUE

f_RES

Numerator of fraction

—

128

8388608

5.96

2147483648

0.023

—

Resolution of VCO frequency

f_INPFD= 100 MHz

390625

Hz

Related Information

Memory Output Clock Jitter Specifications on page 50

Provides more information about the external memory interface clock output jitter specifications.

(62)

The cascaded PLL specification is only applicable with the following conditions:

•

Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz

Downstream PLL: Downstream PLL BW > 2 MHz

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DSP Block Performance Specifications

Table 31: DSP Block Performance Specifications for Cyclone V Devices

Performance

–C7, –I7

300

Mode

Unit

–C6

340

287

250

310

–C8, –A7

260

Independent 9 × 9 multiplication

Independent 18 × 19 multiplication

Independent 18 × 18 multiplication

MHz

250

200

250

200

Independent 27 × 27 multiplication

Modes using One

200

160

Independent 18 × 25 multiplication

Independent 20 × 24 multiplication

Two 18 × 19 multiplier adder mode

250

200

DSP Block

250

200

250

200

18 × 18 multiplier added summed with 36-

bit input

250

200

Modes using Two

DSP Blocks

Complex 18 × 19 multiplication

310

250

200

MHz

Memory Block Performance Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL

and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX

.

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Periphery Performance

Table 32: Memory Block Performance Specifications for Cyclone V Devices

Resources Used

Performance

–C7, –I7

350

Memory

Mode

Unit

ALUTs

Memory

–C6

420

340

–C8, –A7

Single port, all supported widths

0

1

300

240

MHz

Simple dual-port, all supported widths

350

MLAB

Simple dual-port with read and write at

the same address

290

ROM, all supported width

0

1

420

315

275

350

275

240

300

240

180

MHz

Single-port, all supported widths

Simple dual-port, all supported widths

Simple dual-port with the read-during-

write option set to Old Data, all

supported widths

M10K

Block

True dual port, all supported widths

ROM, all supported widths

0

1

315

275

240

MHz

Periphery Performance

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/

IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

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High-Speed I/O Specifications

Table 33: High-Speed I/O Specifications for Cyclone V Devices

When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.

For LVDS applications, you must use the PLLs in integer PLL mode. This is achieved by using the LVDS clock network.

The Cyclone V devices support the following output standards using true LVDS output buffer types on all I/O banks.

•

True RSDS output standard with data rates of up to 360 Mbps

True mini-LVDS output standard with data rates of up to 400 Mbps

–C6

Typ

—

–C7, –I7

Typ

–C8, –A7

Typ

Symbol

Condition

Unit

Min

Max

Min

Max

Min

Max

f_{HSCLK_in}(input clock frequency) True

Differential I/O Standards

Clock boost

factor W = 1

to 40⁽⁶³⁾

5

437.5

5

—

420

5

—

320

MHz

f_{HSCLK_in}(input clock frequency) Single-

Ended I/O Standards

Clock boost

factor W = 1

to 40⁽⁶³⁾

5

—

320

5

—

320

5

—

275

MHz

f_{HSCLK_OUT}(output clock frequency)

—

5

(65)

—

420

840

5

(65)

—

370

740

5

(65)

—

320

640

MHz

SERDES

factor J =4 to

10⁽⁶⁴⁾

Mbps

True Differential I/O

Transmitter

Standards - f_HSDR(data rate)

(63)

(64)

Clock boost factor (W) is the ratio between the input data rate and the input clock rate.

The F_maxspecification is based on the fast clock used for serial data. The interface F_maxis also dependent on the parallel clock domain which is design

dependent and requires timing analysis.

(65)

The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or

local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.

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High-Speed I/O Specifications

–C8, –A7

–C6

Typ

—

–C7, –I7

Typ

Symbol

Condition

Unit

Min

Max

Min

Max

Min

Typ

Max

(65)

(66)

(65)

(66)

(65)

(66)

SERDES

factor J = 1 to

2, uses DDR

registers

—

Mbps

(65)

Emulated Differential I/O

Standards with Three

SERDES

factor J = 4 to

10

—

640

—

640

—

550

Mbps

External Output Resistor

Networks- f_HSDR(data rate)

(67)

(65)

Emulated Differential I/O

Standards with One

SERDES

factor J = 4 to

10

—

170

350

—

170

380

—

170

500

Mbps

ps

External Output Resistor

Network - f_HSDR(data rate)

Total Jitterfor

Data Rate, 600

Mbps – 840

Mbps

—

t_{x Jitter}-True Differential I/O

Standards⁽⁶⁷⁾

Total Jitter for

Data Rate <

600Mbps

—

0.21

500

—

0.23

500

—

0.30

500

UI

ps

t_{x Jitter}-Emulated

Differential I/O

Total Jitter for

Data Rate <

640Mbps

Standards with Three

External Output Resistor

Networks

(66)

The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (f_out), provided you can close the design timing and the signal

integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the

board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,

transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

(67)

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High-Speed I/O Specifications

Symbol

–C6

Typ

—

–C7, –I7

Typ

–C8, –A7

Typ

Condition

Unit

Min

Max

Min

Max

Min

Max

t_{x Jitter}-Emulated

Differential I/O

Total Jitter for

Data Rate <

640Mbps

—

0.15

—

0.15

—

0.15

UI

Standards with One

External Output Resistor

Network

t_DUTY

TX output

clock duty

45

50

55

45

50

55

45

50

55

%

cycle for both

True and

Emulated

Differential I/

O Standards

True

—

200

250

—

200

250

—

200

300

ps

Differential I/

O Standards

Emulated

Differential I/

O Standards

with Three

External

Output

t_RISEand t_FALL

Resistor

Networks

Emulated

Differential I/

O Standards

with One

External

—

300

—

300

—

300

ps

Output

Resistor

Network

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High-Speed I/O Specifications

–C8, –A7

–C6

Typ

—

–C7, –I7

Typ

Symbol

Condition

Unit

Min

Max

Min

Max

Min

Typ

Max

True

—

200

—

250

—

250

ps

Differential I/

O Standards

Emulated

Differential I/

O Standards

with Three

External

—

300

—

300

—

300

ps

Output

TCCS

Resistor

Networks

Emulated

Differential I/

O Standards

with One

External

—

300

—

300

Output

Resistor

Network

(65)

SERDES

factor J =4 to

10⁽⁶⁴⁾

—

875⁽⁶⁷⁾

—

840⁽⁶⁷⁾

—

640⁽⁶⁷⁾

Mbps

(66)

Receiver

f_HSDR(data rate)

SERDES

factor J = 1 to

2, uses DDR

registers

Sampling Window

—

350

—

350

—

350

ps

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DLL Frequency Range Specifications

Table 34: DLL Frequency Range Specifications for Cyclone V Devices

Parameter

–C6

–C7, –I7

–C8

Unit

DLL operating frequency range

167 – 400

167 – 333

MHz

DQS Logic Block Specifications

Table 35: DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Cyclone V Devices

This error specification is the absolute maximum and minimum error.

Number of DQS Delay Buffer

–C6

–C7, –I7

–C8

Unit

2

40

80

ps

Memory Output Clock Jitter Specifications

Table 36: Memory Output Clock Jitter Specifications for Cyclone V Devices

The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.

The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10^–12, equivalent to 14 sigma.

Altera recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.

–C6

–C7, –I7

–C8

Parameter

Clock Network

Symbol

Unit

Min

–60

—

Max

60

Min

–70

—

Max

70

Min

–70

—

Max

70

Clock period jitter

PHYCLK

t_JIT(per)

t_JIT(cc)

ps

Cycle-to-cycle period jitter

90

100

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OCT Calibration Block Specifications

Table 37: OCT Calibration Block Specifications for Cyclone V Devices

Symbol

OCTUSRCLK

T_OCTCAL

Description

Min

—

Typ

—

Max

20

Unit

Clock required by OCT calibration blocks

MHz

Cycles

Number of OCTUSRCLK clock cycles required for R_S

—

1000

—

OCT/R_TOCT calibration

T_OCTSHIFT

T_{RS_RT}

Number of OCTUSRCLK clock cycles required for OCT

—

32

—

Cycles

ns

code to shift out

Time required between the dyn_term_ctrl and oe

signal transitions in a bidirectional I/O buffer to

dynamically switch between R_SOCT and R_TOCT

2.5

Figure 4: Timing Diagram for oe and dyn_term_ctrl Signals

Tristate

TX

Tristate

RX

oe

dyn_term_ctrl

T_{RS_RT}

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Duty Cycle Distortion (DCD) Specifications

Table 38: Worst-Case DCD on Cyclone V I/O Pins

The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD.

–C6

–C7, –I7

–C8, –A7

Symbol

Unit

Min

Max

Min

Max

Min

Max

Output Duty Cycle

45

55

45

55

45

55

%

HPS Specifications

This section provides HPS specifications and timing for Cyclone V devices.

For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of

HPS_CLK1.

HPS Clock Performance

Table 39: HPS Clock Performance for Cyclone V Devices

Symbol/Description

mpu_base_clk (microprocessor unit clock)

main_base_clk (L3/L4 interconnect clock)

h2f_user0_clk

–C6

–C7, –I7

800

–A7

700

350

100

160

–C8

600

300

100

160

Unit

925

400

100

200

MHz

400

100

h2f_user1_clk

100

h2f_user2_clk

200

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HPS PLL Specifications

HPS PLL VCO Frequency Range

Table 40: HPS PLL VCO Frequency Range for Cyclone V Devices

Description

Speed Grade

–C7, –I7, –A7, –C8

–C6

Minimum

320

Maximum

1,600

Unit

MHz

VCO range

320

1,850

HPS PLL Input Clock Range

The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.

Related Information

Clock Select, Booting and Configuration chapter

Provides more information about the clock range for different values of clock select (CSEL).

HPS PLL Input Jitter

Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value

programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the

denominator is 1 to 64.

Maximum input jitter = Input clock period × Divide value (N) × 0.02

Table 41: Examples of Maximum Input Jitter

Input Reference Clock Period

Divide Value (N)

Maximum Jitter

Unit

ns

40 ns

1

2

4

0.8

1.6

3.2

ns

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Quad SPI Flash Timing Characteristics

Table 42: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices

Symbol

Description

Min

—

Typ

—

Max

108

—

Unit

MHz

ns

F_clk

SCLK_OUT clock frequency (External clock)

T_{qspi_clk}

QSPI_CLK clock period (Internal reference

clock)

2.32

—

T_dutycycle

T_dssfrst

SCLK_OUT duty cycle

45

—

55

—

%

Output delay QSPI_SS valid before first clock

edge

1/2 cycle of

SCLK_OUT

ns

T_dsslst

Output delay QSPI_SS valid after last clock

edge

–1

—

1

ns

T_dio

I/O data output delay

Input data valid start

–1

—

1

ns

T_{din_start}

(2 + R_delay) ×

T_{qspi_clk}– 7.52 ⁽⁶⁸⁾

T_{din_end}

Input data valid end

(2 + R_delay) ×

—

ns

T_{qspi_clk}– 1.21 ⁽⁶⁸⁾

(68)

R_delayis set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Altera provides automatic Quad

SPI calibration in the preloader. For more information about R_delay, refer to the Quad SPI Flash Controller chapter in the Cyclone V Hard Processor

System Technical Reference Manual.

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SPI Timing Characteristics

Figure 5: Quad SPI Flash Timing Diagram

This timing diagram illustrates clock polarity mode 0 and clock phase mode 0.

T_dsslst

QSPI_SS

SCLK_OUT

QSPI_DATA

T_dssfrst

T_dio

T_{din_start}

Data Out

Data In

T_{din_end}

Related Information

Quad SPI Flash Controller Chapter, Cyclone V Hard Processor System Technical Reference Manual

Provides more information about Rdelay.

SPI Timing Characteristics

Table 43: SPI Master Timing Requirements for Cyclone V Devices

The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.

Symbol

Description

Min

16.67

45

Max

—

Unit

ns

%

T_clk

CLK clock period

T_dutycycle

T_dssfrst

T_dsslst

SPI_CLK duty cycle

55

—

Output delay SPI_SS valid before first clock edge

Output delay SPI_SS valid after last clock edge

Master-out slave-in (MOSI) output delay

8

ns

8

—

T_dio

–1

1

T_dinmax

Maximum data input delay from falling edge of SPI_CLK to data

arrival at SoC. The RX sample delay register can be programmed to

control the capture of input data.

—

500

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SPI Timing Characteristics

Figure 6: SPI Master Timing Diagram

T_dsslst

SPI_SS

T_dssfrst

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

T_dio

SPI_MOSI (scph = 1)

SPI_MISO (scph = 1)

T_dinmax

T_dio

SPI_MOSI (scph = 0)

SPI_MISO (scph = 0)

T_dinmax

Table 44: SPI Slave Timing Requirements for Cyclone V Devices

The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.

Symbol

Description

Min

20

5

Max

—

6

Unit

ns

T_clk

T_s

CLK clock period

MOSI Setup time

MOSI Hold time

ns

T_h

5

ns

T_suss

T_hss

T_d

Setup time SPI_SS valid before first clock edge

Hold time SPI_SS valid after last clock edge

Master-in slave-out (MISO) output delay

8

ns

8

ns

—

ns

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SPI Timing Characteristics

Figure 7: SPI Slave Timing Diagram

T_hss

SPI_SS

T_suss

SPI_CLK (scpol = 0)

SPI_CLK (scpol = 1)

T_d

SPI_MISO (scph = 1)

SPI_MOSI (scph = 1)

T_s

T_h

T_d

SPI_MISO (scph = 0)

SPI_MOSI (scph = 0)

T_s

T_h

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SD/MMC Timing Characteristics

Table 45: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices

After power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters the

Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum of 400

kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL setting. The

value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz.

After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of drvsel and smplsel via the system manager.

drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT increase

to a maximum of 200 MHz and 50 MHz respectively.

The SD/MMC interface calibration support will be available in a future release of the preloader through the SoC EDS software update.

Symbol

Description

Min

Max

Unit

SDMMC_CLK clock period

(Identification mode)

20

—

ns

T_{sdmmc_clk}(internal reference

clock)

SDMMC_CLK clock period

(Default speed mode)

5

—

55

ns

SDMMC_CLK clock period

(High speed mode)

SDMMC_CLK_OUT clock

period (Identification mode)

2500

40

T_{sdmmc_clk_out}(interface output

clock)

SDMMC_CLK_OUT clock

period (Default speed mode)

SDMMC_CLK_OUT clock

period (High speed mode)

20

T_dutycycle

T_d

SDMMC_CLK_OUT duty cycle

45

%

SDMMC_CMD/SDMMC_D

output delay

(T_{sdmmc_clk}× drvsel)/2 (T_{sdmmc_clk}× drvsel)/2

ns

– 1.23 ⁽⁶⁹⁾

+ 1.69 ⁽⁶⁹⁾

(69)

drvsel is the drive clock phase shift select value.

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USB Timing Characteristics

Symbol

Description

Min

Max

Unit

T_su

T_h

Input setup time

1.05 – (T_{sdmmc_clk}

×

—

ns

smplsel)/2 ⁽⁷⁰⁾

Input hold time

(T_{sdmmc_clk}× smplsel)/

—

ns

2 ⁽⁷⁰⁾

Figure 8: SD/MMC Timing Diagram

SDMMC_CLK_OUT

T_d

SDMMC_CMD & SDMMC_D (Out)

SDMMC_CMD & SDMMC_D (In)

Command/Data Out

T_su

T_h

Command/Data In

Related Information

Booting and Configuration Chapter, Cyclone V Hard Processor System Technical Reference Manual

Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table.

USB Timing Characteristics

PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the

MicroChip USB3300 PHY device that has been proven to be successful on the development board.

Table 46: USB Timing Requirements for Cyclone V Devices

Symbol

Description

Min

—

Typ

16.67

—

Max

—

Unit

ns

T_clk

T_d

USB CLK clock period

CLK to USB_STP/USB_DATA[7:0] output delay

4.4

11

ns

(70)

smplsel is the sample clock phase shift select value.

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Ethernet Media Access Controller (EMAC) Timing Characteristics

Symbol

Description

Min

2

Typ

—

Max

—

Unit

ns

T_su

T_h

Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]

Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]

1

—

ns

Figure 9: USB Timing Diagram

USB_CLK

USB_STP

T_d

USB_DATA[7:0]

To PHY

From PHY

T_suT_h

USB_DIR & USB_NXT

Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 47: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Cyclone V Devices

Symbol

Description

Min

—

Typ

8

Max

—

Unit

ns

T_clk(1000Base-T) TX_CLK clock period

T_clk(100Base-T) TX_CLK clock period

—

40

400

—

ns

T_clk(10Base-T)

T_dutycycle

T_d

TX_CLK clock period

TX_CLK duty cycle

—

ns

45

55

%

TX_CLK to TXD/TX_CTL output data delay

–0.85

—

0.15

ns

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Ethernet Media Access Controller (EMAC) Timing Characteristics

Figure 10: RGMII TX Timing Diagram

TX_CLK

TX_D[3:0]

T_d

TX_CTL

Table 48: RGMII RX Timing Requirements for Cyclone V Devices

Symbol

T_clk(1000Base-T)

T_clk(100Base-T)

T_clk(10Base-T)

T_su

Description

Min

—

1

Typ

8

Unit

ns

RX_CLK clock period

RX_D/RX_CTL setup time

RX_D/RX_CTL hold time

40

400

—

ns

T_h

1

—

ns

Figure 11: RGMII RX Timing Diagram

RX_CLK

T_h

T_su

RX_D[3:0]

RX_CTL

Table 49: Management Data Input/Output (MDIO) Timing Requirements for Cyclone V Devices

Symbol

Description

Min

—

Typ

400

—

Unit

ns

T_clk

T_d

MDC clock period

MDC to MDIO output data delay

10

ns

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I2C Timing Characteristics

Symbol

Description

Min

10

0

Typ

—

Unit

ns

T_s

Setup time for MDIO data

Hold time for MDIO data

T_h

—

ns

Figure 12: MDIO Timing Diagram

MDC

T_d

MDIO_OUT

T_h

T_su

MDIO_IN

I²C Timing Characteristics

Table 50: I²C Timing Requirements for Cyclone V Devices

Standard Mode

Fast Mode

Symbol

Description

Unit

Min

Max

10

Min

—

Max

2.5

—

T_clk

Serial clock (SCL) clock period

SCL high time

—

4.7

4

µs

T_clkhigh

T_clklow

T_s

—

0.6

1.3

0.1

0

SCL low time

—

Setup time for serial data line (SDA) data to SCL

Hold time for SCL to SDA data

0.25

0

—

T_h

3.45

0.2

—

0.9

0.2

—

T_d

SCL to SDA output data delay

—

4.7

4

—

T_{su_start}

T_{hd_start}

T_{su_stop}

Setup time for a repeated start condition

Hold time for a repeated start condition

Setup time for a stop condition

0.6

—

4

—

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NAND Timing Characteristics

Figure 13: I²C Timing Diagram

I2C_SCL

T_d

T_s

T_{su_stop}

T_{su_start}T_{hd_start}

T_h

Data Out

Data In

I2C_SDA

NAND Timing Characteristics

Table 51: NAND ONFI 1.0 Timing Requirements for Cyclone V Devices

The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. This table lists the

requirements for ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by programming the C4 output of the main HPS PLL and

timing registers provided in the NAND controller.

Symbol

Description

Min

10

7

Max

—

Unit

ns

(71)

T_wp

T_wh

Write enable pulse width

Write enable hold time

Read enable pulse width

Read enable hold time

(71)

T_rp

10

7

(71)

T_reh

(71)

T_clesu

Command latch enable to write enable setup time

Command latch enable to write enable hold time

Chip enable to write enable setup time

10

5

(71)

T_cleh

T_cesu

15

5

(71)

T_ceh

T_alesu

Chip enable to write enable hold time

Address latch enable to write enable setup time

Address latch enable to write enable hold time

Data to write enable setup time

10

5

(71)

T_aleh

(71)

T_dsu

10

(71)

Timing of the NAND interface is controlled through the NAND configuration registers.

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NAND Timing Characteristics

Symbol

Description

Min

5

Max

—

Unit

ns

(71)

T_dh

Data to write enable hold time

T_cea

T_rea

T_rhz

T_rr

Chip enable to data access time

Read enable to data access time

Read enable to data high impedance

Ready to read enable low

—

20

25

ns

16

ns

100

—

ns

Figure 14: NAND Command Latch Timing Diagram

NAND_CLE

NAND_CE

T_clesu

T_cesu

T_cleh

T_ceh

T_wp

NAND_WE

NAND_ALE

T_alesu

T_aleh

T_dsu

Command

T_dh

NAND_DQ[7:0]

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NAND Timing Characteristics

Figure 15: NAND Address Latch Timing Diagram

NAND_CLE

NAND_CE

T_cesu

T_clesu

T_wp

T_wh

NAND_WE

NAND_ALE

T_alesu

T_aleh

T_dsu

T_dh

NAND_DQ[7:0]

Address

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NAND Timing Characteristics

Figure 16: NAND Data Write Timing Diagram

NAND_CLE

NAND_CE

T_cleh

T_ceh

T_wp

NAND_WE

NAND_ALE

T_alesu

T_dsu

T_dh

NAND_DQ[7:0]

Din

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ARM Trace Timing Characteristics

Figure 17: NAND Data Read Timing Diagram

T_cea

NAND_CE

T_rr

T_rp

T_reh

NAND_RE

T_rhz

NAND_RB

T_rea

NAND_DQ[7:0]

Dout

ARM Trace Timing Characteristics

Table 52: ARM Trace Timing Requirements for Cyclone V Devices

Most debugging tools have a mechanism to adjust the capture point of trace data.

Description

Min

12.5

45

Max

—

55

1

Unit

ns

CLK clock period

CLK maximum duty cycle

CLK to D0 –D7 output data delay

%

–1

ns

UART Interface

The maximum UART baud rate is 6.25 megasymbols per second.

GPIO Interface

The minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. The pulse width is based on a debounce clock frequency of 1 MHz.

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CAN Interface

The maximum controller area network (CAN) data rate is 1 Mbps.

HPS JTAG Timing Specifications

Table 53: HPS JTAG Timing Parameters and Values for Cyclone V Devices

Symbol

Description

Min

30

14

2

Max

—

Unit

ns

t_JCP

t_JCH

t_JCL

TCK clock period

TCK clock high time

TCK clock low time

—

t_{JPSU (TDI)}

t_{JPSU (TMS)}

t_JPH

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

JTAG port clock to output

—

3

—

5

—

t_JPCO

—

12⁽⁷²⁾

14⁽⁷²⁾

t_JPZX

JTAG port high impedance to valid output

JTAG port valid output to high impedance

t_JPXZ

Configuration Specifications

This section provides configuration specifications and timing for Cyclone V devices.

(72)

A 1-ns adder is required for each V_{CCIO _HPS}voltage step down from 3.0 V. For example, t_JPCO= 13 ns if V_{CCIO _HPS}of the TDO I/O bank = 2.5 V, or

14 ns if it equals 1.8 V.

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POR Specifications

Table 54: Fast and Standard POR Delay Specification for Cyclone V Devices

POR Delay

Minimum

Maximum

12⁽⁷³⁾

Unit

ms

Fast

4

Standard

100

300

ms

Related Information

MSEL Pin Settings

Provides more information about POR delay based on MSEL pin settings for each configuration scheme.

FPGA JTAG Configuration Timing

Table 55: FPGA JTAG Timing Parameters and Values for Cyclone V Devices

Symbol

Description

Min

Max

—

Unit

ns

t_JCP

t_JCH

t_JCL

TCK clock period

30, 167⁽⁷⁴⁾

TCK clock high time

TCK clock low time

14

1

—

t_{JPSU (TDI)}

t_{JPSU (TMS)}

t_JPH

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

JTAG port clock to output

—

3

—

5

—

11⁽⁷⁵⁾

14⁽⁷⁵⁾

t_JPCO

—

t_JPZX

JTAG port high impedance to valid output

(73)

(74)

(75)

The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.

The minimum TCK clock period is 167 ns if V_CCBATis within the range 1.2 V – 1.5 V when you perform the volatile key programming.

A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns

if it equals 1.8 V.

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FPP Configuration Timing

Symbol

Description

Min

Max

Unit

t_JPXZ

JTAG port valid output to high impedance

—

14⁽⁷⁵⁾

ns

FPP Configuration Timing

DCLK-to-DATA[] Ratio (r) for FPP Configuration

Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.

Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per

second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.

Cyclone V devices use additional clock cycles to decrypt and decompress the configuration data. If the DCLK-to-DATA[] ratio is greater than 1, at

the end of configuration, you can only stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into the Cyclone V device.

Table 56: DCLK-to-DATA[] Ratio for Cyclone V Devices

Configuration Scheme

Encryption

Off

Compression

DCLK-to-DATA[] Ratio (r)

Off

On

Off

On

1

2

1

2

4

On

FPP (8-bit wide)

Off

On

Off

On

FPP (16-bit wide)

Off

On

FPP Configuration Timing when DCLK-to-DATA[] = 1

When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-

to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone V Devices table.

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FPP Configuration Timing when DCLK-to-DATA[] = 1

Table 57: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices

Symbol

Parameter

nCONFIG low to CONF_DONE low

Minimum

Maximum

600

—

1506⁽⁷⁶⁾

1506⁽⁷⁷⁾

—

Unit

ns

µs

ns

s

t_CF2CD

t_CF2ST0

t_CFG

t_STATUS

t_CF2ST1

—

nCONFIG low to nSTATUS low

nCONFIG low pulse width

—

2

nSTATUS low pulse width

268

nCONFIG high to nSTATUS high

nCONFIG high to first rising edge on DCLK

nSTATUS high to first rising edge of DCLK

DATA[] setup time before rising edge on DCLK

DATA[] hold time after rising edge on DCLK

DCLK high time

—

(78)

t_CF2CK

1506

(78)

t_ST2CK

t_DSU

2

—

5.5

—

t_DH

0

—

t_CH

0.45 × 1/f_MAX

—

t_CL

DCLK low time

0.45 × 1/f_MAX

—

s

t_CLK

DCLK period

1/f_MAX

—

s

f_MAX

t_CD2UM

t_CD2CU

t_CD2UMC

DCLK frequency (FPP ×8/ ×16)

CONF_DONE high to user mode⁽⁷⁹⁾

CONF_DONE high to CLKUSR enabled

CONF_DONE high to user mode with CLKUSR option on

—

175

125

437

—

MHz

µs

—

4× maximum DCLK period

t_CD2CU+ (T_init× CLKUSR

—

period)

T_init

Number of clock cycles required for device initialization

17,408

—

Cycles

(76)

You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width.

You can obtain this value if you do not delay configuration by externally holding the nSTATUS low.

If nSTATUS is monitored, follow the t_ST2CKspecification. If nSTATUS is not monitored, follow the t_CF2CKspecification.

The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

(77)

(78)

(79)

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FPP Configuration Timing when DCLK-to-DATA[] >1

Related Information

FPP Configuration Timing

Provides the FPP configuration timing waveforms.

FPP Configuration Timing when DCLK-to-DATA[] >1

Table 58: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices

Use these timing parameters when you use the decompression and design security features.

Symbol

Parameter

nCONFIG low to CONF_DONE low

Minimum

Maximum

600

—

1506⁽⁸⁰⁾

1506⁽⁸¹⁾

—

Unit

ns

µs

ns

s

t_CF2CD

t_CF2ST0

t_CFG

t_STATUS

t_CF2ST1

—

nCONFIG low to nSTATUS low

nCONFIG low pulse width

—

2

nSTATUS low pulse width

268

nCONFIG high to nSTATUS high

nCONFIG high to first rising edge on DCLK

nSTATUS high to first rising edge of DCLK

DATA[] setup time before rising edge on DCLK

DATA[] hold time after rising edge on DCLK

DCLK high time

—

(82)

t_CF2CK

1506

(82)

t_ST2CK

t_DSU

t_DH

2

5.5

—

(83)

N – 1/f_DCLK

—

t_CH

0.45 × 1/f_MAX

—

s

t_CL

DCLK low time

0.45 × 1/f_MAX

—

s

t_CLK

f_MAX

t_R

DCLK period

1/f_MAX

—

s

DCLK frequency (FPP ×8/ ×16)

Input rise time

125

40

MHz

ns

—

(80)

(81)

(82)

(83)

This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

This value can be obtained if you do not delay configuration by externally holding nSTATUS low.

If nSTATUS is monitored, follow the t_ST2CKspecification. If nSTATUS is not monitored, follow the t_CF2CKspecification.

N is the DCLK-to-DATA[] ratio and f_DCLKis the DCLK frequency of the system.

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AS Configuration Timing

Symbol

Parameter

Minimum

Maximum

Unit

ns

t_F

t_CD2UM

t_CD2CU

Input fall time

—

175

40

437

—

CONF_DONE high to user mode⁽⁸⁴⁾

µs

CONF_DONE high to CLKUSR enabled

4 × maximum DCLK period

—

t_CD2UMC

CONF_DONE high to user mode with CLKUSR option on

t_CD2CU+ (T_init× CLKUSR

—

period)

T_init

Number of clock cycles required for device initialization

17,408

—

Cycles

Related Information

FPP Configuration Timing

Provides the FPP configuration timing waveforms.

AS Configuration Timing

Table 59: AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices

The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configura‐

tion.

The t_CF2CD, t_CF2ST0, t_CFG, t_STATUS, and t_CF2ST1timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing

Parameters for Cyclone V Devices table. You can obtain the t_CF2ST1value if you do not delay configuration by externally holding nSTATUS low.

Symbol

Parameter

Minimum

Maximum

Unit

ns

t_CO

t_SU

DCLK falling edge to the AS_DATA0/ASDO output

Data setup time before the falling edge on DCLK

Data hold time after the falling edge on DCLK

CONF_DONE high to user mode

—

2

—

1.5

ns

t_DH

0

175

—

ns

t_CD2UM

t_CD2CU

437

—

µs

CONF_DONE high to CLKUSR enabled

4 × maximum DCLK period

—

t_CD2UMC

CONF_DONE high to user mode with CLKUSR option on

t_CD2CU+ (T_init× CLKUSR

—

period)

(84)

The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

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DCLK Frequency Specification in the AS Configuration Scheme

Symbol

Parameter

Minimum

Maximum

Unit

T_init

Number of clock cycles required for device initialization

17,408

—

Cycles

Related Information

•

PS Configuration Timing on page 74

AS Configuration Timing

Provides the AS configuration timing waveform.

DCLK Frequency Specification in the AS Configuration Scheme

Table 60: DCLK Frequency Specification in the AS Configuration Scheme

This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the

internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.

Parameter

Minimum

Typical

Maximum

Unit

5.3

7.9

12.5

MHz

10.6

15.7

31.4

62.9

25.0

DCLK frequency in AS configuration scheme

21.3

50.0

42.6

100.0

PS Configuration Timing

Table 61: PS Timing Parameters for Cyclone V Devices

Symbol

Parameter

nCONFIG low to CONF_DONE low

Minimum

Maximum

600

Unit

ns

t_CF2CD

t_CF2ST0

t_CFG

—

2

nCONFIG low to nSTATUS low

nCONFIG low pulse width

nSTATUS low pulse width

600

ns

—

1506⁽⁸⁵⁾

µs

t_STATUS

268

µs

(85)

You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

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PS Configuration Timing

Symbol

Parameter

nCONFIG high to nSTATUS high

Minimum

Maximum

Unit

µs

ns

s

t_CF2ST1

—

1506⁽⁸⁶⁾

—

(87)

t_CF2CK

nCONFIG high to first rising edge on DCLK

nSTATUS high to first rising edge of DCLK

DATA[] setup time before rising edge on DCLK

DATA[] hold time after rising edge on DCLK

DCLK high time

1506

(87)

t_ST2CK

t_DSU

t_DH

2

—

5.5

—

0

—

t_CH

0.45 × 1/f_MAX

—

t_CL

DCLK low time

0.45 × 1/f_MAX

—

s

t_CLK

f_MAX

t_CD2UM

t_CD2CU

DCLK period

1/f_MAX

—

s

DCLK frequency

—

175

125

437

—

MHz

µs

—

CONF_DONE high to user mode⁽⁸⁸⁾

CONF_DONE high to CLKUSR enabled

CONF_DONE high to user mode with CLKUSR option on

4 × maximum DCLK period

t_CD2UMC

t_CD2CU+ (T_init× CLKUSR

—

period)

T_init

Number of clock cycles required for device initialization

17,408

—

Cycles

Related Information

PS Configuration Timing

Provides the PS configuration timing waveform.

(86)

You can obtain this value if you do not delay configuration by externally holding nSTATUS low.

(87)

(88)

If nSTATUS is monitored, follow the t_ST2CKspecification. If nSTATUS is not monitored, follow the t_CF2CKspecification.

The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

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Initialization

Table 62: Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices

Initialization Clock Source

Configuration Scheme

AS, PS, and FPP

PS and FPP

Maximum Frequency (MHz)

Minimum Number of Clock Cycles

Internal Oscillator

12.5

125

100

125

CLKUSR⁽⁸⁹⁾

T_init

AS

DCLK

PS and FPP

(89)

To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime

software from the General panel of the Device and Pin Options dialog box.

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Configuration Files

Table 63: Uncompressed .rbf Sizes for Cyclone V Devices

Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file

(.ttf) format, have different file sizes.

For the different types of configuration file and file sizes, refer to the Quartus Prime software. However, for a specific version of the Quartus Prime

software, any design targeted for the same device has the same uncompressed configuration file size.

The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature.

Variant

Member Code

Configuration .rbf Size (bits)

IOCSR .rbf Size (bits)

Recommended EPCQ Serial Configuration

Device⁽⁹⁰⁾

A2

A4

A5

A7

A9

C3

C4

C5

C7

C9

D5

D7

D9

21,061,280

33,958,560

56,167,552

102,871,776

14,510,912

33,958,560

56,167,552

102,871,776

33,958,560

56,167,552

102,871,776

275,608

322,072

435,288

400,408

320,280

322,072

435,288

400,408

322,072

435,288

400,408

EPCQ64

Cyclone V E ⁽⁹¹⁾

EPCQ128

EPCQ256

EPCQ32

EPCQ128

EPCQ256

EPCQ128

EPCQ256

Cyclone V GX

Cyclone V GT

(90)

The recommended EPCQ serial configuration devices are able to store more than one image.

No PCIe hard IP, configuration via protocol (CvP) is not supported in this family.

(91)

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Configuration Files

Variant

Member Code

Configuration .rbf Size (bits)

IOCSR .rbf Size (bits)

Recommended EPCQ Serial Configuration

Device⁽⁹⁰⁾

A2⁽⁹²⁾

A4⁽⁹²⁾

A5

33,958,560

56,057,632

33,958,560

56,057,632

322,072

324,888

322,072

324,888

EPCQ128

Cyclone V SE ⁽⁹¹⁾

A6

C2⁽⁹²⁾

C4⁽⁹²⁾

C5

Cyclone V SX

Cyclone V ST

C6

D5

D6

(90)

The recommended EPCQ serial configuration devices are able to store more than one image.

This device will be supported in a future release of the Quartus Prime software.

(92)

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Minimum Configuration Time Estimation

Table 64: Minimum Configuration Time Estimation for Cyclone V Devices

The estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Cyclone V Devices table.

Active Serial⁽⁹³⁾

Fast Passive Parallel⁽⁹⁴⁾

Variant

Member Code

Width

DCLK (MHz) Minimum Configura‐

tion Time (ms)

Width

DCLK (MHz)

Minimum Configuration Time

(ms)

A2

A4

A5

A7

A9

C3

C4

C5

C7

C9

D5

D7

D9

A2

A4

A5

A6

4

100

53

16

125

11

17

28

51

7

Cyclone V E

85

140

257

36

85

17

28

51

17

28

51

17

28

Cyclone V GX

85

140

257

85

Cyclone V GT

Cyclone V SE

140

257

85

140

(93)

DCLK frequency of 100 MHz using external CLKUSR.

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Remote System Upgrades

Active Serial⁽⁹³⁾

Fast Passive Parallel⁽⁹⁴⁾

Variant

Member Code

Width

DCLK (MHz) Minimum Configura‐

tion Time (ms)

Width

DCLK (MHz)

Minimum Configuration Time

(ms)

C2

C4

C5

C6

D5

D6

4

100

85

16

125

17

Cyclone V SX

Cyclone V ST

140

28

Related Information

Configuration Files on page 77

Remote System Upgrades

Table 65: Remote System Upgrade Circuitry Timing Specifications for Cyclone V Devices

Parameter

Minimum

250

Unit

ns

(95)

t_{RU_nCONFIG}

(96)

t_{RU_nRSTIMER}

250

ns

Related Information

•

Remote System Upgrade State Machine

Provides more information about configuration reset (RU_CONFIG) signal.

(93)

(94)

(95)

(96)

DCLK frequency of 100 MHz using external CLKUSR.

Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.

This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.

This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.

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User Watchdog Internal Oscillator Frequency Specifications

•

User Watchdog Timer

Provides more information about reset_timer (RU_nRSTIMER) signal.

User Watchdog Internal Oscillator Frequency Specifications

Table 66: User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices

Parameter

Minimum

Typical

Maximum

Unit

User watchdog internal oscillator frequency

5.3

7.9

12.5

MHz

I/O Timing

Altera offers two ways to determine I/O timing—the Excel-based I/O timing and the Quartus Prime Timing Analyzer.

Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the

FPGA to get an estimate of the timing budget as part of the link timing analysis.

The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete

place-and-route.

Related Information

Cyclone V I/O Timing Spreadsheet

Provides the Cyclone V Excel-based I/O timing spreadsheet.

Programmable IOE Delay

Table 67: I/O element (IOE) Programmable Delay for Cyclone V Devices

Fast Model

Slow Model

–C8

Available

Settings

Minimum

Offset⁽⁹⁸⁾

Parameter⁽⁹⁷⁾

Unit

Industrial

Commercial

–C6

–C7

–I7

–A7

D1

32

0

0.508

0.517

0.971

1.187

1.194

1.179

1.160

ns

(97)

You can set this value in the Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.

Minimum offset does not include the intrinsic delay.

(98)

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Programmable Output Buffer Delay

Fast Model

Slow Model

–C8

Available

Settings

Minimum

Offset⁽⁹⁸⁾

Parameter⁽⁹⁷⁾

Unit

Industrial

Commercial

1.793

–C6

–C7

–I7

–A7

D3

D4

D5

8

0

1.761

0.510

0.508

3.291

1.180

0.970

4.022

1.187

1.186

3.961

3.999

1.180

1.179

3.929

1.160

1.179

ns

32

0.519

1.195

0.517

1.194

Programmable Output Buffer Delay

Table 68: Programmable Output Buffer Delay for Cyclone V Devices

This table lists the delay chain settings that control the rising and falling edge delays of the output buffer.

You can set the programmable output buffer delay in the Quartus Prime software by setting the Output Buffer Delay Control assignment to either

positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment.

Symbol

Parameter

Typical

0 (default)

50

Unit

ps

D_OUTBUF

Rising and/or falling edge delay

100

ps

150

ps

Glossary

Table 69: Glossary

Term

Definition

Differential I/O standards

Receiver Input Waveforms

(97)

(98)

You can set this value in the Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.

Minimum offset does not include the intrinsic delay.

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Glossary

Term

Definition

Single-Ended Waveform

Positive Channel (p) = V

IH

V

ID

Negative Channel (n) = V

IL

V

CM

Ground

Differential Waveform

V

ID

p - n = 0 V

V

ID

Transmitter Output Waveforms

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Glossary

Term

Definition

Single-Ended Waveform

Positive Channel (p) = V

OH

V

OD

Negative Channel (n) = V

Ground

OL

V

CM

Differential Waveform

V

OD

p - n = 0 V

V

OD

f_HSCLK

f_HSDR

J

Left/right PLL input clock frequency.

High-speed I/O block—Maximum/minimum LVDS data transfer rate (f_HSDR=1/TUI).

High-speed I/O block—Deserialization factor (width of parallel data bus).

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Glossary

Term

Definition

JTAG timing specifications

JTAG Timing Specifications

TMS

TDI

t _JCP

t _JCH

t

JCL

t_JPH

t _JPSU

TCK

t_JPXZ

t_JPZX

t_JPCO

TDO

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Glossary

Term

Definition

PLL specifications

Diagram of PLL specifications

CLKOUT Pins

f_OUT

Switchover

_EXT

4

CLK

f_IN

f_INPFD

N

GCLK

RCLK

Counters

C0..C17

f_VCO

VCO

f_OUT

PFD

CP

LF

Core Clock

Delta Sigma

Modulator

Legend

Reconfigurable in User Mode

External Feedback

Note:

(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.

R_L

Receiver differential input discrete resistor (external to the Cyclone V device).

Sampling window (SW)

Timing diagram—The period of time during which the data must be valid in order to capture it correctly.

The setup and hold times determine the ideal strobe position in the sampling window, as shown:

Bit Time

Sampling Window

(SW)

RSKM

0.5 x TCCS

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Glossary

Term

Definition

Single-ended voltage referenced I/O

standard

The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The

AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC

values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined.

After the receiver input has crossed the AC value, the receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach

is intended to provide predictable receiver timing in the presence of input waveform ringing.

Single-Ended Voltage Referenced I/O Standard

V _CCIO

V_OH

V_{IH AC}

( )

V_{IH(DC )}

V _REF

V _{IL(DC )}

V _IL(AC

)

V_OL

V_SS

t_C

High-speed receiver/transmitter input and output clock period.

TCCS (channel-to-channel-skew)

The timing difference between the fastest and slowest output edges, including the t_COvariation and clock

skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to

the Timing Diagram figure under SW in this table).

t_DUTY

High-speed I/O block—Duty cycle on high-speed transmitter output clock.

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Glossary

Term

Definition

t_FALL

Signal high-to-low transition time (80–20%)

t_INCCJ

Cycle-to-cycle jitter tolerance on the PLL clock input

Period jitter on the GPIO driven by a PLL

t_{OUTPJ_IO}

t_{OUTPJ_DC}

t_RISE

Period jitter on the dedicated clock output driven by a PLL

Signal low-to-high transition time (20–80%)

Timing Unit Interval (TUI)

The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/

(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)

V_CM(DC)

V_ICM

DC common mode input voltage.

Input common mode voltage—The common mode of the differential signal at the receiver.

V_ID

Input differential voltage swing—The difference in voltage between the positive and complementary

conductors of a differential transmission at the receiver.

V_DIF(AC)

V_DIF(DC)

V_IH

AC differential input voltage—Minimum AC input differential voltage required for switching.

DC differential input voltage— Minimum DC input differential voltage required for switching.

Voltage input high—The minimum positive voltage applied to the input which is accepted by the device

as a logic high.

V_IH(AC)

V_IH(DC)

V_IL

High-level AC input voltage

High-level DC input voltage

Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as

a logic low.

V_IL(AC)

V_IL(DC)

V_OCM

V_OD

Low-level AC input voltage

Low-level DC input voltage

Output common mode voltage—The common mode of the differential signal at the transmitter.

Output differential voltage swing—The difference in voltage between the positive and complementary

conductors of a differential transmission at the transmitter.

V_SWING

V_X

Differential input voltage

Input differential cross point voltage

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Document Revision History

Term

Definition

V_OX

W

Output differential cross point voltage

High-speed I/O block—Clock boost factor

Document Revision History

Date

Version

Changes

December 2015

2015.12.04

•

Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices table.

•

Updated F_clk, T_dutycycle, and T_dssfrstspecifications.

Added T_{qspi_clk}, T_{din_start}, and T_{din_end}specifications.

Removed T_dinmaxspecifications.

•

Updated the minimum specification for T_clkto 16.67 ns and removed the maximum specification in SPI

Master Timing Requirements for Cyclone V Devices table.

Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table.

•

Updated T _clkto T_{sdmmc_clk_out}symbol.

Updated T_{sdmmc_clk_out}and T_dspecifications.

Added T_{sdmmc_clk}, T_su, and T_hspecifications.

Removed T_dinmaxspecifications.

•

Updated the following diagrams:

•

Quad SPI Flash Timing Diagram

SD/MMC Timing Diagram

•

Updated configuration .rbf sizes for Cyclone V devices.

Changed instances of Quartus II to Quartus Prime.

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Document Revision History

Date

Version

Changes

June 2015

2015.06.12

•

Updated the supported data rates for the following output standards using true LVDS output buffer types in

the High-Speed I/O Specifications for Cyclone V Devices table:

•

True RSDS output standard: data rates of up to 360 Mbps

True mini-LVDS output standard: data rates of up to 400 Mbps

•

Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.

Updated T_hlocation in I²C Timing Diagram.

Updared T_wplocation in NAND Address Latch Timing Diagram.

Updated the maximum value for t_COfrom 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configu‐

rations in Cyclone V Devices table.

•

Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades

in Cyclone V Devices chapter.

•

FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1

FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1

AS Configuration Timing Waveform

PS Configuration Timing Waveform

March 2015

2015.03.31

•

Added V_CCspecifications for devices with internal scrubbing feature (with SC suffix) in Recommended

Operating Conditions table.

Corrected the unit for t_DHfrom ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for

Cyclone V Devices table.

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Document Revision History

Date

Version

Changes

January 2015

2015.01.23

•

Updated the transceiver specification for Cyclone V ST from 5 Gbps to 6.144 Gbps. Updated the note in the

following tables:

•

Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices

Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Transceiver Compliance Specification for All Supported Protocol for Cyclone V Devices

Updated the description for V_{CC_AUX_SHARED}to “HPS auxiliary power supply”. Added a note to state that

V_{CC_AUX_SHARED}must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6

devices, and Cyclone V SE A5 and A6 devices. Updated in the following tables:

•

Absolute Maximum Ratings for Cyclone V Devices

HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices

•

Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the

maximum achievable frequency for general purpose I/O standards.

Updated the conditions for transceiver reference clock rise time and fall time: Measure at 60 mV of

differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK

phase noise specification.

•

Updated f_VCOmaximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL

specifications table.

Updated the description in Periphery Performance Specifications to mention that proper timing closure is

required in design.

Added the following notes in the High-Speed I/O Specifications for Cyclone V Devices table:

•

The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true

LVDS output buffer types on all I/O banks.

•

The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using

true LVDS output buffer types on all I/O banks.

•

Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed

grade.

Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and

1,850 MHz (for –C6 speed grade).

Changed the symbol for HPS PLL input jitter divide value from NR to N.

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Document Revision History

Date

Version

Changes

•

Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:

•

SPI Master Timing Requirements for Cyclone V Devices

SPI Slave Timing Requirements for Cyclone V Devices

Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM

mode may not function properly with the USB controller due to a timing issue. It is recommended that

designers use the MicroChip USB3300 PHY device that has been proven to be successful on the develop‐

ment board.

•

Added HPS JTAG timing specifications.

Updated the configuration .rbf size (bits) for Cyclone V devices.

Added a note to Uncompressed .rbf Sizes for Cyclone V Devices table: The recommended EPCQ serial

configuration devices are able to store more than one image.

July 2014

3.9

•

Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC

(static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN

tool for the additional budget for the dynamic tolerance requirements.

Added a note in Table 19: Differential inputs are powered by V_CCPDwhich requires 2.5 V.

Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20.

Updated h2f_user2_clk specification for –C6, –C7, and –I7 speed grades in Table 34.

Updated description in “HPS PLL Specifications” section.

Updated VCO range maximum specification in Table 35.

Updated T_dand T_hspecifications in Table 41.

Added T_hspecification in Table 43 and Figure 10.

Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK floating after configu‐

ration. DCLK is ignored after configuration is complete. It can toggle high or low if required.

Removed “Remote update only in AS mode” specification in Table 54.

Added DCLK device initialization clock source specification in Table 56.

Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration

via Protocol (CvP) feature.

•

Added "Recommended EPCQ Serial Configuration Device" values in Table 57.

Removed f_{MAX_RU_CLK}specification in Table 59.

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Document Revision History

Date

Version

Changes

February 2014

3.8

•

Updated V_{CCRSTCLK_HPS}maximum specification in Table 1.

Added V_{CC_AUX_SHARED}specification in Table 1.

December 2013

3.7

•

Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34, Table 44, Table 51,

Table 52, Table 55, and Table 61.

Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12,

Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 24, Table 25, Table 26,

Table 27, Table 28, Table 32, Table 33, Table 49, Table 50, Table 51, Table 52, Table 53, Table 54, Table 55,

Table 57, Table 58, Table 59, Table 60, and Table 62.

November 2013

October 2013

3.6

3.5

Updated Table 23, Table 30, and Table 31.

•

Added “HPS PLL Specifications”.

Added Table 23, Table 35, and Table 36.

Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, Table 28, Table 34,

Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47,

and Table 53.

•

Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.

Removed table: GPIO Pulse Width for Cyclone V Devices.

June 2013

May 2013

3.4

3.3

•

Updated Table 20, Table 27, and Table 34.

Updated “UART Interface” and “CAN Interface” sections.

Removed the following tables:

•

Table 45: UART Baud Rate for Cyclone V Devices

Table 47: CAN Pulse Width for Cyclone V Devices

•

Added Table 33.

Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.

Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26, Table 32, Table 35, Table

36, Table 43, Table 53, Table 54, Table 57, and Table 61.

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Document Revision History

Date

Version

Changes

March 2013

3.2

•

Added HPS reset information in the “HPS Specifications” section.

Added Table 57.

Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.

Updated Figure 18.

January 2013

3.1

3.0

Updated Table 4, Table 20, and Table 56.

November 2012

•

Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19, Table 20, Table 25, Table

28, Table 52, Table 55, Table 56, and Table 59.

•

Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices.

Added HPS information:

•

Added “HPS Specifications” section.

Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42,

Table 43, Table 44, Table 45, and Table 46.

•

Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,

Figure 14, Figure 15, and Figure 16.

Updated Table 3.

June 2012

2.0

Updated for the Quartus II software v12.0 release:

•

Restructured document.

Removed “Power Consumption” section.

Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30, Table 31, Table 34,

Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and Table 46.

Added Table 22, Table 23, and Table 29.

Added Figure 1 and Figure 2.

Added “Initialization” and “Configuration Files” sections.

•

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Document Revision History

Date

Version

Changes

February 2012

1.2

•

Added automotive speed grade information.

Added Figure 2–1.

Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21, Table 2–22, Table 2–23,

Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30, Table 2–35, and Table 2–43.

Minor text edits.

•

November 2011

October 2011

1.1

1.0

•

Added Table 2–5.

Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.

Initial release.

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型号：	5CGXFC9A6U19I7N
厂家：	INTEL
描述：	Field Programmable Gate Array, 301000-Cell, CMOS, PBGA484, ROHS COMPLIANT, UBGA-484 栅
文件：	总95页 (文件大小：1359K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5CGXFC9A6U19I7N [INTEL]

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