6400 [INTEL]
Advanced Memory Buffer; 高级内存缓冲器
| 元器件型号： | 6400 |
| 生产厂家： | 
INTEL CORPORATION
|
| 描述和应用： | Advanced Memory Buffer |
| PDF文件： | 总250页 (文件大小：3863K) |
| 下载文档： | 下载PDF数据表文档文件 |
| 型号参数：6400参数 | |
| 是否Rohs认证 | 符合 |
| 生命周期 | Transferred |
| 包装说明 | ROHS COMPLIANT |
| Reach Compliance Code | unknown |
| Factory Lead Time | 8 weeks |
| 风险等级 | 2.68 |
| 主体材料 | ALUMINUM |
| 颜色 | BLACK |
| 构造 | EXTRUDED |
| 面层 | ANODIZED |
| 高度 | 63.5 mm |
| 长度 | 41.91 mm |
| 轮廓 | PIN FIN ARRAY |
| 热阻 | 2.7 Ω |
| 耐热支撑装置类型 | HEAT SINK |
| 宽度 | 25.4 mm |
| Base Number Matches | 1 |
MAX34334CSE前5页PDF页面详情预览
Intel® 6400/6402 Advanced
Memory Buffer
Datasheet
October 2006
Reference Number: 313072-002
IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,
life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained
Intel, Intel Interconnect BIST and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in
the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2003-2006, Intel Corporation. All Rights Reserved.
2
Intel® 6400/6402 Advanced Memory Buffer Datasheet
Contents
1
Introduction
............................................................................................................ 11
1.1
Intel
®
6400/6402 Advanced Memory Buffer Overview ............................................ 11
1.1.1 Transparent Mode for DRAM Test Support.................................................. 12
1.1.2 Debug and Logic Analyzer Interface .......................................................... 12
1.1.3 DDR SDRAM .......................................................................................... 12
1.2
AMB Block Diagram ........................................................................................... 12
1.3
Interfaces ........................................................................................................ 13
1.3.1 FBD High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces ............................................................................................ 14
1.3.2 DDR2 Channel ....................................................................................... 14
1.3.3 SMBus Slave Interface ............................................................................ 14
1.4
References ....................................................................................................... 15
FBD Channel Interface.............................................................................................
17
2.1
Intel 6400/6402 Advanced Memory Buffer (AMB) Support for FBD Operating Modes .. 17
2.2
Channel Initialization ......................................................................................... 17
2.3
Channel Protocol ............................................................................................... 17
2.3.1 General................................................................................................. 17
2.3.2 Timeouts During TS0 .............................................................................. 17
2.3.3 Recalibrate State Considerations .............................................................. 18
2.3.4 Address Mapping of DDR Commands to DRAMs .......................................... 19
2.3.5 FBD L0s State........................................................................................ 19
2.4
Reliability, Availability, and Serviceability ............................................................. 19
2.4.1 Channel Error Detection and Logging ........................................................ 19
2.5
Channel Configuration........................................................................................ 19
2.5.1 Re-sync and Resample Modes .................................................................. 19
2.5.2 Other Channel Configuration Modes .......................................................... 20
2.5.3 Lane to Lane Skew on a Channel .............................................................. 20
2.6
Repeater Mode.................................................................................................. 21
2.7
Channel Latency ............................................................................................... 21
2.7.1 Command to Data Delay Calculation ......................................................... 21
DDR Interface..........................................................................................................
25
3.1
Intel 6400/6402 Advanced Memory Buffer (AMB) DDR Interface Overview ............... 25
3.2
Data Mapping ................................................................................................... 25
3.3
Command / Address Outputs .............................................................................. 26
3.3.1 CKE Output Control ................................................................................ 27
3.4
DQS I/O and DM Outputs ................................................................................... 27
3.5
Refresh ............................................................................................................ 28
3.5.1 Self-Refresh During Channel Reset ........................................................... 29
3.5.2 Automatic Refresh .................................................................................. 29
3.6
Back to Back Turnaround Time............................................................................ 30
3.7
S3 State Background Description......................................................................... 31
3.7.1 S3 Recovery Configuration Registers......................................................... 32
3.8
DDR Calibration ................................................................................................ 32
3.8.1 DRAM Initialization and (E)MRS FSM ......................................................... 32
3.8.2 DQS Failure CSR .................................................................................... 33
3.8.3 Automatic DDR Bus Calibration ................................................................ 34
3.8.4 Receive Enable Calibration....................................................................... 34
3.8.5 DQS Delay Calibration............................................................................. 34
3.9
DIMM Organization ............................................................................................ 35
Electrical, Power, and Thermal
................................................................................ 37
4.1
Electrical DC Parameters .................................................................................... 37
2
3
4
Intel® 6400/6402 Advanced Memory Buffer Datasheet
3
4.2
4.3
4.4
4.5
4.6
4.7
4.1.1 Absolute Maximum Ratings ......................................................................37
4.1.2 Operating DC Parameters ........................................................................37
4.1.3 AMB Power Specifications ........................................................................38
FB-DIMM Electrical Timing Specifications...............................................................44
DDR2 DRAM Interface Electrical Specifications .......................................................45
DDR2 Electrical Output Timing Specifications .........................................................46
4.4.1 Description of DQ/DQS Alignment .............................................................46
4.4.2 Description of ADD/CMD/CNTL Outputs......................................................46
4.4.3 Test Load Specification ............................................................................46
4.4.4 tDVA and tDVB Parameter Description .......................................................46
4.4.5 tjit and tjitHP Parameter Description..........................................................46
4.4.6 tCVA, tCVB, tECVA and tECVB Parameter Description...................................47
4.4.7 tDQSCK Timing Parameter Description.......................................................47
4.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS
(Read Operation) ....................................................................................48
4.4.9 Write Preamble Duration..........................................................................49
4.4.10 Write Postamble Duration ........................................................................49
4.4.11 Advance Memory Buffer Component Electrical Timing Summary ....................50
4.4.12 Reference DDR2 Interface Package Trace Lengths .......................................51
SMBUS Interface ...............................................................................................51
Miscellaneous I/O (1.5 Volt CMOS Driver) .............................................................51
Thermal Diode and Analog to Digital Converter (ADC).............................................51
4.7.1 Thermal Sensor Effects on the AMB’s
Functional Behavior.................................................................................52
5
Debug and Logic Analyzer Mode...............................................................................53
5.1
Logic Analyzer Interface (LAI) Mode .....................................................................53
5.1.1 LAI Mode Architecture .............................................................................54
5.1.2 LAI Mode Clocking ..................................................................................55
5.1.3 LAI Mode Pins ........................................................................................55
5.1.4 LAI Mode Signal Definitions ......................................................................56
5.1.5 LAI to DDR Pin Mapping...........................................................................57
5.1.6 FBD to LAI Signal Mapping .......................................................................58
5.1.7 LAI to DDR Pin Timing .............................................................................59
5.1.8 LAI Features ..........................................................................................60
5.1.9 LAI Block Diagram ..................................................................................67
5.2
Normal Mode Debug Features..............................................................................68
5.2.1 Normal Mode Debug Triggers ...................................................................68
5.2.2 Error Injection........................................................................................68
Errors
......................................................................................................................71
6.1
Types of Errors and Responses ............................................................................71
6.1.1 FBD Link Errors ......................................................................................71
6.1.2 DDR Errors ............................................................................................73
6.1.3 Host Protocol Errors ................................................................................73
6.1.4 Other Errors...........................................................................................74
6.2
Error Logging ....................................................................................................74
6.2.1 Error Logging Procedure ..........................................................................74
6.3
Fail Over Mode Support ......................................................................................75
6.4
Failback to Pass-Thru .........................................................................................75
SMBus Interface
......................................................................................................77
7.1
System Management Access ...............................................................................77
7.1.1 SMBus 2.0 Specification Compatibility........................................................77
7.1.2 Supported SMBus Commands ...................................................................77
7.1.3 FBD AMB Register Access Protocols ...........................................................78
7.1.4 SMBus Error Handling..............................................................................81
7.1.5 SMBus Resets ........................................................................................81
6
7
4
Intel® 6400/6402 Advanced Memory Buffer Datasheet
8
Clocking
.................................................................................................................. 83
8.1
Intel 6400/6402 Advanced Memory Buffer (AMB) Clock Domains ............................. 83
8.2
PLL Clocks ........................................................................................................ 85
8.3
Reference Clock ................................................................................................ 85
8.4
FBD Lane Frame Clocks...................................................................................... 86
8.5
Clock Ratios ..................................................................................................... 86
8.6
DDR DRAM Clock Support................................................................................... 86
8.7
SMBus ............................................................................................................. 86
8.8
Clock Pins ........................................................................................................ 86
8.9
Additional Clock Modes....................................................................................... 87
8.9.1 Transparent Mode Clocking...................................................................... 87
8.10 PLL Requirements.............................................................................................. 87
8.10.1 Jitter .................................................................................................... 87
8.10.2 PLL Bandwidth Requirements ................................................................... 87
8.10.3 External Reference ................................................................................. 87
8.10.4 Spread Spectrum Support ....................................................................... 88
8.10.5 Frequency of Operation ........................................................................... 88
8.10.6 RESET# ................................................................................................ 88
8.10.7 Other PLL Characteristics......................................................................... 88
8.11 Analog Power Supply Pins................................................................................... 89
Reset
....................................................................................................................... 91
9.1
Platform Reset Functionality ............................................................................... 91
9.1.1 Platform RESET# Requirements ............................................................... 91
9.1.2 RESET# Requirements ............................................................................ 91
9.1.3 Power-Up and Suspend-to-RAM Considerations .......................................... 92
9.2
Reset Types...................................................................................................... 92
9.3
Pads Controlling Reset ....................................................................................... 92
9.3.1 RESET# Pad .......................................................................................... 92
9.3.2 Primary FBD Link ................................................................................... 93
9.4
Details ............................................................................................................. 93
9.4.1 Cold Power-Up Reset Sequence ................................................................ 93
9.4.2 S3 Restore Power-Up Reset Sequence ....................................................... 94
9.4.3 Reset Sequence for a Fast Reset .............................................................. 95
9.4.4 Fast Reset Handshake............................................................................. 95
9.4.5 Timing Diagrams .................................................................................... 96
9.5
I/O Initialization ................................................................................................ 97
9.5.1 FBD Channel Initialization........................................................................ 97
9.5.2 DDR ..................................................................................................... 97
Transparent Mode
................................................................................................... 99
10.1 Transparent Mode ............................................................................................. 99
10.1.1 Block Diagram ..................................................................................... 100
10.1.2 Transparent Mode Signal Definitions ....................................................... 100
10.1.3 Transparent Mode to FBD Pin Mapping .................................................... 101
10.2 Transparent Mode Timing ................................................................................. 102
10.2.1 Clock Frequency and Core Timing ........................................................... 102
10.2.2 Edge Placement Accuracy ...................................................................... 102
10.2.3 Transparent Mode Timing ...................................................................... 102
10.2.4 Error Reporting .................................................................................... 106
10.2.5 Transparent Mode IO Specifications ........................................................ 107
10.2.6 IO Implementation Guidelines ................................................................ 108
10.3 Transparent Mode Control and Status Registers................................................... 109
DDR
11.1
11.2
11.3
MemBIST
....................................................................................................... 111
MemBIST Overview ......................................................................................... 111
MemBIST Feature Summary ............................................................................. 112
MemBIST Operation......................................................................................... 113
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Intel® 6400/6402 Advanced Memory Buffer Datasheet
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