82544EI [INTEL]
Gigabit Ethernet Controller; 千兆位以太网控制器
| 型号： | 82544EI |
| 厂家： | 
INTEL |
| 描述： | Gigabit Ethernet Controller |
| 文件： | 总52页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82544EI Gigabit Ethernet Controller
Networking Silicon
Datasheet
Product Features
■ Full IEEE 802.3ab compliant
■ Provides adaptive Inter Frame Spacing
(IFS) capability, enabling collision
reduction in half duplex networks
■ Enables control of the transmission of
Pause packets through software or
hardware triggering
—Auto-Negotiation of speed, duplex, and
flow control configuration
■ 32/64-bit 33/66 MHz, PCI Rev 2.2
compliant host interface
■ Host interface compliant to the PCI-X
addendum, revision 1.0a, from 50 MHz to
133 MHz
■ Offers both hardware and software based
IEEE 802.3z Auto-Negotiation and Link
Setup for Ten-Bit Interface (TBI) mode
■ Internally implements IEEE 802.3 MII
management interface for monitoring and
control of the internal PHY
■ Offers an external link interface: TBI as
specified in IEEE 802.3z standard for 1000
Mb/s full duplex operation with 1.25 Gb/s
SERDES
■ Provides indications of receive FIFO status
through programming interface
■ Provides six activity and link indication
outputs to directly drive LEDs
■ Provides external parallel interface for up
to 4 Mb of Flash or Boot EPROM for boot
agent capability
■ 4-wire 64 x 16 serial EEPROM interface
for loading product configuration
information
■ Operating temperature: 0°C to 70° C
(ambient)
■ Targeted power dissipation is 2.5 W
■ Receive and transmit IP and TCP/UDP
maximum
checksum offloading capabilities
■ Provides boundary scan through IEEE
■ Automatic MDI crossover operation for
1149.1 (JTAG) Test Access Port
100BASE-TX and 10BASE-T modes
■ Leaded and lead-freea 416-pin Ball Grid
Array (BGA). Devices that are lead-free are
marked with a circled “e1” and have a
product code: NHXXXXX
■ IEEE 802.1q VLAN support
■ Implements enhanced ACPI register set and
power down functionality supporting D0
and D3 states, Wake on LAN capability
with Power Management Event support
a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.
The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazard-
ous Substances (RoHS) -banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Pack
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.
Revision 1.0
April 2005
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Revision History
Revision
Revision Date
Description
1.0
April 2005
Initial release (removed secret status)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82544EI Gigabit Ethernet Controller described in this document may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2005
*Third-party brands and names are the property of their respective owners.
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Contents
1.0
Overview ............................................................................................................................1
1.1
1.2
1.3
1.4
Scope ....................................................................................................................1
Reference Documents...........................................................................................1
Product Codes.......................................................................................................2
Block Diagram.......................................................................................................3
2.0
Additional Features of the 82544EI Gigabit Ethernet Controller ........................................5
2.1
2.2
2.3
2.4
2.5
2.6
PCI/PCI-X Features...............................................................................................5
PHY-Specific Features..........................................................................................5
Host Offloading Features ......................................................................................5
Additional Performance Features..........................................................................5
Additional Device Features ...................................................................................6
Technology Features.............................................................................................6
3.0
Signal Descriptions.............................................................................................................7
3.1
3.2
Signal Type Definitions..........................................................................................7
PCI/PCI-X Bus Interface........................................................................................7
3.2.1 PCI Address, Data and Control Signals ...................................................8
3.2.2 Arbitration Signals ..................................................................................10
3.2.3 Interrupt Signal.......................................................................................10
3.2.4 System Signals.......................................................................................10
3.2.5 Error Reporting Signals..........................................................................10
3.2.6 Power Management Signals ..................................................................11
3.2.7 Impedance Compensation Signals.........................................................11
Ten-Bit Interface (TBI) Signals............................................................................11
EEPROM/FLASH Interface Signals ....................................................................13
Miscellaneous Signals.........................................................................................13
3.5.1 LED Signals............................................................................................13
3.5.2 Other Signals..........................................................................................13
PHY Signals ........................................................................................................15
3.6.1 Crystal Signals .......................................................................................15
3.6.2 Analog Signals .......................................................................................15
Test Interface Signals..........................................................................................16
Power Supply Connections .................................................................................16
3.8.1 Digital Supplies.......................................................................................16
3.8.2 Analog Supplies .....................................................................................16
3.8.3 Ground and No Connects.......................................................................16
3.3
3.4
3.5
3.6
3.7
3.8
4.0
Targeted Electrical and Timing Specifications .................................................................17
4.1
4.2
4.3
4.4
4.5
Targeted Absolute Maximum Ratings ................................................................17
Recommended Operating Conditions ................................................................18
Targeted DC Specifications ................................................................................18
Targeted AC Characteristics ..............................................................................21
Targeted Timing Specifications...........................................................................23
4.5.1 PCI/PCI-X Bus Interface.........................................................................23
4.5.2 Targeted Link Interface Timing...............................................................27
4.5.3 FLASH Interface.....................................................................................30
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5.4 EEPROM Interface.................................................................................31
Package and Pinout Information......................................................................................33
5.0
5.1
5.2
5.3
5.4
Device Identification............................................................................................33
Mechanical Specifications...................................................................................33
Targeted Thermal Specifications ........................................................................35
Targeted Ball Mapping Diagram .........................................................................36
Figures
1
2
3
4
5
6
7
8
82544EI Gigabit Ethernet Controller Block Diagram.............................................3
AC Test Loads for General Output Pins..............................................................22
PCI/PCI-X Clock Timing......................................................................................23
PCI Bus Interface Output Timing Measurement Conditions ...............................24
PCI Bus Interface Input Timing Measurement Conditions ..................................25
TVAL (max) Rising Edge Test Load....................................................................26
TVAL (max) Falling Edge Test Load...................................................................26
TVAL (min) Test Load.........................................................................................26
TVAL Test Load (PCI 5V Signalling Environment)..............................................27
Output Slew Rate Test Load (PCI-X only) ..........................................................27
Link Interface Rise/Fall Timing............................................................................28
Transmit Interface Timing ...................................................................................28
Receive Interface Timing ....................................................................................29
Flash Read Timing..............................................................................................30
Flash Write Timing ..............................................................................................30
Device Identification:...........................................................................................33
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10
11
12
13
14
15
16
Tables
1
1
2
3
4
5
6
7
Product Ordering Codes .......................................................................................2
Absolute Maximum Ratings (Referenced to VSS [Ground]) ...............................17
Recommended Operating Conditions.................................................................18
DC Specifications................................................................................................18
Power Supply Characteristics – 1 .......................................................................18
Power Supply Characteristics – 2 .......................................................................19
AC Characteristics: 3.3 V Interfacing ..................................................................21
Switching Current................................................................................................21
25Mhz Clock Input Requirements.......................................................................21
Link Interface Clock Requirements .....................................................................21
EEPROM Interface Clock Requirements ............................................................21
AC Test Loads for General Output Pins..............................................................22
PCI/PCI-X Bus Interface Clock Parameters........................................................23
PCI/PCI-X BUS Interface Timing Parameters, , .................................................24
PCI/PCI-X Bus Interface Timing Measurement Conditions.................................25
Rise and Fall Time Definition ..............................................................................27
Transmit Interface Timing ...................................................................................28
Receive Interface Receive Timing ......................................................................29
Targeted Flash Read Operation Timing..............................................................30
Targeted Flash Write Operation Timing..............................................................31
EEPROM Interface Clock Timing........................................................................31
EEPROM Interface Clock Data Timing ...............................................................31
82544GC Gigabit Ethernet Controller Thermal Characteristics ..........................35
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
iv
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
1.0
Overview
The 82544EI Gigabit Ethernet Controller is an integrated third-generation Ethernet LAN
component capable of providing 1000, 100, and 10 Mbps data rates. It is a single-chip device,
containing both the MAC and PHY layer functions, and optimized for LAN on Motherboard
(LOM) designs, enterprise networking, and Internet appliances that use the Peripheral Component
Interconnect (PCI) and PCI-X bus backplanes.
The 82544EI utilizes a 32/64 bit, 33/66 MHz direct interface to the PCI bus, compliant with the
PCI Local Bus Specification, Revision 2.2. It also supports the emerging PCI-X extension to the
PCI Local Bus, Revision 1.0a. The controller interfaces with the host processor through on-chip
command and status registers and a shared host memory area, which is set up during initialization.
The 82544EI Gigabit Ethernet Controller provides a highly optimized architecture to deliver high
performance and PCI/PCI-X bus efficiency. Its hardware, acceleration features enable offloading
of various tasks, such as TCP/UDP/ IP checksum calculations and TCP segmentation, from the
host processor. The 82544EI device accommodates highly-configurable Ethernet designs, which
require minimal CPU overhead from interrupts and register accesses.
The physical layer circuitry provides an IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX and 10BASE-T applications. With the addition of an appropriate serializer/
deserializer (SERDES), the 82544EI controller also provides an Ethernet interface for 1000BASE-
SX or 1000BASE-LX applications.
The 82544EI Gigabit Ethernet Controller is packaged in a 27 mm x 27 mm, 416-ball grid array.
1.1
1.2
Scope
This document contains datasheet specifications for the 82544EI Gigabit Ethernet Controller
including signal descriptions, DC and AC parameters, packaging data, and pinout information.
Reference Documents
This document assumes that the designer is acquainted with high-speed design and board layout
techniques. The following documents provide additional information:
• 8254x Family of Gigabit Ethernet Controllers Software Developer’s Manual, Intel
Corporation.
• PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group.
• PCI-X Specification, Revision 1.0a, PCI Special Interest Group.
• PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.
• IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).
Datasheet
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
• IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers
(IEEE).
1.3
Product Codes
Table 1 lists the product ordering codes for the 82544EI.
Table 1. Product Ordering Codes
Device
Product Code
82544EI (Leaded)
FW82544EI
NH82544EI
82544EI (Lead Free)
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Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
1.4
Block Diagram
Figure 1. 82544EI Gigabit Ethernet Controller Block Diagram
PCI Core
EEPROM FLASH
Slave
DMA Function
Access
Descriptor Management
Logic
64KB
Packet
RAM
RX Filters
Control
Status
Logic
TX/RX MAC
CSMA/CD
(Perfect,
Multicast,
VLAN)
VLA
N
Statistics
TBI
(Fiber
Interface)
Transmit
PCS
Receive
PCS
Management
Interface
Trellis
Decoder
PHY
Control
Equalizer
Echo
Cancelation
Filter
A/D
Near End
Crosstalk
Cancelation
10Base-T
Receiver
D/A
AGC
Media Dependent Interface
10/100/1000
MDI [3:0] + / -
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
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Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
2.0
Additional Features of the 82544EI Gigabit Ethernet
Controller
2.1
PCI/PCI-X Features
• Operates in either 5V or 3.3V PCI signaling environments
• 64-bit addressing for systems with more than 4 GB of physical memory
• Efficient PCI bus master operation, supported by optimized internal DMA controller
• Command usage optimization for advanced PCI commands such as MWI, MRM and MRL,
and PCI-X commands such as MRD, MRB and MWB
2.2
2.3
PHY-Specific Features
• Complete full duplex and half duplex support
• Next page support
• Automatic polarity correction
• Digital implementation of adaptive equalizer and cancellers for echo and crosstalk
Host Offloading Features
• TCP segmentation (Large send)
• Packet filtering based on checksum errors
• Supports for various address filtering modes:
— 16 exact matches (unicast or multicast)
— 4096-bit hash filter for multicast frames
— Promiscuous unicast and promiscuous multicast transfer modes
• IEEE 802.1q VLAN support
— Ability to add and strip IEEE 802.1q VLAN tags
— Packet filtering based on VLAN tagging, supporting 4096 tags
• SNMP and RMON statistic counters
2.4
Additional Performance Features
• Programmable host memory receive buffers (256 B to 16 KB)
• Programmable cache line size from 16 B to 128 B for efficient usage of PCI bandwidth
Datasheet
5
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
• Implements a total of 64 KB of configurable receive and transmit data FIFOs:
— default allocation is 48 KB for Receive data FIFO and 16 KB for transmit data FIFO
• Descriptor ring management hardware for transmit and receive:
— optimized descriptor fetching and write-back mechanisms for efficient system memory
and PCI bandwidth usage
• Provides a mechanism for reducing the number of interrupts generated by receive and transmit
operations
• Supports reception and transmission of packets with length up to 16 KB
2.5
2.6
Additional Device Features
• Provides seven general-purpose user mode pins
• Supports little-endian byte ordering for both 32- and 64-bit systems
• Supports big-endian byte ordering for 64-bit systems
• Provides loopback capabilities
• Provides boundary scan through IEEE 1149.1 (JTAG) Test Access Port
Technology Features
• Implemented in 0.18µ process
• Packaged in 416 PBGA package (27 mm x 27 mm)
• Implemented as low power CMOS device
6
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.0
Signal Descriptions
Special Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales
office that you have the latest data sheet before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82544EI controller are electrically defined in the following fashion:
Name
Definition
I
A standard input-only digital signal.
O
A standard output-only digital signal.
TS
STS
A bi-directional, three-state digital input/output signal.
A sustained, digital, three-state signal that is driven by one owner at a time. An agent that drives
an STS pin low must actively drive it high for at least one clock before letting it float. The next
owner of the signal cannot start driving it any sooner than one clock after it is released by the
previous owner.
OD
An open-drain digital signal. It is wired-OR’ed with other agents. The signaling agent asserts the
signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up
resistor may take two or three clock periods to fully restore the signal to the deasserted state.
A
P
PHY analog data signal.
A power connection, voltage reference, or other reference connection.
3.2
PCI/PCI-X Bus Interface
When RST# is asserted, the 82544EI Gigabit Ethernet Controller will not drive any PCI output or
bi-directional pins except PME#.
Datasheet
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.2.1
PCI Address, Data and Control Signals
Signal Name
AD[63:0]
Type
TS
Name and Function
Address and Data. Address and Data are multiplexed on the same PCI
pins. A bus transaction consists of an address phase followed by one or
more data phases.
The address phase is the clock cycle in which FRAME# is asserted. During
the address phase AD[63:0] contain a physical address (64 bits). For I/O,
this is a byte address; for configuration and memory, it is a DWORD
address. The 82544EI device uses little endian byte ordering.
During data phases AD[7:0] contain the least significant byte (LSB) and
AD[63:56] contain the most significant byte (MSB).
The 82544EI controller may be optionally connected to a 32-bit PCI Local
Bus. On a 32-bit bus, AD[63:32] and other signals corresponding to the
high order byte lanes do not participate in the bus cycle.
CBE[7:0]#
TS
TS
Bus Command and Byte Enables. Bus Command and Byte Enables are
multiplexed on the same PCI pins.
During the address phase of a transaction, CBE#[7:0] define the bus
command. During the data phase CBE#[7:0] are used as Byte Enables.
The Byte Enables are valid for the entire data phase and determine which
byte lanes carry meaningful data.
CBE#[0] applies to byte 0 (LSB) and CBE#[7] applies to byte 7 (MSB).
PAR
Parity. Parity issued to implement Even Parity across AD[31:0] and
CBE#[3:0]. PAR is stable and valid one clock after the address phase. For
data phases, PAR is stable and valid one clock after either IRDY# is
asserted on a write transaction or TRDY# is asserted after a read
transaction. Once PAR is valid, it remains valid until one clock after the
completion of the current data phase.
When the 82544EI controller is a bus master, it drives PAR for address and
write data phases. As a slave, it drives PAR for read data phases.
PAR64
TS
Parity 64. Parity issued to implement Even Parity across AD[63:32] and
CBE#[7:4]. PAR64 is stable and valid one clock after the address phase.
For data phases, PAR is stable and valid one clock after either IRDY# is
asserted on a write transaction or TRDY# is asserted after a read
transaction. Once PAR is valid, it remains valid until one clock after the
completion of the current data phase.
When the 82544EI controller is a bus master, it drives PAR64 for address
and write data phases. As a slave, it drives PAR64 for read data phases.
FRAME#
IRDY#
STS
STS
FRAME. FRAME# is driven by the 82544EI device to indicate the
beginning and duration of an access. FRAME# is asserted to indicate the
beginning of a bus transaction.
While FRAME# is asserted, data transfers continue. When FRAME# is
asserted, the transaction is in the final data phase.
Initiator Ready. IRDY# indicates the ability of the 82544EI controller (as a
bus master device) to complete the current data phase of the transaction.
IRDY# is used in conjunction with TRDY#.
A data phase is completed on any clock in which both IRDY# and TRDY#
are sampled asserted.
During a write, IRDY# indicates that valid data is present on AD[63:0].
During a read, it indicates the master is ready to accept data. Wait cycles
are inserted until both IRDY# and TRDY# are asserted together. The
82544EI controller drives IRDY# when acting as a master and samples it
when acting as a slave.
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Signal Name
TRDY#
Type
STS
Name and Function
Target Ready. TRDY# indicates the ability of the 82544EI controller (as a
selected device) to complete the current data phase of the transaction.
TRDY# is used in conjunction with IRDY#.
A data phase is completed on any clock in which both TRDY# and IRDY#
are sampled asserted. During a read, TRDY# indicates that valid data is
present on AD[63:0]. During a write, it indicates the target is ready to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted together. The 82544EI device drives IRDY# when acting as a
slave and samples it when acting as a master.
STOP#
STS
Stop. STOP# indicates the current target is requesting the master to stop
the current transaction. As a slave, the 82544EI controller drives STOP# to
request the bus master to stop the transaction. As a master, the 82544EI
controller receives STOP# from the slave and stops the current transaction.
IDSEL
I
Initialization Device Select. IDSEL is used by the 82544EI device as a
chip select during configuration read and write transactions.
DEVSEL#
STS
Device Select. When being actively driven by the 82544EI controller,
DEVSEL# indicates to the bus master that it has decoded its address as
the target of the current access. As an input, DEVSEL# indicates whether
any device on the bus has been selected.
VIO
P
VIO. VIO is a voltage reference for PCI interface (3.3 V or 5 V). It is used as
the clamping voltage.
NOTE: An external resistor is required between the voltage reference and
the VIO balls.The targeted resistor value is 100 KΩ.
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.2.2
Arbitration Signals
Signal Name
REQ64#
Type
TS
Name and Function
Request Transfer. REQ64# is generated by the current initiator to indicate
its desire to perform a 64-bit transfer. REQ64# has the same timing as the
FRAME# signal.
ACK64#
TS
Acknowledge Transfer. ACK64# is generated by the currently-addressed
target in response to a REQ64# assertion by the initiator. ACK64# has the
same timing as the DEVSEL# signal.
REQ#
GNT#
LOCK#
TS
Request Bus. REQ# indicates to the arbiter that the 82544EI controller
desires use of the bus. This is a point to point signal.
I
I
Grant Bus. GNT# indicates to the 82544EI device that access to the bus
has been granted. This is a point to point signal
Lock Bus. LOCK# is asserted by an initiator to require sole access to a
target memory device during two or more separate transfers. The 82544EI
device does not implement bus locking.
3.2.3
3.2.4
Interrupt Signal
Signal Name
Type
TS
Name and Function
INTA#
Interrupt A. The signal is used to request an interrupt by the 82544EI
controller. This is an active low, level-triggered interrupt signal.
System Signals
Signal Name
Type
Name and Function
CLK
I
I
I
PCI_Clock. CLK provides timing for all transactions on the PCI bus and is
an input to the 82544EI device. All other PCI signals, except RST# and
INTA# lines are sampled on the rising edge of CLK. All other timing
parameters are defined with respect to this edge.
M66EN
RST#
66 MHz Enable. M66EN indicates whether the system bus is enabled for
66MHz if the slot is capable of that operating frequency. This signal is
ignored by the 82544EI controller, but should be connected properly for
future compatibility.
PCI Reset. Most of the internal state of the 82544EI controller is reset on
the de-assertion (rising edge) of RST#. Whenever RST# is asserted, all
PCI output signals except PME# are floated and inputs are ignored. The
PME# context is preserved, depending on power management settings.
3.2.5
Error Reporting Signals
Signal Name
SERR#
Type
OD
Name and Function
System Error. SERR# is used by the 82544EI controller to report address
parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
PERR#
STS
Parity Error. PERR# is used by the 82544EI controller to report data parity
errors during all PCI transactions except by a Special Cycle. PERR# is
sustained tri-state and must be driven active by the 82544EI controller
receive data two clocks following the data when a data parity error is
detected. The minimum duration of PERR# is one clock for each data phase
that a data parity error is detected.
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Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.2.6
Power Management Signals
Signal Name
Type
Name and Function
LAN_PWR_GOOD
I
Power Good (Power-On Reset). The LAN_PWR_GOOD signal
indicates that good power is available for 82544EI device. When the
signal is zero, the 82544EI controller will hold the entire chip in reset state
and float all PCI signals.
PME#
OD
Power Management Event. The 82544EI device will drive this signal to
zero when it receives a wakeup event and either the PME_En bit in the
Power Management Control / Status Register is 1 or the Advanced Power
Management Enable (APME) bit of the Wake Up Control Register (WUC)
is 1.
APM_WAKEUP
AUX_PWR
O
I
Advance Power Management Wakeup. When APM Wakeup is enabled
in the 82544EI controller and the 82544EI controller receives a Magic
Packet* it will set this signal to a logic 1 for 50 ms.
Auxiliary Power Available. If AUX_PWR equals 1, it indicates that
Auxiliary Power is available and the 82544EI device should support D3
power state.
cold
PWR_STATE[1:0]
O
Power State. The bits are set in the following power states:
00b = D0u, D1, or D3 state with wakeup disabled
•
No PHY operation is required
01b = D0u, D1, or D3 state with wakeup enabled
•
PHY operation is required in this state, although it may be at low
speed.
11b = D0 active state
Full speed PHY operation is required.
The resulting meaning of the bits is as follows:
•
•
•
Bit 1: asserted when normal (full power/speed) operation is required.
Bit 0: asserted when link is required.
The polarity of bit 0 and 1 may be individually inverted by setting the IPS0
and IPS1 bits in the Extended Device Control Register (CTRL_EXT),
respectively.
3.2.7
Impedance Compensation Signals
Signal Name
ZN_COMP
Type
I/O
Name and Function
N Device Impedance Compensation. Connect to an external precision
resistor (to VDD) that is indicative of the PCI/PCI-X trace load. This cell is
used to dynamically determine the drive strength required on the N-channel
transistors in the PCI/PCI-X IO cells.
ZP_COMP
I/O
P Device Impedance Compensation. Connect to an external precision
resistor (to VSS) that is indicative of the PCI/PCI-X trace load. This cell is
used to dynamically determine the drive strength required on the P-channel
transistors in the PCI/PCI-X IO cells.
3.3
Ten-Bit Interface (TBI) Signals
The TBI is a MAC interface that can connect to an external Serializer/Deserializer (SERDES)
device for fiber-based designs. When the 82544EI controller is not in TBI mode, the TBI signals
are in a high-impedance state.
Datasheet
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82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
The 82544EI device has a special GMII test mode for the IEEE Unfiltered Jitter Test. This test
mode reuses the TBI signals as GMII outputs. After PHY conformance testing is completed, it is
permissible to gang the TBI interface pins together to reduce the number of pulldown resistors
needed.
Signal Name
TBI_MODE
Type
Name and Function
I
TBI Mode Enable. This signal forces the device into TBI mode when
TBI_MODE is asserted (high).
TX_DATA[9:0]
O
Transmit Data. Parallel TBI data bus to be transmitted through a
serializer/deserializer (SERDES). If TBI mode is not used, connect these
pins to ground through pulldown resistors. During GMII test mode these
pins become GMII outputs.
GTX_CLK
EWRAP
O
O
Transmit Clock. Operates at 125 MHz. If TBI mode is not used, connect
this ball to ground through a pulldown resistor. During GMII test mode
this pin becomes the transmit clock test output.
Enable Wrap. EWRAP is low in normal operation. When it is high, the
SERDES device is forced to transceiver loopback the serialized transmit
data to the receiver. If TBI mode is not used, connect this ball to ground
through a pulldown resistor.
RX_DATA[9:0]
I
Receive Data. Parallel TBI data bus received from a serializer/
deserializer (SERDES). If TBI mode is not used, connect these balls to
ground through a pulldown resistor. During GMII test mode these pins
become GMII outputs.
RBC0
RBC1
I
I
Receive Clock. RBC0 is the 62.5 MHz receive clock. If TBI mode is not
used, connect this ball to ground through a pulldown resistor. During
GMII test mode this pin becomes an output.
Receive Clock: RBC1 is the 62.5 MHz receive clock shifted 180
degrees from RBC0. If TBI mode is not used, connect this ball to ground
through a pulldown resistor. During GMII test mode this pin becomes the
receive clock test output.
12
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.4
EEPROM/FLASH Interface Signals
Signal Name
EE_DI
Type
Name and Function
O
I
EEPROM DI. This pin is an output to the memory device.
EE_DO
EEPROM DO. This pin is an input from the memory device. Internal
pullup resistor provided.
EE_CS
EE_SK
O
O
EEPROM CSO. Used to enable the device.
EEPROM Serial Clock. The clock rate of the EEPROM interface is
approximately 1 MHz.
FL_ADDR[18:0]
FL_CS#
O
O
O
O
FLASH Address Outputs. Used to FLASH or Boot ROM
FLASH Chip Select. Used to enable FLASH or Boot ROM
FLASH Output Enable. Used to enable buffers in FLASH.
FLASH Write Enable Output. Used for write cycles.
FL_OE#
FL_WE#
FL_DATA[7:0]
TS
FLASH Data I/O. Bi-directional data bus for FLASH data. These
signals have internal pullup devices.
3.5
Miscellaneous Signals
3.5.1
LED Signals
Signal Name
LINK_UP#
Type
Name and Function
O
Link Up. LINK_UP# indicates link connectivity
RX_ACTIVITY#
OD
OD
Receive Activity. Flashes an LED to indicate link receive activity.
This output uses an open drain cell to allow a wired-OR of activity
signals.
TX_ACTIVITY#
Transmit Activity. Flashes an LED to indicate link transmit activity.
This output uses an open drain cell to allow a wired-OR of activity
signals.
LINK10#
OD
OD
OD
Link 10. Drives an LED to indicate link at 10 Mbps. This output uses
an open drain cell.
LINK100#
LINK1000#
Link 100. Drives an LED to indicate link at 100 Mbps. This output
uses an open drain cell.
Link 1000. Drives an LED to indicate link at 1000 Mbps. This output
uses an open drain cell.
3.5.2
Other Signals
Signal Name
Type
Name and Function
LOS
I
I
I
Loss of Signal. Loss of signal from the optical transceiver when
TBI_MODE=1
XOFF
XON
External XOFF. This is an external indication of the Above High
Threshold for flow control.
External XON. This provides an external indication of Below Low
Threshold for flow control.
Datasheet
13
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Signal Name
ABV_HI
Type
Name and Function
O
O
Above High Threshold. Output indicating the RX FIFO fullness is
above the programmed high threshold.
BLW_LO
Below Low Threshold. Output indicating the RX FIFO fullness is
below the programmed low threshold.
SDP[7:6]
SDP[4:0]
TS
S/W Defined Pins. These pins are reserved pins which are software
programmable with respect to input/output capability. These default
to inputs upon power up but may have their direction and output
values defined in the EEPROM. The upper four bits may be mapped
to the General Purpose Interrupt bits when configured as inputs.
SPECIAL NOTE: SDP5 is intentionally missing from the group of
software-defined pins.
TEST0
TEST1
I
Factory Test Pin. Connect this ball to ground through a pulldown
resistor.
Factory Test Pin. Attach an external pullup resistor to the pin to
ensure the test mode is disabled. Use a common value resistor such
as 1 KΩ (the value is not critical). Alternatively, the pin may be
connected directory to the 3.3V supply.
GMII_TEST[1:0]
COL_TEST
I
GMII Test Mode Pins. For normal operation, the test pins are
connected to ground through a common pulldown resistor. For PHY
Unfiltered Jitter Test, drive both pins high.
O
O
Collision Test Pin. For normal operation, these pins are connected
to ground through a pulldown resistor. During GMII test mode it is
driving as an output.
CRS_TEST
Carrier Sense Test Pin. For normal operation, this pin is connected
to ground through a pulldown resistor. It is driven as an output during
GMII test mode.
14
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.6
PHY Signals
3.6.1
Crystal Signals
Signal Name
Type
Name and Function
XTAL1
I
XTAL1. 25MHz +/- 30 ppm input; can be connected to an
oscillator or a crystal. If a crystal is used, XTAL2 must be
connected as well.
XTAL2
O
XTAL2. Output of internal oscillator circuit used to drive crystal
into oscillation. If an external oscillator is used, XTAL2 must be
disconnected.
3.6.2
Analog Signals
Signal Name
Type
Name and Function
REF
P
A
Reference. External 2.49 KΩ resistor connection to VSS.
MDI[0]+/-
Media Dependent Interface[0].
1000BASE-T:
In MDI configuration, MDI[0]+/- corresponds to
BI_DA+/- and in MDIX configuration MDI[0]+/-
corresponds to BI_DB+/-.
100BASE-TX: In MDI configuration, MDI[0]+/- is used for the
transmit pair and in MDIX configuration
MDI[0]+/- is used for the receive pair.
10BASE-T:
In MDI configuration, MDI[0]+/- is used for the
transmit pair and in MDIX configuration
MDI[0]+/- is used for the receive pair.
MDI[1]+/-
A
Media Dependent Interface[1].
1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to
BI_DB+/-, and in MDIX configuration, to the
BI_DA+/-.
100BASE-TX: In MDI configuration, MDI[1]+/- is used for the
receive pair, and in MDIX configuration,
the transmit pair.
10BASE-T:
In MDI configuration, MDI[1]+/- is used for the
receive pair, and in MDIX configuration,
the transmit pair.
MDI[2]+/-
MDI[3]+/-
A
A
Media Dependent Interface[2].
1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to
BI_DC+/-, and in MDIX configuration, to the
BI_DD+/-.
100BASE-TX: Unused.
10BASE-T: Unused.
Media Dependent Interface[3].
1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to
BI_DD+/-, and in MDIX configuration, to the
BI_DC+/-.
100BASE-TX: Unused.
10BASE-T: Unused.
Datasheet
15
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
3.7
Test Interface Signals
Signal Name
JTAG_TCK
Type
Name and Function
JTAG Clock. Input to device
I
JTAG_TDI
I
JTAG TDI. Input to device
JTAG TDO. Output from device
JTAG TMS. Input to device
JTAG_TDO
JTAG_TMS
JTAG_TRST#
O
I
I
JTAG Reset. Active low reset for JTAG. Terminate this signal
through a resistor to ground. Do not leave unconnected.
3.8
Power Supply Connections
3.8.1
Digital Supplies
Signal Name
Type
Name and Function
VDDO. 3.3 V I/O power supply.
VDDO
P
P
P
DVDDH
DVDDL
DVDDH. 1.8 V Digital core power supply.
DVDDL. 1.5 V Digital core power supply.
3.8.2
3.8.3
Analog Supplies
Signal Name
Type
Name and Function
AVDDH
AVDDL
P
P
AVDDH. 3.3 V Analog power supply.
AVDDL. 2.5 V Analog power supply.
Ground and No Connects
Signal Name
Type
Name and Function
Grounds.
GND
NO_CONNECT
P
P
No Connects. Do not connect to these pins to any circuit. Do not
use pullup or pulldown resistors.
16
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.0
Targeted Electrical and Timing Specifications
4.1
Targeted Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings (Referenced to VSS [Ground])a
Symbol
Parameter
Min
Max
Units
V
V
DC supply voltage on VDDD or AVDDH with
respect to VSS
VSS - 0.5
4.6
V
DD(3.3)
DC supply voltage on AVDDL with respect to
VSS
VSS - 0.5
VSS - 0.5
VSS - 0.5
4.6 or
V
V
V
DD(2.5)
DD(1.8)
DD(1.5)
DD
V
+ 0.5
DD(2.5)
(whichever is
less)b
V
V
V
DC supply voltage on DVDDH with respect to
VSS
4.6 or
V
+ 0.5
DD(2.5)
(whichever is
less)b
DC supply voltage on DVDDL with respect to
VSS
4.6 or
V
+ 0.5
DD(2.5)
(whichever is
less)b
DC supply voltage
VSS - 0.5
VSS - 0.5
VSS - 0.5
4.6
4.6
6.6
V
V
VI / VO
VI / VO
LVTTL input voltage
5 V compatible input voltage
DC output current (by cell type):
V
I
mA
O
I
I
I
I
I
I
I
I
3
OL = 1mA
7
OL = 2 mA
OL = 3 mA
OL = 6 mA
OL = 9 mA
OL = 12 mA
OL = 18 mA
OL = 24 mA
10
20
30
40
60
75
T
Storage temperature range
-40
125
°C
V
STG
ESD per MIL_STD-883 Test Method 3015,
Specification 2001V Latchup Over/Undershoot:
±150 mA, 125 C
V
DD
overstress:
(7.2 V)
V
DD(3.3)
a.
b.
Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as
the limits for normal device operations.
This specification applies to biasing the device to a steady state for an indefinite duration. During normal device powerup,
explicit power sequencing is not required.
Datasheet
17
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditionsa
Symbol
Parameter
Min
Max
Units
V
V
V
V
DC supply voltage on VDDD or AVDDHb
DC supply voltage on AVDDLc
DC supply voltage on DVDDHc
DC supply voltage on DVDDLc
PCI bus voltage reference
3.0
2.38
1.71
1.43
3.0
0
3.6
2.62
1.89
1.57
5.25
200
10
V
V
DD(3.3)
DD(2.5)
DD(1.8)
DD(1.5)
V
V
VIO
t /t
V
Input rise/fall time (normal input)
Input rise/fall time (Schmitt input)
Operating temperature range (ambient)
Junction temperature
ns
ms
C
R
F
t /t
0
r
f
T
0
70
A
T
≤125
C
J
a.
For normal device operations, adhere to the limits in this table. Sustained operation of a device at conditions exceeding
these values, even if they are within the absolute maximum rating limits, might result in permanent guaranteed if conditions
exceed recommended operating conditions.
b.
c.
It is recommended that VDD0 = AVDDH during powerup and normal operation.
It is recommended that both VDDO and AVVDH are greater than AVDDL > DVDDH > DVDDL during powerup. However,
voltage sequencing is not a strict requirement as long as the power supply ramp is faster than approximately 200 ms.
4.3
Targeted DC Specifications
Table 3. DC Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
DC supply voltage on VDDO or
AVDDH
3.00
3.3
3.60
V
DD(3.3)
V
V
V
DC supply voltage on AVDDL
DC supply voltage on DVDDH
DC supply voltage on DVDDL
2.38
1.71
1.43
2.5
1.8
1.5
2.62
1.89
1.57
V
V
V
DD(2.5)
DD(1.8)
DD(1.5)
Table 4. Power Supply Characteristics – 1 (Sheet 1 of 2)
Symbol
Parameter
Condition
Min
Typa
Maxb Units
I
3.3 V supply current
TBI mode
200
130
90
230
160
110
105
105
60
mA
CC(3.3)
1000BASE-T
100BASE-T
10BASE-T
85
Powerdownc
Quiescentd
85
50
18
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Table 4. Power Supply Characteristics – 1 (Sheet 2 of 2) (Continued)
Symbol
Parameter
Condition
Min
Typa
Maxb Units
I
2.5 V supply current
TBI mode
2.2
340
85
2.6
410
105
150
105
2.5
mA
mA
mA
CC(2.5)
CC(1.8)
CC(1.5)
1000BASE-T
100BASE-T
10BASE-T
Powerdownc
Quiescentd
TBI mode
125
85
2.0
170
300
160
110
90
I
1.8 V supply current
200
360
200
135
110
20
1000BASE-T
100BASE-T
10BASE-T
Powerdownc
Quiescentd
TBI mode
15
I
1.5 V supply current
0.4
200
0.3
0.2
0.1
0.1
0.5
1000BASE-T
100BASE-T
10BASE-T
Powerdownc
Quiescentd
240
0.4
0.3
0.15
0.15
a.
b.
Typical conditions are TA = 25 C, voltages are nominal. Where applicable, network traffic is moderate at full duplex and the
system interface is PCI 66 MHz.
Maximum conditions are TA = minimum, voltages are maximum. Where applicable, network traffic is continuous at full duplex
and the system interface is PCI-X 100 to 133 MHz.
c.
d.
In the powerdown mode, the controller is in the D3hot state, with PME# wake-up enabled. Link is present at 100 Mbps.
In the quiescent mode, the controller is in the D3cold state, with wake-up disabled. Link is not present.
Table 5. Power Supply Characteristics – 2 (Sheet 1 of 2)
Symbol
Parameter
Condition
LVTTL
Min
Typ
Max
Units
V
Input high voltage
Input low voltage
2.0
2.0
V
V
V
IH
DD(3.3)
5 V tolerant
5.5
3.3 V PCI
0.5
VDD(3.3)
DD(3.3)
V
LVTTL
VSS
0.8
V
IL
5 V tolerant
VSS
VSS
1.2
0.8
3.3 V PCI
0.3V
DD(3.3)
V
V
V
Switching threshold: Positive edge
Switching threshold: Negative edge
Schmitt trigger-hysteresis
LVTTL & 5 V tolerant
LVTTL & 5 V tolerant
2.4
1.8
1.5
V
V
V
T+
T+
H
0.6
0.3
Datasheet
19
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Table 5. Power Supply Characteristics – 2 (Sheet 2 of 2) (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
Input current
V
= V
or
-10
10
µA
IN
IN
DD(3.3)
VSS
Inputs with pull-down resistor (50 KΩ)
Inputs with pull-up resistor (5 KΩ)
Output low current:
V
V
= V
28
191
IN
IN
DD(3.3)
= VSS
-28
-191
I
mA
OL
Type LVTTL
3 mA
V
= 0.4 V
3
6
OL
6 mA
12 mA
3 mA
6 mA
12
3
Type: 5 V tol
6
I
Output high current
Type: LVTTL
mA
OH
3 mA
6 mA
3 mA
6 mA
V
= 0.4 V
-3
-6
-2
-2
OL
Type: 5 V tol
V
Output high voltage
LVTTL
OH
I
I
I
= 0 mA
V
V
V
V
OH
OH
OH
DD(3.3)
-0.1
5 V tolerant
= 0 mA
DD(3.3)
-0.2
3.3 V PCI
= -500 µA
0.9V
DD(3.3)
V
Output low voltage
LVTTL
OL
I
I
I
= 0 mA
0.1
0.1
OL
OL
OL
5 V tolerant
= 0 mA
3.3 V PCI
= 1500 µA
0.1V
DD(3.3)
I
I
Off-state output leakage current
Output short circuit current
Input capacitancea
V
= V or VSS
-10
10
µA
µA
pF
OZ
O
DD
-250
OS
C
Input and bi-
4
IN
directional buffers
5 V tolerant
Output buffers
5 V tolerant
8
6
C
Output capacitancea
pF
OUT
10
a.
VDD(3.3) = 0 V; TA = 25 C; f = 1 MHz
20
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.4
Targeted AC Characteristics
Table 6. AC Characteristics: 3.3 V Interfacing
Symbol
Parameter
Min
Typ
Max
Units
f
CLK frequency in PCI mode
CLK frequency in PCI-X mode
66
MHz
PCICLK
66
133
Table 7. Switching Current
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
Switching current high
Switching current high
Switching current low
Switching current low
V
V
V
V
= 0.3V
= 0.7V
= 0.6V
TBD
mA
mA
mA
mA
OH(min)
OH(max)
OL(min)
OL(max)
OUT
OUT
OUT
OUT
CC(3.3)
CC(3.3)
CC(3.3)
I
I
I
TBD
TBD
TBD
= 0.18V
CC(3.3)
Table 8. 25Mhz Clock Input Requirements
Symbol
Parametera
Min
Typ
25
Max
25 + 50 ppm
Units
MHz
f
TX_CLK_IN Frequency
25 – 50 ppm
i_TX_CLK
a.
This parameter applies to an oscillator connected to the XTAL1 input. Alternatively, a crystal may be connected to XTAL1
and XTAL 2 as the frequency source for the internal oscillator.
Table 9. Link Interface Clock Requirements
Symbol
Parameter
Min
Typ
Max
Units
a
f
GTX_CLK Frequency
125
MHz
GTX
GMII Mode (1000 Mb/s)
a.
GTX_CLK is used externally only for test purposes.
Table 10. EEPROM Interface Clock Requirements
Symbol
Parameter
Min
Typ
Max
Units
f
O_EE_SK Frequency
1
MHz
SK
Datasheet
21
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Table 11. AC Test Loads for General Output Pins
Symbol
Signal Name
Value
Units
pF
C
C
TDO
10
16
L
L
EWRAP, GTX_CLK, ABV_HI, BLW_LO, PWR_STATE[1:0],
APM_WAKEUP, PME#, TX_DATA,[9:0], SDP[7:0]
pF
pF
pF
C
C
FL_ADDR[18:0], FL_OE#, FL_CS#, FL_WE#, FL_DATA[7:0],
EE_SK, EE_DI
18
20
L
L
RX_ACTIVITY, TX_ACTIVITY, LINK_UP
Figure 2. AC Test Loads for General Output Pins
CL
22
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5
Targeted Timing Specifications
Note: Timing specifications are preliminary and subject to change.
4.5.1
PCI/PCI-X Bus Interface
4.5.1.1
PCI/PCI-X Bus Interface Clock
Table 12. PCI/PCI-X Bus Interface Clock Parameters
PCI-X
PCI-X
PCI
PCI
133 MHz
66 MHz
66 MHz
33 MHz
Symbol
Parametera
Units Notes
Min
Max
Min
Max
Min
Max
Min
Max
T
CLK Cycle Time
CLK High Time
CLK Low Time
CLK Slew Rate
RST# Slew Rateb
7.5
3
20
15
6
20
15
6
30
30
11
11
1
∞
ns
ns
ns
CYC
T
T
H
L
3
6
6
1.5
50
4
1.5
50
4
1.5
50
4
4
V/ns
a
b
50
mV/
ns
a.
b.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform as shown.
The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal, and ensures that system
noise cannot render an otherwise monotonic signal to appear to bounce in the switching range.
Figure 3. PCI/PCI-X Clock Timing
Tcyc
3.3 V Clock
Th
0.6 Vcc
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc p-to-p
(minimum)
0.2 Vcc
Tl
Datasheet
23
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5.1.2
PCI/PCI-X BUS Interface Timing
Table 13. PCI/PCI-X BUS Interface Timing Parametersa, b, c
PCI-X 133 MHz
PCI-X 66 MHz
PCI 66 MHz
PCI 33 MHz
Note
s
Symbol
Parameter
Units
Min
Max
Min
Max
Min
Max
Min
Max
CLK to Signal Valid Delay
- bused signals
T
0.7
3.8
0.7
3.8
2
6
2
11
ns
ns
a,b,c
a,b,c
VAL
CLK to Signal Valid Delay
- point-to-point signals
T
(ptp)
0.7
0
3.8
7
0.7
0
3.8
7
2
2
6
2
2
12
28
VAL
T
T
Float to Active Delay
Active to Float Delay
ns
ns
a
a
ON
14
OFF
Input Setup Time to -
bused signals
T
1.2
1.2
1.7
1.7
3
5
7
ns
c
c
SU
Input Setup Time to CLK -
point-to-point signals
T
T
T
(ptp)
10,12
ns
ns
ns
SU
Input Hold Time from CLK
0.5
0.5
0
0
H
REQ64# to RST# setup
time
10*
10*
10*
CYC
10*
CYC
RRSU
T
T
T
T
CYC
CYC
RST# to REQ64# hold
time
T
0
0
0
0
ns
RRH
a.
Output timing measurement as shown.
b.
REQ# and GNT# are point-to-point signals, and have different output valid delay and input set up times than do bused signals. GNT# has a set
up of 10; REQ# has a set up of 12. All other signals are bused
c.
Input timing measurement as shown.
Figure 4. PCI Bus Interface Output Timing Measurement Conditions
VTH
PCI_CLK
VTEST
V
TL
Output
Delay
VTEST
VSTEP(3.3VSignalling)
≤
output current leakage current
Tri-State
Output
TON
TOFF
24
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Figure 5. PCI Bus Interface Input Timing Measurement Conditions
V
V
TH
TL
PCI_CLK
V
TEST
H
T
SU
T
V
TH
Input
Valid
Input
V
MAX
V
TEST
V
TEST
V
TL
Table 14. PCI/PCI-X Bus Interface Timing Measurement Conditions
PCI 66
MHz 3.3V
Symbol
TH
Parameter
PCI-X
0.6*V
Units
Notes
V
V
V
Input Measurement Test
Voltage (high)
0.6*V
0.2*V
0.4*V
1.5
V
V
V
CC
CC
CC
CC
Input Measurement Test
Voltage (low)
0.25*V
CC
TL
Output Measurement Test
Voltage
0.4*V
1.5
TEST
CC
Input Signal Slew Rate
V / ns
Datasheet
25
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Figure 6. TVAL (max) Rising Edge Test Load
Pin
Test
Point
1/2 inch max.
25Ω
10 pF
Figure 7. TVAL (max) Falling Edge Test Load
Pin
Test
Point
1/2 inch max.
25Ω
VCC
10 pF
Figure 8. TVAL (min) Test Load
Pin
Test
Point
1/2 inch max.
10 pF
1kΩ
1kΩ
VCC
26
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Figure 9. TVAL Test Load (PCI 5V Signalling Environment)
Pin
Test
Point
1/2 inch max.
50 pF
Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.
Figure 10. Output Slew Rate Test Load (PCI-X only)
Pin
Test
Point
1/2 inch max.
VCC
10 pF
140 Ω
140 Ω
4.5.2
Targeted Link Interface Timing
4.5.2.1
Link Interface Rise and Fall Time
Table 15. Rise and Fall Time Definition
Symbol
Parameter
Clock Rise Time
Condition
Min
Max
Units
T
0.8V to 2.0V
2.0V to 0.8V
0.8V to 2.0V
2.0V to 0.8V
0.7
0.7
0.7
0.7
ns
ns
ns
ns
R
T
Clock Fall Time
Data Rise Time
Data Fall Time
F
T
R
T
F
Datasheet
27
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Figure 11. Link Interface Rise/Fall Timing
2.0 V
0.8 V
T
R
T
F
4.5.2.2
Link Interface Transmit Timing
Figure 12. Transmit Interface Timing
1.4V
TX_CLOCK
T
SU
T
H
TX_DATA[9:0]
Valid Data
T
PERIOD
Table 16. Transmit Interface Timing
Symbol
Parameter
Min
Typ
Max
Units
GTX_CLK Perioda
T
PERIOD
TBI Mode (1000 Mb/s)
8
ns
ns
ns
%
T
T
T
Data Setup to Rising GTX_CLK
Data Hold from Rising GTX_CLK
GTX_CLK Duty Cycle
2.5
1.0
SETUP
HOLD
DUTY
40
60
a.
±100 ppm tolerance on GTX_CLK
28
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5.2.3
Link Interface Receive Interface Timing
Figure 13. Receive Interface Timing
1.4V
RBC1
T
SU
T
H
2.0V
RX_DATA[9:0]
0.8V
COMMA
Code_Group
Valid
Data
2.0V
0.8V
COM_DET
T
A-B
T
SU
T
H
1.4V
RBC0
Table 17. Receive Interface Receive Timing
Symbol
Parameter
Min
Typ
Max
Units
RBC0/RBC1 Frequency
TBI Mode (1000Mb/s)
T
FREQ
62.5
2.5
1
MHz
ns
T
T
T
T
Data Setup before Rising RBC0 / RBC1
Data Hold after Rising RBC0 / RBC1
RBC0 / RBC1 Duty Cycle
SETUP
HOLD
DUTY
ns
40
60
%
RBC0 / RBC1 Skew
7.5
8.5
ns
A-B
Datasheet
29
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5.3
FLASH Interface
Figure 14. Flash Read Timing
0ns
250ns
Flash CE#
Flash OE#
Flash WE#
Flash Address [18:0]
Flash Data
Table 18. Targeted Flash Read Operation Timing
Symbol
Parameter
Min
Typ
Max
Units
ns
T
Flash CE# or OE# to Read Data Delay
Flash Address Setup time
Data hold time
160
160
CE
T
ns
ns
ACC
T
0
HOLD
Figure 15. Flash Write Timing
0ns
250ns
500ns
Flash CE#
Flash OE#
Flash WE#
Flash Address [18:0]
Flash Data
30
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Table 19. Targeted Flash Write Operation Timing
Symbol
Parameter
Min
Typ
Max
Units
T
Flash Write Pulse Width (WE#)
Flash Address Hold Time
Flash Data Setup Time
160
ns
ns
ns
WE
T
0
AH
T
160
DS
4.5.4
EEPROM Interface
Table 20. EEPROM Interface Clock Timing
Symbol
Parameter
EE_SK Pulse widtha
Min
Typ
Max
Units
T
T
*128
ns
PW
PERIOD
a.
The EE_SK EEPROM clock output is derived from GTX_CLK.
Table 21. EEPROM Interface Clock Data Timing
Parametera
Symbol
Min
Typ
Max
Units
T
T
EE_DO Setup Time
EE_DO Hold Time
T
*2
ns
ns
DOS
CYC
0
DOH
a.
The EE_DO setup and hold time is a function of the CLK cycle time as indicated, but is referenced to O_EE_SK.
Datasheet
31
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Note: This page intentionally left blank.
32
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
5.0
Package and Pinout Information
The 82544EI controller is packaged in a space-saving, 416-lead, ball grid array (BGA) package
that measures 27 mm x 27 mm, with a nominal ball pitch of 1 mm.
5.1
Device Identification
Figure 16. Device Identification:
5.2
Mechanical Specifications
The drawing on the following page indicates the complete package dimensions:
Datasheet
33
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
34
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
5.3
Targeted Thermal Specifications
The 82544EI device is specified for operation when TA (ambient temperature) is within the range
of 0° − 55°C.
TC (case temperature) is calculated using the equation:
TC = TA + P (θJA - θ JC
)
TJ (junction temperature) is calculated using the equation:
TJ = TA + P θJA
P (power consumption) is calculated by using the typical Icc as indicated in Table 4 and nominal
Vcc. The thermal resistances are shown in Table 22.
Table 22. 82544GC Gigabit Ethernet Controller Thermal Characteristics
Value @
Given Airflow (m/s)
Symbol
Parameter
Units
0
1
2
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
16.6 14.6 13.7 °C/Watt
0.4 0.4
0.4 °C/Watt
θJA
θ JC
Thermal resistances are determined empirically with test devices mounted on standard thermal test
boards. Real system designs may have somewhat different characteristics due to board thickness,
arrangement of ground planes, and proximity of other components. Use case temperature
measurements to assure that the 82544EI device is operating under recommended conditions.
Datasheet
35
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
5.4
Targeted Ball Mapping Diagram
The figure below represents the overall targeted signal ballout map from a top view. Following the
figure is a table (in two-column format) mapping the signal names to targeted ball numbers and pad
cell types:
Note: The 82544EI device employs five categories of VDD connections:
• VDDO (3.3V)
• DVDDH (1.8V)
• AVDDH (Analog 3.3V)
• AVDDL (Analog 2.5V)
• DVDDL (1.5V)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
36
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
Ball #
Signal Name
(IN/OUT/BI-DIR)
PCI Address, Data and Control Signals
AF18
AD0
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
AD1
AD17
AF17
AC16
AE16
AF16
AC15
AD15
AC14
AE14
AF14
AD13
AC13
AF13
AE12
AC12
AF8
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AC7
AD7
AF7
AE6
AC6
AF6
AD5
AF4
AC1
AE4
AC2
AB3
AC3
AB1
AB4
P24
P23
R26
R25
R23
Datasheet
37
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
(IN/OUT/BI-DIR)
Signal Name
AD37
Ball #
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
T26
AD38
AD39
AD40
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AD56
AD57
AD58
AD59
AD60
AD61
AD62
AD63
CBE0#
CBE1#
CBE2#
CBE3#
CBE4#
CBE5#
CBE6#
CBE7#
PAR
T24
T23
U26
U25
U23
V26
V24
W26
W25
W23
Y26
Y24
Y23
AA26
AA25
AA23
AB26
AB24
AB23
AC25
AC24
AD23
AC22
AC21
AD21
AF21
AF15
AF12
AE8
AF5
AC20
AE20
AF20
AC19
AC11
AD19
AC8
PAR64
FRAME#
38
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
Ball #
Signal Name
IRDY#
(IN/OUT/BI-DIR)
PCI BI-DIR
PCI BI-DIR
AF9
TRDY#
STOP#
IDSEL
DEVSEL#
VIO
AD9
AE10
AC5
AF10
AF3
PCI BI-DIR
PCI BI-DIR
PCI BI-DIR
Power
VIO
Power
AF24
Arbitration Signals
PCI BI-DIR
REQ64#
ACK64#
REQ#
AF19
AC18
AA1
PCI BI-DIR
PCI BI-DIR
GNT#
PCI BI-DIR
AA4
LOCK#
PCI BI-DIR
AC10
Interrupt Signal
PCI BI-DIR
INTA#
W2
System Signals
PCI IN
CLK
Y3
M66EN
RST#
PCI IN
AE18
Y1
PCI IN
Error Reporting Signals
PCI BI-DIR
SERR#
PERR#
AD11
AF11
PCI BI-DIR
Power Management Signals
LAN_PWR_GOOD
PME#
IN
B21
AA2
P25
Y4
OPEN DRAIN
BI-DIR
PCI IN
BI-DIR
BI-DIR
APM_WAKEUP
AUX_PWR
PWR_STATE1
PWR_STATE0
V1
V4
Impedance Compensation Signals
ZN_COMP
IN
W1
W4
ZP_COMP
IN
TBI Interface Signals
TBI_MODE
TX_DATA0
TX_DATA1
TX_DATA2
TX_DATA3
IN
A21
A4
BI-DIR
BI-DIR
BI-DIR
BI-DIR
D5
C5
A5
Datasheet
39
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
(IN/OUT/BI-DIR)
Signal Name
TX_DATA4
Ball #
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
D6
TX_DATA5
TX_DATA6
TX_DATA7
TX_DATA8
TX_DATA9
GTX_CLK
EWRAP
B6
A6
D7
D8
A7
C7
D13
A8
RX_DATA0
RX_DATA1
RX_DATA2
RX_DATA3
RX_DATA4
RX_DATA5
RX_DATA6
RX_DATA7
RX_DATA8
RX_DATA9
RBC0
D9
B9
A9
D10
A10
C11
B11
C12
D12
B13
A12
RBC1
EEPROM/FLASH Interface Signals
EE_DI
BI-DIR
IN
D25
D24
D23
E24
M25
K26
K24
K25
J24
H25
J23
H24
J26
G26
L26
G23
F24
EE_DO
EE_CS
EE_SK
BI-DIR
BI-DIR
FL_ADDR0
FL_ADDR1
FL_ADDR2
FL_ADDR3
FL_ADDR4
FL_ADDR5
FL_ADDR6
FL_ADDR7
FL_ADDR8
FL_ADDR9
FL_ADDR10
FL_ADDR11
FL_ADDR12
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
40
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
Ball #
Signal Name
FL_ADDR13
(IN/OUT/BI-DIR)
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
LED Signals
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
Other Signals
IN
G25
F25
E26
H26
D26
F26
L23
H23
F23
M23
N26
N23
P26
M24
N24
M26
L25
FL_ADDR14
FL_ADDR15
FL_ADDR16
FL_ADDR17
FL_ADDR18
FL_CS#
FL_OE#
FL_WE#
FL_DATA0
FL_DATA1
FL_DATA2
FL_DATA3
FL_DATA4
FL_DATA5
FL_DATA6
FL_DATA7
LINK_UP#
P3
P1
R4
R3
R2
R1
RX_ACTIVITY#
TX_ACTIVITY#
LINK10#
LINK100#
LINK1000#
LOS
A14
C23
A23
C22
D21
G2
J1
XOFF
XON
IN
IN
ABV_HI
BLW_LO
SDP0
SDP1
SDP2
SDP3
SDP4
SDP6
SDP7
TEST0
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
J3
K4
K3
K2
K1
A13
Datasheet
41
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
(IN/OUT/BI-DIR)
Signal Name
TEST1
Ball #
IN
N1
GMII_TEST0
GMII_TEST1
COL_TEST
CRS_TEST
IN
IN
BI-DIR
BI-DIR
PHY Signals
XTAL1
XTAL2
REF
IN
OUT
B4
C4
E3
C1
C2
D1
D2
E1
E2
F1
F2
IN
MDI[0]-
MDI[0]+
MDI[1]-
MDI[1]+
MDI[2]-
MDI[2]+
MDI[3]-
MDI[3]+
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
BI-DIR
Test Interface Signals
IN
JTAG_TCK
JTAG_TDI
T3
U4
U2
U1
T1
IN
JTAG_TDO
JTAG_TMS
JTAG_TRST#
OUT
IN
IN
Digital Power Supplies
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
B5
B7
B10
B17
B19
B22
E25
J25
N25
P2
T2
T25
V2
V25
42
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
Ball #
Signal Name
VDDO
(IN/OUT/BI-DIR)
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
3.3V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.8V Power
1.5V Power
Y2
VDDO
Y25
AB2
AB25
AE5
AE7
AE9
AE11
AE13
AE15
AE17
AE19
AE21
D4
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDH
DVDDL
D14
D19
E23
J4
K10
K11
K16
K17
K23
L10
L17
T4
T10
T17
U10
U11
U16
U17
V23
AC4
AC9
AC17
AC23
C10
Datasheet
43
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
(IN/OUT/BI-DIR)
Signal Name
DVDDL
Ball #
1.5V Power
1.5V Power
1.5V Power
C13
C14
G3
DVDDL
DVDDL
Analog Power Supplies
AVDDH
AVDDH
AVDDH
AVDDH
AVDDL
AVDDL
AVDDL
AVDDL
3.3V Power
3.3V Power
3.3V Power
3.3V Power
2.5V Power
2.5V Power
2.5V Power
2.5V Power
Grounds and No Connects
Power
A22
D11
G4
AD3
D22
H2
H3
H4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
Power
A2
Power
A3
Power
A11
A24
A25
A26
B1
Power
Power
Power
Power
Power
B2
Power
B3
Power
B8
Power
B12
B24
B25
B26
C3
Power
Power
Power
Power
Power
C6
Power
C8
Power
C9
Power
C16
C18
C21
C24
C25
C26
Power
Power
Power
Power
Power
44
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
Ball #
Signal Name
(IN/OUT/BI-DIR)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
D3
E4
G24
H1
K12
K13
K14
K15
L1
L2
L3
L11
L12
L13
L14
L15
L16
L24
M1
M3
M4
M10
M11
M12
M13
M14
M15
M16
M17
N3
N4
N10
N11
N12
N13
N14
N15
N16
Datasheet
45
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
(IN/OUT/BI-DIR)
Signal Name
Ball #
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
N17
P4
P10
P11
P12
P13
P14
P15
P16
P17
R10
R11
R12
R13
R14
R15
R16
R17
R24
T11
T12
T13
T14
T15
T16
U3
U12
U13
U14
U15
U24
W3
W24
AA3
AA24
AD1
AD2
AD4
46
Datasheet
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
Ball #
Signal Name
(IN/OUT/BI-DIR)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
AD6
AD8
AD10
AD12
AD14
AD16
AD18
AD20
AD22
AD24
AD25
AD26
AE1
AE2
AE3
AE23
AE24
AE25
AE26
AF1
AF2
AF25
AF26
A15
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
A16
A17
A18
A19
A20
B14
B15
B16
B18
B20
B23
C15
C17
C19
Datasheet
47
82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
Cell Type
(IN/OUT/BI-DIR)
Signal Name
Ball #
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO-CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
NO_CONNECT
C20
D15
D16
D17
D18
D20
F3
F4
G1
J2
L4
M2
N1
N2
V3
AC26
AE22
AF22
AF23
48
Datasheet
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