82945GZ [INTEL]
DRAM Controller, 2G X 8, CMOS, 37.50 X 37.50 MM, FCBGA;
| 型号： | 82945GZ |
| 厂家： | 
INTEL |
| 描述： | DRAM Controller, 2G X 8, CMOS, 37.50 X 37.50 MM, FCBGA 动态存储器 外围集成电路 |
| 文件： | 总318页 (文件大小：1535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® 945G/945GZ/945GC/
945P/945PL Express Chipset
Family
Datasheet
- For the Intel® 82945G/82945GZ/82945GC Graphics and Memory
Controller Hub (GMCH) and Intel® 82945P/82945PL Memory
Controller Hub (MCH)
June 2008
Document Number: 307502-005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH may contain design defects or errors known as errata, which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading
Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See
http://www.intel.com/info/hyperthreading/ for more information including details on which processors support HT Technology.
Intel and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright© 2005-2008, Intel Corporation
2
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Contents
1
Introduction .......................................................................................................................17
1.1
1.2
1.3
Terminology..........................................................................................................21
Reference Documents..........................................................................................23
(G)MCH Overview................................................................................................23
1.3.1
1.3.2
1.3.3
1.3.4
Host Interface........................................................................................24
System Memory Interface.....................................................................24
Direct Media Interface (DMI).................................................................25
PCI Express* Interface (Intel® 82945G/82945GC/82945P/82945PL
(G)MCH Only).......................................................................................26
1.4
1.5
Graphics (Intel® 82945G/82945GC/82945GZ GMCH Only)................................27
Analog and SDVO Displays (Intel® 82945G/82945GC/82945GZ GMCH Only) ..29
1.5.1
1.5.2
1.5.3
System Interrupts..................................................................................29
(G)MCH Clocking..................................................................................29
Power Management..............................................................................30
2
Signal Description .............................................................................................................31
2.1
2.2
2.3
2.4
2.5
Host Interface Signals ..........................................................................................33
DDR2 DRAM Channel A Interface.......................................................................36
DDR2 DRAM Channel B Interface.......................................................................37
DDR2 DRAM Reference and Compensation.......................................................38
PCI Express* Interface Signals (Intel® 82945G/82945GC/82945P/82945PL
Only).....................................................................................................................38
2.6
2.7
2.8
2.9
Analog Display Signals (Intel® 82945G/82945GC/ 82945GZ GMCH Only) .......39
Clocks, Reset, and Miscellaneous .......................................................................40
Direct Media Interface (DMI) ................................................................................41
Intel® Serial DVO (SDVO) Interface (Intel® 82945G/82945GC/82945GZ GMCH
Only).....................................................................................................................41
2.10
2.11
Power and Ground ...............................................................................................43
Reset States and Pull-up/Pull-downs...................................................................44
3
Register Description..........................................................................................................49
3.1
3.2
3.3
Register Terminology ...........................................................................................50
Platform Configuration..........................................................................................50
Configuration Mechanisms...................................................................................53
3.3.1
3.3.2
Standard PCI Configuration Mechanism ..............................................53
PCI Express* Enhanced Configuration Mechanism (Intel®
82945G/82945GC/82945P/82945PL (G)MCH Only) ...........................53
3.4
Routing Configuration Accesses..........................................................................55
3.4.1
3.4.2
Internal Device Configuration Accesses...............................................56
Bridge Related Configuration Accesses...............................................56
3.4.2.1
PCI Express* Configuration Accesses (Intel®
82945G/82945GC/82945P/82945PL (G)MCH Only)..........56
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
3
3.4.2.2
DMI Configuration Accesses...............................................57
3.5
I/O Mapped Registers ..........................................................................................57
3.5.1
3.5.2
CONFIG_ADDRESS—Configuration Address Register ......................58
CONFIG_DATA—Configuration Data Register....................................59
4
Host Bridge/DRAM Controller Registers (D0:F0) .............................................................61
4.1 Device 0 Configuration Register Details ..............................................................63
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
VID—Vendor Identification (D0:F0)......................................................63
DID—Device Identification (D0:F0) ......................................................63
PCICMD—PCI Command (D0:F0).......................................................64
PCISTS—PCI Status (D0:F0)...............................................................65
RID—Revision Identification (D0:F0)....................................................66
CC—Class Code (D0:F0) .....................................................................66
MLT—Master Latency Timer (D0:F0)...................................................67
HDR—Header Type (D0:F0) ................................................................67
SVID—Subsystem Vendor Identification (D0:F0).................................67
4.1.10 SID—Subsystem Identification (D0:F0)................................................68
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ...............................................68
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ......................................69
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address
(D0:F0)..................................................................................................70
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0)
(Intel® 82945G/82945GC/82945P/82945PL (G)MCH Only).................71
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ......73
4.1.16 GGC—GMCH Graphics Control Register (D0:F0) (Intel®
82945G/82945GC/82945GZ GMCH Only)..........................................74
4.1.17 DEVEN—Device Enable (D0:F0) .........................................................75
4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0)..................................76
4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0)..................................77
4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0)..................................78
4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0)..................................79
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0)..................................80
4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0)..................................81
4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0)..................................82
4.1.25 LAC—Legacy Access Control (D0:F0).................................................83
4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0).......................................84
4.1.27 SMRAM—System Management RAM Control (D0:F0)........................85
4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) ..86
4.1.29 ERRSTS—Error Status (D0:F0) ...........................................................87
4.1.30 ERRCMD—Error Command (D0:F0) ...................................................88
4.1.31 SKPD—Scratchpad Data (D0:F0) ........................................................89
4.1.32 CAPID0—Capability Identifier (D0:F0) .................................................89
MCHBAR Register ...............................................................................................90
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
C0DRB0—Channel A DRAM Rank Boundary Address 0 ....................91
C0DRB1—Channel A DRAM Rank Boundary Address 1 ....................93
C0DRB2—Channel A DRAM Rank Boundary Address 2 ....................93
C0DRB3—Channel A DRAM Rank Boundary Address 3 ....................93
C0DRA0—Channel A DRAM Rank 0,1 Attribute .................................94
C0DRA2—Channel A DRAM Rank 2,3 Attribute .................................94
C0DCLKDIS—Channel A DRAM Clock Disable ..................................95
C0BNKARC—Channel A DRAM Bank Architecture ............................96
C0DRT1—Channel A DRAM Timing Register .....................................97
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 .................................98
4
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 ...............................100
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0 ..................100
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1 ..................100
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2 ..................100
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3 ..................101
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ...............................101
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ...............................101
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ................................101
4.2.19 C1BNKARC—Channel B Bank Architecture ......................................101
4.2.20 C1DRT1—Channel B DRAM Timing Register 1 ................................102
4.2.21 C1DRC0—Channel B DRAM Controller Mode 0 ...............................102
4.2.22 C1DRC1—Channel B DRAM Controller Mode 1 ...............................102
4.2.23 PMCFG—Power Management Configuration ....................................102
4.2.24 PMSTS—Power Management Status ................................................103
EPBAR Registers—Egress Port Register Summary .........................................104
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
EPESD—EP Element Self Description...............................................105
EPLE1D—EP Link Entry 1 Description ..............................................106
EPLE1A—EP Link Entry 1 Address....................................................107
EPLE2D—EP Link Entry 2 Description ..............................................107
EPLE2A—EP Link Entry 2 Address....................................................108
5
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL
Only)................................................................................................................................109
5.1
Configuration Register Details (D1:F0) ..............................................................112
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
VID1—Vendor Identification (D1:F0)..................................................112
DID1—Device Identification (D1:F0) ..................................................112
PCICMD1—PCI Command (D1:F0)...................................................113
PCISTS1—PCI Status (D1:F0)...........................................................115
RID1—Revision Identification (D1:F0)................................................116
CC1—Class Code (D1:F0) .................................................................116
CL1—Cache Line Size (D1:F0)..........................................................117
HDR1—Header Type (D1:F0) ............................................................117
PBUSN1—Primary Bus Number (D1:F0)...........................................117
5.1.10 SBUSN1—Secondary Bus Number (D1:F0) ......................................118
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) .................................118
5.1.12 IOBASE1—I/O Base Address (D1:F0) ...............................................119
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................119
5.1.14 SSTS1—Secondary Status (D1:F0)...................................................120
5.1.15 MBASE1—Memory Base Address (D1:F0)........................................121
5.1.16 MLIMIT1—Memory Limit Address (D1:F0).........................................122
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0)................123
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0).................124
5.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ...........................................124
5.1.20 INTRLINE1—Interrupt Line (D1:F0) ...................................................125
5.1.21 INTRPIN1—Interrupt Pin (D1:F0).......................................................125
5.1.22 BCTRL1—Bridge Control (D1:F0)......................................................126
5.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) ..................128
5.1.24 PM_CS1—Power Management Control/Status (D1:F0) ....................129
5.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ......130
5.1.26 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) ....................130
5.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0)....131
5.1.28 MC—Message Control (D1:F0)..........................................................132
5.1.29 MA—Message Address (D1:F0).........................................................133
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
5
5.1.30 MD—Message Data (D1:F0) ..............................................................133
5.1.31 PEG_CAPL—PCI Express* Capability List (D1:F0)...........................134
5.1.32 PEG_CAP—PCI Express* Capabilities (D1:F0).................................134
5.1.33 DCAP—Device Capabilities (D1:F0) ..................................................135
5.1.34 DCTL—Device Control (D1:F0)..........................................................136
5.1.35 DSTS—Device Status (D1:F0) ...........................................................137
5.1.36 LCAP—Link Capabilities (D1:F0) .......................................................138
5.1.37 LCTL—Link Control (D1:F0)...............................................................139
5.1.38 LSTS—Link Status (D1:F0) ................................................................140
5.1.39 SLOTCAP—Slot Capabilities (D1:F0) ................................................141
5.1.40 SLOTCTL—Slot Control (D1:F0)........................................................142
5.1.41 SLOTSTS—Slot Status (D1:F0) .........................................................143
5.1.42 RCTL—Root Control (D1:F0) .............................................................144
5.1.43 RSTS—Root Status (D1:F0)...............................................................145
5.1.44 PEG_LC—PCI Express* Legacy Control (D1:F0)..............................146
5.1.45 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) ......147
5.1.46 PVCCAP1—Port VC Capability Register 1 (D1:F0)...........................147
5.1.47 PVCCAP2—Port VC Capability Register 2 (D1:F0)...........................148
5.1.48 PVCCTL—Port VC Control (D1:F0) ...................................................148
5.1.49 VC0RCAP—VC0 Resource Capability (D1:F0) .................................149
5.1.50 VC0RCTL—VC0 Resource Control (D1:F0) ......................................149
5.1.51 VC0RSTS—VC0 Resource Status (D1:F0)........................................150
5.1.52 VC1RCAP—VC1 Resource Capability (D1:F0) .................................150
5.1.53 VC1RCTL—VC1 Resource Control (D1:F0) ......................................151
5.1.54 VC1RSTS—VC1 Resource Status (D1:F0)........................................152
5.1.55 RCLDECH—Root Complex Link Declaration Enhanced Capability
Header (D1:F0)...................................................................................152
5.1.56 ESD—Element Self Description (D1:F0)............................................153
5.1.57 LE1D—Link Entry 1 Description (D1:F0)............................................154
5.1.58 LE1A—Link Entry 1 Address (D1:F0).................................................154
5.1.59 UESTS—Uncorrectable Error Status (D1:F0)....................................155
5.1.60 UEMSK—Uncorrectable Error Mask (D1:F0).....................................156
5.1.61 CESTS—Correctable Error Status (D1:F0)........................................157
5.1.62 CEMSK—Correctable Error Mask (D1:F0).........................................158
5.1.63 PEG_SSTS—PCI Express* Sequence Status (D1:F0)......................159
6
Direct Media Interface (DMI) RCRB................................................................................161
6.1
DMI RCRB Configuration Register Details.........................................................162
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
DMIVCECH—DMI Virtual Channel Enhanced Capability Header .....162
DMIPVCCAP1—DMI Port VC Capability Register 1..........................162
DMIPVCCAP2—DMI Port VC Capability Register 2..........................163
DMIPVCCTL—DMI Port VC Control ..................................................163
DMIVC0RCAP—DMI VC0 Resource Capability ................................164
DMIVC0RCTL—DMI VC0 Resource Control .....................................165
DMIVC0RSTS—DMI VC0 Resource Status.......................................166
DMIVC1RCAP—DMI VC1 Resource Capability ................................166
DMIVC1RCTL—DMI VC1 Resource Control .....................................167
6.1.10 DMIVC1RSTS—DMI VC1 Resource Status.......................................167
6.1.11 DMILCAP—DMI Link Capabilities ......................................................168
6.1.12 DMILCTL—DMI Link Control..............................................................168
6.1.13 DMILSTS—DMI Link Status ...............................................................169
6.1.14 DMIUESTS—DMI Uncorrectable Error Status ...................................170
6.1.15 DMIUEMSK—DMI Uncorrectable Error Mask....................................171
6
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
6.1.16 DMICESTS—DMI Correctable Error Status.......................................172
7
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)173
7.1
Configuration Register Details (D2:F0) ..............................................................175
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
VID2—Vendor Identification (D2:F0)..................................................175
DID2—Device Identification (D2:F0) ..................................................175
PCICMD2—PCI Command (D2:F0)...................................................176
PCISTS2—PCI Status (D2:F0)...........................................................177
RID2—Revision Identification (D2:F0)................................................178
CC—Class Code (D2:F0) ...................................................................178
CLS—Cache Line Size (D2:F0)..........................................................179
MLT2—Master Latency Timer (D2:F0)...............................................179
HDR2—Header Type (D2:F0) ............................................................179
7.1.10 MMADR—Memory Mapped Range Address (D2:F0) ........................180
7.1.11 IOBAR—I/O Base Address (D2:F0) ...................................................181
7.1.12 GMADR—Graphics Memory Range Address (D2:F0).......................182
7.1.13 GTTADR—Graphics Translation Table Range Address (D2:F0).......182
7.1.14 SVID2—Subsystem Vendor Identification (D2:F0).............................183
7.1.15 SID2—Subsystem Identification (D2:F0)............................................183
7.1.16 ROMADR—Video BIOS ROM Base Address (D2:F0).......................183
7.1.17 CAPPOINT—Capabilities Pointer (D2:F0) .........................................184
7.1.18 INTRLINE—Interrupt Line (D2:F0) .....................................................184
7.1.19 INTRPIN—Interrupt Pin (D2:F0).........................................................184
7.1.20 MINGNT—Minimum Grant (D2:F0)....................................................185
7.1.21 MAXLAT—Maximum Latency (D2:F0) ...............................................185
7.1.22 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F0)
(Mirrored_D0_34) ...............................................................................185
7.1.23 MCAPID—Mirror of Device 0 Capability Identification (D2:F0)
(Mirrored_D0_E0)...............................................................................185
7.1.24 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0)
(Mirrored_D0_52) ...............................................................................186
7.1.25 MDEVEN—Mirror of Device 0 Device Enable (D2:F0)
(Mirrored_D0_54) ...............................................................................186
7.1.26 BSM—Base of “Stolen” Memory (D2:F0) ...........................................186
7.1.27 PMCAPID—Power Management Capabilities ID (D2:F0)..................187
7.1.28 PMCAP—Power Management Capabilities (D2:F0)..........................187
7.1.29 PMCS—Power Management Control/Status (D2:F0) ........................188
7.1.30 SWSMI—Software SMI (D2:F0) .........................................................188
7.1.31 ASLE—System Display Event Register (D2:F0) ................................189
7.1.32 ASLS—ASL Storage (D2:F0) .............................................................189
8
Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ
GMCH Only)....................................................................................................................191
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
VID2—Vendor Identification (D2:F1)..................................................192
DID2—Device Identification (D2:F1) ..................................................192
PCICMD2—PCI Command (D2:F1)...................................................193
PCISTS2—PCI Status (D2:F1)...........................................................194
RID2—Revision Identification (D2:F1)................................................195
CC—Class Code Register (D2:F1).....................................................195
CLS—Cache Line Size (D2:F1)..........................................................196
MLT2—Master Latency Timer (D2:F1)...............................................196
HDR2—Header Type Register (D2:F1)..............................................196
8.1.10 MMADR—Memory Mapped Range Address (D2:F1) ........................197
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
7
8.1.11 SVID2—Subsystem Vendor Identification (D2:F1).............................197
8.1.12 SID2—Subsystem Identification (D2:F1)............................................197
8.1.13 ROMADR—Video BIOS ROM Base Address (D2:F1).......................198
8.1.14 CAPPOINT—Capabilities Pointer (D2:F1) .........................................198
8.1.15 MINGNT—Minimum Grant Register (D2:F1)......................................198
8.1.16 MAXLAT—Maximum Latency (D2:F1) ...............................................198
8.1.17 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F1)
(Mirrored_D0_34) ...............................................................................199
8.1.18 MCAPID—Mirror of Device 0 Capability Identification (D2:F1)
(Mirrored_D0_E0)...............................................................................199
8.1.19 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F1)
(Mirrored_D0_52) ...............................................................................199
8.1.20 MDEVEN—Mirror of Device 0 Device Enable (D2:F1)
(Mirrored_D0_54) ...............................................................................199
8.1.21 BSM—Base of Stolen Memory Register (D2:F1) ...............................200
8.1.22 PMCAPID—Power Management Capabilities ID (D2:F1)..................200
8.1.23 PMCAP—Power Management Capabilities (D2:F1)..........................200
8.1.24 PMCS—Power Management Control/Status (D2:F1) ........................201
8.1.25 SWSMI—Software SMI (D2:F1) .........................................................201
8.1.26 ASLS—ASL Storage (D2:F1) .............................................................202
Device 2 – PCI I/O Registers .............................................................................203
8.2
8.2.1
8.2.2
MMIO Index—MMIO Address Register..............................................203
MMIO Data—MMIO Data Register.....................................................203
9
System Address Map......................................................................................................205
9.1
Legacy Address Range......................................................................................207
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
DOS Range (0h – 9_FFFFh) ..............................................................208
Legacy Video Area (A_0000h–B_FFFFh) ..........................................208
Expansion Area (C_0000h–D_FFFFh)...............................................209
Extended System BIOS Area (E_0000h–E_FFFFh)..........................210
System BIOS Area (F_0000h–F_FFFFh)...........................................210
Programmable Attribute Map (PAM) Memory Area Details................210
9.2
9.3
Main Memory Address Range (1 MB to TOLUD) ..............................................211
9.2.1
9.2.2
9.2.3
ISA Hole (15 MB–16 MB) ...................................................................212
TSEG ..................................................................................................212
Pre-allocated Memory.........................................................................212
PCI Memory Address Range (TOLUD – 4 GB) .................................................213
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
APIC Configuration Space (FEC0_0000h–FECF_FFFFh).................214
HSEG (FEDA_0000h–FEDB_FFFFh)................................................214
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................214
High BIOS Area ..................................................................................214
PCI Express* Configuration Address Space ......................................214
PCI Express* Graphics Attach (Intel®
82945G/82945GC/82945P/82945PL GMCH Only)............................215
AGP DRAM Graphics Aperture ..........................................................215
Graphics Memory Address Ranges (Intel® 82945G/82945GC/82945GZ
GMCH Only) .......................................................................................216
9.3.7
9.3.8
9.4
System Management Mode (SMM) ...................................................................216
9.4.1
9.4.2
9.4.3
9.4.4
SMM Space Definition ........................................................................217
SMM Space Restrictions ....................................................................217
SMM Space Combinations .................................................................218
SMM Control Combinations................................................................218
8
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
9.4.5
9.4.6
9.4.7
SMM Space Decode and Transaction Handling ................................219
Processor WB Transaction to an Enabled SMM Address Space ......219
SMM Access through GTT TLB (Intel® 82945G/82945GC/82945GZ
GMCH Only) .......................................................................................219
Memory Shadowing............................................................................219
I/O Address Space..............................................................................220
9.4.8
9.4.9
9.4.10 PCI Express* I/O Address Mapping ...................................................220
9.4.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping ............220
9.4.12 Legacy VGA and I/O Range Decode Rules .......................................221
10
Functional Description ....................................................................................................223
10.1
Host Interface .....................................................................................................223
10.1.1 FSB IOQ Depth...................................................................................223
10.1.2 FSB OOQ Depth.................................................................................223
10.1.3 FSB GTL+ Termination.......................................................................223
10.1.4 FSB Dynamic Bus Inversion...............................................................223
10.1.4.1 APIC Cluster Mode Support..............................................224
System Memory Controller.................................................................................224
10.2.1 System Memory Configuration Registers Overview...........................226
10.2.2 DRAM Technologies and Organization ..............................................226
10.2.2.1 Rules for Populating DIMM Slots ......................................228
10.2.2.2 System Memory Supported Configurations ......................229
10.2.2.3 Main Memory DRAM Address Translation and Decoding 229
10.2.3 DRAM Clock Generation ....................................................................232
10.2.4 Suspend to RAM and Resume ...........................................................232
10.2.5 DDR2 On Die Termination..................................................................232
PCI Express* (Intel® 82945G/82945GC/ 82945P/82945PL (G)MCH Only)......233
10.3.1 Transaction Layer...............................................................................233
10.3.2 Data Link Layer...................................................................................233
10.3.3 Physical Layer.....................................................................................233
Intel® Serial Digital Video Output (SDVO) (Intel® 82945G/82945GC/82945GZ
GMCH Only).......................................................................................................234
10.4.1 Intel® SDVO Capabilities.....................................................................234
10.4.2 Intel® SDVO Modes ............................................................................235
10.4.3 PCI Express* and Internal Graphics Simultaneous Operation (Intel®
82945G/82945GC GMCH Only).........................................................236
10.4.3.1 Standard PCI Express* Cards and Internal Graphics .......236
10.4.3.2 ADD2+ Cards (Concurrent SDVO and PCI Express*)......236
Integrated Graphics Device (Intel® 82945G/82945GC/82945GZ GMCH Only) 239
10.5.1 3D Graphics Pipeline..........................................................................239
10.5.2 3D Engine ...........................................................................................240
10.5.3 4X Faster Setup Engine......................................................................241
10.5.3.1 3D Primitives and Data Formats Support..........................241
10.5.3.2 Pixel Accurate “Fast” Scissoring and Clipping Operation .241
10.5.3.3 Depth Bias.........................................................................241
10.5.3.4 Backface Culling................................................................242
10.5.3.5 Scan Converter..................................................................242
10.5.3.6 Pixel Rasterization Rules ..................................................242
10.5.3.7 Pixel Pipeline.....................................................................242
10.5.3.8 Texture Samplers ..............................................................242
10.5.3.9 2D Functionality.................................................................242
10.5.4 Texture Engine....................................................................................243
10.2
10.3
10.4
10.5
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
9
10.5.4.1 Perspective Correct Texture Support................................243
10.5.4.2 Texture Formats and Storage ...........................................243
10.5.4.3 Texture Decompression ....................................................243
10.5.4.4 Texture ChromaKey ..........................................................243
10.5.4.5 Anti-Aliasing.......................................................................243
10.5.4.6 Texture Map Filtering ........................................................244
10.5.4.7 Multiple Texture Composition............................................244
10.5.4.8 Pixel Shader ......................................................................245
10.5.4.9 Cube Map Textures...........................................................245
10.5.4.10 4x4 Texture Filtering Includes Cube Maps........................245
10.5.5 Raster Engine .....................................................................................245
10.5.5.1 Texture Map Blending .......................................................245
10.5.5.2 Combining Intrinsic and Specular Color Components ......246
10.5.5.3 Color Shading Modes........................................................246
10.5.5.4 Color Dithering...................................................................246
10.5.5.5 Vertex and Per Pixel Fogging............................................246
10.5.5.6 Alpha Blending (Frame Buffer)..........................................247
10.5.5.7 Microsoft Direct X* API and SGI OpenGL* Logic Ops......247
10.5.5.8 Color Buffer Formats: 8-, 16-, or 32-bits per Pixel
(Destination Alpha)............................................................247
10.5.5.9 Depth Buffer ......................................................................248
10.5.5.10 Stencil Buffer .....................................................................248
10.5.5.11 Projective Textures............................................................248
10.5.6 2D Engine ...........................................................................................249
10.5.6.1 GMCH VGA Registers.......................................................249
10.5.6.2 Logical 128-bit Fixed BLT and 256 Fill Engine..................249
10.5.7 Video Engine.......................................................................................250
10.5.7.1 Hardware Motion Compensation.......................................250
10.5.7.2 Sub-Picture Support..........................................................250
10.5.8 Planes.................................................................................................250
10.5.8.1 Cursor Plane......................................................................251
10.5.8.2 Overlay Plane....................................................................251
10.5.8.3 Advanced Deinterlacing and Dynamic Bob and Weave ...252
10.5.9 Pipes...................................................................................................252
10.5.9.1 Clock Generator Units (DPLL) ..........................................252
Display Interfaces (Intel® 82945G/82945GC/82945GZ GMCH Only)................252
10.6.1 Analog Display Port Characteristics ...................................................253
10.6.1.1 Integrated RAMDAC..........................................................254
10.6.1.2 Sync Signals......................................................................254
10.6.1.3 VESA/VGA Mode ..............................................................254
10.6.1.4 DDC (Display Data Channel) ............................................254
10.6.2 Digital Display Interface......................................................................255
10.6.2.1 Multiplexed Digital Display Channels – Intel® SDVOB and
Intel® SDVOC ....................................................................255
10.6
10.6.3 Multiple Display Configurations ..........................................................257
10.7
10.8
Power Management ...........................................................................................258
Clocking..............................................................................................................258
11
Electrical Characteristics.................................................................................................261
11.1
Absolute Minimum and Maximum Ratings.........................................................261
11.1.1 Power Characteristics.........................................................................263
Signal Groups.....................................................................................................264
11.2
10
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
11.3
DC Characteristics .............................................................................................267
11.3.1 RGB/CRT DAC Display DC Characteristics (Intel®
82945G/82945GC/82945GZ GMCH Only).........................................270
12
13
Ballout and Package Information....................................................................................271
12.1
12.2
12.3
Ballout.................................................................................................................271
Ballout Table.......................................................................................................275
Package..............................................................................................................305
Testability........................................................................................................................308
13.1
13.2
13.3
13.4
13.5
Complimentary Pins ...........................................................................................308
XOR Test Mode Initialization..............................................................................309
XOR Chain Definition .........................................................................................310
XOR Chains........................................................................................................311
PADs Excluded from XOR Mode(s)...................................................................318
Figures
Figure 1-1. Intel® 945G Express Chipset System Block Diagram Example.....................18
Figure 1-2. Intel® 945GZ/82945GC Express Chipset System Block Diagram Example ..19
Figure 1-3. Intel® 945P/945PL Express Chipset System Block Diagram Example..........20
Figure 2-1. Signal Information Diagram............................................................................32
Figure 3-1. Conceptual Chipset Platform PCI Configuration Diagram .............................51
Figure 3-2. Register Organization.....................................................................................52
Figure 3-3. Memory Map-to-PCI Express* Device Configuration Space..........................54
Figure 3-4. Intel® 82945G/82945GC (G)MCH Configuration Cycle Flow Chart...............55
Figure 4-1. Link Declaration Topology............................................................................104
Figure 9-1. System Address Ranges..............................................................................207
Figure 9-2. Microsoft MS-DOS* Legacy Address Range ...............................................208
Figure 9-3. Main Memory Address Range......................................................................211
Figure 9-4. PCI Memory Address Range........................................................................213
Figure 10-1. System Memory Styles...............................................................................225
Figure 10-2. SDVO Conceptual Block Diagram..............................................................235
Figure 10-3. Concurrent SDVO / PCI Express* Non-Reversed Configurations.............237
Figure 10-4. Concurrent SDVO / PCI Express* Reversed Configurations.....................237
Figure 10-5. Concurrent SDVO / PCI Express* Signal Multiplexing...............................238
Figure 10-6. Integrated 3D Graphics Pipeline ................................................................240
Figure 10-7. System Clocking Example..........................................................................259
Figure 12-1. Intel® 82945G GMCH Ballout Diagram (Top View – Columns 43–30) ......272
Figure 12-2. Intel® 82945G GMCH Ballout Diagram (Top View – Columns 29–16) ......273
Figure 12-3. Intel® 82945G GMCH Ballout Diagram (Top View – Columns 15–1) ........274
Figure 12-4. (G)MCH Package Dimensions ...................................................................306
Figure 13-1. XOR Test Mode Initialization Cycles..........................................................309
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
11
Tables
Table 4-1. Host Bridge/DRAM Controller Register Address Map (D0:F0) .......................61
Table 4-2. MCHBAR Register Address Map ....................................................................90
Table 4-3. Egress Port Register Address Map ...............................................................104
Table 5-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0) ...........109
Table 6-1. DMI Register Address Map ...........................................................................161
Table 7-1. Integrated Graphics Device Register Address Map (D2:F0).........................173
Table 8-1. Device 2 Function 1 Register Address Map (D2:F1).....................................191
Table 9-1. Expansion Area Memory Segments..............................................................209
Table 9-2. Extended System BIOS Area Memory Segments.........................................210
Table 9-3. System BIOS Area Memory Segments .........................................................210
Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB
TSEG ............................................................................................................................. 212
Table 9-5. SMM Space ...................................................................................................218
Table 9-6. SMM Control..................................................................................................218
Table 10-1. Sample System Memory Organization with Interleaved Channels .............224
Table 10-2. Sample System Memory Organization with Asymmetric Channels ............224
Table 10-3. DDR2 DIMM Supported Configurations ......................................................229
Table 10-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) ......230
Table 10-5. DRAM Address Translation (Dual Channel Interleaved Mode)...................231
Table 10-6. Concurrent SDVO / PCI Express* Configuration Strap Controls ................236
Table 10-7. Display Port Characteristics ........................................................................253
Table 10-8. Analog Port Characteristics.........................................................................254
Table 11-1. Absolute Minimum and Maximum Ratings..................................................262
Table 11-2. Non Memory Power Characteristics............................................................263
Table 11-3. DDR2 Power Characteristics.......................................................................263
Table 11-4. Signal Groups..............................................................................................264
Table 11-5. DC Characteristics.......................................................................................267
Table 11-6. RGB/CRT DAC Display DC Characteristics: Functional Operating Range
(VCCA_DAC = 2.5 V 5%) ......................................................................................270
Table 12-1. Intel® 82945G//82945GZ/82945GC/82945P/82945PL (G)MCH Ballout Sorted
by Signal Name........................................................................................................275
Table 13-1. Complimentary Pins to Drive.......................................................................308
Table 13-2. XOR Chain Outputs.....................................................................................310
Table 13-3. XOR Chain 0................................................................................................311
Table 13-4. XOR Chain 1................................................................................................312
Table 13-5. XOR Chain 2................................................................................................313
Table 13-6. XOR Chain 3................................................................................................313
Table 13-7. XOR Chain 4................................................................................................314
Table 13-8. XOR Chain 5................................................................................................314
Table 13-9. XOR Chain 6................................................................................................315
Table 13-10. XOR Chain 7..............................................................................................316
Table 13-11. XOR Chain 8..............................................................................................316
Table 13-12. XOR Chain 9..............................................................................................317
Table 13-13. XOR Pad Exclusion List.............................................................................318
12
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Revision History
Rev
-001
-002
-003
-004
-005
Description
Date
Initial Release
May 2005
Added Intel® 82945PL specifications
Added Intel® 82945GZ specifications
Added Intel® 82945GC specifications
Updated Intel® 82945GC specifications
October 2005
December 2005
October 2006
June 2008
§
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
13
14
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Intel® 82945G/82945GZ/82945GC/82945P
/82945PL (G)MCH Features
Processor Interface
Integrated Graphics Device (82945G/GZ/GC only)
Core frequency of 400 MHz
1.6 GP/s pixel rate
High-Quality 3D Setup and Render Engine
High-Quality Texture Engine
VLD/iDCT for enabling dual Intel® High
Definition streams for MPEG playback
3D Graphics Rendering Enhancements
2D Graphics
Video Overlay
Multiple Overlay Functionality
Analog Display Support (82945G/GZ/GC only)
400 MHz Integrated 24-bit RAMDAC
Up to 2048x1536 @ 75 Hz refresh
Hardware Color Cursor Support
.
.
Intel® CoreTM2 Duo, Intel® Celeron 400 Series,
Intel® Pentium® 4 processor in the 90 nm process
in the LGA775 Land Grid Array package or
Intel® Pentium® D processor (supports 775-Land
package)
Intel® AtomTM 200 series and Intel AtomTM 300
Series (82945GC only)
Supports Pentium 4 processor FSB interrupt
delivery
533/800 MT/s (133/200 MHz) FSB
1066 MT/s (266 MHz) FSB (82945G/P only)
Supports Hyper-Threading Technology1
(HT Technology)
FSB Dynamic Bus Inversion (DBI)
32-bit host bus addressing
12-deep In-Order Queue
1-deep Defer Queue
GTL+ bus driver with integrated GTL
termination resistors
Supports a Cache Line Size of 64 bytes
System Memory
4 GB maximum memory
.
.
DDC2B Compliant Interface
Digital Display Support (82945G/GZ/GC only)
Two SDVO ports multiplexed with PCI Express
graphics interface
200 MHz dot clock on each 12-bit interface
Can combine two channels to form one larger
interface
Flat panels up to 2048x1536 @ 60 Hz or digital
CRT/HDTV at 1920x1080 @ 85Hz
Dual independent display options with digital
display (82945G only)
Intel® Extended Desktop and Dual Display
Zoom (82945G only)
Intel® Dual Display Clone and Dual Display
Twin
Multiplexed digital display channels (Supported
with ADD2 Card).
Supports TMDS transmitters or TV-Out encoders
ADD2/ADD2+ card uses PCI Express graphics
x16 connector (ADD2+ support for 945G only)
.
One or two 64-bit wide DDR2 SDRAM data
channels
DDR2 400, DDR2 533
DDR2 667 (82945G/ GC/P only)
Bandwidth up to 10.7 GB/s (DDR2 667) in dual-
channel Interleaved mode.
Non-ECC memory only
256-Mb, 512-Mb and 1-Gb DDR2 technologies
Only x8, x16, DDR2 devices with four banks and
also supports eight bank, 1-Gbit DDR2 devices.
Opportunistic refresh
Up to 32 simultaneously open pages in dual-
channel mode
SPD (Serial Presence Detect) scheme for DIMM
detection support
Suspend-to-RAM support using CKE
Supports configurations defined in the JEDEC
DDR2 DIMM specification only
DMI Interface
.
.
A chip-to-chip connection interface to Intel®
ICH7
2 GB/s point-to-point DMI to ICH7 (1 GB/s each
direction)
100 MHz reference clock (shared with PCI
Express graphics attach)
32-bit downstream addressing
Messaging and Error Handling
Package
PCI Express* Graphics Interface (82945G/GC/P/PL
only)
One x16 PCI Express port
.
Compatible with the PCI Express Base
Specification, Revision 1.0a
Raw bit rate on data pins of 2.5 Gb/s resulting in
a real bandwidth per pair of 250 MB/s
34 mm × 34 mm, 1202 balls, non-grid pattern
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
15
§
16
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
1 Introduction
The Intel® 945G/945GZ/945GC/945P/945PL Express chipsets are designed for use with the
Intel® CoreTM2 Duo, Intel® Celeron 400 series, Intel® Pentium® D processor, Intel® Pentium® 4
processor. Additionally, Intel® 945GC Express chipsets also support Intel® AtomTM Processor 200
Series and Intel® AtomTM Processor 300 Series. Each chipset contains two components: GMCH
(or MCH) for the host bridge and I/O Controller Hub 7 (ICH7) for the I/O subsystem. The
82945G GMCH is part of the 945G Express chipset, 82945GZ GMCH is part of the 945GZ
Express chipset, 82945GC GMCH is part of the 945GC Express chipset, 82945P MCH is part of
the 945P Express chipset, and 82945PL MCH is part of the 945PL Express chipset. The ICH7 is
the seventh generation I/O Controller Hub and provides a multitude of I/O related functions.
Figure 1-1, Figure 1-2, and Figure 1-3 show example system block diagrams for the 945G,
945GZ, 945GC and 945P/945PL Express chipsets.
This document is the datasheet for the Intel® 82945G Graphics and Memory Controller Hub
(GMCH), Intel® 82945GZ Graphics and Memory Controller Hub (GMCH), Intel® 82945GC
Graphics and Memory Controller Hub (GMCH), Intel® 82945P Memory Controller Hub (MCH),
and Intel® 82945PL Memory Controller Hub (MCH). Topics covered include; signal description,
system memory map, PCI register description, a description of the (G)MCH interfaces and major
functional units, electrical characteristics, ballout definitions, and package characteristics.
The primary differences between the 82945G GMCH, 82945GZ GMCH, 92945GC GMCH,
82945P MCH, and 82945PL are listed below:
Intel®
82945G
Intel®
82945GZ
Intel®
82945GC
Intel®
82945P
Intel®
82945PL
Intel® AtomTM
Processor 200
and 300 Series
No
No
Yes
Yes
No
No
No
No
Integrated
Graphics Device
(and associated
SDVO and
Yes
Yes
analog display
ports)
PCI Express
Interface
Yes
No
Yes
Yes
Yes
FSB Frequency
1066/800/533
MHz
800/533 MHz
800/533 MHz
1066/800/533
MHz
800/533
MHz
Memory Speed
DDR2-
DDR2-
DDR2-
DDR2-
DDR2-
667/533/400
533/400
667/533/400
667/533/400
533/400
System Memory
Maximum
4 GB
2 GB
2 GB
4 GB
2 GB
Note: Unless otherwise specified, the information in this document applies to Intel® 82945G Graphics
and Memory Controller Hub (GMCH), Intel® 82945GZ Graphics and Memory Controller Hub
(GMCH), Intel® 82945GC Graphics and Memory Controller Hub (MCH), Intel® 82945P Memory
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
17
Introduction
Controller Hub (MCH), and Intel® 82945PL Memory Controller Hub (MCH),. The term (G)MCH
refers to both the 82945G/82945GZ/82945GC GMCHs and 82945P/82945PL MCHs.
Note: Unless otherwise specified, ICH7 refers to the Intel® 82801GB ICH7 and 82801GR ICH7R I/O
Controller Hub 7 components.
Figure 1-1. Intel® 945G Express Chipset System Block Diagram Example
Processor
533/800/1066 MHz FSB
Intel® 945G Express Chipset
Analog
Display
VGA
System Memory
Add2 or
Add2+
Card
Display
Display
Channel A
Channel B
Intel® 82945G GMCH
DDR2
SDVO
OR
DDR2
PCI Express*
x16 Graphics
Graphics
Card
Display
DMI Interface
USB* 2.0
8 ports, 480 Mb/s
Power Management
IDE
Clock Generation
LAN Connect
4 SATA* Ports
Intel® ICH7 Family
AC '97/Intel® High
Definition Audio
CODECs
System
Management (TCO)
SMBus 2.0/I2C
PCI Express* x1
Intel® PCI Express
Gigabit Ethernet
PCI Bus
GPIO
SPI BIOS
LPC Interface
Super I/O
Other ASICs
(Optional)
TPM
(Optional)
Flash BIOS
Sys_Blk_945G
18
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
Figure 1-2. Intel® 945GZ/82945GC Express Chipset System Block Diagram Example
Processor
82945GZ/82945GC = 533/ 800 MHz FSB
Analog
Display
VGA
System Memory
ADD2 Card
Display
Display
Channel A
Channel B
DDR2
®
Intel 82945GZ/82945GC
GMCH
SDVO
®
DDR2
Intel 82945GC GMCH ONLY
PCI Express*
x16 Graphics
Graphics
Display
Card
DMI Interface
USB*2.0
8 ports, 480Mb/s
Power Management
Clock Generation
LAN Connect
IDE
4 SATA* Ports
Intel® ICH7 Family
®
System
AC'97/Intel High
Management(TCO)
Definition Audio
CODECs
SMBus2.0/I2C
PCI Express*x1
GPIO
®
Intel PCI Express
PCI Bus
Gigabit Ethernet
SPI BIOS
LPC Interface
Super I/O
Other ASICs
( Optional)
TPM
( Optiona)l
Flash BIOS
Sys_Blk_945G
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
19
Introduction
Figure 1-3. Intel® 945P/945PL Express Chipset System Block Diagram Example
Processor
82945P MCH: 533/800/1066 MHz FSB
82945PL MCH: 533/800 MHz FSB
Intel® 945P/945PL
Express Chipset
System Memory
DDR2
Intel® 82945P/82945PL
MCH
Channel A
Channel B
PCI Express*
x16 Graphics
Graphics
Card
Display
DDR2
DMI Interface
USB* 2.0
8 ports, 480 Mb/s
Power Management
IDE
Clock Generation
LAN Connect
4 SATA* Ports
Intel® ICH7 Family
AC '97/Intel® High
Definition Audio
CODECs
System
Management (TCO)
SMBus 2.0/I2C
PCI Express* x1
Intel® PCI Express
Gigabit Ethernet
PCI Bus
GPIO
SPI BIOS
LPC Interface
Super I/O
Other ASICs
(Optional)
TPM
(Optional)
Flash BIOS
Sys_Blk_945P-and-945PL
20
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
1.1
Terminology
Term
Description
Accelerated
Graphics Port
(AGP)
Refers to the AGP/PCI interface that was previously in the (G)MCH. It has been
replaced by PCI Express*.
ADD Card
AGP Digital Display Card. It provides digital display options for an Intel Graphics
Controller that supports ADD cards (DVOs multiplexed with AGP interface). It is keyed
like an AGP 4x card and plugs into an AGP connector. The AGP Digital Display Card
will not work with an Intel graphics controller that implements Intel® SDVO.
ADD2 Card
Advanced Digital Display Card – 2nd Generation. This card provides digital display
options for an Intel graphics controller that supports ADD2 cards. It plugs into a x16 PCI
Express* connector but uses the multiplexed SDVO interface. This Advanced Digital
Display Card will not work with an Intel graphics controller that supports Intel® DVO and
ADD cards.
ADD2+ Card
Advanced Digital Display Card – 2nd Generation. This card provides digital display
options for an Intel graphics controller that supports ADD2+ cards. It plugs into a x16
PCI Express connector but uses the multiplexed SDVO interface. The card adds Video
In capabilities to the platform. This Advanced Digital Display Card will not work with an
Intel graphics controller that supports DVO and ADD cards. It will function as an ADD2
card in an ADD2 supported system, but Video In capabilities will not work. This is only
supported on the Intel® 82945G GMCH.
Core
CRT
DBI
The internal base logic in the (G)MCH
Cathode Ray Tube
Dynamic Bus Inversion
DDR
DDR2
DMI
Double Data Rate SDRAM memory technology
A second generation Double Data Rate SDRAM memory technology
(G)MCH-Intel® ICH7 Direct Media Interface
DVI
Digital Video Interface. DVI is a specification that defines the connector and interface
for digital displays.
FSB
Front Side Bus. FSB is synonymous with Host or processor bus
Full Reset
Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN# and
PWROK are asserted.
GMCH
Graphics Memory Controller Hub component that contains the processor interface,
DRAM controller, x16 PCI Express port (typically, the external graphics interface), and
an Integrated Graphics Device (IGD). The GMCH communicates with the I/O Controller
Hub 7 (ICH7*) and other I/O controller hubs over the DMI interconnect. In this
document GMCH refers to the Intel 82945G GMCH and/or 82945GZ GMCH
components.
HDMI
High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-
definition video, plus multi-channel digital audio on a single cable. HDMI transmits all
ATSC HDTV standards and supports 8-channel digital audio, with bandwidth to spare
for future requirements and enhancements (additional details available through:
http://www.hdmi.org/)
Host
INTx
This term is used synonymously with processor.
An interrupt request signal where “x” stands for interrupts A, B, C, and D
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
21
Introduction
Term
Description
Intel® DVO
Digital Video Out port. This term is used for the first generation of Intel graphics
controller’s digital display channels. Digital display data is provided in a parallel format.
This interface is not electrically compatible with the 2nd generation digital display
channel discussed in this document – SDVO.
Intel® ICH7
Seventh generation I/O Controller Hub component that contains additional functionality
compared to previous ICHs. The I/O Controller Hub 7 component contains the primary
PCI interface, LPC interface, USB2, ATA-100, and other I/O functions. ICH7
communicates with the (G)MCH over a proprietary interconnect called DMI.
IGD
Internal Graphics Device.
Liquid Crystal Display.
LCD
LVDS
Low Voltage Differential Signaling. LVDS is a high speed, low power data transmission
standard used for display connections to LCD panels.
MCH
Memory Controller Hub. The MCH contains the processor interface, DRAM controller,
and x16 PCI Express port (typically, the external graphics interface). It communicates
with the I/O Controller Hub 7 (ICH7) and other I/O controller hubs over the DMI
interconnect. In this document MCH refers to the Intel 82945P MCH and/or 82945PL
MCH components.
MSI
Message Signaled Interrupt. MSI is a transaction initiated outside the host, conveying
interrupt information to the receiving agent through the same path that normally carries
read and write commands.
PCI Express*
Third Generation input/output graphics attach called PCI Express Graphics. PCI
Express is a high-speed serial interface. The PCI Express configuration is software
compatible with the existing PCI specifications. The specific PCI Express
implementation intended for connecting the (G)MCH to an external Graphics Controller
is a x16 link and replaces AGP.
Primary PCI
The Primary PCI is the physical PCI bus that is driven directly by the ICH7 component.
Communication between Primary PCI and the (G)MCH occurs over DMI. Note that the
Primary PCI bus is not PCI Bus 0 from a configuration standpoint.
Processor
SCI
Intel® Pentium® D processor and Intel® Pentium® 4 processor
System Control Interrupt. SCI is used in ACPI protocol.
SDVO
Serial Digital Video Out (SDVO). SDVO is a digital display channel that serially
transmits digital display data to an external SDVO device. The SDVO device accepts
this serialized format and then translates the data into the appropriate display format
(i.e., TMDS, LVDS, TV-Out). This interface is not electrically compatible with the
previous digital display channel – DVO. For the 82945G/82945GZ GMCH, the SDVO
interface is multiplexed on a portion of the x16 graphics PCI Express interface.
SDVO Device
SERR
Third party codec that uses SDVO as an input. May have a variety of output formats,
including DVI, LVDS, HDMI, TV-Out, etc.
System Error. SERR is an indication that an unrecoverable error has occurred on an
I/O bus.
SMI
System Management Interrupt. SMI is used to indicate any of several system conditions
(such as, thermal sensor events, throttling activated, access to System Management
RAM, chassis open, or other system state related activity).
Rank
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16
SDRAM devices in parallel ignoring ECC. These devices are usually, but not always,
mounted on a single side of a DIMM.
TMDS
Transition Minimized Differential Signaling. TMDS is a signaling interface from Silicon
Image that is used in DVI and HDMI.
22
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
Term
TOLM
Description
Top Of Low Memory. The highest address below 4 GB where a processor-initiated
memory read or write transaction will create a corresponding cycle to DRAM on the
memory interface.
VCO
UMA
Voltage Controlled Oscillator
Unified Memory Architecture. UMA describes an IGD using system memory for its
frame buffers.
1.2
Reference Documents
Document Name
Doc Number/Location
Intel® I/O Controller Hub 7 (ICH7) Family Datasheet
http://developer.intel.com//design/ch
ipsets/datashts/307013.htm
Intel® 945G/945GZ/82945GC/945P/945PL Express Chipset Family
Thermal and Mechanical Design Guidelines
http://developer.intel.com/design/chi
psets/designex/307504.htm
Intel® 945G/945GZ/82945GC/945P/945PL Express Chipset Family
Specification Update
http://developer.intel.com/design/chi
psets/specupdt/307503.htm
Advanced Configuration and Power Interface Specification,
Revision 2.0
http://www.acpi.info/
Advanced Configuration and Power Interface Specification,
Revision 1.0b
http://www.acpi.info/
The PCI Local Bus Specification, Revision 2.3
http://www.pcisig.com/specifications
http://www.pcisig.com/specifications
PCI Express* Specification, Revision 1.0a, July 22, 2002
1.3
(G)MCH Overview
The (G)MCH connects to the processor as shown in the previous system block diagrams. The
primary role of a (G)MCH in a system is to manage the flow of information between its
interfaces: the processor interface (FSB), the system memory interface (DRAM controller), the
integrated graphics interface (82945G/82945GZ/82945GC GMCH only), the external graphics
interface (PCI Express), and the I/O Controller through DMI interface. This includes arbitrating
between the four interfaces when each initiates transactions.
The (G)MCH supports one or two channels of DDR2 SDRAM. The (G)MCH also supports the
new PCI Express based external graphics attach. To increase system performance, the (G)MCH
incorporates several queues and a write cache. The (G)MCH also contains advanced desktop
power management logic.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
23
Introduction
1.3.1
Host Interface
The (G)MCH is optimized for the Intel® AtomTM 200 Series, Intel® AtomTM 300 Series based on
45nm process technology in a FCBGA 437 pins socket, Intel® CoreTM 2 Duo, Intel® Celeron 400
series, Intel® Pentium 4 processor in the 90 nm process in the LGA775 Land Grid Array package
and Intel® Pentium D processor in a LGA775 socket; Only the 82945GC (G)MCH are designed
for use with Intel® AtomTM 200 Series and Intel® AtomTM 300 Series. The (G)MCH supports FSB
frequencies using a scalable FSB Vcc_CPU. FSB frequencies supported are 133 MHz
(533 MT/s), 200 MHz (800 MT/s), and 266 MHz (1066 MT/s); only the 82945G/82945P
(G)MCH support 266 MHz (1066 MT/s).
The (G)MCH supports the Pentium 4 processor subset of the Extended Mode Scaleable Bus
Protocol. The primary enhancements over the Compatible Mode P6 bus protocol are source
synchronous double-pumped (2x) address and source synchronous quad-pumped (4x) data. Other
(G)MCH supported features of the host interface include: Hyper-Threading Technology (HT
Technology), Pentium 4 processor FSB interrupt delivery, FSB Dynamic Bus Inversion (DBI),
12-deep in-order queue, and a 1-deep defer queue.
The (G)MCH supports 32-bit host addressing, decoding up to 4 GB (2 GB for the
82945PL/82945GC/82945GZ) of the processor’s usable memory address space. Host-initiated I/O
cycles are decoded to PCI Express, DMI, or the (G)MCH configuration space. Host-initiated
memory cycles are decoded to PCI Express, DMI or main memory. PCI Express device accesses
to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated
from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped on the
host bus.
1.3.2
System Memory Interface
The (G)MCH integrates a system memory DDR2 controller with two, 64-bit wide interfaces.
Only Double Data Rate (DDR2) memory is supported; consequently, the buffers support only
SSTL_1.8 V signal interfaces. The memory controller interface is fully configurable through a set
of control registers. Features of the (G)MCH memory controller include:
Maximum memory size:
4 GB for 82945G GMCH and 82945P MCH
2 GB for 82945GZ/82945GC GMCH and 82945PL MCH
Directly supports one or two channels of memory (each channel consisting of 64 data lines)
The memory channels are asymmetric: "Stacked" channels are assigned addresses
serially. Channel B addresses are assigned after all Channel A addresses.
The memory channels are interleaved: Addresses are ping-ponged between the channels
after each cache line (64-B boundary).
Supports DDR2 400, DDR2 533, and DDR2 667. DDR2 667 is supported on
82945G/82945GC/82945P Only.
Available bandwidth up to 5.3 GB/s (DDR2 667) for single-channel mode or dual-channel
asymmetric mode and 10.7 GB/s (DDR2 667) in dual-channel Interleaved mode.
Supports DDR2 memory DIMM frequencies of 400 MHz, 533 MHz, and
667 MHz (82945G/82945GC/82945P Only). The speed used in all channels is the speed of
the slowest DIMM in the system.
Supports 256-Mb, 512-Mb, and 1-Gb DDR2 technologies for x8 and x16 devices.
24
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
Supports four banks for all DDR2 devices up to 512-Mbit density. Supports eight banks for
1-Gbit DDR2 devices.
DDR2-667 4-4-4 is Not supported.
Supports only unbuffered DIMMs.
Supports opportunistic refresh.
In dual channel mode the (G)MCH supports 32 simultaneously open pages.
SPD (Serial Presence Detect) scheme for DIMM detection support.
Suspend-to-RAM support using CKE.
Supports configurations defined in the JEDEC DDR2 DIMM specification only.
Directly supports two channels of non-ECC DDR2 DIMMs.
Supports Partial Writes to memory using Data Mask (DM) signals.
Supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric
operating modes.
Supports Enhanced Memory Interleave.
1.3.3
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and I/O
Controller Hub 7 (ICH7). This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions,
the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a
fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of
traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both
ends of the DMI link (i.e., the ICH7 and (G)MCH).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the (G)MCH Register Description.
A chip-to-chip connection interface to the ICH7
2 GB/s point-to-point DMI to ICH7 (1 GB/s each direction)
100 MHz reference clock (shared with PCI Express graphics attach)
32-bit downstream addressing
APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt”
broadcast message when initiated by the processor.
Message Signaled Interrupt (MSI) messages
SMI, SCI, and SERR error indication
Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
25
Introduction
1.3.4
PCI Express* Interface (Intel®
82945G/82945GC/82945P/82945PL (G)MCH Only)
The 82945G/82945GC/82945P/82945PL (G)MCH contains one 16-lane (x16) PCI Express port
intended for an external PCI Express graphics card. The PCI Express port is compliant to the PCI
Express* Base Specification, Revision 1.0a. The x16 port operates at a frequency of 2.5 Gb/s on
each lane while employing 8b/10b encoding, and supports a maximum theoretical bandwidth of 4
Gb/s each direction. The 82945G GMCH multiplexes the PCI Express interface with two Intel®
SDVO ports.
One, 16-lane PCI Express port intended for Graphics Attach, compatible to the PCI Express*
Base Specification, Revision 1.0a.
A base PCI Express frequency of 2.5 Gb/s only.
Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of 250 MB/s
given the 8b/10b encoding used to transmit data across this interface
Maximum theoretical realized bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16.
PCI Express extended configuration space. The first 256 bytes of configuration space is
aliased directly to the PCI Compatibility configuration space. The remaining portion of the
fixed 4-KB block of memory-mapped space above the first 256 bytes (starting at 100h) is
known as extended configuration space.
PCI Express Enhanced Addressing Mechanism. This mechanism accesses the device
configuration space in a flat memory mapped fashion.
Automatic discovery, negotiation, and training of link out of reset
Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-relaxed
ordering)
Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal
PCI 2.3 Configuration space as a PCI-to-PCI bridge)
Supports “static” lane numbering reversal. This method of lane reversal is controlled by a
Hardware Reset strap, and reverses both the receivers and transmitters for all lanes
(e.g., TX15->TX0, RX15->RX0). This method is transparent to all external devices and is
different than lane reversal as defined in the PCI Express specification. In particular, link
initialization is not affected by static lane reversal.
26
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
1.4
Graphics (Intel® 82945G/82945GC/82945GZ GMCH
Only)
The 82945G/82945GC/82945GZ GMCH provides an integrated graphics device (IGD) delivering
cost competitive 3D, 2D, and video capabilities. The GMCH contains an extensive set of
instructions for 3D operations, BLT and Stretch BLT operations, motion compensation, overlay,
and display control. The GMCH’s video engines support video conferencing and other video
applications. The GMCH does not support a dedicated local graphics memory interface, it may
only be used in a UMA configuration. The GMCH also has the capability to support external
graphics accelerators via the PCI Express Graphics (PEG) port but cannot work concurrently with
the integrated graphics device. High bandwidth access to data is provided through the system
memory port. The GMCH also provides 3D hardware acceleration for block-level transfers of
data (BLTs). The 2D BLTs are considered a special case of 3D transfers and use the 3D
acceleration. The BLT engine provides the ability to copy a source block of data to a destination
and perform raster operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or
another destination. Performing these common tasks in hardware reduces processor load, and thus
improves performance.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
27
Introduction
GMCH graphics support includes:
3D Graphics Rendering Enhancements
Core Frequency of 400 MHz
1.6 GP/s pixel rate
1.3 Dual Texture GigaPixel/Sec Fill Rate
Flat and Gouraud Shading
Color Alpha Blending for Transparency
Vertex and Programmable Pixel Fog and
Atmospheric Effects
Serial DVO port with two channels (multiplexed on
PCI Express* Graphics port) for optional addition
of TV-Out/TV-In and/or DVI digital display
connections
Color Specular Lighting
Z Bias Support
Dithering
Anti-Aliased Lines
16- and 24-bit Z Buffering
8-bit Stencil Buffering
Double and Triple Render Buffer Support
16- and 32-bit Color
Destination Alpha
Maximum 3D Resolution Supported:
1600x1200x32 @ 85 Hz
Fast Clear Support
ADD2+ card support (Concurrent PCI
Express with SDVO) (82945G only)
High Quality 3D Setup and Render Engine
Setup matching processor geometry delivery
rates
Triangle lists, strips, and fans
Indexed vertex and flexible vertex formats
Vertex cache
Pixel accurate fast scissoring and clipping
operation
Backface culling
Supports D3D* and OGL* pixelization rules
Anti-aliased lines
Sprite points
Zone Rendering Technology 3
Shadow maps
2D Graphics
Optimized 256-bit BLT Engine
Alpha Stretch Blitter
Anti-aliased Lines
32-bit Alpha Blended Cursor
Color Space Conversion
Programmable 3-Color Transparent Cursor
8-, 16-, and 32-bit Color
ROP Support
Double-sided stencil
High-Quality Texture Engine
DX9* Compliant Hardware Pixel Shader 2.0
Per-pixel perspective corrected texture
mapping
Video DVD/PC-VCR
2/10/10/10 texture format
4x4 filtering
Single-pass quad texture compositing
Enhanced texture blending functions
12 levels of detail mip map sizes from 1x1 to
2Kx2K
VLD/iDCT for enabling Dual HD Streams for
MPEG playback (82945G only)
H/W Motion Compensation for MPEG2
- 4x HWMC computes
Dynamic Bob and Weave Support for Video
Streams
Source Resolution up to 1920x1080 with 2
vertical taps
All texture formats including 32-bit RGBA
and 8-bit palettes
Software DVD At 30 fps, Full Screen
Supports 720x480 DVD Quality Encoding at
low processor Utilization for PC-VCR or home
movie recording and editing
Alpha and luminance maps
Texture color-keying/chromakeying
Bilinear, trilinear and anisotropic mip-mapped
filtering
Cubic environment reflection mapping
Embossed and DOT3 bump-mapping
DXTn and FXT1 texture decompression
Non-power of 2 texture
Video Overlay
Advanced Deinterlacing
Process Amplifier Color Control
Single High Quality Scalable Overlay
Render to texture
Multiple Overlay Functionality provided via Stretch
Blitter (PIP, Video Conferencing, etc.)
Video DVD/PC-VCR
VLD/iDCT for enabling Dual HD Streams for
5-tap Horizontal, 3-tap Vertical Filtered Scaling
Independent Gamma Correction
Independent Brightness/Contrast/Saturation
Independent Tint/Hue Support
Destination Color-keying
MPEG playback (82945G only)
H/W Motion Compensation for MPEG2
- 4x HWMC computes
Dynamic Bob and Weave Support for Video
Streams
Source Resolution up to 1920x1080 with 2
vertical taps
Software DVD At 30 fps, Full Screen
Supports 720x480 DVD Quality Encoding at
low processor Use for PC-VCR or home
movie recording and editing
Source Chroma-keying
Maximum Source Resolution: 720x480x32
Maximum Overlay Display Resolution:
2048x1536x32
Video Mixer Render (VMR)
28
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Introduction
1.5
Analog and SDVO Displays (Intel®
82945G/82945GC/82945GZ GMCH Only)
The GMCH provides interfaces to a progressive scan analog monitor and two SDVO ports
(multiplexed with PCI Express x16 graphics port signals on the 82945G/82945GC) capable of
driving an ADD2/ADD2+ card. The digital display channels are capable of driving a variety of
SDVO devices (e.g., TMDS, TV-Out). Note that SDVO only works with the Integrated Graphics
Device (IGD). The ADD2+ card adds Video-in capabilities and is only supported on the 82945G
GMCH. The GMCH provides two multiplexed SDVO ports that are capable of driving up to a
200 MHz pixel clock each. The GMCH can make use of these digital display channels via an
Advanced Digital Display card (ADD2/2+) card.
The GMCH SDVO ports can each support a single-channel SDVO device. If both ports are active
in single-channel mode, they can have different display timing and data. Alternatively, the SDVO
ports can be combined to support dual channel devices, supporting higher resolutions and refresh
rates. The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high-speed interface to a digital
display (e.g., flat panel or digital CRT).
The 82945G/82945GC GMCH supports Hot-Plug and Display for the PCI Express x16 graphics.
This is not supported for ADD2 cards.
1.5.1
1.5.2
System Interrupts
Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms.
Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI
MSIs routed directly to FSB
From I/OxAPICs
Provides redirection for IPI(Inter-Processor Interrupts) and upstream interrupts to the FSB
(G)MCH Clocking
The differential Host clock of 133/200/266 MHz (HCLKP/HCLKN) supports transfer rates of
533/800/1066 MT/s, respectively. The 266 MHz HCLKP/HCLKN is only available on the
82945G GMCH and 82945P MCH. The Host PLL generates 2X, 4X, and 8X versions of the host
clock for internal optimizations. The (G)MCH core clock is synchronized to the host clock.
The internal and external memory clocks of 200, 266, and 333 MHz are generated from one of
two (G)MCH PLLs that use the Host clock as a reference. This includes 2x and 4x for internal
optimizations.
The PCI Express core clock of 250 MHz is generated from a separate PCI Express PLL that uses
the fixed 100 MHz Serial Reference Clock (GCLKP/GCLKN) for reference.
Display timings are generated from display PLLs that use a 96 MHz differential non-spread
spectrum clock as a reference. Display PLLs can also use the SDVO_TVCLKIN[+/-] from an
SDVO device as a reference.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
29
Introduction
All of the above clocks are capable of tolerating Spread Spectrum clocking as defined in the
Clock Generator specification. Host, memory, and PCI Express PLLs, and all associated internal
clocks are disabled until PWROK is asserted.
1.5.3
Power Management
(G)MCH Power Management support includes:
PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)
SMRAM space remapping to A0000h (128 KB)
Supports extended SMRAM space above 256 MB, additional 1-MB TSEG from the base of
graphics “stolen” memory (BSM) when enabled, and cacheable (cacheability controlled by
processor)
ACPI Revision 1.0 compatible power management
Supports processor states C0 and C1. The (G)MCH does not support the C2, C3, and C4
states.
Supports system states S0, S1D, S3, S4, and S5
Supports processor Thermal Management 2 (TM2)
Microsoft Windows NT* Hardware Design Guide v1.0 compliant
§
30
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
2 Signal Description
This chapter provides a detailed description of (G)MCH signals. The signals are arranged in
functional groups according to their associated interface (see Figure 2-1).
The following notations are used to describe the signal type:
PCIE
DMI
PCI Express interface signals. These signals are compatible with PCI Express 1.0
Signaling Environment AC Specifications and are AC coupled. The buffers are
not 3.3 V tolerant. Differential voltage specification = (|D+ - D-|) * 2
= 1.2 Vmax. Single-ended maximum = 1.5 V. Single-ended minimum = 0 V.
Direct Media Interface signals. These signals are compatible with PCI Express 1.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are
not 3.3 V tolerant. Differential voltage specification = (|D+ - D-|) * 2
= 1.2 Vmax. Single-ended maximum = 1.5 V. Single-ended minimum = 0 V.
CMOS
COD
CMOS buffers. 1.5 V tolerant.
CMOS Open Drain buffers. 2.5 V tolerant.
HCSL
Host Clock Signal Level buffers. Current mode differential pair. Differential
typical swing = (|D+ - D-|) * 2 = 1.4 V. Single ended input tolerant from -0.35 V
to 1.2 V. Typical crossing voltage is 0.35 V.
HVCMOS
HVIN
High Voltage CMOS buffers. 2.5 V tolerant.
High Voltage CMOS input-only buffers. 3.3 V tolerant.
SSTL-1.8
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
31
Signal Description
Figure 2-1. Signal Information Diagram
Intel®
82945G/
82945GZ/
82945GC
GMCH
HA[31:3]#
HD[63:0]
HADS#
HSYNC
VSYNC
RED, RED#
GREEN, GREEN#
BLUE, BLUE#
REFSET
DDC_CLK
DDC_DATA
HBNR#
Analog
Display
HBPRI#
HDBSY#
HDEFER#
HDRDY#
HEDRDY#
HHIT#
Only
SDVOB_GREEN-, SDVOB_GREEN+
SDVOB_BLUE-, SDVOB_BLUE+
SDVOB_RED-, SDVOB_RED+
SDVOB_CLK-, SDVOB_CLK+
SDVOC_RED- / SDVOB_ALPHA-,
SDVOC_RED+ / SDVOB_ALPHA+
SDVOC_GREEN-, SDVOC_GREEN+
SDVOC_BLUE-, SDVOC_BLUE+
SDVOC_CLK-, SDVOC_CLK+
SDVO_TVCLKIN-, SDVO_TVCLKIN+
SDVOB_INT-, SDVOB_INT+
SDVOC_INT-, SDVOC_INT+
SDVO_STALL-, SDVO_STALL+
SDVO_CTRLCLK
HHITM#
HLOCK#
HREQ[4:0]#
HPCREQ#
HTRDY#
HRS[2:0]#
HCPURST#
HBREQ0#
Processor
System
Bus
Intel®
SDVO
Intel®
82945G/
82945GZ/
82945GC
GMCH
Interface
Device
Interface1
HDINV[3:0]#
HADSTB[1:0]#
HDSTBP[3:0]#, HDSTBN[3:0]#
BSEL[2:0]
Only
HRCOMP
HSCOMP
HSWING
SDVO_CTRLDATA
Intel®
82945G/
82945GC
GMCH
and
82945P/
82945PL
MCH
HDVREF
HACCVREF
PCI
Express*
x16
Graphics
Port
EXP_RXN[15:0], EXP_RXP[15:0]
EXP_TXN[15:0], EXP_TXP[15:0]
EXP_COMPO
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
SCAS_A#
EXP_COMPI
System
Memory
SWE_A#
SDQ_A[63:0]
DDR2
Channel
A
HCLKP, HCLKN
GCLKP, GCLKN
DREFCLKN, DREFCLKP
RSTIN#
PWROK
EXTTS#
Only
SDM_A[7:0]
SDQS_A[7:0], SDQS_A[7:0]#
SCKE_A[3:0]
SCLK_A[5:0], SCLK_A[5:0]#
SODT_A[3:0]
Clocks,
Reset, and
Misc.
EXP_EN
EXP_SLR
ICH_SYNC#
XORTEST
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
SCAS_B#
System
Memory
ALLZTEST
Direct
Media
Interface
SWE_B#
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[7:0], SDQS_B[7:0]#
SCKE_B[3:0]
DMI_RXP[3:0], DMI_RXN[3:0]
DMI_TXP[3:0], DMI_TXN[3:0]
DDR2
Channel
B
VCC
VTT
VCC_EXP
VCCSM
VCC2
VCCA_EXPPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_SMPLL
VSS
SCLK_B[5:0], SCLK_B[5:0]#
SODT_B[3:0]
Voltage
Reference,
and Power
SRCOMP[1:0]
SOCOMP[1:0]
SMVREF[1:0]
System
Memory
DDR2 Ref./
Comp.
VCCA_DAC
VSSA_DAC
Note:
1. SDVO signals on the 82945G GMCH are multiplexed with the PCI Express x16 Graphics Port signals.
Signal_Info
32
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
2.1
Host Interface Signals
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
voltage of the Host Bus (VTT).
Signal Name
Type
Description
HADS#
I/O
GTL+
Address Strobe: The processor bus owner asserts HADS# to indicate the
first of two cycles of a request phase. The (G)MCH can assert this signal for
snoop cycles and interrupt messages.
HBNR#
HBPRI#
I/O
GTL+
Block Next Request: HBNR# is used to block the current request bus
owner from issuing new requests. This signal is used to dynamically control
the processor bus pipeline depth.
O
GTL+
Priority Agent Bus Request: The (G)MCH is the only Priority Agent on the
processor bus. It asserts this signal to obtain the ownership of the address
bus. This signal has priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
HBREQ0#
I/O
GTL+
Bus Request 0: The (G)MCH pulls the processor’s bus HBREQ0# signal
low during HCPURST#. The processor samples this signal on the active-to-
inactive transition of HCPURST#. The minimum setup time for this signal is
4 HCLKs. The minimum hold time is 2 HCLKs and the maximum hold time
is 20 HCLKs. HBREQ0# should be tristated after the hold time requirement
has been satisfied.
HCPURST#
O
GTL+
CPU Reset: The HCPURST# pin is an output from the (G)MCH. The
(G)MCH asserts HCPURST# while RSTIN# is asserted and for
approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows
the processors to begin execution in a known state.
Note that the Intel® ICH7 must provide processor frequency select strap set-
up and hold times around HCPURST#. This requires strict synchronization
between (G)MCH HCPURST# de-assertion and the ICH7 driving the straps.
HDBSY#
I/O
Data Bus Busy: This signal is used by the data bus owner to hold the data
GTL+
bus for transfers requiring more than one cycle.
HDEFER#
O
GTL+
Defer: HDEFER# indicates that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or with a retry
response.
HDINV[3:0]#
I/O
GTL+
Dynamic Bus Inversion: These signals are driven along with the HD[63:0]
signals. They indicate if the associated signals are inverted or not.
HDINV[3:0]# are asserted such that the number of data bits driven
electrically low (low voltage) within the corresponding 16 bit group never
exceeds 8.
HDINV[x]#
HDINV3#
HDINV2#
HDINV1#
HDINV0#
Data Bits
HD[63:48]
HD[47:32]
HD[31:16]
HD[15:0]
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
33
Signal Description
Signal Name
Type
Description
HDRDY#
I/O
Data Ready: This signal is asserted for each cycle that data is transferred.
GTL+
HEDRDY#
HA[31:3]#
O
GTL+
Early Data Ready: This signal indicates that the data phase of a read
transaction will start on the bus exactly one common clock after assertion.
I/O
GTL+
Host Address Bus: HA[31:3]# connect to the processor address bus.
During processor cycles, the HA[31:3]# are inputs. The (G)MCH drives
HA[31:3]# during snoop cycles on behalf of DMI and PCI Express* initiators.
HA[31:3]# are transferred at 2x rate.
HADSTB[1:0]#
HD[63:0]
I/O
GTL+
Host Address Strobe: These signals are the source synchronous strobes
used to transfer HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
I/O
GTL+
Host Data: These signals are connected to the processor data bus. Data on
HD[63:0] is transferred at 4x rate. Note that the data signals may be
inverted on the processor bus, depending on the HDINV[3:0]# signals.
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
GTL+
Differential Host Data Strobes: These signals are the differential source
synchronous strobes used to transfer HD[63:0]# and HDINV[3:0]# at 4x
transfer rate.
These signals are named this way because they are not level sensitive.
Data is captured on the falling edge of both strobes. Hence, they are
pseudo-differential, and not true differential.
Strobes
Data
Bits
HDSTBP3#, HDSTBN3#
HDSTBP2#, HDSTBN2#
HDSTBP1#, HDSTBN1#
HDSTBP0#, HDSTBN0#
HD[63:48]
HD[47:32]
HD[31:16]
HD[15:0]
HDINV3#
HDINV2#
HDINV1#
HDINV0#
HHIT#
I/O
GTL+
Hit: This signal indicates that a caching agent holds an unmodified version
of the requested line. In addition, HHIT# is driven in conjunction with
HHITM# by the target to extend the snoop window.
HHITM#
I/O
GTL+
Hit Modified: This signal indicates that a caching agent holds a modified
version of the requested line and that this agent assumes responsibility for
providing the line. In addition, HHITM# is driven in conjunction with HHIT#
to extend the snoop window.
HLOCK#
I/O
GTL+
Host Lock: All processor bus cycles sampled with the assertion of HLOCK#
and HADS#, until the negation of HLOCK# must be atomic (i.e., no DMI or
PCI Express accesses to DRAM are allowed when HLOCK# is asserted by
the processor).
HPCREQ#
I
Precharge Request: The processor provides a “hint” to the (G)MCH that it
is OK to close the DRAM page of the memory read request with which the
hint is associated. The (G)MCH uses this information to schedule the read
request to memory using the special “AutoPrecharge” attribute. This causes
the DRAM to immediately close (Precharge) the page after the read data
has been returned. This allows subsequent processor requests to more
quickly access information on other DRAM pages, since it will no longer be
necessary to close an open page prior to opening the proper page.
HPCREQ# is asserted by the requesting agent during both halves of
Request Phase. The same information is provided in both halves of the
request phase.
GTL+
2x
34
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
Signal Name
Type
Description
HREQ[4:0]#
I/O
GTL+
2x
Host Request Command: These signals define the attributes of the
request. HREQ[4:0]# are transferred at 2x rate. They are asserted by the
requesting agent during both halves of Request Phase. In the first half, the
signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half, the signals carry additional
information to define the complete transaction type.
HTRDY#
O
Host Target Ready: This signal indicates that the target of the processor
GTL+
transaction is able to enter the data transfer phase.
HRS[2:0]#
O
Response Signals: These signals indicate the type of response as shown
GTL+
below:
000 = Idle state
001 = Retry response
010 = Deferred response
011 = Reserved (not driven by (G)MCH)
100 = Hard Failure (not driven by (G)MCH)
101 = No data response
110 = Implicit Writeback
111 = Normal data response
BSEL[2:0]
HRCOMP
HSCOMP
HSWING
I
Bus Speed Select: At the de-assertion of RSTIN#, the value sampled on
these pins determines the expected frequency of the bus.
CMOS
I/O
CMOS
Host RCOMP: This signal is used to calibrate the Host GTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (VTT).
I/O
CMOS
Slew Rate Compensation: This is the compensation signal for the Host
Interface.
I
A
Host Voltage Swing: This signal provides the reference voltage used by
FSB RCOMP circuits. HSWING is used for the signals handled by
HRCOMP.
HDVREF
I
Host Reference Voltage: Voltage input for the data, address, and common
A
clock signals of the Host GTL interface.
HACCVREF
I
Host Reference Voltage. Reference voltage input for the Address, and
A
Common clock signals of the Host GTL interface.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
35
Signal Description
2.2
DDR2 DRAM Channel A Interface
Signal Name
Type
Description
SCLK_A[5:0]
O
SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its complement
SCLK_Ax# signal make a differential clock pair output. The crossing of the
positive edge of SCLK_Ax and the negative edge of its complement
SCLK_Ax# are used to sample the command and control signals on the
SDRAM.
SSTL-1.8
SCLK_A[5:0]#
SCS_A[3:0]#
O
SDRAM Complementary Differential Clock: (3 per DIMM). These are the
complementary Differential DDR2 Clock signals.
SSTL-1.8
O
Chip Select: (1 per Rank). These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank.
SSTL-1.8
SMA_A[13:0]
SBS_A[2:0]
O
Memory Address: These signals are used to provide the multiplexed row
and column address to the SDRAM.
SSTL-1.8
O
Bank Select: These signals define which banks are selected within each
SSTL-1.8
SDRAM rank.
DDR2: 1-Gb technology is 8 banks.
SRAS_A#
SCAS_A#
SWE_A#
O
Row Address Strobe: This signal is used with SCAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
SSTL-1.8
O
Column Address Strobe: This signal is used with SRAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
SSTL-1.8
O
Write Enable: This signal is used with SCAS_A# and SRAS_A# (along with
SSTL-1.8
SCS_A#) to define the SDRAM commands.
SDQ_A[63:0]
I/O
SSTL-1.8
2x
Data Lines: The SDQ_A[63:0] signals interface to the SDRAM data bus.
SDM_A[7:0]
O
SSTL-1.8
2X
Data Mask: When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SDM_Ax bit for every data byte lane.
SDQS_A[7:0]
I/O
SSTL-1.8
2x
Data Strobes: For DDR2, SDQS_Ax and its complement SDQS_Ax# signal
make up a differential strobe pair. The data is captured at the crossing point
of SDQS_Ax and its complement SDQS_Ax# during read and write
transactions.
SDQS_A[7:0]#
SCKE_A[3:0]
SODT_A[3:0]
I/O
SSTL-1.8
2x
Data Strobe Complements: These are the complementary DDR2 strobe
signals.
O
Clock Enable: (1 per Rank). SCKE_Ax is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
SSTL-1.8
O
On Die Termination: Active On-die Termination Control signals for DDR2
SSTL-1.8
devices.
36
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
2.3
DDR2 DRAM Channel B Interface
Signal Name
Type
Description
SCLK_B[5:0]
O
SDRAM Differential Clock: (3 per DIMM). SCLK_Bx and its complement
SCLK_Bx# signal make a differential clock pair output. The crossing of the
positive edge of SCLK_Bx and the negative edge of its complement
SCLK_Bx# are used to sample the command and control signals on the
SDRAM.
SSTL-1.8
SCLK_B[5:0]#
SCS_B[3:0]#
O
SDRAM Complementary Differential Clock: (3 per DIMM). These are
the complementary Differential DDR2 Clock signals.
SSTL-1.8
O
Chip Select: (1 per Rank). These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank
SSTL-1.8
SMA_B[13:0]
SBS_B[2:0]
O
Memory Address: These signals are used to provide the multiplexed row
and column address to the SDRAM
SSTL-1.8
O
Bank Select: These signals define which banks are selected within each
SSTL-1.8
SDRAM rank.
DDR2: 1-Gb technology is 8 banks.
SRAS_B#
SCAS_B#
SWE_B#
O
Row Address Strobe: This signal is used with SCAS_B# and SWE_B#
(along with SCS_B#) to define the SDRAM commands.
SSTL-1.8
O
Column Address Strobe: This signal is used with SRAS_B# and
SWE_B# (along with SCS_B#) to define the SDRAM commands.
SSTL-1.8
O
Write Enable: This signal is used with SCAS_B# and SRAS_B# (along
SSTL-1.8
with SCS_B#) to define the SDRAM commands.
SDQ_B[63:0]
I/O
SSTL-1.8
2x
Data Lines: The SDQ_B[63:0] signals interface to the SDRAM data bus.
SDM_B[7:0]
O
SSTL-1.8
2x
Data Mask: When activated during writes, the corresponding data groups
in the SDRAM are masked. There is one SDM_Bx for every data byte
lane.
SDQS_B[7:0]
I/O
SSTL-1.8
2x
Data Strobes: For DDR2, SDQS_Bx and its complement SDQS_Bx#
make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Bx and its complement SDQS_Bx# during read and write
transactions.
SDQS_B[7:0]#
SCKE_B[3:0]
SODT_B[3:0]
I/O
SSTL-1.8
2x
Data Strobe Complements: These are the complementary DDR2 Strobe
signals.
O
Clock Enable: (1 per Rank). SCKE_Bx is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
SSTL-1.8
O
On Die Termination: Active On-die Termination Control signals for DDR2
SSTL-1.8
devices.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
37
Signal Description
2.4
DDR2 DRAM Reference and Compensation
Signal Name
Type
Description
SRCOMP[1:0]
SOCOMP[1:0]
I/O
System Memory RCOMP
I/O
A
DDR2 On-Die DRAM Over Current Detection (OCD) Driver
Compensation
SMVREF[1:0]
I
SDRAM Reference Voltage: These signals are reference voltage inputs for
A
each SDQ_x, SDM_x, SDQS_x, and SDQS_x# input signals.
2.5
PCI Express* Interface Signals (Intel®
82945G/82945GC/82945P/82945PL Only)
Unless otherwise specified, PCI Express signals are AC coupled, so the only voltage specified is a
maximum 1.2 V differential swing.
Note: PCI Express Interface signals are not on the 82945GZ.
Signal Name
Type
Description
PCI Express* Receive Differential Pair
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
I/O
PCIE
O
PCIE
PCI Express* Transmit Differential Pair
I
A
PCI Express* Output Current Compensation
PCI Express* Input Current Compensation
EXP_COMPI
I
A
38
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
2.6
Analog Display Signals (Intel® 82945G/82945GC/
82945GZ GMCH Only)
Signal Name
RED
Type
Description
O
A
RED Analog Video Output: This signal is a CRT Analog video output
from the internal color palette DAC. The DAC is designed for a 37.5
routing impedance; however, the terminating resistor to ground will be 75
(e.g., 75 resistor on the board, in parallel with a 75 CRT load).
RED#
O
A
REDB Analog Output: This signal is an analog video output from the
internal color palette DAC. It should be shorted to the ground plane.
GREEN
O
A
GREEN Analog Video Output: This signal is a CRT Analog video output
from the internal color palette DAC. The DAC is designed for a 37.5
routing impedance: however, the terminating resistor to ground will be 75
(e.g., 75 resistor on the board, in parallel with a 75 CRT load).
GREEN#
BLUE
O
A
GREENB Analog Output: This signal is an analog video output from the
internal color palette DAC. It should be shorted to the ground plane.
O
A
BLUE Analog Video Output: This signal is a CRT Analog video output
from the internal color palette DAC. The DAC is designed for a 37.5
routing impedance; however, the terminating resistor to ground will be 75
(e.g., 75 resistor on the board, in parallel with a 75 CRT load).
BLUE#
O
A
BLUEB Analog Output: This signal is an analog video output from the
internal color palette DAC. It should be shorted to the ground plane.
REFSET
HSYNC
O
A
Resistor Set: Set point resistor for the internal color palette DAC. A
255 1% resistor is required between REFSET and motherboard ground.
O
CRT Horizontal Synchronization: This signal is used as the horizontal
2.5V
sync (polarity is programmable) or “sync interval”. 2.5 V output
CMOS
VSYNC
O
CRT Vertical Synchronization: This signal is used as the vertical sync
2.5V
(polarity is programmable). 2.5 V output.
CMOS
DDC_CLK
DDC_DATA
I/O
2.5V
CMOS
Monitor Control Clock. This signal may be used as the DDC_CLK for a
secondary multiplexed digital display connector.
I/O
Monitor Control Data. This signal may be used as the DDC_Data for a
2.5V
secondary multiplexed digital display connector.
CMOS
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
39
Signal Description
2.7
Clocks, Reset, and Miscellaneous
Signal
Name
Type
Description
HCLKP
I
Differential Host Clock In: These pins receive a differential host clock from
the external clock synthesizer. This clock is used by all of the (G)MCH logic
that is in the Host clock domain. Memory domain clocks are also derived
from this source.
HCSL
HCLKN
GCLKP
GCLKN
I
Differential PCI Express* Clock In: These pins receive a differential
100 MHz Serial Reference clock from the external clock synthesizer. This
clock is used to generate the clocks necessary for the support of PCI
Express.
HCSL
DREFCLKN
DREFCLKP
RSTIN#
I
Display PLL Differential Clock In
HCSL
I
Reset In: When asserted, this signal will asynchronously reset the (G)MCH
logic. This signal is connected to the PCIRST# output of the Intel® ICH7. All
PCI Express graphics attach output signals will also tri-state compliant to
PCI Express* Specification, Revision 1.0a.
HVIN
This input should have a Schmitt trigger to avoid spurious resets.
This signal is required to be 3.3 V tolerant.
PWROK
EXTTS#
I
Power OK: When asserted, PWROK is an indication to the (G)MCH that
core power has been stable for at least 10 us.
HVIN
I
External Thermal Sensor Input: This signal may connect to a precision
thermal sensor located on or near the DIMMs. If the system temperature
reaches a dangerously high value, then this signal can be used to trigger
the start of system thermal management. This signal is activated when an
increase in temperature causes a voltage to cross some threshold in the
sensor.
CMOS
EXP_EN
I
PCI Express SDVO Concurrent Select
CMOS
0 = Only SDVO or PCI Express operational
1 = SDVO and PCI Express operating simultaneously via PCI Express
port
NOTES: For the 82945GZ GMCH and 82945P/82945PL MCH, this signal
should be pulled low.
EXP_SLR
I
PCI Express* Static Lane Reversal/Form Factor Selection: (G)MCH’s
PCI Express lane numbers are reversed to differentiate Balanced
Technology Extended (BTX) or ATX form factors.
CMOS
0 = (G)MCH’s PCI Express lane numbers are reversed (BTX Platforms)
1 = Normal operation (ATX Platforms)
NOTES: This signal does not apply to the 82945GZ.
ICH_SYNC#
XORTEST
ALLZTEST
O
ICH Sync: This signal is connected to the MCH_SYNCH# signal on the
ICH7.
HVCMOS
I/O
GTL+
XOR Test: This signal is used for Bed of Nails testing by OEMs to execute
XOR Chain test.
I/O
All Z Test: As an input this signal is used for Bed of Nails testing by OEMs
GTL+
to execute XOR Chain test. It is used as an output for XOR chain testing.
40
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
2.8
2.9
Direct Media Interface (DMI)
Signal Name
Type
Description
DMI_RXP[3:0]
DMI_RXN[3:0]
DMI_TXP[3:0]
DMI_TXN[3:0]
I/O
DMI
Direct Media Interface: These signals are receive differential pairs (Rx).
Direct Media Interface: These signals are transmit differential pairs (Tx).
O
DMI
Intel® Serial DVO (SDVO) Interface (Intel®
82945G/82945GC/82945GZ GMCH Only)
For the 82945G/82945GC GMCH, all but two of the pins in this section are multiplexed with the
upper 8 lanes of the PCI Express interface.
Signal Name
Type
Description
SDVOB_CLK-
O
Serial Digital Video Channel B Clock Complement. This signal is
PCIE
multiplexed with EXP_TXN12.
SDVOB_CLK+
SDVOB_RED-
O
PCIE
Serial Digital Video Channel B Clock. This signal is multiplexed with
EXP_TXP12.
O
Serial Digital Video Channel C Red Complement. This signal is
PCIE
multiplexed with EXP_TXN15.
SDVOB_RED+
SDVOB_GREEN-
SDVOB_GREEN+
SDVOB_BLUE-
SDVOB_BLUE+
O
PCIE
Serial Digital Video Channel C Red. This signal is multiplexed with
EXP_TXP15.
O
PCIE
Serial Digital Video Channel B Green Complement. This signal is
multiplexed with EXP_TXN14.
O
PCIE
Serial Digital Video Channel B Green. This signal is multiplexed with
EXP_TXP14.
O
PCIE
Serial Digital Video Channel B Blue Complement. This signal is
multiplexed with EXP_TXN13.
O
Serial Digital Video Channel B Blue. This signal is multiplexed with
PCIE
EXP_TXP13.
SDVOC_RED- /
SDVOB_ALPHA-
O
PCIE
Serial Digital Video Channel C Red Complement Channel B Alpha
Complement. This signal is multiplexed with EXP_TXN11.
SDVOC_RED+ /
SDVOB_ALPHA+
O
PCIE
Serial Digital Video Channel C Red Channel B Alpha. This signal is
multiplexed with EXP_TXP11.
SDVOC_GREEN-
SDVOC_GREEN+
SDVOC_BLUE-
SDVOC_BLUE+
O
PCIE
Serial Digital Video Channel C Green Complement. This signal is
multiplexed with EXP_TXN10.
O
PCIE
Serial Digital Video Channel C Green. This signal is multiplexed with
EXP_TXP10.
O
PCIE
Serial Digital Video Channel C Blue Complement. This signal is
multiplexed with EXP_TXN9.
O
Serial Digital Video Channel C Blue. This signal is multiplexed with
PCIE
EXP_TXP9.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
41
Signal Description
Signal Name
Type
Description
SDVOC_CLK-
O
Serial Digital Video Channel C Clock Complement. This signal is
PCIE
multiplexed with EXP_TXN8.
SDVOC_CLK+
SDVO_TVCLKIN-
SDVO_TVCLKIN+
SDVOB_INT-
O
PCIE
Serial Digital Video Channel C Clock. This signal is multiplexed with
EXP_TXP8.
I
Serial Digital Video TV-OUT Synchronization Clock Complement.
This signal is multiplexed with EXP_RXN15.
PCIE
I
Serial Digital Video TV-OUT Synchronization Clock. This signal is
multiplexed with EXP_RXP15.
PCIE
I
Serial Digital Video Input Interrupt Complement. This signal is
PCIE
multiplexed with EXP_RXN14.
SDVOB_INT+
I
Serial Digital Video Input Interrupt. This signal is multiplexed with
PCIE
EXP_RXP14.
SDVOC_INT+
I
Serial Digital Video Input Interrupt. This signal is multiplexed with
PCIE
EXP_RXP10
SDVOC_INT-
I
Serial Digital Video Input Interrupt Complement. This signal is
PCIE
multiplexed with EXP_RXN10
SDVO_STALL-
SDVO_STALL+
SDVO_CTRLCLK
SDVO_CTRLDATA
I
Serial Digital Video Field Stall Complement. This signal is multiplexed
with EXP_RXN13.
PCIE
I
Serial Digital Video Field Stall. This signal is multiplexed with
EXP_RXP13.
PCIE
I/O
COD
Serial Digital Video Device Control Clock.
Serial Digital Video Device Control Data.
I/O
COD
42
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
2.10
Power and Ground
Name
Voltage
Description
VCC
VTT
1.5 V
1.2 V
1.5 V
1.8 V
2.5 V
1.5 V
1.5 V
Core Power
Processor System Bus Power
PCI Express* and DMI Power
System Memory Power
VCC_EXP
VCCSM
VCC2
2.5 V CMOS Power
VCCA_EXPPLL
PCI Express PLL Analog Power
Display PLL A Analog Power
VCCA_DPLLA
(GMCH ONLY)
VCCA_DPLLB
(GMCH ONLY)
1.5 V
Display PLL B Analog Power
VCCA_HPLL
VCCA_SMPLL
VCCA_DAC
VSS
1.5 V
1.5 V
2.5 V
0 V
Host PLL Analog Power
System Memory PLL Analog Power
Display DAC Analog Power
Ground
VSSA_DAC
0 V
Ground
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
43
Signal Description
2.11
Reset States and Pull-up/Pull-downs
This section describes the expected states of the (G)MCH I/O buffers during and immediately
after the assertion of RSTIN#. This table only refers to the contributions on the interface from the
(G)MCH and does NOT reflect any external influence (such as, external pull-up/pull-down
resistors or external drivers).
Legend:
DRIVE:
TERM:
LV:
Strong drive (to normal value supplied by core logic if not otherwise stated)
Normal termination devices are turned on
Low voltage
HV:
High voltage
IN:
Input buffer enabled
TRI:
Tri-state
PU:
Weak internal pull-up: 7.2 K – 11.1 K, unless otherwise specified.
Weak internal pull-down: 600 – 880 unless otherwise specified.
PD:
CMCT:
Common Mode Center Tapped. Differential signals are weakly driven to the
common mode central voltage.
STRAP:
Strap input sampled during assertion edge of PWROK.
State After
State During
RSTIN# Assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
De-assertion
Host
HCPURST#
O
DRIVE LV
TERM HV after
Interface
approximately 1ms
HADSTB[1:0]#
HA[35:3]#
I/O
I/O
TERM HV
TERM HV
POC
TERM HV
STRAP
HD[63:0]
I/O
I/O
I/O
I/O
I/O
I/O
O
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
HDSTBP[3:0]#
HDSTBN[3:0]#
HDINV[3:0]#
HADS#
HBNR#
HBPRI#
HDBSY#
I/O
O
HDEFER#
HDRDY#
HEDRDY#
HHIT#
I/O
O
I/O
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
State After
RSTIN#
De-assertion
State During
RSTIN# Assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
HHITM#
I/O
I/O
I/O
O
I
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
IN
TERM HV
HLOCK#
TERM HV
HREQ[4:0]#
HTRDY#
TERM HV
TERM HV
HRS[2:0]#
TERM HV
HBREQ0#
HPCREQ#
HDREF
O
I
TERM HV
TERM HV
I
IN
HRCOMP
I/O
I
TRI
TRI after RCOMP
RCOMP
HSWING
IN
IN
HSCOMP
I/O
I
TRI
TRI
IN
HACCVREF
SCLK_A[5:0]
SCLK_A[5:0]#
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
IN
System
Memory
O
O
O
O
O
O
O
O
I/O
O
I/O
I/O
O
O
O
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
TRI
Channel A
TRI
TRI
TRI
TRI
SCAS_A#
TRI
SWE_A#
TRI
SDQ_A[63:0]
SDM_A[7:0]
SDQS_A[7:0]
SDQS_A[7:0]#
SCKE_A[3:0]
SCKE_A[3:0]
SODT_A[3:0]
TRI
TRI
TRI
TRI
LV
LV
LV
LV
LV
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
45
Signal Description
State After
RSTIN#
De-assertion
State During
RSTIN# Assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
System
Memory
SCLK_B[5:0]
O
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
TRI
SCLK_B[5:0]#
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
O
TRI
Channel B
O
TRI
O
TRI
O
TRI
O
TRI
SCAS_B#
O
TRI
SWE_B#
O
TRI
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[7:0]
SDQS_B[7:0]#
SCKE_B[3:0]
SODT_B[3:0]
SRCOMP0
I/O
O
TRI
TRI
I/O
I/O
O
TRI
TRI
LV
O
LV
LV
System
Memory
I/O
I/O
I
TRI
TRI
IN
TRI after RCOMP
SRCOMP1
TRI after RCOMP
Reference
Comp.
SMVREF[1:0]
SOCOMP[1:0]
IN
I/O
TRI
TRI
External
40 resistor
to ground
PCI
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
I/O
I/O
O
CMCT
CMCT
Express*
(82945G/8
2945GC/
82945P/
82945PL
Only)
CMCT
CMCT
CMCT 1.0V
CMCT 1.0V
TRI
CMCT 1.0V
CMCT 1.0V
TRI
O
O
I
TRI
TRI
DMI
DMI_RXN[3:0]
DMI_RXP[3:0]
DMI_TXN[3:0]
DMI_TXP[3:0]
I/O
I/O
O
CMCT
CMCT
CMCT
CMCT
CMCT 1.0V
CMCT 1.0V
CMCT 1.0V
CMCT 1.0V
O
46
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Signal Description
State After
RSTIN#
De-assertion
State During
RSTIN# Assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
HCLKN
I
IN
IN
IN
IN
IN
IN
IN
HV
PU
IN
IN
IN
IN
IN
IN
IN
HV
PU
Clocks
HCLKP
I
GCLKN
I
GCLKP
I
DREFCLKN
DREFCLKP
RSTIN#
I
I
I
Misc
PWROK
I
ICH_SYNC#
O
INT 10 K
PU
EXTTS#
I
IN
IN
BSEL[2:0]
I/O
TRI
TRI
STRAP
EXP_SLR
EXP_EN
I/O
I/O
I/O
I/O
I/O
I/O
TERM HV
STRAP
TERM HV
TRI
PD STRAP
INT 10 K
PD
SDVO_CTRLCLK
(GMCH Only)
PD
TRI
INT 10 K
PD
SDVO_CTRLDATA
(GMCH Only)
PDSTRAP
TRI
XORTEST
TERM HV
STRAP
TERM HV
TERM HV
ALLZTEST
TERM HV
STRAP
HSYNC
O
O
O
O
O
LV
DAC
VSYNC
LV
RED (GMCH Only)
RED# (GMCH Only)
TRI
TRI
TRI
TRI
TRI
TRI
GREEN (GMCH
Only)
GREEN# (GMCH
Only)
O
TRI
TRI
BLUE (GMCH Only)
O
O
TRI
TRI
TRI
TRI
BLUE# (GMCH
Only)
REFSET
I/O
TRI
0.5*Bandgap
255 1%
Resistor to
Ground
DDC_CLK
I/O
I/O
IN
IN
IN
IN
DDC_DATA
§
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
47
Signal Description
48
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Register Description
3 Register Description
The (G)MCH contains two sets of software accessible registers, accessed via the Host processor
I/O address space: Control registers and internal configuration registers.
Control registers are I/O mapped into the processor I/O space that controls access to PCI and
PCI Express configuration space (see Section 3.5).
Internal configuration registers residing within the (G)MCH are partitioned into logical
device register sets (“logical” since they reside within a single physical device). One register
set is dedicated to Host Bridge functionality (i.e., DRAM configuration, other chipset
operating parameters, and optional features). Another register set is dedicated to Host-PCI
Express Bridge functions (controls PCI Express interface configurations and operating
parameters). The 82945G/82945G/82945GZ GMCH contains a third register set that is for
the internal graphics functions.
The (G)MCH internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the Host processor. The registers that reside within the
lower 256 bytes of each device can be accessed as Byte, Word (16-bit), or DWord (32-bit)
quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a DWord.
All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least
significant parts of the field). Registers that reside in bytes 256 through 4095 of each device may
only be accessed using memory mapped transactions in DWord (32-bit) quantities.
Some of the (G)MCH registers described in this chapter contain reserved bits. These bits are
labeled "Reserved”. Software must deal correctly with fields that are reserved. On reads, software
must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit positions are
preserved. That is, the values of reserved bit positions must first be read, merged with the new
values for other bit positions and then written back. Note that the software does not need to
perform read, merge, and write operation for the configuration address register.
In addition to reserved bits within a register, the (G)MCH contains address locations in the
configuration space of the Host Bridge entity that are marked either "Reserved" or “Intel
Reserved”. The (G)MCH responds to accesses to “Reserved” address locations by completing the
host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved”
registers can be 8-, 16-, or 32-bits in size). Writes to “Reserved” registers have no effect on the
(G)MCH. Registers that are marked as “Intel Reserved” must not be modified by system software.
Writes to “Intel Reserved” registers may cause system failure. Reads from “Intel Reserved”
registers may return a non-zero value.
Upon a Full Reset, the (G)MCH sets its entire set of internal configuration registers to
predetermined default states. Some register values at reset are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system configuration. It
is the responsibility of the system initialization software (usually BIOS) to properly determine the
DRAM configurations, operating parameters, and optional system features that are applicable, and
to program the (G)MCH registers accordingly.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
49
Register Description
3.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
Description
RO
Read Only bit(s). Writes to these bits have no effect.
RS/WC
Read Set / Write Clear bit(s). These bits are set to 1 when read and then will continue to
remain set until written. A write of 1 clears (sets to ‘0’) the corresponding bit(s) and a write
of 0 has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A write of
1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this bit. A
write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect. Bits are
not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express*
related bits a cold reset is “Power Good Reset” as defined in the PCI Express*
Specification).
R/W/L
Read / Write / Lockable bit(s). These bits can be read and written. Additionally, there is a
bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field
from being writeable (bit field becomes Read Only).
R/W/S
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a
cold reset is “Power Good Reset” as defined in the PCI Express* Specification).
R/WSC
R/WSC/L
Read / Write Self Clear bit(s). These bits can be read and written. When the bit is 1,
hardware may clear the bit to 0 based upon internal events, possibly sooner than any
subsequent read could retrieve a 1.
Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the bit
is 1, hardware may clear the bit to 0 based upon internal events, possibly sooner than any
subsequent read could retrieve a 1. Additionally there is a bit (which may or may not be a
bit marked R/W/L) that, when set, prohibits this bit field from being writeable (bit field
becomes Read Only).
R/WO
W
Write Once bit(s). Once written, bits with this attribute become Read Only. These bits can
only be cleared by a Reset.
Write Only. Registers with this attribute have bits that may be written, but will always-return
zeros when read. They are used for write side effects. Any data written to these registers
cannot be retrieved.
3.2
Platform Configuration
In platforms that support DMI (such as, this (G)MCH) the configuration structure is significantly
different from hub architectures prior to the Intel® 915x Express chipsets. The DMI physically
connects the (G)MCH and the ICH7; thus, from a configuration standpoint, the DMI is logically
PCI bus 0. As a result, all devices internal to the (G)MCH and the ICH7 appear to be on PCI
bus 0.
Note: The ICH7 internal LAN controller does not appear on bus 0; it appears on the external PCI bus
(bus number is configurable).
The system’s primary PCI expansion bus is physically attached to the ICH7 and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and,
therefore, has a programmable PCI bus number. The PCI Express graphics attach appears to
system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI
bus 0.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Register Description
Note: A physical PCI bus 0 does not exist; DMI and the internal devices in the (G)MCH and ICH7
logically constitute PCI Bus 0 to configuration software (see Figure 3-1).
Figure 3-1. Conceptual Chipset Platform PCI Configuration Diagram
Processor
(G)MCH
PCI Configuration Window in
I/O Space
DRAM Controller Interface
Bus 0, Device 0
Host-PCI Express Bridge
Bus 0, Device 1 (Intel®
82945G/82945P/82945PL
GMCH Only)
Internal Graphics Controller
Bus 0, Device 2
(Intel® 82945G/82945GZ
GMCH Only)
Direct Media Interface (DMI)
PCI_Config_Dia
The (G)MCH contains three PCI devices within a single physical component. The configuration
registers for the three devices are mapped as devices residing on PCI bus 0.
Device 0: Host Bridge Controller. Logically, this device is a PCI device residing on PCI
bus 0. Device 0 contains the standard PCI header registers, PCI Express base address register,
DRAM control (including thermal/throttling control), and configuration for the DMI and
other (G)MCH specific registers.
Device 1: Host-PCI Express Bridge (82945G/82945GC/82945P/82945PL (G)MCH
Only). Logically, this device appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0
and is compliant with PCI Express* Specification, Revision 1.0a. Device 1 contains the
standard PCI-to-PCI bridge registers and the standard PCI Express/PCI configuration
registers (including the PCI Express memory address mapping). It also contains Isochronous
and Virtual Channel controls in the PCI Express extended configuration space.
Device 2: Internal Graphics Control (82945G/82945GC/82945GZ GMCH Only).
Logically, this device appears as a PCI device residing on PCI bus 0. Physically, device 2
contains the configuration registers for 3D, 2D, and display functions.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
51
Register Description
Figure 3-2. Register Organization
PCI Express* Egress Port
(RCRB)
FFFh
Device 2 Configuration
Registers: Internal Graphics
(Intel® 82945G/82945GZ
GMCH Only)
VC1 (Isochronous) Port
Arbitration Controls
FFFh
000h
FFFh
Unused
DMI Root Complex Register
Block (RCRB)
0FFh
(G)MCH-ICH7 Serial Interface
(DMI) Controls:
Analog Controls
Error Reporting Controls
VC Control
Mirror of bits needed by
graphics driver
Graphics Thermal Controls
000h
000h
Device 1 Configuration
Registers: PCI Express X16
PCI Express Address Range
FFFh
0FFF FFFFh
PCI Express x16 Controls:
Analog Controls
Error Reporting Controls
VC Controls
Accessed only by PCI
Express enhanced access
mechanism. 4 KB block
allocated for each potential
device in root hierarchy.
Hot Plug/Slot Controls
0FFh
Device Level Controls
Device 2 Range
Device 1 Range
Device 0 Range
000h
0000 0000h
Device 0 Configuration
Registers
FFFh
Device 0 MMIO Registers:
(G)MCH Control
3FFFh
Unused
Thermal Sensor
PSB Analog Controls
SM Analog Crontrols
(Rcomp+)
0FFh
CH 0/1 Analog Controls
CH 0/1 Timing Controls
Ch 0/1 Throttling
Ch 0/1 Oranization
Arbiter Controls
Device Level Controls, PAM
EPBAR
DMI BAR
PCIEXBAR
0000h
MCHBAR
000h
Note:
1. Diagram not to scale
2. PCI Express is for the Intel® 82945G/82945P/82945PL (G)MCH Only.
3. Internal Graphics Device is for the Intel® 82945G/82945GZ (G)MCH Only.
Reg_Org
NOTES:
1.
2.
3.
4.
5.
Very high level representation. Many details omitted.
Internal graphics memory mapped registers are not shown.
Only Device 1 uses PCI Express extended configuration space.
Device 0 and Device 2 use only standard PCI configuration space.
Hex numbers represent address range size and not actual locations.
52
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Register Description
3.3
Configuration Mechanisms
The processor is the originator of configuration cycles; thus, the FSB is the only interface in the
platform where these mechanisms are used. The MCH translates transactions received through
both configuration mechanisms to the same format.
3.3.1
Standard PCI Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to configuration cycles.
The PCI specification defines a slot based "configuration space" that allows each device to
contain up to 8 functions with each function containing up to 256 8-bit configuration registers.
The PCI specification defines two bus cycles to access the PCI configuration space: Configuration
Read and Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the (G)MCH.
The configuration access mechanism uses the CONFIG_ADDRESS register (at I/O address
0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though 0CFFh). To
reference a configuration register, a DWord I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the
device, and a specific configuration register of the device function being accessed.
CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then
becomes a window into the four bytes of configuration space specified by the contents of
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the (G)MCH
translating the CONFIG_ADDRESS into the appropriate configuration cycle.
The (G)MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal (G)MCH configuration registers,
DMI, or PCI Express.
3.3.2
PCI Express* Enhanced Configuration Mechanism (Intel®
82945G/82945GC/82945P/82945PL (G)MCH Only)
PCI Express extends the configuration space to 4096 bytes per device/function as compared to
256 bytes allowed by the PCI Local Bus Specification, Revision 2.3. PCI Express configuration
space is divided into a PCI 2.3 compatible region that consists of the first 256B of a logical
device’s configuration space and a PCI Express extended region that consists of the remaining
configuration space.
The PCI compatible region can be accessed using either the Standard PCI configuration
mechanism or using the PCI Express enhanced configuration mechanism described in this section.
The extended configuration registers may only be accessed using the PCI Express enhanced
configuration mechanism. To maintain compatibility with PCI configuration addressing
mechanisms, system software must access the extended configuration space using
32-bit operations (32-bit aligned) only. These 32-bit operations include byte enables allowing
only appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express
memory-mapped configuration address space are not supported. All changes made using either
access mechanism are equivalent.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
53
Register Description
The PCI Express enhanced configuration mechanism uses a flat memory-mapped address space to
access device configuration registers. This address space is reported by the system firmware to the
operating system. The PCIEXBAR register defines the base address for the block of addresses
below 4 GB for the configuration space associated with busses, devices, and functions that are
potentially a part of the PCI Express root complex hierarchy. The PCIEXBAR register contains
controls to limit the size of this reserved memory-mapped space; 256 MB is the amount of
address space required to reserve space for every bus, device, and function is currently available.
Options for 128 MB and 64 MB are available to free up those addresses for other uses. In these
cases the number of busses and all of their associated devices and functions are limited to 128 or
64 busses respectively.
The PCI Express configuration transaction header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the function number and register address fields to
provide indexing into the 4 KB of configuration space allocated to each potential device. For PCI
compatible configuration requests, the Extended Register Address field must be all zeros.
Figure 3-3. Memory Map-to-PCI Express* Device Configuration Space
FFFFFFFh
FFFFFh
FFFh
7FFFh
Bus 255
Device 31
Function 7
PCI Express*
Extended
Configuration
Space
FFFFh
7FFFh
1FFFh
FFFh
FFh
3Fh
1FFFFFh
PCI
Compatible
Config Space
Bus 1
Bus 0
Function 1
Function 0
Device 1
Device 0
FFFFFh
0h
PCI
Compatible
Config Header
Located By PCI
Express Base
Address
MemMap_PCIExpress
As with PCI devices, each PCI Express device is selected based on decoded address information
that is provided as a part of the address portion of configuration request packets. A PCI Express
device will decode all address information fields (bus, device, function, and extended address
numbers) to provide access to the correct register.
To access this space (steps 1, 2, and 3 are completed only once by BIOS):
1. use the PCI compatible configuration mechanism to enable the PCI Express enhanced
configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register.
2. use the PCI compatible configuration mechanism to write an appropriate PCI Express
base address into the PCIEXBAR register .
3. calculate the host address of the register you wish to set using (PCI Express base +
(bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address).
4. use a memory write or memory read cycle to the calculated host address to write or read
that register.
54
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Register Description
3.4
Routing Configuration Accesses
The (G)MCH supports two PCI related interfaces: DMI and PCI Express. The (G)MCH is
responsible for routing PCI and PCI Express configuration cycles to the appropriate device that is
an integrated part of the (G)MCH or to one of these two interfaces. Configuration cycles to the
ICH7 internal devices and Primary PCI (including downstream devices) are routed to the ICH7
via DMI. Configuration cycles to both the PCI Express graphics PCI compatibility configuration
space and the PCI Express graphics extended configuration space are routed to the PCI Express
graphics port device or associated link.
Figure 3-4. Intel® 82945G/82945GC (G)MCH Configuration Cycle Flow Chart
DWord I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Yes
Bus# = 0
No
GMCH Generates
Type 1 Access to
PCI Express
Bus# > Sec Bus
Bus# Sub Bus in
GMCH Dev 1
Yes
Yes
Dev# = 0 &
Func# = 0
GMCH Claims
No
No
Dev# = 1 &
Dev# 1 Enabled
& Func# = 0
Bus# =
Secondary Bus in
GMCH Dev 1
Yes
GMCH Claims
Yes
No
No
Dev# = 2 &
GMCH Generates DMI
Type 1Configuration
Cycle
(Func#=0 & Dev#2,
Func#0 Enabled)
OR
Yes
GMCH Claims
(Func#=1 & Dev#2,
Funcs#0&1 Enabled)
No
GMCH Generates
Type 0 Access
to PCI Express
Yes
Device# = 0
GMCH Generates DMI
Type 0 Configuration
Cycle
No
GMCH allows cycle to
go to DMI resulting in
Master Abort
Config_Cyc_Flow
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
55
Register Description
3.4.1
3.4.2
Internal Device Configuration Accesses
The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus 0 device. If the targeted PCI Bus 0 device exists in the
(G)MCH and is not disabled, the configuration cycle is claimed by the appropriate device.
Bridge Related Configuration Accesses
Configuration accesses on PCI Express or DMI are PCI Express configuration TLPs (Transaction
Layer Packets).
Bus Number [7:0] is Header Byte 8 [7:0]
Device Number [4:0] is Header Byte 9 [7:3]
Function Number [2:0] is Header Byte 9 [2:0]
Special fields for this type of TLP are:
Extended Register Number [3:0] is Header Byte 10 [3:0]
Register Number [5:0] is Header Byte 11 [7:2]
See the PCI Express specification for more information on both the PCI 2.3 compatible and PCI
Express Enhanced Configuration Mechanism and transaction rules.
3.4.2.1
PCI Express* Configuration Accesses (Intel®
82945G/82945GC/82945P/82945PL (G)MCH Only)
When the Bus Number of a type 1 Standard PCI configuration cycle or PCI Express enhanced
configuration access matches the Device 1 Secondary Bus Number, a PCI Express type 0
configuration TLP is generated on the PCI Express link targeting the device directly on the
opposite side of the link. This should be Device 0 on the bus number assigned to the PCI Express
link (likely Bus 1).
The device on the other side of the link must be Device 0. The (G)MCH will Master Abort any
type 0 configuration access to a non-zero device number. If there is to be more than one device on
that side of the link, there must be a bridge implemented in the downstream device.
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express enhanced
configuration access is within the claimed range (between the upper bound of the bridge device’s
Subordinate Bus Number register and the lower bound of the bridge device’s Secondary Bus
Number register) but does not match the Device 1 Secondary Bus Number, a PCI Express type 1
configuration TLP is generated on the secondary side of the PCI Express link.
PCI Express Configuration Writes:
Internally, the host interface unit translates writes to PCI Express extended configuration
space to configuration writes on the backbone.
Writes to extended space are posted on the FSB, but non-posted on the PCI Express or DMI
(i.e., translated to configuration writes)
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Register Description
3.4.2.2
DMI Configuration Accesses
Accesses to disabled (G)MCH internal devices, bus numbers not claimed by the Host-PCI
Express bridge, or PCI Bus 0 devices not part of the (G)MCH will subtractively decode to the
ICH7 and consequently be forwarded over the DMI via a PCI Express configuration TLP.
If the Bus Number is zero, the (G)MCH generates a type 0 configuration cycle TLP on DMI. If
the Bus Number is non-zero, and falls outside the range claimed by the Host-PCI Express bridge,
the (G)MCH generates a type 1 configuration cycle TLP on DMI.
The ICH7 routes configuration accesses in a manner similar to the (G)MCH. The ICH7 decodes
the configuration TLP and generates a corresponding configuration access. Accesses targeting a
device on PCI Bus 0 may be claimed by an internal device. The ICH7 compares the non-zero Bus
Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-to-
PCI bridges to determine if the configuration access is meant for Primary PCI, or some other
downstream PCI bus or PCI Express link.
Configuration accesses that are forwarded to the ICH7, but remain unclaimed by any device or
bridge, will result in a master abort.
3.5
I/O Mapped Registers
The (G)MCH contains two registers that reside in the processor I/O address space: the
Configuration Address (CONFIG_ADDRESS) register and the Configuration Data
(CONFIG_DATA) register. The Configuration Address register enables/disables the
configuration space and determines what portion of configuration space is visible through the
Configuration Data window.
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57
Register Description
3.5.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
0CF8h (Accessed as a DWord)
00000000h
R/W
Size:
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or Word
reference will "pass through" the Configuration Address Register and DMI onto the Primary PCI
bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent configuration access is
intended.
Bit
Access
&
Default
Description
31
R/W
0b
PCI Configuration Space Enable (CFGE):
1 = Enabled. Accesses to PCI configuration space are Enabled.
0 = Disabled.
Reserved
30:24
23:16
R/W
00h
Bus Number: If the Bus Number is programmed to 00h, the target of the
configuration cycle is a PCI Bus 0 agent. If this is the case and the (G)MCH is not
the target (i.e., the device number is 2), then a DMI type 0 configuration cycle is
generated.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by
Device 1’s Secondary Bus Number or Subordinate Bus Number register, then a
DMI type 1 configuration cycle is generated.
If the Bus Number is non-zero and matches the value programmed into the
Secondary Bus Number Register of device 1, a type 0 PCI configuration cycle will
be generated on PCI Express*.
If the Bus Number is non-zero, greater than the value in the Secondary Bus
Number register of Device 1, and less than or equal to the value programmed into
the Subordinate Bus Number register of Device 1, a type 1 PCI configuration cycle
will be generated on PCI Express.
This field is mapped to byte 8 [7:0] of the request header format during PCI
Express configuration cycles and A[23:16] during the DMI type 1 configuration
cycles.
15:11
R/W
00h
Device Number: This field selects one agent on the PCI bus selected by the Bus
Number. When the Bus Number field is 00h, the (G)MCH decodes the Device
Number field. The (G)MCH is always Device Number 0 for the Host bridge entity,
Device Number 1 for the Host-PCI Express entity, and Device Number 2 for the
Internal Graphics Control (82945G/82945GC/82945GZ GMCH only). Therefore,
when the
Bus Number =0 and the Device Number equals 0, 1, or 2
(82945G/82945GC/82945GZ GMCH only), the internal GMCH devices are
selected.
This field is mapped to byte 6 [7:3] of the request header format during PCI
Express configuration cycles and A [15:11] during the DMI configuration cycles.
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Register Description
Bit
Access
&
Default
Description
10:8
R/W
000b
Function Number: This field allows the configuration registers of a particular
function in a multi-function device to be accessed. The (G)MCH ignores
configuration cycles to its internal devices if the function number is not equal to 0
or 1.
This field is mapped to byte 6 [2:0] of the request header format during PCI
Express configuration cycles and A[10:8] during the DMI configuration cycles.
7:2
1:0
R/W
00h
Register Number: This field selects one register within a particular bus, device,
and function as specified by the other fields in the Configuration Address Register.
This field is mapped to byte 7 [7:2] of the request header format during PCI
Express configuration cycles and A[7:2] during the DMI Configuration cycles.
Reserved
3.5.2
CONFIG_DATA—Configuration Data Register
I/O Address:
Default Value:
Access:
0CFCh
00000000h
R/W
Size:
32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
Bit
Access &
Default
Description
31:0
R/W
0000 0000h
Configuration Data Window (CDW): If bit 31 of the CONFIG_ADDRESS
Register is 1, any I/O access to the CONFIG_DATA register will produce a
configuration transaction using the contents of CONFIG_ADDRESS to
determine the bus, device, function, and offset of the register to be accessed.
§
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
59
Register Description
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Host Bridge/DRAM Controller Registers (D0:F0)
4 Host Bridge/DRAM Controller
Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Table 4-1 provides an
address map of the D0:F0 registers listed by address offset in ascending order. Section 4.1
provides a detailed bit description of the registers.
Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to
reserved register locations may return non-zero values. Writes to reserved locations may cause
system failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in
this component are simply not included in this document. The reserved/unimplemented space in
the PCI configuration header space is not documented as such in this summary.
Table 4-1. Host Bridge/DRAM Controller Register Address Map (D0:F0)
Address
Offset
Default
Value
Symbol
Register Name
Vendor Identification
Access
00–01h
02–03h
04–05h
06–07h
08h
VID
DID
8086h
2770h
0006h
0090h
RO
RO
Device Identification
PCI Command
PCICMD
PCISTS
RID
RO, R/W
RO, R/WC
RO
PCI Status
Revision Identification
see register
description
09–0Bh
0Ch
CC
—
Class Code
00h
—
RO
—
Reserved
0Dh
MLT
Master Latency Timer
Header Type
00h
RO
RO
—
0Eh
HDR
—
00h
0F–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
Reserved
—
SVID
SID
Subsystem Vendor Identification
Subsystem Identification
Reserved
0000h
0000h
—
R/WO
R/WO
—
—
CAPPTR
—
Capabilities Pointer
Reserved
E0h
RO
—
35–3Fh
40–43h
44–47h
—
EPBAR
MCHBAR
Egress Port Base Address
00000000h
00000000h
RO
R/W
GMCH Memory Mapped Register Range
Base Address
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61
Host Bridge/DRAM Controller Registers (D0:F0)
Address
Symbol
Offset
Default
Value
Register Name
Access
48–4Bh
PCIEXBAR
PCI Express* Register Range Base Address
(Intel® 82945G/82945GC/82945P/82945PL
(G)MCH Only)
E0000000h
R/W
4C–4Fh
DMIBAR
Root Complex Register Range Base
Address
00000000h
R/W
50–51h
52–53h
—
Reserved
—
—
GGC
GMCH Graphics Control Register
0030h
R/W/L
(82945G/82945GC/82945GZ GMCH only)
54–57h
DEVEN
Device Enable
See register
description
R/W
58–8Fh
90h
—
Reserved
—
—
PAM0
PAM1
PAM2
PAM3
PAM4
PAM5
PAM6
LAC
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Programmable Attribute Map 4
Programmable Attribute Map 5
Programmable Attribute Map 6
Legacy Access Control
00h
00h
00h
00h
00h
00h
00h
00h
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
91h
92h
93h
94h
95h
96h
97h
98–9Bh
9Ch
9Dh
—
Reserved
TOLUD
SMRAM
Top of Low Usable DRAM
System Management RAM Control
08h
00h
R/W
RO, R/W,
R/W/L
9Eh
ESMRAMC
—
Extended System Management RAM Control
Reserved
38h
—
RO, R/W/L
—
9F–C7h
C8–C9h
CA–CBh
CC–DBh
DC–DFh
E0–E8h
ERRSTS
ERRCMD
—
Error Status
0000h
0000h
—
RO, R/W/L
R/W
Error Command
Reserved
—
SKPD
Scratchpad Data
Capability Identifier
00000000h
R/W
CAPID0
See register
description
RO
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1
Device 0 Configuration Register Details
4.1.1
VID—Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
00h
8086h
RO
Size:
16 bits
This register, combined with the Device Identification register, uniquely identifies any PCI
device.
Bit
Access
&
Default
Description
15:0
RO
Vendor Identification Number (VID): This field provides the PCI standard
8086h
identification for Intel.
4.1.2
DID—Device Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
02h
2770h
RO
Size:
16 bits
This register, combined with the Vendor Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID): This field provides an identifier assigned to
2770h
the (G)MCH core/primary PCI device.
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1.3
PCICMD—PCI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
04h
0006h
RO, R/W
16 bits
Size:
Since (G)MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are not
implemented.
Bit
Access &
Default
Description
15:10
9
Reserved
RO
0b
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master
can do fast back-to-back write. Since device 0 is strictly a target, this bit is not
implemented and is hardwired to 0.
8
R/W
0b
SERR Enable (SERRE): This bit is a global enable bit for Device 0 SERR
messaging. The (G)MCH does not have a SERR signal. The (G)MCH
communicates the SERR condition by sending an SERR message over DMI to the
Intel® ICH7.
1 = The (G)MCH is enabled to generate SERR messages over DMI for specific
Device 0 error conditions that are individually enabled in the ERRCMD
register. The error status is reported in the ERRSTS and PCISTS registers.
0 = The SERR message is not generated by the (G)MCH for Device 0.
NOTE: This bit only controls SERR messaging for the Device 0. Device 1 has its
own SERRE bits to control error reporting for error conditions occurring in
that device. The control bits are used in a logical OR manner to enable the
SERR DMI message mechanism.
7
6
5
4
RO
0b
Address/Data Stepping Enable (ADSTEP): Hardwired to 0. Address/data
stepping is not implemented in the (G)MCH.
RO
0b
Parity Error Enable (PERRE): Hardwired to 0. PERR# is not implemented by the
(G)MCH.
RO
0b
VGA Palette Snoop Enable (VGASNOOP): Hardwired to 0. The (G)MCH does
not implement this bit.
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The (G)MCH will
never issue memory write and invalidate commands.
3
2
Reserved
RO
1b
Bus Master Enable (BME): Hardwired to 1. The (G)MCH is always enabled as a
master.
1
0
RO
1b
Memory Access Enable (MAE): Hardwired to 1. The (G)MCH always allows
access to main memory.
RO
0b
I/O Access Enable (IOAE): Hardwired to 0. This bit is not implemented.
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1.4
PCISTS—PCI Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
06h
0090h
RO, R/WC
16 bits
Size:
This status register reports the occurrence of error events on Device 0’s PCI interface. Since the
(G)MCH Device 0 does not physically reside on Primary PCI, many of the bits are not
implemented.
Bit
15
14
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Hardwired to 0. Not implemented.
Signaled System Error (SSE): Software clears this bit by writing a 1 to it.
R/WC
0b
1 = (G)MCH Device 0 generated a SERR message over DMI for any enabled
Device 0 error condition. Device 0 error conditions are enabled in the
PCICMD, and ERRCMD registers. Device 0 error flags are read/reset from
the PCISTS, or ERRSTS registers.
0 = (G)MCH Device 0 did Not generate a SERR message over DMI.
13
12
R/WC
0b
Received Master Abort Status (RMAS): Software clears this bit by writing a 1 to
it.
1 = (G)MCH generated a DMI request that receives an Unsupported Request
completion packet.
0 = (G)MCH did Not generate a DMI request that receives an Unsupported
Request completion packet.
R/WC
0b
Received Target Abort Status (RTAS): Software clears this bit by writing a 1 to it.
1 = (G)MCH generated a DMI request that receives a Completer Abort
completion packet.
0 = (G)MCH did Not generate a DMI request that receives a Completer Abort
completion packet.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. Not implemented. The
(G)MCH will not generate a Target Abort DMI completion packet or Special Cycle.
10:9
RO
00b
DEVSEL Timing (DEVT): These bits are hardwired to 00. Device 0 does not
physically connect to Primary PCI. These bits are set to "00" (fast decode) so that
optimum DEVSEL timing for Primary PCI is not limited by the (G)MCH.
8
7
RO
0b
Master Data Parity Error Detected (DPD): Hardwired to 0. Not implemented.
PERR signaling and messaging are not implemented by the (G)MCH.
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. Device 0 does not physically connect
to the Primary PCI. This bit is set to 1 (indicating fast back-to-back capability) so
that the optimum setting for the Primary PCI is not limited by the (G)MCH.
6
5
Reserved
RO
0b
66 MHz Capable: Hardwired to 0. Does not apply to PCI Express*.
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Host Bridge/DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
4
RO
1b
Capability List (CLIST): Hardwired to 1 to indicate to the configuration software
that this device/function implements a list of new capabilities. A list of new
capabilities is accessed via the CAPPTR register (address offset 34h). The
CAPPTR register contains an offset pointing to the start address within
configuration space of this device where the Capability standard register resides.
3:0
Reserved
4.1.5
RID—Revision Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
08h
See bit description
RO
Size:
8 bits
This register contains the revision number of the (G)MCH Device 0.
Bit
Access &
Default
Description
7:0
RO
Revision Identification Number (RID): This is an 8-bit value that indicates the
revision identification number for the (G)MCH Device 0. Refer to the Intel®
945G/945GC/945GZ/945P/945PL Express Chipset Specification Update for the
value of the Revision ID register.
4.1.6
CC—Class Code (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
09h
060000h
RO
Size:
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a register-
specific programming interface.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This is an 8-bit value that indicates the base class code
06h
for the (G)MCH.
06h = Bridge device.
15:8
7:0
RO
00h
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of
bridge for the (G)MCH.
00h = Host Bridge.
RO
00h
Programming Interface (PI): This is an 8-bit value that indicates the programming
interface of this device. This value does not specify a particular register set layout
and provides no practical use for this device.
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1.7
MLT—Master Latency Timer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
0Dh
00h
RO
8 bits
Size:
Device 0 in the (G)MCH is not a PCI master. Therefore, this register is not implemented.
Bit
Access &
Default
Description
7:0
Reserved
4.1.8
HDR—Header Type (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
0Eh
00h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Access &
Default
Description
7:0
RO
00h
PCI Header (HDR): This field always returns 0 to indicate that the (G)MCH is a
single function device with standard header layout. Reads and writes to this
location have no effect.
4.1.9
SVID—Subsystem Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
2Ch
0000h
R/WO
16 bits
Size:
This value is used to identify the vendor of the subsystem.
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-
up to indicate the vendor of the system board. After it has been written once, it
becomes read only.
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67
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.10
SID—Subsystem Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
2Eh
0000h
R/WO
16 bits
Size:
This value is used to identify a particular subsystem.
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem ID (SUBID): This field should be programmed during BIOS
initialization. After it has been written once, it becomes read only.
4.1.11
CAPPTR—Capabilities Pointer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
34h
E0h
RO
8 bits
Size:
The CAPPTR register provides the offset that is the pointer to the location of the first device
capability in the capability list.
Bit
Access &
Default
Description
7:0
RO
Pointer to the offset of the first capability ID register block: In this case the
E0h
first capability is the product-specific Capability Identifier (CAPID0).
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1.12
EPBAR—Egress Port Base Address (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
40h
00000000h
RO
Size:
32 bits
This is the base address for the Egress Port MMIO configuration space. There is no physical
memory within this 4-KB window that can be addressed. The 4 KB reserved by this register does
not alias to any PCI 2.3 compliant memory-mapped space.
On reset, the Egress Port MMIO Base Address field in this register is disabled and must be
enabled by writing a 1 to the EPBAREN bit.
Bit
Access &
Default
Description
31:12
R/W
Egress Port MMIO Base Address: This field corresponds to bits 31:12 of the
00000h
base address Egress Port MMIO configuration space.
BIOS will program this register resulting in a base address for a 4-KB block of
contiguous memory address space. This register ensures that a naturally aligned
4-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH MMIO register
set.
11:1
0
Reserved
R/W
0b
EPBAR Enable (EPBAREN):
0 = EPBAR is disabled and does not claim any memory.
1 = EPBAR memory-mapped accesses are claimed and decoded appropriately.
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1.13
MCHBAR—(G)MCH Memory Mapped Register Range Base
Address (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
44h
00000000h
R/W
Size:
32 bits
This is the base address for the (G)MCH memory-mapped configuration space. There is no
physical memory within this 16-KB window that can be addressed. The 16 KB reserved by this
register does not alias to any PCI 2.3 compliant memory-mapped space.
On reset, the (G)MCH Memory Mapped Base Address field in this register is disabled and must
be enabled by writing a 1 to the MCHBAREN bit.
Bit
Access &
Default
Description
31:14
R/W
(G)MCH Memory Mapped Base Address: This field corresponds to bits 31:14 of
00000h
the base address (G)MCH memory-mapped configuration space.
BIOS will program this register resulting in a base address for a 16-KB block of
contiguous memory address space. This register ensures that a naturally aligned
16-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH memory-mapped
register set.
13:1
0
Reserved
R/W
0b
MCHBAR Enable (MCHBAREN):
0 = MCHBAR is disabled and does not claim any memory.
1 = MCHBAR memory-mapped accesses are claimed and decoded appropriately
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Host Bridge/DRAM Controller Registers (D0:F0)
4.1.14
PCIEXBAR—PCI Express* Register Range Base Address
(D0:F0) (Intel® 82945G/82945GC/82945P/82945PL (G)MCH
Only)
PCI Device:
Address Offset:
Default Value:
Access:
0
48h
E0000000h
R/W
Size:
32 bits
This is the base address for the PCI Express configuration space. This window of addresses
contains the 4 KB of configuration space for each PCI Express device that can potentially be part
of the PCI Express hierarchy associated with the (G)MCH. This window of up to 256-MB does
not contain actual physical memory that can be addressed. The actual length is determined by a
field in this register. Each PCI Express hierarchy requires a PCI Express ase register. The
(G)MCH supports one PCI Express hierarchy.
The region reserved by this register does not alias to any PCI 2.3 compliant memory-mapped
space. For example, MCHBAR reserves a 16-KB space outside of PCIEXBAR space. It cannot be
overlaid on the space reserved by PCIEXBAR for device 0.
On reset, this register is disabled and must be enabled by writing a 1 to the enable field in this
register. This base address shall be assigned on a boundary consistent with the number of buses
defined by the Length field in this register), above TOLUD and still within total 32 bit
addressable memory space.
All other bits not decoded are read only 0. The PCI Express Base Address cannot be less than the
maximum address written to the top of physical memory register (TOLUD). Software must ensure
that these ranges do not overlap with known ranges located above TOLUD.
Bit
Access &
Default
Description
31:28
R/W
Eh
PCI Express* Base Address: This field corresponds to bits 31:28 of the base
address for PCI Express enhanced configuration space. BIOS will program this
register resulting in a base address for a contiguous memory address space; size
is defined by bits 2:1 of this register.
This base address shall be assigned on a boundary consistent with the number of
buses (defined by the Length field in this register) above TOLUD and still within
total 32-bit addressable memory space. The address bits decoded depends on the
length of the region defined by this register.
The address used to access the PCI Express configuration space for a specific
device can be determined as follows:
PCI Express Base Address + Bus Number * 1 MB + Device Number * 32 KB +
Function Number * 4 KB
The address used to access the PCI Express configuration space for Device 1 in
this component would be PCI Express Base Address + 0 * 1 MB + 1 * 32 KB +
0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this address is the
beginning of the 4 KB space that contains both the PCI compatible configuration
space and the PCI Express extended configuration space.
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Host Bridge/DRAM Controller Registers (D0:F0)
Bit
Access &
Default
Description
27
R/W
0b
128 MB Base Address Mask (128ADMSK): This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask (RO, read 0b),
depending on the value of bits 2:1 in this register.
26
R/W
0b
64 MB Base Address Mask (64ADMSK): This bit is either part of the PCI Express
Base Address (R/W) or part of the Address Mask (RO, read 0b), depending on the
value of bits 2:1 in this register
25:3
2:1
Reserved
R/W
00b
Length (LENGTH): This field describes the length of this region.
00 = 256 MB (buses 0–255). Bits 31:28 are decoded in the PCI Express Base
Address Field
01 = 128 MB (Buses 0–127). Bits 31:27 are decoded in the PCI Express Base
Address Field.
10 = 64 MB (Buses 0–63). Bits 31:26 are decoded in the PCI Express Base
Address Field.
11 = Reserved
0
R/W
0h
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write transactions
proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:26 are
R/W with no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and write transactions
whose address bits 31:26 match PCIEXBAR will be translated to
configuration reads and writes within the (G)MCH.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.15
DMIBAR—Root Complex Register Range Base Address
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
4Ch
00000000h
R/W
Size:
32 bits
This is the base address for the Root Complex configuration space. This window of addresses
contains the Root Complex Register set for the PCI Express hierarchy associated with the
(G)MCH. There is no physical memory within this 4-KB window that can be addressed. The
4 KB reserved by this register does not alias to any PCI 2.3 compliant memory-mapped space.
On reset, the DMI Base Address field in this register is disabled and must be enabled by writing a
1 to the DMIBAREN bit.
Bit
Access &
Default
Description
31:12
R/W
DMI Base Address: This field corresponds to bits 31:12 of the base address DMI
00000 h
configuration space.
BIOS will program this register resulting in a base address for a 4-KB block of
contiguous memory address space. This register ensures that a naturally aligned
4-KB space is allocated within total addressable memory space of 4 GB (2 GB for
the 82945GC, 82945GZ and 82945PL).
System Software uses this base address to program the DMI register set.
Reserved
11:1
0
R/W
0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory.
1 = DMIBAR memory-mapped accesses are claimed and decoded appropriately.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
73
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.16
GGC—GMCH Graphics Control Register (D0:F0) (Intel®
82945G/82945GC/82945GZ GMCH Only)
PCI Device:
Address Offset:
Default Value:
Access:
0
52h
0030h
R/W/L
16 bits
Size:
Bit
Access &
Default
Descriptions
15:7
6:4
Reserved
R/W/L
011 b
Graphics Mode Select (GMS): This field selects the amount of main memory
that is pre-allocated to support the internal graphics device in VGA (non-linear)
and native (linear) modes. BIOS ensures that memory is pre-allocated only when
internal graphics is enabled.
000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles
(Memory and I/O), and the Sub-Class Code field within D2:F0 Class Code
register is 80h.
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer.
010 = Reserved.
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer.
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
NOTE: This register is locked and becomes read only when the D_LCK bit in the
SMRAM register is set.
3:2
1
Reserved
R/W
0 b
IGD VGA Disable (IVD):
0 = Enable. Device 2 (IGD) claims VGA cycles (memory and I/O); the Sub-Class
Code within Device 2 Class Code register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (memory and I/O); the
Sub-Class Code field within D2:F0 Class Code register is 80h.
0
Reserved
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.17
DEVEN—Device Enable (D0:F0)
PCI Device:
0
Address Offset:
Default Value:
54h
82945G/82945GC/82945GZ GMCH: 0000001Bh
82945P/82945PL MCH: 00000003h
Access:
Size:
R/W
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within the
(G)MCH.
Bit
Access &
Default
Description
31:5
4
Reserved
R/W
1b
(GMCH)
82945G/82945GC/82945GZ GMCH
Internal Graphics Engine Function 1 (D2F1EN):
0 = Disable. Bus0:D2:F1 is disabled and hidden
1 = Enable. Bus0:D2:F1 is enabled and visible
0b
(MCH)
NOTE: Setting this bit to enabled when bit 3 is 0 has no meaning.
82945P/82945PL MCH
Reserved.
3
R/W
1b
(GMCH)
82945G/82945GC/82945GZ GMCH
Internal Graphics Engine Function 0 (D2F0EN):
0 = Disable. Bus0:D2:F0 is disabled and hidden
1 = Enable. Bus0:D2:F0 is enabled and visible
82945P/82945PL MCH
0b
(MCH)
Reserved
2
1
Reserved
R/W
1b
82945G/82945GC/82945P/82945PL (G)MCH
PCI Express* Port (D1EN):
0 = Disable. Bus0:D1:F0 is disabled and hidden.
1 = Enable. Bus0:D1:F0 is enabled and visible.
82945GZ GMCH
Reserved
0
RO
1b
Host Bridge: Hardwired to 1. Bus0:D0:F0 can not be disabled.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
75
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.18
PAM0—Programmable Attribute Map 0 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
90h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h–
0FFFFFh
The (G)MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 768-KB to 1-MB address range. Seven Programmable Attribute Map (PAM)
registers are used to support these features. Two bits are used to specify memory attributes for
each memory segment. These bits apply to both host accesses and PCI initiator accesses to the
PAM areas. These attributes are:
RE (Read Enable). When RE = 1, the processor read accesses to the corresponding memory
segment are claimed by the (G)MCH and directed to main memory. Conversely, when
RE = 0, the host read accesses are directed to Primary PCI.
WE (Write Enable). When WE = 1, the host write accesses to the corresponding memory
segment are claimed by the (G)MCH and directed to main memory. Conversely, when
WE = 0, the host write accesses are directed to Primary PCI.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write,
or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read
Only.
Each PAM Register controls two regions, typically 16 KB in size.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0F0000h–0FFFFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that addresses the BIOS area from 0F0000 to 0FFFFF.
00 = DRAM Disabled: All accesses are directed to the DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to the DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:0
Reserved
Warning: The (G)MCH may hang if a PCI Express graphics attach or DMI-originated access to read
disabled or write disabled PAM segments occur (due to a possible IWB to non-DRAM). For these
reasons, the following critical restriction is placed on the programming of the PAM regions:
At the time that a DMI or PCI Express graphics attach accesses to the PAM
region may occur, the targeted PAM segment must be programmed to be both
readable and writeable.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.19
PAM1—Programmable Attribute Map 1 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
91h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h–
0C7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0C4000h–0C7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0C0000h–0C3FFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
77
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.20
PAM2—Programmable Attribute Map 2 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
92h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h–
0CFFFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0CC000h–0CFFFFh Attribute (HIENABLE):
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0C8000h–0CBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.21
PAM3—Programmable Attribute Map 3 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
93h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h–
0D7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00 b
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00 b
0D0000h–0D3FFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
79
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.22
PAM4—Programmable Attribute Map 4 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
94h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h–
0DFFFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00 b
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00 b
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D8000h to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.23
PAM5—Programmable Attribute Map 5 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
95h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h–
0E7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
81
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.24
PAM6—Programmable Attribute Map 6 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
96h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h–
0EFFFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.25
LAC—Legacy Access Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
97h
00h
R/W
8 bits
Size:
This register controls a fixed DRAM hole from 15–16 MB.
Bit
Access
&
Default
Description
7
R/W
0 b
Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM
that lies "behind" this space is not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
6:1
0
Reserved
R/W
0 b
MDA Present (MDAP): This bit works with the VGA Enable bits in the BCTRL
register of Device 1 to control the routing of processor-initiated transactions targeting
MDA compatible I/O and memory address ranges. This bit should not be set if
device 1's VGA Enable bit is not set.
If device 1's VGA enable bit is not set, accesses to I/O address range x3BCh–x3BFh
are forwarded to the DMI.
If the VGA enable bit is set and MDA is not present, accesses to I/O address range
x3BCh–x3BFh are forwarded to PCI Express*, if the address is within the
corresponding IOBASE and IOLIMIT; otherwise, the accesses are forwarded to the
DMI.
MDA resources are defined as the following:
Memory:
I/O:
0B0000h–0B7FFFh
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(Including ISA address aliases, A [15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to the DMI even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN
MDAP
Description
0
0
All References to MDA and VGA space are routed to the
DMI
0
1
1
0
Invalid combination
All VGA and MDA references are routed to PCI Express
graphics attach.
1
1
All VGA references are routed to PCI Express graphics
attach. MDA references are routed to the DMI
VGA and MDA memory cycles can only be routed across the PCI Express when
MAE (PCICMD1[1]) is set.
VGA and MDA I/O cycles can only be routed across the PCI Express if IOAE
(PCICMD1[0]) is set.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
83
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.26
TOLUD—Top of Low Usable DRAM (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
9Ch
08h
R/W
8 bits
Size:
This register defines the Top of Low usable DRAM. TSEG and graphics stolen memory are
within the DRAM space defined. From the top of the DRAM space, the (G)MCH optionally
claims 1 to 8 MBs of DRAM for internal graphics if enabled, and 1, 2, or 8 MB of DRAM for
TSEG if enabled.
Bit
Access &
Default
Description
7:3
R/W
01h
Top of Low Usable DRAM (TOLUD): This register contains bits 31:27 of an
address one byte above the maximum DRAM memory that is usable by the
operating system. Address bits 31:27 programmed to 01h implies a minimum
memory size of 128 MBs.
Configuration software must set this value to the smaller of the following 2 choices:
Maximum amount of memory in the system plus one byte or
Minimum address allocated for PCI memory
Address bits 26:0 are assumed to be 000_0000h for the purposes of address
comparison. The Host interface positively decodes an address intended for DRAM
if the incoming address is less than the value programmed in this register.
If this register is set to 0000 0b, it implies 128 MBs of system memory.
NOTE: The Top of Low Usable memory is the lowest address above both graphics
stolen memory and TSEG. The host interface determines the base of
graphics stolen memory by subtracting the Graphics Stolen Memory Size
from TOLUD and further decrements by 1 MB to determine the base of
TSEG.
2:0
Reserved
Programming Example (82945G GMCH only):
C1DRB7 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Internal graphics is enabled and Graphics Mode Select is set to 32 MB
BIOS knows the OS requires 1GB of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This
20-MB range at the very top of addressable memory space is lost to APIC.
According to the above equation, TOLUD is originally calculated to: 4 GB = 1_0000_0000h
The system memory requirements are:
4 GB (max addressable space) – 1 GB (PCI space) – 20 MB (lost memory) =
3 GB – 128 MB (minimum granularity) = B800_0000h
Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h; TOLUD
should be programmed to B8h.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.27
SMRAM—System Management RAM Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
9Dh
02h
R/W, RO, R/W/L
8 bits
Size:
The SMRAMC register controls how accesses to compatible and extended SMRAM spaces are
treated. The Open, Close, and Lock bits function only when the G_SMRAME bit is set to a 1.
Also, the OPEN bit must be reset before the LOCK bit is set.
Bit
Access &
Default
Description
7
6
Reserved
R/W/L
0b
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM
space DRAM is made visible even when SMM decode is not active. This is
intended to help BIOS initialize SMM space. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
5
4
R/W
0b
SMM Space Closed (D_CLS): When D_CLS = 1, SMM space DRAM is not
accessible to data references, even if SMM decode is active. Code references
may still access SMM space DRAM. This will allow SMM software to reference
through SMM space to update the display, even when SMM is mapped over the
VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set
at the same time.
R/W/L
0b
SMM Space Locked (D_LCK): When D_LCK is set to 1, then D_OPEN is reset
to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and
TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration
space write but can only be cleared by a Full Reset. The combination of D_LCK
and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to "lock down"
SMM space in the future so that no application software (or BIOS itself) can
violate the integrity of SMM space, even if the program has knowledge of the
D_OPEN function.
3
R/W/L
0b
Global SMRAM Enable (G_SMRAME): If set to a 1, Compatible SMRAM
functions are enabled, providing 128 KB of DRAM accessible at the A0000h
address while in SMM (ADSB with SMM decode). To enable Extended SMRAM
function this bit has be set to 1. Refer to the Section 9.4 for more details. Once
D_LCK is set, this bit becomes read only.
2:0
RO
010b
Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates
the location of SMM space. SMM DRAM is not remapped. It is simply made
visible if the conditions are right to access SMM space; otherwise, the access is
forwarded to DMI. Since the (G)MCH supports only the SMM space between
A0000h and BFFFFh, this field is hardwired to 010.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
85
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.28
ESMRAMC—Extended System Management RAM Control
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
9Eh
38h
R/W/L, RO
8 bits
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 MB.
Bit
Access &
Default
Description
7
R/W/L
0 b
Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space
location (i.e., above 1 MB or below 1 MB). When G_SMRAME=1 and
H_SMRAME=1, the high SMRAM memory space is enabled. SMRAM accesses
within the range 0FEDA0000h to 0FEDBFFFFh are remapped to DRAM
addresses within the range 000A0000h to 000BFFFFh. Once D_LCK has been
set, this bit becomes read only.
6
R/WC
0 b
Invalid SMRAM Access (E_SMERR): This bit is set when the processor has
accessed the defined memory ranges in Extended SMRAM (High Memory and
TSEG) while not in SMM space and with D_OPEN = 0. It is software’s
responsibility to clear this bit. Software must write a 1 to this bit to clear it.
5
4
RO
1 b
SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the (G)MCH .
L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the (G)MCH.
L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the (G)MCH.
RO
1 b
3
RO
1 b
2:1
R/W/L
00 b
TSEG Size (TSEG_SZ): This field selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space is partitioned away so that it may
only be accessed by the processor interface and only then when the SMM bit is
set in the request packet. Non-SMM accesses to this memory region are sent to
the DMI when the TSEG memory block is enabled.
00 = 1-MB TSEG (TOLUD – Graphics Stolen Memory Size – 1M) to
(TOLUD – Graphics Stolen Memory Size).
01 = 2-MB TSEG (TOLUD – Graphics Stolen Memory Size – 2M) to
(TOLUD – Graphics Stolen Memory Size).
10 = 8-MB TSEG (TOLUD – Graphics Stolen Memory Size – 8M) to
(TOLUD – Graphics Stolen Memory Size).
11 = Reserved.
Once D_LCK has been set, these bits become read only.
0
R/W/L
0 b
TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM
space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to
appear in the appropriate physical address space. Note that once D_LCK is set,
this bit becomes read only.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.29
ERRSTS—Error Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
C8h
0000h
R/WC/S, RO
16 bits
Size:
This register is used to report various error conditions via the SERR DMI messaging mechanism.
A SERR DMI message is generated on a 0-to-1 transition of any of these flags (if enabled by the
ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is
enabled and generated. After the error processing is complete, the error logging mechanism can
be unlocked by clearing the appropriate status bit by software writing a 1 to it.
Bit
Access &
Default
Description
15:13
12
Reserved
R/WC/S
0b
(G)MCH Software Generated Event for SMI:
1 = Source of the SMI was a Device 2 software event.
(G)MCH Thermal Sensor Event for SMI/SCI/SERR:
11
R/WC/S
0b
1 =A (G)MCH Thermal Sensor trip has occurred and a SMI, SCI, or SERR has
been generated. The status bit is set only if a message is sent based on
Thermal event enables in the Error Command, SMI Command, and SCI
Command registers. A trip point can generate one of SMI, SCI, or SERR
interrupts (two or more per event is Invalid). Multiple trip points can generate
the same interrupt. If software chooses this mode, subsequent trips may be
lost. If this bit is already set, an interrupt message will not be sent on a new
thermal sensor event.
10
9
Reserved
R/WC/S
0b
LOCK to non-DRAM Memory Flag (LCKF):
1 =(G)MCH has detected a lock operation to memory space that did not map into
DRAM.
8
R/WC/S
0b
Received Refresh Timeout Flag(RRTOF):
1 = 1024 memory core refreshes are enqueued.
Reserved
7:0
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
87
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.30
ERRCMD—Error Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
CAh
0000h
R/W
16 bits
Size:
This register controls the (G)MCH responses to various system errors. Since the (G)MCH does
not have a SERR# signal, SERR messages are passed from the (G)MCH to the ICH7 over DMI.
When a bit in this register is set, a SERR message will be generated on DMI when the
corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is
globally enabled for Device 0 via the PCI Command register.
Bit
Access &
Default
Description
15:12
11
Reserved
R/W
0b
SERR on (G)MCH Thermal Sensor Event (TSESERR)
1 =Enable. The (G)MCH generates a DMI SERR special cycle when bit 11 of the
ERRSTS register is set. The SERR must not be enabled at the same time as
the SMI for the same thermal sensor event.
0 =Disable. Reporting of this condition via SERR messaging is disabled.
Reserved
10
9
R/W
0b
SERR on LOCK to non-DRAM Memory (LCKERR)
1 =Enable. The (G)MCH will generate a DMI SERR special cycle when a
processor lock cycle is detected that does not hit DRAM.
0 =Disable. Reporting of this condition via SERR messaging is disabled.
8
R/W
0b
SERR on DRAM Refresh Timeout (DRTOERR)
1 =Enable. The (G)MCH generates a DMI SERR special cycle when a DRAM
Refresh timeout occurs.
0 =Disable. Reporting of this condition via SERR messaging is disabled.
Reserved
7:0
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.1.31
SKPD—Scratchpad Data (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
DCh
00000000h
R/W
Size:
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the convenience of
BIOS and graphics drivers.
Bit
Access &
Default
Description
31:0
R/W
Scratchpad Data: 1 DWord of data storage.
00000000 h
4.1.32
CAPID0—Capability Identifier (D0:F0)
PCI Device:
0
Address Offset:
Default Value:
E0h
82945G/82945GC/82945GZ GMCH:
000000000001090009h
82945P/82945PL MCH:
000000000001090009h
Access:
Size:
RO
72 bits
Bit
Access &
Default
Description
71:28
27:24
Reserved
RO
1h
CAPID Version: This field has the value 0001b to identify the first revision of the
CAPID register definition.
23:16
15:8
7:0
RO
09h
CAPID Length: This field has the value 09h to indicate the structure length
(9 bytes).
RO
00h
Next Capability Pointer: This field is hardwired to 00h indicating the end of the
capabilities linked list.
RO
CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the
09h
PCI SIG for vendor dependent capability pointers.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
89
Host Bridge/DRAM Controller Registers (D0:F0)
4.2
MCHBAR Register
The MCHBAR registers are offset from the MCHBAR base address. Table 4-2 provides an
address map of the registers listed by address offset in ascending order. Detailed register bit
descriptions follow the table.
Table 4-2. MCHBAR Register Address Map
Address
Offset
Symbol
Register Name
Default
Value
Access
100h
101h
C0DRB0
C0DRB1
Channel A DRAM Rank Boundary Address 0
Channel A DRAM Rank Boundary Address 1
Channel A DRAM Rank Boundary Address 2
Channel A DRAM Rank Boundary Address 3
Channel A DRAM Rank 0,1 Attribute
Channel A DRAM Rank 2,3 Attribute
Channel A DRAM Clock Disable
00h
00h
R/W
R/W
102h
C0DRB2
00h
R/W
103h
C0DRB3
00h
R/W
108h
C0DRA0
00h
RO, R/W
RO, R/W
RO, R/W
RO, R/W
R/W, RO
RO, R/W
109h
C0DRA2
00h
10Ch
C0DCLKDIS
C0BNKARC
C0DRT1
00h
10E–10Fh
114–117h
120–123h
Channel A DRAM Bank Architecture
Channel A DRAM Timing Register 1
Channel A DRAM Controller Mode 0
0000h
02903D22h
C0DRC0
4000280_
00ssh
124–127h
180h
C0DRC1
C1DRB0
C1DRB1
C1DRB2
C1DRB3
C1DRA0
C1DRA2
C1DCLKDIS
C1BNKARC
C1DRT1
Channel A DRAM Controller Mode 1
Channel B DRAM Rank Boundary Address 0
Channel B DRAM Rank Boundary Address 1
Channel B DRAM Rank Boundary Address 2
Channel B DRAM Rank Boundary Address 3
Channel B DRAM Rank 0,1 Attribute
Channel B DRAM Rank 2,3 Attribute
Channel B DRAM Clock Disable
00000000h
00h
R/W
R/W
181h
00h
R/W
182h
00h
R/W
183h
00h
R/W
188h
00h
RO, R/W
RO, R/W
RO, R/W/L
RO, R/W
RO
189h
00h
18Ch
00h
18E–18Fh
194–197h
1A0–1A3h
Channel B Bank Architecture
0000h
02903D22h
Channel B DRAM Timing Register 1
Channel B DRAM Controller Mode 0
C1DRC0
4000280_
00ssh
RO, R/W
1A4–1A7h
C1DRC1
Channel B DRAM Controller Mode 1
00000000h
R/W, RO,
R/W/L
F10–F13h
F14–F17h
PMCFG
PMSTS
Power Management Configuration
Power Management Status
00000000h
00000000h
R/W, RO
R/WC/S
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.1
C0DRB0—Channel A DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
100h
00h
R/W
Size:
8 bits
The DRAM Rank Boundary register defines the upper boundary address of each DRAM rank
with a granularity of 32 MB. Each rank has its own single-byte DRB register. These registers are
used to determine which chip select will be active for a given address.
Channel and rank map:
Channel A Rank 0: 100h
Channel A Rank 1: 101h
Channel A Rank 2: 102h
Channel A Rank 3: 103h
Channel B Rank 0: 180h
Channel B Rank 1: 181h
Channel B Rank 2: 182h
Channel B Rank 3: 183h
Single Channel or Asymmetric Channels Example
If the channels are independent, addresses in Channel B should begin where addresses in Channel
A left off, and the address of the first rank of Channel A can be calculated from the technology
(256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a
value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and
the top address in that rank is 32 MB.
Programming guide:
If Channel A is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in chA rank0 (in 32-MB increments)
C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments)
––––
C1DRB0 = Total memory in chA rank0 + chA rank1 + chA rank2 + chA rank3 + chB rank0
(in 32-MB increments)
If Channel B is empty, all of the C1DRBs are programmed with the same value as C0DRB3.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host Bridge/DRAM Controller Registers (D0:F0)
Interleaved Channels Example
If channels are interleaved, corresponding ranks in opposing channels will contain the same value,
and the value programmed takes into account the fact that twice as many addresses are spanned
by this rank compared to the single-channel case. With interleaved channels, a value of 01h in
C0DRB0 and a value of 01h in C1DRB0 indicate that 32 MB of DRAM has been populated in
the first rank of each channel and the top address in that rank of either channel is 64 MB.
Programming guide:
C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32-MB increments)
C0DRB1 = C1DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments)
––––
C0DRB3 = C1DRB3 = Total memory in chA rank0 + chA rank1+ chA rank2 + chA rank3
(in 32-MB increments)
In all modes, if a DIMM is single sided, it appears as a populated rank and an empty rank. A DRB
must be programmed appropriately for each mode.
Each Rank is represented by a byte. Each byte has the following format.
Bit
Access &
Default
Description
7:0
R/W
00h
Channel A DRAM Rank Boundary Address: This 8 bit value defines the upper
and lower addresses for each DRAM rank. Bits 6:2 are compared against
Address 31:27 to determine the upper address limit of a particular rank. Bits 1:0
must be 0s. For the 82945G and 82945P, bit 7 may be programmed to a 1 in the
highest DRB (DRB3) if 4 GBs of memory are present.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.2
4.2.3
4.2.4
C0DRB1—Channel A DRAM Rank Boundary Address 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
101h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
C0DRB2—Channel A DRAM Rank Boundary Address 2
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
102h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
C0DRB3—Channel A DRAM Rank Boundary Address 3
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
103h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
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93
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.5
C0DRA0—Channel A DRAM Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
108h
00h
R/W
Size:
8 bits
The DRAM Rank Attribute registers define the page sizes to be used when accessing different
ranks. These registers should be left with their default value (all zeros) for any rank that is
unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in
the CxDRA registers describes the page size of a pair of ranks.
Channel and rank map:
Channel A Rank 0, 1: 108h
Channel A Rank 2, 3: 109h
Channel B Rank 0, 1: 188h
Channel B Rank 2, 3: 189h
Bit
Access &
Default
Description
7
Reserved
6:4
R/W
Channel A DRAM odd Rank Attribute: This 3-bit field defines the page size of
000b
the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
3
Reserved
2:0
R/W
Channel A DRAM even Rank Attribute: This 3-bit field defines the page size of
000b
the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
4.2.6
C0DRA2—Channel A DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
109h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRA0 register.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.7
C0DCLKDIS—Channel A DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
10Ch
00h
R/W
Size:
8 bits
This register can be used to disable the system memory clock signals to each DIMM slot, which
can significantly reduce EMI and power concerns for clocks that go to unpopulated DIMMs.
Clocks should be enabled based on whether a slot is populated, and what kind of DIMM is
present.
Note: Since there are multiple clock signals assigned to each rank of a DIMM, it is important to clarify
exactly which rank width field affects which clock signal.
Bit
Access &
Default
Description
7:6
5
Reserved
R/W
0b
DIMM Clock Gate Enable Pair 5:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
4
3
2
1
0
R/W
0b
DIMM Clock Gate Enable Pair 4:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 3:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 2:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 1:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 0:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
Channel
Rank
Clocks Affected
0
0
1
1
0 or 1
2 or 3
0 or 1
2 or 3
SCLK_A[2:0]/ SCLK_A[2:0]#
SCLK_A[5:3]/ SCLK_A[5:3]#
SCLK_B[2:0]/ SCLK_B[2:0]#
SCLK_B[5:3]/ SCLK_B[5:3]#
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Host Bridge/DRAM Controller Registers (D0:F0)
4.2.8
C0BNKARC—Channel A DRAM Bank Architecture
PCI Device:
Function:
MCHBAR
0
Address Offset:
Default Value:
Access:
10E–10Fh
0000h
R/W
Size:
16 bits
This register is used to program the bank architecture for each rank.
Bit
Access &
Default
Description
15:8
7:6
Reserved
R/W
00b
Rank 3 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
5:4
3:2
1:0
R/W
00b
Rank 2 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
R/W
00b
Rank 1 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
R/W
00b
Rank 0 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.9
C0DRT1—Channel A DRAM Timing Register
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
114–117h
02903D22h
R/W
Size:
32 bits
Bit
Access &
Default
Description
31:23
22:19
Reserved
R/W
9h
Activate to Precharge delay (tRAS): This bit controls the number of DRAM
clocks for tRAS. The minimum recommendations are beside their corresponding
encodings.
0h – 3h = Reserved
4h – Fh = Four to fifteen clocks respectively.
18:10
9:8
Reserved
R/W
01b
CAS# Latency (tCL): This value is programmable on DDR2 DIMMs. The value
programmed here must match the CAS Latency of every DDR2 DIMM in the
system.
00 = 5
01 = 4
10 = 3
11 = 6
7
Reserved
6:4
R/W
DRAM RAS to CAS Delay (tRCD): This bit controls the number of clocks inserted
010b
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 = 6 DRAM clocks
101–111 = Reserved
3
Reserved
2:0
R/W
010b
DRAM RAS Precharge (tRP): This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 = 6 DRAM clocks
101–111 = Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
97
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.10
C0DRC0—Channel A DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
120–123h
400028_00ssh (s = strap dependent)
RO, R/W
32 bits
Size:
Access &
Default
Bit
Description
31:30
29
01b
Reserved
R/W
0b
Initialization Complete (IC): This bit is used for communication of the software
state between the memory controller and BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete.
28:11
10:8
00h
Reserved
R/W
Refresh Mode Select (RMS): This field determines whether refresh is enabled
000b
and, if so, at what rate refreshes will be executed.
000 = Refresh disabled
001 = Refresh enabled. Refresh interval 15.6 usec
010 = Refresh enabled. Refresh interval 7.8 usec
011 = Refresh enabled. Refresh interval 3.9 usec
100 = Refresh enabled. Refresh interval 1.95 usec
111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other = Reserved
7
RO
0b
Reserved
98
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
Access &
Default
Bit
Description
6:4
R/W
Mode Select (SMS): These bits select the special operational mode of the
000b
DRAM interface. The special modes are intended for initialization at power up.
000 = Post Reset state – When the (G)MCH exits reset (power-up or otherwise),
the mode select field is cleared to 000. During any reset sequence, while
power is applied and reset is active, the (G)MCH de-asserts all CKE
signals. After internal reset is de-asserted, CKE signals remain de-
asserted until this field is written to a value different than 000. On this
event, all CKE signals are asserted. During suspend, (G)MCH internal
signal triggers DRAM controller to flush pending commands and enter all
ranks into Self-Refresh mode. As part of resume sequence, the (G)MCH
will be reset, which will clear this bit field to 000 and maintain CKE signals
de-asserted. After internal reset is de-asserted, the CKE signals remain
de-asserted until this field is written to a value different than 000. On this
event, all CKE signals are asserted. During entry to other low power states
(C3, S1), the (G)MCH internal signal triggers the DRAM controller to flush
pending commands and enter all ranks into Self-Refresh mode. During
exit to normal mode, the (G)MCH signal triggers the DRAM controller to
exit Self-Refresh and resume normal operation without software
involvement.
001 = NOP Command Enable – All processor cycles to DRAM result in a NOP
command on the DRAM interface.
010 = All Banks Pre-charge Enable – All processor cycles to DRAM result in an
"all banks precharge" command on the DRAM interface.
011 = Mode Register Set Enable – All processor cycles to DRAM result in a
"mode register" set command on the DRAM interface. Host address lines
are mapped to DRAM address lines in order to specify the command sent,
as shown in Volume 1, System Memory Controller section, memory
Detection and Initialization. Refer to JEDEC Standard 79-2A Section 2.2.2
“Programming the Mode and Extended Mode Registers”.
100 = Extended Mode Register Set Enable – All processor cycles to DRAM
result in an "extended mode register set" command on the DRAM
interface. Host address lines are mapped to DRAM address lines in order
to specify the command sent, as shown in Volume 1, System Memory
Controller section, memory Detection and Initialization. Refer to JEDEC
Standard 79-2A Section 2.2.2 “Programming the Mode and Extended
Mode Registers”.
110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in
a CBR cycle on the DRAM interface.
111 = Normal operation
3:2
1:0
Reserved
RO
ss
DRAM Type (DT): This field is used to select between supported SDRAM types.
00 = Reserved
01 = Reserved
10 = Second Revision Dual Data Rate (DDR2) SDRAM
11 = Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
99
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.11
C0DRC1—Channel A DRAM Controller Mode 1
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
124–127h
00000000h
R/W
Size:
32 bits
Bit
Access &
Default
Description
31
R/W
0b
Enhanced Addressing Enable (ENHADE):
0 = Enhanced Addressing mode disabled. The DRAM address map follows the
standard address map.
1 = Enhanced Address mode enabled. The DRAM address map follows the
enhanced address map.
30:0
Intel Reserved
4.2.12
4.2.13
4.2.14
C1DRB0—Channel B DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
180h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
C1DRB1—Channel B DRAM Rank Boundary Address 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
181h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
C1DRB2—Channel B DRAM Rank Boundary Address 2
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
182h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
100
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.15
C1DRB3—Channel B DRAM Rank Boundary Address 3
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
183h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRB0 register.
4.2.16
4.2.17
4.2.18
4.2.19
C1DRA0—Channel B DRAM Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
188h
00h
RO, R/W
8 bits
Size:
The operation of this register is detailed in the description for the C0DRA0 register.
C1DRA2—Channel B DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
189h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for the C0DRA0 register.
C1DCLKDIS—Channel B DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
18Ch
00h
RO, R/W/L
8 bits
Size:
The operation of this register is detailed in the description for the C0DCLKDIS register.
C1BNKARC—Channel B Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
18E–18Fh
0000h
RO, R/W
16 bits
Size:
The operation of this register is detailed in the description for the C0BNKARC register.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
101
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.20
4.2.21
4.2.22
4.2.23
C1DRT1—Channel B DRAM Timing Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
194–197h
02903D22h
RO
Size:
32 bits
The operation of this register is detailed in the description for the C0DRT1 register.
C1DRC0—Channel B DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
1A0–1A3h
4000280_00ssh (s = strap dependent)
RO, R/W
32 bits
Size:
The operation of this register is detailed in the description for the C0DRC0 register.
C1DRC1—Channel B DRAM Controller Mode 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
1A4–1A7h
00000000h
RO, R/W, R/W/L
32 bits
Size:
The operation of this register is detailed in the description for the C0DRC1 register.
PMCFG—Power Management Configuration
PCI Device:
Address Offset:
Default:
Access:
Size:
MCHBAR
F10–F13h
00000000h
RO, R/W
32 bits
Bit
Access &
Default
Description
31:5
4
Reserved
R/W
0b
Enhanced Power Management Features Enable:
0 = Legacy power management mode
1 = Reserved.
3:0
Reserved
102
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.2.24
PMSTS—Power Management Status
PCI Device:
Address Offset:
Default:
MCHBAR
F14–F17h
00h
Access:
Size:
R/WC/S
32 bits
This register is reset by PWROK only.
Bit
Access &
Default
Description
31:2
1
Reserved
R/WC/S
0b
Channel B in self-refresh: This bit is set by power management hardware after
Channel B is placed in self refresh as a result of a Power State or a Warm Reset
sequence.
This bit is cleared by power management hardware before starting Channel B
self refresh exit sequence initiated by a power management exit.
This bit is cleared by the BIOS in a warm reset (Reset# asserted while PWROK
is asserted) exit sequence.
0 = Channel B not ensured to be in self refresh.
1 = Channel B in self refresh.
0
R/WC/S
0b
Channel A in Self-refresh: This bit is set by power management hardware after
Channel A is placed in self refresh as a result of a Power State or a Reset Warn
sequence.
This bit is cleared by power management hardware before starting Channel A
self refresh exit sequence initiated by a power management exit.
This bit is cleared by the BIOS in a warm reset (Reset# asserted while PWROK
is asserted) exit sequence.
0 = Channel A not ensured to be in self refresh.
1 = Channel A in self refresh.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
103
Host Bridge/DRAM Controller Registers (D0:F0)
4.3
EPBAR Registers—Egress Port Register Summary
The MCHBAR registers are offset from the EPBAR base address. Table 4-3 provides an address
map of the registers listed by address offset in ascending order. Detailed bit descriptions of the
registers follow the table. Link Declaration Topology is shown in Figure 4-1.
Table 4-3. Egress Port Register Address Map
Address
Symbol
Offset
Default
Value
Register Name
Access
044h–047h
050h–053h
EPESD
EPLE1D
EPLE1A
EP Element Self Description
EP Link Entry 1 Description
EP Link Entry 1 Address
00000201h
01000000h
R/WO, RO
R/WO, RO
R/WO, RO
058h–
05Fh
000000000
0000000h
060h–063h
EPLE2D
EPLE2A
EP Link Entry 2 Description
EP Link Entry 2 Address
02000002h
R/WO, RO
RO
068h–
06Fh
000000000
0008000h
Figure 4-1. Link Declaration Topology
(G)MCH
X16
PEG
(Port #2)
Link #2
(Type 1)
Link #1
(Type 0)
Egress Port
(Port #0)
Main Memory
Subsystem
Link #2
(Type 0)
Link #1
(Type 0)
DMI
(Port #1)
Link #1
(Type 0)
X4
Intel® ICH7
Egress Port
(Port #0)
Egress_LinkDeclar_Topo
104
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.3.1
EPESD—EP Element Self Description
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
044–047h
00000201h
RO, R/WO
32 bits
Size:
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access &
Default
Description
31:24
RO
Port Number: This field specifies the port number associated with this element
00h
with respect to the component that contains this element.
00h = Indicates to configuration software that this is the default egress port.
23:16
15:8
R/WO
00h
Component ID: This field identifies the physical component that contains this
Root Complex Element. Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
RO
02h
Number of Link Entries: This field indicates the number of link entries following
the Element Self Description. This field reports 2 (one each for PCI Express* and
DMI).
7:4
3:0
Reserved
RO
01h
Element Type: This field indicates the type of the Root Complex Element.
1h = Represents a port to system memory
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
105
Host Bridge/DRAM Controller Registers (D0:F0)
4.3.2
EPLE1D—EP Link Entry 1 Description
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
050–053h
01000000h
RO, R/WO
32 bits
Size:
This register provides the first part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
31:24
RO
01h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (DMI). The target port number is with respect to
the component that contains this element as specified by the target component ID.
23:16
R/WO
00h
Target Component ID: This field identifies the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:2
1
Reserved
RO
0b
Link Type: This bit indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
0
R/WO
0b
Link Valid:
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
106
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
4.3.3
EPLE1A—EP Link Entry 1 Address
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
058–05Fh
00000000_00000000h
R/WO
Size:
64 bits
This register is the second part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
63:32
31:12
Reserved
R/WO
Link Address: This field provides the memory mapped base address of the
0 0000h
RCRB that is the target element (DMI) for this link entry.
11:0
Reserved
4.3.4
EPLE2D—EP Link Entry 2 Description
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
060–63h
02000002h
RO, R/WO
32 bits
Size:
This register provides the first part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
31:24
RO
02h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (PCI Express). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
23:16
R/WO
00h
Target Component ID: This field identifies the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:2
1
Reserved
RO
1b
Link Type: This bit indicates that the link points to configuration space of the
integrated device that controls the x16 root port. The link address specifies the
configuration address (segment, bus, device, function) of the target root port.
0
R/WO
0b
Link Valid:
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
107
Host Bridge/DRAM Controller Registers (D0:F0)
4.3.5
EPLE2A—EP Link Entry 2 Address
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
068–06Fh
0000000000008000h
RO
Size:
64 bits
This register is the second part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
63:28
27:20
Reserved
RO
Bus Number
00h
19:15
14:12
11:0
RO
0 0001b
Device Number: Target for this link is PCI Express* x16 port (Device 1).
RO
000b
Function Number
Reserved
§
108
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5 Host-PCI Express* Bridge
Registers (D1:F0) (Intel®
82945G/82945GC/82945P/82945PL
Only)
Device 1 contains the controls associated with the PCI Express x16 root port that is the intended
to attach as the point for external graphics. It is typically referred to as PCI Express (PCI Express
graphics) port. In addition, it also functions as the virtual PCI-to-PCI bridge. Table 5-1 provides
an address map of the D1:F0 registers listed by address offset in ascending order. Section 5.1
provides a detailed bit description of the registers.
Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a valid value
unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits: Reserved and Preserved.
Reserved for future RW implementations; software must preserve value read for writes to
bits.
Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for
writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are part of the
Reserved and Preserved type, which have historically been the typical definition for Reserved.
Note: Most (if not all) control bits in this device cannot be modified unless the link is down. Software is
required to first Disable the link, then program the registers, and then re-enable the link (which
will cause a full-retrain with the new settings).
Table 5-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0)
Address
Offset
Default
Value
Symbol
Register Name
Access
00–01h
02–03h
04–05h
06–07h
08h
VID1
DID1
Vendor Identification
8086h
2771h
0000h
0010h
RO
RO
Device Identification
PCI Command
PCICMD1
PCISTS1
RID1
RO, R/W
RO, R/W
RO
PCI Status
Revision Identification
See register
description
09–0Bh
0Ch
CC1
CL1
—
Class Code
Cache Line Size
Reserved
060400h
00h
RO
R/W
—
0Dh
—
0Eh
HDR1
Header Type
01h
RO
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
109
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Address
Offset
Default
Value
Symbol
Register Name
Access
0F–17h
18h
—
Reserved
—
00h
—
RO
PBUSN1
SBUSN1
SUBUSN1
—
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reserved
19h
00h
RO
1Ah
00h
R/W
1Bh
—
—
1Ch
IOBASE1
IOLIMIT1
SSTS1
I/O Base Address
F0h
RO
1Dh
I/O Limit Address
00h
R/W
1Eh–1Fh
20–21h
22–23h
24–25h
26–27h
28–33h
34h
Secondary Status
00h
RO, R/WC
R/W
MBASE1
MLIMIT1
PMBASE1
PMLIMIT1
—
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Reserved
FFF0h
0000h
FFF0h
0000h
—
R/W
RO, R/W
RO, R/W
—
CAPPTR1
—
Capabilities Pointer
88h
RO
35–3Bh
3Ch
Reserved
—
—
INTRLINE1
INTRPIN1
BCTRL1
—
Interrupt Line
00h
R/W
3Dh
Interrupt Pin
01h
RO
3E–3Fh
40–7Fh
80–83h
84–87h
88–8Bh
8C–8Fh
90–91h
Bridge Control
0000h
—
RO, R/W
—
Reserved
PM_CAP1
PM_CS1
SS_CAPID
SS
Power Management Capabilities
Power Management Control/Status
Subsystem ID and Vendor ID Capabilities
Subsystem ID and Subsystem Vendor ID
C8029001h
00000000h
0000800Dh
00008086h
A005h
RO
RO, R/W/S
RO
RO
MSI_CAPID
Message Signaled Interrupts Capability
ID
RO
92–93h
94–97h
98–99h
9A–9Fh
A0–A1h
A2–A3h
A4–A7h
A8–A9h
AA–ABh
AC–AFh
B0–B1h
B2–B3h
B4–B7h
B8–B9h
BA–BBh
MC
MA
Message Control
Message Address
Message Data
Reserved
0000h
00000000h
0000h
RO, R/W
RO, R/W
R/W
MD
—
—
—
PEG_CAPL
PEG_CAP
DCAP
PCI Express* Capability List
PCI Express* Capabilities
Device Capabilities
Device Control
Device Status
0010h
RO
0141h
RO
00000000h
0000h
RO
DCTL
R/W
DSTS
0000h
RO
LCAP
Link Capabilities
Link Control
02014D01h
0000h
R/WO
RO, R/W
RO
LCTL
LSTS
Link Status
1001h
SLOTCAP
SLOTCTL
SLOTSTS
Slot Capabilities
Slot Control
00000000h
01C0h
R/WO
RO, R/W
RO, R/WC
Slot Status
0000h
110
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Address
Offset
Default
Value
Symbol
Register Name
Access
BC–BDh
BE–BFh
C0–C3h
C4–FFh
EC–EFh
100–103h
RCTL
—
Root Control
Reserved
0000h
—
R/W
—
RSTS
—
Root Status
Reserved
00000000h
—
RO, R/WC
—
PEG_LC
VCECH
PCI Express* Legacy Control
00000000h
14010002h
R/W
Virtual Channel Enhanced Capability
Header
RO
104–107h
108–10Bh
10C–10Dh
10E–10Fh
110–113h
114–117h
118–119h
11A–11Bh
11C–11Fh
120–123h
124–125h
126–127h
128–13Fh
140–143h
PVCCAP1
PVCCAP2
PVCCTL
—
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
00000001h
00000001h
0000h
RO, R/WO
RO
R/W
—
Reserved
—
VC0RCAP
VC0RCTL
—
VC0 Resource Capability
VC0 Resource Control
Reserved
00000000h
800000FFh
—
RO
RO, R/W
—
VC0RSTS
VC1RCAP
VC1RCTL
—
VC0 Resource Status
VC1 Resource Capability
VC1 Resource Control
Reserved
0002h
RO
00008000h
01000000h
—
RO
RO, R/W
—
VC1RSTS
—
VC1 Resource Status
Reserved
0002h
RO
—
—
RCLDECH
Root Complex Link Declaration
Enhanced Capability Header
00010005h
RO
144–147h
148–14Fh
150–153h
154–157h
158–15Fh
ESD
—
Element Self Description
Reserved
02000100h
RO, R/WO
—
—
00000000h
—
LE1D
—
Link Entry 1 Description
Reserved
RO, R/WO
—
LE1A
Link Entry 1 Address
0000000000
000000h
R/WO
160–1C5h
1C4–1C7h
1C8–1CBh
1D0–1D3h
1D4–1D3h
1D4–1D7h
1D8–217h
218–21Fh
—
UESTS
UEMSK
CESTS
—
Reserved
—
—
RO, R/WC/S
RO, R/W/S
RO, R/W/S
—
Uncorrectable Error Status
Uncorrectable Error Mask
Correctable Error Status
Reserved
00000000h
00000000h
00000000h
—
CEMSK
—
Correctable Error Mask
Reserved
00000000h
—
R/W/S
—
PEG_SSTS
PCI Express* Sequence Status
0000000000
000FFFh
RO
220–FFFh
—
Reserved
—
—
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
111
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1
Configuration Register Details (D1:F0)
5.1.1
VID1—Vendor Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
00h
8086h
RO
Size:
16 bits
This register, combined with the Device Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Vendor Identification (VID1): This field provides the PCI standard identification for
8086 h
Intel.
5.1.2
DID1—Device Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
02h
2771h
RO
Size:
16 bits
This register, combined with the Vendor Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID1): This field is an identifier assigned to the
2581h
(G)MCH device 1 (virtual PCI-to-PCI bridge, PCI Express* graphics port).
112
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.3
PCICMD1—PCI Command (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
04h
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15:11
10
Reserved
INTA Assertion Disable:
R/W
0b
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages.
Any INTA emulation interrupts already asserted must be de-asserted when this
bit is set.
This bit only affects interrupts generated by the device (PCI INTA from a PME or
Hot Plug event) controlled by this register. It does not affect upstream MSIs,
upstream PCI INTA-INTD assert and de-assert messages.
9
8
RO
0b
Fast Back-to-Back Enable (FB2B): Hardwired to 0. Not Applicable or
Implemented.
R/W
0b
SERR Message Enable (SERRE1): This bit is an enable bit for Device 1 SERR
messaging. The (G)MCH communicates the SERR# condition by sending a
SERR message to the Intel® ICH7. This bit, when set, enables reporting of non-
fatal and fatal errors to the Root Complex. Note that errors are reported if
enabled either through this bit or through the PCI Express* specific bits in the
Device Control register.
0 =Disable. The SERR message is generated by the (G)MCH for Device 1 only
under conditions enabled individually through the Device Control register.
1 =Enable. The (G)MCH is enabled to generate SERR messages that will be
sent to the ICH7 for specific Device 1 error conditions generated/detected on
the primary side of the virtual PCI-to-PCI Express bridge (not those received
by the secondary side). The error status is reported in the PCISTS1 register.
7
6
Reserved
R/WO
0b
Parity Error Enable (PERRE): This bit controls whether or not the Master Data
Parity Error bit in the PCI Status register can bet set.
0 = Disable. Master Data Parity Error bit in PCI Status register cannot be set.
1 = Enable. Master Data Parity Error bit in PCI Status register can be set.
VGA Palette Snoop: Hardwired to 0. Not Applicable or Implemented.
5
4
3
RO
0b
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. Not Applicable or
Implemented.
RO
0b
Special Cycle Enable (SCE): Hardwired to 0. Not Applicable or Implemented.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Bit
Access &
Default
Description
2
R/W
0b
Bus Master Enable (BME): This bit controls the ability of the PCI Express port to
forward memory and I/O read/write requests in the upstream direction.
0 = Disable. This device is prevented from making memory or I/O requests to its
primary bus. Note that according to PCI Local Bus Specification, as MSI
interrupt messages are in-band memory writes, disabling the bus master
enable bit prevents this device from generating MSI interrupt messages or
passing them from its secondary bus to its primary bus. Upstream memory
writes/reads, I/O writes/reads, peer writes/reads, and MSIs will all be treated
as invalid cycles. Writes are forwarded to memory address 0h with byte
enables de-asserted. Reads will be forwarded to memory address 0h and
will return Unsupported Request status (or Master abort) in its completion
packet.
1 = Enable. This device is allowed to issue requests to its primary bus.
Completions for previously issued memory read requests on the primary
bus will be issued when the data is available.
This bit does not affect forwarding of completions from the primary interface to
the secondary interface.
1
0
R/W
0b
Memory Access Enable (MAE):
0 = Disable. All of device 1’s memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges defined in
the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
R/W
0b
IO Access Enable (IOAE):
0 = Disable. All of device 1’s I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1
registers.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.4
PCISTS1—PCI Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
06h
0010h
RO, R/WC
16 bits
Size:
This register reports the occurrence of error conditions associated with the primary side of the
“virtual” Host-PCI Express bridge in the (G)MCH.
Bit
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Hardwired to 0. Not Applicable or Implemented.
Parity (generating poisoned TLPs) is not supported on the primary side of this
device; the (G)MCH does Not do error forwarding.
14
R/WC
0b
Signaled System Error (SSE):
1 =This Device sent a SERR due to detecting an ERR_FATAL or
ERR_NONFATAL condition and the SERR Enable bit in the Command
register is 1. Both received (if enabled by BCTRL1[1]) and internally detected
error messages do not affect this field.
13
12
RO
0b
Received Master Abort Status (RMAS): Hardwired to 0. Not Applicable or
Implemented. The concept of a master abort does not exist on primary side of
this device.
RO
0b
Received Target Abort Status (RTAS): Hardwired to 0. Not Applicable or
Implemented. The concept of a target abort does not exist on primary side of this
device.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. Not Applicable or
Implemented. The concept of a target abort does not exist on primary side of this
device.
10:9
8
RO
00b
DEVSELB Timing (DEVT): This device is not the subtractive decoded device on
bus 0. This bit field is therefore hardwired to 00 to indicate that the device uses
the fastest possible decode.
RO
0b
Master Data Parity Error (PMDPE): Because the primary side of the PCI
Express’s virtual PCI-to-PCI bridge is integrated with the (G)MCH functionality,
there is no scenario where this bit will get set. Because hardware will not set this
bit, it is impossible for software to have an opportunity to clear this bit or
otherwise test that it is implemented. The PCI specification defines it as a R/WC,
but for this implementation, a RO definition behaves the same way and will meet
all Microsoft testing requirements.
7
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0. Not Applicable or Implemented.
6
5
Reserved
RO
0b
66/60MHz capability (CAP66): Hardwired to 0. Not Applicable or Implemented.
4
RO
1b
Capabilities List: Hardwired to 1. This indicates that a capabilities list is present.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Bit
Access &
Default
Description
3
RO
0b
INTA Status:
1 =An interrupt message is pending internally to the device. Only PME and Hot
Plug sources feed into this status bit (not PCI INTA-INTD assert and de-
assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no
effect on this bit.
2:0
Reserved
5.1.5
RID1—Revision Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
08h
See bit description
RO
Size:
8 bits
This register contains the revision number of the (G)MCH device 1. These bits are read only and
writes to this register have no effect.
Bit
Access &
Default
Description
7:0
RO
Revision Identification Number (RID1): This field indicates the number of times
that this device in this component has been “stepped” through the manufacturing
process. It is always the same as the RID values in all other devices in this
component. Refer to the Intel® 945G/945GC/945GZ/945P/945PL Express Chipset
Specification Update for the value of the Revision ID register.
5.1.6
CC1—Class Code (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
09h
060400h
RO
Size:
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a register-
specific programming interface.
Bit
Access &
Default
Description
23:16
RO
06h
Base Class Code (BCC): This field indicates the base class code for this device.
06h = Bridge device.
15:8
7:0
RO
04h
Sub-Class Code (SUBCC): This field indicates the sub-class code for this device.
04h = PCI-to-PCI bridge.
RO
00h
Programming Interface (PI): This field indicates the programming interface of this
device. This value does not specify a particular register set layout and provides no
practical use for this device.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.7
CL1—Cache Line Size (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
0Ch
00h
R/W
8 bits
Size:
Bit
Access &
Default
Description
7:0
R/W
00h
Cache Line Size (Scratch pad): This field is implemented by PCI Express*
devices as a read-write field for legacy compatibility purposes but has no impact
on any PCI Express device functionality.
5.1.8
HDR1—Header Type (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
0Eh
01h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Access &
Default
Description
7:0
RO
Header Type Register (HDR): This field returns 01h to indicate that this is a single
01h
function device with bridge header layout.
5.1.9
PBUSN1—Primary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
18h
00h
RO
8 bits
Size:
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus 0.
Bit
Access &
Default
Description
7:0
RO
00h
Primary Bus Number (BUSN): Configuration software typically programs this field
with the number of the bus on the primary side of the bridge. Since device 1 is an
internal device and its primary bus is always 0, these bits are read only and are
hardwired to 0s.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.10
SBUSN1—Secondary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
19h
00h
RO
8 bits
Size:
This register identifies the bus number assigned to the second bus side of the “virtual” bridge (i.e.,
to PCI Express). This number is programmed by the PCI configuration software to allow mapping
of configuration cycles to PCI Express.
Bit
Access &
Default
Description
7:0
R/W
00h
Secondary Bus Number (BUSN): This field is programmed by configuration
software with the bus number assigned to PCI Express.
5.1.11
SUBUSN1—Subordinate Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Ah
00h
R/W
8 bits
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI Express.
This number is programmed by the PCI configuration software to allow mapping of configuration
cycles to PCI Express.
Bit
Access &
Default
Description
7:0
R/W
00h
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device 1 bridge. When only a single PCI device resides on the PCI
Express segment, this register will contain the same value as the SBUSN1
register.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.12
IOBASE1—I/O Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Ch
F0h
RO
8 bits
Size:
This register controls the processor-to-PCI Express I/O access routing based on the following
formula:
IO_BASE address IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]
are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB
boundary.
Bit
Access &
Default
Description
7:4
R/W
Fh
I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O
addresses passed by bridge 1 to PCI Express. BIOS must not set this register to
00h; otherwise, 0CF8h/0CFCh accesses will be forwarded to the PCI Express
hierarchy associated with this device.
3:0
Reserved
5.1.13
IOLIMIT1—I/O Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Dh
00h
R/W
8 bits
Size:
This register controls the processor-to-PCI Express I/O access routing based on the following
formula:
IO_BASE address IO_LIMIT
Only the upper 4 bits are programmable. For the purposes of address decode, address bits A[11:0]
are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-
KB aligned address block.
Bit
Access &
Default
Description
7:4
R/W
0h
I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O
address limit of device 1. Devices between this upper limit and IOBASE1 will be
passed to the PCI Express hierarchy associated with this device.
3:0
Reserved
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.14
SSTS1—Secondary Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Eh
00h
RO, R/WC
16 bits
Size:
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the
secondary side (i.e., PCI Express side) of the “virtual” PCI-PCI Bridge in the (G)MCH.
Bit
Access &
Default
Description
15
R/WC
0b
Detected Parity Error (DPE):
0 =Parity error Not detected.
1 =The (G)MCH received across the link (upstream) a Posted Write Data
Poisoned TLP (EP=1).
14
13
12
R/WC
0b
Received System Error (RSE):
0 =System error Not received.
1 =The secondary side sent an ERR_FATAL or ERR_NONFATAL message due
to an error detected by the secondary side, and the SERR Enable bit in the
Bridge Control register is 1.
R/WC
0b
Received Master Abort (RMA):
0 =Master abort Not received.
1 =The Secondary Side for Type 1 Configuration Space Header Device (for
requests initiated by the Type 1 Header Device itself) receives a completion
with Unsupported Request Completion Status.
R/WC
0b
Received Target Abort (RTA):
0 =Target abort Not received.
1 =The Secondary Side for Type 1 Configuration Space Header Device (for
requests initiated by the Type 1 Header Device itself) receives a Completion
with Completer Abort completion status.
11
RO
0b
Signaled Target Abort (STA): Hardwired to 0. Not Applicable or Implemented.
The (G)MCH does not generate Target Aborts (the (G)MCH will never complete
a request using the Completer Abort completion status).
10:9
RO
DEVSELB Timing (DEVT): Hardwired to 0. Not Applicable or Implemented.
00b
8
7
Reserved
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0. Not Applicable or Implemented.
6
5
Reserved
RO
0b
66/60 MHz capability (CAP66): Hardwired to 0. Not Applicable or Implemented.
4:0
Reserved
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.15
MBASE1—Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
20h
FFF0h
R/W
16 bits
Size:
This register controls the processor-to-PCI Express non-prefetchable memory access routing
based on the following formula:
MEMORY_BASE address MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. The configuration software must initialize this register. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
Bit
15:4
3:0
Access &
Default
Description
R/W
FFFh
Memory Address Base (MBASE): This field corresponds to A[31:20] of the
lower limit of the memory range that will be passed to PCI Express.
Reserved
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.16
MLIMIT1—Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
22h
0000h
R/W
16 bits
Size:
This register controls the processor-to-PCI Express non-prefetchable memory access routing
based on the following formula:
MEMORY_BASE address MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. The configuration software must initialize this register. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1-MB aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-pre-fetchable PCI
Express address ranges (typically where control/status memory-mapped I/O data structures of the
graphics controller will reside) and PMBASE and PMLIMIT are used to map pre-fetchable
address ranges (typically, graphics local memory).
This segregation allows application of USWC space attribute to be performed in a true plug-and-
play manner to the pre-fetchable address range for improved processor -PCI Express memory
access performance.
Note: Configuration software is responsible for programming all address range registers (pre-fetchable,
non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with
each other and/or with the ranges covered with the main memory). There is no provision in the
(G)MCH hardware to enforce prevention of overlap and operations of the system in the case of
overlap may be affected.
Bit
15:4
3:0
Access &
Default
Description
R/W
000h
Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the
upper limit of the address range passed to PCI Express.
Reserved
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.17
PMBASE1—Prefetchable Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
24h
FFF0h
RO, R/W
16 bits
Size:
This register, in conjunction with the corresponding Upper Base Address register, controls the
processor-to-PCI Express prefetchable memory access routing based on the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A [31:20] of the
40-bit address. The lower 8 bits of the Upper Base Address register are read/write and correspond
to address bits A[39:32] of the 40-bit address. The configuration software must initialize this
register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the
bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit
Access &
Default
Description
15:4
R/W
FFFh
Prefetchable Memory Base Address (MBASE): This field corresponds to
A[31:20] of the lower limit of the memory range that will be passed to PCI
Express.
3:0
RO
0h
64-bit Address Support: This field indicates the bridge supports only 32-bit
address support.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.18
PMLIMIT1—Prefetchable Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
26h
0000h
RO, R/W
16 bits
Size:
This register, in conjunction with the corresponding Upper Limit Address register, controls the
processor-to-PCI Express prefetchable memory access routing based on the following formula:
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-
bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to
address bits A[39:32] of the 40-bit address. The configuration software must initialize this
register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh.
Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory
block. Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit
15:4
3:0
Access &
Default
Description
R/W
000h
Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to
A[31:20] of the upper limit of the address range passed to PCI Express.
RO
0h
64-bit Address Support: This field indicates the bridge only supports 32-bit
addresses.
5.1.19
CAPPTR1—Capabilities Pointer (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
34h
88h
RO
8 bits
Size:
The capabilities pointer provides the address offset to the location of the first entry in this
device’s linked list of capabilities.
Bit
Access &
Default
Description
7:0
RO
First Capability (CAPPTR1): The first capability in the list is the Subsystem ID
88h
and Subsystem Vendor ID Capability.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.20
INTRLINE1—Interrupt Line (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
3Ch
00h
R/W
8 bits
Size:
This register contains interrupt line routing information. The device itself does not use this value;
rather, device drivers and operating systems use it to determine priority and vector information.
Bit
Access &
Default
Description
7:0
R/W
00h
Interrupt Connection: This field is used to communicate interrupt line routing
information. POST software writes the routing information into this register as it
initializes and configures the system. The value in this register indicates which
input of the system interrupt controller is connected to this device’s interrupt pin.
5.1.21
INTRPIN1—Interrupt Pin (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
3Dh
01h
RO
8 bits
Size:
This register specifies which interrupt pin this device uses.
Bit
Access &
Default
Description
7:0
RO
Interrupt Pin: As a single function device, the PCI Express device specifies
01h
INTA as its interrupt pin.
01h=INTA.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.22
BCTRL1—Bridge Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
3Eh
0000h
RO, R/W
16 bits
Size:
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as
well as some bits that affect the overall behavior of the “virtual” Host-to-PCI Express bridge in
the (G)MCH (e.g., VGA compatible address ranges mapping).
Bit
Access &
Default
Description
15:12
11
Reserved
RO
0b
Discard Timer SERR Enable: Hardwired to 0. Not Applicable or Implemented.
Discard Timer Status: Hardwired to 0. Not Applicable or Implemented.
Secondary Discard Timer: Hardwired to 0. Not Applicable or Implemented.
Primary Discard Timer: Hardwired to 0. Not Applicable or Implemented.
10
9
RO
0b
RO
0b
8
RO
0b
7
RO
0b
Fast Back-to-Back Enable (FB2BEN): Hardwired to 0. Not Applicable or
Implemented.
6
R/W
0b
Secondary Bus Reset (SRESET):
0 = Hot reset not triggered on the corresponding PCI Express port.
1 = Setting this bit triggers a hot reset on the corresponding PCI Express port.
5
4
RO
0b
Master Abort Mode (MAMODE): Hardwired to 0. When acting as a master,
unclaimed reads that experience a master abort return all 1s and any writes that
experience a master abort complete normally and the data is discarded.
R/W
0b
VGA 16-bit Decode: This bit enables the PCI-to-PCI bridge to provide 16-bit
decoding of VGA I/O address precluding the decoding of alias addresses every
1 KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to
1, enabling VGA I/O decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
3
R/W
0b
VGA Enable (VGAEN): This bit controls the routing of processor-initiated
transactions targeting VGA compatible I/O and memory address ranges. See the
VGAEN/MDAP table in the LAC Register[0] (Device 0, offset 97h).
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Bit
Access &
Default
Description
2
R/W
0b
ISA Enable (ISAEN): This bit is used to exclude legacy resource decode to route
ISA resources to the legacy decode path. This bit modifies the response by the
(G)MCH to an I/O access issued by the processor that target ISA I/O addresses.
This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT
registers.
0 =All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express.
1 =(G)MCH will not forward to PCI Express any I/O transactions addressing the
last 768 bytes in each 1-KB block, even if the addresses are within the range
defined by the IOBASE and IOLIMIT registers. Instead of going to PCI
Express, these cycles are forwarded to DMI where they can be subtractively
or positively claimed by the ISA bridge.
1
0
R/W
0b
SERR Enable (SERREN):
0 =Disable. No forwarding of error messages from secondary side to primary
side that could result in a SERR.
1 =Enable. ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in
SERR message when individually enabled by the Root Control register.
RO
0b
Parity Error Response Enable (PEREN): This bit controls whether or not the
Master Data Parity Error bit in the Secondary Status register is set when the
(G)MCH receives across the link (upstream) a Read Data Completion Poisoned
TLP.
0 =Disable. Master Data Parity Error bit in Secondary Status register cannot be
set.
1 =Enable. Master Data Parity Error bit in Secondary Status register can be set.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.23
PM_CAPID1—Power Management Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
80h
C8029001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:27
RO
19h
PME Support: This field indicates the power states in which this device may
indicate PME wake via PCI Express messaging: D0, D3hot, and D3cold. This
device is not required to do anything to support D3hot and D3cold; it simply must
report that those states are supported. Refer to the PCI Power Management
Interface Specification, Revision 1.1 for encoding explanation and other power
management details.
26
25
RO
0b
D2: Hardwired to 0 to indicate that the D2 power management state is NOT
supported.
RO
0b
D1: Hardwired to 0 to indicate that the D1 power management state is NOT
supported.
24:22
21
RO
000b
Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
RO
0b
Device Specific Initialization (DSI): Hardwired to 0 to indicate that special
initialization of this device is NOT required before generic class device driver is to
use it.
20
19
RO
0b
Auxiliary Power Source (APS): Hardwired to 0.
RO
0b
PME Clock: Hardwired to 0 to indicate this device does NOT support PME#
generation.
18:16
RO
010b
PCI PM CAP Version: Hardwired to 02h to indicate there are 4 bytes of power
management registers implemented and that this device complies with the PCI
Power Management Interface Specification, Revision 1.1.
15:8
7:0
RO
90h / A0h
Pointer to Next Capability: This filed contains a pointer to the next item in the
capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, the next item in the capabilities
list is the Message Signaled Interrupts (MSI) capability at 90h. If MSICH
(CAPL[0] @ 7Fh) is 1, the next item in the capabilities list is the PCI Express
capability at A0h.
RO
Capability ID: The value of 01h identifies this linked list item (capability structure)
01h
as being for PCI Power Management registers.
128
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.24
PM_CS1—Power Management Control/Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
84–87h
00000000h
RO, R/W/S
32 bits
Size:
Bit
Access &
Default
Description
31:16
15
Reserved
PME Status: This bit indicates that this device does not support PME#
RO
0b
generation from D3
.
cold
14:13
12:9
8
RO
00b
Data Scale: This field indicates that this device does not support the Power
Management Data register.
RO
0h
Data Select: This field indicates that this device does not support the Power
Management Data register.
R/W/S
0b
PME Enable: This bit indicates that this device does not generate PME#
assertion from any D state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware. See PM_CAP[15:11]
Reserved
7:2
1:0
R/W
00b
Power State: This field indicates the current power state of this device and can
be used to set the device into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3. Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device
also cannot generate interrupts or respond to MMR cycles in the D3 state.
The device must return to the D0 state to be fully functional.
There is no hardware functionality required to support these power states.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.25
SS_CAPID—Subsystem ID and Vendor ID Capabilities
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
88h
0000800Dh
RO
Size:
32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides. Because
this device is an integrated part of the system and not an add-in device, it is anticipated that this
capability will never be used. However, it is necessary because Microsoft will test for its presence
as part of its compliance testing.
Bit
Access &
Default
Description
31:16
15:8
Reserved
RO
Pointer to Next Capability: This field contains a pointer to the next item in the
80h
capabilities list that is the PCI Power Management capability.
7:0
RO
Capability ID: The value of 0Dh identifies this linked list item (capability
0Dh
structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
5.1.26
SS—Subsystem ID and Subsystem Vendor ID (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
8Ch
00008086h
RO
Size:
32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These values
must be preserved through power management transitions and hardware reset.
Bit
Access &
Default
Description
31:16
15:0
R/WO
0000h
Subsystem ID (SSID): This field identifies the particular subsystem and is
assigned by the vendor.
R/WO
8086h
Subsystem Vendor ID (SSVID): This field identifies the manufacturer of the
subsystem and is the same as the vendor ID that is assigned by the PCI Special
Interest Group.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.27
MSI_CAPID—Message Signaled Interrupts Capability ID
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
90h
A005h
RO
Size:
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by writing a
predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @
7Fh). In that case going through this linked list will skip this capability and instead go directly
from the PCI PM capability to the PCI Express capability.
Bit
15:8
7:0
Access &
Default
Description
RO
A0h
Pointer to Next Capability: This field contains a pointer to the next item in the
capabilities list which is the PCI Express capability.
RO
Capability ID: The value of 05h identifies this linked list item (capability
05h
structure) as being for MSI registers.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.28
MC—Message Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
92h
0000h
RO, R/W
16 bits
Size:
System software can modify bits in this register, but the device is prohibited from doing
modifying the bits.
If the device writes the same message multiple times, only one of those messages is ensured to be
serviced. If all of them must be serviced, the device must not generate the same message again
until the driver services the previous one(s).
Bit
Access &
Default
Description
15:8
7
Reserved
RO
0b
64-bit Address Capable: Hardwired to 0 to indicate that the function does not
implement the upper 32 bits of the Message Address register and is incapable of
generating a 64-bit memory address.
6:4
3:1
R/W
000b
Multiple Message Enable (MME): System software programs this field to
indicate the actual number of messages allocated to this device. This number will
be equal to or less than the number actually requested. The encoding is the
same as for the MMC field (Bits 3:1).
RO
Multiple Message Capable (MMC): System software reads this field to
000b
determine the number of messages being requested by this device.
000 = 1
001–111 = Reserved
0
R/W
0b
MSI Enable (MSIEN): This bit controls the ability of this device to generate MSIs.
0 =Disable. MSI will not be generated.
1 =Enable. MSI will be generated when (G)MCH receive PME or HotPlug
messages. INTA will not be generated and INTA Status (PCISTS1[3]) will not
be set.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.29
MA—Message Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
94h
00000000h
RO, R/W
32 bits
Size:
Bit
Access &
Default
Description
31:2
R/W
00000000h
Message Address: This field is used by system software to assign a MSI
address to the device. The device handles a MSI by writing the padded
contents of the MD register to this address.
1:0
RO
Force DWord Align: Hardwired to 0s so that addresses assigned by system
00b
software are always aligned on a DWord address boundary.
5.1.30
MD—Message Data (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
98–99h
0000h
R/W
Size:
16 bits
Bit
Access &
Default
Description
15:0
R/W
Message Data: This field is the base message data pattern assigned by system
0000h
software and used to handle a MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16 bits are always
set to 0. This register supplies the lower 16 bits.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.31
PEG_CAPL—PCI Express* Capability List (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A0–A1h
0010h
RO
Size:
16 bits
This register enumerates the PCI Express capability structure.
Bit
Access &
Default
Description
15:8
RO
00h
Pointer to Next Capability: This value terminates the capabilities list. The Virtual
Channel capability and any other PCI Express specific capabilities that are
reported via this mechanism are in a separate capabilities list located entirely
within PCI Express extended configuration space.
7:0
RO
Capability ID: This field identifies this linked list item (capability structure) as
10h
being for PCI Express registers.
5.1.32
PEG_CAP—PCI Express* Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A2–A3h
0141h
RO, R/WO
16 bits
Size:
This register indicates PCI Express device capabilities.
Bit
Access &
Default
Description
15:14
13:9
Reserved
RO
Interrupt Message Number: Hardwired to 0. Not Applicable or Implemented.
00h
8
R/WO
1b
Slot Implemented:
0 = The PCI Express* Link associated with this port is connected to an integrated
component or is disabled.
1 = The PCI Express Link associated with this port is connected to a slot.
BIOS must initialize this field appropriately if a slot connection is not implemented.
7:4
3:0
RO
4h
Device/Port Type: Hardwired to 4h to indicate root port of PCI Express Root
Complex.
RO
1h
PCI Express Capability Version: Hardwired to 1h as it is the first version.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.33
DCAP—Device Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A4–A7h
00000000h
RO
Size:
32 bits
This register indicates PCI Express link capabilities.
Bit
Access &
Default
Description
31:6
5
Reserved
RO
0b
Extended Tag Field Supported: Hardwired to indicate support for 5-bit tags as a
requestor.
4:3
2:0
RO
00b
Phantom Functions Supported: Hardwired to 0. Not Applicable or Implemented.
RO
Max Payload Size: Hardwired to indicate 128 Byte maximum supported payload
000b
for Transaction Layer Packets (TLP).
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135
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.34
DCTL—Device Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A8–A9h
0000h
R/W
Size:
16 bits
This register provides control for PCI Express device specific capabilities.
Note: The error reporting enable bits are in reference to errors detected by this device, not error
messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by the Root
Port Command register.
Bit
Access &
Default
Description
15:8
7:5
Reserved
R/W
Max Payload Size:
000b
000 =128B maximum supported payload for Transaction Layer Packets (TLP).
As a receiver, the Device must handle TLPs as large as the set value. As
a transmitter, the Device must not generate TLPs exceeding the set
value.
001–111 = Reserved.
4
3
Reserved
R/W
0b
Unsupported Request Reporting Enable:
0 = Disable.
1 = Enable. Unsupported requests will be reported.
NOTE: Reporting of error messages received by Root Port is controlled
exclusively by Root Control register.
2
1
R/W
0b
Fatal Error Reporting Enable:
0 = Disable.
1 = Enable. Fatal errors will be reported. For a Root Port, the reporting of fatal
errors is internal to the root. No external ERR_FATAL message is
generated.
R/W
0b
Non-Fatal Error Reporting Enable:
0 = Disable.
1 = Enable. Non-fatal errors will be reported. For a Root Port, the reporting of
non-fatal errors is internal to the root. No external ERR_NONFATAL
message is generated. Uncorrectable errors can result in degraded
performance.
0
R/W
0b
Correctable Error Reporting Enable:
0 = Disable.
1 = Enable. Correctable errors will be reported. For a Root Port, the reporting of
correctable errors is internal to the root. No external ERR_CORR message
is generated.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.35
DSTS—Device Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
AAh
0000h
RO
Size:
16 bits
This register reflects the status corresponding to controls in the Device Control register.
Note: The error reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
Bit
Access &
Default
Description
15:6
5
Reserved
RO
0b
Transactions Pending:
0 = All pending transactions (including completions for any outstanding non-
posted requests on any used virtual channel) have been completed.
1 = Device has transaction(s) pending (including completions for any outstanding
non-posted requests for all used traffic classes).
4
3
Reserved
R/WC
0b
Unsupported Request Detected:
0 = Unsupported Request Not detected.
1 = Device received an Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
2
1
0
R/WC
0b
Fatal Error Detected: When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the Correctable Error Mask
register.
0 = Fatal Error Not detected.
1 = Fatal error(s) detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device Control register.
R/WC
0b
Non-Fatal Error Detected: When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the Correctable Error Mask
register.
0 = Non-fatal error Not detected.
1 = Non-fatal error(s) detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device Control register.
R/WC
0b
Correctable Error Detected: When Advanced Error Handling is enabled, errors
are logged in this register regardless of the settings of the Correctable Error Mask
register.
0 = Correctable error Not detected.
1 = Correctable error(s) detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device Control register.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.36
LCAP—Link Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
AC–AF
02014D01h
R/WO, RO
16 bits
Size:
This register indicates PCI Express device specific capabilities.
Bit
Access &
Default
Description
31:24
RO
Port Number: This field indicates the PCI Express* port number for the given PCI
02h
Express link. It matches the value in Element Self Description [31:24].
23:15
14:12
Reserved
R/WO
100b
L0s Exit Latency: This field indicates the length of time this port requires to
complete the transition from L0s to L0. The value 100b indicates the range of
256 ns to less than 512 ns. If this field is required to be any value other than the
default, BIOS must initialize it accordingly.
11:10
RO
Active State Link PM Support: L0s and L1 entry supported.
11b
NOTE: L1 state is Not supported on the 82945G/82945GC/82945GZ GMCH and
82945P/82945PL MCH.
9:4
3:0
RO
10h
Max Link Width: Hardwired to indicate X16. When Force X1 mode is enabled on
this PCI Express device, this field reflects X1 (01h).
RO
1h
Max Link Speed: Hardwired to indicate 2.5 Gb/s.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.37
LCTL—Link Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B0–B1
0000h
RO, R/W
16 bits
Size:
This register allows control of the PCI Express link.
Bit
Access &
Default
Description
15:8
7
Reserved
R/W
0h
Reserved. Must be 0 when writing this register.
6
R/W
0b
Common Clock Configuration: Components use this common clock
configuration information to report the correct L0s exit latency.
The state of this bit affects the L0s exit latency reported in LCAP [14:12] and the
N_FTS value advertised during link training.
0 = This component and the component at the opposite end of this Link are
operating with asynchronous reference clock.
1 = This component and the component at the opposite end of this Link are
operating with a distributed common reference clock.
5
4
R/W
0b
Retrain Link: This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
0 = Normal operation
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0
or L0s states to the recovery state.
R/W
0b
Link Disable: The link retraining happens automatically on a 0-to-1 transition, just
like when coming out of reset. Writes to this bit are immediately reflected in the
value read from the bit, regardless of actual Link state.
0 = Enable. Normal operation
1 = Link is disabled. This forces the LTSSM to transition to the disabled state (via
Recovery) from L0 or L0s states.
3
RO
0b
Read Completion Boundary (RCB) : Hardwired to 0 to indicate 64 byte.
2
Reserved
1:0
R/W
00b
Active State PM: This field controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s Entry Supported
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
139
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.38
LSTS—Link Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B2–B3h
1001h
RO
Size:
16 bits
This register indicates PCI Express link status.
Bit
Access &
Default
Description
15:13
12
Reserved
RO
1b
Slot Clock Configuration:
0 = The device uses an independent clock irrespective of the presence of a
reference on the connector.
1 = The device uses the same physical reference clock that the platform provides
on the connector.
11
10
RO
0b
Link Training: Hardware clears this bit once link training is complete.
0 = Link training Not in progress.
1 = Link training is in progress.
RO
0b
Training Error:
0 = No training error
1 = Set by hardware upon detection of unsuccessful training of the link to the L0
Link state.
9:4
RO
Negotiated Width: This field indicates negotiated link width.
00h
00h = Reserved
01h = X1
04h = Reserved
08h = Reserved
10h = X16
All other encodings are reserved.
Negotiated Speed: This field indicates negotiated link speed.
1h = 2.5 Gb/s
3:0
RO
1h
All other encodings are reserved.
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.39
SLOTCAP—Slot Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B4–B7h
00000000h
R/WO
32 bits
Size:
PCI Express slot-related registers allow for the support of Hot-Plug.
Bit
Access &
Default
Description
31:19
R/WO
0000h
Physical Slot Number: This field indicates the physical slot number attached to
this port. This field must be initialized by BIOS to a value that assigns a slot
number that is globally unique within the chassis.
18:17
16:15
Reserved
R/WO
00b
Slot Power Limit Scale: This field specifies the scale used for the Slot Power
Limit value. If this field is written, the link sends a Set_Slot_Power_Limit
message.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
14:7
R/WO
00h
Slot Power Limit Value: This field, in combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by the slot. Power limit
(in watts) is calculated by multiplying the value in this field by the value in the Slot
Power Limit Scale field. If this field is written, the link sends a
Set_Slot_Power_Limit message.
6
5
4
3
R/WO
0b
Hot-plug Capable: This bit indicates that this slot is capable of supporting hot-
plug operations.
0 = Not capable
1 =Capable.
R/WO
0b
Hot-plug Surprise: This bit indicates that a device present in this slot might be
removed from the system without any prior notification.
0 = No hot-plug surprise
1 = Hot plug Surprise capable.
R/WO
0b
Power Indicator Present: This bit indicates that a power indicator is
implemented on the chassis for this slot.
0 = Not present
1 = Present
R/WO
0b
Attention Indicator Present: This bit indicates that an Attention Indicator is
implemented on the chassis for this slot.
0 = Not present
1 = Present
2:1
0
Reserved
R/WO
0b
Attention Button Present: This bit indicates that an attention button is
implemented on the chassis for this slot. The attention button allows the user to
request hot-plug operations.
0 = Not present
1 = Present
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.40
SLOTCTL—Slot Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B8h
01C0h
R/W
16 bits
Size:
PCI Express slot related registers allow for the support of hot-plug.
Bit
Access &
Default
Description
15:10
9:8
Reserved
R/W
01b
Power Indicator Control: Reads to this field return the current state of the
power indicator. Writes to this field set the power indicator and cause the port to
send the appropriate POWER_INDICATOR_* messages.
00 = Reserved
01 = On
10 = Blink
11 = Off
7:6
R/W
11 b
Attention Indicator Control: Reads to this field return the current state of the
attention indicator. Writes to this field set the attention indicator and cause the
port to send the appropriate ATTENTION_INDICATOR_* messages.
00 = Reserved
01 = On
10 = Blink
11 = Off
5
4
R/W
0b
Hot plug Interrupt Enable:
0 =Disable.
1 = Enables generation of hot plug interrupt on enabled hot plug events.
Command Completed Interrupt Enable:
0 = Disable.
R/W
0b
1 = Enables the generation of a hot-plug interrupt when the hot-plug controller
completes a command.
3
R/W
0b
Presence Detect Changed Enable:
0 = Disable.
1 = Enables the generation of a hot-plug interrupt or wake message on a
presence detect changed event.
2:1
0
Reserved
R/W
0b
Attention Button Pressed Enable:
0 = Disable.
1 = Enables the generation of hot-plug interrupt or wake message on an
attention button pressed event.
142
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.41
SLOTSTS—Slot Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
BA–BBh
0000h
RO, R/WC
16 bits
Size:
PCI Express slot-related registers allow for the support of hot-plug.
Bit
Access &
Default
Description
15:7
6
Reserved
RO
Strap
Presence Detect State: This bit indicates the presence of a card in the slot.
0 = Slot Empty
1 = Card Present in slot.
5
4
Reserved
R/WC
0b
Command Completed:
0 = Command Not completed.
1 = Hot-plug controller completes an issued command.
Presence Detect Changed:
3
R/WC
0b
0 =No Presence Detect change.
1 = Presence detect change is detected. This corresponds to an edge on the
signal that corresponds to bit 6 of this register (Presence Detect State).
2:1
0
Reserved
R/WC
0b
Attention Button Pressed:
0 = Attention button Not pressed.
1 = Attention button is pressed.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
143
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.42
RCTL—Root Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
BCh
0000h
R/W
16 bits
Size:
This register allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when the device
detects an error (reported in this device’s Device Status register) or when an error message is
received across the link. Reporting of SERR, as controlled by these bits, takes precedence over
the SERR Enable in the PCI Command register.
Bit
Access &
Default
Description
15:4
3
Reserved
R/W
0b
PME Interrupt Enable:
0 = Disable. No interrupts are generated as a result of receiving PME
messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit of the Root Status register. A PME interrupt is also
generated if the PME Status bit of the Root Status register is set when this
bit is set from a cleared state.
2
1
0
R/W
0b
System Error on Fatal Error Enable: This bit controls the root complex’s
response to fatal errors.
0 = Disable. No SERR generated on receipt of fatal error.
1 = SERR is generated if a fatal error is reported by any of the devices in the
hierarchy associated with this root port, or by the Root Port itself.
R/W
0b
System Error on Non-Fatal Uncorrectable Error Enable: This bit controls the
Root Complex’s response to non-fatal errors.
0 = Disable. No SERR generated on receipt of non-fatal error.
1 = SERR is generated if a non-fatal error is reported by any of the devices in
the hierarchy associated with this Root Port, or by the Root Port itself.
R/W
0b
System Error on Correctable Error Enable: This bit controls the Root
Complex’s response to correctable errors.
0 = Disable. No SERR generated on receipt of correctable error.
1 = SERR is generated if a correctable error is reported by any of the devices in
the hierarchy associated with this Root Port, or by the Root Port itself.
144
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.43
RSTS—Root Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
C0–C3h
00000000h
RO, R/WC
32 bits
Size:
This register provides information about PCI Express Root Complex specific parameters.
Bit
Access &
Default
Description
31:18
17
Reserved
RO
0b
PME Pending:
0 = PME Not pending.
1 = Another PME is pending when the PME Status bit is set. When the PME
Status bit is cleared by software; the PME is delivered by hardware by
setting the PME Status bit again and updating the Requestor ID
appropriately. The PME pending bit is cleared by hardware if no more
PMEs are pending.
16
R/WC
0b
PME Status:
0 = Requestor ID did Not assert PME.
1 = Requestor ID indicated in the PME Requestor ID field asserted PME.
Subsequent PMEs are kept pending until the status register is cleared by
writing a 1 to this field.
15:0
RO
PME Requestor ID: This field indicates the PCI requestor ID of the last PME
0000h
requestor.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
145
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.44
PEG_LC—PCI Express* Legacy Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
EC–EFh
00000000h
R/W
Size:
32 bits
This register controls functionality that is needed by legacy (non-PCI Express aware) operating
systems during run time.
Bit
Access &
Default
Description
31:3
2
Reserved
R/W
0b
PME GPE Enable (PMEGPE):
0 = Disable. Do Not generate GPE PME message when PME is received.
1 = Enable. Generate a GPE PME message when PME is received
(Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This enables
the (G)MCH to support PMEs on the PCI Express* port under legacy
operating systems.
1
R/W
0b
Hot-Plug GPE Enable (HPGPE):
0 = Disable. Do Not generate GPE hot-plug message when a hot-plug event is
received.
1 = Enable. Generate a GPE hot-plug message when a hot-plug event is received
(Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the
(G)MCH to support Hot-Plug on the PCI Express port under legacy operating
systems.
0
R/W
0b
General Message GPE Enable (GENGPE):
0 = Disable. Do Not forward received GPE assert/de-assert messages.
1 = Enable. Forward received GPE assert/de-assert messages. These general
GPE message can be received via the PCI Express port from an external
Intel device and will be subsequently forwarded to the Intel® ICH7 (via
Assert_GPE and Deassert_GPE messages on DMI).
146
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.45
VCECH—Virtual Channel Enhanced Capability Header
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
100–103h
14010002h
RO
Size:
32 bits
This register indicates PCI Express device Virtual Channel capabilities.
Note: Extended capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability structures.
Bit
Access &
Default
Description
31:20
19:16
15:0
RO
140h
Pointer to Next Capability: The Link Declaration Capability is the next in the PCI
Express* extended capabilities list.
RO
1h
PCI Express Virtual Channel Capability Version: Hardwired to 1 to indicate
compliances with the PCI Express specification, Revsion 1.0a.
RO
Extended Capability ID: A value of 0002h identifies this linked list item
0002h
(capability structure) as being for PCI Express Virtual Channel registers.
5.1.46
PVCCAP1—Port VC Capability Register 1 (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
104h
00000001h
RO, R/WO
32 bits
Size:
This register describes the configuration of PCI Express Virtual Channels associated with this
port.
Bit
Access &
Default
Description
31:7
6:4
Reserved
RO
000b
Low Priority Extended VC Count: This field indicates the number of (extended)
Virtual Channels in addition to the default VC belonging to the low-priority VC
(LPVC) group that has the lowest priority with respect to other VC resources in a
strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
3
2:0
R/WO
001b
Extended VC Count: This field indicates the number of (extended) Virtual
Channels in addition to the default VC supported by the device.
BIOS Requirement: Set this field to 000b for all configurations.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.47
PVCCAP2—Port VC Capability Register 2 (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
108–10Bh
00000001h
RO
Size:
32 bits
This register describes the configuration of PCI Express Virtual Channels associated with this
port.
Bit
Access &
Default
Description
31:24
RO
00h
VC Arbitration Table Offset: This field indicates the location of the VC arbitration
table. This field contains the zero-based offset of the table in DQWords (16 bytes)
from the base address of the Virtual Channel capability structure. A value of 0
indicates that the table is not present (due to fixed VC priority).
23:8
7:0
Reserved
RO
VC Arbitration Capability: This field indicates that the only possible VC
01h
arbitration scheme is hardware fixed (in the root complex).
VC1 is the highest priority, VC0 is the lowest priority.
5.1.48
PVCCTL—Port VC Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
10C–10Dh
0000h
R/W
Size:
16 bits
Bit
Access &
Default
Description
15:4
3:1
Reserved
R/W
000b
VC Arbitration Select: This field is programmed by software to the only possible
value as indicated in the VC Arbitration Capability field. The value 001b, when
written to this field, indicates the VC arbitration scheme is hardware fixed (in the
root complex).
This field can not be modified when more than one VC in the LPVC group is
enabled.
0
Reserved
148
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.49
VC0RCAP—VC0 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
110–113h
00000000h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15
Reserved
Reject Snoop Transactions
RO
0b
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
14:0
Reserved
5.1.50
VC0RCTL—VC0 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
114–117h
800000FFh
RO, R/W
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
VC0 Enable: For VC0, this bit is hardwired to 1 and read only as VC0 can never
be disabled.
30:27
26:24
Reserved
RO
VC0 ID: This field assigns a VC ID to the VC resource. For VC0, this is hardwired
000b
to 0 and read only.
23:8
7:1
Reserved
R/W
7Fh
TC/VC0 Map: This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. To remove one or more TCs from the TC/VC map of an enabled
VC, software must ensure that no new or outstanding transactions with the TC
labels are targeted at the given Link.
0
RO
1b
TC0/VC0 Map: Traffic Class 0 is always routed to VC0.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.51
VC0RSTS—VC0 Resource Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
11A–11Bh
0002h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
1b
VC0 Negotiation Pending: This bit indicates the status of the process of Flow
Control initialization. It is set by default on reset, as well as when the
corresponding Virtual Channel is disabled or the Link is in the DL_Down state. It is
cleared when the link successfully exits the FC_INIT2 state.
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both components on a Link.
0
Reserved
5.1.52
VC1RCAP—VC1 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
11C–11Fh
00008000h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15
Reserved
Reject Snoop Transactions:
RO
1b
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
14:0
Reserved
150
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.53
VC1RCTL—VC1 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
120–123h
01000000h
RO, R/W
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 1.
Bit
Access &
Default
Description
31
R/W
0b
VC1 Enable: Software must use the VC Negotiation Pending bit to check whether
the VC negotiation is complete. When VC Negotiation Pending bit is cleared, a 1
read from this VC Enable bit indicates that the VC is enabled (Flow Control
Initialization is completed for the PCI Express* port); a 0 read from this bit
indicates that the Virtual Channel is currently disabled.
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. See exceptions in following notes.
NOTES:
1.
2.
3.
4.
To enable a Virtual Channel, the VC Enable bits for that Virtual
Channel must be set in both components on a Link.
To disable a Virtual Channel, the VC Enable bits for that Virtual
Channel must be cleared in both components on a Link.
Software must ensure that no traffic is using a Virtual Channel at the
time it is disabled.
Software must fully disable a Virtual Channel in both components on a
Link before re-enabling the Virtual Channel.
BIOS Requirement: This field must not be set to 1b.
30:27
26:24
Reserved
R/W
VC1 ID: This field assigns a VC ID to the VC resource. The assigned value must
001b
be non-zero. This field cannot be modified when the VC is already enabled.
23:8
7:1
Reserved
R/W
00h
TC/VC1 Map: This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. To remove one or more TCs from the TC/VC map of an enabled
VC, software must ensure that no new or outstanding transactions with the TC
labels are targeted at the given Link.
0
RO
0b
TC0/VC1 Map: Traffic Class 0 is always routed to VC0.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.54
VC1RSTS—VC1 Resource Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
126–127h
0002h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
1 b
VC1 Negotiation Pending: This bit indicates the status of the process of Flow
Control initialization. It is set by default on reset, as well as when the
corresponding Virtual Channel is disabled or the Link is in the DL_Down state. It is
cleared when the link successfully exits the FC_INIT2 state.
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
Reserved
5.1.55
RCLDECH—Root Complex Link Declaration Enhanced
Capability Header (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
140–143h
00010005h
RO
Size:
32 bits
This capability declares links from this element (PCI Express) to other elements of the root
complex component to which it belongs. See the PCI Express specification for link/topology
declaration requirements.
Bit
Access &
Default
Description
31:20
19:16
15:0
RO
000h
Pointer to Next Capability: This is the last capability in the PCI Express*
extended capabilities list.
RO
1h
Link Declaration Capability Version: Hardwired to 1 to indicate compliances
with PCI Express Specification, Revision 1.0a.
RO
Extended Capability ID: The value of 0005h identifies this linked list item
0005h
(capability structure) as being for PCI Express Link Declaration Capability.
Note: See corresponding Egress Port Link Declaration Capability registers for diagram of Link
Declaration Topology.
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Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.56
ESD—Element Self Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
144–147h
02000100h
RO, R/WO
32 bits
Size:
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access &
Default
Description
31:24
RO
02h
Port Number: This field specifies the port number associated with this element
with respect to the component that contains this element. The egress port of the
component to provide arbitration to this Root Complex Element uses this port
number value.
23:16
15:8
R/WO
00h
Component ID: This field identifies the physical component that contains this
Root Complex Element. Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
RO
01h
Number of Link Entries: This field identifies the number of link entries following
the Element Self Description. This field reports 1 (to Egress port only as no peer-
to-peer capabilities are reported in this topology).
7:4
3:0
Reserved
RO
0h
Element Type: This field identifies the type of the Root Complex Element.
Value of 0h represents a root port.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.57
LE1D—Link Entry 1 Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
150–153h
00000000h
RO, R/WO
32 bits
Size:
This register contains the first part of a Link Entry, which declares an internal link to another
Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
00h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
23:16
R/WO
00h
Target Component ID: This field identifies the physical or logical component that
is targeted by this link entry.
15:2
1
Reserved
RO
0b
Link Type: This bit identifies that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
0
R/WO
0b
Link Valid:
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
5.1.58
LE1A—Link Entry 1 Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
158158–15Fh
0000000000000000h
R/WO
Size:
64 bits
This register contains the second part of a Link Entry that declares an internal link to another Root
Complex element.
Bit
Access &
Default
Description
63:32
31:12
Reserved
R/WO
Link Address: This field contains the memory-mapped base address of the
0 0000h
RCRB that is the target element (Egress Port) for this link entry.
11:0
Reserved
154
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.59
UESTS—Uncorrectable Error Status (D1:F0)
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
1C4–1C7h
00000000h
RO, R/WC/S
32 bits
Size:
This register reports error status of individual error sources on a PCI Express device. An
individual error status bit that is set indicates that a particular error occurred.
Note: Software clears an error status by writing a 1 to the respective bit.
Bit
Access
& Default
Description
31:2
1
Reserved
20
R/WC/S
0b
Unsupported Request Error Status:
0 = Error did Not occur
1 = Error occurred
19
18
Reserved
R/WC/S
0b
Malformed TLP Status:
0 = Error did Not occur
1 = Error occurred
17
16
R/WC/S
0b
Receiver Overflow Status:
0 = Error did Not occur
1 = Error occurred
R/WC/S
0b
Unexpected Completion Status:
0 = Error did Not occur
1 = Error occurred
15
14
Reserved
R/WC/S
0b
Completion Timeout Status:
0 = Error did Not occur
1 = Error occurred
13:5
4
Reserved
R/WC/S
0b
Data Link Protocol Error Status (DLPES): The Data Link Layer Protocol Error that
causes this bit to be set will also cause the Fatal Error Detected bit (bit 2) in the
DSTS (Device Status, D1:F0) to be set if not already set.
0 = Error did Not occur
1 = Error occurred
3:0
Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
155
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.60
UEMSK—Uncorrectable Error Mask (D1:F0)
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
1C8–1CBh
00000000h
RO, R/W/S
32 bits
Size:
This register controls reporting of individual errors by the device (or logic associated with this
port) to the PCI Express Root Complex. As these errors are not originating on the other side of a
PCI Express link, no PCI Express error message is sent, but the unmasked error is reported
directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has
no action taken. There is a mask bit per error bit of the Uncorrectable Error Status register.
Bit
Access
& Default
Description
31:21
20
Reserved
R/W/S
0b
Unsupported Request Error Mask:
0 = Not masked
1 = Masked
19
18
Reserved
R/W/S
0b
Malformed TLP Mask:
0 = Not masked
1 = Masked
17
16
R/W/S
0b
Receiver Overflow Mask:
0 = Not masked
1 = Masked
R/W/S
0b
Unexpected Completion Mask:
0 = Not masked
1 = Masked
15
14
Reserved
R/W/S
0b
Completion Timeout Mask:
0 = Not masked
1 = Masked
13:5
4
Reserved
R/W/S
0b
Data Link Protocol Error Mask
0 = Not masked
1 = Masked
3:0
Reserved
156
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.61
CESTS—Correctable Error Status (D1:F0)
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
1D0–1D3h
00000000h
RO,R/WC/S
32 bits
Size:
This register reports error status of individual error sources on a PCI Express device. An
individual error status bit that is set indicates that a particular error occurred.
Note: Software clears an error status by writing a 1 to the respective bit.
Bit
Access
& Default
Description
31:1
3
Reserved
12
R/WC/S
0b
Replay Timer Timeout Status:
0 = Error did Not occur
1 = Error occurred
11:9
8
Reserved
R/WC/S
0b
Replay Number Rollover Status:
0 = Error did Not occur
1 = Error occurred
7
6
R/WC/S
0b
Bad DLLP Status:
0 = Error did Not occur
1 = Error occurred
R/WC/S
0b
Bad TLP Status:
0 = Error did Not occur
1 = Error occurred
5:1
0
Reserved
R/WC/S
0b
Receiver Error Status (RES): Receiver errors will be indicated due to all of the
following: 8b/10b Decode Errors, Framing Errors, Lane Deskew Errors, and Elasticity
Buffer Overflow/Underflow.
0 = Error did Not occur
1 = Error occurred
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
157
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.62
CEMSK—Correctable Error Mask (D1:F0)
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
1D4–1D7h
00000000h
RO, R/W/S
32 bits
Size:
This register controls reporting of individual correctable errors by the device (or logic associated
with this port) to the PCI Express Root Complex. As these errors are not originating on the other
side of a PCI Express link, no PCI Express error message is sent; however, the unmasked error is
reported directly to the root control logic. A masked error (respective bit set to 1 in the mask
register) has no action taken. There is a mask bit per error bit of the Correctable Error Status
register.
Bit
Access &
Default
Description
31:13
12
Reserved
R/W/S
0b
Replay Timer Timeout Mask:
0 = Not masked
1 = Masked
11:9
8
Reserved
R/W/S
0b
Replay Number Rollover Mask:
0 = Not masked
1 = Masked
7
6
R/W/S
0b
Bad DLLP Mask:
0 = Not masked
1 = Masked
R/W/S
0b
Bad TLP Mask:
0 = Not masked
1 = Masked
5:1
0
Reserved
R/W/S
0b
Receiver Error Mask:
0 = Not masked
1 = Masked
158
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.63
PEG_SSTS—PCI Express* Sequence Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
218–21Fh
0000000000000FFFh
RO
Size:
64 bits
This register provides PCI Express status reporting that is required by the PCI Express
specification.
Bit
Access &
Default
Description
63:60
59:48
Reserved
RO
000h
Next Transmit Sequence Number: This field contains the value of the
NXT_TRANS_SEQ counter. This counter represents the transmit Sequence
number to be applied to the next TLP to be transmitted onto the Link for the first
time.
47:44
43:32
Reserved
RO
000h
Next Packet Sequence Number: This field contains the packet sequence
number to be applied to the next TLP to be transmitted or re-transmitted onto the
Link.
31:28
27:16
Reserved
RO
Next Receive Sequence Number: This field contains the sequence number
000h
associated with the TLP that is expected to be received next.
15:12
11:0
Reserved
RO
Last Acknowledged Sequence Number: This field contains the sequence
FFFh
number associated with the last acknowledged TLP.
§
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
159
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
160
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Direct Media Interface (DMI) RCRB
6 Direct Media Interface (DMI) RCRB
This Root Complex Register Block (RCRB) controls the (G)MCH-ICH7 serial interconnect. The
base address of this space is programmed in DMIBAR in D0:F0 configuration space. Table 6-1
provides an address map of the DMI registers listed by address offset in ascending order.
Section 6.1 provides a detailed bit description of the registers.
Note: All RCRB register spaces need to remain organized as they are here.
Table 6-1. DMI Register Address Map
Offset
Address
Register
Symbol
Register Name
PCI Dev #
000–003h
004–007h
008–00Bh
00C–00Dh
00E–00Fh
010–013h
014–017h
018–019h
01A–01Bh
01C–01Fh
020–023h
024–025h
026–027h
028–083h
DMIVCECH
DMIPVCCAP1
DMIPVCCAP2
DMIPVCCTL
—
DMI Virtual Channel Enhanced Capability Header
DMI Port VC Capability Register 1
DMI Port VC Capability Register 2
DMI Port VC Control
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
Reserved
DMIVC0RCAP
DMIVC0RCTL
—
DMI VC0 Resource Capability
DMI VC0 Resource Control
Reserved
DMIVC0RSTS
DMIVC1RCAP
DMIVC1RCTL
—
DMI VC0 Resource Status
DMI VC1 Resource Capability
DMI VC1 Resource Control
Reserved
DMIVC1RSTS
—
DMI VC1 Resource Status
Reserved
084–087h
088–089h
08A–08Bh
1C4–1C7h
DMILCAP
DMILCTL
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMI Link Capabilities
DMI Link Control
DMILSTS
DMI Link Status
DMIUESTS
DMIUEMSK
DMI Uncorrectable Error Status
DMI Uncorrectable Error Mask
1C8–
1CBh
1D0–1D3h
08C–1FFh
DMICESTS
—
DMIBAR
DMIBAR
DMI Correctable Error Status
Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
161
Direct Media Interface (DMI) RCRB
6.1
DMI RCRB Configuration Register Details
6.1.1
DMIVCECH—DMI Virtual Channel Enhanced Capability
Header
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
000–003h
04010002h
RO
Size:
32 bits
This register indicates DMI Virtual Channel capabilities.
Bit
Access &
Default
Description
31:20
19:16
15:0
RO
040h
Pointer to Next Capability: This field indicates the next item in the list.
RO
1h
Capability Version: This field indicates support as a version 1 capability
structure.
RO
Capability ID: This field indicates this is the Virtual Channel capability item.
0002h
6.1.2
DMIPVCCAP1—DMI Port VC Capability Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
004–007h
00000001h
RO, R/WO
32 bits
Size:
This register describes the configuration of Virtual Channels associated with this port.
Bit
Access &
Default
Description
31:12
11:10
Reserved
RO
Port Arbitration Table Entry Size (PATS): This field indicates the size of the
00b
port arbitration table is 4 bits (to allow up to 8 ports).
9:8
RO
Reference Clock (RC): This field is hardwired for a clock of 10 ns.
00b
7
Reserved
6:4
RO
Low Priority Extended VC Count (LPEVC): This field indicates that there are
000b
no additional VCs of low priority with extended capabilities.
3
Reserved
2:0
R/WO
001b
Extended VC Count: This field indicates that there is one additional VC (VC1)
that exists with extended capabilities.
162
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Direct Media Interface (DMI) RCRB
6.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
008–00Bh
00000001h
RO
Size:
32 bits
This register describes the configuration of Virtual Channels associated with this port.
Bit
Access &
Default
Description
31:24
RO
VC Arbitration Table Offset (ATO): This field indicates that no table is present
00h
for VC arbitration since it is fixed.
23:8
7:0
Reserved
RO
VC Arbitration Capability: This field indicates that the VC arbitration is fixed in
01h
the root complex. VC1 is highest priority and VC0 is lowest priority.
6.1.4
DMIPVCCTL—DMI Port VC Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
00C–00Dh
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15:4
3:1
Reserved
R/W
000b
VC Arbitration Select: This field indicates which VC should be programmed in
the VC arbitration table. The root complex takes no action on the setting of this
field since there is no arbitration table.
0
Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
163
Direct Media Interface (DMI) RCRB
6.1.5
DMIVC0RCAP—DMI VC0 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
010–013h
00000001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:23
22:16
Reserved
RO
Maximum Time Slots (MTS): This VC implements fixed arbitration; therefore, this
00h
field is not used.
15
RO
0b
Reject Snoop Transactions (RTS): This VC must be able to take snoopable
transactions.
14:8
7:0
Reserved
RO
Port Arbitration Capability (PAC): This field indicates that this VC uses fixed
01h
port arbitration.
164
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Direct Media Interface (DMI) RCRB
6.1.6
DMIVC0RCTL—DMI VC0 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
014–017h
800000FEh
RO, R/W
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
Virtual Channel Enable (EN):
0 = Disable
1 = Enable.
30:27
26:24
Reserved
RO
Virtual Channel Identifier (ID): This field indicates the ID to use for this virtual
000b
channel.
23:20
19:17
Reserved
R/W
0h
Port Arbitration Select (PAS): This field indicates which port table is being
programmed. The root complex takes no action on this setting since the
arbitration is fixed and there is no arbitration table.
16:8
7:1
Reserved
R/W
7Fh
Transaction Class / Virtual Channel Map (TVM): This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel. For example when bit 7 is set
in this field, Transaction Class 7 is mapped to this Virtual channel resource. When
more than one bit in this field is set, it indicates that multiple Transaction Classes
from the Transcation Class/Virtual Channel map of an enabled Virtual Channel,
software must ensure that no new or outstanding transactions with the
Transaction Class labels are targeted at the given Link.
0
Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
165
Direct Media Interface (DMI) RCRB
6.1.7
DMIVC0RSTS—DMI VC0 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
01A–01Bh
0002h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
VC Negotiation Pending (NP):
RO
1 b
0 = The Virtual Channel negotiation is complete.
1 =The Virtual Channel resource is still in the process of negotiation (initialization
or disabling).
NOTE: Before using a Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are cleared in both
components on a link.
0
Reserved
6.1.8
DMIVC1RCAP—DMI VC1 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
01C–01Fh
00008001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15
Reserved
Reject Snoop Transactions (RTS):
RO
1b
0 =Transactions with or without the no snoop bit set within the TLP header are
allowed on this VC.
1 =Any transaction without the no Snoop bit set within the TLP header will be
rejected as an unsupported request.
14:8
7:0
Reserved
RO
Port Arbitration Capability (PAC): This field indicates the port arbitration
01h
capability is time-based WRR of 128 phases.
166
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Direct Media Interface (DMI) RCRB
6.1.9
DMIVC1RCTL—DMI VC1 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
020–023h
01000000h
R/W
Size:
32 bits
This register controls the resources associated with Virtual Channel 1.
Bit
Access &
Default
Description
31
R/W
0b
Virtual Channel 1 Enable (VC1E):
0 = Disable
1 = Enable
30:27
26:24
Reserved
R/W
001b
Virtual Channel 1 Identifier (VC1ID): This field indicates the ID to use for this
virtual channel. Assigned value must be non-zero. This field can not be modified
when the VC is already enabled.
23:20
19:17
Reserved
R/W
0h
Port Arbitration Select (PAS): This field indicates which port table is being
programmed. The only permissible value of this field is 4h for the time-based
WRR entries.
16:8
7:1
Reserved
R/W
00h
Transaction Class / Virtual Channel Map (TVM): This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
0
Reserved
6.1.10
DMIVC1RSTS—DMI VC1 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
026–027h
0002h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
0b
VC Negotiation Pending (NP):
0 = VC negotiation Not pending
1 = Virtual channel is still being negotiated with ingress ports.
0
Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
167
Direct Media Interface (DMI) RCRB
6.1.11
DMILCAP—DMI Link Capabilities
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
084–087h
00012C41h
RO, R/WO
32 bits
Size:
This register indicates DMI specific capabilities.
Bit
Access &
Default
Description
31:18
17:15
Reserved
R/WO
010b
L1 Exit Latency (EL1): L1 is not supported on DMI.
14:12
11:10
9:4
R/WO
010b
L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less than
256 ns.
RO
11b
Active State Link PM Support (APMS): This field indicates that L0s is supported
on DMI.
RO
4h
Maximum Link Width (MLW): This field indicates the maximum link width is
4 ports.
3:0
RO
1h
Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s.
6.1.12
DMILCTL—DMI Link Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
088–089h
0000h
R/W
Size:
16 bits
This register allows control of DMI.
Bit
Access &
Default
Description
15:8
7
Reserved
Extended Synch (ES):
R/W
0 h
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0.
6:2
1:0
Reserved
R/W
00 b
Active State Link PM Control (APMC): This field indicates whether DMI should
enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
168
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Direct Media Interface (DMI) RCRB
6.1.13
DMILSTS—DMI Link Status
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
08A–08Bh
0001h
RO
Size:
16 bits
This register indicates DMI status.
Bit
Access &
Default
Description
15:10
9:4
Reserved
RO
Negotiated Link Width (NLW): The negotiated link width is x4 (000100b).
00h
3:0
RO
1h
Link Speed (LS): Link is 2.5 Gb/s.
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
169
Direct Media Interface (DMI) RCRB
6.1.14
DMIUESTS—DMI Uncorrectable Error Status
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/0/0/DMIBAR
1C4–1C7h
00000000h
R/WC/S
Size:
32 bits
This register reports error status of individual uncorrectable error sources on DMI. An individual
error status bit that is set indicates that a particular error occurred.
Note: Software clears an error status by writing a 1 to the respective bit.
Bit
Access
& Default
Description
31:21
20
Reserved
R/WC/S
0b
Unsupported Request Error Status:
0 = Error did Not occur
1 = Error occurred
19
18
Reserved
R/WC/S
0b
Malformed TLP Status:
0 = Error did Not occur
1 = Error occurred
17
16
R/WC/S
0b
Receiver Overflow Status:
0 = Error did Not occur
1 = Error occurred
R/WC/S
0b
Unexpected Completion Status:
0 = Error did Not occur
1 = Error occurred
15
14
Reserved
R/WC/S
0b
Completion Timeout Status:
0 = Error did Not occur
1 = Error occurred
13:5
4
Reserved
R/WC/S
0b
Data Link Protocol Error Status:
0 = Error did Not occur
1 = Error occurred
3:0
Reserved
170
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Direct Media Interface (DMI) RCRB
6.1.15
DMIUEMSK—DMI Uncorrectable Error Mask
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/0/0/DMIBAR
1C8–1CBh
00000000h
R/W/S
Size:
32 bits
This register controls reporting of individual uncorrectable errors over DMI. A masked error
(respective bit set to 1 in the mask register) has no action taken. There is a mask bit per error bit
of the DMIUESTS register.
Bit
Access
& Default
Description
31:21
20
Reserved
R/W/S
0b
Unsupported Request Error Mask:
0 = Not masked
1 = Masked
19
18
Reserved
R/W/S
0b
Malformed TLP Mask:
0 = Not masked
1 = Masked
17
16
R/W/S
0b
Receiver Overflow Mask:
0 = Not masked
1 = Masked
R/W/S
0b
Unexpected Completion Mask:
0 = Not masked
1 = Masked
15
14
Reserved
R/W/S
0b
Completion Timeout Mask:
0 = Not masked
1 = Masked
13:5
4
Reserved
R/W/S
0b
Data Link Protocol Error Mask:
0 = Not masked
1 = Masked
3:0
Reserved
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
171
Direct Media Interface (DMI) RCRB
6.1.16
DMICESTS—DMI Correctable Error Status
Bus/Dev/Func/Type:
Address Offset:
Default Value:
Access:
0/0/0/DMIBAR
1D0–1D3h
00000000h
R/WC/S
Size:
32 bits
This register reports error status of individual correctable error sources on DMI. An individual
error status bit that is set indicates that a particular error occurred.
Note: Software clears an error status by writing a 1 to the respective bit.
Bit
Access
& Default
Description
31:13
12
Reserved
R/WC/S
0b
Replay Timer Timeout Status:
0 = Error did Not occur
1 = Error occurred
11:9
8
Reserved
R/WC/S
0b
REPLAY_NUM Rollover Status:
0 = Error did Not occur
1 = Error occurred
7
6
R/WC/S
0b
Bad DLLP Status:
0 = Error did Not occur
1 = Error occurred
R/WC/S
0b
Bad TLP Status:
0 = Error did Not occur
1 = Error occurred
5:1
0
Reserved
R/WC/S
0b
Receiver Error Status (RES): Receiver errors will be indicated due to all of the
following: 8b/10b Decode Errors, Framing Errors, Lane Deskew Errors, and
Elasticity Buffer Overflow/Underflow.
0 = Error did Not occur
1 = Error occurred
§
172
Intel® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7 Integrated Graphics Device
(D2:F0) (Intel® 82945G/82945GC/
82945GZ GMCH Only)
The Integrated Graphics Device registers are located in Device 2 (D2), Function 0 (F0) and
Function 1 (F1). This chapter provides the descriptions for the D2:F0 registers. Table 7-1
provides an address map of the D2:F0 registers listed in ascending order by address offset.
Section 7.1 provides a detailed bit description of the registers.
Function 0 can be VGA compatible or not; this is selected through bit 1 of the GGC register
(D0:F0, offset 52h).
Note: The following sections describe Device 2 PCI configuration registers only.
Table 7-1. Integrated Graphics Device Register Address Map (D2:F0)
Address
Offset
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID2
DID2
Vendor Identification
8086h
2772h
0000h
0090h
RO
RO
Device Identification
PCI Command
PCICMD2
PCISTS2
RID2
RO, R/W
RO
PCI Status
Revision Identification
See register
description
RO
09–0Bh
0Ch
CC
CLS
Class Code
030000h
00h
RO
RO
Cache Line Size
0Dh
MLT2
HDR2
—
Master Latency Timer
Header Type
00h
RO
0Eh
80h
RO
0Fh
Reserved
—
—
10–13h
14–17h
18–1Bh
MMADR
IOBAR
GMADR
Memory Mapped Range Address
I/O Base Address
00000000h
00000001h
00000008h
RO, R/W
RO, R/W
Graphics Memory Range Address
RO,
R/W/L
1C–1Fh
GTTADR
Graphics Translation Table Range
Address
00000000h
RO, R/W
20–2Bh
2C–2Dh
2E–2Fh
—
Reserved
—
—
SVID2
SID2
Subsystem Vendor Identification
Subsystem Identification
0000h
0000h
R/WO
R/WO
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
173
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
Address
Offset
Symbol
Register Name
Default
Value
Access
30–33h
34h
ROMADR
CAPPOINT
—
Video BIOS ROM Base Address
Capabilities Pointer
Reserved
00000000h
90h
—
RO
RO
—
35–3Bh
3Ch
INTRLINE
INTRPIN
MINGNT
MAXLAT
—
Interrupt Line
01h
01h
00h
00h
—
R/W
RO
RO
RO
—
3Dh
Interrupt Pin
3Eh
Minimum Grant
3Fh
Maximum Latency
Reserved
40–43h
44h
MCAPPTR
—
Mirror of Device 0 Capability Pointer
Reserved
E0h
—
RO
—
45–47h
48–50h
MCAPID
Mirror of Device 0 Capability
Identification
0000000000
01090009h
RO
51h
—
Reserved
—
—
52–53h
MGGC
Mirror of Device 0 GMCH Graphics
Control
0030h
RO
54–57h
MDEVEN
Mirror of Device 0 Device Enable
See register
description
RO
58–5Bh
5C–5Fh
60–61h
63–CFh
D0–D1h
D2–D3h
D4–D5h
D6–D7h
E0–E1h
E2–E3h
E4–E7h
E8h–FBh
FC–FFh
—
BSM
—
Reserved
—
07800000h
0000h
—
—
RO
Base of Stolen Memory
Reserved
R/W
—
—
Reserved
PMCAPID
PMCAP
PMCS
—
Power Management Capabilities ID
Power Management Capabilities
Power Management Control/Status
Reserved
0001h
0022h
0000h
—
RO
RO
RO, R/W
—
SWSMI
—
Software SMI
0000h
—
R/W
—
Reserved
ASLE
—
System Display Event
Reserved
00000000h
—
R/W
—
ASLS
ASL Storage
00000000h
R/W
174
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1
Configuration Register Details (D2:F0)
7.1.1
VID2—Vendor Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
00h
8086h
RO
Size:
16 bits
This register, combined with the Device Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Vendor Identification Number (VID): This field provides the PCI standard
8086h
identification for Intel.
7.1.2
DID2—Device Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
02h
2772h
RO
Size:
16 bits
This register, combined with the Vendor Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID): This is a 16 bit value assigned to the GMCH
2772h
Graphic device
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.3
PCICMD2—PCI Command (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
04h
0000h
RO, R/W
16 bits
Size:
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
Access &
Default
Description
15:11
10
Reserved
R/W
0b
Interrupt Disable: This bit disables the device from asserting INTx#.
0 = Enable the assertion of this device’s INTx# signal.
1 = Disable the assertion of this device’s INTx# signal. DO_INTx messages will
not be sent to the DMI.
9
8
7
6
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0. Not Implemented.
RO
0b
SERR Enable (SERRE): Hardwired to 0. Not Implemented.
RO
0b
Address/Data Stepping Enable (ADSTEP): Hardwired to 0. Not Implemented.
RO
0b
Parity Error Enable (PERRE): Hardwired to 0. Not Implemented. Since the IGD
belongs to the category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error that it detects
and continues with normal operation.
5
4
3
2
RO
0b
Video Palette Snooping (VPS): This bit is hardwired to 0 to disable snooping.
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does
not support memory write and invalidate commands.
RO
0b
Special Cycle Enable (SCE): Hardwired to 0. The IGD ignores special cycles.
R/W
0b
Bus Master Enable (BME):
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1
0
R/W
0b
Memory Access Enable (MAE): This bit controls the IGD’s response to memory
space accesses.
0 = Disable.
1 = Enable.
R/W
0b
I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space
accesses.
0 = Disable.
1 = Enable.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.4
PCISTS2—PCI Status (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
06h
0090h
RO
Size:
16 bits
PCISTS2 reports the occurrence of a PCI compliant master abort and PCI compliant target abort.
PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Bit
15
14
13
12
11
10:9
8
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Hardwired to 0. The IGD does not detect parity.
Signaled System Error (SSE): Hardwired to 0. The IGD never asserts SERR#.
RO
0b
RO
0b
Received Master Abort Status (RMAS): Hardwired to 0. The IGD never gets a
Master Abort.
RO
0b
Received Target Abort Status (RTAS): Hardwired to 0. The IGD never gets a
Target Abort.
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use
target abort semantics.
RO
00b
DEVSEL Timing (DEVT): N/A. Hardwired to 00b.
RO
0b
Master Data Parity Error Detected (DPD): Hardwired to 0. Parity Error
Response is hardwired to disabled (and the IGD does not do any parity
detection).
7
6
5
4
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back
when the transactions are not to the same agent.
RO
0b
User Defined Format (UDF): Hardwired to 0.
RO
0b
66 MHz PCI Capable (66C): N/A. Hardwired to 0.
RO
1b
Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h
provides an offset into the function’s PCI configuration space containing a pointer
to the location of the first item in the list.
3
RO
0b
Interrupt Status: This bit reflects the state of the interrupt in the device. Only
when the Interrupt Disable bit in the Command register is a 0 and this Interrupt
Status bit is a 1, will the devices INTx# signal be asserted. Setting the Interrupt
Disable bit to a 1 has no effect on the state of this bit.
2:0
Reserved
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.5
RID2—Revision Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
08h
See bit description
RO
Size:
8 bits
This register contains the revision number for Device 2, Functions 0 and 1.
Bit
Access &
Default
Description
7:0
RO
Revision Identification Number (RID): This is an 8-bit value that indicates the
revision identification number for the GMCH. Refer to the Intel®
945G/945GC/945GZ/945P/945PL Express Chipset Specification Update for the
value of the Revision ID register.
7.1.6
CC—Class Code (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
09h
030000h
RO
Size:
24 bits
This register contains the device programming interface information related to the Sub-Class
Code and Base Class Code definition for the IGD. This register also contains the Base Class Code
and the function sub-class in relation to the Base Class Code.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This is an 8-bit value that indicates the base class
03h
code for the GMCH.
03h = Display Controller.
15:8
7:0
RO
00h
Sub-Class Code (SUBCC): The value in this field is determined based on
Device 0 GGC register, bit 1.
00h = VGA compatible
80h = Non VGA
RO
00h
Programming Interface (PI):
00h = Display controller.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.7
7.1.8
7.1.9
CLS—Cache Line Size (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Ch
00h
RO
8 bits
Size:
The IGD does not support this register as a PCI slave.
Bit
Access &
Default
Description
7:0
RO
00h
Cache Line Size (CLS): This field is hardwired to 0s. The IGD, as a PCI
compliant master, does not use the memory write and invalidate command and,
in general, does not perform operations based on cache line size.
MLT2—Master Latency Timer (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Dh
00h
RO
8 bits
Size:
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit
Access &
Default
Description
7:0
RO
Master Latency Timer Count Value: Hardwired to 0s.
00h
HDR2—Header Type (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Eh
80h
RO
8 bits
Size:
This register contains the Header Type of the IGD.
Bit
Access &
Default
Description
7
RO
1b
Multi Function Status (MFunc): This bit indicates if the device is a multi-
function device. The value of this register is determined by Device 0, offset 54h,
DEVEN[4]. If Device 0 DEVEN[4] is set, the MFunc bit is also set.
6:0
RO
00h
Header Code (H): This field is a 7-bit value that indicates the header code for
the IGD. This code has the value 00h, indicating a type 0 configuration space
format.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.10
MMADR—Memory Mapped Range Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
10h
00000000h
RO, R/W
32 bits
Size:
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
Bit
31:19
18:4
3
Access &
Default
Description
R/W
0000h
Memory Base Address: Set by the operating system, these bits correspond to
address signals 31:19.
RO
0000h
Address Mask: Hardwired to 0s to indicate 512 KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 0 to indicate memory space.
RO
0b
2:1
0
RO
00b
RO
0b
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.11
IOBAR—I/O Base Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
14h
00000001h
RO, R/W
32 bits
Size:
This register provides the base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O base to be located anywhere in 16-bit I/O address space. Bits 2:1
are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of I/O space are
decoded.
Access to the 8 Bytes of I/O space is allowed in PM state D0 when the I/O Enable bit
(PCICMD[0]) is set to 1. Access is disallowed in PM states D1–D3 or if the I/O Enable is clear or
if Device 2 is turned off. Note that access to this I/O BAR is independent of VGA functionality
within Device 2. Also, note that this mechanism is available only through function 0 of Device 2
and is not duplicated in Function 1.
If accesses to this I/O bar are allowed, the GMCH claims all 8, 16, or 32 bit I/O cycles from the
processor that fall within the 8 Bytes claimed.
Bit
Access &
Default
Description
31:16
15:3
Reserved
R/W
IO Base Address: Set by the operating system, these bits correspond to
0000h
address signals 15:3.
2:1
0
RO
00b
Memory Type: Hardwired to 0s to indicate 32-bit address.
RO
1b
Memory / IO Space: Hardwired to 1 to indicate I/O space.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.12
GMADR—Graphics Memory Range Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
18h
00000008h
RO, R/W/L
32 bits
Size:
The IGD graphics memory base address is specified in this register.
Bit
31:28
27:4
3
Access &
Default
Description
R/W
0h
Memory Base Address: Set by the OS, these bits correspond to address signals
31:28.
RO
000000h
Address Mask: Hardwired to 0s to indicate a 256-MB address range
Prefetchable Memory: Hardwired to 1 to enable prefetching
Memory Type: Hardwired to 0 to indicate 32-bit address.
Memory/IO Space: Hardwired to 0 to indicate memory space.
RO
1b
2:1
0
RO
00b
RO
0b
7.1.13
GTTADR—Graphics Translation Table Range Address
(D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
1Ch
00000000h
RO, R/W/L
32 bits
Size:
This register requests allocation for the Graphics Translation Table Range. The allocation is for
256 KB and the base address is defined by bits 31:18.
Bit
31:18
17:4
3
Access &
Default
Description
R/W
0000h
Memory Base Address (MBA): Set by the operating system, these bits
correspond to address signals 31:18.
RO
0000h
Address Mask (ADMSK): Hardwired to 0s to indicate a 256 KB address range.
Prefetchable Memory (PREFMEM): Hardwired to 0 to prevent prefetching.
Memory Type (MEMTYP): Hardwired to 0s to indicate 32-bit address.
Memory/IO Space (MIOS): Hardwired to 0 to indicate memory space.
RO
0b
2:1
0
RO
00b
RO
0b
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.14
SVID2—Subsystem Vendor Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Ch
0000h
R/WO
16 bits
Size:
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Vendor ID: This value is used to identify the vendor of the
subsystem. This register should be programmed by BIOS during boot-up. Once
written, this register becomes read only. This register can only be cleared by a
reset.
7.1.15
SID2—Subsystem Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Eh
0000h
R/WO
16 bits
Size:
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Identification: This value is used to identify a particular subsystem.
This field should be programmed by BIOS during boot-up. Once written, this
register becomes read only. This register can only be cleared by a reset.
7.1.16
ROMADR—Video BIOS ROM Base Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
30h
00000000h
RO
Size:
32 bits
The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to 0s.
Bit
Access &
Default
Description
31:18
17:11
RO
0000h
ROM Base Address: Hardwired to 0s.
RO
Address Mask: Hardwired to 0s to indicate 256-KB address range.
00h
10:1
0
Reserved
RO
0b
ROM BIOS Enable: Hardwired to 0 to indicate ROM is not accessible.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.17
CAPPOINT—Capabilities Pointer (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
34h
90h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
90h
Capabilities Pointer Value: This field contains an offset into the function’s PCI
configuration space for the first item in the New Capabilities Linked List, the MSI
Capabilities ID registers at address 90h, or the Power Management Capabilities
ID registers at address D0h.
7.1.18
INTRLINE—Interrupt Line (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Ch
01h
R/W
8 bits
Size:
Bit
Access &
Default
Description
7:0
R/W
01h
Interrupt Connection: This field is used to communicate interrupt line routing
information. POST software writes the routing information into this register as it
initializes and configures the system. The value in this register indicates which
input of the system interrupt controller that is connected to the device’s interrupt
pin.
7.1.19
INTRPIN—Interrupt Pin (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Dh
01h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Interrupt Pin: As a device that only has interrupts associated with a single
01h
function, the IGD specifies INTA# as its interrupt pin.
01h = INTA#.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.20
MINGNT—Minimum Grant (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Eh
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Minimum Grant Value: The IGD does not burst as a PCI compliant master.
00h
7.1.21
MAXLAT—Maximum Latency (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Fh
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Maximum Latency Value: The IGD has no specific requirements for how often it
00h
needs to access the PCI bus.
7.1.22
7.1.23
MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F0)
(Mirrored_D0_34)
PCI Device:
Address Offset:
Default Value:
Access:
2
44h
E0h
RO
8 bits
Size:
This register is a read only copy of Device 0, offset 34h register.
MCAPID—Mirror of Device 0 Capability Identification
(D2:F0) (Mirrored_D0_E0)
PCI Device:
Address Offset:
Default Value:
Access:
2
48h
000000000001090009h
RO
Size:
72 bits
This register is a read only copy of Device 0, offset E0h register.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.24
7.1.25
MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0)
(Mirrored_D0_52)
PCI Device:
Address Offset:
Default Value:
Access:
2
52h
0030h
RO
Size:
16 bits
This register is a read only copy of Device 0, offset 52h register.
MDEVEN—Mirror of Device 0 Device Enable (D2:F0)
(Mirrored_D0_54)
PCI Device:
2
Address Offset:
Default Value:
54h
82945G/82945GC/82945GZ GMCH: 0000001Bh
82945P/82945PL MCH: 00000003h
Access:
Size:
RO
32 bits
This register is a read only copy of Device 0, Function 0, offset 54h register.
7.1.26
BSM—Base of “Stolen” Memory (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
5Ch
07800000h
RO
Size:
32 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the
top of low used DRAM, the GMCH claims 1 to 64 MBs of DRAM for internal graphics if
enabled.
Bit
Access &
Default
Description
31:20
RO
078h
Base of Stolen Memory (BSM): This register contains bits 31:20 of the base
address of stolen DRAM memory. The host interface determines the base of
graphics stolen memory by subtracting the graphics stolen memory size from
TOLUD. See Device 0 TOLUD for more explanation.
19:0
Reserved
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.27
PMCAPID—Power Management Capabilities ID (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
D0h
0001h
RO
Size:
16 bits
Bit
15:8
7:0
Access &
Description
Default
RO
00h
NEXT_PTR: This field contains a pointer to the next item in the capabilities list.
This is the final capability in the list and must be set to 00h.
RO
CAP_ID: SIG defines this ID is 01h for power management.
01h
7.1.28
PMCAP—Power Management Capabilities (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
D2h
0022h
RO
Size:
16 bits
Bit
Access &
Default
Description
15:11
RO
00h
PME Support: This field indicates the power states in which the IGD may assert
PME#. The field is hardwired to 0s to indicate that the IGD does not assert the
PME# signal.
10
9
RO
0b
D2: Hardwired to 0 to indicate that the D2 power management state is not
supported.
RO
0b
D1: Hardwired to 0 to indicate that the D1 power management state is not
supported.
8:6
5
Reserved
RO
1b
Device Specific Initialization (DSI): Hardwired to 1 to indicate that special
initialization of the IGD is required before generic class device driver is to use it.
4
3
RO
0b
Auxiliary Power Source: Hardwired to 0.
RO
0b
PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation.
2:0
RO
010b
Version: Hardwired to 010b to indicate that there are 4 bytes of power
management registers implemented and that this device complies with the PCI
Power Management Interface Specification, Revision 1.1.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.29
PMCS—Power Management Control/Status (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
D4h
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15
RO
0b
PME_Status: This bit is 0 to indicate that the IGD does not support PME#
generation from D3 (cold).
14:9
8
Reserved
RO
0b
PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2
1:0
Reserved
R/W
00b
Power State: This field indicates the current power state of the IGD and can be
used to set the IGD into a new power state. If software attempts to write an
unsupported state to this field, the write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
7.1.30
SWSMI—Software SMI (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
E0h
0000h
R/W
16 bits
Size:
As long as there is the potential that DVO port legacy drivers exist that expect this register at this
address, D2, F0, address E0h–E1h must be reserved for this register.
Bit
Access &
Default
Description
15:8
7:1
0
R/W
00h
SW scratch bits
R/W
00h
Software Flag: This field indicates the caller and SMI function desired, as well
as return result.
R/W
0b
GMCH Software SMI Event: Software must write a 0 to clear this bit.
0 = SMI Not triggered.
1 = When set, this bit will trigger an SMI.
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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.31
ASLE—System Display Event Register (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
E4h
00000000h
R/W
Size:
32 bits
Byte, Word, or Double Word PCI configuration cycles can access this register.
Bit
Access &
Default
Description
31:24
R/W
00h
ASLE Scratch Trigger 3: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
23:16
15:8
7:0
R/W
00h
ASLE Scratch Trigger 2: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
R/W
00h
ASLE Scratch Trigger 1: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
R/W
00h
ASLE Scratch Trigger 0: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
7.1.32
ASLS—ASL Storage (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
FCh
00000000h
R/W
Size:
32 bits
This software scratch register is read/write accessible. The exact bit register usage must be
worked out in common between system BIOS and driver software, but storage for
switching/indicating up to 6 devices is possible with this amount. For each device, the ASL
control method requires two bits for _DOD (BIOS detectable yes or no, VGA/Non VGA), one bit
for _DGS (enable/disable requested), and two bits for _DCS (enabled now/disabled now,
connected or not).
Bit
Access &
Default
Description
31:0
R/W
RW according to a software controlled usage to support device switching.
00000000h
§
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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
8 Integrated Graphics Device
(D2:F1) Registers (Intel®
82945G/82945GC/82945GZ GMCH
Only)
The Integrated Graphics Device registers are located in Device 0 (D0), Function 0 (F0) and
Function 1 (F1). This chapter provides the descriptions for the D2:F1 registers. Table 8-1
provides an address map of the D2:F1registers listed in ascending order by address offset.
Detailed bit descriptions follow this table.
Table 8-1. Device 2 Function 1 Register Address Map (D2:F1)
Address
Offset
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID2
DID2
Vendor Identification
8086h
2776h
0000h
0090h
RO
RO
Device Identification
PCI Command
PCICMD2
PCISTS2
RID2
RO, R/W
RO
PCI Status
Revision Identification
See register
description
RO
09–0Bh
0Ch
CC
CLS
Class Code Register
Cache Line Size
03800h
00h
RO
RO
0Dh
MLT2
HDR2
—
Master Latency Timer
Header Type Register
Reserved
00h
RO
0Eh
80h
RO
0Fh
—
—
10–13h
14–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
MMADR
—
Memory Mapped Range Address
Reserved
00000000h
—
RO, R/W
—
SVID2
SID2
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
Reserved
0000h
0000h
00000000h
D0h
R/WO
R/WO
RO
ROMADR
CAPPOINT
—
RO
35–3Dh
3Eh
—
—
MINGNT
MAXLAT
—
Minimum Grant Register
Maximum Latency
00h
RO
3Fh
00h
RO
40–43h
Reserved
—
—
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Address
Offset
Symbol
Register Name
Default
Value
Access
44h
MCAPPTR
—
Mirror of Device 0 Capability Pointer
Reserved
E0h
—
RO
—
45–47h
48–50h
MCAPID
Mirror of Device 0 Capability Identification
0000000000
01090009h
RO
51h
—
Reserved
—
—
52–53h
MGGC
Mirror of Device 0 GMCH Graphics
Control
0030h
RO
54–57h
58–5Bh
5C–5Fh
60–CFh
D0–D1h
D2–D3h
D4–D5h
D6–DFh
E0–E1h
E2–FBh
FC–FFh
MDEVEN
—
Mirror of Device 0 Device Enable
Reserved
0000001Bh
—
RO
—
BSM
Base of Stolen Memory Register
Reserved
07800000h
0000h
0001h
0022h
0000h
—
RO
—
—
PMCAPID
PMCAP
PMCS
—
Power Management Capabilities ID
Power Management Capabilities
Power Management Control/Status
Reserved
RO
RO
RO, R/W
—
SWSMI
—
Software SMI
0000h
—
R/W
—
Reserved
ASLS
ASL Storage
00000000h
R/W
8.1.1
8.1.2
VID2—Vendor Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
00h
8086h
RO
Size:
16 bits
This register is a copy of Device2, Function 0. It has the same read, write attributes as Function 0.
It is implemented as common hardware with two access addresses.
DID2—Device Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
02h
2776h
RO
Size:
16 bits
This register is unique in Function 1 (the Function 0 DID is separate). This difference in Device
ID is necessary for allowing distinct Plug and Play enumeration of Function 1 when both
Function 0 and Function 1 have the same class code.
192
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8.1.3
PCICMD2—PCI Command (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
04h
0000h
RO, R/W
16 bits
Size:
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
Access &
Default
Description
15:10
9
Reserved
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0. Not Implemented.
8
7
6
RO
0b
SERR Enable (SERRE): Hardwired to 0. Not Implemented.
RO
0b
Address/Data Stepping Enable (ADSTEP): Hardwired to 0. Not Implemented.
RO
0b
Parity Error Enable (PERRE): Hardwired to 0. Not Implemented. Since the IGD
belongs to the category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error that it detects
and continues with normal operation.
5
4
3
2
RO
0b
VGA Palette Snoop Enable (VGASNOOP): Hardwired to 0 to disable snooping.
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does
not support memory write and invalidate commands.
RO
0b
Special Cycle Enable (SCE): Hardwired to 0. The IGD ignores special cycles.
R/W
0b
Bus Master Enable (BME):
0 = Disable.
1 = Enable. Enable the IGD to function as a PCI compliant master.
1
0
R/W
0b
Memory Access Enable (MAE): This bit controls the IGD’s response to memory
space accesses.
0 = Disable.
1 = Enable.
R/W
0b
I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space
accesses.
0 = Disable.
1 = Enable.
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8.1.4
PCISTS2—PCI Status (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
06h
0090h
RO
Size:
16 bits
PCISTS2 reports the occurrence of a PCI compliant master abort and PCI compliant target abort.
PCISTS2 also indicates the DEVSEL# timing that has been set by the IGD.
Bit
15
14
13
12
11
10:9
8
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Hardwired to 0. The IGD does not detect parity.
Signaled System Error (SSE): Hardwired to 0. The IGD never asserts SERR#.
RO
0b
RO
0b
Received Master Abort Status (RMAS): Hardwired to 0. The IGD never gets a
master abort.
RO
0b
Received Target Abort Status (RTAS): Hardwired to 0. The IGD never gets a
target abort.
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use
target abort semantics.
RO
00b
DEVSEL Timing (DEVT): N/A. Hardwired to 00.
RO
0b
Master Data Parity Error Detected (DPD): Hardwired to 0. Since Parity Error
Response is hardwired to disabled (and the IGD does not do any parity
detection), this bit is hardwired to 0.
7
6
5
4
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back
when the transactions are not to the same agent.
RO
0b
User Defined Format (UDF): Hardwired to 0.
66 MHz PCI Capable (66C): Hardwired to 0.
RO
0b
RO
1b
Capability List (CLIST): This bit is hardwired to 1 to indicate that the register at
34h provides an offset into the function’s PCI configuration space containing a
pointer to the location of the first item in the list.
3
RO
0b
Interrupt Status: Hardwired to 0.
2:0
Reserved
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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
8.1.5
RID2—Revision Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
08h
See bit description
RO
Size:
8 bits
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
Bit
Access &
Default
Description
7:0
RO
Revision Identification Number (RID): This is an 8-bit value that indicates the
revision identification number for the GMCH. Refer to the Intel®
945G/945GC/945GZ/945P/945PL Express Chipset Specification Update for the
value of the Revision ID register.
8.1.6
CC—Class Code Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
09h
038000h
RO
Size:
24 bits
This register contains the device programming interface information related to the Sub-Class
Code and Base Class Code definition for the IGD. This register also contains the Base Class Code
and the function sub-class in relation to the Base Class Code.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This is an 8-bit value that indicates the base class
03h
code for the GMCH.
03h = Display controller.
Sub-Class Code (SUBCC):
80h = Non VGA
15:8
7:0
RO
80h
RO
00h
Programming Interface (PI):
00h = Display controller.
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8.1.7
8.1.8
8.1.9
CLS—Cache Line Size (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Ch
00h
RO
8 bits
Size:
This register is a copy of Device2, Function 0. It has the same read, write attributes as Function 0.
It is implemented as common hardware with two access addresses.
MLT2—Master Latency Timer (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Dh
00h
RO
8 bits
Size:
This register is a copy of Device2, Function 0. It has the same read, write attributes as Function 0.
It is implemented as common hardware with two access addresses.
HDR2—Header Type Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Eh
80h
RO
8 bits
Size:
This register is a copy of Device2, Function 0. It has the same read, write attributes as Function 0.
It is implemented as common hardware with two access addresses.
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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
8.1.10
MMADR—Memory Mapped Range Address (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
10h
00000000h
RO, R/W
32 bits
Size:
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits 31:19.
Bit
31:19
18:4
3
Access &
Default
Description
R/W
0000h
Memory Base Address: Set by the operating system, these bits correspond to
address signals 31:19.
RO
0000h
Address Mask: Hardwired to 0s to indicate 512-KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 0 to indicate memory space.
RO
0b
2:1
0
RO
00b
RO
0b
8.1.11
8.1.12
SVID2—Subsystem Vendor Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Ch
0000h
RO
Size:
16 bits
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
SID2—Subsystem Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Eh
0000h
RO
Size:
16 bits
This register is a read only copy of Device 2, Function 0.
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8.1.13
8.1.14
8.1.15
8.1.16
ROMADR—Video BIOS ROM Base Address (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
30h
00000000h
RO
Size:
32 bits
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
CAPPOINT—Capabilities Pointer (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
34h
D0h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
MINGNT—Minimum Grant Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Eh
00h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
MAXLAT—Maximum Latency (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Fh
00h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
8.1.17
8.1.18
8.1.19
8.1.20
MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F1)
(Mirrored_D0_34)
PCI Device:
Address Offset:
Default Value:
Access:
2
44h
D0h
RO
8 bits
Size:
This register is a read only copy of Device 0, Offset 34h register.
MCAPID—Mirror of Device 0 Capability Identification
(D2:F1) (Mirrored_D0_E0)
PCI Device:
Address Offset:
Default Value:
Access:
2
48h
000000000001090009h
RO
Size:
72 bits
This register is a read only copy of Device 0, Offset E0h register.
MGGC—Mirror of Device 0 GMCH Graphics Control
(D2:F1) (Mirrored_D0_52)
PCI Device:
Address Offset:
Default Value:
Access:
2
52h
0030h
RO
Size:
16 bits
This register is a read only copy of Device 0, Offset 52h register.
MDEVEN—Mirror of Device 0 Device Enable (D2:F1)
(Mirrored_D0_54)
PCI Device:
2
Address Offset:
Default Value:
54h
82945G/82945GC/82945GZ GMCH: 0000001Bh
82945P/82945PL MCH: 00000003h
Access:
Size:
RO
32 bits
This register is a read only copy of Device 0, Function 0, Offset 54h register.
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8.1.21
8.1.22
8.1.23
BSM—Base of Stolen Memory Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
5Ch
07800000h
RO
Size:
32 bits
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
PMCAPID—Power Management Capabilities ID (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
D0h
0001h
RO
Size:
16 bits
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
PMCAP—Power Management Capabilities (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
D2h
0022h
RO
Size:
16 bits
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
8.1.24
PMCS—Power Management Control/Status (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
D4h
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15
RO
0b
PME_Status: This bit is 0 to indicate that IGD does not support PME#
generation from D3 (cold).
14:9
8
Reserved
RO
0b
PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2
1:0
Reserved
R/W
00b
Power State: This field indicates the current power state of the IGD and can be
used to set the IGD into a new power state. If software attempts to write an
unsupported state to this field, the write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
8.1.25
SWSMI—Software SMI (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
E0h
0000h
R/W
16 bits
Size:
This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function
0. It is implemented as common hardware with two access addresses.
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8.1.26
ASLS—ASL Storage (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
FCh
00000000h
R/W
Size:
32 bits
This software scratch register is read/write accessible. The exact bit register usage must be
worked out in common between system BIOS and driver software, but storage for
switching/indicating up to 6 devices is possible with this amount. For each device, the ASL
control method requires two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one bit
for _DGS (enable/disable requested), and two bits for _DCS (enabled now/disabled now,
connected or not).
Bit
Access &
Default
Description
31:0
R/W
R/W according to a software controlled usage to support device switching.
00000000h
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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
8.2
Device 2 – PCI I/O Registers
The following are not PCI configuration registers; they are I/O registers.
8.2.1
MMIO Index—MMIO Address Register
I/O Address:
Default:
Access:
Size:
IOBAR + 0h
00000000h
R/W
32 bits
A 32 bit I/O write to this port loads the offset of the MMIO register that needs to be accessed. An
I/O read returns the current value of this register. An 8/16-bit I/O write to this register is
completed by the GMCH but does not update this register. This mechanism is used to access
internal graphics MMIO registers; however, it must not be used to access VGA I/O registers that
are mapped through the MMIO space. VGA registers must be accessed directly through the
dedicated VGA IO ports.
Bit
31:2
1:0
Access &
Default
Description
R/W
00000000h
Register Offset: This field selects any one of the DWord registers within the
MMIO register space of Device 2.
Reserved
8.2.2
MMIO Data—MMIO Data Register
I/O Address:
Default:
Access:
Size:
IOBAR + 4h
00000000h
R/W
32 bits
A 32 bit I/O write to this port is re-directed to the MMIO register pointed to by the MMIO-index
register. A 32 bit I/O read to this port is re-directed to the MMIO register pointed to by the
MMIO-index register. 8 or 16 bit I/O writes are completed by the GMCH and may have un-
intended side effects; hence, must not be used to access the data port. 8 or 16 bit I/O reads are
completed normally.
Bit
Access &
Default
Description
31:0
R/W
MMIO Data Window
00000000h
§
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System Address Map
9 System Address Map
The 82945G/82945P (G)MCH supports 4 GB of addressable memory space (see Figure 9-1) and
64 KB+3 bytes of addressable I/O space. The 82945GC/82945GZ/82945PL (G)MCH supports 2
GB of addressable memory space and 64 KB+3 bytes of addressable I/O space. A programmable
memory address space under the 1-MB region is divided into regions that can be individually
controlled with programmable attributes such as disable, read/write, write only, or read only. This
section focuses on how the memory space is partitioned and memory region usage. The I/O
address space has simpler mapping and is explained near the end of this section.
Note: Address mapping information for the Integrated Graphics Device applies to the
82945G/82945GC/82945GZ GMCH only. The 82945P/82945PL MCH does not have an IGD.
Note: References to PCI Express applies to the 82945G/82945GC/82945P/82945PL (G)MCH only. The
82945GZ GMCH does not support PCI Express.
Note: References to 4 GB addressable memory space applies to the 82945G/82945P only. The
82945GC/82945GZ/82945PL support 2 GB addressable memory space.
Addressing of memory ranges larger than 4 GB (2 GB for 82945GC/82945GZ/82945PL) is not
supported. The HREQ[4:3] FSB pins are decoded to determine whether the access is above or
below 4 GB (2 GB for 82945GC/82945GZ/82945PL).
The (G)MCH does not support the PCI Dual Address Cycle (DAC) mechanism, PCI Express
64-bit prefetchable memory transactions, or any other addressing mechanism that allows
addressing of greater than 4 GB (2 GB for 82945GC/82945GZ/82945PL) on either the DMI or
PCI Express interface. The (G)MCH does not limit system memory space in hardware. There is
no hardware lock to prevent someone from inserting more memory than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the
DMI. The exception to this rule is VGA ranges that may be mapped to PCI Express, DMI, or to
the internal graphics device (IGD). In the absence of more specific references, cycle descriptions
referencing PCI should be interpreted as the DMI/PCI, while cycle descriptions referencing PCI
Express or IGD are related to the PCI Express bus or the internal graphics device, respectively.
The (G)MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low
Usable DRAM). The TOLUD register is set to the appropriate value by BIOS.
The Address Map includes a number of programmable ranges:
Device 0
EPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous channel
using time based weighted round robin arbitration. (4-KB window)
MCHBAR – Memory mapped range for internal (G)MCH registers. For example,
memory buffer register controls. (16-KB window)
PCIEXBAR (82945G/82945GC/82945P/82945PL Only) – Flat memory-mapped address
space to access device configuration registers. This mechanism can be used to access
PCI configuration space (0–FFh) and Extended configuration space (100h–FFFh) for
PCI Express devices. This enhanced configuration access mechanism is defined in the
PCI Express specification. (64 MB, 128 MB, or 256-MB window)
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DMIBAR – This window is used to access registers associated with the (G)MCH/ICH7
(DMI) register memory range. (4-KB window)
IFPBAR – Any write to this window will trigger a flush of the (G)MCH’s Global Write
Buffer to let software include coherency between writes from an isochronous agent and
writes from the processor (4-KB window).
GGC – GMCH graphics control register (82945G/82945GC/82945GZ GMCH only).
This register is used to select the amount of main memory that is pre-allocated to support
the internal graphics device in VGA (non-linear) and Native (linear) modes (0–64-MB
options).
Device 1, Function 0
MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
Device 2, Function 0 (82945G/82945GC/82945GZ GMCH only)
MMADR – IGD registers and internal graphics instruction port (512-KB window)
IOBAR – I/O access window for internal graphics. Through this window address/data
register pair, using I/O semantics, the IGD and internal graphics instruction port registers
can be accessed. Note that this allows accessing the same registers as MMADR. In
addition, the IOBAR can be used to issue writes to the GTTADR table.
GMADR – Internal graphics translation window (256-MB or 512-MB window)
GTTADR – Internal graphics translation table location (256-KB or 512-KB window).
Device 2, Function 1 (82945G/82945GC/82945GZ GMCH only)
MMADR – Function 1 IGD registers and internal graphics instruction port (512-KB
window)
The rules for the above programmable ranges are:
ALL of these ranges Must be unique and Non-Overlapping. It is the BIOS or system
designer’s responsibility to limit memory population so that adequate PCI, PCI Express ,
High BIOS, PCI Express memory-mapped space, and APIC memory space can be allocated.
In the case of overlapping ranges with memory, the memory decode will be given priority.
There are No Hardware Interlocks to prevent problems in the case of overlapping ranges.
Accesses to overlapped ranges may produce indeterminate results.
The only peer-to-peer cycles allowed below the top of memory (TOLUD register) are DMI to
PCI Express VGA range writes. Note that peer-to-peer cycles to the internal graphics VGA
range are not supported.
Figure 9-1 shows a simplified form of the the system memory address map.
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Figure 9-1. System Address Ranges
4 GB1
Device 0
Bars
(EPBAR,
MCHBAR,
PCIEXBAR,
DMIBAR)
Device 1
Bars
(MBASE1/
MLIMIT1,
PMBASE1/
PMLIMIT1)
Device 2
Bars
(MMADR,
GMADR,
GTTADR)
PCI Memory
Address Range
(Subtractively
decoded to DMI)
TOLUD
Device 0
GGC
(Graphics
Stolen
Main Memory
Address Range
Independently Programmable
Non-Overlapping Windows
Memory)
1 MB
Legacy Address
Range
0
Notes:
1. The 4 GB maximum is for the 82945G/82945P only. The maximum addressable
space for the 82945GZ/82945PL is 2 GB.
MemMap_SysAdr_Ranges
9.1
Legacy Address Range
This area is divided into the following address regions:
0 – 640 KB – DOS Area
640 – 768 KB – Legacy Video Buffer Area
768 – 896 KB in 16-KB sections (total of 8 sections) – Expansion Area
896 – 960 KB in 16-KB sections (total of 4 sections) – Extended System BIOS Area
960-KB – 1-MB Memory – System BIOS Area
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System Address Map
Figure 9-2. Microsoft MS-DOS* Legacy Address Range
000F_FFFFh
1 MB
System BIOS (Upper)
64 KB
000F_0000h
000E_FFFFh
960 KB
896 KB
Extended System BIOS
(Lower)
000E_0000h
000D_FFFFh
64 KB (16 KB x 4)
Expansion Area
128 KB (16 KB x 8)
000C_0000h
000B_FFFFh
768 KB
640 KB
Legacy Video Area
(SMM Memory)
128 KB
000A_0000h
0009_FFFFh
DOS Area
0000_0000h
MemMap_Legacy
9.1.1
9.1.2
DOS Range (0h – 9_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main
memory controlled by the (G)MCH.
Legacy Video Area (A_0000h–B_FFFFh)
The legacy 128-KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can be
mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI. The appropriate
mapping depends on which devices are enabled and the programming of the VGA steering bits.
Based on the VGA steering bits, priority for VGA mapping is constant. The (G)MCH always
decodes internally mapped devices first. Internal to the GMCH, decode precedence is always
given to IGD. The (G)MCH always positively decodes internally mapped devices, namely the
IGD and PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMI
depends on the Legacy VGA configuration bits (VGA Enable and MDAP); see the LAC register
(Device 0, offset 97h). This region is also the default for SMM space.
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Compatible SMRAM Address Range (A_0000h–B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed
to physical system DRAM at 000A 0000h –000B FFFFh. Non-SMM-mode processor accesses to
this range are considered to be to the video buffer area as previously described. PCI Express and
DMI-originated cycles to enabled SMM space are not allowed and are considered to be to the
video buffer area if IGD (82945G/82945GC/82945GZ GMCH on ly) is not enabled as the VGA
device. PCI Express and DMI initiated cycles are attempted as peer cycles, and will master abort
on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the
system. Accesses in the standard VGA range are forwarded to IGD, PCI Express, or the DMI
(depending on configuration bits). Since the monochrome adapter may be mapped to any one of
these devices, the (G)MCH must decode cycles in the MDA range (000B_0000h – 000B_7FFFh)
and forward either to IGD, PCI Express, or the DMI. This capability is controlled by a VGA
steering bits and the legacy configuration bit (MDAP bit). In addition to the memory range
B0000h to B7FFFh, the (G)MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and
3BFh and forwards them to the either IGD, PCI Express, and/or the DMI.
9.1.3
Expansion Area (C_0000h–D_FFFFh)
This 128-KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight 16-KB
segments. Each segment can be assigned one of four read/write states: read only, write only,
read/write, or disabled. Typically, these blocks are mapped through (G)MCH and are
subtractively decoded to ISA space. Memory that is disabled is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 9-1. Expansion Area Memory Segments
Memory Segments
Attributes
Comments
0C0000h–0C3FFFh
0C4000h–0C7FFFh
0C8000h–0CBFFFh
0CC000h–0CFFFFh
0D0000h–0D3FFFh
0D4000h–0D7FFFh
0D8000h–0DBFFFh
0DC000h–0DFFFFh
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
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9.1.4
Extended System BIOS Area (E_0000h–E_FFFFh)
This 64-KB area (000E_0000h–000E_FFFFh) is divided into four, 16-KB segments. Each
segment can be assigned independent read and write attributes so it can be mapped either to main
memory or to the DMI. Typically, this area is used for RAM or ROM. Memory segments that are
disabled are not remapped elsewhere.
Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM.
Table 9-2. Extended System BIOS Area Memory Segments
Memory Segments
Attributes
Comments
0E0000h–0E3FFFh
0E4000h–0E7FFFh
0E8000h–0EBFFFh
0EC000h–0EFFFFh
W/R
W/R
W/R
W/R
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
9.1.5
System BIOS Area (F_0000h–F_FFFFh)
This area is a single, 64-K segment (000F_0000h–000F_FFFFh). This segment can be assigned
read and write attributes. It is by default (after reset) read/write disabled and cycles are forwarded
to the DMI. By manipulating the read/write attributes, the (G)MCH can “shadow” BIOS into
main memory. When disabled, this segment is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 9-3. System BIOS Area Memory Segments
Memory Segments
Attributes
WE RE
Comments
0F0000h–0FFFFFh
BIOS Area
9.1.6
Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM memory area.
The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be IWB cycles
targeting DMI.
However, DMI becomes the default target for processor and DMI-originated accesses to disabled
segments of the PAM region. If the MTRRs covering the PAM regions are set to WB (writeback)
or RC (reference clock), it is possible to get IWB cycles targeting DMI. This may occur for DMI
originated cycles to disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read targeting the
PAM region. A snoop is generated on the FSB and the result is an IWB. Since the PAM region is
read disabled, the default target for the memory read becomes DMI. The IWB associated with this
cycle will cause the (G)MCH to hang.
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9.2
Main Memory Address Range (1 MB to TOLUD)
This address range extends from 1 MB to the top of physical memory that is permitted to be
accessible by the (G)MCH (as programmed in the TOLUD register). All accesses to addresses
within this range are forwarded by the (G)MCH to main memory unless they fall into the optional
TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
The (G)MCH provides a maximum main memory address decode space of 4 GB (2 GB for the
82945GC/82945GZ /82945PL). The (G)MCH does not remap APIC or PCI Express memory
space. This means that as the amount of physical memory populated in the system reaches 4 GB
(2 GB for the 82945GC/82945GZ/82945PL), there will be physical memory that exists yet is non-
addressable and therefore unusable by the system.
The (G)MCH does not limit main memory address space in hardware.
Figure 9-3. Main Memory Address Range
4 GB Maximum1
FFFF_FFFFh
Flash
APIC
Contains Dev 0, 1,
2 (GMCH Only),
BARS, and ICH7/
PCI Ranges
PCI Memory Range
TOLUD
IGD (1–32 MB, optional)
TSEG (1 MB / 2 MB /
8 MB, optional)
Main Memory
0100_000h
00F0_000h
16 MB
15 MB
ISA Hole (optional)
Main Memory
0010_000h
1 MB
0 MB
DOS Compatibility
Memory
0h
Notes:
1. The 4 GB maximum is for the 82945G/82945P Only. The
maximum memory for the 82945GZ/82945PL is 2 GB .
MemMap_MainMemory
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9.2.1
ISA Hole (15 MB–16 MB)
A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable bit in the LAC
register (Device 0, offset 97h). Accesses within this hole are forwarded to the DMI. The range of
physical main memory disabled by opening the hole is not remapped to the top of the memory;
that physical main memory space is not accessible. This 15 MB–16 MB hole is an optionally
enabled ISA hole.
Video accelerators originally used this hole. It is also used by validation and customer SV teams
for test cards. That is why it is being supported. There is no inherent BIOS request for the
15–16-MB window.
9.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory, which is
at the top of physical memory. SMM-mode processor accesses to enabled TSEG access the
physical DRAM at the same address. Non- processor originated accesses are not allowed to SMM
space. PCI Express, DMI, and Internal Graphics originated cycles to enabled SMM space are
handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for
writes. When the extended SMRAM space is enabled, processor accesses to the TSEG range
without SMM attribute or without WB attribute are also forwarded to memory as invalid accesses.
Non-SMM-mode Write Back cycles that target TSEG space are completed to DRAM for cache
coherency. When SMM is enabled, the maximum amount of memory available to the system is
equal to the amount of physical DRAM minus the value in the TSEG register that is fixed at 1
MB, 2 MB, or 8 MB.
9.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within
system memory address range (< TOLUD) are created for SMM-mode and legacy VGA graphics
compatibility. It is the responsibility of BIOS to properly initialize these regions. Table 9-4
details the location and attributes of the regions. How to enable and disable these ranges are
described in the (G)MCH Control Register Device 0 (GCC).
Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG
Memory Segments
Attributes
Comments
0000_0000h – 03DF_FFFFh
03E0_0000h – 03EF_FFFFh
R/W
Available system memory 62 MB
SMM mode only -
processor reads
TSEG address range and pre-allocated
memory
03F0_0000h – 03FF_FFFFh
R/W
Pre-allocated graphics VGA memory.
1 MB (or 4/8/16/32/64 MB) when IGD is
enabled.
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9.3
PCI Memory Address Range (TOLUD – 4 GB)
This address range (see Figure 9-4), from the top of physical memory to 4 GB (2 GB for the
82945GC/82945GZ/82945PL) is normally mapped via the DMI to PCI. Exceptions to this
mapping include the BAR memory mapped regions that include:
EPBAR, MCHBAR, DMIBAR
The second exception to the mapping rule deals with the PCI Express port
Addresses decoded to the PCI Express memory window defined by the MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1 registers are mapped to PCI Express.
Addresses decoded to PCI Express configuration space are mapped based on bus, device,
and function number. (PCIEXBAR range).
The third exception to the mapping rule occurs in an internal graphics configuration
(82945G/82945GC/82945GZ GMCH only)
Addresses decoded to the graphics memory range. (GMADR range)
Addresses decoded to the Graphics Translation Table range (GTTADR range).
Addresses decoded to the memory mapped range of the Internal Graphics Device
(MMADR range). There is a MMADR range for Device 2, Function 0 and a MMADR
range for Device 2, Function 1. Both ranges are forwarded to the Internal Graphics
Device.
The exceptions listed above for internal graphics and the PCI Express ports Must Not overlap
with APCI Configuration, FSB Interrupt space, and High BIOS address range.
Figure 9-4. PCI Memory Address Range
Intel®
82945GZ,
82945PL
Intel® 82945G,
82945P
FFFF_FFFFh
FFE0_0000h
4 GB
2 GB
High BIOS
4 GB – 2 MB
2 GB – 2 MB
DMI Interface
(subtractive decode)
FEF0_0000h
FEE0_0000h
4 GB – 17 MB
4 GB – 18 MB
2 GB – 17 MB
2 GB – 18 MB
FSB Interrupts
Optional HSEG
FEDA_0000h to
FEDB_FFFFh
DMI Interface
(subtractive decode)
FED0_0000h
4 GB – 19 MB
2 GB – 19 MB
Local (processor)
APIC
FEC8_0000h
FEC0_0000h
I/O APIC
4 GB – 20 MB
2 GB – 20 MB
DMI Interface
(subtractive decode)
F000_0000h
E000_0000h
4 GB – 256 MB
2 GB – 256 MB
PCI Express*
Configuration Space
Possible address range
(Not ensured)
4 GB – 512 MB
2 GB – 512 MB
Programmable windows, graphics
ranges, PCI Express* Port could be
here
DMI Interface
(subtractive decode)
TOLUD
TOLUD
MemMap_PCI
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9.3.1
9.3.2
APIC Configuration Space (FEC0_0000h–FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the ICH7
portion of the chipset, but may also exist as stand-alone components.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be
populated in the system. Since it is difficult to relocate an interrupt controller using plug-and-play
software, fixed address decode regions have been allocated for them. Processor accesses to the
default IOAPIC region (FEC0_0000h to FEC7_FFFFh) are always forwarded to DMI.
HSEG (FEDA_0000h–FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to
SMM memory. It is sometimes called the High SMM memory space. SMM-mode processor
accesses to the optionally enabled HSEG are remapped to 000A_0000h–000B_FFFFh. Non-
SMM-mode processor accesses to enabled HSEG are considered invalid and are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode writeback cycles that
are remapped to SMM space to maintain cache coherency. PCI Express and DMI originated
cycles to enabled SMM space are not allowed. Physical DRAM behind the HSEG transaction
address is not remapped and is not accessible. All Cacheline writes with WB attribute or Implicit
write backs to the HSEG range are completed to main memory like an SMM cycle.
9.3.3
9.3.4
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI
Express or DMI may issue a memory write to 0FEEx_xxxxh. The (G)MCH will forward this
memory write along with the data to the FSB as an Interrupt Message Transaction. The (G)MCH
terminates the FSB transaction by providing the response and asserting HTRDY#. This memory
write cycle does not go to main memory.
High BIOS Area
The top 2 MB (FFE0_0000h–FFFF_FFFFh) of the PCI memory address range is reserved for
system BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system
BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to
the DMI so that the upper subset of this region aliases to the 16-MB–256-KB range. The actual
address space required for the BIOS is less than 2 MB, but the minimum processor MTRR range
for this region is 2 MB so that full 2 MB must be considered.
9.3.5
PCI Express* Configuration Address Space
The device 0 PCIEXBAR register defines the base address for the 256-MB block of addresses
below top of addressable memory (currently 4 GB) for the configuration space associated with all
devices and functions that are potentially a part of the PCI Express root complex hierarchy. This
range will be aligned to a 256-MB boundary. BIOS must assign this address range such that it
will not conflict with any other address ranges.
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9.3.6
PCI Express* Graphics Attach (Intel®
82945G/82945GC/82945P/82945PL GMCH Only)
The (G)MCH can be programmed to direct memory accesses to the PCI Express interface when
addresses are within either of two ranges specified via registers in the (G)MCH’s Device 1
configuration space.
The first range is controlled via the Memory Base (MBASE) register and Memory Limit
(MLIMIT) register.
The second range is controlled via the Prefetchable Memory Base (PMBASE) register and
Prefetchable Memory Limit (PMLIMIT) register.
The (G)MCH positively decodes memory accesses to PCI Express memory address space as
defined by the following inequalities:
Memory_Base_Address Address Memory_Limit_Address
Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address
It is essential to support a separate prefetchable range to apply the USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note: The (G)MCH Device 1 memory range registers described above are used to allocate memory
address space for any PCI Express devices on PCI Express that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In other
words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the
memory base/limit and prefetchable base/limit windows.
9.3.7
AGP DRAM Graphics Aperture
Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result,
there is no need to translate addresses from PCI Express. Therefore, the (G)MCH has no
APBASE and APSIZE registers.
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System Address Map
9.3.8
Graphics Memory Address Ranges (Intel®
82945G/82945GC/82945GZ GMCH Only)
The GMCH can be programmed to direct memory accesses to IGD when addresses are within any
of three ranges specified via registers in the GMCH’s Device 2 configuration space.
The Memory Map Base register (MMADR) is used to access graphics control registers.
The Graphics Memory Aperture Base register (GMADR) is used to access graphics memory
allocated via the graphics translation table.
The Graphics Translation Table Base register (GTTADR) is used to access the translation
table.
Normally, these ranges will reside above the Top-of-Main-DRAM and below High BIOS and
APIC address ranges. They normally reside above the top of memory (TOLUD) so they do not
steal any physical DRAM memory space.
GMADR is a prefetchable range to apply USWC attribute (from the processor point of view) to
that range. The USWC attribute is used by the processor for write combining.
9.4
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM RAM). The
(G)MCH supports Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of
Memory Segment (TSEG). System Management RAM space provides a memory area that is
available for the SMI handlers and code and data storage. This memory resource is normally
hidden from the system OS so that the processor has immediate access to this memory space upon
entry to SMM. The (G)MCH provides three SMRAM options:
Below 1-MB option that supports compatible SMI handlers.
Above 1-MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD stolen
memory.
The above 1-MB solutions require changes to compatible SMRAM handlers’ code to properly
execute above 1 MB.
Note: DMI and PCI Express masters are not allowed to access the SMM space.
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9.4.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the processor to access SMM space.
DRAM SMM space is defined as the range of physical DRAM memory locations containing the
SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible,
High, and TSEG. The Compatible and TSEG SMM space is not remapped; therefore, the
addressed and DRAM SMM space is the same address range. Since the High SMM space is
remapped, the addressed and DRAM SMM space are different address ranges. Note that the High
DRAM space is the same as the Compatible Transaction Address space. The following table
describes three unique address ranges:
Compatible Transaction Address
High Transaction Address
TSEG Transaction Address
SMM Space Enabled
Transaction Address Space
DRAM Space (DRAM)
Compatible (C)
High (H)
000A_0000h to 000B_FFFFh
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
TSEG (T)
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
9.4.2
SMM Space Restrictions
If any of the following conditions are not met, the results of SMM accesses are unpredictable and
may cause the system to hang:
The Compatible SMM space must not be set-up as cacheable.
High or TSEG SMM transaction address space must not overlap address space assigned to
system DRAM, or to any PCI devices (including DMI, PCI Express, and graphics devices).
This is a BIOS responsibility.
Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
When TSEG SMM space is enabled, the TSEG space must not be reported to the operating
system as available DRAM. This is a BIOS responsibility.
Any address translated through the GMADR TLB must not target DRAM from A_0000–
F_FFFFh.
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9.4.3
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1), the compatible SMM
space is effectively disabled. Processor originated accesses to the compatible SMM space are
forwarded to PCI Express if VGAEN=1 (also depends on MDAP); otherwise, they are forwarded
to the DMI. PCI Express and DMI originated accesses are never allowed to access SMM space.
Table 9-5. SMM Space
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Disable
Enable
Disable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Disable
Enable
Enable
Disabled
Disabled
9.4.4
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows
software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit
to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM
mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI
Express. The SMM software can use this bit to write to video memory while running SMM code
out of main memory.
Table 9-6. SMM Control
G_SMRAME
D_LCK
D_CLS
D_OPEN
Processor
in SMM
Mode
SMM Code
Access
SMM Data
Access
0
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
X
X
0
0
1
1
X
0
1
X
0
0
1
0
1
X
X
X
X
0
1
X
1
X
0
1
1
Disable
Disable
Enable
Enable
Enable
Invalid
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Invalid
Disable
Enable
Disable
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9.4.5
9.4.6
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to access SMM space.
Processor WB Transaction to an Enabled SMM Address
Space
Processor writeback transactions (HREQ1# = 0) to enabled SMM address space must be written
to the associated SMM DRAM even though D_OPEN=0 and the transaction is not performed in
SMM mode. This ensures SMM space cache coherency when cacheable extended SMM space is
used.
9.4.7
SMM Access through GTT TLB (Intel®
82945G/82945GC/82945GZ GMCH Only)
Accesses through GTT TLB address translation to enabled SMM DRAM space are not allowed.
Writes will be routed to memory address 0h with byte enables de-asserted and reads will be
routed to memory address 0h.
PCI Express and DMI originated accesses are never allowed to access SMM space directly or
through the GTT TLB address translation. If a GTT TLB translated address hits enabled SMM
DRAM space, the Invalid Translation Table Entry Flag (ITTEF) in the ERRSTS register is set.
PCI Express and DMI write accesses through GMADR range will be snooped. If, when
translated, the resulting physical address is to enabled SMM DRAM space, the request will be
remapped to address 0h with de-asserted byte enables.
PCI Express and DMI read accesses to the GMADR range are not supported; therefore,
users/systems will have no address translation concerns. PCI Express and DMI reads to GMADR
will be remapped to address 0h. The read will complete with UR (unsupported request)
completion status.
GTT fetches are always decoded (at fetch time) to ensure they are not in SMM (actually, anything
above base of TSEG or 640 KB–1 MB). Thus, they will be invalid and go to address 0h. This is
not specific to PCI Express or DMI; it applies to processor or internal graphics engines. Also,
since the GMADR snoop would not be directly to the SMM space, there would not be a writeback
to SMM. In fact, the writeback would also be invalid (because it uses the same translation) and go
to address 0h.
9.4.8
Memory Shadowing
Any block of memory that can be designated as read only or write only can be “shadowed” into
(G)MCH DRAM memory. Typically, this is done to allow ROM code to execute more rapidly out
of main DRAM memory. ROM is used as read only during the copy process while DRAM, at the
same time, is designated write only. After copying, the DRAM is designated read only so that
ROM is shadowed. Processor bus transactions are routed accordingly.
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9.4.9
I/O Address Space
The (G)MCH does not support the existence of any other I/O devices beside itself on the
processor bus. The (G)MCH generates either DMI or PCI Express bus cycles for all processor I/O
accesses that it does not claim. Within the host bridge, the (G)MCH contains two internal
registers in the processor I/O space: Configuration Address (CONFIG_ADDRESS) register and
the Configuration Data (CONFIG_DATA) register. These locations are used to implement a
configuration space access mechanism.
The processor allows 64 K+3 bytes to be addressed within the I/O space. The (G)MCH
propagates the processor I/O address without any translation on to the destination bus and,
therefore, provides addressability for 64 K+3 byte locations. Note that the upper 3 locations can
be accessed only during I/O address wrap-around when the processor bus HA16# address signal
is asserted. HA16# is asserted on the processor bus whenever an I/O access is made to 4 bytes
from address 0FFFDh, 0FFFEh, or 0FFFFh. HA16# is also asserted when an I/O access is made
to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are consumed by the
internal graphics device if it is enabled. The mechanisms for internal graphics I/O decode and the
associated control are explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
the DMI bus unless they fall within the PCI Express I/O address range as defined by the
mechanisms explained below. I/O writes are not posted. Memory writes to ICH7 or PCI Express
are posted. The PCICMD1 register can disable the routing of I/O cycles to PCI Express.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream
I/O cycles and configuration cycles should never occur. If one does occur, the request will route
as a read to memory address 0h so a completion is naturally generated (whether the original
request was a read or write). The transaction will complete with a UR completion status.
For Pentium 4 processors, I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries
are issued from the processor as 1 transaction. The (G)MCH splits this into 2 separate
transactions. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed
to be split into 2 transactions by the processor.
9.4.10
9.4.11
PCI Express* I/O Address Mapping
The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus
interface when processor-initiated I/O cycle addresses are within the PCI Express I/O address
range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address
(IOLIMIT) registers in (G)MCH Device 1 configuration space.
(G)MCH Decode Rules and Cross-Bridge Address Mapping
The following are (G)MCH decode rules and cross-bridge address mapping used in this chipset:
VGAA = 000A_0000 – 000A_FFFF
MDA = 000B_0000 – 000B_7FFF
VGAB = 000B_8000 – 000B_FFFF
MAINMEM = 0100_0000 to TOLUD
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9.4.12
Legacy VGA and I/O Range Decode Rules
The legacy 128-KB VGA memory range 000A_0000h–000B_FFFFh can be mapped to IGD
(Device 2), to PCI Express (Device 1), and/or to the DMI depending on the programming of the
VGA steering bits. Priority for VGA mapping is constant in that the (G)MCH always decodes
internally mapped devices first. Internal to the GMCH, decode precedence is always given to the
IGD. The (G)MCH always positively decodes internally mapped devices, namely the IGD and
PCI Express. Subsequent decoding of regions mapped to PCI Express or the DMI depends on the
Legacy VGA configurations bits (VGA Enable and MDAP) in the LAC register (Device 0).
§
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Functional Description
10 Functional Description
This chapter describes the (G)MCH interfaces and major functional units.
10.1
Host Interface
The (G)MCH supports the Pentium® 4 processor subset of the Enhanced Mode Scaleable Bus.
The cache line size is 64 bytes. Source synchronous transfer is used for the address and data
signals. The address signals are double pumped and a new address can be generated every other
bus clock. At 200/267 MHz bus clock, the address signals run at 400/533MT/s. The data is quad
pumped and an entire 64 B cache line can be transferred in two bus clocks. At 200/267 MHz bus
clock, the data signals run at 800/1066MT/s for a maximum bandwidth of 10.7 GB/s.
10.1.1
10.1.2
10.1.3
FSB IOQ Depth
The Scalable bus supports up to 12 simultaneous outstanding transactions.
FSB OOQ Depth
The (G)MCH supports only one outstanding deferred transaction on the FSB.
FSB GTL+ Termination
The (G)MCH integrates GTL+ termination resistors on die. Also, approximately 2.8 pf (fast) –
3.3 pf (slow) per pad of on die capacitance will be implemented to provide better FSB electrical
performance.
10.1.4
FSB Dynamic Bus Inversion
The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from
the processor. DBI limits the number of data signals that are driven to a low voltage on each quad
pumped data phase. This decreases the worst-case power consumption of the (G)MCH.
HDINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus for each quad
pumped data phase:
HDINV[3:0]#
Data Bits
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HD15:0#
HD31:16#
HD47:32#
HD63:48#
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Functional Description
When the processor or the (G)MCH drives data, each 16-bit segment is analyzed. If more than 8
of the 16 signals would normally be driven low on the bus, the corresponding HDINVx# signal
will be asserted and the data will be inverted prior to being driven on the bus. When the processor
or the (G)MCH receives data, it monitors HDINV[3:0]# to determine if the corresponding data
segment should be inverted.
10.1.4.1
APIC Cluster Mode Support
This is required for backwards compatibility with existing software, including various operating
systems. As one example, beginning with Microsoft Windows 2000 there is a mode (boot.ini) that
allows an end user to enable the use of cluster addressing support of the APIC.
The (G)MCH supports three types of interrupt re-direction:
Physical
Flat-Logical
Clustered-Logical
10.2
System Memory Controller
The system memory controller supports two styles of memory organization (Interleaved and
Asymmetric). Rules for populating DIMM slots are included in this section. Sample memory
organizations are provided in Table 10-1 and Table 10-2.
Note: The 82945G/82945P (G)MCH maximum memory size is 4 GB.
Note: The 82945GC/82945GZ/82945PL (G)MCH maximum memory size is 2 GB.
Table 10-1. Sample System Memory Organization with Interleaved Channels
Rank
Channel A
Population
Cumulative Top
Address in
Channel B
Population
Cumulative Top
Address in
Channel A
Channel B
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
Table 10-2. Sample System Memory Organization with Asymmetric Channels
Rank
Channel A
Population
Cumulative Top
address in
Channel B
Population
Cumulative Top
Address in
Channel A
Channel B
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
1280 MB
1280 MB
1024 MB
512 MB
0 MB
2560 MB
2560 MB
2304 MB
1792 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
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Functional Description
Interleaved Mode
This mode provides maximum performance on real applications. Addresses are ping-ponged
between the channels, and the switch happens after each cache line (64 byte boundary). If two
consecutive cache lines are requested, both may be retrieved simultaneously, since they are
ensured to be on opposite channels. The drawbacks of Interleaved Mode are that the system
designer must populate both channels of memory such that they have equal capacity, but the
technology and device width may vary from one channel to the other. Refer to Figure 10-1 for
further clarification.
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode, addresses
start in channel A and stay there until the end of the highest rank in channel A; then, addresses
continue from the bottom of channel B to the top. Real world applications are unlikely to make
requests that alternate between addresses that sit on opposite channels with this memory
organization, so in most cases, bandwidth will be limited to that of a single channel. The system
designer is free to populate or not to populate any rank on either channel, including either
degenerate single channel case. Refer to Figure 10-1 for further clarification.
Figure 10-1. System Memory Styles
Dual Channel Interleaved
(channels must match
total size)
Dual Channel Asymmetric
(channels do not have to
match)
Single Channel
CL
CL
CL
CH B
TOM
TOM
CH B
CH A
TOM
CH B
CH B0
CH A
TOM
CH A or CH B
CH B
CH A
CH B
CH A
CH A
CH A0
MemSys_Styles
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Functional Description
10.2.1
System Memory Configuration Registers Overview
The configuration registers located in the PCI configuration space of the (G)MCH control the
system memory operation. Following is a brief description of configuration registers.
DRAM Rank Boundary (CxDRBy): The x represents a channel, either A or B. The y
represents a rank, 0 through 3. DRB registers define the upper addresses for a rank of DRAM
devices in a channel. When the (G)MCH is configured in asymmetric mode, each register
represents a single rank. When the (G)MCH is configured in a dual interleaved mode, each
register represents a pair of corresponding ranks in opposing channels. There are 4 DRB
registers for each channel.
DRAM Rank Architecture (CxDRAy): The x represents a channel, either A or B. The y
represents a rank, 0 through 3. DRA registers specify the architecture features of each rank of
devices in a channel. The only architecture feature specified is page size. When the (G)MCH
is configured in asymmetric mode, each DRA represents a single rank in a single channel.
When (G)MCH is configured in a dual-channel interleaved mode, each DRA represents a
pair of corresponding ranks in opposing channels. There are 4 DRA registers per channel.
Each requires only 3 bits, so there are two DRAs packed into a byte.
Clock Configuration (CLKCFG): CLKCFG specifies DRAM frequency. The same clock
frequency will be driven to all DIMMs.
DRAM Timing (CxDRT1): The x represents a channel, A or B represented by 0 and 1
respectively. The DRT Register defines the timing parameters for all devices in a channel.
BIOS programs this register with “least common denominator” values after reading the SPD
registers of each DIMM in the channel.
DRAM Control (CxDRC0): The x represents a channel, A or B represented by 0 and 1
respectively. DRAM refresh mode, rate, and other controls are selected here.
10.2.2
DRAM Technologies and Organization
"Single sided" below is a logical term referring to the number of chip selects attached to the
DIMM. A real DIMM may put the components on both sides of the substrate, but be logically
indistinguishable from single-sided DIMM if all components on the DIMM are attached to the
same chip select signal.
x8 means that each component has 8 data lines.
x16 means that each component has 16 data lines
All standard 256-Mb, 512-Mb, and 1-Gb technologies and addressing are supported for x16 and
x8 devices.
For DDR2:
400 MHz (PC2 3200)
Non-ECC
Version A = Single sided x8
Version B = Double sided x8
Version C = Single sided x16
533 MHz (PC 4300)
Non-ECC
Version A = Single sided x8
Version B = Double sided x8
Version C = Single sided x16
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Functional Description
667 MHz (PC 5300) (82945G/82945GC/82945P (G)MCH Only)
Non-ECC
Version C = Single sided x16
Version D = Single sided x8
Version E = Double sided x8
There is No support for DIMMs with different technologies or capacities on opposite sides of the
same DIMM. If one side of a DIMM is populated, the other side is either identical or empty.
Supported components include:
For DDR2 at 533 MHz (PC4300) and 667 MHz (PC5300) (667 MHz on
82945G/82945GC/82945P (G)MCH Only)
256-Mb technology
32-M cells x8 data bits/cell
1-K columns
4 banks
8-K rows
Each component has a 1-KB page.
One DIMM has 8 components resulting in an 8-KB page.
The capacity of one rank is 256 MB.
16-M cells x16 data bits/cell
512 columns
4 banks
8-K rows
Each component has a 1-KB page.
One DIMM has 4 components resulting in a 4-KB page.
The capacity of one rank is 128 MB.
512-Mb technology
64-M cells x8 data bits/cell
1K columns
4 banks
16K rows
Each component has a 1-KB page.
One DIMM has 8 components resulting in an 8-KB page.
The capacity of one rank is 512 MB.
32-M cells x16 data bits/cell
1-K columns
4 banks
8-K rows
Each component has a 2-KB page.
One DIMM has 4 components resulting in an 8-KB page.
The capacity of one rank is 256 MB.
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Functional Description
1-Gb technology
128-M cells x8 data bits/cell
1-K columns
8 banks
16-K rows
Each component has a 1-KB page.
One DIMM has 8 components resulting in an 8-KB page.
The capacity of one rank is 1 GB.
64-M cells x16 data bits/cell
1-K columns
8 banks
8-K rows
Each component has a 2-KB page.
One DIMM has 4 components resulting in an 8-KB page.
The capacity of one rank is 512MB.
The DRAM sub-system supports single or dual channels, 64b wide per channel. There can be a
maximum of 4 ranks populated (2 Double Sided DIMMs) per channel. Mixed mode DDR DS-
DIMMs (x8 and x16 on the same DIMM) are not supported (not validated)
By using 1Gb technology, the largest memory capacity is 8 GB (16K rows * 1K columns *
1 cell/(row * column) * 8 b/cell * 8 banks/device * 8 devices/rank * 4 ranks/channel *
2 channel *1M/(K*K) * 1G/1024M * 1B/8b = 8 GB). Using 8 GB of memory is only possible in
Interleaved mode with all ranks populated at maximum capacity. The Intel 82945G GMCH and
82894P MCH are limited to 4 GB of address space. Any memory in the system beyond 4 GB
cannot be addressed and should not be populated due to the additional loading it places on the
memory subsystem.
By using 256Mb technology, the smallest memory capacity is 128 MB (8K rows * 512 columns *
1 cell/(row * column) * 16b/cell * 4 banks/device * 4 devices/rank * 1 rank * 1M/1024K * 1B/8b
= 128 MB)
10.2.2.1
Rules for Populating DIMM Slots
In all modes, the frequency of system memory will be the lowest frequency of all DIMMs in
the system, as determined through the SPD registers on the DIMMs.
In the single channel mode, any DIMM slot within the channel may be populated in any
order. Either channel may be used. To save power, do not populate the unused channel.
In dual channel asymmetric mode, any DIMM slot may be populated in any order.
In dual channel interleaved mode, any DIMM slot may be populated in any order, but the
total memory in each channel must be the same.
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Functional Description
10.2.2.2
System Memory Supported Configurations
The (G)MCH supports the 256 Mbit, 512 Mbit and 1 Gbit technology based DIMMs from
Table 10-3.
Table 10-3. DDR2 DIMM Supported Configurations
Technology
Configuration
# of Row
Address
Bits
# of
Column
Address
Bits
# of Bank
Address
Bits
Page
Size
Rank
Size
256Mbit
256Mbit
512Mbit
512Mbit
1Gbit
16M X 16
32M X 8
32M X 16
64M X 8
64M X 16
128M X 8
13
13
13
14
13
14
9
2
2
2
2
3
3
4K
8K
8K
8K
8K
8K
128 MB
256 MB
256 MB
512 MB
512 MB
1 GB
10
10
10
10
10
1Gbit
10.2.2.3
Main Memory DRAM Address Translation and Decoding
Table 10-4 and Table 10-5 specify the host interface to memory interface address multiplex for
the (G)MCH. Refer to the details of the various DIMM configurations as described in
Table 10-3. The address lines specified in the column header refer to the host (processor) address
lines.
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S k i z e R a n
z e
P a g e S i
B a n k s
T e c h
S k i z e R a n
z e
P a g e S i
B a n k s
T e c h
Functional Description
10.2.3
10.2.4
DRAM Clock Generation
The (G)MCH generates three differential clock pairs for every supported DIMM. There are a total
of 6 clock pairs driven directly by the (G)MCH to 2 DIMMs per channel.
Suspend to RAM and Resume
When entering the Suspend to RAM (STR) state, the SDRAM controller will flush pending cycles
and then enter all SDRAM rows into self refresh. In STR, the CKE signals remain Low so the
SDRAM devices will perform self-refresh.
10.2.5
DDR2 On Die Termination
On die termination (ODT) is a feature that allows a DRAM to turn on/off internal termination
resistance for each SDQ_x, SDM_x, SDQS_x, and SDQS_x# signal for x8 and x16
configurations via the SODT_x control signals. The SODT_x feature is designed to improve
signal integrity of the memory channel by allowing the termination resistance for the SDQ_x,
SDM_x, SDQS_x, and SDQS_x# signals to be located inside the DRAM devices themselves
instead of on the motherboard. The (G)MCH drives out the required SODT_x signals, based on
memory configuration and which rank is being written to or read from, to the DRAM devices on a
targeted DIMM rank to enable or disable their termination resistance.
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Functional Description
10.3
PCI Express* (Intel® 82945G/82945GC/
82945P/82945PL (G)MCH Only)
Refer to Section 1.3.4 for list of PCI Express features, and the PCI Express specification for
further details. Refer to Section 10.4 for additional information on the features/capabilities of the
multiplexed PCI Express interface and SDVO ports.
The (G)MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in device 1 configuration space and two Root Complex Register Blocks
(RCRBs). The DMI RCRB contains registers for control of the ICH7 attach ports.
The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model
(a load-store architecture with a flat address space) is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses standard
mechanisms as defined in the PCI Plug-and-Play specification. The initial speed of 1.25 GHz
(250 MHz internally) results in 2.5 Gb/s/direction that provides a 250 MB/s communications
channel in each direction (500 MB/s total) that is close to twice the data rate of classic PCI per
lane.
10.3.1
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer’s
primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
TLPs are used to communicate transactions, such as read and write, as well as certain types of
events. The Transaction Layer also manages flow control of TLPs.
10.3.2
10.3.3
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage
between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer
include link management, error detection, and error correction.
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input
buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching
circuitry.
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Functional Description
10.4
Intel® Serial Digital Video Output (SDVO) (Intel®
82945G/82945GC/82945GZ GMCH Only)
The 82945G/82945GC GMCH SDVO ports are multiplexed with the PCI Express x16 interface.
The 82945GZ GMCH SDVO ports are not multiplexed. The Intel® SDVO port is the second
generation of digital video output from compliant Intel GMCHs. The electrical interface is based
on the PCI Express interface, though the protocol and timings are completely unique. Whereas
PCI Express runs at a fixed frequency, the frequency of the SDVO interface is dependant on the
active display resolution and timing. The port can be dynamically configured in several modes to
support display configurations.
Essentially, a SDVO port will transmit display data in a high speed, serial format across
differential AC coupled signals. A SDVO port consists of a sideband differential clock pair and a
number of differential data pairs.
10.4.1
Intel® SDVO Capabilities
SDVO ports can support a variety of display types including LVDS, DVI, Analog CRT, TV-Out
and external CE type devices. The GMCH uses an external SDVO device to translate from SDVO
protocol and timings to the desired display format and timings.
The internal graphics controller can have one or two SDVO ports multiplexed on the x16 PCI
Express interface. When an external x16 PCI Express graphics accelerator is not in use, an ADD2
card may be plugged into the x16 connector or if a x16 slot is not present, the SDVO(s) may be
located ‘down’ on the motherboard to access the multiplexed SDVO ports and provide a variety
of digital display options.
The ADD2/ADD2+ card is designed to fit in a x16 PCI Express connector. The ADD2/ADD2+
card can support one or two devices. If a single channel SDVO device is used, it should be
attached to the channel B SDVO pins. The ADD2 card can support two separate SDVO devices
when the interface is in Dual Independent or Dual Simultaneous Standard modes. The ADD2+
card adds Video in capabilities.
The SDVO port defines a two-wire point-to-point communication path between the SDVO device
and GMCH. The SDVO control clock and data provide similar functionality to I2C. However,
unlike I2C, this interface is intended to be point-to-point (from the GMCH to the SDVO device)
and will require the SDVO device to act as a switch and direct traffic from the SDVO control bus
to the appropriate receiver. Additionally, this control bus will be able to run at faster speeds (up to
1 MHz) than a traditional I2C interface.
234
Functional Description
Figure 10-2. SDVO Conceptual Block Diagram
Analog RGB
Monitor
Control Clock
Control Data
TV Clock In
Stall
Interrupt
3rd Party
SDVO
External
Device(s)
Digital
Display
Device(s)
or TV
ClockC
Internal
Graphics
RedC / AlphaB
BlueC
PCI
Express*
Logic
ClockB
RedB
GreenB
BlueB
GMCH
SDVO_BlkDia
Note: PCI Express ports are only on the 82945G/82945GC GMCH. On the 82945GZ,
these pins are dedicated SDVO pins.
10.4.2
Intel® SDVO Modes
The port can be dynamically configured in several modes:
Standard. This mode provides baseline SDVO functionality. It supports pixel rates between
25 MP/s and 200 MP/s. It uses three data pairs to transfer RGB data.
Extended. This mode adds Alpha support to data stream. It supports pixel rates between
25 MP/s and 200 MP/s. This mode uses four data channels and is only supported on SDVOB.
It leverages channel C (SDVOC) Red pair as the Alpha pair for channel B (SDVOB).
Dual Standard. This mode uses standard data streams across both SDVOB and SDVOC.
Both channels can only run in Standard mode (3 data pairs) and each channel supports pixel
rates between 25 MP/s and 200 MP/s.
Dual Independent Standard. In Dual Independent Standard mode, each SDVO channel
will see a different pixel stream. The data stream across SDVOB will not be the same as
the data stream across SDVOC.
Dual Simultaneous Standard. In Dual Simultaneous Standard mode, both SDVO
channels will see the same pixel stream. The data stream across SDVOB will be the same
as the data stream across SDVOC. The display timings will be identical, but the transfer
timings may not be (i.e., SDVOB clocks and data may not be perfectly aligned with
SDVOC clock and data as seen at the SDVO device(s). Since this mode uses just a single
data stream, it uses a single pixel pipeline within the GMCH.
235
Functional Description
10.4.3
PCI Express* and Internal Graphics Simultaneous
Operation (Intel® 82945G/82945GC GMCH Only)
10.4.3.1
Standard PCI Express* Cards and Internal Graphics
BIOS control of simultaneous operation is needed to ensure the PCI Express is configured
appropriately.
10.4.3.2
ADD2+ Cards (Concurrent SDVO and PCI Express*)
SDVO lane reversal is supported. This functionality allows current SDVO ADD2 cards to work
in current ATX and BTX systems instead of requiring a separate card. The 82945G GMCH
allows SDVO and PCI Express to operate concurrently on the PCI Express port. The card that
plugs into the x16 connector in this case is called an ADD2+ card. It uses 4 or 8 lanes for SDVO
and up to 8 lanes of standard PCI Express.
Note: The only supported PCI Express width when SDVO is present is x1.
Note: The 82945GC supports only ADD2 cards and not ADD2+. The 945GC does not support
concurrent SDVO and PCI Express*)
This concurrency is supported in reversed and non-reversed configurations. Mirroring / Reversing
is always about the axis between PCI Express lanes 7 and 8.
Table 10-6. Concurrent SDVO / PCI Express* Configuration Strap Controls
Slot
Reversed
Strap
SDVO
Present
Strap
SDVO/PCI
Express*
Concurrent Strap
Config #
Description
1
2
3
4
5
PCI Express not reversed
PCI Express Reversed
—
Yes
—
—
—
—
—
SDVO (ADD2) not reversed
SDVO (ADD2) Reversed
Yes
Yes
Yes
—
Yes
—
—
SDVO and PCI Express (ADD2+)
not reversed
Yes
6
SDVO and PCI Express (ADD2+)
Reversed
Yes
Yes
Yes
NOTES:
1.
The Configuration #s refer to the following figures (no intentional relation to validation
configurations).
2.
Configurations 4, 5, and 6 are new for the 82945G GMCH (required addition of SDVO/PCI Express
Concurrent Strap).
236
Functional Description
Figure 10-3. Concurrent SDVO / PCI Express* Non-Reversed Configurations
GMCH GMCH
PEG PEG
Signals Pins
1
3
5
0
0
0
0
0
0
PCIe Lane 0
x1
PCIe
Card
x4
sDVO
(ADD2)
PCIe
Video In
Card
PCIe Lane N
x8
ADD2+ Card
x16
PCIe
Card
sDVO
(ADD2)
Card
sDVO Lane
7
Video Out
sDVO
sDVO Lane
0
15
15
15
15
15
SDVO-Conc-PCIe_Non-Reversed_Con
Figure 10-4. Concurrent SDVO / PCI Express* Reversed Configurations
GMCH GMCH
2
4
6
PEG
PEG
Signals Pins
15
0
15
15
15
sDVO Lane 0
sDVO
Video Out
sDVO Lane 7
x8
x16
PCIe
Card
sDVO
(ADD2)
Card
ADD2+ Card
PCIe Lane N
PCIe
x4
sDVO
(ADD2)
Card
Video In
x1
PCIe
Card
0
PCIe Lane 0
0
15
0
0
0
SDVO-Conc-PCIe_Reversed_Con
237
Functional Description
Figure 10-5. Concurrent SDVO / PCI Express* Signal Multiplexing
PCIe[15:8]
PCIe[0:7]
0
1
0
1
nothing
0
1
sDVO[0:7]
0
1
Upper 8 lanes
nothing
0
1
sDVO[0:7]
PCIe[0:7]
0
1
LaneReversal
ToPEG
port pins
PCIe[7:0]
0
1
PCIe[8:15]
0
1
sDVO[7:0]
0
1
nothing
Lower 8 lanes
0
1
nothing
0
1
PCIe[7:0]
0
1
sDVO[7:0]
Gray logic is optional. The sDVO/PCIe
Concurrent strap is sufficient toindicate
concurrentconfigurations. It canimply
that sDVOis present.
Straps
Slot Reversed
sDVO Present
sDVO/PCIeConcurrent
SD VO-Conc -PCIe_SignalMux in
238
Functional Description
10.5
Integrated Graphics Device (Intel®
82945G/82945GC/82945GZ GMCH Only)
The major components in the Integrated Graphics Device (IGD) are the engines, planes, pipes and
ports. The GMCH has a 3D/2D instruction processing unit to control the 3D and 2D engines. The
IGD’s 3D and 2D engines are fed with data through the memory controller. The output of the
engines are surfaces sent to memory that are then retrieved and processed by the GMCH planes.
The GMCH contains a variety of planes, such as display, overlay, cursor and VGA. A plane
consists of rectangular shaped image that has characteristics such as source, size, position,
method, and format. These planes get attached to source surfaces that are rectangular memory
surfaces with a similar set of characteristics. They are also associated with a particular destination
pipe.
A pipe consists of a set of combined planes and a timing generator. The GMCH has two
independent display pipes, allowing for support of two independent display streams. A port is the
destination for the result of the pipe. The GMCH contains three display ports; 1 analog (DAC)
and two digital (SDVO ports B and C). The ports will be explained in more detail later in this
section .
The entire IGD is fed with data from its memory controller. The GMCH’s graphics performance
is directly related to the amount of bandwidth available. If the engines are not receiving data fast
enough from the memory controller (e.g., single-channel DDR2 533), the rest of the IGD will also
be affected.
The rest of this section will focus on explaining the IGD components, their limitations, and
dependencies.
10.5.1
3D Graphics Pipeline
The GMCH graphics is the next step in the evolution of integrated graphics. In addition to
running the graphics engine at 400 MHz, the GMCH graphics has four pixel pipelines that
provide a 1.3 GB/s fill rate that enables an excellent consumer gaming experience.
The 3D graphics pipeline for the GMCH has a deep pipelined architecture in which each stage
can simultaneously operate on different primitives or on different portions of the same primitive.
The 3D graphics pipeline is divided into four major stages: geometry processing, setup (vertex
processing), texture application, and rasterization.
The GMCH graphics is optimized for use with current and future Intel® processors for advance
software based transform and lighting techniques (geometry processing) as defined by the
Microsoft Direct X* API. The other three stages of 3D processing are handled on the integrated
graphics device. The setup stage is responsible for vertex processing; converting vertices to
pixels. The texture application stage applies textures to pixels. The rasterization engine takes
textured pixels and applies lighting and other environmental affects to produce the final pixel
value. From the rasterization stage, the final pixel value is written to the frame buffer in memory
so it can be displayed.
239
Functional Description
Figure 10-6. Integrated 3D Graphics Pipeline
Processor
Geometry:
Transform and Lighting, Vertex Shader
GMCH
Setup Engine:
Vertices in, Pixels out
Texture Engine:
Pixels in, Textured Pixels out
Raster Engine:
Textured Pixels in, Final Pixels out
3D-Gfx_Pipeline
10.5.2
3D Engine
The 3D engine on the GMCH has been designed with a deep pipelined architecture, where
performance is maximized by allowing each stage of the pipeline to simultaneously operate on
different primitives or portions of the same primitive. The GMCH supports Perspective-Correct
Texture Mapping, Multitextures, Bump-Mapping, Cubic Environment Maps, Bilinear, Trilinear
and Anisotropic MIP mapped filtering, Gouraud shading, Alpha-blending, Vertex and Per Pixel
Fog and Z/W Buffering.
The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the
pipline are the setup engine, scan converter, texture pipeline, and raster pipeline. A typical
programming sequence would be to send instructions to set the state of the pipeline followed by
rending instructions containing 3D primitive vertex data.
The engines’ performance is dependent on the memory bandwidth available. Systems that have
more bandwidth available will outperform systems with less bandwidth. The engines’
performance is also dependent on the core clock frequency. The higher the frequency, the more
data is processed.
240
Functional Description
10.5.3
4X Faster Setup Engine
The setup stage of the pipeline takes the input data associated with each vertex of a 3D primitive
and computes the various parameters required for scan conversion. In formatting this data, the
GMCH maintains sub-pixel accuracy. For the 82945G/82945GC/82945GZ GMCH, it was
redesigned to run at 1 cycle/attribute.
10.5.3.1
3D Primitives and Data Formats Support
The 3D primitives rendered by the GMCH are points, lines, discrete triangles, line strips, triangle
strips, triangle fans, and polygons. In addition to this, the GMCH supports the Microsoft DirectX
Flexible Vertex Format (FVF) that enables the application to specify a variable length parameter
list. This obviates the need for sending unused information to the hardware. Strips, Fans, and
Indexed Vertices, as well as FVF, improve the vertex rate delivered to the setup engine
significantly.
10.5.3.2
Pixel Accurate “Fast” Scissoring and Clipping Operation
The GMCH supports 2D clipping to a scissor rectangle within the drawing window. Objects are
clipped to the scissor rectangle, avoiding processing pixels that fall outside the rectangle. The
GMCH’s clipping and scissoring in hardware reduce the need for software to clip objects, and
thus improve performance. During the setup stage, the GMCH clips objects to the scissor
window.
A scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger
region than the hardware renders to. The scissor rectangle needs to be pixel accurate, and
independent of line and point width. The GMCH supports a single scissor box rectangle that can
be enabled or disabled. The rectangle is defined as an Inclusive box. Inclusive is defined as “draw
the pixel if it is inside the scissor rectangle”.
10.5.3.3
Depth Bias
The GMCH supports source depth biasing in the setup engine The depth bias value is specified in
the vertex command packet on a per primitive basis. The value ranges from -1 to 1. The depth
bias value is added to the z or w value of the vertices. This is used for coplanar polygon priority.
If two polygons are to be rendered that are coplanar, due to the inherent precision differences
induced by unique x, y, and z values, there is no assurance of which polygon will be closer or
farther. By using depth bias, it is possible to offset the destination z value (compare value) before
comparing with the new z value.
241
Functional Description
10.5.3.4
Backface Culling
As part of the setup, the GMCH discards polygons from further processing, if they are facing
away from or towards the user’s viewpoint. This operation, referred to as “Backface Culling” is
accomplished based on the “clockwise” or “counter-clockwise” orientation of the vertices on a
primitive. This can be enabled or disabled by the driver.
10.5.3.5
10.5.3.6
Scan Converter
Working on a per-polygon basis, the scan converter uses the vertex and edge information to
identify all pixels affected by features being rendered.
Pixel Rasterization Rules
The GMCH supports both OpenGL and D3D pixel rasterization rules to determine whether a
pixel is filled by the triangle or line. For both D3D and OpenGL modes, a top-left filling
convention for filling geometry will be used. Pixel rasterization rule on rectangle primitive is also
supported using the top-left fill convention.
10.5.3.7
Pixel Pipeline
The pixel pipeline function combines, for each pixel, the interpolated vertex components from the
scan conversion function, texel values from the texture samplers, and the pixel’s current values
from the color and/or depth buffers. This combination is performed by a programmable pixel
shader engine, followed by a pipeline for optional pixel operations performed in a specific order.
The result of these operations can be written to the color and depth buffers.
10.5.3.8
10.5.3.9
Texture Samplers
A texture sampler takes a texture coordinate and its partial derivatives, access (samples) texture
maps, applies filtering and other operations to the texel samples, and feeds the resultant per-pixel
texel outputs to pixel shader registers. Sixteen texture samplers are supported.
2D Functionality
The stretch Block Level Transfer (BLT) function can stretch source data in the X and Y directions
to a destination larger or smaller than the source. Stretch BLT functionality expands a region of
memory into a larger or smaller region using replication and interpolation. The stretch BLT
function also provides format conversion and data alignment.
242
Functional Description
10.5.4
Texture Engine
The GMCH allows an image, pattern, or video to be placed on the surface of a 3D polygon. The
texture processor receives the texture coordinate information from the setup engine and the
texture blend information from the scan converter. The texture processor performs texture color
or ChromaKey matching, texture filtering (anisotropic, trilinear, and bilinear interpolation), and
YUV-to-RGB conversions.
10.5.4.1
Perspective Correct Texture Support
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon.
A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in
perspective, it is important that texture be mapped in perspective as well. Without perspective
correction, texture is distorted when an object recedes into the distance.
10.5.4.2
10.5.4.3
Texture Formats and Storage
The GMCH supports up to 32 bits of color for textures.
Texture Decompression
DirectX supports texture compression to reduce the bandwidth required to deliver textures. As the
textures’ average size gets larger with higher color depth and multiple textures become the norm,
it becomes increasingly important to provide a mechanism for compressing textures. Texture
decompression formats supported include DXT1, DXT2, DXT3, DXT4, DXT5, and FXT1.
10.5.4.4
10.5.4.5
Texture ChromaKey
ChromaKey describes a method of removing a specific color or range of colors from a texture
map before it is applied to an object. For “nearest” texture filter modes, removing a color simply
makes those portions of the object transparent (the previous contents of the back buffer show
through). For “ linear “ texture filtering modes, the texture filter is modified if only the non-
nearest neighbor texels match the key (range).
Anti-Aliasing
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing
causes the jagged staircase effects on sloped lines and polygon edges. Another artifact is the
moiré patterns that occur as a result of a very small number of pixels available on screen to
contain the data of a high-resolution texture map. More subtle effects are observed in animation,
where very small primitives blink in and out of view.
243
Functional Description
10.5.4.6
Texture Map Filtering
The GMCH supports many texture mapping modes. Perspective correct mapping is always
performed. As the map is fitted across the polygon, the map can be tiled, mirrored in either the U
or V directions, or mapped up to the end of the texture and no longer placed on the object (this is
known as clamp mode). The way a texture is combined with other object attributes is also
definable.
The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1
texels. Textures need not be square. Included in the texture processor is a texture cache that
provides efficient MIP-mapping.
The GMCH supports 7 types of texture filtering:
Nearest (aka Point Filtering): Texel with coordinates nearest to the desired pixel is used.
(This is used if only one LOD is present).
Linear (aka Bilinear Filtering): A weighted average of a 2x2 area of texels surrounding the
desired pixel is used. (This is used if only one LOD is present).
Nearest MIP Nearest (aka Point Filtering): This is used if many LODs are present. The
nearest LOD is chosen and the texel with coordinates nearest to the desired pixel is used.
Linear MIP Nearest (Bilinear MIP Mapping): This is used if many LODs are present. The
nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the
desired pixel is used (four texels). This is also referred to as Bilinear MIP Mapping.
Nearest MIP Linear (Point MIP Mapping): This is used if many LODs are present. Two
appropriate LODs are selected and within each LOD the texel with coordinates nearest to the
desired pixel is selected. The final texture value is generated by linear interpolation between
the two texels selected from each of the MIP Maps.
Linear MIP Linear (Trilinear MIP Mapping): This is used if many LODs are present. Two
appropriate LODs are selected and a weighted average of a 2x2 area of texels surrounding the
desired pixel in each MIP Map is generated (four texels per MIP Map). The final texture
value is generated by linear interpolation between the two texels generated for each of the
MIP Maps. Trilinear MIP Mapping is used to minimize the visibility of LOD transitions
across the polygon.
Anisotropic MIP Nearest (Anisotropic Filtering): This is used if many LODs are present. The
nearest LOD-1 level will be determined for each of four sub-samples for the desired pixel.
These four sub-samples are then bilinear filtered and averaged together.
Both D3D (DirectX 6.0) and OGL (Revision 1.1) allow support for all these filtering modes.
10.5.4.7
Multiple Texture Composition
The GMCH also performs multiple texture composition. This allows the combination of two or
greater MIP Maps to produce a new one with new LODs and texture attributes in a single or
iterated pass. Flexible vertex format support allows multitexturing because it makes it possible to
pass more than one texture in the vertex structure.
244
Functional Description
10.5.4.8
10.5.4.9
Pixel Shader
DX9 PS 2.0-compliant pixel shader. This includes perspective-correct diffuse and specular color
interpolation via internal use of texcoords. In addition, there is support for non-perspective-
correct texture coordinates as well as support for fog parameter separate from specular alpha.
Cube Map Textures
Multiple texture map surfaces arranged into a cubic environment map are supported. There is also
support for CLAMP and CUBE texture address mode for Cubemaps.
10.5.4.10 4x4 Texture Filtering Includes Cube Maps
Compressed Cube Map Mip-amps
New format support for compressed cube maps that allows each mip/face to exist in its own
compression block.
Cubic Environment Mapping
Environment maps allow applications to render scenes with complex lighting and reflections
while significantly decreasing processor load. There are several methods to generate environment
maps (such as, spherical, circular, and cubic). The GMCH supports cubic reflection mapping over
spherical and circular since it is the best choice to provide real-time environment mapping for
complex lighting and reflections.
Cubic mapping requires a texture map for each of the 6 cube faces. These can be generated by
pointing a camera with a 90-degree field-of-view in the appropriate direction. Per-vertex vectors
(normal, reflection, or refraction) are interpolated across the polygon and the intersection of these
vectors with the cube texture faces is calculated. Texel values are then read from the intersection
point on the appropriate face and filtered accordingly.
10.5.5
Raster Engine
The raster engine is where the color data (such as, fogging, specular RGB, texture map blending,
etc.) is processed. The final color of the pixel is calculated and the RGBA value combined with
the corresponding components resulting from the texture engine. These textured pixels are
modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels
are color blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth
buffer tests are conducted that determine whether the frame and depth buffers will be updated
with the new pixel values.
10.5.5.1
Texture Map Blending
Multiple textures can be blended together in an iterative process and applied to a primitive. The
GMCH allows up to four texture coordinates and texture maps to be specified onto the same
polygon. Also, the GMCH supports using a texture coordinate set to access multiple texture maps.
State variables in multiple texture are bound to texture coordinates, texture map, or texture
blending.
245
Functional Description
10.5.5.2
10.5.5.3
Combining Intrinsic and Specular Color Components
The GMCH allows an independently specified and interpolated “specular RGB” attribute to be
added to the post-texture blended pixel color. This feature provides a full RGB specular highlight
to be applied to a textured surface, permitting a high quality reflective colored lighting effect not
available in devices that apply texture after the lighting components have been combined. If
specular-add state variable is disabled, only the resultant colors from the map blending are used.
If this state variable is enabled, RGB values from the output of the map blending are added to
values for RS, GS, and BS on a component by component basis.
Color Shading Modes
The raster engine supports the flat and Gouraud shading modes. These shading modes are
programmed by the appropriate state variables issued through the command stream.
Flat shading is performed by smoothly interpolating the vertex intrinsic color components (Red,
Green, Blue), Specular Highlights (R,G,B), Fog, and Alpha to the pixel, where each vertex color
has the same value. The setup engine substitutes one of the vertex’s attribute values for the other
two vertices attribute values thereby creating the correct flat shading terms. This condition is set
up by the appropriate state variables issued prior to rendering the primitive.
OpenGL and D3D use a different vertex to select the flat shaded color. This vertex is defined as
the “provoking vertex”. In the case of strips/fans, after the first triangle, attributes on every vertex
that define a primitive are used to select the flat color of the primitive. A state variable is used to
select the “flat color” prior to rendering the primitive.
Gouraud shading is performed by smoothly interpolating the vertex intrinsic color components
(Red, Green, Blue). Specular Highlights (R,G,B), Fog, and Alpha to the pixel, where each vertex
color has a different value.
All the attributes can be selected independently from one of the shading modes by setting the
appropriate value state variables.
10.5.5.4
10.5.5.5
Color Dithering
Color dithering helps to hide color quantization errors. Color dithering takes advantage of the
human eye’s propensity to “average” the colors in a small area. Input color, alpha, and fog
components are converted from 8-bit components to 5- or 6- bit components by dithering.
Dithering is performed on blended textured pixels. In 32-bit mode, dithering is not performed on
the components.
Vertex and Per Pixel Fogging
Fogging is used to create atmospheric effects (such as low visibility conditions in flight simulator-
type games). It adds another level of realism to computer-generated scenes. Fog can be used for
depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer
details (fewer polygons); thereby, improving the rendering speed or frame rate. Fog is simulated
by attenuating the color of an object with the fog color as a function of distance. The higher the
density the lower the visibility for distant objects.
There are two ways to implement the fogging technique: per-vertex (linear) fogging and per-pixel
(non-linear) fogging. The per-vertex method interpolates the fog value at the vertices of a polygon
246
Functional Description
to determine the fog factor at each pixel within the polygon. This method provides realistic
fogging as long as the polygons are small. With large polygons (such as a ground plane depicting
an airport runway), the per-vertex technique results in unnatural fogging.
The GMCH supports both types of fog operations: vertex and per pixel or table fog. If fog is
disabled, the incoming color intensities are passed unchanged to the destination blend unit.
10.5.5.6
Alpha Blending (Frame Buffer)
Alpha blending adds the material property of transparency or opacity to an object. Alpha blending
combines a source pixel color (RS, GS, BS) and alpha (AS) component with a destination pixel
color (RD, GD, BD) and alpha (AD) component. For example, alpha blending could be used
where there is glass surface on top (source) of a red surface (destination) allowing much of the
red base color to show through.
Blending allows the source and destination color values to be multiplied by programmable factors
and then combined via a programmable blend function. The combined and independent selection
of factors and blend functions for color and alpha are supported.
10.5.5.7
10.5.5.8
Microsoft Direct X* API and SGI OpenGL* Logic Ops
Both APIs provide a mode to use bitwise ops in place of alpha blending. This is used for rubber-
banding (i.e., draw a rubber band outline over the scene using an XOR operation). Drawing it
again restores the original image without having to do a potentially expensive redraw.
Color Buffer Formats: 8-, 16-, or 32-bits per Pixel (Destination Alpha)
The raster engine supports 8-bit, 16-bit, and 32-bit color buffer formats. The 8-bit format is used
to support planar YUV420 format, which is used only in motion compensation and arithmetic
stretch format. The bit format of color and Z will be allowed to mix.
The GMCH supports both double and triple buffering, where one buffer is the primary buffer
used for display and one or two are the back buffer(s) used for rendering.
The frame buffer of the GMCH contains at least two hardware buffers: the front buffer (display
buffer) and the back buffer (rendering buffer). While the back buffer may actually coincide with
(or be part of) the visible display surface, a separate (screen or window-sized) back buffer is used
to permit double-buffered drawing. That is, the image being drawn is not visible until the scene is
complete and the back buffer made visible (via an instruction) or copied to the front buffer (via a
2D BLT operation). Rendering to one and displaying from the other remove the possibility of
image tearing. This also speeds up the display process over a single buffer. Additionally, triple
back buffering is also supported. The instruction set of the GMCH provides a variety of controls
for the buffers (e.g., initializing, flip, clear, etc.).
247
Functional Description
10.5.5.9
Depth Buffer
The raster engine will be able to read and write from this buffer and use the data in per fragment
operations that determine whether resultant color and depth value of the pixel for the fragment are
to be updated or not.
Typical applications for entertainment or visual simulations with exterior scenes require far/near
ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can
cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A
24-bit Z-buffer provides 16 million Z-values, as opposed to only 64 K with a 16-bit Z buffer.
With lower Z-resolution, two distant overlapping objects may be assigned the same Z-value. As a
result, the rendering hardware may have a problem resolving the order of the objects, and the
object in the back may appear through the object in the front.
By contrast, when W (or eye-relative Z) is used, the buffer bits can be more evenly allocated
between the near and far clip planes in world space. The key benefit is that the ratio of far and
near is no longer an issue, allowing applications to support a maximum range of miles, yet still get
reasonably accurate depth buffering within inches of the eye point.
The GMCH supports a flexible format for the floating-point W buffer, wherein the number of
exponent bits is programmable. This allows the driver to determine variable precision as a
function of the dynamic range of the W (screen-space Z) parameter.
The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or
24-bit Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit
mode.
10.5.5.10 Stencil Buffer
The raster engine will provide 8-bit stencil buffer storage in 32-bit mode and the ability to
perform stencil testing. Stencil testing controls 3D drawing on a per pixel basis, conditionally
eliminating a pixel on the outcome of a comparison between a stencil reference value and the
value in the stencil buffer at the location of the source pixel being processed. They are typically
used in multipass algorithms to achieve special effects (such as, decals, outlining, shadows and
constructive solid geometry rendering).
10.5.5.11 Projective Textures
The GMCH supports two, simultaneous projective textures at full rate processing, and four
textures at half rate. These textures require three floating point texture coordinates to be included
in the Flexible Vertex Format (FVF). Projective textures enable special effects such as projecting
spot light textures obliquely onto walls, etc.
248
Functional Description
10.5.6
2D Engine
The GMCH contains BLT functionality, and an extensive set of 2D instructions. To take
advantage of the 3D drawing engine’s functionality, some BLT functions (such as, Alpha BLTs,
arithmetic (bilinear) stretch BLTs, rotations, transposing pixel maps, limited color space
conversion, and DIBs) make use of the 3D renderer.
10.5.6.1
10.5.6.2
GMCH VGA Registers
The 2D registers are a combination of registers defined by IBM when the Video Graphics Array
(VGA) was first introduced and others that Intel has added to support graphics modes that have
color depths, resolutions, and hardware acceleration features that go beyond the original VGA
standard.
Logical 128-bit Fixed BLT and 256 Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows*
operating systems. The 128-bit GMCH BLT engine provides hardware acceleration of block
transfers of pixel data for many common Windows operations. The term BLT refers to a block
transfer of pixel data between memory locations. The BLT engine can be used for the following:
Move rectangular blocks of data between memory locations
Data Alignment
Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory locations. The
allowable memory transfers are between: cacheable system memory and frame buffer memory,
frame buffer memory and frame buffer memory, and within system memory. Data to be
transferred can consist of regions of memory, patterns, or solid color fills. A pattern will always
be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel.
The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8, 16, or
32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the
destination. Transparent transfers compare destination color to source color and write according
to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the BLT
overlaps with the source memory location, the GMCH can specify which area in memory to begin
the BLT transfer. Hardware is included for all 256 raster operations (Source, Pattern, and
Destination) defined by Microsoft, including transparent BLT.
The GMCH has instructions to invoke BLT and stretch BLT operations, permitting software to set
up instruction buffers and use batch processing. The GMCH can perform hardware clipping
during BLTs.
249
Functional Description
10.5.7
Video Engine
10.5.7.1
Hardware Motion Compensation
The Motion Compensation (MC) process consists of reconstructing a new picture by predicting
(either forward, backward, or bidirectionally) the resulting pixel colors from one or more
reference pictures. The GMCH receives the video stream and implements motion compensation
and subsequent steps in hardware. Performing motion compensation in hardware reduces the
processor demand of software-based MPEG-2 decoding, and thus improves system performance.
The motion compensation functionality is overloaded onto the texture cache and texture filter.
The texture cache is used to typically access the data in the reconstruction of the frames and the
filter is used in the actual motion compensation process. To support this overloaded functionality
the texture cache additionally supports the following input format:
YUV420 planar
4-Channel MPEG YUV
Improvements allow hardware MC output rate to be quadrupled.
10.5.7.2
Sub-Picture Support
Sub-picture is used for two purposes; one is Subtitles for movie captions, etc. (which are
superimposed on a main picture), and the other is Menus used to provide some visual operation
environments for the user of a content player.
DVD allows movie subtitles to be recorded as Sub-pictures. On a DVD disc, it is called "Subtitle"
because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks
for Subtitles, they can be used for various applications; for example, as Subtitles in different
languages or other information to be displayed.
There are two kinds of menus; the System Menus and other In-Title Menus. First, the System
Menus are displayed and operated at startup of or during the playback of the disc or from the stop
state. Second, In-Title Menus can be programmed as a combination of Sub-picture and Highlight
commands to be displayed during playback of the disc.
The GMCH supports sub-picture for DVD and DBS by mixing the two video streams via alpha
blending. Unlike color keying, alpha blending provides a softer effect and each pixel that is
displayed is a composite between the two video stream pixels. The GMCH can use four methods
when dealing with sub-pictures. This flexibility enables the GMCH to work with all sub- picture
formats.
10.5.8
Planes
A plane consists of a rectangular shaped image that has characteristics such as source, size,
position, method, and format. These planes get attached to source surfaces that are rectangular
memory surfaces with a similar set of characteristics. They are also associated with a particular
destination pipe.
250
Functional Description
10.5.8.1
10.5.8.2
Cursor Plane
The cursor planes are one of the simplest display planes. With a few exceptions, the cursor plan
has a fixed size of 64x64 and a fixed Z-order (top). In legacy modes, cursor can cause the display
data below it to be inverted.
Overlay Plane
The overlay engine provides a method of merging either video capture data (from an external
video capture device) or data delivered by the processor, with the graphics data on the screen. The
source data can be mirrored horizontally or vertically or both.
Source/Destination Color Keying/ChromaKeying
Overlay source/destination ChromaKeying enables blending of the overlay with the underlying
graphics background. Destination color keying/ChromaKeying can be used to handle occluded
portions of the overlay window on a pixel-by-pixel basis that is actually an underlay. Destination
ChromaKeying would only be used for YUV passthrough to TV. Destination color keying
supports a specific color (8- or 15-bit) mode as well as 32-bit alpha blending.
Source color keying/ChromaKeying is used to handle transparency based on the overlay window
on a pixel-by-pixel basis. This is used when “blue screening” an image to overlay the image on a
new background later.
Gamma Correction
To compensate for overlay color intensity loss due to the non-linear response between display
devices, the overlay engine supports independent gamma correction. This allows the overlay data
to be converted to linear data or corrected for the display device when not blending.
YUV-to-RGB Conversion
The format conversion can be bypassed in the case of RGB source data. The format conversion
assumes that the YUV data is input in the 4:4:4 format and uses the full range scale.
Maximum Resolution and Frequency
The maximum frequency supported by the overlay logic is 180 MHz. The maximum resolution is
dependent on a number of variables.
Deinterlacing Support
For display on a progressive computer monitor, interlaced data that has been formatted for display
on interlaced monitors (TV), needs to be de-interlaced. The simple approaches to de-interlacing
create unwanted display artifacts. More advanced de-interlacing techniques have a large cost
associated with them. The compromise solution is to provide a low cost but effective solution and
enable both hardware and software based external solutions. Software based solutions are enabled
through a high bandwidth transfer to system memory and back.
251
Functional Description
10.5.8.3
Advanced Deinterlacing and Dynamic Bob and Weave
Interlaced data that originates from a video camera creates two fields that are temporally offset by
1/60 of a second. There are several schemes to deinterlace the video stream: line replication,
vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the
previous field and inserts them into the current field to construct the frame – this is known as
Weaving. This is the best solution for images with little motion; however, showing a frame that
consists of the two fields will have serration or feathering of moving edges when there is motion
in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest
neighbor. This is the best solution for images with motion; however, it will have reduced spatial
resolution in areas that have no motion and introduces jaggies. In absence of any other
deinterlacing, these form the baseline and are supported by the GMCH.
Scaling Filter and Control
The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel
granularity) for any video source (YUV422 or YUV420) format is supported.
The overlay logic can scale an input image up to 1600X1200 with no major degradation in the
filter used as long as the maximum frequency limitation is met. Display resolution and refresh rate
combinations where the dot clock is greater than the maximum frequency require the overlay to
use pixel replication.
10.5.9
Pipes
The display consists of two pipes. The pipes can operate in a single-wide or “double-wide” mode
at 2x graphics core clock though they are effectively limited by the respective display port. The
display planes and the cursor plane will provide a “double wide” mode to feed the pipe.
10.5.9.1
Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It operates by
converting an input reference frequency into an output frequency. The timing generators take
their input from internal DPLL devices that are programmable to generate pixel clocks in the
range of 25–400 MHz. Accuracy for VESA timing modes is required to be within ±0.5%.
The DPLL can take a reference frequency from the external reference input (DREFCLKN/P) or
the TV clock input (SDVO_TVCLKIN+/-).
10.6
Display Interfaces (Intel® 82945G/82945GC/82945GZ
GMCH Only)
The GMCH has three display ports; one analog and two digital. Each port can transmit data
according to one or more protocols. The digital ports are connected to an external device that
converts one protocol to another. Examples of this are TV encoders, external DACs, LVDS
transmitters, and TMDS transmitters. Each display port has control signals that may be used to
control, configure, and/or determine the capabilities of an external device.
The GMCH has one dedicated display port; the analog port. SDVO ports B and C are multiplexed
with the PCI Express graphics interface and are not available if an external PCI Express graphics
252
Functional Description
device is in use. When a system uses a PCI Express graphics connector, SDVO ports B and C can
be used via an ADD2/ADD2+ (Advanced Digital Display 2) card. Ports B and C can also operate
in dual-channel mode, where the data bus is connected to both display ports, allowing a single
device to take data at twice the pixel rate.
The GMCH’s analog port uses an integrated 400 MHz RAMDAC that can directly drive a
standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit
color at 75 Hz.
The GMCH’s SDVO ports are each capable of driving a 200-MP pixel rate. Each port is
capable of driving a digital display up to 1600x1200 @ 60 Hz. When in dual-channel mode,
the GMCH can drive a flat panel up to 2048x1536 @ 75 Hz or dCRT/HDTV up to
1920x1080 @ 85 Hz.
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant
external device and connector, the GMCH has a high speed interface to a digital display
(e.g., flat panel or digital CRT).
Table 10-7. Display Port Characteristics
Analog
Digital Port B
DVO 1.0
Digital Port C
DVO 1.0
Interface Protocol
RGB DAC
HSYNC
VSYNC
Yes Enable/Polarity
Yes Enable/Polarity
BLANK
No
No
No
No
Yes(1)
Yes
Yes
—
Yes(1)
Yes
Yes
No
STALL
Field
Display_Enable
Image Aspect Ratio
Pixel Aspect Ratio
Voltage
Programmable and typically 1.33:1 or 1.78:1
Square(1)
RGB 0.7 V p-p
NA
PCI Express*
PCI Express
Clock
Differential
Max Rate
400 Mpixel
Analog RGB
DDC1/DDC2B
No
200/400 Mpixel
RGB 8:8:8 YUV 4:4:4
Format
Control Bus
External Device
Connector
DDC2B
TMDS/LVDS Transmitter /TV Encoder
DVI/CVBS/S-Video/Component/SCART
VGA/DVI-I
NOTES:
1.
Single signal software selectable between display enable and Blank#.
10.6.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal.
There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the
analog port. The intended target device is for a CRT based monitor with a VGA connector.
Display devices (such as, LCD panels with analog inputs) may work satisfactorily but no
functionality has been added to the signals to enhance that capability.
253
Functional Description
Table 10-8. Analog Port Characteristics
Signal
Port Characteristic
Support
Voltage Range
Monitor Sense
Analog Copy Protection
Sync on Green
Voltage
0.7 V p-p only
Analog Compare
RGB
No
No
2.5 V
Enable/Disable
Polarity adjust
Composite Sync Support
Special Flat Panel Sync
Stereo Sync
Port control
VGA or port control
HSYNC
VSYNC
No
No
No
Voltage
Externally buffered to 5 V
Through GPIO interface
DDC
Control
10.6.1.1
10.6.1.2
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for the CRT
monitor. The GMCH’s integrated 400 MHz RAMDAC supports resolutions up to 2048 x 1536 @
75 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since
these levels cannot be generated internal to the device, external level shifting buffers are required.
These signals can be polarity adjusted and individually disabled in one of the two possible states.
The sync signals should power up disabled in the high state. No composite sync or special flat
panel sync support will be included.
10.6.1.3
10.6.1.4
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that sets the display mode
using the VGA CRTC registers. Timings are generated based on the VGA register values and the
timing generator registers are not used.
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the host
system and display. Both configuration and control information can be exchanged allowing plug-
and-play systems to be realized. Support for DDC 1 and 2 is implemented. The GMCH uses the
DDC_CLK and DDC_DATA signals to communicate with the analog monitor. The GMCH
generates these signals at 2.5 V. External pull-up resistors and level shifting circuitry should be
implemented on the board.
The GMCH implements a hardware GMBus controller that can be used to control these signals
allowing for transactions speeds up to 400 kHz.
254
Functional Description
10.6.2
Digital Display Interface
The GMCH has several options for driving digital displays. The GMCH contains two SDVO
ports. On the 82945G/82945GC GMCH these ports are multiplexed on the PCI Express interface.
When an external PCI Express graphics accelerator is not present, the GMCH can use the
multiplexed SDVO ports to provide extra digital display options. These additional digital display
capabilities may be provided through an ADD2 card that is designed to plug into a PCI Express
connector.
10.6.2.1
Multiplexed Digital Display Channels – Intel® SDVOB and Intel®
SDVOC
The 82945G/82945GC/82945GZ GMCH has the capability to support digital display devices
through two SDVO ports. For the 82945G/82945GC GMCH, when an external graphics
accelerator is used via the multiplexed PCI Express port, these SDVO ports are not available.
The shared SDVO ports each support a pixel clock up to 200 MHz and can support a variety of
transmission devices. When using a dual-channel external transmitter, it will be possible to pair
the two SDVO ports in dual-channel mode to support a single digital display with higher
resolutions and refresh rates. In this mode, the GMCH is capable of driving the pixel clock up to
400 MHz.
SDVO_CTRLDATA is an open-drain signal that acts as a strap during reset to tell the GMCH
whether the interface is a PCI Express interface or an SDVO interface. When implementing
SDVO, either via ADD2 cards or with a down device, a pull-up is placed on this line to signal to
the GMCH to run in SDVO mode and for proper GMBus operation.
10.6.2.1.1 ADD2/ADD2+ Card
When a 945G/945GC Express chipset platform uses a PCI Express connector, the multiplexed
SDVO ports may be used via an ADD2 card for 945GC and ADD2/ADD2+ card for 945G. The
ADD2/ADD2+ card will be designed to fit a standard PCI Express (x16) connector.
10.6.2.1.2 TMDS Capabilities
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant
external device and connector, the GMCH has a high-speed interface to a digital display
|(e.g., flat panel or digital CRT). When combining the two multiplexed SDVO ports, the GMCH
can drive a flat panel up to 2048x1536 or a dCRT/HDTV up to 1920x1080. Flat Panel is a fixed
resolution display. The GMCH supports panel fitting in the transmitter, receiver, or an external
device, but has no native panel fitting capabilities. The GMCH will, however, provide unscaled
mode where the display is centered on the panel.
10.6.2.1.3 LVDS Capabilities
The GMCH may use the SDVO ports to drive an LVDS transmitter. Flat Panel is a fixed
resolution display. The GMCH supports panel fitting in the transmitter, receiver, or an external
device, but has no native panel fitting capabilities. The GMCH will, however, provide unscaled
mode where the display is centered on the panel. The GMCH supports scaling in the LVDS
transmitter through the SDVO stall input pair.
255
Functional Description
10.6.2.1.4 TV-Out Capabilities
Although traditional TVs are not digital displays, the GMCH uses a digital display channel to
communicate with a TV-Out transmitter. For that reason, the GMCH considers a TV-Output to be
a digital display. The GMCH supports NTSC/PAL/SECAM standard definition formats. The
GMCH generates the proper timing for the external encoder. The external encoder is responsible
for generation of the proper format signal. Since the multiplexed SDVO interface is a
NTSC/PAL/SECAM display, the TV-Out port can be configured to be the boot device. It is
necessary to ensure that appropriate BIOS support is provided.
The TV-Out interface on the GMCH is addressable as a master device. This allows an external
TV encoder device to drive a pixel clock signal on SDVO_TVClk[+/-] that the GMCH uses as a
reference frequency. The frequency of this clock is dependent on the output resolution required.
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV encoder chip.
Care must be taken to allow for support of TV sets with high performance de-interlacers and
progressive scan displays connected to by way of a non-interlaced signal. Timing will be
generated with pixel granularity to allow more overscan ratios to be supported.
Direct YUV from Overlay
When source material is in the YUV format and is destined for a device that can take YUV format
data in, it is desired to send the data without converting it to RGB. This avoids the truncation
errors associated with multiple color conversion steps. The common situation will be that the
overlay source data is in the YUV format and will bypass the conversion to RBG as it is sent to
the TV port directly.
Sync Lock Support
Sync lock to the TV will be accomplished using the external encoders PLL combined with the
display phase detector mechanism. The availability of this feature will be determined by which
external encoder is in use.
Analog Content Protection
Analog content protection will be provided through the external encoder using Macrovision 7.01.
DVD software must verify the presence of a Macrovision TV encoder before playback continues.
Simple attempts to disable the Macrovision operation must be detected.
Connectors
Target TV connectors support includes the CVBS, S-Video, Component, and SCART connectors.
The external TV encoder in use will determine the method of support.
256
Functional Description
10.6.2.1.5 Control Bus
Communication to SDVO registers and if used, ADD2 PROMs and monitor DDCs, are
accomplished by using the SDVO_CTRLDATA and SDVO_CTRLCLK signals through the
SDVO device. These signals run up to 1 MHz and connect directly to the SDVO device. The
SDVO device is then responsible for routing the DDC and PROM data streams to the appropriate
location. Consult SDVO device datasheets for level shifting requirements of these signals.
Intel® SDVO Modes
The GMCH port can be dynamically configured in the Standard, Extended, and Dual Standard
modes. Refer to Section 10.4.2 for details.
10.6.3
Multiple Display Configurations
Microsoft Windows* 2000 and Windows* XP operating systems have enabled support for multi-
monitor display. Since the GMCH has several display ports available for its two pipes, it can
support up to two different images on different display devices. Timings and resolutions for these
two images may be different. The GMCH (see note) supports Intel® Dual Display Clone, Intel
Dual Display Twin, Intel Dual Display Zoom, and Extended Desktop.
Intel Dual Display Clone uses both display pipes to drive the same content, at the same resolution
and color depth to two different displays. This configuration allows for different refresh rates on
each display.
Intel Dual Display Twin uses one of the display pipes to drive the same content, at the same
resolution, color depth, and refresh rates to two different displays.
Intel Dual Display Zoom uses both display pipes to drive different content, at potentially different
resolutions, refresh rates, and color depths to two different displays. This configuration results in
a portion of the primary display to be zoomed in on and displayed on the secondary display.
Extended desktop uses both display pipes to drive different content, at potentially different
resolutions, refresh rates, and color depths to two different displays. This configuration allows for
a larger Windows desktop by using both displays as a work surface.
Note: The 82945G/82945GC GMCH IGD is Not capable of operating in parallel with an external PCI
Express graphics device. The GMCH can, however, work in conjunction with a PCI graphics
adapter. Intel® Extended Desktop and Dual Display Zoom feature is supported with the 82945G
GMCH only. Intel® Dual Display Clone and Dual Display Twin are supported with the 82945G,
82945GC, and the 82945GZ
257
Functional Description
10.7
Power Management
Power management feature List:
ACPI 1.0b support
ACPI S0, S1D, S3 (both Cold and Chipset Hot), S4, S5, C0, and C1. C2, C3, C4 states and
corresponding Enhanced states- S3hot, C2, C3, and C4 are not used in the (G)MCH.
Enhanced power management state transitions for increasing time processor spends in low
power states
Internal Graphics Display Device Control D0, D1, D2, D3
Graphics Adapter States: D0, D3
PCI Express Link States: L0, L0s (82945G/82945GC/82945P/82945PL Only)
10.8
Clocking
The (G)MCH has a total of 5 PLLs providing many times that many internal clocks. The PLLs
are:
Host PLL – This PLL generates the main core clocks in the host clock domain. The Host PLL
can also be used to generate memory and internal graphics core clocks. It uses the Host clock
(HCLKIN) as a reference.
Memory PLL – This PLL can be used to generate memory and internal graphics core clocks,
when not generated by the Host PLL. The memory PLL is not needed in all configurations,
but exists to provide more flexible frequency combinations without an unreasonable VCO
frequency. It uses the Host clock (HCLKIN) as a reference.
PCI Express PLL – This PLL generates all PCI Express related clocks, including the Direct
Media Interface that connects to the ICH7. The PCI Express PLL uses the 100 MHz
(GCLKIN) as a reference.
Display PLL A (82945G/82945GC/82945GZ GMCH Only) – This PLL generates the
internal clocks for Display A. It uses DREFCLK as a reference.
Display PLL B (82945G/82945GC/82945GZ GMCH Only) – This PLL generates the
internal clocks for Display B. It uses DREFCLK as a reference.
258
Functional Description
Figure 10-7 illustrates the various clocks in the 945G Express chipset platform.
Figure 10-7. System Clocking Example
Processor Diff Pair
CPU_1 /
CPU_1#
Processor
CK410
56-Pin SSOP
Processor Diff Pair
Processor Diff Pair
CPU_0 /
CPU_0#
Memory
ITP_SRC7 /
ITP_SRC7 #
ITP
FSB
x16 PCI Express*
PCI Express
DIff Pair
SRC_1 / SRC_1#
SRC_2 / SRC_2#
PCI Express GFX
PCI Express
DIff Pair
PCI Express Slot
(G)MCH
DMI
PCI Express DIff Pair
SRC_3 / SRC_3#
PCI Express DIff Pair
SATA Diff Pair
SRC_5 / SRC_5#
SRC_4 / SRC_4#
PCI Express
LAN
SRC_6 / SRC_6#
DOT 96 MHz Diff Pair
USB 48 MHz
DOT_96 / DOT_96#
USB_48 / USB_48#
REF 14 MHz
REF 0
REF 14 MHz
REF 33 MHz
SIO LPC
AC 97
Intel® ICH7
REF 14 MHz
AC 97 Bit Clock
PCIF_1
PCI 33 MHz
LCI Bit Clock
LAN
25 MHz Xtal
PCI 33 MHz
PCI 33 MHz
TPM LPC
OSC
PCIF_2
PCI 33 MHz
FWH LPC
24 MHz
Intel® High
Definition Audio
PCI 33 MHz
PCI 33 MHz
PCI 33 MHz
32.768 kHz
PCI_5
PCI_4
PCI_3
PCI_2
PCI Slot
PCI Slot
PCI 33 MHz
PCI 33 MHz
PCI 33 MHz
PCI_1
PCI_0
Sys_Clocking
§
259
Functional Description
260
Electrical Characteristics
11 Electrical Characteristics
This chapter contains the (G)MCH absolute maximum electrical ratings, power dissipation values,
and DC characteristics.
Note: References to SDVO apply to the 82945G/82945GC/82945GZ GMCH only.
Note: References to 1066 MHz FSB apply to the 82945G/82945P only.
Note: References to DDR2-667 apply to the 82945G/82945GC/82945P only.
Note: References to the PCI Express Interface applies to the 82945G/82945GC/82945P/82945PL only.
11.1
Absolute Minimum and Maximum Ratings
Table 11-1 specifies the (G)MCH’s absolute maximum and minimum ratings. Within functional
operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-
term reliability can be expected. Moreover, if a device is subjected to these conditions for any
length of time, then, when returned to conditions within the functional operating condition limits,
it will either not function, or its reliability will be severely degraded.
Although the (G)MCH contains protective circuitry to resist damage from static electric
discharge, precautions should always be taken to avoid high static voltages or electric fields.
261
Electrical Characteristics
Table 11-1. Absolute Minimum and Maximum Ratings
Symbol
Tstorage
Parameter
Storage Temperature
Min
Max
Unit
Notes
-55
150
C
1
(G)MCH Core
VCC
1.5 V Core Supply Voltage with respect to VSS
-0.3
1.65
V
Host Interface (533 MHz/800 MHz/1066 MHz) (1066 MHz on 82945G/82945P (G)MCH Only)
VTT
System Bus Input Voltage with respect to VSS
-0.3
-0.3
1.65
1.65
V
V
VCCA_HPLL
1.5 V Host PLL Analog Supply Voltage with
respect to VSS
DDR2 Interface (533 MHz/667 MHz) (667 MHz on 82945G/82945GC/82945P (G)MCH Only)
VCCSM
1.8 V DDR2 System Memory Supply Voltage
with respect to VSS
-0.3
-0.3
4.0
V
V
VCCA_SMPLL
1.5 V System Memory PLL Analog Supply
Voltage with respect to VSS
1.65
PCI Express*/SDVO/DMI Interface
VCC_EXP
1.5 V PCI Express* and DMI Supply Voltage
with respect to VSS
-0.3
-0.3
1.65
1.65
V
V
VCCA_EXPPLL
1.5 V PCI Express PLL Analog Supply Voltage
with respect to VSS
RGB/CRT DAC Display Interface (8 bit) (82945G/82945GC/82945GZ GMCH Only)
VCCA_DAC
2.5 V Display DAC Analog Supply Voltage with
respect to VSS
-0.3
-0.3
-0.3
2.65
1.65
1.65
V
V
V
VCCA_DPLLA
VCCA_DPLLB
1.5 V Display PLL A Analog Supply Voltage with
respect to VSS
1.5 V Display PLL B Analog Supply Voltage with
respect to VSS
CMOS Interface
VCC2
2.5 V CMOS Supply Voltage with respect to VSS
-0.3
2.65
V
NOTES:
1. Possible damage to the (G)MCH may occur if the (G)MCH temperature exceeds 150 °C. Intel does not
warrant functionality for parts that have exceeded temperatures above 150 °C since this exceeds Intel’s
specification.
262
Electrical Characteristics
11.1.1
Power Characteristics
Table 11-2. Non Memory Power Characteristics
Symbol
IVTT
Parameter
Signal Names
Min
Max
Unit
Notes
System Bus Supply Current
VTT
—
—
—
—
—
—
—
0.9
13.8
8.9
1.5
70
A
A
1, 4,5
IVCC
1.5 V Core Supply Current (Integrated)
1.5 V Core Supply Current (Discrete)
1.5 V PCI Express and DMI Supply Current
2.5 V Display DAC Analog Supply Current
2.5 V CMOS Supply Current
VCC
2,3,4,5
IVCC
VCC
A
2,3,4,5
IVCC_EXP
IVCCA_DAC
IVCC2
VCC_EXP
VCCA_DAC
VCC2
A
5
5
5
5
mA
mA
mA
2.0
45
IVCCA_EXPPLL
1.5 V PCI Express and DMI PLL Analog
Supply Current
VCCA_EXPPLL
IVCCA_HPLL
IVCCA_DPLLA
IVCCA_DPLLB
1.5 V Host PLL Supply Current
VCCA_HPLL
VCCA_DPLLA
VCCA_DPLLB
—
—
45
55
mA
mA
5
5
1.5 V Display PLL A and PLL B Supply
Current (82945G/82945GC/82945GZ
GMCH Only)
NOTES:
1. Estimate is only for maximum current coming through (G)MCH supply balls.
2. Rail includes DLLs and FSB sense amps.
3. Includes worst case leakage.
4. Calculated for highest frequencies.
5. Icc_max values are determined on a per-interface basis. Maximum currents cannot occur simultaneously on
all interfaces.
Table 11-3. DDR2 Power Characteristics
Symbol
Parameter
Min
Max
Uni
t
Notes
IVCCSM
ISUS_VCCSM
ISMVREF
DDR2 System Memory Interface (1.8 V) Supply Current
—
—
—
4.0
25
2
A
1,2,3
DDR2 System Memory Interface (1.8 V) Standby Supply Current
mA
mA
1
1
DDR2 System Memory Interface Reference Voltage (0.90 V)
Supply Current
ISUS_SMVREF
DDR2 System Memory Interface Reference Voltage (0.90 V)
Standby Supply Current
—
—
—
—
10
36
10
66
µA
mA
µA
1
1
1
1
ITTRC
DDR2 System Memory Interface Resister Compensation
Voltage (1.8 V) Supply Current
ISUS_TTRC
DDR2 System Memory Interface Resister Compensation
Voltage (1.8 V) Standby Supply Current
IVCCA_SMPLL
System Memory PLL Analog (1.5 V) Supply Current
mA
NOTES:
1. Estimate is only for max current coming through (G)MCH supply balls
2. Calculated for highest frequencies
3. Icc_max values are determined on a per-interface basis. Maximum currents cannot occur simultaneously on
all interfaces.
263
Electrical Characteristics
11.2
Signal Groups
The signal description includes the type of buffer used for the particular signal:
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification
for complete details. The (G)MCH integrates most GTL+ termination
resistors.
DDR2
DDR2 System memory (1.8 V CMOS buffers)
PCI Express/SDVO
PCI Express interface signals. These signals are compatible with PCI
Express 1.0a signaling environment AC specifications. The buffers are
not 3.3 V tolerant.
Analog
Ref
Analog signal interface
Voltage reference signal
HVCMOS
SSTL-1.8
2.5 V Tolerant High Voltage CMOS buffers
1.8 V Tolerant Stub Series Termination Logic
Table 11-4. Signal Groups
Signal
Group
Signal Type
Signals
Notes
Host Interface Signal Groups
(a)
(b)
GTL+
HADS#, HBNR#, HBREQ0#, HDBSY#, HDRDY#,
HDINV[3:0]#, HA[31:3]#, HADSTB[1:0]#, HD[63:0],
HDSTBP[3:0]#, HDSTBN[3:0]#, HHIT#, HHITM#,
HREQ[4:0]#, HLOCK#
Input/Outputs
GTL+
HBPRI#, HCPURST#, HDEFER#, HTRDY#, HRS[2:0]#,
HEDRDY#
Common Clock
Outputs
(c)
(d)
Asynchronous GTL+
Input
HPCREQ#
Analog Host Interface
Reference and
Compensation
Signals
HDVREF, HACCVREF, HSWING HRCOMP, HSCOMP
(c1)
Miscellaneous CMOS
Inputs
BSEL[2:0]
264
Electrical Characteristics
Signal
Group
Signal Type
Signals
Notes
PCI-Express* Graphics and Intel® SDVO Interface Signal Groups
(e)
PCI Express*/
PCI Express Interface
Intel SDVO Input
(82945G/82945GC/82945P/82945PL Only):
EXP_RXN[15:0], EXP_RXP[15:0]
SDVO Interface (82945G/82945GC/82945GZ GMCH Only):
SDVO_TVCLKIN+, SDVO_TVCLKIN-, SDVOB_INT+,
SDVOB_INT-, SDVO_STALL+, SDVO_STALL-,
SDVOC_INT+, SDVOC_INT-
(f)
PCI Express/
SDVO Output
PCI Express Interface
(82945G/82945GC/82945P/82945PL Only):
EXP_TXN[15:0], EXP_TXP[15:0]
SDVO Interface (82945G/82945GC/82945GZ GMCH Only):
SDVOB_RED+, SDVOB_RED-, SDVOB_GREEN+,
SDVOB_GREEN-, SDVOB_BLUE+, SDVOB_BLUE-,
SDVOB_CLK+, SDVOB_CLK-,
SDVOC_RED+/SDVOB_ALPHA+, SDVOC_RED-
/SDVOB_ALPHA-, SDVOC_GREEN+, SDVOC_GREEN-,
SDVOC_BLUE+, SDVOC_BLUE-, SDVOC_CLK+,
SDVOC_CLK-
(g)
Analog
EXP_COMPO
EXP_COMPI
PCI Express/SDVO
Interface
Compensation
Signals
DDR2 Interface Signal Groups
(h)
SSTL – 1.8
DDR2 CMOS I/O
SSTL – 1.8
SDQ_A[63:0], SDQ_B[63:0], SDQS_A[7:0], SDQS_A[7:0]#,
SDQS_B[7:0], SDQS_B[7:0]#
(i)
SDM_A[7:0], SDM_B[7:0], SMA_A[13:0], SMA_B[13:0]
SBS_A[2:0], SBS_B[2:0], SRAS_A#, SRAS_B#, SCAS_A#,
SCAS_B#, SWE_A#, SWE_B#, SODT_A[3:0],
SODT_B[3:0], SCKE_A[3:0], SCKE_B[3:0], SCS_A[3:0]#,
SCS_B[3:0]#, SCLK_A[5:0], SCLK_A[5:0]#, SCLK_B[5:0],
SCLK_B[5:0]#
DDR2 CMOS Output
(j)
DDR2 Reference
Voltage
SMVREF[1:0]
RGB/CRT DAC Display Signal Groups (82945G/82945GC/82945GZ GMCH Only)
Analog Current
Outputs
RED, RED#, GREEN, GREEN#, BLUE, BLUE#
Analog/Ref DAC
Miscellaneous
REFSET
1
HVCMOS Type
HSYNC, VSYNC
Clocks, Reset, and Miscellaneous Signal Groups
(k) HVCMOS Input EXTTS#
265
Electrical Characteristics
Signal
Group
Signal Type
Signals
Notes
(l)
Miscellaneous Inputs
RSTIN#, PWROK
ICH_SYNC#
Miscellaneous
HVCMOS Output
(m)
(n)
Low Voltage Diff.
Clock Input
HCLKN, HCLKP, DREFCLKP, DREFCLKN, GCLKP,
GCLKN
HVCMOS I/O
(82945G/82945GC
SDVO_CRTLCLK, SDVO_CTRLDATA, DDC_CLK,
DDC_DATA
/8
2945GZ GMCH Only)
I/O Buffer Supply Voltages
(o)
(p)
System Bus Input
Supply Voltage
VTT
1.5 V SDVO, PCI
Express Supply
Voltages
VCC_EXP
(q)
(r)
1.8 V DDR2 Supply
Voltage
VCCSM
1.5 V DDR2 PLL
Analog Supply
Voltage
VCC_SMPLL
(s)
(t)
1.5 V (G)MCH Core
Supply Voltage
VCC
2.5 V CMOS Supply
Voltage
VCC2
(u)
2.5 V RGB/CRT DAC
Display Analog
VCCA_DAC
Supply Voltage
(v)
PLL Analog Supply
Voltages
VCCA_HPLL, VCCA_EXPPLL, VCCA_DPLLA,
VCCA_DPLLB
NOTE:
1.
Current Mode Reference pin. DC Specification not required
266
Electrical Characteristics
11.3
DC Characteristics
Table 11-5. DC Characteristics
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
I/O Buffer Supply Voltage (AC Noise not included unless noted)
VCCSM
(q)
(r)
DDR2 I/O Supply Voltage
1.7
1.8
1.5
1.9
V
V
4
VCCA_SMPLL
DDR2 I/O PLL Analog Supply
Voltage
1.425
1.575
VCC_EXP
VTT
(p)
(o)
SDVO, PCI-Express Supply
Voltage
1.425
1.14
1.5
1.2
1.575
1.26
V
V
System Bus Input Supply
Voltage
VCC
(s)
(t)
GMCH Core Supply Voltage
CMOS Supply Voltage
1.425
2.375
2.375
1.5
2.5
2.5
1.575
2.625
2.625
V
V
V
11
VCC2
VCCA_DAC
(u)
CRT Display DAC Supply
Voltage
VCCA_HPLL,
VCCA_EXPPLL
,
(v)
Various PLLs’ Analog Supply
Voltages
1.425
1.5
1.575
V
VCCA_DPLLA,
VCCA_DPLLB
Reference Voltages
HVREF
(d)
Host Address, Data, and
Common Clock Signal
Reference Voltage
0.63 x VTT –2% 0.63 x VTT
0.63 x VTT +2%
V
HSWING
(d)
(j)
Host Compensation Reference 0.22 x VTT –2% 0.22 x VTT
Voltage
0.22 x VTT+2%
0.51 x VCCSM
V
V
SMVREF
DDR2 Reference Voltage
0.49 x VCCSM 0.50 x VCCSM
Host Interface
VIL_H
VIH_H
(a, c, c1) Host GTL+ Input Low Voltage
(a, c, c1) Host GTL+ Input High Voltage
-0.10
0
(0.63 x VTT) – 0.1
VTT +0.1
V
V
(0.63 x
VTT
V
TT)+0.1
VOL_H
VOH_H
IOL_H
(a, b) Host GTL+ Output Low
Voltage
—
—
—
—
—
(0.22 x VTT)+0.1
VTT
V
V
(a, b) Host GTL+ Output High
Voltage
VTT – 0.1
(a, b) Host GTL+ Output Low
Current
—
—
VTTmax *(1–0.22) / mA Rttmin = 54
Rttmin
ILEAK_H
(a, c, c1) Host GTL+ Input Leakage
Current
20
A
VOL<Vpad<
VTT
267
Electrical Characteristics
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
CPAD
(a, c, c1) Host GTL+ Input Capacitance
2
—
—
2.5
2.5
pF
pF
CPCKG
(a, c, c1) Host GTL+ Input Capacitance
(common clock)
0.90
DDR2 Interface
VIL(DC)
VIH(DC)
(h)
(h)
DDR2 Input Low Voltage
DDR2 Input High Voltage
—
—
—
SMVREF – 0.125
—
V
V
SMVREF +
0.125
VIL(AC)
VIH(AC)
(h)
(h)
DDR2 Input Low Voltage
DDR2 Input High Voltage
—
—
—
SMVREF – 0.250
—
V
V
SMVREF +
0.250
VOL
VOH
ILeak
ILeak
CI/O
(h, i)
(h, i)
(h)
DDR2 Output Low Voltage
DDR2 Output High Voltage
Input Leakage Current
Input Leakage Current
—
1.5
—
—
—
—
—
—
0.3
—
V
1
1
5
6
V
±20
±550
6.0
µA
µA
pF
(h)
—
(h, i)
DDR2 Input/Output Pin
Capacitance
3.0
1.5V PCI Express* Interface 1.0a (includes PCI Express and SDVO)
VTX-DIFF P-P
VTX_CM-ACp
ZTX-DIFF-DC
VRX-DIFF p-p
VRX_CM-ACp
(f)
(f)
Differential Peak to Peak
Output Voltage
0.800
—
—
—
1.2
20
V
2
AC Peak Common Mode
Output Voltage
mV
(f)
DC Differential TX Impedance
80
100
—
120
1.2
150
Ohm
s
(e)
(e)
Differential Peak to Peak Input
Voltage
0.175
—
V
3
AC Peak Common Mode Input
Voltage
—
mV
Clocks, Reset, and Miscellaneous Signals
VIL
(k)
(k)
Input Low Voltage
—
—
—
0.8
—
V
V
VIH
Input High Voltage
Input Leakage Current
Input Capacitance
2.0
ILEAK
(k)
—
20
A
CIN
(k)
3.0
—
6.0
—
pF
V
VIL
(m)
(m)
(m)
(m)
Input Low Voltage
- 0.150
0.660
0.250
0
VIH
Input High Voltage
Absolute Crossing Point
Relative Crossing Point
0.700
—
0.850
0.550
V
VCROSS(abs)
VCROSS(rel)
V
7, 9
8, 9
0.250 + 0.5 *
—
0.550 + 0.5 *
V
(VHavg – 0.700)
(VHavg – 0.770)
∆VCROSS
(m)
Range of Crossing Points
—
—
0.140
V
10
268
Electrical Characteristics
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
CIN
(m)
(n)
Input Capacitance
1
—
—
3
pF
V
VOL
Output Low Voltage (CMOS
Outputs)
—
0.4
VOH
(n)
(n)
(n)
Output High Voltage (CMOS
Outputs)
2.1
—
-1
—
—
—
—
1
V
IOL
Output Low Current (CMOS
Outputs)
mA
@VOL_HI
max
IOH
Output High Current (CMOS
Outputs)
—
mA @VOH_HI min
VIL
(n)
(n)
(n)
(n)
(l)
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Input Low Voltage
Input High Voltage
Input Leakage Current
—
1.4
—
—
—
—
—
—
—
—
1.1
—
V
V
VIH
ILEAK
CIN
VIL
± 20
6.0
A
3.0
—
pF
V
0.8
VIH
(l)
2.0
—
—
V
ILEAK
(l)
±100
A
0<Vin<VCC
3_3
CIN
(l)
Input Capacitance
4.690
—
5.370
pF
NOTES:
1. Determined with 2x GMCH DDR2 Buffer Strength Settings into a 50
to 0.5xVCCSM test load.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter
compliance eye diagram of PCI Express specification and measured over any 250 consecutive TX Uls.
3. Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown in
Receiver compliance eye diagram of PCI Express specification should be used as the RX device when
taking measurements.
4. This is the DC voltage supplied at the (G)MCH and is inclusive of all noise up to 20 MHz. Any noise above
20 MHz at the (G)MCH generated from any source other than the (G)MCH itself may not exceed the DC
voltage range of 1.8 V ±100 mV.
5. Applies to the pin to VCC or VSS leakage current for the SDQ_A[63:0]# and SDQ_B[63:0]# signals.
6. Applies to the pin-to-pin leakage current between the SDQS_A[7:0], SDQS_A[7:0]#, SDQS_B[7:0]#, and
SDQS_B[7:0]# signals.
7. Crossing Voltage is defined as the instantaneous voltage value when the rising edge is equal to the falling
edge.
8. VHavg is the statistical average of the VH measured by the oscilloscope.
9. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
10. ∆VCROSS is defined as the total variation of all crossing voltages as defined in note 7.
11. For all noise components ≤ 20 MHz, the sum of the DC voltage and AC noise component must be within
the specified DC min/max operating range.
269
Electrical Characteristics
11.3.1
RGB/CRT DAC Display DC Characteristics (Intel®
82945G/82945GC/82945GZ GMCH Only)
Table 11-6. RGB/CRT DAC Display DC Characteristics: Functional Operating Range
(VCCA_DAC = 2.5 V 5%)
Typica
Parameter
DAC Resolution
Min
Max
Units
Notes
l
8
—
—
Bits
V
1
1, 2, 4 (white video
level voltage)
Max Luminance (full-scale)
Min Luminance
0.665
0.700
0.000
0.770
1, 3, 4 (black video
level voltage)
—
—
V
LSB Current
—
73.2
—
—
A
4, 5
1, 6
1, 6
Integral Linearity (INL)
Differential Linearity (DNL)
-1.0
-1.0
+1.0
+1.0
LSB
LSB
—
Video channel-channel voltage amplitude
mismatch
—
—
6
%
7
Monotonicity
Ensured
NOTES:
1. Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of Analog
Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Maximum steady-state amplitude
3. Minimum steady-state amplitude
4. Defined for a double 75-
5. Set by external reference resistor value.
termination.
6. INL and DNL measured and calculated according to VESA Video Signal Standards.
7.
Max full-scale voltage difference among R, G, B outputs (percentage of steady-state full-scale voltage).
§
270
Ballout and Package Information
12 Ballout and Package Information
This chapter provides the ballout and package information.
12.1
Ballout
Figure 12-1 through Figure 12-3 show the GMCH ballout for platforms using DDR2 system
memory, as viewed from the top side of the package.
Note: Balls that are listed as RSV are reserved. Board traces should Not be routed to these balls.
Note: Some balls marked as reserved (RSV) are used in XOR testing. See Chapter 0 for details.
Note: Some balls marked as reserved (RSV) can be used as test points. These are marked as RSV_TPx.
Note: Balls that are listed as NC are No Connects.
271
Ballout and Package Information
Figure 12-1. Intel® 82945G GMCH Ballout Diagram (Top View – Columns 43–30)
43
NC
NC
42
41
40
39
38
37
36
35
34
33
32
31
30
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
NC
VCCSM
SODT_A3
SCS_B0#
SMA_A13
VCCSM
VCCSM
SWE_A#
SCS_A2#
SBS_A0
VCCSM
VCCSM
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
VCCSM
VSS
VSS
VSS
SCS_A0#
SCAS_A#
SODT_A2
SODT_A0
VSS
VSS
SCLK_A0 SCLK_A3#
SMA_A2
SMA_A3
SMA_A4
SCS_B2#
VCCSM
SCS_B1#
SCS_A1#
SODT_A1
SRAS_A#
SBS_A1
VCCSM
SMA_A0
SCLK_A3
VCCSM
SODT_B0
SMA_B13
VCCSM
SDQ_A45
SCS_A3#
SMA_A10 SCLK_A0#
SMA_A1
SDQ_A36
VSS
SCS_B3#
SODT_B1
SODT_B3
VCCSM
VCCSM
VCCSM
SDQ_B39
VSS
SODT_B2
SDQ_A34
SDQ_B45
SDQS_A4# SDQ_A33
SDQ_A44
SDQ_A40
SDQ_A35
SDQ_A39
SDQS_A4
VSS
SDM_A4
SDQ_A38
VSS
SDQ_A37
VSS
VSS
SDQ_A42
VSS
SDQ_A41
SDQS_A5
VSS
VSS
SDM_B5
VSS
VSS
SDQ_B44
SDQ_B40
SDQ_B34
SDQ_B38
VSS
SDQ_A46 SDQS_A5#
SDQ_A47
SDM_A5
SDQ_B41
SDQS_B5
VSS
SDQ_A32
SDQ_B42
VSS
SDQ_A53
SDQ_A49
SDQ_A52
SDQ_A48
SDQ_A43
VSS
RSV
SDQ_B46
SCLK_B2
VSS
VSS
SDQS_B5# SDQ_B47
SDQ_B35
SDQ_B52
SCLK_B2# SDQ_B43
SDQ_B48
VSS
VSS
SCLK_A2 SCLK_A2#
RSV
VSS
VSS
SDM_B6
SCLK_B5
VSS
SCLK_B5#
VSS
SDQ_B49
VSS
SDQ_B53
VSS
SCLK_A5#
VSS
VSS
SCLK_A5
SDM_A6
SDQS_A6 SDQS_A6#
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B54
SDQ_B60
SDQS_B6
SDQ_B51
VSS
VSS
SDQS_B6#
SDQ_B50
VSS
RSV
VSS
VCC
SDQ_A55
SDQ_A60
VSS
SDQ_A54
SDQ_A61
SDQ_A50
SDQ_B61
SDQ_A51
SDQ_A56
SDM_A7
SDQ_A57
VSS
SDM_B7
VSS
SDQS_B7#
VSS
VSS
VSS
SDQS_B7
VSS
VSS
SDQ_B57
RSV
VSS
SDQ_B55
SDQ_B56
RSV
VSS
RSV
RSV
SDQS_A7 SDQS_A7#
SDQ_B63
SDQ_B62
SDQ_A63
RSV
SDQ_A62
HBREQ0#
SDQ_A59
HEDRDY#
HTRDY#
SDQ_A58
VSS
RSV
HA29#
VSS
VSS
RSV
VSS
RSV
VSS
RSV
SDQ_B59
SDQ_B58
VSS
VSS
RSV
RSV
HRS1#
VSS
VSS
HA28#
HA27#
HA31#
W
HADS#
HA25#
HDBSY#
VSS
HHITM#
HDRDY#
HHIT#
W
V
VSS
VSS
VSS
VSS
VSS
VSS
HADSTB1#
HA26#
VSS
HA22#
VSS
HA30#
HA24#
RSV
VSS
RSV
RSV
V
U
HLOCK#
HRS0#
HBNR#
HA19#
HA23#
U
T
HRS2#
T
R
VSS
HA21#
VSS
HA18#
HA20#
VSS
HA10#
HA17#
HA11#
VSS
VSS
VSS
R
P
HD2
HA14#
HD3
HD0
HD4
HD7
HDEFER#
P
N
VSS
HDSTBN0#
VSS
VSS
HD1
HA16#
HA13#
HA15#
VSS
VSS
HA9#
VSS
HA12#
HA8#
VSS
VSS
HCLKP
VSS
N
M
HD5
HD6
HADSTB0#
HD33
M
L
VSS
HD30
VSS
L
K
HD8
HDSTBP0# HDINV0#
HD10
VSS
HA4#
VSS
VSS
HREQ2#
HA6#
HD18
VSS
HD27
HD34
HD31
HD32
VSS
K
J
HA5#
HA3#
HA7#
HD25
VSS
J
H
HD23
H
G
HD11
VSS
HD13
HD12
HD14
HD50
HD9
VSS
HREQ3#
HD16
VSS
HDSTBP1#
NC
HDSTBN1#
VSS
VSS
G
F
HD15
VSS
HPCREQ#
HD29
VSS
HD37
HD48
F
E
HREQ4#
HBPRI#
NC
HREQ0#
HREQ1#
HD20
HD17
HDSTBP3#
HD56
E
D
HD19
HD52
HD21
HD53
HD51
HD54
HD61
HD60
HDINV3#
HD63
HCPURST#
HD62
D
C
VSS
HD22
VSS
40
HD24
HD55
HD26
VSS
35
HD57
HD59
HD58
VSS
31
C
B
NC
RSV
43
NC
NC
VSS
HDINV1#
38
HDSTBN3#
HD28
VSS
HD49
33
B
A
NC
A
42
41
39
37
36
34
32
30
272
Ballout and Package Information
Figure 12-2. Intel® 82945G GMCH Ballout Diagram (Top View – Columns 29–16)
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
SMA_A6
VCCSM
VCCSM
SMA_A12
SBS_A2
SCKE_A2
VCCSM
VCCSM
SMA_B0
SMA_B4
VCCSM
VCCSM
SMA_B9
SMA_B7
RSV
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
SMA_A9
SMA_A5
SMA_A7
SMA_A11
NC
SCKE_A0
SCKE_A3
SCKE_A1
SWE_B#
SMA_B1
SMA_B2
SMA_B3
VCCSM
VCCSM
VSS
VSS
SMA_B11
SMA_B12
SBS_B2
RSV
VCCSM
SRAS_B# SMA_B10
SBS_B1
SBS_B0
VCCSM
SMA_B8
SMA_B5
SMA_A8
SCAS_B#
VCCSM
SDQ_B26
VSS
SMA_B6
VCCSM
SDQ_A26
VSS
SCKE_B1
VCCSM
SDQS_B4#
VSS
NC
NC
RSV
VCCSM
SDQS_A3
VSS
VSS
SDQ_B32
VSS
VSS
SDQS_B3
VSS
VSS
SDQS_B4
SDM_B4
VSS
VSS
SDQ_B31
VSS
VSS
SDQ_A31
VSS
VSS
SDQ_B37
SDQ_B36
VSS
SCLK_B3#
SCLK_B3
VSS
SDQS_B3#
SDM_B3
VSS
SDQ_B29
SDQ_B28
VSS
SDQS_A3#
SDM_A3
VSS
SDQ_A29
SDQ_A28
VSS
SDQ_B30
VSS
SDQ_A30
VSS
SDQ_B33
SCLK_B0
RSV
SCLK_B0#
VSS
SDQ_B27
RSV
SDQ_B24
VSS
SDQ_B25
VSS
SDQ_A27
VSS
SDQ_A24
RSV
SDQ_A25
VSS
SDQ_B19
RSV_TP1
RSV_TP0
VCC
VSS
RSV
VSS
VSS
RSV_TP2
RSV
RSV
VCC
RSV_TP3
VCC
RSV
RSV
RSV
RSV
RSV
VCC
RSV
VCC
RSV
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VCC
RSV
RSV
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
RSV
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
W
W
V
VSS
VSS
V
U
U
T
T
R
VSS
VSS
RSV
VSS
VSS
VSS
VCC
VSS
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R
P
P
N
VSS
VSS
VSS
VSS
RSV_TP6
VSS
DDC_CLK1
VSS
DDC_DATA1
ICH_SYNC#
RSV_TP5
ALLZTEST
BLUE#1
BLUE1
VCC
N
M
HCLKN
VSS
HD35
HD40
VSS
HDSTBN2#
VSS
HD41
VSS
VCC
M
L
RSV_TP4
EXP_SLR
VSS
BSEL2
VSS
VSS
L
K
HD36
VSS
HD43
HD42
VSS
HD46
VSS
GREEN1
GREEN#1
VSS
K
J
HDSTBP2#
VSS
EXTTS#
XORTEST
VSS
J
H
HD38
VSS
HD45
VSS
BSEL1
VSS
H
G
VSS
HD44
VSS
VSS
RED#1
RED1
VSS
G
F
HD39
HDINV2#
VTT
HD47
VTT
BSEL0
VSS
EXP_EN
VSS
VSS
F
E
VTT
VTT
VSS
E
HACCVRE
F
D
C
HDVREF
HSCOMP
HSWING
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VCC2
HSYNC1
VSYNC1
VSS
D
C
VCCA_
HPLL
VCCA_
DPLLA1
VTT
VTT
VSS
VSS
VCCA_DAC
VCCA_DAC
VCCA_
SMPLL
VCCA_
DPLLB1
VCCA_
EXPPLL
B
A
VSS
VTT
VSS
GCLKN
B
A
HRCOMP
28
VSS
26
VTT
24
VSS
22
REFSET1
20
VSSA_DAC
18
VSS
16
29
27
25
23
21
19
17
NOTES:
1.
This analog display signal ball is reserved (RSV) on the 82945P/82945PL MCH component.
273
Ballout and Package Information
Figure 12-3. Intel® 82945G GMCH Ballout Diagram (Top View – Columns 15–1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
NC
1
BC
BB
BA
AY
AW
VCCSM
SCKE_B3
SCKE_B2
SDQ_A22
VSS
VSS
SDQ_A14
VSS
VSS
NC
NC
BC
BB
BA
AY
AW
VSS
SCKE_B0
RSV
SDQ_A19
SDQ_A18
SDQ_A23
SDQ_A16
SDQ_B10
VSS
SDM_A2
SDQ_A21
SDQ_A11
SDQ_A10
SDQ_A15
SDM_B1
SDQS_B1
SDQ_B8
SCLK_A1# SDQS_A1#
VSS
NC
SDQS_A2# SDQ_A20
SDQ_A17
SCLK_A4#
SCLK_A1
VSS
SDQS_A1
SDQ_A9
SDQ_A8
NC
SDQS_A2
SCLK_A4
SDM_A1
NC
VSS
VCCSM
VCCSM
SDQS_B2
VSS
VSS
VSS
SCLK_B1#
SCLK_B1
VSS
SDQ_A13
SDQ_A3
AV SDQ_B18
AU VSS
AT SDQ_B23
AR VSS
AP SDQ_B22
AN VSS
AM SDQ_B16
SDQ_B9
VSS
VSS
SDQ_A12 AV
SCLK_B4
SCLK_B4#
SDQ_A6
SDQS_A0
SDQ_A2
SDQ_A7
AU
AT
SDQS_B2#
SDQ_B21
SDM_B2
VSS
VSS
SDQ_B14
VSS
SDQ_B15 SDQS_B1#
SDQ_B13
VSS
VSS
SDQ_B12
VSS
SDM_A0
SDQ_A0
SDQS_A0#
SDQ_A1
VSS
VSS
SDQ_A4
VSS
AR
AP
AN
AM
AL
VSS
SDQ_B3
SDQ_B2
SDQ_B7
SDQ_A5
VSS
SDQ_B20
SDQ_B17
VSS
SDQ_B11
SDM_B0
SDQ_B6
VSS
VSS
SDQS_B0
SDQ_B1
VSS
VSS
SDQS_B0#
SDQ_B0
VSS
SMVREF0 SOCOMP1 SMVREF1
AL
AK
AJ
VSS
VCC
VCC
VSS
SDQ_B5
SRCOMP0
VSS
VCC
VSS
VCC
VCC
VCC
VCC
AK
AJ
VCC
RSTIN#
SDQ_B4
VSS
PWROK
SOCOMP0
VSS
SRCOMP1
VCC
AH
AG
AF
AE
AD
VCC
VCC
VCC
VCC
VSS
VCC
VSS
AH
AG
AF
AE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC_EXP VCC_EXP VCC_EXP
VCC
VCC
VCC
VSS
VSS
VCC_EXP
VSS
VCC_EXP
VSS
VSS
VCC_EXP
VSS
VSS
VCC_EXP VCC_EXP VCC_EXP
VCC_EXP VCC_EXP DMI_TXN3
VCC_EXP VCC_EXP AD
EXP_
COMPO
EXP_
COMPI
AC
VCC_EXP
DMI_RXP3 DMI_RXN3
VSS
VSS
AC
AB
AA
DMI_TXP3
VSS
VSS
DMI_TXN1 AB
AA
VCC
VCC
VSS
VSS
VCC_EXP
VCC_EXP
VSS
VSS
VSS
DMI_RXN1 DMI_RXP1
VSS
DMI_RXN2 DMI_RXP2 VCC_EXP DMI_TXN2
DMI_TXP1
EXP_
RXN15
EXP_
VSS
Y
DMI_RXN0 DMI_RXP0
VSS
VSS
DMI_TXP2
VSS
DMI_TXN0
Y
RXP15
W
V
EXP_TXN15
VSS
DMI_TXP0
VSS
W
V
VCC
VCC
VSS
VSS
VCC_EXP
VCC_EXP
VSS
VSS
VSS
VCC_EXP VCC_EXP
VSS
VCC_EXP VCC_EXP VCC_EXP
EXP_TXP15
EXP_TXN14
EXP_
RXP12
EXP_
VSS
U
T
VCC_EXP VCC_EXP VCC_EXP
VSS
EXP_TXN13
EXP_TXP13
VSS
EXP_TXP14
VSS
U
T
RXN12
EXP_TXN12
EXP_TXN11
EXP_
RXP13
EXP_
RXN13
R
VCC
VSS
VSS
RSV
RSV
VSS
VSS
VSS
VCC_EXP
VSS
VCC_EXP VCC_EXP
VSS
VSS
VSS
VCC_EXP
R
EXP_
RXP14
P
N
M
L
VSS
EXP_TXP12
VSS
P
N
M
L
EXP_
RXN14
VSS
VSS
VSS
VSS
VCC_EXP VCC_EXP VCC_EXP VCC_EXP
VSS
VSS
VCC_EXP
VCC_EXP
VSS
EXP_
RXN10
EXP_
RXP10
RSV
VSS
VSS
EXP_TXN10
EXP_TXP10
EXP_TXN9
VSS
EXP_TXP11
VSS
EXP_
RXN11
VSS
VSS
EXP_
RXP11
K
VSS
EXP_RXP8 EXP_RXN8
EXP_RXP4
VSS
VSS
VSS
VSS
VSS
VSS
K
J
DREFCLKP
DREFCLKN
VSS
EXP_RXP2
EXP_RXN2
VSS
VSS
VSS
VSS
EXP_RXN4
VSS
EXP_RXN7
EXP_TXP9
VSS
EXP_TXN8
J
H
G
H
G
EXP_RXP0
VSS
VSS
EXP_RXP7
VSS
VSS
EXP_RXN9
EXP_RXP9
VSS
EXP_TXP8
VSS
SDVO_
F
E
VSS
VSS
EXP_RXN0
VSS
EXP_RXN3 EXP_RXN5
EXP_RXP5
EXP_TXN7
VSS
F
E
CTRLDATA1
SDVO_
EXP_RXP3
VSS
VSS
VSS
VSS
VSS
EXP_TXP7
CTRLCLK1
D
C
B
A
EXP_TXP0
VSS
EXP_RXN1 EXP_RXP1
VSS
EXP_TXP5 EXP_TXN5
VSS
VSS
VSS
EXP_RXN6
VSS
VSS
NC
D
C
B
A
EXP_TXN0
VSS
EXP_TXP3 EXP_TXN3
EXP_RXP6
GCLKP
EXP_TXN1
VSS
EXP_TXP2
11
EXP_TXN2
VSS
EXP_TXP4
9
EXP_TXN4
VSS
EXP_TXP6
6
EXP_TXN6
VSS
VSS
4
NC
NC
EXP_TXP1
13
15
14
12
10
8
7
5
3
2
1
NOTES:
1.
This analog display signal ball is reserved on the 82945P/82945PL MCH component.
274
Ballout and Package Information
12.2
Ballout Table
Table 12-1 lists the Intel® 82945G/82945GC/82945GZ GMCH and Intel® 82945P/82945PL MCH
ballout in alphabetical order by signal name.
Table 12-1. Intel® 82945G//82945GZ/82945GC/82945P/82945PL (G)MCH Ballout Sorted by
Signal Name
Intel® 82945GZ
(82945GC) GMCH Signal
Name
Intel® 82945P
/82945PL MCH Signal
Name
Intel® 82945G GMCH
Signal Name
Ball #
ALLZTEST
BLUE
ALLZTEST
BLUE
ALLZTEST
RSV
K18
H18
J18
BLUE#
BLUE#
RSV
BSEL0
BSEL0
BSEL0
F21
H21
L20
N20
N18
Y8
BSEL1
BSEL1
BSEL1
BSEL2
BSEL2
BSEL2
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
EXP_EN
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
RSV (EXP_COMPI)
RSV (EXP_COMP0)
EXP_EN
RSV
RSV
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
EXP_EN
AA10
AA7
AC8
Y7
AA9
AA6
AC9
Y1
AB1
AA4
AC4
W2
AA2
Y4
AB3
H15
J15
AC11
AC12
F20
F12
D12
EXP_RXN0
EXP_RXN1
RSV (EXP_RXN0)
RSV (EXP_RXN1)
EXP_RXN0
EXP_RXN1
275
Ballout and Package Information
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
RSV (EXP_RXN2)
RSV (EXP_RXN3)
RSV (EXP_RXN4)
RSV (EXP_RXN5)
RSV (EXP_RXN6)
RSV (EXP_RXN7)
RSV (EXP_RXN8)
RSV (EXP_RXN9)
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
H13
F10
H10
F9
D3
J6
K8
G4
SDVOC_INT-
(EXP_RXN10/
SDVOC_INT-)
EXP_RXN10/
SDVOC_INT-
EXP_RXN10
M7
EXP_RXN11
EXP_RXN12
RSV (EXP_RXN11)
RSV (EXP_RXN12)
EXP_RXN11
EXP_RXN12
L1
U10
SDVO_STALL-
(EXP_RXN13/
SDVO_STALL-)
EXP_RXN13/
SDVO_STALL-
EXP_RXN13
EXP_RXN14
EXP_RXN15
R7
SDVOB_INT-
(EXP_RXN14/
SDVOB_INT-)
EXP_RXN14/
SDVOB_INT-
N3
SDVO_TVCLKIN-
(EXP_RXN15/
SDVO_TVCLKIN-)
EXP_RXN15/
SDVO_TVCLKIN-
Y11
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
RSV (EXP_RXP0)
RSV (EXP_RXP1)
RSV (EXP_RXP2)
RSV (EXP_RXP3)
RSV (EXP_RXP4)
RSV (EXP_RXP5)
RSV (EXP_RXP6)
RSV (EXP_RXP7)
RSV (EXP_RXP8)
RSV (EXP_RXP9)
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
G12
D11
J13
E10
J9
F7
C4
G6
K9
F4
SDVOC_INT+
(EXP_RXP10/
SDVOC_INT+)
EXP_RXP10/
SDVOC_INT+
EXP_RXP10
M6
EXP_RXP11
EXP_RXP12
RSV (EXP_RXP11)
RSV (EXP_RXP12)
EXP_RXP11
EXP_RXP12
K2
U11
SDVO_STALL+
(EXP_RXP13/
SDVO_STALL+)
EXP_RXP13/
SDVO_STALL+
EXP_RXP13
EXP_RXP14
EXP_RXP15
R8
SDVOB_INT+
(EXP_RXP14/
SDVOB_INT+)
EXP_RXP14/
SDVOB_INT+
P4
SDVO_TVCLKIN+
(EXP_RXP15/
SDVO_TVCLKIN+)
EXP_RXP15/
SDVO_TVCLKIN+
Y10
276
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
EXP_SLR
EXP_SLR
EXP_SLR
K21
C13
B12
B10
C9
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
RSV (EXP_TXN0)
RSV (EXP_TXN1)
RSV (EXP_TXN2)
RSV (EXP_TXN3)
RSV (EXP_TXN4)
RSV (EXP_TXN5)
RSV (EXP_TXN6)
RSV (EXP_TXN7)
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
B7
D6
B5
F1
SDVOC_CLK-
(EXP_TXN8/
SDVOC_CLK-
EXP_TXN8/
SDVOC_CLK-
EXP_TXN8
EXP_TXN9
EXP_TXN10
J1
SDVOC_BLUE-
(EXP_TXN9/
SDVOC_BLUE-)
EXP_TXN9/
SDVOC_BLUE-
K4
M4
SDVOC_GREEN-
(EXP_TXN10/
SDVOC_GREEN-)
EXP_TXN10/
SDVOC_GREEN-
SDVOC_RED-/
SDVOB_ALPHA-
(EXP_TXN11/
EXP_TXN11/
EXP_TXN11
N1
SDVOC_RED-/
SDVOB_ALPHA-
SDVOC_RED-/
SDVOB_ALPHA-)
SDVOB_CLK-
(EXP_TXN12/
SDVOB_CLK-)
EXP_TXN12/
SDVOB_CLK-
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
T1
SDVOB_BLUE-
(EXP_TXN13/
SDVOB_BLUE-)
EXP_TXN13/
SDVOB_BLUE-
U4
V1
W4
SDVOB_GREEN-
(EXP_TXN14/
SDVOB_GREEN-)
EXP_TXN14/
SDVOB_GREEN-
SDVOB_RED-
(EXP_TXN15/
SDVOB_RED-)
EXP_TXN15/
SDVOB_RED-
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
RSV (EXP_TXP0)
RSV (EXP_TXP1)
RSV (EXP_TXP2)
RSV (EXP_TXP3)
RSV (EXP_TXP4)
RSV (EXP_TXP5)
RSV (EXP_TXP6)
RSV (EXP_TXP7)
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
D14
A13
A11
C10
A9
D7
A6
E2
SDVOC_CLK+
(EXP_TXP8/
SDVOC_CLK+)
EXP_TXP8/
SDVOC_CLK+
EXP_TXP8
G2
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
277
Ballout and Package Information
SDVOC_BLUE+
(EXP_TXP9/
SDVOC_BLUE+)
EXP_TXP9/
SDVOC_BLUE+
EXP_TXP9
J3
L4
SDVOC_GREEN+
(EXP_TXP10/
SDVOC_GREEN+)
EXP_TXP10/
SDVOC_GREEN+
EXP_TXP10
SDVOC_RED+/
SDVOB_ALPHA+
(EXP_TXP11/
EXP_TXP11/
EXP_TXP11
M2
SDVOC_RED+/
SDVOB_ALPHA+
SDVOC_RED+/
SDVOB_ALPHA+)
SDVOB_CLK+
(EXP_TXP12/
SDVOB_CLK+)
EXP_TXP12/
SDVOB_CLK+
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
P2
T4
U2
V3
SDVOB_BLUE+
(EXP_TXP13/
SDVOB_BLUE+)
EXP_TXP13/
SDVOB_BLUE+
SDVOB_GREEN+
(EXP_TXP14/
SDVOB_GREEN+)
EXP_TXP14/
SDVOB_GREEN+
SDVOB_RED+
(EXP_TXP15/
SDVOB_RED+)
EXP_TXP15/
SDVOB_RED+
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
EXTTS#
GCLKN
GCLKP
RSV
J20
B16
B14
K17
J17
RSV
HA3#
J39
HA4#
HA4#
HA4#
K38
J42
HA5#
HA5#
HA5#
HA6#
HA6#
HA6#
K35
J37
HA7#
HA7#
HA7#
HA8#
HA8#
HA8#
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
HA9#
HA9#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
278
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HACCVREF
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HACCVREF
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
R38
V33
U34
U32
V42
U35
Y36
Y38
AA37
V32
Y34
HACCVREF
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
D28
W42
M36
V35
U39
D42
AA41
M29
M31
C30
P41
M39
P42
M42
N41
M40
L40
HD1
HD1
HD1
HD2
HD2
HD2
HD3
HD3
HD3
HD4
HD4
HD4
HD5
HD5
HD5
HD6
HD6
HD6
HD7
HD7
HD7
M41
K42
G39
J41
HD8
HD8
HD8
HD9
HD9
HD9
HD10
HD10
HD10
HD11
HD11
HD11
G42
G40
G41
F40
F43
F37
E37
J35
HD12
HD12
HD12
HD13
HD13
HD13
HD14
HD14
HD14
HD15
HD15
HD15
HD16
HD16
HD16
HD17
HD17
HD17
HD18
HD18
HD18
HD19
HD19
HD19
D39
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
279
Ballout and Package Information
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
280
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
HD61
HD61
HD61
D32
B30
D30
U42
HD62
HD62
HD62
HD63
HD63
HD63
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HDVREF
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HDVREF
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HDVREF
HEDRDY#
HHIT#
P40
K40
A38
E29
B32
V41
L43
G34
M26
B37
K41
F35
J27
E34
D27
Y40
U41
W41
U40
F38
A28
E41
D41
K36
G37
E42
T40
Y43
T43
C27
B27
D17
W40
M18
BC43
BC42
BC2
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS1#
HRS1#
HRS2#
HRS2#
HRS2#
HSCOMP
HSWING
HSYNC
HSCOMP
HSWING
HSYNC
HSCOMP
HSWING
RSV
HTRDY#
ICH_SYNC#
NC
HTRDY#
ICH_SYNC#
NC
HTRDY#
ICH_SYNC#
NC
NC
NC
NC
NC
NC
NC
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
281
Ballout and Package Information
NC
NC
NC
BC1
BB43
BB2
BB1
BA2
AW26
AW2
AV27
AV26
E35
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C42
NC
NC
NC
C2
NC
NC
NC
B43
NC
NC
NC
B42
NC
NC
NC
B41
NC
NC
NC
B3
NC
NC
NC
B2
NC
NC
NC
A42
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RSV
RSV
RSV
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
AJ9
F17
G17
A20
AJ12
V30
AG29
AJ29
AK27
AL26
AJ21
AL20
AL29
AJ26
AJ23
AK21
AC30
AA30
V31
U30
AD31
AF31
Y33
282
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
Y30
RSV
RSV
AC34
AD30
BC16
AY14
AW18
AW17
AL39
AK40
AJ27
AJ24
AG27
AG26
AG25
M11
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
A43
RSV
RSV
R27
RSV
RSV
U27
RSV
RSV
M15
RSV
RSV
L15
RSV
RSV
AA38
AA34
AA42
AA35
RSV
RSV
RSV
RSV
RSV
RSV
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
RSV_TP4
RSV_TP5
RSV_TP6
SBS_A0
SBS_A1
SBS_A2
SBS_B0
SBS_B1
SBS_B2
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
RSV_TP4
RSV_TP5
RSV_TP6
SBS_A0
SBS_A1
SBS_A2
SBS_B0
SBS_B1
SBS_B2
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
RSV_TP4
RSV_TP5
RSV_TP6
SBS_A0
AK17
AL17
AK23
AK18
L21
L18
N21
BC33
AY34
BA26
AW23
AY23
AY17
BA37
AY24
BB25
AY25
SBS_A1
SBS_A2
SBS_B0
SBS_B1
SBS_B2
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
283
Ballout and Package Information
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
BC24
BA25
BA14
AY16
BA13
BB13
BB32
AY32
AY5
BB5
AK42
AK41
BA31
BB31
AY6
BA5
AH40
AH43
AM29
AM27
AV9
AW9
AL38
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
BB37
BA39
BA35
AY38
BA40
AW41
BA41
AW40
AR3
SDM_A1
SDM_A1
SDM_A1
AY2
SDM_A2
SDM_A2
SDM_A2
BB10
284
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
AP18
AT34
AP39
AG40
AC40
AL11
AW7
AP13
AP23
AR29
AR38
AJ39
AD39
AP3
AP2
AU3
AV4
AN1
AP4
AU5
AU2
AW3
AY3
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
BA7
BB7
AV1
AW4
BC6
AY7
AW12
AY10
BA12
BB12
BA9
BB9
BC11
AY12
AM20
AM18
AV20
AM21
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
285
Ballout and Package Information
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
AP17
AR17
AP20
AT20
AP32
AV34
AV38
AU39
AV32
AT32
AR34
AU37
AR41
AR42
AN43
AM40
AU41
AU42
AP41
AN40
AL41
AL42
AF39
AE40
AM41
AM42
AF41
AF42
AD40
AD43
AA39
AA40
AE42
AE41
AB41
AB42
AL6
SDQ_B1
SDQ_B1
SDQ_B1
AL8
SDQ_B2
SDQ_B2
SDQ_B2
AP8
SDQ_B3
SDQ_B3
SDQ_B3
AP9
SDQ_B4
SDQ_B4
SDQ_B4
AJ11
286
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
SDQ_B5
SDQ_B5
SDQ_B5
SDQ_B6
SDQ_B7
SDQ_B8
SDQ_B9
AL9
SDQ_B6
SDQ_B6
AM10
AP6
AU7
AV6
SDQ_B7
SDQ_B7
SDQ_B8
SDQ_B8
SDQ_B9
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
AV12
AM11
AR5
AR7
AR12
AR10
AM15
AM13
AV15
AM17
AN12
AR13
AP15
AT15
AM24
AM23
AV24
AM26
AP21
AR21
AP24
AT24
AU27
AN29
AR31
AM31
AP27
AR27
AP31
AU31
AP35
AP37
AN32
AL35
AR35
AU38
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
287
Ballout and Package Information
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
AM38
AM34
AL34
AJ34
AF32
AF34
AL31
AJ32
AG35
AD32
AC32
AD34
Y32
AA32
AF35
AF37
AC33
AC35
AU4
AR2
BA3
BB4
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
AM8
AM6
AV7
AR9
AV13
AT13
AU23
288
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SDVO_CTRLCLK
SDVO_CTRLDATA
SMVREF0
SMVREF1
SMA_A0
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SDVO_CTRLCLK
SDVO_CTRLDATA
SMVREF0
SMVREF1
SMA_A0
SDQS_B3#
AR23
AT29
AV29
AP36
AM35
AG34
AG32
AD36
AD38
E15
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
RSV
RSV
F15
SMVREF0
SMVREF1
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
AM4
AM2
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
BB22
BB21
BA21
AY21
BC20
AY19
AY20
BA18
BA19
BB18
BA22
BB17
BA17
AW42
SMA_A1
SMA_A1
SMA_A2
SMA_A2
SMA_A3
SMA_A3
SMA_A4
SMA_A4
SMA_A5
SMA_A5
SMA_A6
SMA_A6
SMA_A7
SMA_A7
SMA_A8
SMA_A8
SMA_A9
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B1
SMA_B2
SMA_B2
SMA_B3
SMA_B3
SMA_B4
SMA_B4
SMA_B5
SMA_B5
SMA_B6
SMA_B6
SMA_B7
SMA_B7
SMA_B8
SMA_B8
SMA_B9
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SMA_B10
SMA_B11
SMA_B12
SMA_B13
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
289
Ballout and Package Information
SOCOMP0
SOCOMP1
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SWE_A#
SWE_B#
VCC
SOCOMP0
SOCOMP1
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SWE_A#
SWE_B#
VCC
SOCOMP0
SOCOMP1
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SWE_A#
SWE_B#
VCC
AJ8
AM3
AW37
AY39
AY37
BB40
AY42
AV40
AV43
AU40
BA34
BA23
AL5
AJ6
BB35
BB23
AJ20
AJ18
AJ17
AJ15
AG24
AG23
AG22
AG21
AG20
AG19
AG18
AG17
AG15
AF29
AF27
AF26
AF25
AF23
AF21
AF19
AF17
AF15
AE27
AE26
AE24
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
290
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AE22
AE20
AE18
AE17
AD26
AD25
AD23
AD21
AD19
AD17
AD15
AC27
AC26
AC24
AC20
AC18
AC17
AC15
AB27
AB26
AB25
AB24
AB20
AB19
AB18
AB17
AA26
AA24
AA20
AA19
AA18
AA17
AA15
Y27
Y25
Y23
Y21
Y19
Y18
Y17
Y15
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
291
Ballout and Package Information
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W27
W26
W24
W22
W20
W19
W18
W17
V27
V25
V23
V22
V21
V20
V19
V18
V17
V15
U26
U25
U24
U23
U22
U21
U20
U19
U18
U17
U15
R24
R23
R21
R20
R18
R17
R15
AK20
AK15
AK14
AK4
AK3
292
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AK2
AJ14
AJ13
AJ5
AH4
AH2
AH1
AG14
AG13
AG12
AG11
AG10
AG9
AG8
AG7
AG6
AG5
AG4
AG3
AG2
AF30
AF14
AF13
AF12
AF11
AF10
AF9
AF8
AF7
AF6
AD14
AC22
AB23
AB22
AB21
AA22
P21
P20
P18
P17
N17
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
293
Ballout and Package Information
VCC
VCC
VCC
M17
AE4
AE3
AE2
AD12
AD10
AD8
AD6
AD5
AD4
AD2
AD1
AC13
AC6
AC5
AA13
AA5
Y13
V13
V10
V9
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
V7
V6
V5
U13
U8
U7
U6
R13
R11
R10
R5
N12
N11
N10
N9
N7
N5
D19
C18
B18
VCCA_DAC
VCCA_DAC
VCCA_DAC
VCCA_DAC
VCCA_DAC
VCCA_DAC
294
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
RSV
RSV
C19
B19
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
B17
C21
B20
BC40
AY43
BC35
BC31
BC26
BC22
BC18
BC13
BB42
BB38
BB33
BB28
BB24
BB20
BB16
AY41
AW35
AW34
AW31
AW29
AW24
AW21
AW20
AW15
AW13
AV42
AV31
AV23
AV21
AV18
BC4
VSS
VSS
VSS
AY1
VSS
VSS
VSS
AF24
AF22
AF20
AF18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
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VSS
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VSS
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VSS
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VSS
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VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE25
AE23
AE21
AE19
AD29
AD27
AD24
AD22
AD20
AD18
AC29
AC25
AC19
AA29
AA27
AA25
Y29
Y26
Y24
Y22
Y20
W25
W23
W21
V29
V26
V24
U29
R29
R26
D43
D1
A40
A4
BC9
BB41
BB39
BB34
BB19
BB14
BB11
296
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
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VSS
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VSS
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VSS
VSS
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VSS
VSS
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VSS
VSS
VSS
VSS
VSS
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VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BB6
BB3
BA42
BA4
AW10
AV37
AV17
AV10
AV2
AU34
AU32
AU29
AU26
AU24
AU21
AU20
AU17
AU15
AU13
AU12
AU9
AU6
AT31
AT27
AT26
AT23
AT21
AT18
AT17
AT12
AR43
AR39
AR37
AR32
AR24
AR20
AR15
AR6
AR1
AP38
AP34
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
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VSS
VSS
VSS
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VSS
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VSS
VSS
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VSS
VSS
VSS
VSS
VSS
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VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP29
AP12
AP10
AP7
AP5
AN42
AN31
AN27
AN26
AN24
AN23
AN21
AN20
AN18
AN17
AN15
AN13
AN4
AN2
AM39
AM37
AM36
AM33
AM9
AM7
AM5
AL43
AL37
AL33
AL32
AL27
AL24
AL23
AL21
AL18
AL15
AL13
AL12
AL10
AL7
AL3
298
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL2
AL1
AK30
AK29
AK26
AK24
AJ37
AJ35
AJ33
AJ31
AJ30
AJ10
AJ7
AH42
AG39
AG38
AG37
AG36
AG33
AG31
AG30
AF43
AF38
AF36
AF33
AF5
AF3
AF2
AF1
AD42
AD37
AD35
AD33
AD13
AD11
AD9
AD7
AC39
AC38
AC37
AC36
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
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VSS
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VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC31
AC23
AC21
AC14
AC10
AC7
AC3
AC2
AB43
AB2
AA36
AA33
AA31
AA23
AA21
AA14
AA12
AA11
AA8
AA3
Y42
Y39
Y37
Y35
Y31
Y14
Y12
Y9
Y6
Y5
Y2
W3
V43
V39
V38
V37
V36
V34
V14
V12
V11
300
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
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VSS
VSS
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VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V8
V2
U38
U36
U33
U31
U14
U12
U9
U5
U3
T42
T2
R39
R37
R34
R31
R30
R14
R12
R9
R6
P30
P29
P27
P26
P24
P15
P14
P3
N43
N39
N36
N33
N31
N29
N27
N26
N24
N15
N13
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N8
N6
N2
M37
M35
M21
M20
M13
M10
M9
M8
M5
M3
L42
L31
L29
L26
L24
L13
L12
L2
K39
K37
K34
K32
K27
K20
K15
K13
K12
K10
K7
K6
K5
K3
J43
J38
J29
J24
J21
J12
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
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VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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VSS
VSS
VSS
VSS
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J10
J7
J5
J2
H32
H27
H26
H17
H12
G38
G35
G32
G31
G29
G27
G24
G21
G20
G18
G15
G13
G10
G9
G7
G5
G3
F42
F34
F26
F18
F13
F6
F2
E32
E21
E20
E18
E17
E13
E12
E9
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VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
RSV
VTT
VTT
VTT
VTT
VTT
VTT
VTT
E7
E4
E3
D21
D20
D16
D10
D5
D2
C40
C22
C14
C12
C7
C5
C3
B38
B33
B28
B22
B21
B13
B11
B9
B6
B4
A35
A31
A26
A22
A16
L17
A18
C17
P23
N23
M23
L23
K23
J23
H23
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
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VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
XORTEST
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
XORTEST
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
G23
F27
F23
E27
E26
E24
E23
D25
D24
D23
C26
C25
C23
B26
B25
B24
B23
A24
XORTEST
H20
§
12.3
Package
The (G)MCH package measures 34 mm × 34 mm. The 1202 balls are located in a non-grid
pattern. The package dimensions are shown in Figure 12-4.
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
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307
Testability
13 Testability
In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been
implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin
connected to it.
13.1
Complimentary Pins
Table 13-1 contains pins that must remain complimentary while performing XOR testing. The
first and third column contain the pin and its compliment. The second and fourth column specify
which chain the associated pins are on.
Table 13-1. Complimentary Pins to Drive
Complimentary Pin
XOR Chain
Complimentary Pin
XOR Chain
SDQS_A0
SDQS_A1
SDQS_A2
SDQS A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
Not in XOR Chain
SDQS_A0#
SDQS_A1#
SDQS_A2#
SDQS_A3#
SDQS_A4#
SDQS_A5#
SDQS_A6#
SDQS_A7#
SDQS_B0#
SDQS_B1#
SDQS_B2#
SDQS_B3#
SDQS_B4#
SDQS_B5#
SDQS_B6#
SDQS_B7#
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
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Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Testability
13.2
XOR Test Mode Initialization
XOR test mode can be entered by pulling a Reserved ball (ball V30) and XORTEST (ball H20)
low through the de-assertion of external reset (RSTIN# at ball AJ12). It was intended that no
clocks should be required to enter this test mode; however, it is recommended that customers use
the following sequence.
On power up, hold PWROK (ball AJ9), RSTIN# (ball AJ12), and a Reserved ball (ball V30) low
and start external clocks. After a few clock cycles, pull PWROK high. After ~3–4 clocks, de-
assert RSTIN# (pull it high). Release the Reserved ball (ball V30) and XORTEST. No external
drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains. Refer to
Figure 13-1.
Figure 13-1. XOR Test Mode Initialization Cycles
32 clocks
PWROK
~3-4 Clocks
XORTEST
Don’t Care
Reserved Ball V30
Don’t Care
RSTIN#
Start XOR testing
XOR_Chain_Tim
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
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Testability
13.3
XOR Chain Definition
The (G)MCH chipset has 10 XOR chains. The XOR chain outputs are driven out on the following
output pins. During fullwidth testing, XOR chain outputs will be visible on both pins.
Table 13-2. XOR Chain Outputs
XOR Chain
Output Pins
Coordinate Location
xor_out0
xor_out1
xor_out2
xor_out3
xor_out4
xor_out5
xor_out6
xor_out7
xor_out8
xor_out9
BSEL2
ALLZTEST
XORTEST
RSV_TP5
EXP_SLR
RSV_TP4
EXP_EN
RSV_TP6
BSEL1
L20
K18
H20
L18
K21
L21
F20
N21
H21
F21
BSEL0
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Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Testability
13.4
XOR Chains
Table 13-3 through Table 13-12 show the XOR chains. Section 13.5 has a pin exclusion list.
Table 13-3. XOR Chain 0 Table 13-3. XOR Chain 0
Pin Count
Ball #
Signal Name
Pin Count
Ball #
Signal Name
1
M11
N18
E15
F15
N20
M18
J20
RSV_TP71
DDC_DATA1
SDVO_CTRLCLK1
SDVO_CTRLDATA1
DDC_CLK1
ICH_SYNC#
EXTTS#
HD42#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
C32
D33
C34
E34
B37
D30
D38
E31
E40
D34
C35
D37
B34
A38
B39
F32
H34
J32
HD60#
HD54#
2
3
HD57#
4
HDSTBP3#
HDSTBN3#
HD63#
5
6
7
HD53#
8
J26
HD48#
9
M24
F24
G26
K26
H24
M27
L27
J27
HD41#
HD50#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
HD47#
HD56#
HD44#
HD55#
HD43#
HD51#
HD45#
HD28#
HD35#
HDINV1#
HD21#
HD40#
HDSTBP2#
HDSTBN2#
HD46#
HD29#
M26
K24
C30
H29
H31
K31
F31
K29
M33
E29
F29
B31
B32
C39
A33
B30
D32
C31
HD23#
HD25#
HCPURST#
HD38#
C37
E37
F35
G34
B35
B40
J31
HD24#
HD17#
HD32#
HDSTBP1#
HDSTBN1#
HD26#
HD34#
HD37#
HD36#
HD22#
HD33#
HD31#
HDINV2#
HD39#
D39
J34
HD19#
HD27#
HD58#
C41
L32
J35
HD20#
HDINV3#
HD52#
HD30#
HD18#
HD49#
F37
F43
K41
G41
HD16#
HD62#
HD15#
HD61#
HDSTBP0#
HD13#
HD59#
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
311
Testability
Table 13-3. XOR Chain 0
Table 13-4. XOR Chain 1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
E42
N42
M38
R33
M34
N32
N38
N35
F38
T43
T40
U41
V41
W41
W42
U40
Y43
U39
W40
R32
U37
R36
U35
R35
U34
R38
AA41
Y34
V35
V33
U32
V42
V32
Y36
Y38
AA37
HREQ4#
HAB14#
HAB13#
HAB10#
HAB8#
Pin Count
Ball #
Signal Name
69
70
71
72
73
74
75
76
77
78
79
80
L40
M39
D41
K38
J42
HD6#
HD1#
HREQ1#
HAB4#
HAB11#
HAB16#
HAB9#
HAB5#
K35
N34
N37
P40
U42
Y40
D42
HAB6#
HAB12#
HAB15#
HDEFER#
HDBSY#
HEDRDY#
HBPRI#
HPCREQ#
HRS2#
HRS0#
HHIT#
HDRDY#
HHITM#
HADS#
NOTES:
1.
Intel® 82945G/82945GC/82945GZ
GMCH Only.
HLOCK#
HRS1#
HBNR#
Table 13-4. XOR Chain 1
HTRDY#
HAB17#
HAB19#
HAB18#
HAB26#
HAB20#
HAB23#
HAB21#
HBREQ0#
HAB31#
HADSTB1#
HAB22#
HAB24#
HAB25#
HAB30#
HAB27#
HAB28#
HAB29#
Pin Count
Ball #
Signal Name
1
2
G42
F40
K42
G40
L43
G39
P42
M42
M41
P41
N41
M40
K40
J41
HD11#
HD14#
HD8#
3
4
HD12#
HDSTBN0#
HD9#
5
6
7
HD2#
8
HD3#
9
HD7#
10
11
12
13
14
15
16
17
18
19
20
HD0#
HD4#
HD5#
HDINV0#
HD10#
HREQ3#
HAB3#
HREQ2#
HADSTB0#
HREQ0#
HAB7#
G37
J39
K36
M36
E41
J37
312
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Testability
Table 13-5. XOR Chain 2
Table 13-6. XOR Chain 3
Pin Count
Ball #
Signal Name
Pin Count
Ball #
Signal Name
1
AC40
AB41
AA39
AB42
AD40
AE41
AE42
AA40
AD43
AM42
AL41
AF42
AE40
AF39
AH43
AK42
AR42
AP41
AN40
AP39
AM40
BB40
AW37
AY38
AV38
AT34
AV32
BC33
BB37
BA39
BB35
AY34
BA35
AY28
BA30
BB26
AY32
AW27
AY25
SDM_A7
SDQ_A62
SDQ_A58
SDQ_A63
SDQ_A56
SDQ_A61
SDQ_A60
SDQ_A59
SDQ_A57
SDQ_A53
SDQ_A48
SDQ_A55
SDQ_A51
SDQ_A50
SCLK_A5#
SCLK_A2
SDQ_A41
SDQ_A46
SDQ_A47
SDM_A5
1
AD34
Y32
SDQ_B57
SDQ_B58
SDQ_B62
SDQ_B59
SDQ_B56
SDM_B7
2
2
3
3
AC33
AA32
AC32
AD39
AF37
BB23
AC35
AF35
AL36
AF32
AL34
AJ34
AD32
AL31
BA41
AW41
AU40
AV40
AM38
AL35
AP35
AR35
AW42
AR31
AU27
AU31
AR26
BA22
BA17
AY21
AY20
AM26
AM24
AP21
BA14
BA13
4
4
5
5
6
6
7
7
SDQ_B61
SWE_B#
8
8
9
9
SDQ_B63
SDQ_B60
SCLK_B2#
SDQ_B50
SDQ_B48
SDQ_B49
SDQ_B55
SDQ_B52
SCS_B2#
SCS_B1#
SODT_B3
SODT_B1
SDQ_B46
SDQ_B43
SDQ_B40
SDQ_B44
SMA_B13
SDQ_B34
SDQ_B32
SDQ_B39
SCLK_B3#
SMA_B10
SMA_B12
SMA_B3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SDQ_A43
SODT_A3
SODT_A0
SCS_A3#
SDQ_A34
SDM_A4
SDQ_A36
SBS_A0
SCS_A0#
SCS_A1#
SWE_A#
SBS_A1
SCS_A2#
SMA_A8
SMA_B6
SDQ_B27
SDQ_B24
SDQ_B28
SCKE_B0
SCKE_B2
SMA_A3
SMA_A12
SCLK_A0#
SMA_A11
SCKE_A1
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
313
Testability
Table 13-6. XOR Chain 3
Table 13-7. XOR Chain 4
Pin Count
Ball #
Signal Name
Pin Count
Ball #
Signal Name
39
40
41
42
AT15
AM17
AR13
AV9
SDQ_B23
SDQ_B19
SDQ_B21
SCLK_B1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
AR17
AM20
BA10
BA12
BB12
BB10
AY6
SDQ_A29
SDQ_A24
SDQS_A2#
SDQ_A18
SDQ_A19
SDM_A2
Table 13-7. XOR Chain 4
SCLK_A4
SCLK_A1#
SDQ_A14
SDQ_A10
SDQ_A8
BB5
Pin Count
Ball #
Signal Name
BC6
1
AC41
AG41
AM41
AG40
AL42
AF41
AH40
AK41
AP40
AN43
AU41
AU42
AR41
AY39
AY37
AV35
AU39
AT32
AV34
BA34
BB31
BC38
BC28
BB27
BA27
AY27
BB25
AR18
AM21
AM18
SDQS_A7#
SDQS_A6#
SDQ_A52
SDM_A6
BA7
2
AW3
AY2
3
SDM_A1
4
BB4
SDQS_A1#
SDQS_A0#
RSV_TP0
SDQ_A5
5
SDQ_A49
SDQ_A54
SCLK_A5
SCLK_A2#
SDQS_A5#
SDQ_A42
SDQ_A44
SDQ_A45
SDQ_A40
SODT_A1
SODT_A2
SDQS_A4#
SDQ_A35
SDQ_A37
SDQ_A33
SRAS_A#
SCLK_A3#
SMA_A13
SMA_A6
AR2
6
AK17
AP4
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Table 13-8. XOR Chain 5
Pin Count
Ball #
Signal Name
1
2
AD38
AJ36
AL38
AG35
AJ39
AF34
AJ32
AG32
BA40
AW40
AV43
AY42
AU38
AR38
AM34
AP37
AN32
AM35
SDQS_B7#
SCLK_B5#
SCLK_B2
SDQ_B54
SDM_B6
3
4
5
6
SDQ_B51
SDQ_B53
SDQS_B6#
SCS_B0#
SCS_B3#
SODT_B2
SODT_B0
SDQ_B45
SDM_B5
7
8
9
10
11
12
13
14
15
16
17
18
SMA_A9
SMA_A5
SMA_A7
SCKE_A0
SDQS_A3#
SDQ_A27
SDQ_A25
SDQ_B47
SDQ_B41
SDQ_B42
SDQS_B5#
314
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Testability
Table 13-8. XOR Chain 5
Table 13-9. XOR Chain 6
Pin Count
Ball #
Signal Name
Pin Count
Ball #
Signal Name
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AM31
AR27
AR29
AV29
AM29
AY24
BA23
BB18
AY17
BB21
BA18
BA19
AV24
AM23
AR21
AR23
BB13
AP15
AM13
AM15
AT13
AT10
AV12
AM11
AR5
SDQ_B35
SDQ_B37
SDM_B4
5
BA31
AY33
BA32
AY30
AW32
BB32
BB30
BA26
BC24
BA25
AV20
AP20
AP18
AT20
AP17
AW12
AY12
BC11
AY10
BB9
SCLK_A3
SMA_A10
SMA_A0
SMA_A4
SMA_A1
SCLK_A0
SMA_A2
SBS_A2
6
7
SDQS_B4#
SCLK_B0
SCAS_B#
SRAS_B#
SMA_B9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SBS_B2
SCKE_A2
SCKE_A3
SDQ_A26
SDQ_A30
SDM_A3
SDQ_A31
SDQ_A28
SDQ_A16
SDQ_A23
SDQ_A22
SDQ_A17
SDQ_A21
SDQ_A20
SCLK_A4#
SCLK_A1
SDQ_A15
SDQ_A11
SDQ_A13
SDQ_A9
SDQ_A12
SDQ_A0
SDM_A0
SDQ_A3
SDQ_A6
SDQ_A4
SDQ_A2
SDQ_A7
SDQ_A1
SMA_B1
SMA_B7
SMA_B8
SDQ_B26
SDQ_B25
SDQ_B29
SDQS_B3#
SCKE_B3
SDQ_B22
SDQ_B17
SDQ_B16
SDQS_B2#
SCLK_B4#
SDQ_B10
SDQ_B11
SDQ_B12
SDQS_B1#
SDQS_B0#
SDQ_B4
BA9
BA5
AY5
AY7
BB7
AR9
AW4
AY3
AM6
AJ11
AP6
AV1
SDQ_B7
AP3
AP8
SDQ_B2
AR3
AV4
AU5
Table 13-9. XOR Chain 6
AN1
AU3
Pin Count
Ball #
Signal Name
AU2
1
2
3
4
AU37
AR34
AP32
BA37
SDQ_A39
SDQ_A38
SDQ_A32
SCAS_A#
AP2
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
315
Testability
Table 13-11. XOR Chain 8
Table 13-10. XOR Chain 7
Pin Count
Ball #
Signal Name
Pin Count
Ball #
Signal Name
1
F12
C13
D12
B12
H13
B10
F10
C9
EXP_RXN0
EXP_TXN0
EXP_RXN1
EXP_TXN1
EXP_RXN2
EXP_TXN2
EXP_RXN3
EXP_TXN3
EXP_RXN4
EXP_TXN4
EXP_RXN5
EXP_TXN5
EXP_RXN6
EXP_TXN6
EXP_RXN7
EXP_TXN7
EXP_RXN8
EXP_TXN8
EXP_RXN9
EXP_TXN9
EXP_RXN10
EXP_TXN10
EXP_RXN11
EXP_TXN11
EXP_RXN12
EXP_TXN12
EXP_RXN13
EXP_TXN13
EXP_RXN14
EXP_TXN14
EXP_RXN15
EXP_TXN15
EXP_RXP0
EXP_TXP0
EXP_RXP1
EXP_TXP1
EXP_RXP2
EXP_TXP2
EXP_RXP3
1
AN29
AP31
AP27
AM27
AP26
AW23
AY23
BC20
BB22
BB17
BA21
AY19
AT24
AP24
AP23
AY16
AV15
AP13
AN12
AW9
AU10
AU7
SDQ_B33
SDQ_B38
SDQ_B36
SCLK_B0#
SCLK_B3
SBS_B0
2
2
3
3
4
4
5
5
6
6
7
7
SBS_B1
8
8
SMA_B4
SMA_B0
SMA_B11
SMA_B2
SMA_B5
SDQ_B31
SDQ_B30
SDM_B3
SCKE_B1
SDQ_B18
SDM_B2
SDQ_B20
SCLK_B1#
SCLK_B4
SDQ_B8
SDQ_B15
SDQ_B14
SDM_B1
SDQ_B13
SDQ_B9
SDM_B0
SDQ_B0
SDQ_B5
SDQ_B6
SDQ_B3
SDQ_B1
9
H10
B7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
F9
D6
D3
B5
J6
F1
K8
J1
G4
K4
M7
M4
L1
AR10
AR12
AW7
AR7
N1
U10
T1
R7
AV6
U4
AL11
AL6
N3
V1
AL9
Y11
W4
G12
D14
D11
A13
J13
A11
E10
AM10
AP9
AL8
316
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Testability
Table 13-11. XOR Chain 8
Table 13-12. XOR Chain 9
Pin Count
Ball #
Signal Name
Pin Count
Ball #
Signal Name
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C10
J9
EXP_TXP3
EXP_RXP4
EXP_TXP4
EXP_RXP5
EXP_TXP5
EXP_RXP6
EXP_TXP6
EXP_RXP7
EXP_TXP7
EXP_RXP8
EXP_TXP8
EXP_RXP9
EXP_TXP9
EXP_RXP10
EXP_TXP10
EXP_RXP11
EXP_TXP11
EXP_RXP12
EXP_TXP12
EXP_RXP13
EXP_TXP13
EXP_RXP14
EXP_TXP14
EXP_RXP15
EXP_TXP15
1
2
Y8
Y7
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
A9
F7
3
Y1
D7
C4
A6
G6
E2
K9
G2
F4
4
W2
5
AA10
AA9
AB1
AA2
AA7
AA6
AA4
Y4
6
7
8
9
10
11
12
13
14
15
16
J3
M6
L4
AC8
AC9
AC4
AB3
K2
M2
U11
P2
R8
T4
P4
U2
Y10
V3
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
317
Testability
13.5
PADs Excluded from XOR Mode(s)
A large number of pads do not support XOR testing. The majority of the pads that fall into this
category are analog related pins (see Table 13-13).
Table 13-13. XOR Pad Exclusion List
PCI Express*
GCLKN
FSB
HCLKN
SM
SRCOMP1
Misc
DREFCLKN
DREFCLKP
BLUE
GCLKP
HCLKP
SRCOMP0
EXP_COMPO
EXP_COMPI
HRCOMP
HSCOMP
HVREF
SMVREF1
SMVREF0
BLUE#
SOCOMP1
GREEN
GREEN#
RED
HSWING
SOCOMP0
SM_SLEWOUT1
SM_SLEWOUT0
SM_SLEWIN1
SM_SLEWIN0
RED#
RSTIN#
HSYNC
VSYNC
REFSET
318
Intel® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
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