82X38 [INTEL]
Express Chipset; Express芯片组
| 型号： | 82X38 |
| 厂家： | 
INTEL |
| 描述： | Express Chipset |
| 文件： | 总342页 (文件大小：2370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Intel X38 Express Chipset
Datasheet
— For the Intel® 82X38 Memory Controller Hub (MCH)
October 2007
Document Number: 317610-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
®
The Intel 82X38Memory Controller Hub (MCH) may contain design defects or errors known as errata, which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
2
2
I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel.
2
Implementations of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
®
®
®
No computer system can provide absolute security under all conditions. Intel Trusted Execution Technology (Intel TXT) is a security technology under
®
development by Intel and requires for operation a computer system with Intel Virtualization Technology, a Intel Trusted Execution Technology-
enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured
virtual machine monitor. In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing
®
®
Group and specific software for some uses.
Intel, Pentium, Xeon, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
©
Copyright 2007, Intel Corporation
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Datasheet
Contents
1
Introduction............................................................................................................ 15
1.1
1.2
Terminology ..................................................................................................... 16
MCH Overview .................................................................................................. 19
1.2.1 Host Interface........................................................................................ 19
1.2.2 System Memory Interface ....................................................................... 19
1.2.3 Direct Media Interface (DMI).................................................................... 20
1.2.4 PCI Express* Interface............................................................................ 21
1.2.5 MCH Clocking ........................................................................................ 22
1.2.6 Power Management ................................................................................ 22
1.2.7 Thermal Sensor ..................................................................................... 22
2
Signal Description ................................................................................................... 23
2.1
2.2
Host Interface Signals........................................................................................ 24
System Memory (DDR2/DDR3) Interface Signals ................................................... 27
2.2.1 System Memory Channel A Interface Signals.............................................. 27
2.2.2 System Memory Channel B Interface Signals.............................................. 28
2.2.3 System Memory Miscellaneous Signals ...................................................... 29
PCI Express* Interface Signals............................................................................ 30
Controller Link Interface Signals.......................................................................... 30
Clocks, Reset, and Miscellaneous......................................................................... 31
Direct Media Interface........................................................................................ 32
Power and Grounds ........................................................................................... 32
2.3
2.4
2.5
2.6
2.7
3
System Address Map ............................................................................................... 33
3.1
Legacy Address Range ....................................................................................... 36
3.1.1 DOS Range (0h – 9_FFFFh) ..................................................................... 36
3.1.2 Expansion Area (C_0000h-D_FFFFh)......................................................... 37
3.1.3 Extended System BIOS Area (E_0000h–E_FFFFh)....................................... 37
3.1.4 System BIOS Area (F_0000h–F_FFFFh)..................................................... 38
3.1.5 PAM Memory Area Details........................................................................ 38
Main Memory Address Range (1MB – TOLUD)........................................................ 38
3.2.1 ISA Hole (15 MB –16 MB)........................................................................ 39
3.2.2 TSEG.................................................................................................... 40
3.2.3 Pre-allocated Memory ............................................................................. 40
PCI Memory Address Range (TOLUD – 4 GB) ........................................................ 41
3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh)................................. 43
3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ........................................................... 43
3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF)................................ 43
3.3.4 High BIOS Area...................................................................................... 43
Main Memory Address Space (4 GB to TOUUD)...................................................... 44
3.4.1 Memory Re-claim Background.................................................................. 45
3.4.2 Memory Reclaiming ................................................................................ 45
PCI Express* Configuration Address Space ........................................................... 45
PCI Express* Address Space............................................................................... 46
System Management Mode (SMM)....................................................................... 47
3.7.1 SMM Space Definition ............................................................................. 47
3.7.2 SMM Space Restrictions .......................................................................... 48
3.7.3 SMM Space Combinations........................................................................ 48
3.7.4 SMM Control Combinations ...................................................................... 49
3.7.5 SMM Space Decode and Transaction Handling ............................................ 49
3.7.6 Processor WB Transaction to an Enabled SMM Address Space....................... 49
3.2
3.3
3.4
3.5
3.6
3.7
Datasheet
3
3.7.7 SMM Access Through TLB.........................................................................49
Memory Shadowing............................................................................................50
I/O Address Space.............................................................................................50
3.9.1 PCI Express* I/O Address Mapping............................................................51
3.8
3.9
4
MCH Register Description.........................................................................................53
4.1
4.2
Register Terminology .........................................................................................54
Configuration Process and Registers.....................................................................55
4.2.1 Platform Configuration Structure...............................................................55
Configuration Mechanisms ..................................................................................56
4.3.1 Standard PCI Configuration Mechanism......................................................56
4.3.2 PCI Express Enhanced Configuration Mechanism .........................................57
Routing Configuration Accesses ...........................................................................58
4.4.1 Internal Device Configuration Accesses......................................................59
4.4.2 Bridge Related Configuration Accesses.......................................................60
4.4.2.1 PCI Express Configuration Accesses.............................................60
4.4.2.2 DMI Configuration Accesses........................................................60
I/O Mapped Registers.........................................................................................61
4.5.1 CONFIG_ADDRESS—Configuration Address Register....................................61
4.5.2 CONFIG_DATA—Configuration Data Register ..............................................62
4.3
4.4
4.5
5
DRAM Controller Registers (D0:F0)..........................................................................63
5.1
Configuration Register Details..............................................................................65
5.1.1 VID—Vendor Identification.......................................................................65
5.1.2 DID—Device Identification .......................................................................65
5.1.3 PCICMD—PCI Command ..........................................................................66
5.1.4 PCISTS—PCI Status ................................................................................67
5.1.5 RID—Revision Identification .....................................................................68
5.1.6 CC—Class Code ......................................................................................68
5.1.7 MLT—Master Latency Timer......................................................................68
5.1.8 HDR—Header Type .................................................................................69
5.1.9 SVID—Subsystem Vendor Identification.....................................................69
5.1.10 SID—Subsystem Identification..................................................................69
5.1.11 CAPPTR—Capabilities Pointer....................................................................70
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address ....................................70
5.1.13 MCHBAR—MCH Memory Mapped Register Range Base .................................71
5.1.14 DEVEN—Device Enable............................................................................72
5.1.15 PCIEXBAR—PCI Express* Register Range Base Address ...............................73
5.1.16 DMIBAR—Root Complex Register Range Base Address.................................75
5.1.17 PAM0—Programmable Attribute Map 0.......................................................76
5.1.18 PAM1—Programmable Attribute Map 1.......................................................77
5.1.19 PAM2—Programmable Attribute Map 2.......................................................78
5.1.20 PAM3—Programmable Attribute Map 3.......................................................79
5.1.21 PAM4—Programmable Attribute Map 4.......................................................80
5.1.22 PAM5—Programmable Attribute Map 5.......................................................81
5.1.23 PAM6—Programmable Attribute Map 6.......................................................82
5.1.24 LAC—Legacy Access Control.....................................................................83
5.1.25 REMAPBASE—Remap Base Address Register...............................................83
5.1.26 REMAPLIMIT—Remap Limit Address Register..............................................84
5.1.27 SMRAM—System Management RAM Control................................................85
5.1.28 ESMRAMC—Extended System Management RAM Control..............................86
5.1.29 TOM—Top of Memory ..............................................................................87
5.1.30 TOUUD—Top of Upper Usable Dram ..........................................................87
5.1.31 BSM—Base of Stolen Memory...................................................................88
5.1.32 TSEGMB—TSEG Memory Base ..................................................................88
5.1.33 TOLUD—Top of Low Usable DRAM.............................................................89
5.1.34 ERRSTS—Error Status .............................................................................90
5.1.35 ERRCMD—Error Command .......................................................................92
5.1.36 SMICMD—SMI Command.........................................................................93
4
Datasheet
5.1.37 SKPD—Scratchpad Data .......................................................................... 93
5.1.38 CAPID0—Capability Identifier................................................................... 94
MCHBAR .......................................................................................................... 97
5.2.1 CHDECMISC—Channel Decode Misc .......................................................... 99
5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ............................... 100
5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ............................... 101
5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ............................... 102
5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ............................... 102
5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute........................................ 103
5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute........................................ 104
5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG ............................................. 104
5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT.................................................. 105
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR.................................................... 106
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ ................................................. 107
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR............................................... 107
5.2.13 C0CKECTRL—Channel 0 CKE Control....................................................... 108
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control ....................................... 109
5.2.15 C0ECCERRLOG—Channel 0 ECC Error Log................................................ 111
5.2.16 C0ODTCTRL—Channel 0 ODT Control...................................................... 112
5.2.17 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ............................... 112
5.2.18 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ............................... 113
5.2.19 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ............................... 113
5.2.20 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ............................... 114
5.2.21 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes....................................... 114
5.2.22 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes....................................... 114
5.2.23 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG ............................................. 115
5.2.24 C1CYCTRKACT—Channel 1 CYCTRK ACT.................................................. 115
5.2.25 C1CYCTRKWR—Channel 1 CYCTRK WR.................................................... 116
5.2.26 C1CYCTRKRD—Channel 1 CYCTRK READ ................................................. 117
5.2.27 C1CKECTRL—Channel 1 CKE Control....................................................... 118
5.2.28 C1REFRCTRL—Channel 1 DRAM Refresh Control ....................................... 119
5.2.29 C1ECCERRLOG—Channel 1 ECC Error Log................................................ 120
5.2.30 C1ODTCTRL—Channel 1 ODT Control...................................................... 121
5.2.31 EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0........................ 122
5.2.32 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1........................ 122
5.2.33 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2........................ 122
5.2.34 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3........................ 123
5.2.35 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute ................................ 123
5.2.36 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute ................................ 124
5.2.37 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE ........................................... 124
5.2.38 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT........................................... 125
5.2.39 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR............................................. 125
5.2.40 EPDCYCTRKWRTREF—EPD CYCTRK WRT REF ........................................... 126
5.2.41 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ .......................................... 126
5.2.42 EPDCKECONFIGREG—EPD CKE Related Configuration................................ 127
5.2.43 EPDREFCONFIG—EP DRAM Refresh Configuration ..................................... 128
5.2.44 TSC1—Thermal Sensor Control 1............................................................ 130
5.2.45 TSC2—Thermal Sensor Control 2............................................................ 131
5.2.46 TSS—Thermal Sensor Status ................................................................. 133
5.2.47 TSTTP—Thermal Sensor Temperature Trip Point ....................................... 134
5.2.48 TCO—Thermal Calibration Offset ............................................................ 135
5.2.49 THERM1—Thermal Hardware Protection................................................... 136
5.2.50 TIS—Thermal Interrupt Status ............................................................... 136
5.2.51 TSMICMD—Thermal SMI Command......................................................... 138
5.2.52 PMSTS—Power Management Status ........................................................ 139
EPBAR ........................................................................................................... 140
5.3.1 EPESD—EP Element Self Description ....................................................... 140
5.3.2 EPLE1D—EP Link Entry 1 Description....................................................... 141
5.3.3 EPLE1A—EP Link Entry 1 Address ........................................................... 141
5.3.4 EPLE2D—EP Link Entry 2 Description....................................................... 142
5.2
5.3
Datasheet
5
5.3.5 EPLE2A—EP Link Entry 2 Address............................................................142
5.3.6 EPLE3D—EP Link Entry 3 Description.......................................................143
5.3.7 EPLE3A—EP Link Entry 3 Address............................................................144
6
Host-Primary PCI Express* Bridge Registers (D1:F0) ............................................145
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
VID1—Vendor Identification ..............................................................................147
DID1—Device Identification...............................................................................148
PCICMD1—PCI Command .................................................................................148
PCISTS1—PCI Status........................................................................................150
RID1—Revision Identification ............................................................................151
CC1—Class Code .............................................................................................151
CL1—Cache Line Size .......................................................................................152
HDR1—Header Type.........................................................................................152
PBUSN1—Primary Bus Number ..........................................................................152
6.10 SBUSN1—Secondary Bus Number......................................................................153
6.11 SUBUSN1—Subordinate Bus Number..................................................................153
6.12 IOBASE1—I/O Base Address .............................................................................154
6.13 IOLIMIT1—I/O Limit Address.............................................................................154
6.14 SSTS1—Secondary Status.................................................................................155
6.15 MBASE1—Memory Base Address........................................................................156
6.16 MLIMIT1—Memory Limit Address .......................................................................157
6.17 PMBASE1—Prefetchable Memory Base Address ....................................................158
6.18 PMLIMIT1—Prefetchable Memory Limit Address....................................................159
6.19 PMBASEU1—Prefetchable Memory Base Address Upper.........................................160
6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper ........................................161
6.21 CAPPTR1—Capabilities Pointer...........................................................................161
6.22 INTRLINE1—Interrupt Line................................................................................162
6.23 INTRPIN1—Interrupt Pin...................................................................................162
6.24 BCTRL1—Bridge Control ...................................................................................162
6.25 PM_CAPID1—Power Management Capabilities......................................................164
6.26 PM_CS1—Power Management Control/Status ......................................................165
6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities ..........................................166
6.28 SS—Subsystem ID and Subsystem Vendor ID......................................................166
6.29 MSI_CAPID—Message Signaled Interrupts Capability ID........................................167
6.30 MC—Message Control.......................................................................................167
6.31 MA—Message Address......................................................................................168
6.32 MD—Message Data ..........................................................................................168
6.33 PE_CAPL—PCI Express* Capability List ...............................................................168
6.34 PE_CAP—PCI Express* Capabilities ....................................................................169
6.35 DCAP—Device Capabilities ................................................................................169
6.36 DCTL—Device Control.......................................................................................170
6.37 DSTS—Device Status .......................................................................................171
6.38 LCAP—Link Capabilities.....................................................................................172
6.39 LCTL—Link Control...........................................................................................174
6.40 LSTS—Link Status............................................................................................176
6.41 SLOTCAP—Slot Capabilities ...............................................................................177
6.42 SLOTCTL—Slot Control .....................................................................................178
6.43 SLOTSTS—Slot Status ......................................................................................180
6.44 RCTL—Root Control..........................................................................................181
6.45 RSTS—Root Status ..........................................................................................182
6.46 PELC—PCI Express Legacy Control .....................................................................182
6.47 VCECH—Virtual Channel Enhanced Capability Header............................................183
6.48 PVCCAP1—Port VC Capability Register 1 .............................................................183
6.49 PVCCAP2—Port VC Capability Register 2 .............................................................184
6.50 PVCCTL—Port VC Control ..................................................................................184
6.51 VC0RCAP—VC0 Resource Capability ...................................................................185
6.52 VC0RCTL—VC0 Resource Control .......................................................................186
6.53 VC0RSTS—VC0 Resource Status ........................................................................187
6.54 RCLDECH—Root Complex Link Declaration Enhanced............................................187
6.55 ESD—Element Self Description ..........................................................................188
6
Datasheet
6.56 LE1D—Link Entry 1 Description ......................................................................... 188
6.57 LE1A—Link Entry 1 Address.............................................................................. 189
6.58 PESSTS—PCI Express* Sequence Status ............................................................ 189
7
Intel Manageability Engine Subsystem PCI (D3:F0,F3).......................................... 191
7.1
HECI Function in ME Subsystem (D3:F0) ............................................................ 191
7.1.1 ID—Identifiers ..................................................................................... 192
7.1.2 CMD—Command .................................................................................. 192
7.1.3 STS—Device Status.............................................................................. 193
7.1.4 RID—Revision ID.................................................................................. 193
7.1.5 CC—Class Code.................................................................................... 193
7.1.6 CLS—Cache Line Size............................................................................ 194
7.1.7 MLT—Master Latency Timer ................................................................... 194
7.1.8 HTYPE—Header Type ............................................................................ 194
7.1.9 HECI_MBAR—HECI MMIO Base Address................................................... 195
7.1.10 SS—Sub System Identifiers ................................................................... 195
7.1.11 CAP—Capabilities Pointer....................................................................... 196
7.1.12 INTR—Interrupt Information.................................................................. 196
7.1.13 MGNT—Minimum Grant......................................................................... 196
7.1.14 MLAT—Maximum Latency...................................................................... 197
7.1.15 HFS—Host Firmware Status ................................................................... 197
7.1.16 PID—PCI Power Management Capability ID.............................................. 197
7.1.17 PC—PCI Power Management Capabilities ................................................. 198
7.1.18 PMCS—PCI Power Management Control And Status................................... 198
7.1.19 MID—Message Signaled Interrupt Identifiers............................................ 199
7.1.20 MC—Message Signaled Interrupt Message Control..................................... 199
7.1.21 MA—Message Signaled Interrupt Message Address.................................... 200
7.1.22 MUA—Message Signaled Interrupt Upper Address (Optional) ...................... 200
7.1.23 MD—Message Signaled Interrupt Message Data........................................ 200
7.1.24 HIDM—HECI Interrupt Delivery Mode...................................................... 201
KT IO/ Memory Mapped Device Specific Registers [D3:F3] .................................... 202
7.2.1 KTRxBR—KT Receive Buffer .................................................................. 202
7.2.2 KTTHR—KT Transmit Holding ................................................................ 203
7.2.3 KTDLLR—KT Divisor Latch LSB .............................................................. 203
7.2.4 KTIER—KT Interrupt Enable .................................................................. 204
7.2.5 KTDLMR—KT Divisor Latch MSB ............................................................. 204
7.2.6 KTIIR—KT Interrupt Identification .......................................................... 205
7.2.7 KTFCR—KT FIFO Control ....................................................................... 206
7.2.8 KTLCR—KT Line Control ....................................................................... 207
7.2.9 KTMCR—KT Modem Control .................................................................. 208
7.2.10 KTLSR—KT Line Status ......................................................................... 209
7.2.11 KTMSR—KT Modem Status ................................................................... 210
7.2.12 KTSCR—KT Scratch ............................................................................. 210
7.2
8
Host-Secondary PCI Express* Bridge Registers (D6:F0) ....................................... 211
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
VID1—Vendor Identification.............................................................................. 213
DID1—Device Identification .............................................................................. 214
PCICMD1—PCI Command................................................................................. 214
PCISTS1—PCI Status ....................................................................................... 216
RID1—Revision Identification............................................................................ 217
CC1—Class Code............................................................................................. 217
CL1—Cache Line Size....................................................................................... 218
HDR1—Header Type ........................................................................................ 218
PBUSN1—Primary Bus Number.......................................................................... 218
8.10 SBUSN1—Secondary Bus Number...................................................................... 219
8.11 SUBUSN1—Subordinate Bus Number ................................................................. 219
8.12 IOBASE1—I/O Base Address............................................................................. 220
8.13 IOLIMIT1—I/O Limit Address ............................................................................ 220
8.14 SSTS1—Secondary Status ................................................................................ 221
8.15 MBASE1—Memory Base Address........................................................................ 222
Datasheet
7
8.16 MLIMIT1—Memory Limit Address .......................................................................223
8.17 PMBASE1—Prefetchable Memory Base Address Upper...........................................224
8.18 PMLIMIT1—Prefetchable Memory Limit Address....................................................225
8.19 PMBASEU1—Prefetchable Memory Base Address Upper.........................................226
8.20 PMLIMITU1—Prefetchable Memory Limit Address Upper ........................................227
8.21 CAPPTR1—Capabilities Pointer...........................................................................228
8.22 INTRLINE1—Interrupt Line................................................................................228
8.23 INTRPIN1—Interrupt Pin...................................................................................228
8.24 BCTRL1—Bridge Control ...................................................................................229
8.25 PM_CAPID1—Power Management Capabilities......................................................230
8.26 PM_CS1—Power Management Control/Status ......................................................231
8.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities ..........................................232
8.28 SS—Subsystem ID and Subsystem Vendor ID......................................................232
8.29 MSI_CAPID—Message Signaled Interrupts Capability ID........................................233
8.30 MC—Message Control.......................................................................................233
8.31 MA—Message Address......................................................................................234
8.32 MD—Message Data ..........................................................................................234
8.33 PE_CAPL—PCI Express* Capability List ...............................................................234
8.34 PE_CAP—PCI Express* Capabilities ....................................................................235
8.35 DCAP—Device Capabilities ................................................................................235
8.36 DCTL—Device Control.......................................................................................236
8.37 DSTS—Device Status .......................................................................................237
8.38 LCAP—Link Capabilities.....................................................................................238
8.39 LCTL—Link Control...........................................................................................240
8.40 LSTS—Link Status............................................................................................242
8.41 SLOTCAP—Slot Capabilities ...............................................................................243
8.42 SLOTCTL—Slot Control .....................................................................................244
8.43 SLOTSTS—Slot Status ......................................................................................246
8.44 RCTL—Root Control..........................................................................................247
8.45 RSTS—Root Status ..........................................................................................248
8.46 PELC—PCI Express Legacy Control .....................................................................248
8.47 VCECH—Virtual Channel Enhanced Capability Header............................................249
8.48 PVCCAP1—Port VC Capability Register 1 .............................................................249
8.49 PVCCAP2—Port VC Capability Register 2 .............................................................250
8.50 PVCCTL—Port VC Control ..................................................................................250
8.51 VC0RCAP—VC0 Resource Capability ...................................................................251
8.52 VC0RCTL—VC0 Resource Control .......................................................................252
8.53 VC0RSTS—VC0 Resource Status ........................................................................253
8.54 RCLDECH—Root Complex Link Declaration Enhanced............................................253
8.55 ESD—Element Self Description ..........................................................................254
8.56 LE1D—Link Entry 1 Description..........................................................................255
8.57 LE1A—Link Entry 1 Address ..............................................................................255
9
Direct Media Interface (DMI) RCRB........................................................................257
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
DMIVCECH—DMI Virtual Channel Enhanced Capability ..........................................258
DMIPVCCAP1—DMI Port VC Capability Register 1 .................................................258
DMIPVCCTL—DMI Port VC Control......................................................................259
DMIVC0RCAP—DMI VC0 Resource Capability .......................................................259
DMIVC0RCTL0—DMI VC0 Resource Control .........................................................260
DMIVC0RSTS—DMI VC0 Resource Status............................................................261
DMIVC1RCAP—DMI VC1 Resource Capability .......................................................261
DMIVC1RCTL1—DMI VC1 Resource Control .........................................................262
DMIVC1RSTS—DMI VC1 Resource Status............................................................263
9.10 DMILCAP—DMI Link Capabilities ........................................................................263
9.11 DMILCTL—DMI Link Control...............................................................................264
9.12 DMILSTS—DMI Link Status ...............................................................................264
8
Datasheet
10
Functional Description........................................................................................... 265
10.1 Host Interface................................................................................................. 265
10.1.1 FSB IOQ Depth .................................................................................... 265
10.1.2 FSB OOQ Depth ................................................................................... 265
10.1.3 FSB GTL+ Termination.......................................................................... 265
10.1.4 FSB Dynamic Bus Inversion ................................................................... 265
10.1.5 APIC Cluster Mode Support.................................................................... 266
10.2 System Memory Controller ............................................................................... 267
10.2.1 System Memory Organization Modes....................................................... 267
10.2.1.1 Single Channel Mode............................................................... 267
10.2.1.2 Dual Channel Modes................................................................ 267
10.2.2 System Memory Technology Supported................................................... 269
10.2.3 Error Checking and Correction................................................................ 270
10.3 PCI Express* .................................................................................................. 273
10.3.1 PCI Express* Architecture ..................................................................... 273
10.3.1.1 Transaction Layer ................................................................... 273
10.3.1.2 Data Link Layer ...................................................................... 273
10.3.1.3 Physical Layer ........................................................................ 273
10.4 Thermal Sensor............................................................................................... 274
10.4.1 PCI Device 0, Function 0 ....................................................................... 274
10.4.2 MCHBAR Thermal Sensor Registers......................................................... 274
10.5 Power Management ......................................................................................... 275
10.6 Clocking......................................................................................................... 275
11
Electrical Characteristics ....................................................................................... 277
11.1 Absolute Minimum and Maximum Ratings ........................................................... 277
11.2 Current Consumption....................................................................................... 279
11.3 Signal Groups................................................................................................. 280
11.4 Buffer Supply and DC Characteristics ................................................................. 283
11.4.1 I/O Buffer Supply Voltages .................................................................... 283
11.4.2 General DC Characteristics .................................................................... 284
12
13
Ballout and Package Information........................................................................... 287
12.1 Ballout Information.......................................................................................... 287
12.2 Package Information........................................................................................ 311
Testability ............................................................................................................. 313
13.1 XOR Test Mode Initialization ............................................................................. 313
13.2 XOR Chain Definition ....................................................................................... 314
13.3 XOR Chains .................................................................................................... 315
13.3.1 XOR Chains for DDR2 (No ECC).............................................................. 316
13.3.2 XOR Chains for DDR2 (ECC) .................................................................. 325
13.3.3 XOR Chains for DDR3 (No ECC).............................................................. 334
Datasheet
9
Figures
1
2
3
4
5
6
7
8
9
Intel® X38 Express Chipset System Diagram Example...................................................16
System Address Ranges ............................................................................................35
DOS Legacy Address Range .......................................................................................36
Main Memory Address Range .....................................................................................39
Pre-allocated Memory Example for 64 MB DRAM, 1 MB stolen and 1 MB TSEG...................40
PCI Memory Address Range ......................................................................................42
Conceptual Platform PCI Configuration Diagram............................................................55
Memory Map to PCI Express Device Configuration Space................................................58
MCH Configuration Cycle Flow Chart............................................................................59
10 System Clocking Diagram........................................................................................276
11 MCH Ballout Diagram (Top View Left – Columns 45–31) ..............................................288
12 MCH Ballout Diagram (Top View Middle – Columns 30–16)...........................................289
13 MCH Ballout Diagram (Top View Left – Columns 15–1) ................................................290
14 MCH Package Drawing ............................................................................................311
15 XOR Test Mode Initialization Cycles...........................................................................313
Tables
1
Intel Specification.....................................................................................................18
2
3
4
5
6
7
8
9
Expansion Area Memory Segments .............................................................................37
Extended System BIOS Area Memory Segments ...........................................................37
System BIOS Area Memory Segments.........................................................................38
Transaction Address Ranges – Compatible, High, and TSEG............................................47
SMM Space Table .....................................................................................................48
SMM Control Table....................................................................................................49
DRAM Controller Register Address Map........................................................................63
MCHBAR Register Address Map...................................................................................97
10 DRAM Rank Attribute Register Programming ..............................................................103
11 EPBAR Address Map................................................................................................140
12 Host-PCI Express Bridge Register Address Map (D1:F0)...............................................145
13 HECI Function in ME Subsystem (D3:F0) Register Address Map ....................................191
14 KT IO/Memory Mapped Register Address Map.............................................................202
15 Host-Secondary PCI Express* Bridge Register Address Map (D6:F0)..............................211
16 Direct Media Interface Register Address Map..............................................................257
17 Host Interface 4X, 2X, and 1X Signal Groups..............................................................266
18 Sample System Memory Dual Channel Symmetric Organization Mode............................267
19 Sample System Memory Dual Channel Asymmetric Organization Mode with
Intel® Flex Memory Mode Enabled............................................................................268
20 Sample System Memory Dual Channel Asymmetric Organization Mode with
Intel® Flex Memory Mode Disabled ...........................................................................268
21 Supported DIMM Module Configurations.....................................................................269
22 Syndrome Bit Values...............................................................................................270
23 Absolute Minimum and Maximum Ratings ..................................................................277
24 Current Consumption in S0......................................................................................279
25 Signal Groups ........................................................................................................281
26 I/O Buffer Supply Voltage........................................................................................283
27 DC Characteristics ..................................................................................................284
28 MCH Ballout Sorted By Name ...................................................................................291
29 MCH Ballout Sorted By Ball ......................................................................................301
30 XOR Chain 14 Functionality......................................................................................314
31 XOR Chain Outputs.................................................................................................315
32 XOR Chain 0 (DDR2, NoECC) ...................................................................................316
33 XOR Chain 1 (DDR2, NoECC) ...................................................................................316
34 XOR Chain 2 (DDR2, NoECC) ...................................................................................317
10
Datasheet
35 XOR Chain 3 (DDR2, NoECC)................................................................................... 317
36 XOR Chain 4 (DDR2, NoECC)................................................................................... 318
37 XOR Chain 5 (DDR2, NoECC)................................................................................... 318
38 XOR Chain 6 (DDR2, NoECC)................................................................................... 318
39 XOR Chain 7 (DDR2, NoECC)................................................................................... 319
40 XOR Chain 8 (DDR2, NoECC)................................................................................... 320
41 XOR Chain 9 (DDR2, NoECC)................................................................................... 320
42 XOR Chain 10 (DDR2, NoECC) ................................................................................. 320
43 XOR Chain 11 (DDR2, NoECC) ................................................................................. 321
44 XOR Chain 12 (DDR2, NoECC) ................................................................................. 322
45 XOR Chain 13 (DDR2, NoECC) ................................................................................. 322
46 XOR Chain 14 (DDR2, NoECC) ................................................................................. 323
47 XOR Chain 0 (DDR2, ECC)....................................................................................... 325
48 XOR Chain 1 (DDR2, ECC)....................................................................................... 326
49 XOR Chain 2 (DDR2, ECC)....................................................................................... 326
50 XOR Chain 3 (DDR2, ECC)....................................................................................... 326
51 XOR Chain 4 (DDR2, ECC)....................................................................................... 327
52 XOR Chain 5 (DDR2, ECC)....................................................................................... 327
53 XOR Chain 6 (DDR2, ECC)....................................................................................... 328
54 XOR Chain 7 (DDR2, ECC)....................................................................................... 329
55 XOR Chain 8 (DDR2, ECC)....................................................................................... 329
56 XOR Chain 9 (DDR2, ECC)....................................................................................... 329
57 XOR Chain 10 (DDR2, ECC)..................................................................................... 330
58 XOR Chain 11 (DDR2, ECC)..................................................................................... 331
59 XOR Chain 12 (DDR2, ECC)..................................................................................... 331
60 XOR Chain 13 (DDR2, ECC)..................................................................................... 331
61 XOR Chain 14 (DDR2, ECC)..................................................................................... 332
62 XOR Chain 0 (DDR3, NoECC)................................................................................... 334
63 XOR Chain 1 (DDR3, NoECC)................................................................................... 334
64 XOR Chain 2 (DDR3, NoECC)................................................................................... 335
65 XOR Chain 3 (DDR3, NoECC)................................................................................... 335
66 XOR Chain 4 (DDR3, NoECC)................................................................................... 336
67 XOR Chain 5 (DDR3, NoECC)................................................................................... 336
68 XOR Chain 6 (DDR3, NoECC)................................................................................... 336
69 XOR Chain 7 (DDR3, NoECC)................................................................................... 337
70 XOR Chain 8 (DDR3, NoECC)................................................................................... 338
71 XOR Chain 9 (DDR3, NoECC)................................................................................... 338
72 XOR Chain 10 (DDR3, NoECC) ................................................................................. 338
73 XOR Chain 11 (DDR3, NoECC) ................................................................................. 339
74 XOR Chain 12 (DDR3, NoECC) ................................................................................. 340
75 XOR Chain 13 (DDR3, NoECC) ................................................................................. 340
76 XOR Chain 14 (DDR3, NoECC) ................................................................................. 341
Datasheet
11
Revision History
Revision
Number
Description
Revision Date
-001
•
Initial release
October 2007
12
Datasheet
®
Intel 82X38 MCH Features
•
Processor/Host Interface (FSB)
•
PCI Express* Interface
®
—
—
—
—
—
—
—
—
—
—
Supports Intel Core™2 Duo desktop processor
Supports Intel Core™2 Quad desktop processor
800/1067/1333 MT/s (200/266/333 MHz) FSB
Hyper-Threading Technology (HT Technology)
FSB Dynamic Bus Inversion (DBI)
36-bit host bus addressing
12-deep In-Order Queue
1-deep Defer Queue
GTL+ bus driver with integrated GTL termination resistors
Supports cache Line Size of 64 bytes
—
—
Two x16 PCI Express ports
Compatible with the PCI Express Base Specification,
Revision 2.0
®
—
Raw bit rate on data pins of 5 Gb/s resulting in a real
bandwidth per pair of 500 MB/s
•
•
Thermal Sensor
—
—
Catastrophic Trip Point support
Hot Trip Point support for SMI generation
Power Management
—
PC99 suspend to DRAM support (“STR”, mapped to
ACPI state S3)
•
System Memory Interface
—
—
—
—
ACPI Revision 2.0 compatible power management
Supports processor states: C0, C1, C2
Supports System states: S0, S1, S3 (Cold), and S5
Supports processor Thermal Management 2
—
—
—
—
—
—
One or two channels (each channel consisting of 64 data lines)
Single or Dual Channel memory organization
DDR2-800/667 frequencies
DDR3-1066/800 frequencies
Unbuffered, ECC and non-ECC DDR2 or non-ECC DDR3 DIMMs
•
Package
—
—
—
FC-BGA
Supports 1-Gb, 512-Mb DDR2 or DDR3 technologies for x8 and
x16 devices
40 mm × 40 mm package size
1300 balls, located in a non-grid pattern
—
8 GB maximum memory
•
Direct Media Interface (DMI)
—
—
—
Chip-to-chip connection interface to Intel ICH9
2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction)
100 MHz reference clock (shared with PCI Express graphics
attach)
—
—
32-bit downstream addressing
Messaging and Error Handling
§
Datasheet
13
14
Datasheet
Introduction
1
Introduction
The Intel® X38 Express Chipset is designed for use with the Intel® CoreTM2 Duo
processor and Intel® Core™2 Quad processor in high-end desktop and workstation
platforms. The chipset contains two components: 82X38 MCH for the host bridge and
I/O Controller Hub 9 (ICH9) for the I/O subsystem. The ICH9 is the ninth generation
I/O Controller Hub and provides a multitude of I/O related functions. Figure 1 shows an
example system block diagram for the Intel® X38 Express Chipset.
This document is the datasheet for the Intel® 82X38 Memory Controller Hub (MCH).
Topics covered include; signal description, system memory map, PCI register
description, a description of the MCH interfaces and major functional units, electrical
characteristics, ballout definitions, and package characteristics.
Note:
Note:
Unless otherwise specified, ICH9 refers to the Intel® 82801IB ICH9 and Intel® 82801IR
ICH9R I/O Controller Hub 9 components.
The term ICH9 refers to the ICH9 and ICH9R components.
Datasheet
15
Introduction
1.1
Terminology
Figure 1.
Intel® X38 Express Chipset System Diagram Example
Processor
System Memory
DDR2/3
CH A
CH B
DDR2 /
DDR3
Intel® 82X38
MCH
PCI Express
PCI Express
PCI Express x16
PCI Express x16
DDR2 /DDR3
C Link – Still
connect on non-
AMT system
DMI
Power
Management
USB2. 0
12 Ports
Clock
Generation
GPIO
SATA
SMBus2.0 /
I2C
6 Ports
Intel® ICH 9
SST/PECI
(Fan Speed Control)
Gb LAN
WLAN
SPI
SPI
Flash
6 PCIe x1
Slots
LPC
Firmware
SIO
PCIe Bus
4 PCI Masters
PCI Bus
Term
Description
Used in this specification to refer to one or more hardware components that
connect processor complexes to the I/O and memory subsystems. The chipset
may include a variety of integrated devices.
Chipset / Root
– Complex
Controller Link is a proprietary chip-to-chip connection between the MCH and
ICH. The chipset requires that Clink is connected in the platform.
CLink
Core
DBI
The internal base logic in the MCH
Dynamic Bus Inversion
DDR2
DDR3
A second generation Double Data Rate SDRAM memory technology
A third generation Double Data Rate SDRAM memory technology
16
Datasheet
Introduction
Term
Description
Direct Media Interface is a proprietary chip-to-chip connection between the
MCH and ICH. This interface is based on the standard PCI Express*
specification.
DMI
A collection of physical, logical or virtual resources that are allocated to work
Domain
together. Domain is used as a generic term for virtual machines, partitions,
etc.
EP
PCI Express Egress Port
FSB
Front Side Bus. Synonymous with Host or processor bus
Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN#
and PWROK are asserted.
Full Reset
MCH
Memory Controller Hub component that contains the processor interface,
DRAM controller, and PCI Express port. It communicates with the I/O
controller hub (Intel® ICH9) over the DMI interconnect. .
Host
INTx
This term is used synonymously with processor
An interrupt request signal where X stands for interrupts A, B, C and D
Ninth generation I/O Controller Hub component that contains the primary PCI
interface, LPC interface, USB2.0, SATA, and other I/O functions. For this MCH,
the term ICH refers to the ICH9.
Intel® ICH9
IOQ
In Order Queue
Message Signaled Interrupt. A transaction conveying interrupt information to
the receiving agent through the same path that normally carries read and
write commands.
MSI
OOQ
Out of Order Queueing
A high-speed serial interface whose configuration is software compatible with
the legacy PCI specifications.
PCI Express*
The physical PCI bus that is driven directly by the Intel® ICH9.
Communication between Primary PCI and the MCH occurs over DMI. The
Primary PCI bus is not PCI Bus 0 from a configuration standpoint.
Primary PCI
Rank
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four
x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but
not always, mounted on a single side of a DIMM.
SCI
System Control Interrupt. Used in ACPI protocol.
System Error. An indication that an unrecoverable error has occurred on an
I/O bus.
SERR
System Management Interrupt. Used to indicate any of several system
conditions such as thermal sensor events, throttling activated, access to
System Management RAM, chassis open, or other system state related
activity.
SMI
Intel® Trusted Execution Technology (TXT) defines platform level
enhancements that provide the building blocks for creating trusted platforms.
Intel® TXT
VCO
Voltage Controlled Oscillator
Datasheet
17
Introduction
Table 1.
Intel Specification
Document Name
Intel® X38 Express Chipset Specification Update
Location
http://www.intel.com/design/
chipsets/specupdt/317611.htm
Intel® X38 Express Chipset Thermal and Mechanical Design http://www.intel.com/design/
Guide
chipsets/designex/317612.htm
Intel® Core™2 Duo Processor and Intel® Pentium® Dual
Core Thermal and Mechanical Design Guide
http://www.intel.com/design/
processor/designex/317804.htm
Intel® I/O Controller Hub 9 (ICH9) Family Thermal
Mechanical Design Guide.
http://www.intel.com/design/
chipsets/designex/316974.htm
http://www.intel.com/design/
chipsets/datashts/316972.htm
Intel® I/O Controller Hub 9 (ICH9) Family Datasheet
http://www.intel.com/design/
chipsets/applnots/316970.htm
Designing for Energy Efficiency White Paper
Intel® X38 Express Chipset Memory Technology and
Configuration Guide White Paper
318469
Intel® P35/G33 Express Chipset Memory Technology and
Configuration Guide White Paper
http://www.intel.com/design/
chipsets/applnots/316971.htm
Advanced Configuration and Power Interface Specification,
Version 2.0
http://www.acpi.info/
http://www.acpi.info/
Advanced Configuration and Power Interface Specification,
Version 1.0b
http://www.pcisig.com/
specifications
The PCI Local Bus Specification, Version 2.3
http://www.pcisig.com/
specifications
PCI Express* Specification, Version 1.1
18
Datasheet
Introduction
1.2
MCH Overview
The role of a MCH in a system is to manage the flow of information between its four
interfaces: the processor interface, the system memory interface, the PCI Express
interface, and the I/O Controller through DMI interface. This includes arbitrating
between the four interfaces when each initiates transactions. It supports one or two
channels of DDR2 or DDR3 SDRAM. It also supports the PCI Express based external
device attach. The Intel X38 Express Chipset platform supports the ninth generation
I/O Controller Hub (Intel ICH9) to provide I/O related features.
1.2.1
Host Interface
The MCH supports a single LGA775 socket processor. The MCH supports a FSB
frequency of 800/1066/1333 MHz. Host-initiated I/O cycles are decoded to PCI
Express, DMI, or the MCH configuration space. Host-initiated memory cycles are
decoded to PCI Express, DMI or system memory. PCI Express device accesses to non-
cacheable system memory are not snooped on the host bus. Memory accesses initiated
from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped
on the host bus.
Processor/Host Interface (FSB) Details
• Supports the Intel® CoreTM2 Duo processor and Intel® Core™2 Quad processor
• Supports Front Side Bus (FSB) at the following Frequency Ranges:
— 800/1066/1333MT/s
• Supports FSB Dynamic Bus Inversion (DBI)
• Supports 36-bit host bus addressing, allowing the processor to access the entire
64 GB of the host address space.
• Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined
address requests on the host bus
• Has a 1-deep Defer Queue
• Uses GTL+ bus driver with integrated GTL termination resistors
• Supports a Cache Line Size of 64 bytes
1.2.2
System Memory Interface
The MCH integrates a system memory DDR2/DDR3 controller with two, 64-bit wide
interfaces. The buffers support both SSTL_1.8 (Stub Series Terminated Logic for 1.8 V)
and SSTL_1.5 (Stub Series Terminated Logic for 1.5 V) signal interfaces. The memory
controller interface is fully configurable through a set of control registers.
System Memory Interface Details
• Directly supports one or two channels of DDR2 or DDR3 memory with a maximum
of two DIMMs per channel.
• Supports single and dual channel memory organization modes.
• Supports a data burst length of eight for all memory organization modes.
• Supports memory data transfer rates of 667 and 800 MHz for DDR2 and 800, 1066,
and 1333 MHz for DDR3.
• I/O Voltage of 1.8 V for DDR2 and 1.5 V for DDR3.
• Supports both un-buffered ECC and non-ECC DDR2 or non-ECC DDR3 DIMMs.
Datasheet
19
Introduction
• Supports maximum memory bandwidth of 6.4 GB/s in single-channel mode or
12.8 GB/s in dual-channel mode assuming DDR2 800 MHz.
• Supports maximum memory bandwidth of 10.6GB/s in single-channel mode or
21 GB/s in dual-channel mode assuming DDR3 1333 MHz.
• Supports 512-Mb and 1-Gb DDR2 or DDR3 DRAM technologies for x8 and x16
devices.
• Using 512 Mb device technologies, the smallest memory capacity possible is
256 MB, assuming Single Channel Mode with a single x16 single sided un-buffered
non-ECC DIMM memory configuration.
• Using 1 Gb device technologies, the largest memory capacity possible is 8 GB,
assuming Dual Channel Mode with four x8 double sided un-buffered non-ECC or
ECC DIMM memory configurations.
Note: The ability to support greater than the largest memory capacity is subject to
availability of higher density memory devices.
• Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of
8 bank devices)
• Supports opportunistic refresh scheme
• Supports Partial Writes to memory using Data Mask (DM) signals
• Supports a memory thermal management scheme to selectively manage reads
and/or writes. Memory thermal management can be triggered either by on-die
thermal sensor, or by preset limits. Management limits are determined by weighted
sum of various commands that are scheduled on the memory interface.
1.2.3
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the MCH and
ICH9. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate
normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH9 supports two virtual channels on DMI: VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (i.e., the ICH9 and
MCH).
• A chip-to-chip connection interface to Intel ICH9
• 2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction)
• 100 MHz reference clock (shared with PCI Express)
• 32-bit downstream addressing
• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of
Interrupt” broadcast message when initiated by the processor.
• Message Signaled Interrupt (MSI) messages
• SMI, SCI, and SERR error indication
20
Datasheet
Introduction
1.2.4
PCI Express* Interface
The MCH supports two 16-lane (x16) PCI Express ports. The PCI Express ports are
compliant to the PCI Express* Base Specification revision 2.0. The x16 ports operate at
a frequency of 5 Gb/s on each lane while employing 8b/10b encoding, and support a
maximum theoretical bandwidth of 8.0 GB/s in each direction.
The PCI Express interface includes:
• Two, 16-lane PCI Express ports intended for external device attach, compatible to
the PCI Express* Base Specification, Revision 2.0.
• PCI Express frequency of 2.5 GHz resulting in 5.0 Gb/s each direction per lane.
• Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 8 GB/s in each
direction simultaneously, for an aggregate of 16 GB/s when x16.
• PCI Express Enhanced Addressing Mechanism allows for accessing the device
configuration space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-
relaxed ordering)
• Hierarchical PCI-compliant configuration mechanism for downstream devices
(i.e., normal PCI 2.3 Configuration space as a PCI-to-PCI bridge).
• Supports “static” lane numbering reversal. This method of lane reversal is
controlled by a Hardware Reset strap, and reverses both the receivers and
transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is
transparent to all external devices and is different than lane reversal as defined in
the PCI Express Specification. In particular, link initialization is not affected by
static lane reversal.
• When two, 16-lane PCI Express ports are used, the second port supports either PCI
Express Gen1.1 I/O cards with x8, x4 or x1 lanes or PCI Express Gen1/Gen2
Graphics cards with x16 or x1 lanes.
Datasheet
21
Introduction
1.2.5
MCH Clocking
• Differential host clock of 200/266/333 MHz. Supports FSB transfer rates of
800/1066/1333 MT/s.
• Differential memory clocks of 333/400/533 MHz. Supports memory
transfer rates of DDR2-667, DDR2-800, DDR3-800, and DDR3-1067.
• The PCI Express* PLL of 100 MHz Serial Reference Clock generates the PCI
Express core clock of 250 MHz.
• All of the above clocks are capable of tolerating Spread Spectrum clocking.
• Host, memory, and PCI Express PLLs are disabled until PWROK is asserted.
1.2.6
Power Management
MCH Power Management support includes:
• PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)
• SMRAM space remapping to A0000h (128 KB)
• Supports extended SMRAM space above 256 MB, and cacheable (cacheability
controlled by processor)
• ACPI Rev 1.0b compatible power management
• Supports processor states: C0, C1, and C2
• Supports System states: S0, S1, S3 (Cold), and S5
• Supports processor Thermal Management 2 (TM2)
• Supports Manageability states M0, M1–S3, M1–S5, Moff–S3, Moff–S5, Moff-M1
1.2.7
Thermal Sensor
MCH Thermal Sensor support includes:
• Catastrophic Trip Point support for emergency clock gating for the MCH
• Hot Trip Point support for SMI generation
§ §
22
Datasheet
Signal Description
2
Signal Description
This chapter provides a detailed description of MCH signals. The signals are arranged in
functional groups according to their associated interface.
The following notations are used to describe the signal type.
Signal Type
Description
PCI Express interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications and are AC coupled. The buffers are
not 3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2 Vmax.
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
PCI Express*
Direct Media Interface signals. These signals are compatible with PCI Express
1.1 Signaling Environment AC Specifications, but are DC coupled. The buffers
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax.
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
DMI
CMOS
COD
CMOS buffers. 1.5 V tolerant.
CMOS Open Drain buffers. 3.3 V tolerant.
High Voltage CMOS buffers. 3.3 V tolerant.
High Voltage CMOS input-only buffers. 3.3 V tolerant.
HVCMOS
HVIN
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
SSTL_1.8
SSTL_1.5
Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V
tolerant
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
A
Gunning Transceiver Logic signaling technology. Implements a voltage level as
defined by VTT of 1.2 V and/or 1.1 V.
GTL+
Datasheet
23
Signal Description
2.1
Host Interface Signals
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to
the termination voltage of the Host Bus (VTT).
Signal Name
Type
Description
Address Strobe: The processor bus owner asserts FSB_ADSB
to indicate the first of two cycles of a request phase. The MCH
can assert this signal for snoop cycles and interrupt messages.
I/O
FSB_ADSB
GTL+
Block Next Request: Used to block the current request bus
owner from issuing new requests. This signal is used to
dynamically control the processor bus pipeline depth.
I/O
FSB_BNRB
FSB_BPRIB
GTL+
Priority Agent Bus Request: The MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain the
ownership of the address bus. This signal has priority over
symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the FSB_LOCKB
signal was asserted.
O
GTL+
Bus Request 0: The MCH pulls the processor bus’
FSB_BREQ0B signal low during FSB_CPURSTB. The processors
sample this signal on the active-to-inactive transition of
FSB_CPURSTB. The minimum setup time for this signal is 4
HCLKs. The minimum hold time is 2 HCLKs and the maximum
hold time is 20 HCLKs. FSB_BREQ0B should be tri-stated after
the hold time requirement has been satisfied.
O
FSB_BREQ0B
FSB_CPURSTB
GTL+
CPU Reset: The FSB_CPURSTB pin is an output from the MCH.
The MCH asserts FSB_CPURSTB while RSTINB (PCIRST# from
the ICH) is asserted and for approximately 1 ms after RSTINB
is de-asserted. The FSB_CPURSTB allows the processors to
begin execution in a known state.
O
GTL+
I/O
Data Bus Busy: Used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
FSB_DBSYB
FSB_DEFERB
GTL+
Defer: Signals that the MCH will terminate the transaction
currently being snooped with either a deferred response or with
a retry response.
O
GTL+
Dynamic Bus Inversion: Driven along with the
FSB_DB_[63:0] signals. Indicates if the associated signals are
inverted or not. FSB_DINVB_[3:0] are asserted such that the
number of data bits driven electrically low (low voltage) within
the corresponding 16 bit group never exceeds 8.
I/O
FSB_DINVB_[3:0]
FSB_DRDYB
FSB_DINVB_x
FSB_DINVB_3
FSB_DINVB_2
FSB_DINVB_1
FSB_DINVB_0
Data Bits
GTL+ 4x
FSB_DB_[63:48]
FSB_DB_[47:32]
FSB_DB_[31:16]
FSB_DB_[15:0]
I/O
Data Ready: Asserted for each cycle that data is transferred.
GTL+
24
Datasheet
Signal Description
Signal Name
Type
Description
Host Address Bus: FSB_AB_[35:3] connect to the processor
address bus. During processor cycles, the FSB_AB_[35:3] are
inputs. The MCH drives FSB_AB_[35:3] during snoop cycles on
behalf of DMI and PCI Express initiators. FSB_AB_[35:3] are
transferred at 2x rate. Note that the address is inverted on the
processor bus. The values are driven by the MCH between
PWROK assertion and FSB_CPURSTINB deassertion to allow
processor configuration.
I/O
FSB_AB_[35:3]
GTL+ 2x
Host Address Strobe: The source synchronous strobes used
to transfer FSB_AB_[31:3] and FSB_REQB_[4:0] at the 2x
transfer rate.
I/O
FSB_ADSTBB_[1:0]
FSB_DB_[63:0]
Strobe
Address Bits
GTL+ 2x
FSB_ADSTBB_0
FSB_ADSTBB_1
FSB_AB_[16:3], FSB_REQB_[4:0]
FSB_AB_[31:17]
Host Data: These signals are connected to the processor data
bus. Data on FSB_DB_[63:0] is transferred at a 4x rate. Note
that the data signals may be inverted on the processor bus,
depending on the FSB_DINVB_[3:0] signals.
I/O
GTL+ 4x
Differential Host Data Strobes: The differential source
synchronous strobes used to transfer FSB_DB_[63:0] and
FSB_DINVB_[3:0] at the 4x transfer rate.
Named this way because they are not level sensitive. Data is
captured on the falling edge of both strobes. Hence, they are
pseudo-differential, and not true differential.
FSB_DSTBPB_[3:0]
I/O
FSB_DSTBNB_[3:0] GTL+ 4x
Strobe
Data Bits
FSB_DSTB[P,N]B_3
FSB_DSTB[P,N]B_2
FSB_DSTB[P,N]B_1
FSB_DSTB[P,N]B_0
FSB_DB_[63:48], HDINVB_3
FSB_DB_[47:32], HDINVB_2
FSB_DB_[31:16], HDINVB_1
FSB_DB_[15:0], HDINVB_0
Hit: Indicates that a caching agent holds an unmodified version
of the requested line. Also, driven in conjunction with
FSB_HITMB by the target to extend the snoop window.
I/O
FSB_HITB
GTL+
Hit Modified: Indicates that a caching agent holds a modified
version of the requested line and that this agent assumes
responsibility for providing the line. Also, driven in conjunction
with FSB_HITB to extend the snoop window.
I/O
FSB_HITMB
GTL+
Host Lock: All processor bus cycles sampled with the assertion
of FSB_LOCKB and FSB_ADSB, until the negation of
FSB_LOCKB must be atomic, i.e. no DMI or PCI Express access
to DRAM are allowed when FSB_LOCKB is asserted by the
processor.
I
FSB_LOCKB
GTL+
Host Request Command: Defines the attributes of the
request. FSB_REQB_[4:0] are transferred at 2x rate. Asserted
by the requesting agent during both halves of Request Phase.
In the first half the signals define the transaction type to a level
of detail that is sufficient to begin a snoop request. In the
second half the signals carry additional information to define
the complete transaction type.
I/O
FSB_REQB_[4:0]
GTL+
2x
The transactions supported by the MCH Host Bridge are defined
in the Host Interface section of this document.
Datasheet
25
Signal Description
Signal Name
FSB_TRDYB
Type
Description
O
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data transfer phase.
GTL+
Response Signals: Indicates type of response according to
the table at left:
Encoding Response Type
000
001
010
011
100
101
110
111
Idle state
Retry response
O
Deferred response
FSB_RSB_[2:0]
GTL+
Reserved (not driven by MCH)
Hard Failure (not driven by MCH)
No data response
Implicit Writeback
Normal data response
Host RCOMP: Used to calibrate the Host GTL+ I/O buffers.
I/O
A
FSB_RCOMP
This signal is powered by the Host Interface termination rail
(VTT). Connects to FSB_XRCOMP1IN in the package.
I/O
A
Slew Rate Compensation: Compensation for the Host
Interface for rising edges.
FSB_SCOMP
I/O
A
Slew Rate Compensation: Compensation for the Host
Interface for falling edges.
FSB_SCOMPB
Host Voltage Swing: These signals provide reference voltages
used by the FSB RCOMP circuits. FSB_XSWING is used for the
signals handled by FSB_XRCOMP.
I/O
A
FSB_SWING
I/O
A
Host Reference Voltage: Reference voltage input for the
Data signals of the Host GTL interface.
FSB_DVREF
I/O
A
Host Reference Voltage: Reference voltage input for the
Address signals of the Host GTL interface.
FSB_ACCVREF
26
Datasheet
Signal Description
2.2
System Memory (DDR2/DDR3) Interface Signals
2.2.1
System Memory Channel A Interface Signals
Signal Name
Type
Description
SDRAM Differential Clocks:
O
DDR_A_CK
—
—
DDR2: Three per DIMM
DDR3: Two per DIMM
SSTL-1.8/1.5
SDRAM Inverted Differential Clocks:
O
DDR_A_CKB
—
—
DDR2: Three per DIMM
DDR3: Two per DIMM
SSTL-1.8/1.5
DDR_A_CSB_3
DDR_A_CSB_2
DDR_A_CSB_0
O
DDR2/DDR3 Device Rank 3, 2, and 0 Chip Selects
DDR2 Device Rank 1 Chip Select
SSTL-1.8/1.5
O
DDR_A_CSB_1
SSTL-1.8
O
DDR3_A_CSB_1
DDR_A_CKE_[3:0]
DDR3 Device Rank 1 Chip Select
SSTL-1.5
O
DDR2/DDR3 Clock Enable:
SSTL-1.8/1.5
(1 per Device Rank)
O
DDR2/DDR3 On Die Termination:
DDR_A_ODT_[3:0]
DDR_A_MA_[14:1]
DDR_A_MA_0
SSTL-1.8/1.5
(1 per Device Rank)
O
DDR2/DDR3 Address Signals [14:1]
DDR2 Address Signal 0
SSTL-1.8/1.5
O
SSTL-1.8
O
DDR3_A_MA_0
DDR_A_BS_[2:0]
DDR_A_RASB
DDR3 Address Signal 0
SSTL-1.5
O
DDR2/DDR3 Bank Select
SSTL-1.8/1.5
O
DDR2/DDR3 Row Address Select signal
DDR2/DDR3 Column Address Select signal
DDR2 Write Enable signal
SSTL-1.8/1.5
O
DDR_A_CASB
SSTL-1.8/1.5
O
DDR_A_WEB
SSTL-1.8
O
DDR3_A_WEB
DDR3 Write Enable signal
SSTL-1.5
I/O
DDR_A_DQ_[63:0]
DDR2/DDR3 Data Lines
SSTL-1.8/1.5
Datasheet
27
Signal Description
Signal Name
Type
Description
I/O
DDR_A_CB_[7:0]
ECC Check Byte
SSTL-1.8
O
DDR_A_DM_[7:0]
DDR_A_DQS_[8:0]
DDR_A_DQSB_[8:0]
DDR2/DDR3 Data Mask
SSTL-1.8/1.5
I/O
DDR2/DDR3 Data Strobes
SSTL-1.8/1.5
I/O
DDR2/DDR3 Data Strobe Complements
SSTL-1.8/1.5
2.2.2
System Memory Channel B Interface Signals
Signal Name
Type
Description
SDRAM Differential Clocks:
O
DDR_B_CK
—
—
DDR2: Three per DIMM
DDR3: Two per DIMM
SSTL-1.8/1.5
SDRAM Inverted Differential Clocks:
O
DDR_B_CKB
—
—
DDR2: Three per DIMM
DDR3: Two per DIMM
SSTL-1.8/1.5
O
DDR2/DDR3 Device Rank 3, 2, 1, and 0 Chip
Select
DDR_B_CSB_[3:0]
SSTL-1.8/1.5
O
DDR2/DDR3 Clock Enable:
DDR_B_CKE_[3:0]
SSTL-1.8/1.5
(1 per Device Rank)
O
DDR2/DDR3 Device Rank 2, 1, and 0 On Die
Termination
DDR_B_ODT_[2:0]
DDR_B_ODT_3
DDR3_B_ODT_3
DDR_B_MA_[14:0]
DDR_B_BS_[2:0]
DDR_B_RASB
SSTL-1.8/1.5
O
DDR2 Device Rank 3 On Die Termination
DDR3 Device Rank 3 On Die Termination
DDR2/DDR3 Address Signals [14:0]
DDR2/DDR3 Bank Select
SSTL-1.8
O
SSTL-1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
DDR2/DDR3 Row Address Select signal
DDR2/DDR3 Column Address Select signal
DDR2/DDR3 Write Enable signal
DDR2/DDR3 Data Lines
SSTL-1.8/1.5
O
DDR_B_CASB
SSTL-1.8/1.5
O
DDR_B_WEB
SSTL-1.8/1.5
I/O
DDR_B_DQ_[63:0]
SSTL-1.8/1.5
28
Datasheet
Signal Description
Signal Name
Type
Description
I/O
DDR_B_CB_[7:0]
ECC Check Byte
SSTL-1.8
O
DDR_B_DM_[7:0]
DDR_B_DQS_[8:0]
DDR2/DDR3 Data Mask
SSTL-1.8/1.5
I/O
DDR2/DDR3 Data Strobes
SSTL-1.8/1.5
I/O
DDR_B_DQSB_[8:0
]
DDR2/DDR3 Data Strobe Complements
SSTL-1.8/1.5
2.2.3
System Memory Miscellaneous Signals
Signal Name
Type
Description
I/O
A
DDR_RCOMPXPD
System Memory Pull-down RCOMP
I/O
A
DDR_RCOMPXPU
DDR_RCOMPYPD
DDR_RCOMPYPU
DDR_VREF
System Memory Pull-up RCOMP
System Memory Pull-down RCOMP
System Memory Pull-up RCOMP
System Memory Reference Voltage
System Memory Pull-up Reference Signal
System Memory Pull-down Reference Signal
DDR3 VCC_DDR Power OK
I/O
A
I/O
A
I
A
I
DDR_RCOMPVOH
DDR_RCOMPVOL
DDR3_DRAM_PWROK
DDR3_DRAMRSTB
A
I
A
I
A
O
DDR3 Reset Signal
SSTL-1.5
Datasheet
29
Signal Description
2.3
PCI Express* Interface Signals
Signal Name
Type
Description
Primary PCI Express Receive Differential Pair
PEG_RXN_[15:0]
PEG_RXP_[15:0]
I/O
The MCH supports a maximum width of x16 where all lanes are
used.
PCIE
Primary PCI Express Transmit Differential Pair
PEG_TXN_[15:0]
PEG_TXP_[15:0]
O
The MCH supports a maximum width of x16 where all lanes are
used.
PCIE
PEG2_RXN_[15:0]
PEG2_RXP_[15:0]
I/O
Secondary PCI Express Receive Differential Pair. The MCH
supports a maximum width of x16 where all lanes are used.
PCIE
PEG2_TXN_[15:0]
PEG2_TXP_[15:0]
O
Secondary PCI Express Transmit Differential Pair. The MCH
supports a maximum width of x16 where all lanes are used.
PCIE
I
EXP_COMPO
EXP_COMPI
EXP2_COMPO
EXP2_COMPI
Primary PCI Express Output Current Compensation
Primary PCI Express Input Current Compensation
Secondary PCI Express Output Current Compensation
Secondary PCI Express Input Current Compensation
A
I
A
I
A
I
A
2.4
Controller Link Interface Signals
Signal Name
CL_DATA
Type
Description
I/O
Controller Link Data (Bi-directional)
CMOS
I/O
CL_CLK
Controller Link Clock (Bi-directional)
Controller Link VREF
CMOS
I
CL_VREF
CL_RST#
CMOS
I
Controller Link Reset (Active low)
CMOS
30
Datasheet
Signal Description
2.5
Clocks, Reset, and Miscellaneous
Signal Name
Type
Description
Differential Host Clock In: These pins receive a differential
host clock from the external clock synthesizer. This clock is used
by all of the MCH logic that is in the Host clock domain.
HPL_CLKINP
HPL_CLKINN
I
CMOS
Differential Primary PCI Express Clock In: These pins
receive a differential 100 MHZ Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of Primary PCI Express and
DMI.
EXP_CLKINP
EXP_CLKINN
I
CMOS
Differential Secondary PCI Express Clock In: These pins
receive a differential 100 MHZ Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of Secondary PCI Express.
EXP2_CLKINP
EXP2_CLKINN
I
CMOS
Reset In: When asserted this signal will asynchronously reset
the MCH logic. This signal is connected to the PCIRST# output
of the ICH. All PCI Express output signals and DMI output
signals will also tri-state compliant to PCI Express Rev 2.0
specification.
I
RSTINB
SSTL
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3 V tolerant.
CL Power OK: When asserted, CL_PWROK is an indication to
the MCH that core power (VCC_CL) has been stable for at least
10 us.
I/O
CL_PWROK
EXP_SLR
SSTL
PCI Express* Static Lane Reversal/Form Factor
Selection: MCH’s PCI Express lane numbers are reversed to
differentiate BTX and ATX form factors
I
CMOS
0 = MCH PCI Express lane numbers are reversed (BTX)
1 = Normal operation (ATX)
Bus Speed Select: At the deassertion of PWROK, the value
sampled on these pins determines the expected frequency of
the bus.
I
BSEL[2:0]
MTYPE
CMOS
Memory Type: Determines DDR2 or DDR3 board
I
0 = DDR3
1 = DDR2
GTL+
I/O
SSTL
O
Power OK: When asserted, PWROK is an indication to the MCH
that core power has been stable for at least 10 us.
PWROK
ICH_SYNCB
ALLZTEST
XORTEST
ICH Sync: This signal synchronizes the MCH with the ICH.
HVCMOS
I
All Z Test: This signal is used for chipset Bed of Nails testing to
execute All Z Test. It is used as output for XOR Chain testing.
GTL+
I
XOR Chain Test: This signal is used for chipset Bed of Nails
testing to execute XOR Chain Test.
GTL+
In Circuit Test: These pins should be connected to test points
on the motherboard. They are internally shorted to the package
ground and can be used to determine if the corner balls on the
MCH are correctly soldered down to the motherboard. These
pins should NOT connect to ground on the motherboard. If
TEST[3:0] are not going to be used, they should be left as no
connects.
I/O
A
TEST[3:0]
Datasheet
31
Signal Description
2.6
2.7
Direct Media Interface
Signal Name
Type
Description
DMI_RXP_[3:0]
DMI_RXN_[3:0]
I
Direct Media Interface: Receive differential pair (RX). MCH-
ICH serial interface input
DMI
DMI_TXP_[3:0]
DMI_TXN_[3:0]
O
Direct Media Interface: Transmit differential pair (TX).
MCH-ICH serial interface output
DMI
Power and Grounds
Name
Voltage
Description
VCC
VTT
1.25 V
1.1 V/1.2 V
1.25 V
Core Power
Processor System Bus Power
PCI Express* and DMI Power
DDR2/DDR3 System Memory Power
DDR2/DDR3 System Clock Memory Power
3.3 V CMOS Power
VCC_EXP
VCC_DDR
VCC_CKDDR
VCC3_3
1.8 V/1.5V
1.8V/1.5V
3.3 V
VCCAPLL_EXP
VCCAPLL_EXP2
VCCA_hplL
VCCA_mpl
VCCABG_EXP
VCC_CL
1.25 V
Primary PCI Express PLL Analog Power
Secondary PCI Express PLL Analog Power
Host PLL Analog Power
1.25 V
1.25 V
1.25 V
System Memory PLL Analog Power
PCI Express* Analog Power
Controller Link Aux Power
3.3 V
1.25 V
VSS
0 V
Ground
§ §
32
Datasheet
System Address Map
3
System Address Map
The MCH supports 64 GB (36 bit) of host address space and 64 KB+3 of addressable
I/O space. There is a programmable memory address space under the 1 MB region
which is divided into regions which can be individually controlled with programmable
attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute
programming is described in the Register Description section. This section focuses on
how the memory space is partitioned and what the separate memory regions are used
for. I/O address space has simpler mapping and is explained near the end of this
section.
The MCH supports PCI Express* upper pre-fetchable base/limit registers. This allows
the PCI Express unit to claim IO accesses above 36 bit, complying with the PCI Express
Specification. Addressing of greater than 8 GB is allowed on either the DMI Interface or
PCI Express interface. The MCH supports a maximum of 8 GB of DRAM. No DRAM
memory will be accessible above 8 GB.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The MCH does not remap APIC or any other memory
spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the
appropriate value by BIOS. The reclaim base/reclaim limit registers remap logical
accesses bound for addresses above 4 GB onto physical addresses that fall within
DRAM.
The Address Map includes a number of programmable ranges:
• Device 0
— PXPEPBAR – Egress port registers. Necessary for setting up VC1 as an
isochronous channel using time based weighted round robin arbitration. (4 KB
window)
— MCHBAR – Memory mapped range for internal MCH registers. For example,
memory buffer register controls. (16 KB window)
— PCIEXBAR – Flat memory-mapped address spaced to access device
configuration registers. This mechanism can be used to access PCI
configuration space (0–FFh) and Extended configuration space (100h–FFFh) for
PCI Express devices. This enhanced configuration access mechanism is defined
in the PCI Express specification. (64 MB, 128 MB, or 256 MB window).
— DMIBAR –This window is used to access registers associated with the Direct
Media Interface (DMI) register memory range. (4 KB window)
• Device 1
— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access
window
— IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
Datasheet
33
System Address Map
• Device 3
— ME Control
• Device 6, Function 0
— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access
window
— IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designers' responsibility to limit memory population so that adequate PCI,
PCI Express, High BIOS, and PCI Express Memory Mapped space, and APIC
memory space can be allocated.
2. In the case of overlapping ranges with memory, the memory decode will be given
priority. This is an Intel Trusted Execution Technology requirement. It is necessary
to get Intel TET protection checks, avoiding potential attacks.
3. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
4. Accesses to overlapped ranges may produce indeterminate results.
5. The only peer-to-peer cycles allowed below the top of Low Usable memory (register
TOLUD) are DMI Interface to PCI Express range writes.
Figure 2 represents system memory address map in a simplified form.
34
Datasheet
System Address Map
Figure 2.
System Address Ranges
NOTE: Do not follow the EP UMA requirement.
Datasheet
35
System Address Map
3.1
Legacy Address Range
This area is divided into the following address regions:
• 0 - 640 KB – DOS Area
• 640 - 768 KB – Legacy Video Buffer Area
• 768 - 896 KB in 16 KB sections (total of 8 sections) – Expansion Area
• 896 -960 KB in 16 KB sections (total of 4 sections) – Extended System BIOS Area
• 960 KB - 1 MB Memory – System BIOS Area
Figure 3.
DOS Legacy Address Range
1 MB
000F_FFFFh
000F_0000h
000E_FFFFh
000E_0000h
000D_FFFFh
System BIOS (Upper)
64 KB
960 KB
896 KB
Extended System BIOS (Lower)
64 KB (16 KB x 4)
Expansion Area
128 KB (16 KB x 8)
000C_0000h
000B_FFFFh
768 KB
640 KB
Legacy Video Area
(SMM Memory)
128 KB
000A_0000h
0009_FFFFh
DOS Area
0000_0000h
3.1.1
DOS Range (0h – 9_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to
the main memory controlled by the MCH.
36
Datasheet
System Address Map
3.1.2
Expansion Area (C_0000h-D_FFFFh)
This 128 KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight
16 KB segments. Each segment can be assigned one of four Read/Write states: read-
only, write-only, read/write, or disabled. Typically, these blocks are mapped through
MCH and are subtractive decoded to ISA space. Memory that is disabled is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table 2.
Expansion Area Memory Segments
Memory Segments
Attributes
Comments
0C0000h – 0C3FFFh
0C4000h – 0C7FFFh
0C8000h – 0CBFFFh
0CC000h – 0CFFFFh
0D0000h – 0D3FFFh
0D4000h – 0D7FFFh
0D8000h – 0DBFFFh
0DC000h – 0DFFFFh
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
3.1.3
Extended System BIOS Area (E_0000h–E_FFFFh)
This 64 KB area (000E_0000h – 000E_FFFFh) is divided into four 16 KB segments. Each
segment can be assigned independent read and write attributes so it can be mapped
either to main DRAM or to DMI Interface. Typically, this area is used for RAM or ROM.
Memory segments that are disabled are not remapped elsewhere.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table 3.
Extended System BIOS Area Memory Segments
Memory Segments
Attributes
Comments
0E0000h – 0E3FFFh
0E4000h – 0E7FFFh
0E8000h – 0EBFFFh
0EC000h – 0EFFFFh
WE RE
WE RE
WE RE
WE RE
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
Datasheet
37
System Address Map
3.1.4
System BIOS Area (F_0000h–F_FFFFh)
This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can be
assigned read and write attributes. It is by default (after reset) Read/Write disabled
and cycles are forwarded to DMI Interface. By manipulating the Read/Write attributes,
the MCH can “shadow” BIOS into the main DRAM. When disabled, this segment is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table 4.
System BIOS Area Memory Segments
Memory Segments
Attributes
Comments
0F0000h – 0FFFFFh
WE RE
BIOS Area
3.1.5
PAM Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory
Area.
The MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be
IWB cycles targeting DMI. However, DMI becomes the default target for processor and
DMI originated accesses to disabled segments of the PAM region. If the MTRRs covering
the PAM regions are set to WB or RD it is possible to get IWB cycles targeting DMI. This
may occur for processor originated cycles (in a DP system) and for DMI originated
cycles to disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is “Read Disabled” the default target for the Memory Read
becomes DMI. The IWB associated with this cycle will cause the MCH to hang.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
3.2
Main Memory Address Range (1MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is
permitted to be accessible by the MCH (as programmed in the TOLUD register). All
accesses to addresses within this range will be forwarded by the MCH to the DRAM
unless it falls into the optional TSEG, or optional ISA Hole.
38
Datasheet
System Address Map
Figure 4.
Main Memory Address Range
8 GB
Main Memory
.
.
.
.
.
FFFF_FFFFh
4 GB
FLASH
APIC
LT
PCI Memory Range
TSEG (1MB/2MB/8MB,
optional)
Main Memory
0100_0000h
00F0_0000h
ISA Hole (optional)
Main Memory
0010_0000h
0h
DOS Compatibility Memory
3.2.1
ISA Hole (15 MB –16 MB)
A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable in
Device 0 space. Accesses within this hole are forwarded to the DMI Interface. The
range of physical DRAM memory disabled by opening the hole is not remapped to the
top of the memory – that physical DRAM space is not accessible. This 15–16 MB hole is
an optionally enabled ISA hole.
The ISA Hole is used by validation and customer SV teams for some of their test cards.
That is why it is being supported. There is no inherent BIOS request for the 15–16 MB
window.
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System Address Map
3.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below stolen memory, which is
at the top of Low Usable physical memory (TOLUD). SMM-mode processor accesses to
enabled TSEG access the physical DRAM at the same address. Non-processor
originated accesses are not allowed to SMM space. PCI Express, and DMI originated
cycles to enabled SMM space are handled as invalid cycle type with reads and writes to
location 0 and byte enables turned off for writes. When the extended SMRAM space is
enabled, processor accesses to the TSEG range without SMM attribute or without WB
attribute are also forwarded to memory as invalid accesses (see table 8). Non-SMM-
mode Write Back cycles that target TSEG space are completed to DRAM for cache
coherency. When SMM is enabled the maximum amount of memory available to the
system is equal to the amount of physical DRAM minus the value in the TSEG register
which is fixed at 1 MB, 2 MB, or 8 MB.
3.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode,
and stolen memory. It is the responsibility of BIOS to properly initialize these
regions. The following table details the location and attributes of the regions.
Enabling/Disabling these ranges are described in the MCH Control Register Device 0
(GCC).
Figure 5.
Pre-allocated Memory Example for 64 MB DRAM, 1 MB stolen and 1 MB TSEG
Memory Segments
Attributes
Comments
0000_0000h – 03CF_FFFFh
R/W
Available System Memory 61 MB
SMM Mode Only -
processor Reads
TSEG Address Range & Pre-allocated
memory
03D0_0000h – 03DF_FFFFh
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System Address Map
3.3
PCI Memory Address Range (TOLUD – 4 GB)
This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
Device 0 exceptions are:
• Addresses decoded to the egress port registers (PXPEPBAR)
• Addresses decoded to the memory mapped range for internal MCH registers
(MCHBAR)
• Addresses decoded to the flat memory-mapped address spaced to access device
configuration registers (PCIEXBAR)
• Addresses decoded to the registers associated with the Direct Media Interface
(DMI) register memory range. (DMIBAR)
With PCI Express port, there are two exceptions to this rule.
• Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
MLIMIT1, registers are mapped to PCI Express.
• Addresses decoded to the PCI Express prefetchable Memory Window defined by the
PMBASE1, PMLIMIT1, registers are mapped to PCI Express.
In an Intel ME configuration, there are exceptions to this rule:
1. Addresses decoded to the ME Keyboard and Text MMIO range (EPKTBAR)
2. Addresses decoded to the ME HECI MMIO range (EPHECIBAR)
3. Addresses decoded to the ME HECI2 MMIO range (EPHECI2BAR)
Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The
exceptions listed above for the PCI Express ports MUST NOT overlap with these
ranges.
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System Address Map
Figure 6.
PCI Memory Address Range
4 GB
FFFF_FFFFh
FFE0_0000h
High BIOS
4 GB – 2 MB
DMI Interface
(subtractive decode)
FEF0_0000h
4 GB – 17 MB
4 GB – 18 MB
4 GB – 19 MB
FSB Interrupts
FEE0_0000h
FED0_0000h
DMI Interface
(subtractive decode)
Local (CPU) APIC
I/O APIC
Optional HSEG
FEC8_0000h
FEC0_0000h
FEDA_0000h to
FEDB_FFFFh
4 GB – 20 MB
DMI Interface
(subtractive decode)
F000_0000h
E000_0000h
4 GB – 256 MB
Possible address
range/size (not
ensured)
PCI Express Configuration
Space
4 GB – 512 MB
BARs and
PCI Express
Port could be
here.
DMI Interface
(subtractive decode)
TOLUD
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System Address Map
3.3.1
APIC Configuration Space (FEC0_0000h–FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the ICH portion of the chipset.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The MCH optionally supports additional I/O APICs behind the PCI Express port. When
enabled via the PCI Express Configuration register (Device 1 Offset 200h), the PCI
Express port will positively decode a subset of the APIC configuration space –
specifically FEC8_0000h thru FECF_FFFFh. Memory request to this range would then be
forwarded to the PCI Express port. When disabled, any access within entire APIC
Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
3.3.2
HSEG (FEDA_0000h–FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window
to SMM Memory. It is sometimes called the High SMM memory space. SMM-mode
processor accesses to the optionally enabled HSEG are remapped to 000A_0000h –
000B_FFFFh. Non-SMM-mode processor accesses to enabled HSEG are considered
invalid and are terminated immediately on the FSB. The exceptions to this rule are
Non-SMM-mode Write Back cycles which are remapped to SMM space to maintain
cache coherency. PCI Express and DMI originated cycles to enabled SMM space are not
allowed. Physical DRAM behind the HSEG transaction address is not remapped and is
not accessible. All cacheline writes with WB attribute or Implicit write backs to the
HSEG range are completed to DRAM like an SMM cycle.
3.3.3
3.3.4
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express or DMI may issue a Memory Write to 0FEEx_xxxxh. The MCH will
forward this Memory Write along with the data to the FSB as an Interrupt Message
Transaction. The MCH terminates the FSB transaction by providing the response and
asserting HTRDYB. This Memory Write cycle does not go to DRAM.
High BIOS Area
The top 2 MB (FFE0_0000h – FFFF_FFFFh) of the PCI Memory Address Range is
reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20
alias of the system BIOS. The processor begins execution from the High BIOS after
reset. This region is mapped to DMI Interface so that the upper subset of this region
aliases to 16 MB–256 KB range. The actual address space required for the BIOS is less
than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full
2 MB must be considered.
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System Address Map
3.4
Main Memory Address Space (4 GB to TOUUD)
The MCH supports 36 bit addressing. The maximum main memory size supported is
8 GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main memory
size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and
RECLAIMBASE/RECLAIMLIMIT registers become relevant.
The new reclaim configuration registers exist to reclaim lost main memory space. The
greater than 32 bit reclaim handling will be handled similar to other MCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid
cycles by PCI Express and DMI.
Top of Memory
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory-mapped I/O above
TOM). TOM is used to allocate the Intel Management Engine's stolen memory. The Intel
ME stolen size register reflects the total amount of physical memory stolen by the Intel
ME. The ME stolen memory is located at the top of physical memory. The ME stolen
memory base is calculated by subtracting the amount of memory stolen by the Intel ME
from TOM.
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of
addressable DRAM. If reclaim is disabled, TOUUD will reflect TOM minus Intel ME stolen
size. If reclaim is enabled, then it will reflect the reclaim limit. Also, the reclaim base
will be the same as TOM minus ME stolen memory size to the nearest 64 MB alignment.
TOLUD register is restricted to 4 GB memory (A[31:20]), but the MCH can support up
to 16 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range in between the 4 GB boundary and the top of
physical memory. This identifies memory that can be directly accessed (including
reclaim address calculation) which is useful for memory access indication, early path
indication, and trusted read indication. When reclaim is enabled, TOLUD must be
64 MB aligned, but when reclaim is disabled, TOLUD can be 1 MB aligned.
C1DRB3 cannot be used directly to determine the effective size of memory as the
values programmed in the DRBs depend on the memory mode (stacked, interleaved).
The Reclaim Base/Limit registers also can not be used because reclaim can be disabled.
The C0DRB3 register is used for memory channel identification (channel 0 vs. channel
1) in the case of stacked memory.
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System Address Map
3.4.1
Memory Re-claim Background
The following are examples of Memory Mapped IO devices are typically located below
4 GB:
• High BIOS
• HSEG
• TSEG
• XAPIC
• Local APIC
• FSB Interrupts
• Mbase/Mlimit
• Memory Mapped IO space that supports only 32 B addressing
The MCH provides the capability to re-claim the physical memory overlapped by the
Memory Mapped I/O logical address space. The MCH re-maps physical memory from
the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent
sized logical address range located just below the Intel ME's stolen memory.
3.4.2
Memory Reclaiming
An incoming address (referred to as a logical address) is checked to see if it falls in the
memory re-map window. The bottom of the re-map window is defined by the value in
the RECLAIMBASE register. The top of the re-map window is defined by the value in the
RECLAIMLIMIT register. An address that falls within this window is reclaimed to the
physical memory starting at the address defined by the TOLUD register. The TOLUD
register must be 64M aligned when RECLAIM is enabled, but can be 1M aligned when
reclaim is disabled.
3.5
PCI Express* Configuration Address Space
There is a device 0 register, PCIEXBAR, which defines the base address for the
configuration space associated with all devices and functions that are potentially a part
of the PCI Express root complex hierarchy. The size of this range will be programmable
for the MCH. BIOS must assign this address range such that it will not conflict with any
other address ranges.
See the configuration portion of this document for more details.
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System Address Map
3.6
PCI Express* Address Space
The MCH can be programmed to direct memory accesses to the PCI Express interface
when addresses are within either of two ranges specified via registers in MCH’s Device
1 configuration space.
• The first range is controlled via the Memory Base Register (MBASE) and Memory
Limit Register (MLIMIT) registers.
• The second range is controlled via the Pre-fetchable Memory Base (PMBASE) and
Pre-fetchable Memory Limit (PMLIMIT) registers.
Conceptually, address decoding for each range follows the same basic concept. The top
12 bits of the respective Memory Base and Memory Limit registers correspond to
address bits A[31:20] of a memory address . For the purpose of address decoding, the
MCH assumes that address bits A[19:0] of the memory base are zero and that address
bits A[19:0] of the memory limit address are FFFFFh. This forces each memory address
range to be aligned to 1MB boundary and to have a size granularity of 1 MB.
The MCH positively decodes memory accesses to PCI Express memory address space
as defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
The window size is programmed by the plug-and-play configuration software. The
window size depends on the size of memory claimed by the PCI Express device.
Normally these ranges will reside above the Top-of-Low Usable-DRAM and below High
BIOS and APIC address ranges. They MUST reside above the top of low memory
(TOLUD) if they reside below 4 GB and MUST reside above top of upper memory
(TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space.
It is essential to support a separate Pre-fetchable range in order to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
Note that the MCH Device 1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express that
require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the device 1 PCICMD1
register to enable the memory base/limit and pre-fetchable base/limit windows.
For the MCH, the upper PMUBASE1/PMULIMIT1 registers have been implemented for
PCI Express Spec compliance. The MCH locates MMIO space above 4 GB using these
registers.
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System Address Map
3.7
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and
Top of Memory Segment (TSEG). System Management RAM space provides a memory
area that is available for the SMI handlers and code and data storage. This memory
resource is normally hidden from the system OS so that the processor has immediate
access to this memory space upon entry to SMM. MCH provides three SMRAM options:
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below stolen
memory.
The above 1 MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
Note:
DMI Interface and PCI Express masters are not allowed to access the SMM space.
3.7.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the processor
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High, and TSEG. The Compatible and
TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space is a different address range. Note that the High DRAM space is the
same as the Compatible Transaction Address space. Table 5 describes three unique
address ranges.
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Table 5.
Transaction Address Ranges – Compatible, High, and TSEG
SMM Space Enabled
Transaction Address Space
DRAM Space (DRAM)
Compatible
High
000A_0000h to 000B_FFFFh
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD–STOLEN–TSEG) to
TOLUD–STOLEN
(TOLUD–STOLEN–TSEG) to
TOLUD–STOLEN
TSEG
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System Address Map
3.7.2
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI Interface and
PCI-Express). This is a BIOS responsibility.
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
5. Any address translated through the GMADR TLB must not target DRAM from
A_0000–F_FFFFh.
3.7.3
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM
space is effectively disabled. Processor originated accesses to the Compatible SMM
space are forwarded to PCI Express; otherwise they are forwarded to the DMI
Interface. PCI Express and DMI Interface originated accesses are never allowed to
access SMM space.
Table 6.
SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Disable
Enable
Disable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Disable
Enable
Enable
Disabled
Disabled
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3.7.4
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS software
can use this bit to initialize SMM code at powerup. The D_LCK bit limits the SMM range
access to only SMM mode accesses. The D_CLS bit causes SMM (both CSEG and TSEG)
data accesses to be forwarded to the DMI Interface or PCI Express. The SMM software
can use this bit to write to video memory while running SMM code out of DRAM.
Table 7.
SMM Control Table
Processor
in SMM
Mode
SMM Code
Access
SMM Data
Access
G_SMRAME
D_LCK
D_CLS
D_OPEN
0
1
1
1
1
1
1
1
1
x
0
0
0
0
0
1
1
1
X
X
0
0
1
1
X
0
1
x
0
0
1
0
1
x
x
x
x
0
1
x
1
x
0
1
1
Disable
Disable
Enable
Enable
Enable
Invalid
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Invalid
Disable
Enable
Disable
3.7.5
3.7.6
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI Interface
originated transactions are not allowed to SMM space.
Processor WB Transaction to an Enabled SMM Address
Space
Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space must
be written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
3.7.7
SMM Access Through TLB
Accesses through TLB address translation to enabled SMM DRAM space are not allowed.
Writes will be routed to Memory address 000C_0000h with byte enables de-asserted
and reads will be routed to Memory address 000C_0000h. If a TLB translated address
hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the TLB address translation. If a TLB translated address hits
enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through GMADR range will be snooped.
Assesses to GMADR linear range (defined via fence registers) are supported. PCI
Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when
translated, the resulting physical address is to enabled SMM DRAM space, the request
will be remapped to address 000C_0000h with de-asserted byte enables.
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System Address Map
PCI Express and DMI Interface read accesses to the GMADR range are not supported
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
Fetches are always decoded (at fetch time) to ensure not in SMM (actually, anything
above base of TSEG or 640 K–1 M). Thus, they will be invalid and go to address
000C_0000h, but that isn’t specific to PCI Express or DMI; it applies to processor. Also,
since the GMADR snoop would not be directly to the SMM space, there wouldn’t be a
writeback to SMM. In fact, the writeback would also be invalid (because it uses the
same translation) and go to address 000C_0000h.
3.8
3.9
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into MCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as a read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are
routed accordingly.
I/O Address Space
The MCH does not support the existence of any other I/O devices beside itself on the
processor bus. The MCH generates either DMI Interface or PCI Express bus cycles for
all processor I/O accesses that it does not claim. Within the host bridge, the MCH
contains two internal registers in the processor I/O space, Configuration Address
Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA).
These locations are used to implement configuration space access mechanism.
The processor allows 64 K+3 bytes to be addressed within the I/O space. The MCH
propagates the processor I/O address without any translation on to the destination bus
and therefore provides addressability for 64K+3 byte locations. Note that the upper 3
locations can be accessed only during I/O address wrap-around when processor bus
HAB_16 address signal is asserted. HAB_16 is asserted on the processor bus whenever
an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HAB_16 is
also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI Interface bus unless they fall within the PCI Express I/O address
range as defined by the mechanisms explained below. I/O writes are NOT posted.
Memory writes to ICH or PCI Express are posted. The PCICMD1 register can disable the
routing of I/O cycles to the PCI Express.
The MCH responds to I/O cycles initiated on PCI Express or DMI with an UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to Memory address 000C_0000h so a completion is
naturally generated (whether the original request was a read or write). The transaction
will complete with an UR completion status.
I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from
the processor as 1 transaction. The MCH will break this into 2 separate transactions.
I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed
to be split into 2 transactions by the processor.
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3.9.1
PCI Express* I/O Address Mapping
The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express
bus interface when processor initiated I/O cycle addresses are within the PCI Express I/
O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O
Limit Address (IOLIMIT) registers in MCH Device 1 configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the
respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an
I/O address. For the purpose of address decoding, the MCH assumes that lower 12
address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the I/O
limit address are FFFh. This forces the I/O address range alignment to 4 KB boundary
and produces a size granularity of 4 KB.
The MCH positively decodes I/O accesses to PCI Express I/O address space as defined
by the following equation:
I/O_Base_Address ≤ Processor I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
Note that the MCH Device 1 and/or Device 6 I/O address range registers defined above
are used for all I/O space allocation for any devices requiring such a window on PCI
Express.
The PCICMD1 register can disable the routing of I/O cycles to PCI Express.
§ §
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System Address Map
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MCH Register Description
4
MCH Register Description
The MCH contains two sets of software accessible registers, accessed via the Host
processor I/O address space: Control registers and internal configuration registers.
• Control registers are I/O mapped into the processor I/O space, which control
access to PCI and PCI Express configuration space (see Chapter 6).
• Internal configuration registers residing within the MCH are partitioned into two
logical device register sets (“logical” since they reside within a single physical
device). The first register set is dedicated to Host Bridge functionality (i.e., DRAM
configuration, other chipset operating parameters and optional features). The
second register block is dedicated to Host-to-PCI Express Bridge functions (controls
PCI Express interface configurations and operating parameters).
The MCH internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the processor. The registers that reside within
the lower 256 bytes of each device can be accessed as Byte, Word (16-bit), or DWord
(32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only be
accessed as a DWord. All multi-byte numeric fields use “little-endian” ordering (i.e.,
lower addresses contain the least significant parts of the field). Registers that reside in
bytes 256 through 4095 of each device may only be accessed using memory-mapped
transactions in DWord (32-bit) quantities.
Some of the MCH registers described in this section contain reserved bits. These bits
are labeled “Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, and write
operation for the Configuration Address Register.
In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host Bridge entity that are marked either “Reserved” or
“Intel Reserved”. The MCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to “Reserved”
registers have no effect on the MCH. Registers that are marked as “Intel Reserved”
must not be modified by system software. Writes to “Intel Reserved” registers may
cause system failure. Reads from “Intel Reserved” registers may return a non-zero
value.
Upon a Full Reset, the MCH sets its entire set of internal configuration registers to
predetermined default states. Some register values at reset are determined by external
strapping options. The default state represents the minimum functionality feature set
required to successfully bringing up the system. Hence, it does not represent the
optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, operating
parameters and optional system features that are applicable, and to program the MCH
registers accordingly.
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MCH Register Description
4.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
Description
RO
Read Only bit(s). Writes to these bits have no effect.
RO/S
Read Only / Sticky. Writes to these bits have no effect. These are status bits only. Bits are
not returned to their default values by “warm” reset, but will be reset with a cold/
complete reset (for PCI Express related bits, a cold reset is “Power Good Reset” as
defined in the PCI Express specification).
RS/WC
Read Set / Write Clear bit(s). These bits are set to ‘1’ when read and then will continue to
remain set until written. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a
write of ‘0’ has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A write
of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this bit.
A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect.
Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI
Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express
Specification).
R/W/L
R/W/K
R/W/L
Read / Write / Lockable bit(s). These bits can be read and written. Additionally, there is a
bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field
from being writeable (bit field becomes Read Only).
Read / Write / Key bit(s). These bits can be read and written by software. Additionally this
bit when set, prohibits some other bit field(s) from being writeable (bit fields become
Read Only).
Read / Write / Lockable bit(s). These bits can be read and written. Additionally there is a
bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field
from being writeable (bit field becomes Read Only).
R/W/S
R/WSC
R/WSC/L
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a
cold reset is “Power Good Reset” as defined in the PCI Express Specification).
Read / Write Self Clear bit(s). These bits can be read and written. When the bit is ‘1’,
hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than any
subsequent read could retrieve a ‘1’.
Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the bit
is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than
any subsequent read could retrieve a ‘1’. Additionally there is a bit (which may or may not
be a bit marked R/W/L) that, when set, prohibits this bit field from being writeable (bit
field becomes Read Only).
R/WO
W
Write Once bit(s). Once written, bits with this attribute become Read Only. These bits can
only be cleared by a Reset.
Write Only. Whose bits may be written, but will always-return zeros when read. They are
used for write side effects. Any data written to these registers cannot be retrieved.
54
Datasheet
MCH Register Description
4.2
Configuration Process and Registers
4.2.1
Platform Configuration Structure
The DMI physically connects the MCH and the Intel ICH9; thus, from a configuration
standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the MCH
and the ICH appear to be on PCI bus 0.
Note:
The ICH9 internal LAN controller does not appear on bus 0 – it appears on the external
PCI bus and this number is configurable.
The system’s primary PCI expansion bus is physically attached to the ICH and from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI
bridge; therefore, it has a programmable PCI Bus number. The PCI Express interface
appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a
device resident on PCI bus 0.
Note:
A physical PCI bus 0 does not exist; DMI and the internal devices in the MCH and ICH
logically constitute PCI Bus 0 to configuration software (see Figure 7).
Figure 7.
Conceptual Platform PCI Configuration Diagram
CPU
MCH
PCI Configuration Window
in I/O Space
Primary Host-PCI
Express Bridge
Bus 0 Device 1
DRAM Controller
Interface Device
Bus 0
Device 0
Manageability
Engine Device
Bus 0
Secondary Host-
PCI Express Bridge
Bus 0 Device 6
Device 3
Direct Media Interface
Datasheet
55
MCH Register Description
The MCH contains four PCI devices within a single physical component. The
configuration registers for the four devices are mapped as devices residing on PCI
bus 0.
• Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control (including thermal/throttling control),
and configuration for the DMI and other MCH specific registers.
• Device 1: Primary Host-PCI Express Bridge. Logically this appears as a
“virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express
Specification Rev 1.0. Device 1 contains the standard PCI-to-PCI bridge registers
and the standard PCI Express/PCI configuration registers (including the PCI
Express memory address mapping). It also contains Isochronous and Virtual
Channel controls in the PCI Express extended configuration space.
• Device 3: Manageability Engine Device. Logically, this appears as a PCI device
residing on PCI bus 0. Physically, device 3.
• Device 6: Secondary Host-PCI Express Bridge. Logically this appears as a
“virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express
Specification Rev 1.0. Device 6 contains the standard PCI-to-PCI bridge registers
and the standard PCI Express/PCI configuration registers (including the PCI
Express memory address mapping). It also contains Isochronous and Virtual
Channel controls in the PCI Express extended configuration space.
4.3
Configuration Mechanisms
The processor is the originator of configuration cycles so the FSB is the only interface in
the platform where these mechanisms are used. The MCH translates transactions
received through both configuration mechanisms to the same format.
4.3.1
Standard PCI Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to configuration
cycles.
The PCI specification defines a slot based "configuration space" that allows each device
to contain up to 8 functions with each function containing up to 256 8-bit configuration
registers. The PCI specification defines two bus cycles to access the PCI configuration
space: Configuration Read and Configuration Write. Memory and I/O spaces are
supported directly by the processor. Configuration space is supported by a mapping
mechanism implemented within the MCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at
I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
though 0CFFh). To reference a configuration register a DW I/O write cycle is used to
place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus,
the function within the device and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration
cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space
specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will
result in the MCH translating the CONFIG_ADDRESS into the appropriate configuration
cycle.
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Datasheet
MCH Register Description
The MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration
registers, DMI or PCI Express.
4.3.2
PCI Express Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3 compatible region, which consists of the
first 256B of a logical device’s configuration space and a PCI Express extended region,
which consists of the remaining configuration space.
The PCI compatible region can be accessed using either the Standard PCI Configuration
Mechanism or using the PCI Express Enhanced Configuration Mechanism described in
this section. The extended configuration registers may only be accessed using the PCI
Express Enhanced Configuration Mechanism. To maintain compatibility with PCI
configuration addressing mechanisms, system software must access the extended
configuration space using 32-bit operations (32-bit aligned) only. These 32-bit
operations include byte enables allowing only appropriate bytes within the DWord to be
accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism are
equivalent.
The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. There is a register, PCIEXBAR, that
defines the base address for the block of addresses below 4 GB for the configuration
space associated with busses, devices and functions that are potentially a part of the
PCI Express root complex hierarchy. In the PCIEXBAR register there exists controls to
limit the size of this reserved memory mapped space. 256 MB is the amount of address
space required to reserve space for every bus, device, and function that could possibly
exist. Options for 128 MB and 64 MB exist in order to free up those addresses for other
uses. In these cases the number of busses and all of their associated devices and
functions are limited to 128 or 64 busses respectively.
The PCI Express Configuration Transaction Header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
Datasheet
57
MCH Register Description
Figure 8.
Memory Map to PCI Express Device Configuration Space
FFFFFFFh
FFFFFh
FFFh
7FFFh
Bus 255
Device 31
Function 7
PCI Express*
Extended
Configuration
Space
FFFFh
7FFFh
1FFFh
FFFh
FFh
PCI
1FFFFFh
Bus 1
Bus 0
Function 1
Function 0
Compatible
Config Space
Device 1
Device 0
FFFFFh
0h
3Fh
PCI
Compatible
Config Header
Located By PCI
Express* Base
Address
MemMap PCIExpress
As with PCI devices, each device is selected based on decoded address information that
is provided as a part of the address portion of Configuration Request packets. A PCI
Express device will decode all address information fields (bus, device, function and
extended address numbers) to provide access to the correct register.
To access this space (steps 1, 2, 3 are done only once by BIOS),
1. Use the PCI compatible configuration mechanism to enable the PCI Express
enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register.
2. Use the PCI compatible configuration mechanism to write an appropriate PCI
Express base address into the PCIEXBAR register.
3. Calculate the host address of the register you wish to set using (PCI Express base
+ (bus number * 1 MB) + (device number * 32KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address).
4. Use a memory write or memory read cycle to the calculated host address to write
or read that register.
4.4
Routing Configuration Accesses
The MCH supports two PCI related interfaces: DMI and PCI Express. The MCH is
responsible for routing PCI and PCI Express configuration cycles to the appropriate
device that is an integrated part of the MCH or to one of these two interfaces.
Configuration cycles to the ICH internal devices and Primary PCI (including downstream
devices) are routed to the ICH via DMI. Configuration cycles to the PCI Express PCI
compatibility configuration space are routed to the PCI Express port device or
associated link.
58
Datasheet
MCH Register Description
Figure 9.
MCH Configuration Cycle Flow Chart
DW I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Yes
Bus# = 0
No
MCH Generates
Type 1 Access
to PCI Express
Bus# > SEC BUS
Device# = 0 &
Function# = 0
Yes
Yes
MCH Claims
Bus# SUB BUS
≤
in MCH Dev 1
No
No
Device# = 1 &
Dev # 1 Enabled
& Function# = 0
Bus# =
SECONDARYBUS
in MCH Dev 1
Yes
Yes
MCH Claims
No
No
MCH Generates
DMI Type 1
MCH Generates
DMI Type 0
Configuration Cycle
Configuration Cycle
MCH Generates
Type 0 Access
to PCI Express
Yes
Device# = 0
No
MCH allows cycle to
go to DMI resulting
in Master Abort
4.4.1
Internal Device Configuration Accesses
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus #0 device.
If the targeted PCI Bus 0 device exists in the MCH and is not disabled, the configuration
cycle is claimed by the appropriate device.
Datasheet
59
MCH Register Description
4.4.2
Bridge Related Configuration Accesses
Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs
(Transaction Layer Packets):
• Bus Number [7:0] is Header Byte 8 [7:0]
• Device Number [4:0] is Header Byte 9 [7:3]
• Function Number [2:0] is Header Byte 9 [2:0]
And special fields for this type of TLP:
• Extended Register Number [3:0] is Header Byte 10 [3:0]
• Register Number [5:0] is Header Byte 11 [7:2]
See the PCI Express specification for more information on both the PCI 2.3 compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
4.4.2.1
PCI Express Configuration Accesses
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI
Express Type 0 Configuration TLP is generated on the PCI Express link targeting the
device directly on the opposite side of the link. This should be Device 0 on the bus
number assigned to the PCI Express link (likely Bus 1).
The device on other side of link must be Device 0. The MCH will Master Abort any
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but does not match the Device 1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
PCI Express Configuration Writes:
• Internally the host interface unit will translate writes to PCI Express extended
configuration space to configuration writes on the backbone.
• Writes to extended space are posted on the FSB, but non-posted on the PCI
Express or DMI (i.e., translated to config writes)
4.4.2.2
DMI Configuration Accesses
Accesses to disabled MCH internal devices, bus numbers not claimed by the Host-PCI
Express bridge, or PCI Bus #0 devices not part of the MCH will subtractively decode to
the ICH and consequently be forwarded over the DMI via a PCI Express configuration
TLP.
If the Bus Number is zero, the MCH will generate a Type 0 Configuration Cycle TLP on
DMI. If the Bus Number is non-zero, and falls outside the range claimed by the Host-
PCI Express bridge, the MCH will generate a Type 1 Configuration Cycle TLP on DMI.
The ICH routes configurations accesses in a manner similar to the MCH. The ICH
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus #0 may be claimed by an internal device. The
ICH compares the non-zero Bus Number with the Secondary Bus Number and
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Datasheet
MCH Register Description
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
Configuration accesses that are forwarded to the ICH9, but remain unclaimed by any
device or bridge will result in a master abort.
4.5
I/O Mapped Registers
The MCH contains two registers that reside in the processor I/O address space − the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
4.5.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
0CF8h Accessed as a DW
00000000h
R/W
32 bits
Size:
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or
Word reference will "pass through" the Configuration Address Register and DMI onto
the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus
Number, Device Number, Function Number, and Register Number for which a
subsequent configuration access is intended.
Access &
Default
Bit
Description
Configuration Enable (CFGE):
R/W
0b
31
0 = Disable
0 = Enable.
30:24
Reserved
Bus Number: If the Bus Number is programmed to 00h the target of the
Configuration Cycle is a PCI Bus 0 agent. If this is the case and the MCH
is not the target (i.e., the device number is ≥ 2), then a DMI Type 0
Configuration Cycle is generated.
If the Bus Number is non-zero and does not fall within the ranges
enumerated by device 1’s Secondary Bus Number or Subordinate Bus
Number Register, then a DMI Type 1 Configuration Cycle is generated.
If the Bus Number is non-zero and matches the value programmed into
the Secondary Bus Number Register of device 1, a Type 0 PCI
configuration cycle will be generated on PCI Express.
R/W
00h
23:16
If the Bus Number is non-zero, greater than the value in the Secondary
Bus Number register of device 1 and less than or equal to the value
programmed into the Subordinate Bus Number Register of device 1 a
Type 1 PCI configuration cycle will be generated on PCI Express.
This field is mapped to byte 8 [7:0] of the request header format during
PCI Express Configuration cycles and A[23:16] during the DMI Type 1
configuration cycles.
Datasheet
61
MCH Register Description
Access &
Default
Bit
Description
Device Number: This field selects one agent on the PCI bus selected by
the Bus Number. When the Bus Number field is “00” the MCH decodes the
Device Number field. The MCH is always Device Number 0 for the Host
bridge entity, Device Number 1 for the Host-PCI Express entity.
Therefore, when the Bus Number =0 and the Device Number equals 0, 1,
or 2 the internal MCH devices are selected.
R/W
00h
15:11
This field is mapped to byte 6 [7:3] of the request header format during
PCI Express Configuration cycles and A [15:11] during the DMI
configuration cycles.
Function Number: This field allows the configuration registers of a
particular function in a multi-function device to be accessed. The MCH
ignores configuration cycles to its internal devices if the function number
is not equal to 0 or 1.
R/W
10:8
000b
This field is mapped to byte 6 [2:0] of the request header format during
PCI Express Configuration cycles and A[10:8] during the DMI
configuration cycles.
Register Number: This field selects one register within a particular Bus,
Device, and Function as specified by the other fields in the Configuration
Address Register.
R/W
00h
7:2
1:0
This field is mapped to byte 7 [7:2] of the request header format during
PCI Express Configuration cycles and A[7:2] during the DMI
Configuration cycles.
Reserved
4.5.2
CONFIG_DATA—Configuration Data Register
I/O Address:
Default Value:
Access:
0CFCh
00000000h
R/W
Size:
32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents
of CONFIG_ADDRESS.
Access &
Default
Bit
Description
Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS
is 1, any I/O access to the CONFIG_DATA register will produce a
configuration transaction using the contents of CONFIG_ADDRESS to
determine the bus, device, function, and offset of the register to be
accessed.
R/W
31:0
0000 0000 h
§
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Datasheet
DRAM Controller Registers (D0:F0)
5
DRAM Controller Registers
(D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Warning:
Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved registers may return non-zero values. Writes to reserved locations
may cause system failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or
implemented in this component are simply not included in this document. The
reserved/unimplemented space in the PCI configuration header space is not
documented as such in this summary.
Table 8.
DRAM Controller Register Address Map
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
0–1h
2–3h
4–5h
6–7h
8h
VID
DID
Vendor Identification
8086h
29E0h
0006h
0090h
00h
RO
RO
Device Identification
PCI Command
PCICMD
PCISTS
RID
RO, RW
RO, RWC
RO
PCI Status
Revision Identification
Class Code
9–Bh
Dh
CC
060000h
00h
RO
MLT
Master Latency Timer
Header Type
RO
Eh
HDR
00h
RO
2C–2Dh
2E–2Fh
34h
SVID
SID
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
0000h
0000h
E0h
RWO
RWO
RO
CAPPTR
0000000000
000000h
40–47h
PXPEPBAR
PCI Express Egress Port Base Address
RO, RW/L
MCH Memory Mapped Register Range
Base
0000000000
000000h
48–4Fh
54–57h
60–67h
MCHBAR
DEVEN
RO, RW/L
RO, RW/L
Device Enable
000023DBh
PCI Express Register Range Base
Address
00000000E0
000000h
RO, RW/L,
RW/L/K
PCIEXBAR
Root Complex Register Range Base
Address
0000000000
000000h
68–6Fh
DMIBAR
RO, RW/L
90h
91h
92h
93h
94h
95h
PAM0
PAM1
PAM2
PAM3
PAM4
PAM5
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Programmable Attribute Map 4
Programmable Attribute Map 5
00h
00h
00h
00h
00h
00h
RO, RW/L
RO, RW/L
RO, RW/L
RO, RW/L
RO, RW/L
RO, RW/L
Datasheet
63
DRAM Controller Registers (D0:F0)
Table 8.
DRAM Controller Register Address Map
Address
Offset
Register
Symbol
Default
Access
Value
Register Name
96h
97h
PAM6
LAC
Programmable Attribute Map 6
Legacy Access Control
00h
00h
RO, RW/L
RW, RW/L,
RO
98–99h
9A–9Bh
REMAPBASE Remap Base Address Register
REMAPLIMIT Remap Limit Address Register
03FFh
0000h
RO, RW/L
RO, RW/L
RO, RW/L,
RW, RW/L/K
9Dh
9Eh
SMRAM
System Management RAM Control
02h
38h
Extended System Management RAM
Control
RW/L, RWC,
RO
ESMRAMC
A0–A1h
A2–A3h
A4–A7h
AC–AFh
B0–B1h
C8–C9h
CA–CBh
CC–CDh
DC–DFh
TOM
TOUUD
BSM
Top of Memory
0001h
0000h
RO, RW/L
RW/L
Top of Upper Usable Dram
Base of Stolen Memory
TSEG Memory Base
Top of Low Usable DRAM
Error Status
00000000h
00000000h
0010h
RW/L, RO
RO, RW/L
RW/L, RO
RWC/S, RO
RW, RO
TSEGMB
TOLUD
ERRSTS
ERRCMD
SMICMD
SKPD
0000h
Error Command
0000h
SMI Command
0000h
RO, RW
RW
Scratchpad Data
00000000h
0000000181
064000010C
0009h
E0–EBh
CAPID0
Capability Identifier
RO
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Datasheet
DRAM Controller Registers (D0:F0)
5.1
Configuration Register Details
5.1.1
VID—Vendor Identification
B/D/F/Type:
0/0/0/PCI
Address Offset: 0–1h
Default Value:
Access:
Size:
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
Default
Value
Bit
Access
RO
Description
15:0
8086h
Vendor Identification Number (VID): PCI standard identification for Intel.
5.1.2
DID—Device Identification
B/D/F/Type:
0/0/0/PCI
Address Offset: 2–3h
Default Value:
Access:
Size:
29E0h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Default
Value
Bit
Access
Description
Device Identification Number (DID): This field identifier assigned to the
MCH core/primary PCI device.
15:0
RO
29E0h
Datasheet
65
DRAM Controller Registers (D0:F0)
5.1.3
PCICMD—PCI Command
B/D/F/Type:
0/0/0/PCI
Address Offset: 4–5h
Default Value:
Access:
Size:
0006h
RO, RW
16 bits
Since MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Default
Value
Bit
Access
Description
15:9
RO
00h
Reserved
SERR Enable (SERRE): This bit is a global enable bit for Device 0 SERR
messaging. The MCH does not have an SERR signal. The MCH communicates the
SERR condition by sending an SERR message over DMI to the ICH.
1 = The MCH is enabled to generate SERR messages over DMI for specific
Device 0 error conditions that are individually enabled in the ERRCMD and
DMIUEMSK registers. The error status is reported in the ERRSTS, PCISTS,
and DMIUEST registers.
8
RW
0b
0 = The SERR message is not generated by the MCH for Device 0.
Note that this bit only controls SERR messaging for the Device 0. Device 1 has
its own SERRE bits to control error reporting for error conditions occurring in
that device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not
implemented in the MCH, and this bit is hardwired to 0. Writes to this bit
position have no effect.
7
6
RO
0b
0b
Parity Error Enable (PERRE): Controls whether or not the Master Data Parity
Error bit in the PCI Status register can bet set.
RW
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5
4
3
2
RO
RO
RO
RO
0b
0b
0b
1b
Reserved
Memory Write and Invalidate Enable (MWIE): The MCH will never issue
memory write and invalidate commands. This bit is therefore hardwired to 0.
Writes to this bit position will have no effect.
Reserved
Bus Master Enable (BME): The MCH is always enabled as a master on the
backbone. This bit is hardwired to a "1". Writes to this bit position have no
effect.
Memory Access Enable (MAE): The MCH always allows access to main
memory. This bit is not implemented and is hardwired to 1. Writes to this bit
position have no effect.
1
0
RO
RO
1b
0b
I/O Access Enable (IOAE): This bit is not implemented in the MCH and is
hardwired to a 0. Writes to this bit position have no effect.
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Datasheet
DRAM Controller Registers (D0:F0)
5.1.4
PCISTS—PCI Status
B/D/F/Type:
0/0/0/PCI
Address Offset: 6–7h
Default Value:
Access:
Size:
0090h
RO, RWC
16 bits
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Default
Value
Bit
Access
Description
Detected Parity Error (DPE): This bit is set when this Device receives a
Poisoned TLP.
15
RWC
RWC
0b
Signaled System Error (SSE): This bit is set to 1 when the MCH Device 0
generates an SERR message over DMI for any enabled Device 0 error condition.
Device 0 error conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK
registers. Device 0 error flags are read/reset from the PCISTS, ERRSTS, or
DMIUEST registers. Software clears this bit by writing a 1 to it.
14
0b
Received Master Abort Status (RMAS): This bit is set when the MCH
generates a DMI request that receives an Unsupported Request completion
packet. Software clears this bit by writing a 1 to it.
13
12
11
RWC
RWC
RO
0b
0b
0b
Received Target Abort Status (RTAS): This bit is set when the MCH
generates a DMI request that receives a Completer Abort completion packet.
Software clears this bit by writing a 1 to it.
Signaled Target Abort Status (STAS): The MCH will not generate a Target
Abort DMI completion packet or Special Cycle. This bit is not implemented in the
MCH and is hardwired to a 0. Writes to this bit position have no effect.
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to these bit
positions have no affect. Device 0 does not physically connect to PCI_A. These
bits are set to "00" (fast decode) so that optimum DEVSEL timing for PCI_A is
not limited by the MCH.
10:9
RO
RWC
RO
00b
0b
Master Data Parity Error Detected (DPD): This bit is set when DMI received
a Poisoned completion from ICH.
8
7
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit
positions have no effect. Device 0 does not physically connect to PCI_A. This bit
is set to 1 (indicating fast back-to-back capability) so that the optimum setting
for PCI_A is not limited by the MCH.
1b
6
5
RO
RO
0b
0b
Reserved
66 MHz Capable: Does not apply to PCI Express. Hardwired to 0.
Capability List (CLIST): This bit is hardwired to 1 to indicate to the
configuration software that this device/function implements a list of new
capabilities. A list of new capabilities is accessed via register CAPPTR at
configuration address offset 34h. Register CAPPTR contains an offset pointing to
the start address within configuration space of this device where the Capability
Identification register resides.
4
RO
RO
1b
3:0
0000b
Reserved
Datasheet
67
DRAM Controller Registers (D0:F0)
5.1.5
RID—Revision Identification
B/D/F/Type:
0/0/0/PCI
Address Offset: 8h
Default Value:
Access:
Size:
00h
RO
8 bits
This register contains the revision number of the MCH Device 0. These bits are read
only and writes to this register have no effect.
Default
Value
Bit
Access
Description
Revision Identification Number (RID): This is an 8-bit value that indicates
the revision identification number for the MCH Device 0.
7:0
RO
00h
5.1.6
CC—Class Code
B/D/F/Type:
0/0/0/PCI
Address Offset: 9–Bh
Default Value:
Access:
Size:
060000h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
Default
Value
Bit
Access
Description
Base Class Code (BCC): This is an 8-bit value that indicates the base class
code for the MCH. This code has the value 06h, indicating a Bridge device.
23:16
15:8
RO
RO
06h
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of
Bridge into which the MCH falls. The code is 00h indicating a Host Bridge.
00h
00h
Programming Interface (PI): This is an 8-bit value that indicates the
programming interface of this device. This value does not specify a particular
register set layout and provides no practical use for this device.
7:0
RO
5.1.7
MLT—Master Latency Timer
B/D/F/Type:
0/0/0/PCI
Address Offset: Dh
Default Value:
Access:
Size:
00h
RO
8 bits
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
Default
Value
Bit
Access
RO
Description
7:0
00h
Reserved
68
Datasheet
DRAM Controller Registers (D0:F0)
5.1.8
HDR—Header Type
B/D/F/Type:
0/0/0/PCI
Address Offset: Eh
Default Value:
Access:
Size:
00h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Default
Value
Bit
Access
Description
PCI Header (HDR): This field always returns 0 to indicate that the MCH is a
single function device with standard header layout. Reads and writes to this
location have no effect.
7:0
RO
00h
5.1.9
SVID—Subsystem Vendor Identification
B/D/F/Type:
0/0/0/PCI
Address Offset: 2C–2Dh
Default Value:
Access:
Size:
0000h
RWO
16 bits
This value is used to identify the vendor of the subsystem.
Default
Value
Bit
Access
Description
Subsystem Vendor ID (SUBVID): This field should be programmed during
boot-up to indicate the vendor of the system board. After it has been written
once, it becomes read only.
15:0
RWO
0000h
5.1.10
SID—Subsystem Identification
B/D/F/Type:
0/0/0/PCI
Address Offset: 2E–2Fh
Default Value:
Access:
Size:
0000h
RWO
16 bits
This value is used to identify a particular subsystem.
Default
Value
Bit
Access
Description
Subsystem ID (SUBID): This field should be programmed during BIOS
initialization. After it has been written once, it becomes read only.
15:0
RWO
0000h
Datasheet
69
DRAM Controller Registers (D0:F0)
5.1.11
CAPPTR—Capabilities Pointer
B/D/F/Type:
0/0/0/PCI
Address Offset: 34h
Default Value:
Access:
Size:
E0h
RO
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Default
Value
Bit
Access
Description
Capabilities Pointer (CAPPTR): Pointer to the offset of the first capability ID
register block. In this case the first capability is the product-specific Capability
Identifier (CAPID0).
7:0
RO
E0h
5.1.12
PXPEPBAR—PCI Express* Egress Port Base Address
B/D/F/Type:
0/0/0/PCI
Address Offset: 40–47h
Default Value:
Access:
Size:
0000000000000000h
RO, RW/L
64 bits
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4 KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0]
All the bits in this register are locked in Intel® TXT mode.
Default
Value
Bit
Access
Description
63:36
RO
0000000h Reserved
PCI Express Egress Port MMIO Base Address (PXPEPBAR): This field
corresponds to bits 35 to 12 of the base address PCI Express Egress Port
MMIO configuration space. BIOS will program this register resulting in a base
address for a 4 KB block of contiguous memory address space. This register
ensures that a naturally aligned 4KB space is allocated within the first 64 GB
of addressable memory space. System Software uses this base address to
program the MCH MMIO register set. All the bits in this register are locked in
Intel TXT mode.
35:12
RW/L
000000h
11:1
0
RO
000h
0b
Reserved
PXPEPBAR Enable (PXPEPBAREN):
0 = PXPEPBAR is disabled and does not claim any memory
RW/L
1 = PXPEPBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel TXT.
70
Datasheet
DRAM Controller Registers (D0:F0)
5.1.13
MCHBAR—MCH Memory Mapped Register Range Base
B/D/F/Type:
0/0/0/PCI
Address Offset: 48–4Fh
Default Value:
Access:
Size:
0000000000000000h
RO, RW/L
64 bits
This is the base address for the MCH Memory Mapped Configuration space. There is no
physical memory within this 16KB window that can be addressed. The 16 KB reserved
by this register does not alias to any PCI 2.3 compliant memory mapped space. On
reset, the MCH MMIO Memory Mapped Configuration space is disabled and must be
enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0]
All the bits in this register are locked in Intel TXT mode.
The register space contains memory control, initialization, timing, and buffer strength
registers; clocking registers; and power and thermal management registers. The 16 KB
space reserved by the MCHBAR register is not accessible during Intel TXT mode of
operation or if the ME security lock is asserted (MESMLCK.ME_SM_lock at PCI device 0,
function 0, offset F4h) except for the following offset ranges.
02B8h to 02BFh: Channel 0 Throttle Counter Status Registers
06B8h to 06BFh: Channel 1 Throttle Counter Status Registers
0CD0h to 0CFFh: Thermal Sensor Control Registers
3000h to 3FFFh: Unlocked registers for future expansion
Default
Value
Bit
Access
Description
63:36
RO
0000000h Reserved
MCH Memory Mapped Base Address (MCHBAR): This field corresponds to
bits 35:14 of the base address MCH Memory Mapped configuration space.
BIOS will program this register resulting in a base address for a 16 KB block of
000000h contiguous memory address space. This register ensures that a naturally
aligned 16 KB space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the MCH Memory
Mapped register set. All the bits in this register are locked in Intel TXT mode.
35:14
RW/L
13:1
0
RO
0000h
Reserved
MCHBAR Enable (MCHBAREN):
0 = MCHBAR is disabled and does not claim any memory
RW/L
0b
1 = MCHBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel TXT.
Datasheet
71
DRAM Controller Registers (D0:F0)
5.1.14
DEVEN—Device Enable
B/D/F/Type:
0/0/0/PCI
Address Offset: 54–57h
Default Value:
Access:
Size:
000023DBh
RO, RW/L
32 bits
Allows for enabling/disabling of PCI devices and functions that are within the MCH. The
table below the bit definitions describes the behavior of all combinations of transactions
to devices controlled by this register. All the bits in this register are Intel TXT Lockable.
Default
Value
Bit
Access
Description
31:14
RO
RW/L
RO
00000h Reserved
PE1 Enable (D6EN):
0 = Bus 0, Device 6 is disabled and hidden.
13
1b
1 = Bus 1, Device 6 is enabled and visible.
NOTE:
12:11
00b
Reserved
EP Function 3 (D3F3EN):
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 3 is also
disabled and hidden independent of the state of this bit.
9
RW/L
1b
If this MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1),
then Device 3, Function 3 is disabled and hidden independent of the state of this
bit.
EP Function 2 (D3F2EN):
0 = Bus 0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 2 is also
disabled and hidden independent of the state of this bit.
8
RW/L
1b
If this MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1),
then Device 3, Function 2 is disabled and hidden independent of the state of this
bit.
EP Function 1 (D3F1EN):
0 = Bus 0, Device 3, Function 1 is disabled and hidden
1 = Bus 0, Device 3, Function 1 is enabled and visible.
7
6
RW/L
RW/L
1b
1b
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 1 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1), then Device 3,
Function 1 is disabled and hidden independent of the state of this bit.
EP Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible.
If this MCH does not have ME capability (CAPID0[57] = 1), then Device 3,
Function 0 is disabled and hidden independent of the state of this bit.
72
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
5:2
RO
0s
Reserved
PCI Express Port (D1EN):
1
RW/L
RO
1b
1b
0 = Bus 0, Device 1, Function 0 is disabled and hidden.
Bus 0, Device 1, Function 0 is enabled and visible.
Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be disabled and is
therefore hardwired to 1.
0
5.1.15
PCIEXBAR—PCI Express* Register Range Base Address
B/D/F/Type:
0/0/0/PCI
Address Offset: 60–67h
Default Value:
Access:
Size:
00000000E0000000h
RO, RW/L, RW/L/K
64 bits
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express Hierarchy associated with the MCH. There is
not actual physical memory within this window of up to 256 MB that can be addressed.
The actual length is determined by a field in this register. Each PCI Express Hierarchy
requires a PCI Express BASE register. The MCH supports one PCI Express hierarchy.
The region reserved by this register does not alias to any PCI 2.3 compliant memory
mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to the enable field
in this register. This base address shall be assigned on a boundary consistent with the
number of buses (defined by the Length field in this register), above TOLUD and still
within 64 bit addressable memory space. All other bits not decoded are read only 0.
The PCI Express Base Address cannot be less than the maximum address written to the
Top of physical memory register (TOLUD). Software must guarantee that these ranges
do not overlap with known ranges located above TOLUD. Software must ensure that the
sum of Length of enhanced configuration region + TOLUD + (other known ranges
reserved above TOLUD) is not greater than the 64-bit addressable limit of 64 GB. In
general system implementation and number of PCI/PCI express/PCI-X buses supported
in the hierarchy will dictate the length of the region.
All the Bits in this register are locked in Intel TXT mode.
Datasheet
73
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
63:36
RO
0000000h Reserved
PCI Express Base Address (PCIEXBAR): This field corresponds to bits
[35:28] of the base address for PCI Express enhanced configuration space.
BIOS will program this register resulting in a base address for a contiguous
memory address space; size is defined by bits [2:1] of this register.
This Base address shall be assigned on a boundary consistent with the
number of buses (defined by the Length field in this register) above TOLUD
and still within 64-bit addressable memory space. The address bits decoded
depend on the length of the region defined by this register.
This register is locked by Intel TXT.
35:28
RW/L
0Eh
The address used to access the PCI Express configuration space for a specific
device can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device Number * 32KB +
Function Number * 4KB
The address used to access the PCI Express configuration space for Device 1
in this component would be PCI Express Base Address + 0 * 1MB + 1 * 32KB
+ 0 * 4KB = PCI Express Base Address + 32KB. Remember that this address
is the beginning of the 4KB space that contains both the PCI compatible
configuration space and the PCI Express extended configuration space.
All the Bits in this register are locked in Intel TXT mode.
128MB Base Address Mask (128ADMSK): This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask (RO, read 0b),
depending on the value of bits [2:1] in this register.
27
RW/L
0b
0b
64MB Base Address Mask (64ADMSK): This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask (RO, read 0b),
depending on the value of bits [2:1] in this register.
26
RW/L
RO
25:3
000000h Reserved
Length (LENGTH): This Field describes the length of this region.
Enhanced Configuration Space Region/Buses Decoded
00 = 256 MB (buses 0-255). Bits [31:28] are decoded in the PCI Express
Base Address Field
01 = 128 MB (Buses 0–127). Bits [31:27] are decoded in the PCI Express
Base Address Field.
2:1
RW/L/K
00b
10 = 64 MB (Buses 0–63). Bits [31:26] are decoded in the PCI Express Base
Address Field.
11 = Reserved
This register is locked by Intel TXT.
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write transactions
proceed as if there were no PCIEXBAR register. PCIEXBAR bits [35:26]
are R/W with no functionality behind them.
0
RW/L
0b
1 = The PCIEXBAR register is enabled. Memory read and write transactions
whose address bits [35:26] match PCIEXBAR will be translated to
configuration reads and writes within the MCH. These Translated cycles
are routed as shown in the table above.
This register is locked by Intel TXT.
74
Datasheet
DRAM Controller Registers (D0:F0)
5.1.16
DMIBAR—Root Complex Register Range Base Address
B/D/F/Type:
0/0/0/PCI
Address Offset: 68–6Fh
Default Value:
Access:
Size:
0000000000000000h
RO, RW/L
64 bits
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the MCH. There is no physical memory within this 4 KB window that can
be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0]. All
the Bits in this register are locked in Intel TXT mode.
Default
Value
Bit
Access
Description
63:36
RO
0000000h Reserved
DMI Base Address (DMIBAR): This field corresponds to bits 35:12 of the
base address DMI configuration space. BIOS will program this register
resulting in a base address for a 4 KB block of contiguous memory address
space. This register ensures that a naturally aligned 4KB space is allocated
within the first 64 GB of addressable memory space. System Software uses
this base address to program the DMI register set. All the Bits in this register
are locked in Intel TXT mode.
35:12
RW/L
000000h
11:1
0
RO
000h
0b
Reserved
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory
RW/L
1 = DMIBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel TXT.
Datasheet
75
DRAM Controller Registers (D0:F0)
5.1.17
PAM0—Programmable Attribute Map 0
B/D/F/Type:
0/0/0/PCI
Address Offset: 90h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h–0FFFFFh. The MCH allows programmable memory attributes on 13 Legacy
memory segments of various sizes in the 768 KB to 1 MB address range. Seven
Programmable Attribute Map (PAM) Registers are used to support these features.
Cacheability of these areas is controlled via the MTRR registers in the processor. Two
bits are used to specify memory attributes for each memory segment. These bits apply
to both host accesses and PCI initiator accesses to the PAM areas. These attributes are:
RE - Read Enable.
When RE = 1, the processor read accesses to the
corresponding memory segment are claimed by the MCH and
directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to PCI_A.
WE - Write Enable.
When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main
memory. Conversely, when WE = 0, the host write accesses are
directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in
size.
Note that the MCH may hang if a PCI Express Link Attach or DMI originated access to
Read Disabled or Write Disabled PAM segments occur (due to a possible IWB to non-
DRAM).
For these reasons the following critical restriction is placed on the programming of the
PAM regions: At the time that a DMI or PCI Express Link Attach accesses to the PAM
region may occur, the targeted PAM segment must be programmed to be both readable
and writeable.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0F0000–0FFFFF Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0F0000h to 0FFFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
5:4
3:0
00b
0h
Reserved
76
Datasheet
DRAM Controller Registers (D0:F0)
5.1.18
PAM1—Programmable Attribute Map 1
B/D/F/Type:
0/0/0/PCI
Address Offset: 91h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h – 0C7FFFh.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0C4000h–0C7FFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
5:4
3:2
1:0
00b
00b
00b
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Reserved
0C0000h–0C3FFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
RW/L
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Datasheet
77
DRAM Controller Registers (D0:F0)
5.1.19
PAM2—Programmable Attribute Map 2
B/D/F/Type:
0/0/0/PCI
Address Offset: 92h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C8000h– 0CFFFFh.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0CC000h–0CFFFFh Attribute (HIENABLE):
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
5:4
3:2
00b
00b
10 =: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Reserved
0C8000h–0CBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
1:0
RW/L
00b
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
78
Datasheet
DRAM Controller Registers (D0:F0)
5.1.20
PAM3—Programmable Attribute Map 3
B/D/F/Type:
0/0/0/PCI
Address Offset: 93h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h – 0D7FFFh.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
5:4
3:2
1:0
00b
00b
00b
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Reserved
0D0000h–0D3FFFh Attribute (LOENABLE): This field controls the steering
of read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
RW/L
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Datasheet
79
DRAM Controller Registers (D0:F0)
5.1.21
PAM4—Programmable Attribute Map 4
B/D/F/Type:
0/0/0/PCI
Address Offset: 94h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D8000h – 0DFFFFh.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from 0DC000h
to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
5:4
3:2
1:0
00b
00b
00b
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Reserved
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from 0D8000h
to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
RW/L
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
80
Datasheet
DRAM Controller Registers (D0:F0)
5.1.22
PAM5—Programmable Attribute Map 5
B/D/F/Type:
0/0/0/PCI
Address Offset: 95h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E0000h – 0E7FFFh.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E4000 to 0E7FFF.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
5:4
3:2
1:0
00b
00b
00b
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Reserved
0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E0000 to 0E3FFF.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
RW/L
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Datasheet
81
DRAM Controller Registers (D0:F0)
5.1.23
PAM6—Programmable Attribute Map 6
B/D/F/Type:
0/0/0/PCI
Address Offset: 96h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h–0EFFFFh.
Default
Value
Bit
Access
Description
7:6
RO
RW/L
RO
00b
Reserved
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
5:4
3:2
1:0
00b
00b
00b
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Reserved
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
RW/L
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
82
Datasheet
DRAM Controller Registers (D0:F0)
5.1.24
LAC—Legacy Access Control
B/D/F/Type:
0/0/0/PCI
Address Offset: 97h
Default Value:
Access:
Size:
00h
RW/L, RO
8 bits
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
Default
Value
Bit
Access
Description
Hole Enable (HEN): This field enables a memory hole in DRAM space. The
DRAM that lies "behind" this space is not remapped.
0 = No memory hole.
7
RW/L
RO
0b
0s
1 = Memory hole from 15 MB to 16 MB.
This bit is Intel TXT lockable.
6:0
Reserved
5.1.25
REMAPBASE—Remap Base Address Register
B/D/F/Type:
0/0/0/PCI
Address Offset: 98–99h
Default Value:
Access:
Size:
03FFh
RO, RW/L
16 bits
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Remap Base Address [35:26] (REMAPBASE): The value in this register
defines the lower boundary of the Remap window. The Remap window is
inclusive of this address. In the decoder A[25:0] of the Remap Base Address are
assumed to be 0s. Thus the bottom of the defined memory range will be aligned
to a 64MB boundary.
9:0
RW/L
3FFh
When the value in this register is greater than the value programmed into the
Remap Limit register, the Remap window is disabled.
These bits are Intel TXT lockable or ME stolen Memory lockable.
Datasheet
83
DRAM Controller Registers (D0:F0)
5.1.26
REMAPLIMIT—Remap Limit Address Register
B/D/F/Type:
0/0/0/PCI
Address Offset: 9A–9Bh
Default Value:
Access:
Size:
0000h
RO, RW/L
16 bits
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Remap Limit Address [35:26] (REMAPLMT): The value in this register
defines the upper boundary of the Remap window. The Remap window is
inclusive of this address. In the decoder A[25:0] of the remap limit address are
assumed to be Fs. Thus the top of the defined range will be one less than a
64 MB boundary.
9:0
RW/L
000h
When the value in this register is less than the value programmed into the
Remap Base register, the Remap window is disabled.
These Bits are Intel TXT lockable or ME stolen Memory lockable.
84
Datasheet
DRAM Controller Registers (D0:F0)
5.1.27
SMRAM—System Management RAM Control
B/D/F/Type:
0/0/0/PCI
Address Offset: 9Dh
Default Value:
Access:
Size:
02h
RO, RW/L, RW, RW/L/K
8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Default
Value
Bit
Access
Description
7
RO
0b
Reserved
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space
DRAM is made visible even when SMM decode is not active. This is intended to
help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and
D_CLS=1 are not set at the same time.
6
5
RW/L
0b
0b
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not
accessible to data references, even if SMM decode is active. Code references
may still access SMM space DRAM. This will allow SMM software to reference
through SMM space to update the display. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
RW
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to
0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN
become read only. D_LCK can be set to 1 via a normal configuration space write
but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN
provide convenience with security. The BIOS can use the D_OPEN function to
initialize SMM space and then use D_LCK to "lock down" SMM space in the future
so that no application software (or BIOS itself) can violate the integrity of SMM
space, even if the program has knowledge of the D_OPEN function.
4
RW/L/K
0b
Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM
functions are enabled, providing 128 KB of DRAM accessible at the A0000h
address while in SMM (ADSB with SMM decode). To enable Extended SMRAM
function this bit has be set to 1. Refer to the section on SMM for more details.
Once D_LCK is set, this bit becomes read only.
3
RW/L
RO
0b
Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates
the location of SMM space. SMM DRAM is not remapped. It is simply made visible
if the conditions are right to access SMM space, otherwise the access is
forwarded to DMI. Since the MCH supports only the SMM space between A0000
and BFFFF, this field is hardwired to 010b.
2:0
010b
Datasheet
85
DRAM Controller Registers (D0:F0)
5.1.28
ESMRAMC—Extended System Management RAM Control
B/D/F/Type:
0/0/0/PCI
Address Offset: 9Eh
Default Value:
Access:
Size:
38h
RW/L, RWC, RO
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
Default
Value
Bit
Access
Description
Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space
location (i.e., above 1 MB or below 1 MB) When G_SMRAME is 1 and H_SMRAME
is set to 1, the high SMRAM memory space is enabled. SMRAM accesses within
the range 0FEDA0000h to 0FEDBFFFFh are remapped to DRAM addresses within
the range 000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes
read only.
7
RW/L
0b
Invalid SMRAM Access (E_SMERR): This bit is set when processor has
accessed the defined memory ranges in Extended SMRAM (High Memory and T-
segment) while not in SMM space and with the D-OPEN bit = 0. It is software's
responsibility to clear this bit. The software must write a 1 to this bit to clear it.
6
RWC
0b
5
4
3
RO
RO
RO
1b
1b
1b
SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the MCH.
L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the MCH.
L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the MCH.
TSEG Size (TSEG_SZ): Selects the size of the TSEG memory block if enabled.
Memory from the top of DRAM space is partitioned away so that it may only be
accessed by the processor interface and only then when the SMM bit is set in the
request packet. Non-SMM accesses to this memory region are sent to DMI when
the TSEG memory block is enabled.
00 = 1 MB TSEG. (TOLUD – Stolen Memory Size – 1M) to (TOLUD – Stolen
Memory Size).
2:1
RW/L
00b
01 = 2 MB TSEG (TOLUD – Stolen Memory Size – 2M) to (TOLUD – Stolen
Memory Size).
10 = 8 MB TSEG (TOLUD – Stolen Memory Size – 8M) to (TOLUD – Stolen
Memory Size).
11 = Reserved.
Once D_LCK has been set, these bits become read only.
TSEG Enable (T_EN): This bit is for enabling of SMRAM memory for Extended
SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is
enabled to appear in the appropriate physical address space. Note that once
D_LCK is set, this bit becomes read only.
0
RW/L
0b
86
Datasheet
DRAM Controller Registers (D0:F0)
5.1.29
TOM—Top of Memory
B/D/F/Type:
0/0/0/PCI
Address Offset: A0–A1h
Default Value:
Access:
Size:
0001h
RO, RW/L
16 bits
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
Default
Value
Bit
Access
Description
15:10
RO
00h
Reserved
Top of Memory (TOM): This register reflects the total amount of populated
physical memory. This is NOT necessarily the highest main memory address
(holes may exist in main memory address map due to addresses allocated for
memory mapped IO). These bits correspond to address bits 35:26 (64MB
granularity). Bits 25:0 are assumed to be 0. All the bits in this register are
locked in Intel TXT mode.
9:0
RW/L
001h
5.1.30
TOUUD—Top of Upper Usable Dram
B/D/F/Type:
0/0/0/PCI
Address Offset: A2–A3h
Default Value:
Access:
Size:
0000h
RW/L
16 bits
This 16 bit register defines the Top of Upper Usable DRAM.
Configuration software must set this value to TOM minus all EP stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1byte
64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are assumed to
be 000_0000h for the purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less than the value
programmed in this register and greater than or equal to 4 GB.
These bits are Intel TXT lockable.
Default
Value
Bit
Access
Description
TOUUD (TOUUD): This register contains bits 35:20 of an address one byte
above the maximum DRAM memory above 4 GB that is usable by the operating
system. Configuration software must set this value to TOM minus all EP stolen
memory if reclaim is disabled. If reclaim is enabled, this value must be set to
15:0
RW/L
0000h reclaim limit 64 MB aligned since reclaim limit + 1byte is 64 MB aligned. Address
bits 19:0 are assumed to be 000_0000h for the purposes of address comparison.
The Host interface positively decodes an address towards DRAM if the incoming
address is less than the value programmed in this register and greater than
4 GB. All the Bits in this register are locked in Intel TXT mode.
Datasheet
87
DRAM Controller Registers (D0:F0)
5.1.31
BSM—Base of Stolen Memory
B/D/F/Type:
0/0/0/PCI
Address Offset: A4–A7h
Default Value:
Access:
Size:
00000000h
RW/L, RO
32 bits
This register contains the base address of stolen DRAM memory. BIOS determines the
base of stolen memory by subtracting the stolen memory size (PCI Device 0 offset 52
bits [6:4]) from TOLUD (PCI Device 0 offset B0 bits [15:04]).
Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM
register is set.
Default
Value
Bit
Access
Description
Base of Stolen Memory (BSM): This register contains bits 31 to 20 of the base
address of stolen DRAM memory. BIOS determines the base of stolen memory
by subtracting the stolen memory size (PCI Device 0, offset 52h, bits 6:4) from
TOLUD (PCI Device 0, offset B0h, bits 15:4).
NOTE: This register is locked and becomes Read Only when the D_LCK bit in the
SMRAM register is set.
31:20
RW/L
RO
000h
19:0
00000h Reserved
5.1.32
TSEGMB—TSEG Memory Base
B/D/F/Type:
0/0/0/PCI
Address Offset: AC–AFh
Default Value:
Access:
Size:
00000000h
RO, RW/L
32 bits
This register contains the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory by subtracting the TSEG size (PCI Device 0 offset 9E bits [2:1])
from stolen base (PCI Device 0 offset A4 bits [31:20]).
Once D_LCK has been set, these bits becomes read only.
Default
Value
Bit
Access
Description
TESG Memory base (TSEGMB): This register contains bits [31:20] of the base
address of TSEG DRAM memory. BIOS determines the base of TSEG memory by
subtracting the TSEG size (PCI Device 0 offset 9E bits [2:1]) from stolen base
(PCI Device 0 offset A8 bits [31:20]).
31:20
19:0
RW/L
RO
000h
Once D_LCK has been set, these bits becomes read only.
00000h Reserved
88
Datasheet
DRAM Controller Registers (D0:F0)
5.1.33
TOLUD—Top of Low Usable DRAM
B/D/F/Type:
0/0/0/PCI
Address Offset: B0–B1h
Default Value:
Access:
Size:
0010h
RW/L, RO
16 bits
This 16 bit register defines the Top of Low Usable DRAM. TSEG, and Stolen Memory are
within the DRAM space defined. From the top, MCH optionally claims 1, 2 MB of DRAM
for Stolen Memory and 1, 2, or 8 MB of DRAM for TSEG if enabled.
Programming Example:
C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Stolen Memory Size set to 2 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the
system. This 20 MB range at the very top of addressable memory space is lost to APIC
and Intel TXT.
According to the above equation, TOLUD is originally calculated to: 4 GB =
1_0000_0000h
The system memory requirements are: 4GB (max addressable space) – 1GB (PCI
space) – 35 MB (lost memory) = 3 GB – 35 MB (minimum granularity) = ECB0_0000h
Since ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h,
TOLUD should be programmed to ECBh.
These bits are Intel TXT lockable.
Default
Value
Bit
Access
Description
Top of Low Usable DRAM (TOLUD): This register contains bits [31:20] of an
address one byte above the maximum DRAM memory below 4GB that is usable
by the operating system. Address bits [31:20] programmed to 01h implies a
minimum memory size of 1 MB. Configuration software must set this value to
the smaller of the following 2 choices: maximum amount memory in the system
minus ME stolen memory plus one byte or the minimum address allocated for
PCI memory. Address bits [19:0] are assumed to be 0_0000h for the purposes
of address comparison. The Host interface positively decodes an address
towards DRAM if the incoming address is less than the value programmed in this
register.
15:4
RW/L
001h
Note that the Top of Low Usable DRAM is the lowest address above both Stolen
memory and TSEG. BIOS determines the base of Stolen Memory by subtracting
the Stolen Memory Size from TOLUD and further decrements by TSEG size to
determine base of TSEG. All the Bits in this register are locked in Intel TXT
mode.
This register must be 64 MB aligned when reclaim is enabled.
3:0
RO
0000b Reserved
Datasheet
89
DRAM Controller Registers (D0:F0)
5.1.34
ERRSTS—Error Status
B/D/F/Type:
0/0/0/PCI
Address Offset: C8–C9h
Default Value:
Access:
Size:
0000h
RWC/S, RO
16 bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a 1 to it.
Default
Value
Bit
Access
Description
15
RO
0b
Reserved
Isochronous TBWRR Run Behind FIFO Full (ITCV): If set, this bit indicates
a VC1 TBWRR is running behind, resulting in the slot timer to stop until the
request is able to complete.
14
RWC/S
0b
If this bit is already set, then a interrupt message will not be sent on a new error
event.
Isochronous TBWRR Run behind FIFO Put (ITSTV): If set, this bit indicates
a VC1 TBWRR request was put into the run behind. This will likely result in a
resulting in a contract violation due to the MCH egress port taking too long to
service the isochronous request.
13
12
RWC/S
RO
0b
0b
If this bit is already set, then a interrupt message will not be sent on a new error
event.
Reserved
MCH Thermal Sensor Event for SMI/SCI/SERR (GTSE): This bit indicates
that a MCH Thermal Sensor trip has occurred and an SMI, SCI or SERR has been
generated. The status bit is set only if a message is sent based on Thermal event
enables in Error command, SMI command and SCI command registers. A trip
point can generate one of SMI, SCI, or SERR interrupts (two or more per event is
illegal). Multiple trip points can generate the same interrupt, if software chooses
this mode, subsequent trips may be lost. If this bit is already set, then an
interrupt message will not be sent on a new thermal sensor event.
11
RWC/S
0b
10
9
RO
RWC/S
RO
0b
0b
0b
Reserved
LOCK to non-DRAM Memory Flag (LCKF): When this bit is set to 1, the MCH
has detected a lock operation to memory space that did not map into DRAM.
8
Reserved
DRAM Throttle Flag (DTF):
7
RWC/S
RO
0b
1 = Indicates that a DRAM Throttling condition occurred.
0 = Software has cleared this flag since the most recent throttling event.
6:2
00h
Reserved
90
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
Multiple-bit DRAM ECC Error Flag (DMERR): If this bit is set to 1, a memory
read data transfer had an uncorrectable multiple-bit error. When this bit is set,
the address, channel number, and device number that caused the error are
logged in the register. Once this bit is set, the fields are locked until the
processor clears this bit by writing a 1. Software uses bits [1:0] to detect
whether the logged error address is for Single or Multiple-bit error. This bit is
reset on PWROK.
1
RWC/S
0b
Single-bit DRAM ECC Error Flag (DSERR): If this bit is set to 1, a memory
read data transfer had a single-bit correctable error and the corrected data was
sent for the access. When this bit is set the address and device number that
caused the error are logged in the DEAP register. Once this bit is set the DEAP,
DERRSYN, and DERRDST fields are locked to further single bit error updates until
the processor clears this bit by writing a 1. A multiple bit error that occurs after
this bit is set will overwrite the DEAP and DERRSYN fields with the multiple-bit
error signature and the DMERR bit will also be set. A single bit error that occurs
after a multi-bit error will set this bit but will not overwrite the other fields. This
bit is reset on PWROK.
0
RWC/S
0b
Datasheet
91
DRAM Controller Registers (D0:F0)
5.1.35
ERRCMD—Error Command
B/D/F/Type:
0/0/0/PCI
Address Offset: CA–CBh
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
This register controls the MCH responses to various system errors. Since the MCH does
not have an SERRB signal, SERR messages are passed from the MCH to the ICH over
DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device 0 via the PCI Command register.
Default
Value
Bit
Access
Description
15:12
RO
0h
Reserved
SERR on MCH Thermal Sensor Event (TSESERR):
1 = The MCH generates a DMI SERR special cycle when bit [11] of the ERRSTS is
set. The SERR must not be enabled at the same time as the SMI for the
same thermal sensor event.
11
RW
0b
0 = Reporting of this condition via SERR messaging is disabled.
10
9
RO
RW
RO
0b
0b
0s
Reserved
SERR on LOCK to non-DRAM Memory (LCKERR):
1 = The MCH will generate a DMI SERR special cycle whenever a processor lock
cycle is detected that does not hit DRAM.
0 = Reporting of this condition via SERR messaging is disabled.
8:2
Reserved
SERR Multiple-Bit DRAM ECC Error (DMERR):
1 = The MCH generates an SERR message over DMI when it detects a multiple-
bit error reported by the DRAM controller.
1
0
RW
RW
0b
0b
0 = Reporting of this condition via SERR messaging is disabled.
For systems not supporting ECC this bit must be disabled.
SERR on Single-bit ECC Error (DSERR):
1 = The MCH generates an SERR special cycle over DMI when the DRAM
controller detects a single bit error.
0 = Reporting of this condition via SERR messaging is disabled.
For systems that do not support ECC this bit must be disabled.
92
Datasheet
DRAM Controller Registers (D0:F0)
5.1.36
SMICMD—SMI Command
B/D/F/Type:
0/0/0/PCI
Address Offset: CC–CDh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
Default
Value
Bit
Access
Description
15:12
RO
RW
RO
RW
0h
Reserved
SMI on MCH Thermal Sensor Trip (TSTSMI):
1 = A SMI DMI special cycle is generated by MCH when the thermal sensor trip
requires an SMI. A thermal sensor trip point cannot generate more than one
special cycle.
11
10:2
1
0b
000h
0b
0 = Reporting of this condition via SMI messaging is disabled.
Reserved
SMI on Multiple-Bit DRAM ECC Error (DMESMI):
1 = The MCH generates an SMI DMI message when it detects a multiple-bit error
reported by the DRAM controller.
0 = Reporting of this condition via SMI messaging is disabled. For systems not
supporting ECC this bit must be disabled.
SMI on Single-bit ECC Error (DSESMI):
1 = The MCH generates an SMI DMI special cycle when the DRAM controller
detects a single bit error.
0
RW
0b
0 = Reporting of this condition via SMI messaging is disabled. For systems that
do not support ECC this bit must be disabled.
5.1.37
SKPD—Scratchpad Data
B/D/F/Type:
0/0/0/PCI
Address Offset: DC–DFh
Default Value:
Access:
Size:
00000000h
RW
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS drivers.
Default
Value
Bit
Access
Description
0000000
0h
31:0
RW
Scratchpad Data (SKPD): 1 DWord of data storage.
Datasheet
93
DRAM Controller Registers (D0:F0)
5.1.38
CAPID0—Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
E0–EBh
0000000181064000010C0009h
RO
96 bits
0h
Size:
BIOS Optimal Default
This register provides control of bits in this register are only required for customer
visible component differentiation.
Default
Value
Bit
Access
Description
95:78
RO
0s
Reserved
Dual Channel Disable (DCD): Disables dual-channel operation
0 = Dual channel operation allowed
1 = Only single channel operation allowed - Only channel 0 will operate, channel
1 will be turned off and tri-stated to save power. This setting hardwires the
rank population field for channel 1 to zero. (MCHBAR offset 660h, bits
20:23).
77
76
RO
0b
0b
2 DIMMS per Channel Disable (2DPCD): Allows Dual-Channel operation but
only supports 1 DIMM per channel.
0 = 2 DIMMs per channel Enabled
RO
1 = 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the
rank population field for each channel to zero. (MCHBAR offset 260h, bits
22:23 for channel 0 and MCHBAR offset 660h, bits 22:23 for channel 1).
75
74:75
72
RO
RO
RO
RO
0b
00b
0b
Chipset Intel TXT disable (LTDIS): Chipset Intel TXT disable
Reserved
Agent Presence Disable (APD):
Circuit Breaker Disable (CBD):
71
0b
Multiprocessor Disable (MD):
70
RO
0b
0 = MCH capable of Multiple Processors
1 = MCH capable of uni-processor only.
69
RO
RO
RO
RO
RO
0b
0b
FAN Speed Control Disable (FSCD):
EastFork Disable (EFD):
Reserved
68
67:65
64:62
61:58
000b
110
Reserved
0000b Reserved
ME Disable (MED):
0 = ME feature is enabled
1 = ME feature is disabled
57
RO
0b
56
RO
RO
RO
1b
0s
Reserved
Reserved
Reserved
55:51
50:49
11b
VT-d Disable (VTDD):
0 = Enable VT-d
48
47
RO
RO
0b
0b
1 = Disable VT-d
Reserved
94
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
46
RO
1b
Reserved
Primary PCI Express Port x16 Disable (PEX16D):
0 = Capable of x16 PCI Express Port.
1 = Not Capable of x16 PCI Express port; instead PCI Express is limited to x8
and below. This causes PCI Express port to enable and train logical lanes
[7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width
field of the Link Capability register reports x8 instead of x16. (In the case of
x8 lane reversal, lanes [15:8] are active and lanes [7:0] are powered
down.).
45
44
43
RO
RO
RO
0b
0b
0b
Primary PCI Express Port Disable (PEPD):
0 = There is a PCI Express Port on this MCH. Device 1 and associated memory
spaces are accessible.
1 = There is no PCI Express Port on this MCH. Device 1 and associated memory
and I/O spaces are disabled by hardwiring the D1EN field bit 1 of the Device
Enable register (DEVEN Dev 0 Offset 54h). In addition, Next_Pointer = 00h,
and IO cannot decode to the PCI Express interface. From a Physical Layer
perspective, all 16 lanes are powered down and the link does not attempt to
train.
Secondary PCI Express Port X16 Disable (PE2X16D):
0 = Capable of x16 PCI Express1 Port.
1 = Not Capable of x16 PCI Express1 port; instead PCI Express1 is limited to x8
and below. This causes PCI Express1 port to enable and train logical lanes
[7:0] only. Logical lanes [15:8] are powered down, and the Max Link Width
field of the Link Capability register reports x8 instead of x16. (In the case of
x8 lane reversal, lanes [15:8] are active and lanes [7:0] are powered
down.)
Secondary PCI Express Port Disable (PE2PD):
0 = There is a secondary PCI Express Port on this MCH. Device 6 and associated
memory spaces are accessible.
1 = There is no secondary PCI Express Port on this MCH. Device 6 and
associated memory and IO spaces are disabled by hardwiring the D6EN field
bit [13] of the Device Enable register (DEVEN Dev 0 Offset 54h). All 16 lanes
are powered down and the link does not attempt to train. In addition,
Next_Pointer = 00h, and IO cannot decode to the PCI Express interface.
From a Physical Layer perspective, all 16 lanes are powered down and the
link does not attempt to train.
42
RO
0b
41
40
RO
RO
0b
0b
Reserved
ECC Disable (ECCDIS):
0 = ECC capable
1 = Not ECC capable. Hardwires ECC enable field, bit 7, of the CWB Control
Registers (MCHBAR Offset 243h and 643h) to "0".
39
38
RO
RO
RO
RO
RO
0b
0b
Reserved
DDR3 Disable (DDR3D):
0 = Capable of supporting DDR3 SDRAM
1 = Not Capable of supporting DDR3 SDRAM
37:35
34
000b
0b
Reserved
Primary and Secondary PCI Express Gen 2 Disable (PEPSD):
0 = Primary and secondary PCI Express Gen 2 enabled
1 = Primary and secondary PCI Express Gen 2 disabled
33:32
00b
Reserved
Datasheet
95
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
DDR Frequency Capability (DDRFC): This field controls which values may be
written to the Memory Frequency Select field [6:4] of the Clocking Configuration
registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will
be ignored.
31:30
RO
00b
00 = MCH capable of up to DDR3 1067
10 = MCH capable of up to DDR2/DDR3 800
11 = MCH capable of up to DDR2/DDR3 667
FSB Frequency Capability (FSBFC): This field controls which values are
allowed in the FSB Frequency Select Field [2:0] of the Clocking Configuration
Register. These values are determined by the BSEL[2:0] frequency straps. Any
unsupported strap values will render the MCH System Memory Interface
inoperable.
29:28
RO
00b
00 = MCH capable of "All" Memory Frequencies
01 = MCH capable of up to FSB 1333
10 = MCH capable of up to FSB 1067
11 = MCH capable of up to FSB 800
CAPID Version (CAPIDV): This field has the value 0001b to identify the first
revision of the CAPID register definition.
27:24
23:16
15:8
7:0
RO
RO
RO
RO
1h
CAPID Length (CAPIDL): This field has the value 0Ch to indicate the structure
length (12 bytes).
0Ch
00h
09h
Next Capability Pointer (NCP): This field is hardwired to 00h indicating the
end of the capabilities linked list.
Capability Identifier (CAP_ID): This field has the value 1001b to identify the
CAP_ID assigned by the PCI SIG for vendor dependent capability pointers.
96
Datasheet
DRAM Controller Registers (D0:F0)
5.2
MCHBAR
Table 9.
MCHBAR Register Address Map
Address
Default
Value
Register Symbol
Offset
Register Name
Access
111h
CHDECMISC
C0DRB0
Channel Decode Misc
00h
RW/L
Channel 0 DRAM Rank
Boundary Address 0
200–201h
0000h
RO, RW/L
Channel 0 DRAM Rank
Boundary Address 1
202–203h
204–205h
206–207h
208–209h
20A
C0DRB1
C0DRB2
C0DRB3
C0DRA01
C0DRA23
0000h
0000h
0000h
0000h
0000h
RW/L, RO
RW/L, RO
RO, RW/L
RW/L
Channel 0 DRAM Rank
Boundary Address 2
Channel 0 DRAM Rank
Boundary Address 3
Channel 0 DRAM Rank 0,1
Attribute
Channel 0 DRAM Rank 2,3
Attribute
RW/L
250–251h
252–255h
256–257h
258–25Ah
25B–25Ch
C0CYCTRKPCHG
C0CYCTRKACT
C0CYCTRKWR
C0CYCTRKRD
C0CYCTRKREFR
Channel 0 CYCTRK PCHG
Channel 0 CYCTRK ACT
Channel 0 CYCTRK WR
Channel 0 CYCTRK READ
Channel 0 CYCTRK REFR
0000h
00000000h
0000h
RO, RW
RW, RO
RW
000000h
0000h
RO, RW
RO, RW
RW, RW/L,
RO
260–263h
269–26Eh
C0CKECTRL
C0REFRCTRL
Channel 0 CKE Control
00000800h
Channel 0 DRAM Refresh
Control
021830000C
30h
RW, RO
0000000000
000000h
280–287h
29C–29Fh
600–601h
C0ECCERRLOG
C0ODTCTRL
C1DRB0
Channel 0 ECC Error Log
Channel 0 ODT Control
RO/P, RO
RO, RW
00000000h
0000h
Channel 1 DRAM Rank
Boundary Address 0
RW/L, RO
Channel 1 DRAM Rank
Boundary Address 1
602–603h
604–605h
606–607h
608–609h
60A–60Bh
C1DRB1
C1DRB2
C1DRB3
C1DRA01
C1DRA23
0000h
0000h
0000h
0000h
0000h
RO, RW/L
RW/L, RO
RW/L, RO
RW/L
Channel 1 DRAM Rank
Boundary Address 2
Channel 1 DRAM Rank
Boundary Address 3
Channel 1 DRAM Rank 0,1
Attributes
Channel 1 DRAM Rank 2,3
Attributes
RW/L
650–651h
652–655h
656–657h
C1CYCTRKPCHG
C1CYCTRKACT
C1CYCTRKWR
Channel 1 CYCTRK PCHG
Channel 1 CYCTRK ACT
Channel 1 CYCTRK WR
0000h
00000000h
0000h
RW, RO
RO, RW
RW
Datasheet
97
DRAM Controller Registers (D0:F0)
Table 9.
MCHBAR Register Address Map
Address
Default
Access
Value
Register Symbol
Offset
Register Name
658–65Ah
660–663h
C1CYCTRKRD
C1CKECTRL
Channel 1 CYCTRK READ
Channel 1 CKE Control
000000h
RW, RO
RO, RW/L,
RW
00000800h
Channel 1 DRAM Refresh
Control
021830000C
30h
669–66Eh
C1REFRCTRL
RW, RO
0000000000
000000h
680–687h
69C–69Fh
A00–A01h
C1ECCERRLOG
C1ODTCTRL
EPC0DRB0
Channel 1 ECC Error Log
Channel 1 ODT Control
RO/P, RO
RO, RW
RW, RO
00000000h
0000h
EP Channel 0 DRAM Rank
Boundary Address 0
EP Channel 0 DRAM Rank
Boundary Address 1
A02–A03h
A04–A05h
A06–A07h
A08–A09h
A0A–A0Bh
EPC0DRB1
EPC0DRB2
EPC0DRB3
EPC0DRA01
EPC0DRA23
0000h
0000h
0000h
0000h
0000h
RW, RO
RW, RO
RW, RO
RW
EP Channel 0 DRAM Rank
Boundary Address 2
EP Channel 0 DRAM Rank
Boundary Address 3
EP Channel 0 DRAM Rank 0,1
Attribute
EP Channel 0 DRAM Rank 2,3
Attribute
RW
A19–A1Ah EPDCYCTRKWRTPRE EPD CYCTRK WRT PRE
A1C–A1Fh EPDCYCTRKWRTACT EPD CYCTRK WRT ACT
A20–A21h EPDCYCTRKWRTWR EPD CYCTRK WRT WR
A22–A23h EPDCYCTRKWRTREF EPD CYCTRK WRT REF
A24–A26h EPDCYCTRKWRTRD EPD CYCTRK WRT READ
0000h
00000000h
0000h
RW, RO
RO, RW
RW, RO
RO, RW
RW
0000h
000000h
EPD CKE related configuration
00E0000000
h
A28–A2Ch EPDCKECONFIGREG
registers
RW
A30–A33h
CD8h
EPDREFCONFIG
TSC1
EP DRAM Refresh Configuration
Thermal Sensor Control 1
40000C30h
00h
RW, RO
RW/L, RW,
RS/WC
CD9h
CDAh
TSC2
TSS
Thermal Sensor Control 2
Thermal Sensor Status
00h
00h
RO, RW/L
RO
Thermal Sensor Temperature
Trip Point
RO, RW,
RW/L
CDC–CDFh
CE2h
TSTTP
TCO
00000000h
00h
RW/L/K,
RW/L
Thermal Calibration Offset
RW/L, RO,
RW/L/K
CE4h
THERM1
Thermal Hardware Protection
00h
CEA–CEBh
CF1–CF1h
F14–F17h
TIS
Thermal Interrupt Status
Thermal SMI Command
Power Management Status
0000h
00h
RO, RWC
RO, RW
TSMICMD
PMSTS
00000000h
RWC/S, RO
98
Datasheet
DRAM Controller Registers (D0:F0)
5.2.1
CHDECMISC—Channel Decode Misc
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 111h
Default Value:
Access:
Size:
00h
RW/L
8 bits
This register provides miscellaneous CHDEC/MAGEN configuration bits.
Default
Value
Bit
Access
Description
7
RW/L
0b
Reserved
Enhanced Mode Select (ENHMODESEL):
00 = Swap Enabled for Bank Selects and Rank Selects
01 = XOR Enabled for Bank Selects and Rank Selects
10 = Swap Enabled for Bank Selects only
6:5
RW/L
00b
11 = XOR Enabled for Bank Select only
This register is locked by ME stolen Memory lock.
4
3
2
1
RW/L
RW/L
RW/L
RW/L
0b
0b
0b
0b
Channel 2 Enhanced Mode (CH2_ENHMODE):
Channel 1 Enhanced Mode (CH1_ENHMODE):
Channel 0 Enhanced Mode (CH0_ENHMODE):
Reserved
EP Present (EPPRSNT): This bit indicates whether EP UMA is present in the
system or not.
0
RW/L
0b
This register is locked by ME stolen Memory lock.
Datasheet
99
DRAM Controller Registers (D0:F0)
5.2.2
C0DRB0—Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 200–201h
Default Value:
Access:
Size:
0000h
RO, RW/L
16 bits
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64MB. Each rank has its own single-word DRB register. These
registers are used to determine which chip select will be active for a given address.
Channel and rank map:
ch0 rank0:
ch0 rank1:
ch0 rank2:
ch0 rank3:
ch1 rank0:
ch1 rank1:
ch1 rank2:
ch1 rank3:
200h
202h
204h
206h
600h
602h
604h
606h
Programming guide:
Non-stacked mode:
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in ch0 rank0 (in 64MB increments)
C0DRB1 = Total memory in ch0 rank0 + ch0 rank1 (in 64MB increments)
and so on.
If Channel 1 is empty, all of the C1DRBs are programmed with 00h.
C1DRB0 = Total memory in ch1 rank0 (in 64MB increments)
C1DRB1 = Total memory in ch1 rank0 + ch1 rank1 (in 64MB increments)
and so on.
Stacked mode:
CODRBs:
Similar to Non-stacked mode.
C1DRB0, C1DRB1 and C1DRB2:
They are also programmed similar to non-stacked mode. Only exception is, the DRBs
corresponding to the topmost populated rank and the (unpopulated) higher ranks in
Channel 1 must be programmed with the value of the total Channel 1 population plus
the value of total Channel 0 population (C0DRB3).
Example: If only ranks 0 and 1 are populated in Ch1 in stacked mode, then
C1DRB0 = Total memory in ch1 rank0 (in 64MB increments)
100
Datasheet
DRAM Controller Registers (D0:F0)
C1DRB1 = C0DRB3 + Total memory in ch1 rank0 + ch1 rank1 (in 64MB increments)
(rank 1 is the topmost populated rank)
C1DRB2 = C1DRB1
C1DRB3 = C1DRB1
C1DRB3:
C1DRB3 = C0DRB3 + Total memory in Channel 1.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): This register
defines the DRAM rank boundary for rank0 of Channel 0 (64 MB granularity)
=R0
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
This register is locked by ME stolen Memory lock.
9:0
RW/L
000h
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 202–203h
Default Value:
Access:
Size:
0000h
RW/L, RO
16 bits
See C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 0 Dram Rank Boundary Address 1 (C0DRBA1): This field defines
the DRAM rank boundary for rank1 of Channel 0 (64 MB granularity)
=(R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
This register is locked by ME stolen Memory lock.
9:0
RW/L
000h
Datasheet
101
DRAM Controller Registers (D0:F0)
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 204–205h
Default Value:
Access:
Size:
0000h
RW/L, RO
16 bits
See C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): This register
defines the DRAM rank boundary for rank2 of Channel 0 (64 MB granularity)
=(R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
This register is locked by ME stolen Memory lock.
9:0
RW/L
000h
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 206–207h
Default Value:
Access:
Size:
0000h
RO, RW/L
16 bits
See C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3): This register
defines the DRAM rank boundary for rank3 of Channel 0 (64 MB granularity)
=(R3 + R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
This register is locked by ME stolen Memory lock.
9:0
RW/L
000h
102
Datasheet
DRAM Controller Registers (D0:F0)
5.2.6
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 208–209h
Default Value:
Access:
Size:
0000h
RW/L
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
Ch0 Rank2, 3:
Ch1 Rank0, 1:
Ch1 Rank2, 3:
208h–209h
20Ah–20Bh
608h–609h
60Ah–60Bh
DRA[6:0] = "00" means cfg0, DRA[6:0] ="01" means cfg1.... DRA[6:0] = "09" means
cfg9 and so on.
DRA[7] indicates whether it's an 8 bank config or not. DRA[7] = 0 means 4 bank,
DRA[7] = 1 means 8 bank.
Table 10.
DRAM Rank Attribute Register Programming
Page
Config
Tech
DDRx
Depth
Width
Row
Col
Bank
Row Size
Size
0
1
2
3
4
5
6
7
256Mb
256Mb
512Mb
512Mb
512Mb
512Mb
1 Gb
2
2
32M
16M
64M
32M
64M
32M
128M
64M
8
16
8
13
13
14
13
13
12
14
13
10
9
2
2
2
2
3
3
3
3
256 MB
128 MB
512 MB
256 MB
512 MB
256 MB
1 GB
8k
4k
8k
8k
8k
8k
8k
8k
2
10
10
10
10
10
10
2
16
8
3
3
16
8
2,3
2,3
1 Gb
16
512 MB
Default
Value
Bit
Access
Description
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This register defines
DRAM pagesize/number-of-banks for rank1 for given channel.
15:8
RW/L
RW/L
00h
See table in register description for programming.
This register is locked by ME stolen Memory lock.
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This register defines
DRAM page size/number-of-banks for rank0 for given channel.
7:0
00h
See table in register description for programming.
This register is locked by ME stolen Memory lock.
Datasheet
103
DRAM Controller Registers (D0:F0)
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 20A–20Bh
Default Value:
Access:
Size:
0000h
RW/L
16 bits
See C0DRA01 register.
Default
Value
Bit
Access
Description
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This register defines DRAM
pagesize/number-of-banks for rank3 for given channel.
15:8
RW/L
RW/L
00h
See table in register description for programming.
This register is locked by ME stolen Memory lock.
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This register defines DRAM
pagesize/number-of-banks for rank2 for given channel.
7:0
00h
See table in register description for programming.
This register is locked by ME stolen Memory lock.
5.2.8
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 250–251h
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
This is the Channel 0 CYCTRK Precharge registers.
Default
Value
Bit
Access
Description
15:11
RO
00000b Reserved
Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the minimum
10:6
5:2
RW
00000b allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the
same rank-bank. This field corresponds to tWR in the DDR Specification.
READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the minimum
0000b allowed spacing (in DRAM clocks) between the READ and PRE commands to the
same rank-bank
RW
RW
PRE To PRE Delayed (C0sd_cr_pchg_pchg): This field indicates the
1:0
00b
minimum allowed spacing (in DRAM clocks) between two PRE commands to the
same rank.
104
Datasheet
DRAM Controller Registers (D0:F0)
5.2.9
C0CYCTRKACT—Channel 0 CYCTRK ACT
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 252–255h
Default Value:
Access:
Size:
00000000h
RW, RO
32 bits
Channel 0 CYCTRK Activate registers.
Default
Value
Bit
Access
Description
31:28
RO
0h
Reserved
ACT Window Count (C0sd_cr_act_windowcnt): This field indicates the
window duration (in DRAM clocks) during which the controller counts the # of
activate commands which are launched to a particular rank. If the number of
activate commands launched within this window is greater than 4, then a check
is implemented to block launch of further activates to this rank for the rest of the
duration of this window.
27:22
RW
000000b
0b
Max ACT Check Disable (C0sd_cr_maxact_dischk): This field enables the
check which ensures that there are no more than four activates to a particular
rank in a given window.
21
RW
RW
ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the minimum
0000b allowed spacing (in DRAM clocks) between two ACT commands to the same
rank. This field corresponds to tRRD in the DDR Specification.
20:17
PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the minimum
allowed spacing (in DRAM clocks) between the PRE and ACT commands to the
same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed.
(C0sd_cr_preall_act):This field indicates the minimum allowed spacing (in DRAM
16:13
RW
0000b
clocks) between the PRE-ALL and ACT commands to the same rank. This field
corresponds to tRP in the DDR Specification.
ALLPRE to ACT Delay (C0sd0_cr_preall_act): From the launch of a
prechargeall command wait for these many # of memory clocks before
launching a activate command. This field corresponds to tPALL_RP in the DDR
Specification.
12:9
8:0
RW
RW
0h
REF to ACT Delayed (C0sd_cr_rfsh_act): This field indicates the minimum
allowed spacing (in DRAM clocks) between REF and ACT commands to the same
rank. This field corresponds to tRFC in the DDR Specification.
0000000
00b
Datasheet
105
DRAM Controller Registers (D0:F0)
5.2.10
C0CYCTRKWR—Channel 0 CYCTRK WR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 256–257h
Default Value:
Access:
Size:
0000h
RW
16 bits
Channel 0 CYCTRK WR registers.
Default
Value
Bit
Access
Description
ACT To Write Delay (C0sd_cr_act_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank. This field corresponds to tRCD_wr in the DDR Specificaiton.
15:12
RW
RW
0h
Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
11:8
7:4
0h
0h
0h
Different Rank Write to Write Delay (C0sd_cr_wrdr_wr): This field
register indicates the minimum allowed spacing (in DRAM clocks) between two
WRITE commands to different ranks. This field corresponds to tWR_WR in the
DDR Specification.
RW
RW
READ To WRTE Delay (C0sd_cr_rd_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and WRITE commands.
3:0
This field corresponds to tRD_WR
.
106
Datasheet
DRAM Controller Registers (D0:F0)
5.2.11
C0CYCTRKRD—Channel 0 CYCTRK READ
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 258–25Ah
Default Value:
Access:
Size:
000000h
RO, RW
24 bits
Channel 0 CYCTRK RD registers.
Default
Value
Bit
Access
Description
23:21
RO
000b
Reserved
Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank. This field corresponds to tRCD_rd in the DDR
specification.
20:17
16:12
11:8
RW
0h
Same Rank Write To READ Delayed (C0sd_cr_wrsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank. This field corresponds to tWTR in the DDR
specification.
RW
RW
00000b
0000b
Different Ranks Write To READ Delayed (C0sd_cr_wrdr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the WRITE
and READ commands to different ranks. This field corresponds to tWR_RD in the
DDR specification.
Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field indicates
7:4
3:0
RW
RW
0000b the minimum allowed spacing (in DRAM clocks) between two READ commands to
the same rank.
Different Ranks Read To Read Delayed (C0sd_cr_rddr_rd): This field
0000b indicates the minimum allowed spacing (in DRAM clocks) between two READ
commands to different ranks. This field corresponds to tRD_RD
.
5.2.12
C0CYCTRKREFR—Channel 0 CYCTRK REFR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 25B–25Ch
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Channel 0 CYCTRK Refresh registers.
Default
Value
Bit
Access
Description
15:13
RO
000b
Reserved
Same Rank PALL to REF Delayed (C0sd_cr_pchgall_rfsh): This field
12:9
8:0
RW
0000b indicates the minimum allowed spacing (in DRAM clocks) between the PRE-ALL
and REF commands to the same rank.
Same Rank REF to REF Delayed (C0sd_cr_rfsh_rfsh): This field indicates
the minimum allowed spacing (in DRAM clocks) between two REF commands to
0000000
RW
00b
same ranks.
Datasheet
107
DRAM Controller Registers (D0:F0)
5.2.13
C0CKECTRL—Channel 0 CKE Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 260–263h
Default Value:
Access:
Size:
00000800h
RW, RW/L, RO
32 bits
This register provides CKE controls for Channel 0.
Default
Value
Bit
Access
Description
31:28
27
RO
0000b Reserved
Start the Self-Refresh Exit Sequence (sd0_cr_srcstart): This field indicates
RW
0b
the request to start the self-refresh exit sequence
CKE Pulse Width Requirement in High Phase (sd0_cr_cke_pw_hl_safe):
This field indicates CKE pulse width requirement in high phase. This field
corresponds to tCKE (high) in the DDR specification.
26:24
23
RW
000b
Rank 3 Population (sd0_cr_rankpop3):
1 = Rank 3 populated
RW/L
0b
0b
0b
0 = Rank 3 not populated
This register is locked by ME stolen Memory lock.
Rank 2 Population (sd0_cr_rankpop2):
1 = Rank 2 populated
22
21
RW/L
RW/L
0 = Rank 2 not populated
This register is locked by ME stolen Memory lock.
Rank 1 Population (sd0_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated
This register is locked by ME stolen Memory lock.
Rank 0 Population (sd0_cr_rankpop0):
1 = Rank 0 populated
20
RW/L
RW
0b
0 = Rank 0 not populated
This register is locked by ME stolen Memory lock.
CKE Pulse Width Requirement in Low Phase (sd0_cr_cke_pw_lh_safe):
This configuration register indicates CKE pulse width requirement in low phase.
19:17
000b
This field corresponds to tCKE (low) in the DDR specification.
Enable CKE Toggle for PDN Entry/Exit (sd0_cr_pdn_enable): This bit
indicates that the toggling of CKEs (for PDN entry/exit) is enabled.
16
RW
RO
0b
15:14
00b
Reserved
Minimum Powerdown exit to Non-Read command spacing (sd0_cr_txp):
This field indicates the minimum number of clocks to wait following assertion of
CKE before issuing a non-read command.
13:10
RW
0010b
1010–1111 = Reserved.
0010–1001 = 2–9clocks.
0000–0001 = Reserved.
Self Refresh Exit Count (sd0_cr_slfrfsh_exit_cnt): This field indicates the
Self refresh exit count. (Program to 255). This field corresponds to tXSNR/tXSRD
in the DDR Specification.
0000000
00b
9:1
0
RW
RW
Indicates only 1 DIMM Populated (sd0_cr_singledimmpop): This field
indicates the that only 1 DIMM is populated.
0b
108
Datasheet
DRAM Controller Registers (D0:F0)
5.2.14
C0REFRCTRL—Channel 0 DRAM Refresh Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 269–26Eh
Default Value:
Access:
Size:
021830000C30h
RW, RO
48 bits
Settings to configure the DRAM refresh controller.
Default
Value
Bit
Access
Description
47:42
RO
00h
Reserved
Direct Rcomp Quiet Window (DIRQUIET): This configuration setting
41:37
36:32
RW
10000b indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
Indirect Rcomp Quiet Window (INDIRQUIET): This configuration setting
11000b indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
RW
Rcomp Wait (RCOMPWAIT): This configuration setting indicates the amount
00110b of refresh_tick events to wait before the service of rcomp request in non-default
mode of independent rank refresh.
31:27
26
RW
RW
0b
Reserved
Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit [23]
REFEN, the modes are:
25
RW
0b
[REFEN:REFCNTEN] Description
[0:0]
[0:1]
[1:X]
Normal refresh disable
Refresh disabled, but counter is accumulating refreshes.
Normal refresh enable
All Rank Refresh (ALLRKREF): This configuration bit enables (by default)
that all the ranks are refreshed in a staggered/atomic fashion. If set, the ranks
are refreshed in an independent fashion.
24
23
RW
RW
0b
0b
Refresh Enable (REFEN): Refresh is enabled.
0 = Disabled
1 = Enabled
DDR Initialization Done (INITDONE): Indicates that DDR initialization is
complete.
22
RW
RW
0b
21:20
00b
Reserved
DRAM Refresh Panic Watermark (REFPANICWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_panic flag is set.
00 = 5
01 = 6
10 = 7
11 = 8
19:18
RW
00b
Datasheet
109
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
DRAM Refresh High Watermark (REFHIGHWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_high flag is set.
00 = 3
01 = 4
10 = 5
11 = 6
17:16
RW
00b
DRAM Refresh Low Watermark (REFLOWWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_low flag is set.
00 = 1
01 = 2
10 = 3
11 = 4
15:14
RW
RW
00b
Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a
value that will provide 7.8 us at the memory clock frequency.
At various memory clock frequencies, this results in the following values:
00110000
13:0
110000b 400 Mhz -> C30 hex (Default Value)
533 Mhz -> 104B hex
666 Mhz -> 1450 hex
110
Datasheet
DRAM Controller Registers (D0:F0)
5.2.15
C0ECCERRLOG—Channel 0 ECC Error Log
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 280–287h
Default Value:
Access:
Size:
0000000000000000h
RO/P, RO
64 bits
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank/bank/row/column address
information of the address block of main memory of which an error (single bit or multi-
bit error) has occurred. Note that the address fields represent the address of the first
single or the first multiple bit error occurrence after the error flag bits in the ERRSTS
register have been cleared by software. A multiple bit error will overwrite a single bit
error. Once the error flag bits are set as a result of an error, this bit field is locked and
doesn't change as a result of a new error until the error flag is cleared by software.
Same is the case with error syndrome field, but the following priority needs to be
followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0
MERR on QW1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on
QW2 CERR on QW3
Default
Value
Bit
Access
Description
Error Column Address (ERRCOL): Row address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
63:48
47:32
31:29
RO/P
RO/P
RO/P
0000h
Error Row Address (ERRROW): Row address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
0000h
000b
Error Bank Address (ERRBANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
Error Rank Address (ERRRANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
00 = rank 0 (DIMM0)
01 = rank 1 (DIMM0)
10 = rank 2 (DIMM1)
11 = rank 3 (DIMM1)
28:27
RO/P
00b
26:24
23:16
15:2
RO
RO/P
RO
0h
00h
0h
Reserved
Error Syndrome (ERRSYND): Syndrome that describes the set of bits
associated with the first failing quadword.
Reserved
Multiple Bit Error Status (MERRSTS): This bit is set when an uncorrectable
multiple-bit error occurs on a memory read data transfer. When this bit is set,
the address that caused the error and the error syndrome are also logged and
they are locked until this bit is cleared. This bit is cleared when it receives an
indication that the processor has cleared the corresponding bit in the ERRSTS
register.
1
0
RO/P
RO/P
0b
0b
Correctable Error Status (CERRSTS): This bit is set when a correctable
single-bit error occurs on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also logged and they
are locked to further single bit errors, until this bit is cleared. But, a multiple bit
error that occurs after this bit is set will over-write the address/error syndrome
info. This bit is cleared when it receives an indication that the processor has
cleared the corresponding bit in the ERRSTS register.
Datasheet
111
DRAM Controller Registers (D0:F0)
5.2.16
C0ODTCTRL—Channel 0 ODT Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 29C–29Fh
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
This register provides ODT controls.
Default
Value
Bit
Access
Description
31:12
RO
00000h Reserved
DRAM ODT for Read Commands (sd0_cr_odt_duration_rd): Specifies the
duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
11:8
RW
0h
DRAM ODT for Write Commands (sd0_cr_odt_duration_wr): Specifies the
duration in MDCLKs to assert DRAM ODT for Write Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
7:4
3:0
RW
RW
0h
0h
MCH ODT for Read Commands (sd0_cr_mchodt_duration): Specifies the
duration in MDCLKs to assert MCH ODT for Read Commands
5.2.17
C1DRB0—Channel 1 DRAM Rank Boundary Address 0
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 600–601h
Default Value:
Access:
Size:
0000h
RW/L, RO
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0): See C0DRB0
register.
9:0
RW/L
000h
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
112
Datasheet
DRAM Controller Registers (D0:F0)
5.2.18
C1DRB1—Channel 1 DRAM Rank Boundary Address 1
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 602–603h
Default Value:
Access:
Size:
0000h
RO, RW/L
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See C0DRB1
register.
9:0
RW/L
000h
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
5.2.19
C1DRB2—Channel 1 DRAM Rank Boundary Address 2
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 604–605h
Default Value:
Access:
Size:
0000h
RW/L, RO
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2): See C0DRB2
register.
9:0
RW/L
000h
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
Datasheet
113
DRAM Controller Registers (D0:F0)
5.2.20
C1DRB3—Channel 1 DRAM Rank Boundary Address 3
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 606–607h
Default Value:
Access:
Size:
0000h
RW/L, RO
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
RO
000000b Reserved
Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See C0DRB3
register.
9:0
RW/L
000h
In stacked mode, this will be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
5.2.21
C1DRA01—Channel 1 DRAM Rank 0,1 Attributes
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 608–609h
Default Value:
Access:
Size:
0000h
RW/L
16 bits
The operation of this register is detailed in the description for register C0DRA01.
Default
Value
Bit
15:8
7:0
Access
Description
Channel 1 DRAM Rank-1 Attributes (C1DRA1): See C0DRA1 register.
RW/L
RW/L
00h
This register is locked by ME stolen Memory lock.
Channel 1 DRAM Rank-0 Attributes (C1DRA0): See C0DRA0 register.
00h
This register is locked by ME stolen Memory lock.
5.2.22
C1DRA23—Channel 1 DRAM Rank 2,3 Attributes
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 60A–60Bh
Default Value:
Access:
Size:
0000h
RW/L
16 bits
The operation of this register is detailed in the description for the C0DRA01 register.
Default
Value
Bit
15:8
7:0
Access
Description
Channel 1 DRAM Rank-3 Attributes (C1DRA3): See C0DRA3 register.
RW/L
RW/L
00h
This register is locked by ME stolen Memory lock.
Channel 1 DRAM Rank-2 Attributes (C1DRA2): See C0DRA2 register.
00h
This register is locked by ME stolen Memory lock.
114
Datasheet
DRAM Controller Registers (D0:F0)
5.2.23
C1CYCTRKPCHG—Channel 1 CYCTRK PCHG
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 650–651h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
Channel 1 CYCTRK Precharge registers.
Default
Value
Bit
Access
Description
15:11
RO
00000b Reserved
Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the minimum
00000b allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the
same rank-bank. This field corresponds to tWR in the DDR Specification.
10:6
5:2
RW
READ To PRE Delayed (C1sd_cr_rd_pchg): This field indicates the minimum
0000b allowed spacing (in DRAM clocks) between the READ and PRE commands to the
same rank-bank
RW
RW
PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field indicates the
1:0
00b
minimum allowed spacing (in DRAM clocks) between two PRE commands to the
same rank.
5.2.24
C1CYCTRKACT—Channel 1 CYCTRK ACT
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 652–655h
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
Channel 1 CYCTRK ACT registers.
Default
Value
Bit
Access
Description
31:28
RO
0h
Reserved
ACT Window Count (C1sd_cr_act_windowcnt): This field indicates the
window duration (in DRAM clocks) during which the controller counts the # of
activate commands which are launched to a particular rank. If the number of
activate commands launched within this window is greater than 4, then a check
is implemented to block launch of further activates to this rank for the rest of the
duration of this window.
27:22
RW
000000b
0b
Max ACT Check Disable (C1sd_cr_maxact_dischk):This field enables the
check which ensures that there are no more than four activates to a particular
rank in a given window.
21
RW
RW
ACT to ACT Delayed (C1sd_cr_act_act[): This field indicates the minimum
0000b allowed spacing (in DRAM clocks) between two ACT commands to the same
rank. This field corresponds to tRRD in the DDR specification.
20:17
Datasheet
115
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
PRE to ACT Delayed (C1sd_cr_pre_act): This field indicates the minimum
allowed spacing (in DRAM clocks) between the PRE and ACT commands to the
same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed
(C1sd_cr_preall_act):This field indicates the minimum allowed spacing (in DRAM
clocks) between the PRE-ALL and ACT commands to the same rank. This field
corresponds to tRP in the DDR Specification.
16:13
RW
0000b
0h
ALLPRE to ACT Delay (C1sd_cr_preall_act): From the launch of a
prechargeall command wait for these many # of memory clocks before
12:9
8:0
RW
RW
launching a activate command. This field corresponds to tPALL_RP
.
REF to ACT Delayed (C1sd_cr_rfsh_act): This field indicates the minimum
allowed spacing (in DRAM clocks) between REF and ACT commands to the same
rank. This field corresponds to tRFC in the DDR specification.
0000000
00b
5.2.25
C1CYCTRKWR—Channel 1 CYCTRK WR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 656–657h
Default Value:
Access:
Size:
0000h
RW
16 bits
Channel 1 CYCTRK WR registers.
Default
Value
Bit
Access
Description
ACT To Write Delay (C1sd_cr_act_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank. This field corresponds to tRCD_wr in the DDR Specification.
15:12
RW
RW
0h
Same Rank Write To Write Delayed (C1sd_cr_wrsr_wr): This field register
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
11:8
7:4
0h
0h
0h
Different Rank Write to Write Delay (C1sd_cr_wrdr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to different ranks. This field corresponds to tWR_WR in the DDR
Specification.
RW
RW
READ To WRTE Delay (C1sd_cr_rd_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and WRITE commands.
3:0
This field corresponds to tRD_WR
.
116
Datasheet
DRAM Controller Registers (D0:F0)
5.2.26
C1CYCTRKRD—Channel 1 CYCTRK READ
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 658–65Ah
Default Value:
Access:
Size:
000000h
RW, RO
24 bits
Channel 1 CYCTRK READ registers.
Default
Value
Bit
Access
Description
23:21
RO
0h
Reserved
Min ACT To READ Delayed (C1sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank. This field Corresponds to tRCD_rd in the DDR
Specification
20:17
16:12
11:8
RW
0h
Same Rank Write To READ Delayed (C1sd_cr_wrsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank. This field corresponds to tWTR in the DDR
Specification.
RW
RW
00000b
0000b
Different Ranks Write To READ Delayed (C1sd_cr_wrdr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the WRITE
and READ commands to different ranks. This field corresponds to tWR_RD in the
DDR Specification.
Same Rank Read To Read Delayed (C1sd_cr_rdsr_rd): This field indicates
7:4
3:0
RW
RW
0000b the minimum allowed spacing (in DRAM clocks) between two READ commands to
the same rank.
Different Ranks Read To Read Delayed (C1sd_cr_rddr_rd): This field
0000b indicates the minimum allowed spacing (in DRAM clocks) between two READ
commands to different ranks. This field corresponds to tRD_RD
.
Datasheet
117
DRAM Controller Registers (D0:F0)
5.2.27
C1CKECTRL—Channel 1 CKE Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 660–663h
Default Value:
Access:
Size:
00000800h
RO, RW/L, RW
32 bits
Channel 1 CKE Control registers.
Default
Value
Bit
Access
Description
31:28
27
RO
0h
Reserved
Start the Self-Refresh Exit Sequence (sd1_cr_srcstart): This bit indicates
the request to start the self-refresh exit sequence
RW
0b
CKE Pulse Width Requirement in High Phase (sd1_cr_cke_pw_hl_safe):
This bit indicates CKE pulse width requirement in high phase. This field
Corresponds to tCKE (high) in the DDR Specification.
26:24
23
RW
000b
Rank 3 Population (sd1_cr_rankpop3):
1 = Rank 3 populated
RW/L
0b
0b
0b
0 = Rank 3 not populated
This register is locked by ME stolen Memory lock.
Rank 2 Population (sd1_cr_rankpop2):
1 = Rank 2 populated
22
21
RW/L
RW/L
0 = Rank 2 not populated
This register is locked by ME stolen Memory lock.
Rank 1 Population (sd1_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated
This register is locked by ME stolen Memory lock.
Rank 0 Population (sd1_cr_rankpop0):
1 = Rank 0 populated
20
RW/L
RW
0b
0 = Rank 0 not populated
This register is locked by ME stolen Memory lock.
CKE Pulse Width Requirement in Low Phase (sd1_cr_cke_pw_lh_safe):
This field indicates CKE pulse width requirement in low phase. This field
Corresponds to tCKE (low) in the DDR Specification.
19:17
000b
Enable CKE Toggle for PDN Entry/Exit (sd1_cr_pdn_enable): This bit
indicates that the toggling of CKEs (for PDN entry/exit) is enabled.
16
RW
RO
0b
15:14
00b
Reserved
Minimum Powerdown Exit to Non-Read Command Spacing
(sd1_cr_txp): This field indicates the minimum number of clocks to wait
following assertion of CKE before issuing a non-read command.
13:10
RW
0010b
1010–1111 = Reserved.
0010–1001 = 2–9 clocks
0000–0001 = Reserved.
Self Refresh Exit Count (sd1_cr_slfrfsh_exit_cnt): This configuration
register indicates the Self refresh exit count. (Program to 255)
0000000
00b
9:1
0
RW
RW
Corresponds to tXSNR/tXSRD in the DDR Specification.
Indicates Only 1 DIMM Populated (sd1_cr_singledimmpop): This field
indicates the that only 1 DIMM is populated.
0b
118
Datasheet
DRAM Controller Registers (D0:F0)
5.2.28
C1REFRCTRL—Channel 1 DRAM Refresh Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 669–66Eh
Default Value:
Access:
Size:
021830000C30h
RW, RO
48 bits
Settings to configure the DRAM refresh controller.
Default
Value
Bit
Access
Description
47:42
RO
00h
Reserved
Direct Rcomp Quiet Window (DIRQUIET): This configuration setting
41:37
36:32
RW
10000b indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
Indirect Rcomp Quiet Window (INDIRQUIET): This configuration setting
11000b indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
RW
Rcomp Wait (RCOMPWAIT): This configuration setting indicates the amount
00110b of refresh_tick events to wait before the service of rcomp request in non-default
mode of independent rank refresh.
31:27
26
RW
RO
0b
Reserved
Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit 23
REFEN, the modes are:
25
RW
0b
[REFEN:REFCNTEN]Description
[0:0]
[0:1]
[1:X]
Normal refresh disable
Refresh disabled, but counter is accumulating refreshes.
Normal refresh enable
All Rank Refresh (ALLRKREF): This configuration bit enables (by default) that
all the ranks are refreshed in a staggered/atomic fashion. If set, the ranks are
refreshed in an independent fashion.
24
23
RW
RW
0b
0b
Refresh Enable (REFEN): Refresh is enabled.
0 = Disabled
1 = Enabled
DDR Initialization Done (INITDONE): Indicates that DDR initialization is
complete.
22
RW
RO
0b
21:20
00b
Reserved
DRAM Refresh Panic Watermark (REFPANICWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_panic flag is set.
00 = 5
01 = 6
10 = 7
11 = 8
19:18
RW
00b
Datasheet
119
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
DRAM Refresh High Watermark (REFHIGHWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_high flag is set.
00 = 3
01 = 4
10 = 5
11 = 6
17:16
RW
00b
00b
DRAM Refresh Low Watermark (REFLOWWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_low flag is set.
00 = 1
01 = 2
10 = 3
11 = 4
15:14
RW
RW
Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a
value that will provide 7.8 us at the memory clock frequency.
0011000
0110000
b
At various memory clock frequencies, this results in the following values:
400 Mhz -> C30 hex (Default Value)
533 Mhz -> 104B hex
13:0
666 Mhz -> 1450 hex
5.2.29
C1ECCERRLOG—Channel 1 ECC Error Log
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 680–687h
Default Value:
Access:
Size:
0000000000000000h
RO/P, RO
64 bits
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank/bank/row/column address
information of the address block of main memory of which an error (single bit or multi-
bit error) has occurred. Note that the address fields represent the address of the first
single or the first multiple bit error occurrence after the error flag bits in the ERRSTS
register have been cleared by software. A multiple bit error will overwrite a single bit
error. Once the error flag bits are set as a result of an error, this bit field is locked and
does not change as a result of a new error until the error flag is cleared by software.
Same is the case with error syndrome field, but the following priority needs to be
followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0,
MERR on QW1, MERR on QW2, MERR on QW3, CERR on QW0, CERR on QW1, CERR on
QW2, CERR on QW3.
Default
Value
Bit
Access
Description
Error Column Address (ERRCOL): Row address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
63:48
47:32
31:29
RO/P
RO/P
RO/P
0000h
Error Row Address (ERRROW): Row address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
0000h
000b
Error Bank Address (ERRBANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
120
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
Error Rank Address (ERRRANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
00 = rank 0 (DIMM0)
01 = rank 1 (DIMM0)
10 = rank 2 (DIMM1)
11 = rank 3 (DIMM1)
28:27
RO/P
00b
26:24
23:16
15:2
RO
RO/P
RO
0h
00h
0h
Reserved
Error Syndrome (ERRSYND): Syndrome that describes the set of bits
associated with the first failing quadword.
Reserved
Multiple Bit Error Status (MERRSTS): This bit is set when an uncorrectable
multiple-bit error occurs on a memory read data transfer. When this bit is set,
the address that caused the error and the error syndrome are also logged and
they are locked until this bit is cleared. This bit is cleared when it receives an
indication that the processor has cleared the corresponding bit in the ERRSTS
register.
1
RO/P
RO/P
0b
0b
Correctable Error Status (CERRSTS): This bit is set when a correctable
single-bit error occurs on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also logged and they
are locked to further single bit errors, until this bit is cleared. But, a multiple bit
error that occurs after this bit is set will over-write the address/error syndrome
info. This bit is cleared when it receives an indication that the processor has
cleared the corresponding bit in the ERRSTS register.
0
5.2.30
C1ODTCTRL—Channel 1 ODT Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 69C–69Fh
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
This register provides ODT controls.
Default
Value
Bit
Access
Description
31:12
RO
00000h Reserved
DRAM ODT for Read Commands (sd1_cr_odt_duration_rd): Specifies the
duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
11:8
RW
0h
DRAM ODT for Write Commands (sd1_cr_odt_duration_wr): Specifies the
duration in MDCLKs to assert DRAM ODT for Write Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
7:4
3:0
RW
RW
0h
0h
MCH ODT for Read Commands (sd1_cr_mchodt_duration): Specifies the
duration in MDCLKs to assert MCH ODT for Read Commands.
Datasheet
121
DRAM Controller Registers (D0:F0)
5.2.31
EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A00–A01h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
Default
Bit
Access
Description
Value
000000b Reserved
000h Channel 0 Dram Rank Boundary Address 0 (C0DRBA0):
15:10
9:0
RO
RW
5.2.32
EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A02–A03h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
See C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
9:0
RO
000000b Reserved
RW
000h
Channel 0 Dram Rank Boundary Address 1 (C0DRBA1):
5.2.33
EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A04–A05h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
See C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
9:0
RO
000000b Reserved
RW
000h
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2):
122
Datasheet
DRAM Controller Registers (D0:F0)
5.2.34
EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A06–A07h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
See C0DRB0 register.
Default
Value
Bit
Access
Description
15:10
9:0
RO
000000b Reserved
RW
000h
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3):
5.2.35
EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A08–A09h
Default Value:
Access:
Size:
0000h
RW
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
Ch0 Rank2, 3:
Ch1 Rank0, 1:
Ch1 Rank2, 3:
108h–109h
10Ah–10Bh
188h–189h
18Ah–18Bh
Default
Value
Bit
Access
Description
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This register defines DRAM
pagesize/number-of-banks for rank1 for given channel.
15:8
7:0
RW
RW
00h
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This register defines DRAM
pagesize/number-of-banks for rank0 for given channel.
00h
Datasheet
123
DRAM Controller Registers (D0:F0)
5.2.36
EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A0A–A0Bh
Default Value:
Access:
Size:
0000h
RW
16 bits
See C0DRA01 register.
Default
Value
Bit
Access
Description
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This register defines DRAM
pagesize/number-of-banks for rank3 for given channel.
15:8
7:0
RW
RW
00h
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This register defines DRAM
pagesize/number-of-banks for rank2 for given channel.
00h
5.2.37
EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A19–A1Ah
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
EPD CYCTRK WRT PRE Status registers.
Default
Value
Bit
Access
Description
ACTTo PRE Delayed (C0sd_cr_act_pchg): This field indicates the minimum
15:11
RW
RW
00000b allowed spacing (in DRAM clocks) between the ACT and PRE commands to the
same rank-bank
Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the minimum
00000b allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the
same rank-bank
10:6
READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the minimum
0000b allowed spacing (in DRAM clocks) between the READ and PRE commands to the
same rank-bank
5:2
1:0
RW
RO
00b
Reserved
124
Datasheet
DRAM Controller Registers (D0:F0)
5.2.38
EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A1C–A1Fh
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
EPD CYCTRK WRT ACT Status registers.
Default
Value
Bit
Access
Description
31:21
RO
000h
Reserved
ACT to ACT Delayed (C0sd_cr_act_act[): This configuration register
20:17
16:13
RW
0000b indicates the minimum allowed spacing (in DRAM clocks) between two ACT
commands to the same rank.
PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the minimum
allowed spacing (in DRAM clocks) between the PRE and ACT commands to the
same rank-bank:12:9R/W0000bPRE-ALL to ACT Delayed
(C0sd_cr_preall_act):This configuration register indicates the minimum allowed
RW
0000b
spacing (in DRAM clocks) between the PRE-ALL and ACT commands to the same
rank.
12:9
8:0
RO
0h
Reserved
REF to ACT Delayed (C0sd_cr_rfsh_act): This configuration register
indicates the minimum allowed spacing (in DRAM clocks) between REF and ACT
commands to the same rank.
0000000
00b
RW
5.2.39
EPDCYCTRKWRTWR—EPD CYCTRK WRT WR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A20–A21h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
EPD CYCTRK WRT WR Status registers.
Default
Value
Bit
Access
Description
ACT To Write Delay (C0sd_cr_act_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank
15:12
RW
0h
Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
11:8
7:4
RW
RO
RW
0h
0h
0h
Reserved
Same Rank WRITE to READ Delay (C0sd_cr_rd_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank.
3:0
Datasheet
125
DRAM Controller Registers (D0:F0)
5.2.40
EPDCYCTRKWRTREF—EPD CYCTRK WRT REF
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A22–A23h
0000h
RO, RW
16 bits
0h
Size:
BIOS Optimal Default
EPD CYCTRK WRT ACT Status registers.
Default
Value
Bit
Access
Description
15:9
RO
0s
Reserved
Different Rank REF to REF Delayed (C0sd_cr_rfsh_rfsh): This
configuration register indicates the minimum allowed spacing (in DRAM clocks)
between two REF commands to different ranks.
0000000
00b
8:0
RW
5.2.41
EPDCYCTRKWRTRD—EPD CYCTRK WRT READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A24–A26h
000000h
RW
Size:
24 bits
BIOS Optimal Default
000h
EPD CYCTRK WRT RD Status registers.
Default
Value
Bit
Access
Description
23:23
22:20
19:18
RO
RW
RO
0h
Reserved
EPDunit DQS Slave DLL Enable to Read Safe (EPDSDLL2RD): Configuration
setting for Read command safe from the point of enabling the slave DLLs.
000b
0h
Reserved
Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank
17:14
RW
0h
Same Rank READ to WRITE Delayed (C0sd_cr_wrsr_rd): This field
13:9
8:6
5:3
2:0
RW
RO
RW
RO
00000b indicates the minimum allowed spacing (in DRAM clocks) between the READ and
WRITE commands.
0h
000b
0h
Reserved
Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field indicates
the minimum allowed spacing (in DRAM clocks) between two READ commands to
the same rank.
Reserved
126
Datasheet
DRAM Controller Registers (D0:F0)
5.2.42
EPDCKECONFIGREG—EPD CKE Related Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A28–A2Ch
00E0000000h
RW
Size:
40 bits
BIOS Optimal Default
0h
CKE related configuration registers For EPD.
Default
Value
Bit
Access
Description
EPDunit TXPDLL Count (EPDTXPDLL): Specifies the delay from precharge
39:35
RW
RW
RW
00000b power down exit to a command that requires the DRAM DLL to be operational.
The commands are read/write.
EPDunit TXP Count (EPDCKETXP): Specifies the timing requirement for
34:32
31:29
000b
111b
Active power down exit or fast exit pre-charge power down exit to any command
or slow exit pre-charge power down to Non-DLL (rd/wr/odt) command.
Mode Select (sd0_cr_sms): Mode Select register: This configuration setting
indicates the mode in which the controller is operating in.
111 = Indicates normal mode of operation, else special mode of operation.
EPDunit EMRS Command Select. (EPDEMRSSEL): EMRS mode to select
BANK address.
01 = EMRS
10 = EMRS2
11 = EMRS3
28:27
RW
00b
CKE Pulse Width Requirement in High Phase (sd0_cr_cke_pw_hl_safe):
This field indicates CKE pulse width requirement in high phase.
26:24
23:20
RW
RW
000b
0h
One-Hot Active Rank Population (ep_scr_actrank): This field indicates the
active rank in a one hot manner
CKE Pulse Width Requirement in Low Phase (sd0_cr_cke_pw_lh_safe):
This field indicates CKE pulse width requirement in low phase.
19:17
16:15
RW
RO
000b
0h
Reserved
EPDunit MPR Mode (EPDMPR): MPR Read Mode
1 = MPR mode
14
RW
0b
0b
0 = Normal mode
In MPR mode, only read cycles must be issued by Firmware. Page Results are
ignored by DCS and just issues the read chip select.
EPDunit Power Down enable for ODT Rank (EPDOAPDEN): Configuration
to enable the ODT ranks to dynamically enter power down.
13
12
RW
RW
1 = Enable active power down.
0 = Disable active power down.
EPDunit Power Down enable for Active Rank (EPDAAPDEN): Configuration
to enable the active rank to dynamically enter power down.
0b
0h
1 = Enable active power down.
0 = Disable active power down.
11:10
9:1
RO
Reserved
0000000 Self Refresh Exit Count (sd0_cr_slfrfsh_exit_cnt): This field indicates the
00b Self refresh exit count. (Program to 255)
RW
Datasheet
127
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
Indicates Only 1 Rank Enabled (sd0_cr_singledimmpop): This field
indicates the that only 1 rank is enabled. This bit needs to be set if there is one
active rank and no odt ranks, or if there is one active rank and one ODT rank and
they are the same rank.
0
RW
0b
5.2.43
EPDREFCONFIG—EP DRAM Refresh Configuration
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A30–A33h
Default Value:
Access:
Size:
40000C30h
RW, RO
32 bits
Settings to configure the EPD refresh controller.
Default
Value
Bit
Access
Description
31
RO
0b
Reserved
EPDunit refresh count addition for self refresh exit. (EPDREF4SR):
Configuration indicating the number of additional refreshes that needs to be
added to the refresh request count after exiting self refresh.
Typical value is to add 2 refreshes.
00 = Add 0 Refreshes
30:29
RW
10b
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit [23]
REFEN, the modes are:
28
RW
0b
[REFEN:REFCNTEN] Description
[0:0]
[0:1]
[1:X]
Normal refresh disable
Refresh disabled, but counter is accumulating refreshes.
Normal refresh enable
Refresh Enable (REFEN): Refresh is enabled.
27
26
RW
RW
0b
0b
0 = Disabled
1 = Enabled
DDR Initialization Done (INITDONE): Indicates that DDR initialization is
complete.
128
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
DRAM Refresh Hysterisis (REFHYSTERISIS): Hysterisis level - Useful for
dref_high watermark cases. The dref_high flag is set when the dref_high
watermark level is exceeded, and is cleared when the refresh count is less than
the hysterisis level. This bit should be set to a value less than the high
watermark level.
25:22
RW
0000b
0000 = 0
0001 = 1
.......
1000 = 8
DRAM Refresh High Watermark (REFHIGHWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_high flag is set.
0000 = 0
0001 = 1
.......
21:18
RW
0000b
0000b
1000 = 8
DRAM Refresh Low Watermark (REFLOWWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_low flag is set.
0000 = 0
0001 = 1
.......
17:14
RW
RW
1000 = 8
Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a
value that will provide 7.8 us at memory clock frequency.
0011000
0110000
b
At various memory clock frequencies, this results in the following values:
400 Mhz -> C30 hex (Default Value)
533 Mhz -> 104B hex
13:0
666 Mhz -> 1450 hex
Datasheet
129
DRAM Controller Registers (D0:F0)
5.2.44
TSC1—Thermal Sensor Control 1
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CD8h
Default Value:
Access:
Size:
00h
RW/L, RW, RS/WC
8 bits
This register controls the operation of the thermal sensor.
Bits 7:1 of this register are reset to their defaults by MPWROK.
Bit 0 is reset to it's default by PLTRST#.
Default
Value
Bit
Access
Description
Thermal Sensor Enable (TSE): This bit enables power to the thermal sensor.
Lockable via TCO bit [7].
7
RW/L
RW
0b
0 = Disabled
1 = Enabled
Analog Hysteresis Control (AHC): This bit enables the analog hysteresis
control to the thermal sensor. When enabled, about 1 degree of hysteresis is
applied. This bit should normally be off in thermometer mode since the
thermometer mode of the thermal sensor defeats the usefulness of analog
hysteresis.
6
0b
0 = Hysteresis disabled
1 = Analog hysteresis enabled.
Digital Hysteresis Amount (DHA): This bit determines whether no offset, 1
LSB, 2... 15 is used for hysteresis for the trip points.
0000 = Digital hysteresis disabled, no offset added to trip temperature
0001 = Offset is 1 LSB added to each trip temperature when tripped
...
5:2
RW
0000b
0110 = ~3.0 °C (Recommended setting)
...
1110 = Added to each trip temperature when tripped
1111 = Added to each trip temperature when tripped
Thermal Sensor Comparator Select (TSCS): This bit multiplexes between
the two analog comparator outputs. Normally Catastrophic is used. Lockable via
TCO bit [7].
1
RW/L
0b
0 = Catastrophic
1 = Hot
130
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
In Use (IU): Software semaphore bit.
After a full MCH RESET, a read to this bit returns a 0.
After the first read, subsequent reads will return a 1.
A write of a 1 to this bit will reset the next read value to 0.
Writing a 0 to this bit has no effect.
Software can poll this bit until it reads a 0, and will then own the usage of the
thermal sensor.
0
RS/WC
0b
This bit has no other effect on the hardware, and is only used as a semaphore
among various independent software threads that may need to use the thermal
sensor.
Software that reads this register but does not intend to claim exclusive access of
the thermal sensor must write a one to this bit if it reads a 0, in order to allow
other software threads to claim it.
See also THERM3 bit 7 and IUB, which are independent additional semaphore
bits.
5.2.45
TSC2—Thermal Sensor Control 2
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CD9h
Default Value:
Access:
Size:
00h
RO, RW/L
8 bits
This register controls the operation of the thermal sensor.
All bits in this register are reset to their defaults by MPWROK.
Default
Value
Bit
Access
RO
Description
7:4
0h
Reserved
Datasheet
131
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
Thermometer Mode Enable and Rate (TE): If analog thermal sensor mode is
not enabled by setting these bits to 0000b, these bits enable the thermometer
mode functions and set the Thermometer controller rate.
When the Thermometer mode is disabled and TSC1[TSE] =enabled, the analog
sensor mode should be fully functional. In the analog sensor mode, the
Catastrophic trip is functional, and the Hot trip is functional at the offset below
the catastrophic programmed into TSC2[CHO]. The other trip points are not
functional in this mode.
When Thermometer mode is enabled, all the trip points (Catastrophic, Hot,
Aux0) will all operate using the programmed trip points and Thermometer mode
rate.
Note: When disabling the Thermometer mode while thermometer running, the
Thermometer mode controller will finish the current cycle.
Note: During boot, all other thermometer mode registers (except lock bits)
should be programmed appropriately before enabling the Thermometer Mode.
Clocks are memory clocks.
Note: Since prior MCHs counted the thermometer rate in terms of host clocks
rather than memory clocks, the clock count for each setting listed below has
been doubled from what is was on those MCHs. This should make the actual
thermometer rate approximately equivalent across products.
3:0
RW/L
0h
Lockable via TCO bit 7.
0000 = Thermometer mode disabled (i.e, analog sensor mode)
0001 = enabled, 512 clock mode
0010 = enabled, 1024 clock mode (normal Thermometer mode operation),
provides ~3.85 us settling time @ 266 MHz
provides ~3.08 us settling time @ 333 MHz
provides ~2.56 us settling time @ 400 MHz
0011 = enabled, 1536 clock mode
0100 = enabled, 2048 clock mode
0101 = enabled, 3072 clock mode
0110 = enabled, 4096 clock mode
0111 = enabled, 6144 clock mode
provides ~23.1 us settling time @ 266 MHz
provides ~18.5 us settling time @ 333 MHz
provides ~15.4 us settling time @ 400 MHz
all other permutations reserved
1111 = enabled, 4 clock mode (for testing digital logic)
132
Datasheet
DRAM Controller Registers (D0:F0)
5.2.46
TSS—Thermal Sensor Status
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CDAh
Default Value:
Access:
Size:
00h
RO
8 bits
This read only register provides trip point and other status of the thermal sensor.
All bits in this register are reset to their defaults by MPWROK.
Default
Value
Bit
Access
Description
Catastrophic Trip Indicator (CTI): A 1 indicates that the internal thermal
sensor temperature is above the catastrophic setting.
7
6
5
RO
RO
RO
0b
Hot Trip Indicator (HTI): A 1 indicates that the internal thermal sensor
temperature is above the Hot setting.
0b
0b
Aux0 Trip Indicator (A0TI): A 1 indicates that the internal thermal sensor
temperature is above the Aux0 setting.
Thermometer Mode Output Valid (TOV): A 1 indicates the Thermometer
mode is able to converge to a temperature and that the TR register is reporting a
reasonable estimate of the thermal sensor temperature. A 0 indicates the
Thermometer mode is off, or that temperature is out of range, or that the TR
register is being looked at before a temperature conversion has had time to
complete.
4
RO
0b
3:2
1
RO
RO
00b
0b
Reserved
Direct Catastrophic Comparator Read (DCCR): This bit reads the output of
the Catastrophic comparator directly, without latching via the Thermometer
mode circuit. Used for testing.
Direct Hot Comparator Read (DHCR): This bit reads the output of the Hot
comparator directly, without latching via the Thermometer mode circuit. Used
for testing.
0
RO
0b
Datasheet
133
DRAM Controller Registers (D0:F0)
5.2.47
TSTTP—Thermal Sensor Temperature Trip Point
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CDC–CDFh
Default Value:
Access:
Size:
00000000h
RO, RW, RW/L
32 bits
This register provides the following:
• Sets the target values for the trip points in thermometer mode. See also TST[Direct
DAC Connect Test Enable].
• Reports the relative thermal sensor temperature.
All bits in this register are reset to their defaults by MPWROK.
Default
Value
Bit
Access
Description
Relative Temperature (RELT): In Thermometer mode, the RELT field of this
register report the relative temperature of the thermal sensor. Provides a two's
complement value of the thermal sensor relative to the Hot Trip Point.
Temperature above the Hot Trip Point will be positive.
31:24
RO
00h
TR and HTPS can both vary between 0 and 255. But RELT will be clipped between
±127 to keep it an 8 bit number.
See also TSS[Thermometer mode Output Valid]
In the Analog mode, the RELT field reports HTPS value.
23:16
15:8
RW
00h
00h
Aux0 Trip point setting (A0TPS): Sets the target for the Aux0 trip point.
Hot Trip Point Setting (HTPS): Sets the target value for the Hot trip point.
RW/L
Lockable via TCO bit 7.
Catastrophic Trip Point Setting (CTPS): Sets the target for the Catastrophic
trip point. See also TST[Direct DAC Connect Test Enable].
7:0
RW/L
00h
Lockable via TCO bit 7.
134
Datasheet
DRAM Controller Registers (D0:F0)
5.2.48
TCO—Thermal Calibration Offset
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CE2h
Default Value:
Access:
Size:
00h
RW/L/K, RW/L
8 bits
Bit 7: reset to it's default by PLTRST#
Bits 6:0 reset to their defaults by MPWROK
Default
Value
Bit
Access
Description
Lock Bit for Catastrophic (LBC): This bit, when written to a 1, locks the
Catastrophic programming interface, including bits [7:0] of this register and bits
[15:0] of TSTTP, bits [1],[7] of TSC 1, bits [3:0] of TSC 2, bits [4:0] of TSC 3,
and bits [0],[7] of TST. This bit may only be set to a 0 by a hardware reset
(PLTRST#). Writing a 0 to this bit has no effect.
7
RW/L/K
0b
Calibration Offset (CO): This field contains the current calibration offset for
the Thermal Sensor DAC inputs. The calibration offset is a twos complement
signed number which is added to the temperature counter value to help
generate the final value going to the thermal sensor DAC.
This field is Read/Write and can be modified by Software unless locked by setting
bit [7] of this register.
The fuses cannot be programmed via this register.
6:0
RW/L
00h
Once this register has been overwritten by software, the values of the TCO fuses
can be read using the Therm3 register.
Note for TCO operation:
While this is a seven-bit field, the 7th bit is sign extended to 9 bits for TCO
operation. The range of 00h to 3fh corresponds to 0 0000 0000 to 0 0011 1111.
The range of 41h to 7Fh corresponds to 1 1100 001 (i.e, negative 3Fh) to 1 1111
1111 (i.e, negative 1), respectively.
Datasheet
135
DRAM Controller Registers (D0:F0)
5.2.49
THERM1—Thermal Hardware Protection
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CE4h
Default Value:
Access:
Size:
00h
RW/L, RO, RW/L/K
8 bits
All bits in this register are reset to their defaults by PLTRST#.
Default
Value
Bit
Access
Description
7:4
RO
RW/L
RO
0b
Reserved
Halt on Catastrophic (HOC):
0 = Continue to toggle clocks when the catastrophic sensor trips.
3
2:1
0
0b
00b
0b
1 = All clocks are disabled when the catastrophic sensor trips. A system reset is
required to bring the system out of a halt from the thermal sensor.
Reserved
Hardware Throttling Lock Bit (HTL): This bit locks bits [7:0] of this register.
The register bits are unlocked.
RW/L/K
1 = The register bits are locked. It may only be set to a 0 by a hardware reset.
Writing a 0 to this bit has no effect.
5.2.50
TIS—Thermal Interrupt Status
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CEA–CEBh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
This register is used to report which specific error condition resulted in the Device 0
Function 0 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR
Thermal Event. SW can examine the current state of the thermal zones by examining
the TSS. Software can distinguish internal or external Trip Event by examining
EXTTSCS.
Software must write a 1 to clear the status bits in this register.
Following scenario is possible. An interrupt is initiated on a rising temperature trip, the
appropriate DMI cycles are generated, and eventually the software services the
interrupt and sees a rising temperature trip as the cause in the status bits for the
interrupts. Assume that the software then goes and clears the local interrupt status bit
in the TIS register for that trip event. It is possible at this point that a falling
temperature trip event occurs before the software has had the time to clear the global
interrupts status bit. But since software has already looked at the status register before
this event happened, software may not clear the local status flag for this event.
Therefore, after the global interrupt is cleared by sw, sw must look at the
instantaneous status in the TSS register.
All bits in this register are reset to their defaults by PLTRST#.
136
Datasheet
DRAM Controller Registers (D0:F0)
Default
Value
Bit
Access
Description
15:10
RO
00h
Reserved
Was Catastrophic Thermal Sensor Interrupt Event (WCTSIE):
1 = Indicates that a Catastrophic Thermal Sensor trip based on a higher to lower
temperature transition thru the trip point
9
8
RWC
RWC
0b
0b
0 = No trip for this event
Was Hot Thermal Sensor Interrupt Event (WHTSIE):
1 = Indicates that a Hot Thermal Sensor trip based on a higher to lower
temperature transition thru the trip point
0 = No trip for this event
Was Aux0 Thermal Sensor Interrupt Event (WA0TSIE):
1 = Indicates that an Aux0 Thermal Sensor trip based on a higher to lower
temperature transition thru the trip point
7
6:5
4
RWC
RO
0b
00b
0b
0 = No trip for this event Software must write a 1 to clear this status bit.
Reserved
Catastrophic Thermal Sensor Interrupt Event (CTSIE):
1 = Indicates that a Catastrophic Thermal Sensor trip event occurred based on a
lower to higher temperature transition thru the trip point.
RWC
0 = No trip for this event Software must write a 1 to clear this status bit.
Hot Thermal Sensor Interrupt Event (HTSIE):
1 = Indicates that a Hot Thermal Sensor trip event occurred based on a lower to
higher temperature transition thru the trip point.
3
RWC
0b
0 = No trip for this event Software must write a 1 to clear this status bit.
Aux0 Thermal Sensor Interrupt Event (A0TSIE):
1 = Indicates that an Aux0 Thermal Sensor trip event occurred based on a lower
to higher temperature transition thru the trip point.
2
RWC
RO
0b
0 = No trip for this event Software must write a 1 to clear this status bit.
1:0
00b
Reserved
Datasheet
137
DRAM Controller Registers (D0:F0)
5.2.51
TSMICMD—Thermal SMI Command
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: CF1h
Default Value:
Access:
Size:
00h
RO, RW
8 bits
This register selects specific errors to generate a SMI DMI special cycle, as enabled by
the Device 0 SMI Error Command Register [SMI on MCH Thermal Sensor Trip]. The SMI
must not be enabled at the same time as the SERR/SCI for the thermal sensor event.
All bits in this register are reset to their defaults by PLTRST#.
Default
Value
Bit
Access
Description
7:3
RO
00h
Reserved
SMI on MCH Catastrophic Thermal Sensor Trip (SMGCTST):
1 = Does not mask the generation of an SMI DMI special cycle on a catastrophic
thermal sensor trip.
2
1
0
RW
0b
0b
0b
0 = Disable reporting of this condition via SMI messaging.
SMI on MCH Hot Thermal Sensor Trip (SMGHTST):
1 = Does not mask the generation of an SMI DMI special cycle on a Hot thermal
sensor trip.
RW
RW
0 = Disable reporting of this condition via SMI messaging.
SMI on MCH Aux Thermal Sensor Trip (SMGATST):
1 = Does not mask the generation of an SMI DMI special cycle on an Auxiliary
thermal sensor trip.
0 = Disable reporting of this condition via SMI messaging.
138
Datasheet
DRAM Controller Registers (D0:F0)
5.2.52
PMSTS—Power Management Status
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: F14–F17h
Default Value:
Access:
Size:
00000000h
RWC/S, RO
32 bits
This register is Reset by PWROK only.
Default
Value
Bit
Access
Description
31:9
RO
RWC/S
RO
000000h Reserved
Warm Reset Occurred (WRO): Set by the PMunit whenever a Warm Reset is
received, and cleared by PWROK=0.
0 = No Warm Reset occurred.
1 = Warm Reset occurred.
8
0b
BIOS Requirement: BIOS can check and clear this bit whenever executing
POST code. This way BIOS knows that if the bit is set, then the PMSTS bits [1:0]
must also be set, and if not BIOS needs to power-cycle the platform.
7:2
00h
Reserved
Channel 1 in Self-Refresh (C1SR): Set by power management hardware after
Channel 1 is placed in self refresh as a result of a Power State or a Reset Warn
sequence.
Cleared by Power management hardware before starting Channel 1 self refresh
exit sequence initiated by a power management exit.
1
RWC/S
0b
Cleared by the BIOS by writing a "1" in a warm reset (Reset# asserted while
PWROK is asserted) exit sequence.
0 = Channel 1 not guaranteed to be in Self-Refresh.
1 = Channel 1 in Self-Refresh.
Channel 0 in Self-Refresh (C0SR):
Set by power management hardware after Channel 0 is placed in self refresh as
a result of a Power State or a Reset Warn sequence.
Cleared by Power management hardware before starting Channel 0 self refresh
exit sequence initiated by a power management exit.
0
RWC/S
0b
Cleared by the BIOS by writing a "1" in a warm reset (Reset# asserted while
PWROK is asserted) exit sequence.
0 = Channel 0 not guaranteed to be in Self-Refresh.
1 = Channel 0 in Self-Refresh.
Datasheet
139
DRAM Controller Registers (D0:F0)
5.3
EPBAR
Table 11.
EPBAR Address Map
Address
Offset
Register
Symbol
Default
Access
Value
Register Name
44–47h
50–53h
EPESD
EP Element Self Description
EP Link Entry 1 Description
00000201h
01000000h
RO, RWO
RO, RWO
EPLE1D
00000000000
00000h
58–5Fh
60–63h
68–6Fh
60–63h
68–6Fh
EPLE1A
EPLE2D
EPLE2A
EPLE3D
EPLE3A
EP Link Entry 1 Address
EP Link Entry 2 Description
EP Link Entry 2 Address
EP Link Entry 3 Description
EP Link Entry 3 Address
RO, RWO
RO, RWO
RO
02000002h
00000000000
08000h
03000002h
RO, RWO
RO
00000000000
08000h
5.3.1
EPESD—EP Element Self Description
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 44–47h
Default Value:
Access:
Size:
00000201h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Default
Value
Bit
Access
Description
Port Number (PN): This field specifies the port number associated with this
element with respect to the component that contains this element. Value of 00h
indicates to configuration software that this is the default egress port.
31:24
RO
RWO
RO
00h
Component ID (CID): Identifies the physical component that contains this
Root Complex Element.
23:16
15:8
00h
03h
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
Number of Link Entries (NLE): Indicates the number of link entries following
the Element Self Description. This field reports 3 (one each for PEG0,
PEG1, and DMI).
7:4
3:0
RO
RO
0h
1h
Reserved
Element Type (ET): Indicates the type of the Root Complex Element. Value of
1h represents a port to system memory.
140
Datasheet
DRAM Controller Registers (D0:F0)
5.3.2
EPLE1D—EP Link Entry 1 Description
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 50–53h
Default Value:
Access:
Size:
01000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
Target Port Number (TPN): Specifies the port number associated with the
element targeted by this link entry (DMI). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
31:24
RO
01h
Target Component ID (TCID): Identifies the physical or logical component
that is targeted by this link entry.
23:16
RWO
00h
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
15:2
1
RO
RO
0000h Reserved
Link Type (LTYP): Indicates that the link points to memory-mapped space (for
0b
RCRB). The link address specifies the 64-bit base address of the target RCRB.
Link Valid (LV):
0
RWO
0b
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
5.3.3
EPLE1A—EP Link Entry 1 Address
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 58–5Fh
Default Value:
Access:
Size:
0000000000000000h
RO, RWO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
63:36
35:12
11:0
RO
RWO
RO
0000000h Reserved
Link Address (LA): Memory mapped base address of the RCRB that is the
000000h
000h
target element (DMI) for this link entry.
Reserved
Datasheet
141
DRAM Controller Registers (D0:F0)
5.3.4
EPLE2D—EP Link Entry 2 Description
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 60–63h
Default Value:
Access:
Size:
02000002h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
Target Port Number (TPN): Specifies the port number associated with the
element targeted by this link entry (PEG0). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
31:24
RO
02h
Target Component ID (TCID): Identifies the physical or logical component
that is targeted by this link entry. A value of 0 is reserved. Component IDs start
at 1. This value is a mirror of the value in the Component ID field of all elements
in this component.
23:16
RWO
00h
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
15:2
1
RO
RO
0000h Reserved
Link Type (LTYP): Indicates that the link points to configuration space of the
integrated device which controls the root port for PEG0.
1b
0b
The link address specifies the configuration address (segment, bus, device,
function) of the target root port.
Link Valid (LV):
0
RWO
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
5.3.5
EPLE2A—EP Link Entry 2 Address
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 68–6Fh
Default Value:
Access:
Size:
0000000000008000h
RO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
0000000
00h
63:28
27:20
19:15
RO
RO
RO
Reserved
00h
Bus Number (BUSN):
Device Number (DEVN): Target for this link is PCI Express port PEG0
(Device1).
00001b
14:12
11:0
RO
RO
000b
000h
Function Number (FUNN):
Reserved
142
Datasheet
DRAM Controller Registers (D0:F0)
5.3.6
EPLE3D—EP Link Entry 3 Description
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 70–73h
Default Value:
Access:
Size:
03000002h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
Target Port Number (TPN): Specifies the port number associated with the
element targeted by this link entry (PEG1). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
31:24
RO
03h
Target Component ID (TCID): Identifies the physical or logical component
that is targeted by this link entry. A value of 0 is reserved. Component IDs start
at 1. This value is a mirror of the value in the Component ID field of all elements
in this component.
23:16
RWO
00h
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
15:2
1
RO
RO
0000h Reserved
Link Type (LTYP): Indicates that the link points to configuration space of the
integrated device which controls the root port for PEG1.
1b
0b
The link address specifies the configuration address (segment, bus, device,
function) of the target root port.
Link Valid (LV):
0
RWO
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Datasheet
143
DRAM Controller Registers (D0:F0)
5.3.7
EPLE3A—EP Link Entry 3 Address
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset: 78–7Fh
Default Value:
Access:
Size:
0000000000008000h
RO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
0000000
00h
63:28
27:20
19:15
RO
RO
RO
Reserved
00h
Bus Number (BUSN):
Device Number (DEVN): Target for this link is PCI Express port PEG1
(Device6).
00001b
14:12
11:0
RO
RO
000b
000h
Function Number (FUNN):
Reserved
§ §
144
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6
Host-Primary PCI Express*
Bridge Registers (D1:F0)
Device 1 contains the controls associated with the PCI Express root port that is the
intended attach point for external graphics. In addition, it also functions as the virtual
PCI-to-PCI bridge. The table below provides an address map of the D1:F0 registers
listed by address offset in ascending order. This chapter provides a detailed bit
description of the registers.
Warning:
When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits:
Reserved and Preserved:
• Reserved for future RW implementations; software must preserve value read for
writes to bits.
• Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Note:
Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first disable the link, then program the registers, and then re-
enable the link (which will cause a full-retrain with the new settings).
Table 12.
Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 1 of 3)
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
0–1h
2–3h
4–5h
6–7h
8h
VID1
DID1
Vendor Identification
8086h
29E1h
0000h
0010h
00h
RO
RO
Device Identification
PCI Command
PCICMD1
PCISTS1
RID1
RO, RW
RO, RWC
RO
PCI Status
Revision Identification
Class Code
9–Bh
Ch
CC1
060400h
00h
RO
CL1
Cache Line Size
RW
Eh
HDR1
Header Type
01h
RO
18h
PBUSN1
SBUSN1
SUBUSN1
IOBASE1
IOLIMIT1
SSTS1
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
I/O Base Address
I/O Limit Address
Secondary Status
Memory Base Address
00h
RO
19h
00h
RW
1Ah
00h
RW
1Ch
F0h
RO, RW
RW, RO
RO, RWC
RW, RO
1Dh
00h
1E–1Fh
20–21h
0000h
FFF0h
MBASE1
Datasheet
145
Host-Primary PCI Express* Bridge Registers (D1:F0)
Table 12.
Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 2 of 3)
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
22–23h
24–25h
26–27h
28–2Bh
2C–2Fh
34h
MLIMIT1
PMBASE1
PMLIMIT1
Memory Limit Address
0000h
FFF1h
0001h
RW, RO
RW, RO
RO, RW
RW
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
PMBASEU1 Prefetchable Memory Base Address Upper 00000000h
PMLIMITU1 Prefetchable Memory Limit Address Upper 00000000h
RW
CAPPTR1
Capabilities Pointer
88h
00h
RO
3Ch
INTRLINE1 Interrupt Line
RW
3Dh
INTRPIN1
BCTRL1
Interrupt Pin
01h
RO
3E–3Fh
80–83h
Bridge Control
0000h
C8039001h
RO, RW
RO
PM_CAPID1 Power Management Capabilities
PM_CS1 Power Management Control/Status
RO, RW,
RW/P
84–87h
00000008h
88–8Bh
8C–8Fh
90–91h
92–93h
94–97h
98–99h
A0–A1h
A2–A3h
A4–A7h
A8–A9h
AA–ABh
SS_CAPID Subsystem ID and Vendor ID Capabilities
SS Subsystem ID and Subsystem Vendor ID
MSI_CAPID Message Signaled Interrupts Capability ID
0000800Dh
00008086h
A005h
RO
RWO
RO
MC
MA
Message Control
0000h
RW, RO
RO, RW
RW
Message Address
Message Data
00000000h
0000h
MD
PE_CAPL
PE_CAP
DCAP
DCTL
DSTS
PCI Express Capability List
PCI Express Capabilities
Device Capabilities
Device Control
0010h
RO
0142h
RO, RWO
RO
00008000h
0000h
RW, RO
RO, RWC
Device Status
0000h
020214D02
h
AC–AFh
B0–B1h
LCAP
LCTL
Link Capabilities
Link Control
RO, RWO
RO, RW,
RW/SC
0000h
B2–B3h
B4–B7h
B8–B9h
BA–BBh
BC–BDh
C0–C3h
EC–EFh
LSTS
SLOTCAP
SLOTCTL
SLOTSTS
RCTL
Link Status
1000h
00040000h
0000h
RWC, RO
RWO, RO
RO, RW
Slot Capabilities
Slot Control
Slot Status
0000h
RO, RWC
RO, RW
Root Control
0000h
RSTS
Root Status
00000000h
00000000h
RO, RWC
RO, RW
PELC
PCI Express Legacy Control
Virtual Channel Enhanced Capability
Header
100–103h
VCECH
14010002h
RO
104–107h
108–10Bh
PVCCAP1
PVCCAP2
Port VC Capability Register 1
Port VC Capability Register 2
00000000h
00000000h
RO
RO
146
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Table 12.
Host-PCI Express Bridge Register Address Map (D1:F0) (Sheet 3 of 3)
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
10C–
10Dh
PVCCTL
Port VC Control
0000h
RO, RW
110–113h
114–117h
11A–11Bh
140–143h
144–147h
150–153h
VC0RCAP
VC0RCTL
VC0RSTS
RCLDECH
ESD
VC0 Resource Capability
VC0 Resource Control
00000001h
800000FFh
0002h
RO
RO, RW
RO
VC0 Resource Status
Root Complex Link Declaration Enhanced
Element Self Description
Link Entry 1 Description
00010005h
02000100h
00000000h
RO
RO, RWO
RO, RWO
LE1D
000000000
0000000h
158–15Fh
218–21Fh
LE1A
Link Entry 1 Address
RO, RWO
RO
000000000
0000FFFh
PESSTS
PCI Express Sequence Status
6.1
VID1—Vendor Identification
B/D/F/Type:
0/1/0/PCI
Address Offset: 0–1h
Default Value:
Access:
Size:
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identify any PCI
device.
Default
Value
Bit
Access
RO
Description
15:0
8086h Vendor Identification (VID1): PCI standard identification for Intel.
Datasheet
147
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.2
DID1—Device Identification
B/D/F/Type:
0/1/0/PCI
Address Offset: 2–3h
Default Value:
Access:
Size:
29E1h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Default
Value
Bit
Access
Description
Device Identification Number (DID1(UB)): Identifier assigned to the MCH
device 1 (virtual PCI-to-PCI bridge, PCI Express port).
15:8
7:4
RO
RO
RO
29h
Device Identification Number (DID1(HW)): Identifier assigned to the MCH
device 1 (virtual PCI-to-PCI bridge, PCI Express port).
Eh
1h
Device Identification Number (DID1(LB)): Identifier assigned to the MCH
device 1 (virtual PCI-to-PCI bridge, PCI Express port).
3:0
6.3
PCICMD1—PCI Command
B/D/F/Type:
0/1/0/PCI
Address Offset: 4–5h
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:11
RO
00h
Reserved
INTA Assertion Disable (INTAAD):
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any INTA
emulation interrupts already asserted must be de-asserted when this bit is
set.
10
9
RW
0b
0b
Only affects interrupts generated by the device (PCI INTA from a PME event)
controlled by this command register. It does not affect upstream MSIs, upstream
PCI INTA-INTD assert and de-assert messages.
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented. Hardwired
to 0.
RO
148
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
SERR# Message Enable (SERRE1): Controls Device 1 SERR# messaging. The
MCH communicates the SERR# condition by sending an SERR message to the
ICH. This bit, when set, enables reporting of non-fatal and fatal errors detected
by the device to the Root Complex. Note that errors are reported if enabled
either through this bit or through the PCI-Express specific bits in the Device
Control Register.
8
RW
0b
0 = The SERR message is generated by the MCH for Device 1 only under
conditions enabled individually through the Device Control Register.
1 = The MCH is enabled to generate SERR messages which will be sent to the
ICH for specific Device 1 error conditions generated/detected on the primary
side of the virtual PCI to PCI bridge (not those received by the secondary
side). The status of SERRs generated is reported in the PCISTS1 register.
7
6
RO
RW
RO
0b
0b
0b
Reserved
Parity Error Response Enable (PERRE): Controls whether or not the Master
Data Parity Error bit in the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5:3
Reserved
Bus Master Enable (BME): Controls the ability of the PCI Express port to
forward Memory and IO Read/Write Requests in the upstream direction.
0 = This device is prevented from making memory or IO requests to its primary
bus. Note that according to PCI Specification, as MSI interrupt messages are
in-band memory writes, disabling the bus master enable bit prevents this
device from generating MSI interrupt messages or passing them from its
secondary bus to its primary bus. Upstream memory writes/reads, IO
writes/reads, peer writes/reads, and MSIs will all be treated as illegal cycles.
Writes are forwarded to memory address C0000h with byte enables de-
asserted. Reads will be forwarded to memory address C0000h and will
return Unsupported Request status (or Master abort) in its completion
packet.
2
RW
0b
1 = This device is allowed to issue requests to its primary bus. Completions for
previously issued memory read requests on the primary bus will be issued
when the data is available.
This bit does not affect forwarding of Completions from the primary interface to
the secondary interface.
Memory Access Enable (MAE):
0 = All of device 1's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges defined in the
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
1
0
RW
RW
0b
0b
I/O Access Enable (IOAE):
0 = All of device 1's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1
registers.
Datasheet
149
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.4
PCISTS1—PCI Status
B/D/F/Type:
0/1/0/PCI
Address Offset: 6–7h
Default Value:
Access:
Size:
0010h
RO, RWC
16 bits
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the MCH.
Default
Value
Bit
Access
Description
Detected Parity Error (DPE): Not Applicable or Implemented. Hardwired to 0.
Parity (generating poisoned Transaction Layer Packets) is not supported on the
primary side of this device.
15
RO
0b
Signaled System Error (SSE): This bit is set when this Device sends an SERR
due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR
Enable bit in the Command register is 1. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not affect this field.
14
RWC
0b
Received Master Abort Status (RMAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a master abort does not exist on primary side of
this device.
13
12
RO
RO
RO
RO
0b
0b
Received Target Abort Status (RTAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a target abort does not exist on primary side of
this device.
Signaled Target Abort Status (STAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a target abort does not exist on primary side of
this device.
11
0b
DEVSELB Timing (DEVT): This device is not the subtractively decoded device
on bus 0. This bit field is therefore hardwired to 00 to indicate that the device
uses the fastest possible decode.
10:9
00b
Master Data Parity Error (PMDPE): Because the primary side of the PCI
Express's virtual peer-to-peer bridge is integrated with the MCH functionality,
there is no scenario where this bit will get set. Because hardware will never set
this bit, it is impossible for software to have an opportunity to clear this bit or
otherwise test that it is implemented. The PCI specification defines it as a R/WC,
but for our implementation an RO definition behaves the same way and will meet
all Microsoft testing requirements.
8
RO
0b
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
7
6
RO
RO
0b
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60MHz capability (CAP66): Not Applicable or Implemented. Hardwired to
0.
5
4
RO
RO
0b
1b
Capabilities List (CAPL): Indicates that a capabilities list is present. Hardwired
to 1.
INTA Status (INTAS): Indicates that an interrupt message is pending
internally to the device. Only PME sources feed into this status bit (not PCI INTA-
INTD assert and de-assert messages). The INTA Assertion Disable bit,
PCICMD1[10], has no effect on this bit.
3
RO
RO
0b
2:0
000b
Reserved
150
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.5
RID1—Revision Identification
B/D/F/Type:
0/1/0/PCI
Address Offset: 8h
Default Value:
Access:
Size:
see table below
RO
8 bits
This register contains the revision number of the MCH device 1. These bits are read
only and writes to this register have no effect.
Default
Value
Bit
Access
Description
Revision Identification Number (RID1): This is an 8-bit value that
indicates the revision identification number for the MCH Device 0. Refer to the
Intel® X38 PCI Express Chipset Specification Update for the value of this
register. Refer to the Intel® X38 Express Chipset Specification Update for the
value of this register.
see
description
7:0
RO
6.6
CC1—Class Code
B/D/F/Type:
0/1/0/PCI
Address Offset: 9–Bh
Default Value:
Access:
Size:
060400h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
Default
Value
Bit
Access
Description
Base Class Code (BCC): Indicates the base class code for this device. This
code has the value 06h, indicating a Bridge device.
23:16
15:8
RO
RO
06h
Sub-Class Code (SUBCC): Indicates the sub-class code for this device. The
code is 04h indicating a PCI to PCI Bridge.
04h
00h
Programming Interface (PI): Indicates the programming interface of this
device. This value does not specify a particular register set layout and provides
no practical use for this device.
7:0
RO
Datasheet
151
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.7
CL1—Cache Line Size
B/D/F/Type:
0/1/0/PCI
Address Offset: Ch
Default Value:
Access:
Size:
00h
RW
8 bits
Default
Value
Bit
Access
Description
Cache Line Size (Scratch pad): Implemented by PCI Express devices as a
read-write field for legacy compatibility purposes but has no impact on any PCI
Express device functionality.
7:0
RW
00h
6.8
HDR1—Header Type
B/D/F/Type:
0/1/0/PCI
Address Offset: Eh
Default Value:
Access:
Size:
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Default
Value
Bit
Access
Description
Header Type Register (HDR): Returns 01h to indicate that this is a single
function device with bridge header layout.
7:0
RO
01h
6.9
PBUSN1—Primary Bus Number
B/D/F/Type:
0/1/0/PCI
Address Offset: 18h
Default Value:
Access:
Size:
00h
RO
8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus 0.
Default
Value
Bit
Access
Description
Primary Bus Number (BUSN): Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device
1 is an internal device and its primary bus is always 0, these bits are read only
and are hardwired to 0.
7:0
RO
00h
152
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
0/1/0/PCI
Address Offset: 19h
Default Value:
Access:
Size:
00h
RW
8 bits
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge. This number is programmed by the PCI configuration software to allow mapping
of configuration cycles to PCI Express.
Default
Value
Bit
Access
Description
Secondary Bus Number (BUSN): This field is programmed by configuration
software with the bus number assigned to PCI Express.
7:0
RW
00h
6.11
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
0/1/0/PCI
Address Offset: 1Ah
Default Value:
Access:
Size:
00h
RW
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express.
Default
Value
Bit
Access
Description
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device 1 bridge. When only a single PCI device resides on the PCI
Express segment, this register will contain the same value as the SBUSN1
register.
7:0
RW
00h
Datasheet
153
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.12
IOBASE1—I/O Base Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 1Ch
Default Value:
Access:
Size:
F0h
RO, RW
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
Default
Value
Bit
Access
Description
I/O Address Base (IOBASE): Corresponds to A[15:12] of the I/O addresses
passed by bridge 1 to PCI Express.
7:4
3:0
RW
RO
Fh
0h
Reserved
6.13
IOLIMIT1—I/O Limit Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 1Dh
Default Value:
Access:
Size:
00h
RW, RO
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode, address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
Default
Value
Bit
Access
Description
I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O address
limit of device #1. Devices between this upper limit and IOBASE1 will be passed
to the PCI Express hierarchy associated with this device.
7:4
3:0
RW
RO
0h
0h
Reserved
154
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.14
SSTS1—Secondary Status
B/D/F/Type:
0/1/0/PCI
Address Offset: 1E–1Fh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.
Default
Value
Bit
Access
Description
Detected Parity Error (DPE): This bit is set by the Secondary Side for a Type 1
Configuration Space header device whenever it receives a Poisoned Transaction
Layer Packet, regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
15
RWC
RWC
RWC
0b
Received System Error (RSE): This bit is set when the Secondary Side for a
Type 1 configuration space header device receives an ERR_FATAL or
ERR_NONFATAL.
14
13
0b
0b
Received Master Abort (RMA): This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Unsupported Request
Completion Status.
Received Target Abort (RTA): This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Completer Abort Completion
Status.
12
RWC
0b
Signaled Target Abort (STA): Not Applicable or Implemented. Hardwired to 0.
The MCH does not generate Target Aborts (the MCH will never complete a
request using the Completer Abort Completion status).
11
RO
RO
0b
10:9
00b
DEVSELB Timing (DEVT): Not Applicable or Implemented. Hardwired to 0.
Master Data Parity Error (SMDPE): When set indicates that the MCH received
across the link (upstream) a Read Data Completion Poisoned Transaction Layer
Packet (EP=1). This bit can only be set when the Parity Error Enable bit in the
Bridge Control register is set.
8
RWC
0b
7
6
RO
RO
0b
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66): Not Applicable or Implemented. Hardwired to
0.
5
RO
RO
0b
4:0
00h
Reserved
Datasheet
155
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.15
MBASE1—Memory Base Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 20–21h
Default Value:
Access:
Size:
FFF0h
RW, RO
16 bits
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode, address bits A[19:0] are assumed to be
0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
Default
Value
Bit
Access
Description
Memory Address Base (MBASE): This field corresponds to A[31:20] of the
lower limit of the memory range that will be passed to PCI Express.
15:4
3:0
RW
RO
FFFh
0h
Reserved
156
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.16
MLIMIT1—Memory Limit Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 22–23h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB
aligned memory block.
Note:
Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express address ranges (typically where control/status memory-
mapped I/O data structures of the controller will reside) and PMBASE and PMLIMIT are
used to map prefetchable address ranges (typically device local memory). This
segregation allows application of USWC space attribute to be performed in a true plug-
and-play manner to the prefetchable address range for improved processor- PCI
Express memory access performance.
Note:
Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges
(i.e., prevent overlap with each other and/or with the ranges covered with the main
memory). There is no provision in the MCH hardware to enforce prevention of overlap
and operations of the system in the case of overlap are not ensured.
Default
Value
Bit
Access
Description
Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the
upper limit of the address range passed to PCI Express.
15:4
3:0
RW
RO
000h
0h
Reserved
Datasheet
157
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.17
PMBASE1—Prefetchable Memory Base Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 24–25h
Default Value:
Access:
Size:
FFF1h
RW, RO
16 bits
This register in conjunction with the corresponding Upper Base Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1MB boundary.
Default
Value
Bit
Access
Description
Prefetchable Memory Base Address (MBASE): Corresponds to A[31:20] of
the lower limit of the memory range that will be passed to PCI Express.
15:4
RW
RO
FFFh
64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region base address are contained in the Prefetchable Memory base
Upper Address register at 28h.
3:0
1h
158
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.18
PMLIMIT1—Prefetchable Memory Limit Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 26–27h
Default Value:
Access:
Size:
0001h
RO, RW
16 bits
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Default
Value
Bit
Access
Description
Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to
A[31:20] of the upper limit of the address range passed to PCI Express.
15:4
RW
RO
000h
64-bit Address Support: This field indicates that the upper 32 bits of the
prefetchable memory region limit address are contained in the Prefetchable
Memory Base Limit Address register at 2Ch
3:0
1h
Datasheet
159
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.19
PMBASEU1—Prefetchable Memory Base Address
Upper
B/D/F/Type:
0/1/0/PCI
Address Offset: 28–2Bh
Default Value:
Access:
Size:
00000000h
RW
32 bits
The functionality associated with this register is present in the PCI Express design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1MB boundary.
Default
Value
Bit
Access
Description
Prefetchable Memory Base Address (MBASEU): This field corresponds to
A[63:32] of the lower limit of the prefetchable memory range that will be passed
to PCI Express.
0000000
0h
31:0
RW
160
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.20
PMLIMITU1—Prefetchable Memory Limit Address
Upper
B/D/F/Type:
0/1/0/PCI
Address Offset: 2C–2Fh
Default Value:
Access:
Size:
00000000h
RW
32 bits
The functionality associated with this register is present in the PCI Express design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the
ones that can be designated as a USWC (i.e. prefetchable) from the processor
perspective.
Default
Value
Bit
Access
Description
Prefetchable Memory Address Limit (MLIMITU): This field corresponds to
A[63:32] of the upper limit of the prefetchable Memory range that will be passed
to PCI Express.
0000000
0h
31:0
RW
6.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
0/1/0/PCI
Address Offset: 34h
Default Value:
Access:
Size:
88h
RO
8 bits
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Default
Value
Bit
Access
Description
First Capability (CAPPTR1): The first capability in the list is the Subsystem ID
and Subsystem Vendor ID Capability.
7:0
RO
88h
Datasheet
161
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.22
INTRLINE1—Interrupt Line
B/D/F/Type:
0/1/0/PCI
Address Offset: 3Ch
Default Value:
Access:
Size:
00h
RW
8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Default
Value
Bit
Access
Description
Interrupt Connection (INTCON): This field is used to communicate interrupt
line routing information.
7:0
RW
00h
6.23
INTRPIN1—Interrupt Pin
B/D/F/Type:
0/1/0/PCI
Address Offset: 3Dh
Default Value:
Access:
Size:
01h
RO
8 bits
This register specifies which interrupt pin this device uses.
Default
Value
Bit
Access
Description
Interrupt Pin (INTPIN): As a single function device, the PCI Express device
specifies INTA as its interrupt pin. 01h=INTA.
7:0
RO
01h
6.24
BCTRL1—Bridge Control
B/D/F/Type:
0/1/0/PCI
Address Offset: 3E–3Fh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface as well as
some bits that affect the overall behavior of the "virtual" Host-PCI Express bridge
embedded within MCH.
Default
Value
Bit
Access
Description
15:12
11
RO
RO
0h
Reserved
Discard Timer SERR# Enable (DTSERRE): Not Applicable or Implemented.
Hardwired to 0.
0b
0b
Discard Timer Status (DTSTS): Not Applicable or Implemented. Hardwired to
0.
10
RO
162
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
Secondary Discard Timer (SDT): Not Applicable or Implemented. Hardwired
to 0.
9
8
7
RO
RO
RO
0b
Primary Discard Timer (PDT): Not Applicable or Implemented. Hardwired to
0.
0b
0b
Fast Back-to-Back Enable (FB2BEN): Not Applicable or Implemented.
Hardwired to 0.
Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the
corresponding PCI Express Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
6
5
RW
RO
0b
0b
Master Abort Mode (MAMODE): Does not apply to PCI Express. Hardwired to
0.
VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI bridge to provide 16-
bit decoding of VGA I/O address precluding the decoding of alias addresses
every 1 KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also
set to 1, enabling VGA I/O decoding and forwarding by the bridge.
4
3
RW
RW
0b
0b
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
VGA Enable (VGAEN): Controls the routing of processor initiated transactions
targeting VGA compatible I/O and memory address ranges. See the VGAEN/
MDAP table in device 0, offset 97h[0].
ISA Enable (ISAEN): Needed to exclude legacy resource decode to route ISA
resources to legacy decode path. Modifies the response by the MCH to an I/O
access issued by the processor that target ISA I/O addresses. This applies only
to I/O addresses that are enabled by the IOBASE and IOLIMIT registers.
2
RW
0b
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express.
1 = MCH will not forward to PCI Express any I/O transactions addressing the last
768 bytes in each 1KB block even if the addresses are within the range
defined by the IOBASE and IOLIMIT registers.
SERR Enable (SERREN):
0 = No forwarding of error messages from secondary side to primary side that
could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
1
0
RW
RW
0b
0b
Parity Error Response Enable (PEREN): Controls whether or not the Master
Data Parity Error bit in the Secondary Status register is set when the MCH
receives across the link (upstream) a Read Data Completion Poisoned
Transaction Layer Packet.
0 = Master Data Parity Error bit in Secondary Status register can NOT be set.
1 = Master Data Parity Error bit in Secondary Status register CAN be set.
Datasheet
163
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.25
PM_CAPID1—Power Management Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: 80–83h
Default Value:
Access:
Size:
C8039001h
RO
32 bits
Default
Value
Bit
Access
Description
PME Support (PMES): This field indicates the power states in which this device
may indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This
device is not required to do anything to support D3hot & D3cold, it simply must
report that those states are supported. Refer to the PCI Power Management 1.1
specification for encoding explanation and other power management details.
31:27
RO
19h
D2 Power State Support (D2PSS): Hardwired to 0 to indicate that the D2
power management state is NOT supported.
26
25
RO
RO
RO
0b
0b
D1 Power State Support (D1PSS): Hardwired to 0 to indicate that the D1
power management state is NOT supported.
Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are no
3.3Vaux auxiliary current requirements.
24:22
000b
Device Specific Initialization (DSI): Hardwired to 0 to indicate that special
initialization of this device is NOT required before generic class device driver is to
use it.
21
RO
0b
20
19
RO
RO
0b
0b
Auxiliary Power Source (APS): Hardwired to 0.
PME Clock (PMECLK): Hardwired to 0 to indicate this device does NOT support
PMEB generation.
PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this function
complies with revision 1.2 of the PCI Power Management Interface Specification.
18:16
15:8
7:0
RO
RO
RO
011b
90h
Pointer to Next Capability (PNC): This contains a pointer to the next item in
the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI) capability at 90h.
Capability ID (CID): Value of 01h identifies this linked list item (capability
structure) as being for PCI Power Management registers.
01h
164
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.26
PM_CS1—Power Management Control/Status
B/D/F/Type:
0/1/0/PCI
Address Offset: 84–87h
Default Value:
Access:
Size:
00000008h
RO, RW, RW/P
32 bits
Default
Value
Bit
Access
Description
31:16
15
RO
RO
0000h Reserved
PME Status (PMESTS): Indicates that this device does not support PMEB
0b
00b
0h
generation from D3cold.
Data Scale (DSCALE): Indicates that this device does not support the power
14:13
12:9
RO
RO
management data register.
Data Select (DSEL): Indicates that this device does not support the power
management data register.
PME Enable (PMEE): Indicates that this device does not generate PMEB
assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
8
RW/P
RO
0b
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:2
0000b Reserved
Power State (PS): Indicates the current power state of this device and can be
used to set the device into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
00 = D0
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The device
must return to the D0 state in order to be fully-functional.
1:0
RW
00b
When the Power State is other than D0, the bridge will Master Abort (i.e. not
claim) any downstream cycles (with exception of type 0 configuration cycles).
Consequently, these unclaimed cycles will go down DMI and come back up as
Unsupported Requests, which the MCH logs as Master Aborts in Device 0
PCISTS[13]
There is no additional hardware functionality required to support these Power
States.
Datasheet
165
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.27
SS_CAPID—Subsystem ID and Vendor ID
Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: 88–8Bh
Default Value:
Access:
Size:
0000800Dh
RO
32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides.
Because this device is an integrated part of the system and not an add-in device, it is
anticipated that this capability will never be used. However, it is necessary because
Microsoft will test for its presence.
Default
Value
Bit
Access
Description
31:16
15:8
RO
RO
0000h Reserved
Pointer to Next Capability (PNC): This contains a pointer to the next item in
80h
0Dh
the capabilities list which is the PCI Power Management capability.
Capability ID (CID): Value of 0Dh identifies this linked list item (capability
7:0
RO
structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
6.28
SS—Subsystem ID and Subsystem Vendor ID
B/D/F/Type:
0/1/0/PCI
Address Offset: 8C–8Fh
Default Value:
Access:
Size:
00008086h
RWO
32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These
values must be preserved through power management transitions and a hardware
reset.
Default
Value
Bit
Access
Description
Subsystem ID (SSID): Identifies the particular subsystem and is assigned by
the vendor.
31:16
RWO
RWO
0000h
Subsystem Vendor ID (SSVID): Identifies the manufacturer of the subsystem
8086h and is the same as the vendor ID which is assigned by the PCI Special Interest
Group.
15:0
166
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.29
MSI_CAPID—Message Signaled Interrupts
Capability ID
B/D/F/Type:
0/1/0/PCI
Address Offset: 90–91h
Default Value:
Access:
Size:
A005h
RO
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This contains a pointer to the next item in
the capabilities list which is the PCI Express capability.
15:8
7:0
RO
RO
A0h
Capability ID (CID): Value of 05h identifies this linked list item (capability
structure) as being for MSI registers.
05h
6.30
MC—Message Control
B/D/F/Type:
0/1/0/PCI
Address Offset: 92–93h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
ensured to be serviced. If all of them must be serviced, the device must not generate
the same message again until the driver services the earlier one.
Default
Value
Bit
Access
Description
15:8
RO
RO
00h
Reserved
64-bit Address Capable (64AC): Hardwired to 0 to indicate that the function
does not implement the upper 32 bits of the Message Address register and is
incapable of generating a 64-bit memory address.
7
0b
Multiple Message Enable (MME): System software programs this field to
indicate the actual number of messages allocated to this device. This number
will be equal to or less than the number actually requested.
6:4
RW
RO
RW
000b
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC): System software reads this field to
determine the number of messages being requested by this device. The value of
000b equates to 1 message requested.
3:1
0
000b
0b
000 = 1 message requested
All other encodings are reserved.
MSI Enable (MSIEN): Controls the ability of this device to generate MSIs.
0 = 0MSI will not be generated.
1 = MSI will be generated when we receive PME messages. INTA will not be
generated and INTA Status (PCISTS1[3]) will not be set.
Datasheet
167
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.31
MA—Message Address
B/D/F/Type:
0/1/0/PCI
Address Offset: 94–97h
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
Default
Value
Bit
Access
Description
Message Address (MA): Used by system software to assign an MSI address to
the device. The device handles an MSI by writing the padded contents of the MD
register to this address.
0000000
0h
31:2
1:0
RW
RO
Force DWord Align (FDWA): Hardwired to 0 so that addresses assigned by
system software are always aligned on a dword address boundary.
00b
6.32
MD—Message Data
B/D/F/Type:
0/1/0/PCI
Address Offset: 98–99h
Default Value:
Access:
Size:
0000h
RW
16 bits
Default
Value
Bit
Access
Description
Message Data (MD): Base message data pattern assigned by system software
and used to handle an MSI from the device.
15:0
RW
0000h
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16-bits are always
set to 0. The lower 16-bits are supplied by this register.
6.33
PE_CAPL—PCI Express* Capability List
B/D/F/Type:
0/1/0/PCI
Address Offset: A0–A1h
Default Value:
Access:
Size:
0010h
RO
16 bits
This register enumerates the PCI Express capability structure.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This value terminates the capabilities list.
The Virtual Channel capability and any other PCI Express specific capabilities
that are reported via this mechanism are in a separate capabilities list located
entirely within PCI Express Extended Configuration Space.
15:8
7:0
RO
RO
00h
Capability ID (CID): Identifies this linked list item (capability structure) as
being for PCI Express registers.
10h
168
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.34
PE_CAP—PCI Express* Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: A2–A3h
Default Value:
Access:
Size:
0142h
RO, RWO
16 bits
This register indicates PCI Express device capabilities.
Default
Value
Bit
Access
Description
15:14
13:9
RO
RO
00b
Reserved
Interrupt Message Number (IMN): Not Applicable or Implemented.
Hardwired to 0.
00h
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is connected to an integrated
component or is disabled.
8
RWO
1b
1 = The PCI Express Link associated with this port is connected to a slot.
Device/Port Type (DPT): Hardwired to 4h to indicate root port of PCI Express
Root Complex.
7:4
3:0
RO
RO
4h
2h
PCI Express Capability Version (PCIECV): Hardwired to 2h to indicate
compliance to the PCI Express Capabilities Register Expansion ECN.
6.35
DCAP—Device Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: A4–A7h
Default Value:
Access:
Size:
00008000h
RO
32 bits
This register indicates PCI Express device capabilities.
Default
Value
Bit
Access
Description
31:16
RO
RO
0000h Reserved
Role Based Error Reporting (RBER): Role Based Error Reporting (RBER):
Indicates that this device implements the functionality defined in the Error
Reporting ECN as required by the PCI Express 1.1 spec.
15
1b
14:6
5
RO
RO
000h
0b
Reserved
Extended Tag Field Supported (ETFS): Hardwired to indicate support for 5-
bit Tags as a Requestor.
Phantom Functions Supported (PFS): Not Applicable or Implemented.
Hardwired to 0.
4:3
2:0
RO
RO
00b
Max Payload Size (MPS): Hardwired to indicate 128B max supported payload
for Transaction Layer Packets (TLP).
000b
Datasheet
169
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.36
DCTL—Device Control
B/D/F/Type:
0/1/0/PCI
Address Offset: A8–A9h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Default
Value
Bit
Access
Description
15:8
RO
0h
Reserved
Max Payload Size (MPS):
000 = 128B max supported payload for Transaction Layer Packets (TLP). As a
receiver, the Device must handle TLPs as large as the set value; as
transmitter, the Device must not generate TLPs exceeding the set value.
7:5
RW
000b
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to support compliance
testing.
4
3
RO
0b
0b
Reserved.
Unsupported Request Reporting Enable (URRE): When set, this bit allows
signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the Root Control register
when detecting an unmasked Unsupported Request (UR). An ERR_CORR is
signaled when an unmasked Advisory Non-Fatal UR is received. An ERR_FATAL
or ERR_NONFATAL is sent to the Root Control register when an uncorrectable
non-Advisory UR is received with the severity bit set in the Uncorrectable Error
Severity register.
RW
Fatal Error Reporting Enable (FERE): When set, this bit enables signaling of
ERR_FATAL to the Root Control register due to internally detected errors or error
messages received across the link. Other bits also control the full scope of
related error reporting.
2
1
0
RW
RW
RW
0b
0b
0b
Non-Fatal Error Reporting Enable (NERE): When set, this bit enables
signaling of ERR_NONFATAL to the Rool Control register due to internally
detected errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
Correctable Error Reporting Enable (CERE): When set, this bit enables
signaling of ERR_CORR to the Root Control register due to internally detected
errors or error messages received across the link. Other bits also control the full
scope of related error reporting.
170
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.37
DSTS—Device Status
B/D/F/Type:
0/1/0/PCI
Address Offset: AA–ABh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
Default
Value
Bit
Access
Description
15:6
RO
RO
RO
000h
Reserved
Transactions Pending (TP):
0 = All pending transactions (including completions for any outstanding non-
posted requests on any used virtual channel) have been completed.
1 = Indicates that the device has transaction(s) pending (including completions
for any outstanding non-posted requests for all used Traffic Classes).
5
4
0b
0b
Reserved
Unsupported Request Detected (URD): When set, this bit indicates that the
Device received an Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
Register.
3
RWC
0b
Additionally, the Non-Fatal Error Detected bit or the Fatal Error Detected bit is
set according to the setting of the Unsupported Request Error Severity bit. In
production systems setting the Fatal Error Detected bit is not an option as
support for AER will not be reported.
Fatal Error Detected (FED): When set, this bit indicates that fatal error(s)
were detected. Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register. When Advanced Error
Handling is enabled, errors are logged in this register regardless of the settings
of the uncorrectable error mask register.
2
1
0
RWC
RWC
RWC
0b
0b
0b
Non-Fatal Error Detected (NFED): When set, this bit indicates that non-fatal
error(s) were detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register
regardless of the settings of the uncorrectable error mask register.
Correctable Error Detected (CED): When set, this bit indicates that
correctable error(s) were detected. Errors are logged in this register regardless
of whether error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register
regardless of the settings of the correctable error mask register.
Datasheet
171
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.38
LCAP—Link Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: AC–AFh
Default Value:
Access:
Size:
02214D02h
RO, RWO
32 bits
This register indicates PCI Express device specific capabilities.
Default
Value
Bit
Access
Description
Port Number (PN): This field indicates the PCI Express port number for the
given PCI Express link. Matches the value in Element Self Description[31:24].
31:24
23:22
RO
RO
02h
000b
Reserved
Link Bandwidth Notification Capability: A value of 1b indicates support for
the Link Bandwidth Notification status and interrupt mechanisms. This capability
is required for all Root Ports and Switch downstream ports supporting Links
wider than x1 and/or multiple Link speeds.
21
RO
1b
This field is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
Data Link Layer Link Active Reporting Capable (DLLLARC): For a
Downstream Port, this bit must be set to 1b if the component supports the
optional capability of reporting the DL_Active state of the Data Link Control and
Management State Machine.
20
19
RO
RO
0b
0b
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
Surprise Down Error Reporting Capable (SDERC): For a Downstream Port,
this bit must be set to 1b if the component supports the optional capability of
detecting and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
Clock Power Management (CPM): A value of 1b in this bit indicates that the
component tolerates the removal of any reference clock(s) when the link is in
the L1 and L2/3 Ready link states. A value of 0b indicates the component does
not have this capability and that reference clock(s) must not be removed in
these link states.
18
RO
0b
This capability is applicable only in form factors that support "clock request"
(CLKREQ#) capability.
For a multi-function device, each function indicates its capability independently.
Power Management configuration software must only permit reference clock
removal if all functions of the multifunction device indicate a 1b in this bit.
L1 Exit Latency (L1ELAT): Indicates the length of time this Port requires to
complete the transition from L1 to L0. The value 010 b indicates the range of 2
us to less than 4 us.
17:15
RWO
010b
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.
172
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
L0s Exit Latency (L0SELAT): Indicates the length of time this Port requires to
complete the transition from L0s to L0.
000 = Less than 64 ns
001 = 64 ns to less than 128 ns
010 = 128 ns to less than 256 ns
011 = 256 ns to less than 512 ns
100 = 512 ns to less than 1 us
101 = 1 us to less than 2 us
110 = 2 us – 4 us
14:12
RO
100b
111 = More than 4 us
The actual value of this field depends on the common Clock Configuration bit
(LCTL[6])
Active State Link PM Support (ASLPMS): The MCH supports ASPM L0s and
L1.
11:10
9:4
RWO
RO
11b
10h
Max Link Width (MLW): This field indicates the maximum number of lanes
supported for this link.
10h = x16
Max Link Speed (MLS): Supported Link Speed - This field indicates the
supported Link speed(s) of the associated Port.
0001b = 2.5GT/s Link speed supported
0010b = 5.0GT/s and 2.5GT/s Link speeds supported
All other encodings are reserved.
3:0
RWO
2h
Datasheet
173
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.39
LCTL—Link Control
B/D/F/Type:
0/1/0/PCI
Address Offset: B0–B1h
Default Value:
Access:
Size:
0000h
RO, RW, RW/SC
16 bits
This register allows control of PCI Express link.
Default
Value
Bit
Access
Description
15:12
RO
0000b Reserved
Link Autonomous Bandwidth Interrupt Enable: When set, this bit enables
the generation of an interrupt to indicate that the Link Autonomous Bandwidth
Status bit has been set.
11
RW
0b
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
Link Bandwidth Management Interrupt Enable: When set, this bit enables
the generation of an interrupt to indicate that the Link Bandwidth Management
Status bit has been set.
10
RW
RO
0b
0b
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Hardware Autonomous Width Disable: When set, this bit disables hardware
from changing the Link width for reasons other than attempting to correct
unreliable Link operation by reducing Link width.
9
Devices that do not implement the ability autonomously to change Link width
are permitted to hardwire this bit to 0b.
The MCH does not support autonomous width change. So, this bit is "RO".
Enable Clock Power Management (ECPM): Applicable only for form factors
that support a "Clock Request" (CLKREQ#) mechanism, this enable functions as
follows:
0 = Clock power management is disabled and device must hold CLKREQ# signal
low
1 = When this bit is set to 1 the device is permitted to use CLKREQ# signal to
power manage link clock according to protocol defined in appropriate form
factor specification.
8
RO
0b
Default value of this field is 0b.
Components that do not support Clock Power Management (as indicated by a 0b
value in the Clock Power Management bit of the Link Capabilities Register) must
hardwire this bit to 0b.
Extended Synch (ES):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the L0s state
and when in the Recovery state.
7
RW
0b
This mode provides external devices (e.g., logic analyzers) monitoring the Link
time to achieve bit and symbol lock before the link enters L0 and resumes
communication.
This is a test mode only and may cause other undesired side effects such as
buffer overflows or underruns.
174
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
Common Clock Configuration (CCC):
0 = Indicates that this component and the component at the opposite end of this
Link are operating with asynchronous reference clock.
6
RW
0b
1 = Indicates that this component and the component at the opposite end of this
Link are operating with a distributed common reference clock.
The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and the
N_FTS value advertised during link training.
Retrain Link (RL):
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from
L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read.
5
RW/SC
0b
This bit is cleared automatically (no need to write a 0).
It is permitted to write 1b to this bit while simultaneously writing modified values
to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the
LTSSM is already in Recovery or Configuration, the modified values are not
required to affect the Link training that's already in progress.
Link Disable (LD):
0 = Normal operation.
1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via
Recovery) from L0, L0s, or L1 states. Link retraining happens automatically
on 0 to 1 transition, just like when coming out of reset.
4
RW
0b
Writes to this bit are immediately reflected in the value read from the bit,
regardless of actual Link state.
3
2
RO
RO
0b
0b
Read Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte.
Reserved
Active State PM (ASPM): Controls the level of active state power management
supported on the given link.
00 = Disabled
1:0
RW
00b
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
Datasheet
175
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.40
LSTS—Link Status
B/D/F/Type:
0/1/0/PCI
Address Offset: B2–B3h
Default Value:
Access:
Size:
1000h
RWC, RO
16 bits
This register indicates PCI Express link status.
Default
Value
Bit
Access
Description
Link Autonomous Bandwidth Status (LABWS): This bit is set to 1b by
hardware to indicate that hardware has autonomously changed link speed or
width, without the port transitioning through DL_Down status, for reasons other
than to attempt to correct unreliable link operation.
15
RWC
0b
This bit must be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was indicated as an autonomous
change.
Link Bandwidth Management Status (LBWMS): This bit is set to 1b by
hardware to indicate that either of the following has occurred without the port
transitioning through DL_Down status:
A link retraining initiated by a write of 1b to the Retrain Link bit has completed.
NOTE: This bit is Set following any write of 1b to the Retrain Link bit, including
14
RWC
0b
when the Link is in the process of retraining for some other reason.
Hardware has autonomously changed link speed or width to attempt to correct
unreliable link operation, either through an LTSSM timeout or a higher level
process
This bit must be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was not indicated as an
autonomous change.
Data Link Layer Link Active (Optional) (DLLLA): This bit indicates the
status of the Data Link Control and Management State Machine. It returns a 1b
to indicate the DL_Active state, 0b otherwise.
13
12
RO
RO
0b
1b
This bit must be implemented if the corresponding Data Link Layer Active
Capability bit is implemented. Otherwise, this bit must be hardwired to 0b.
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of the presence of a
reference on the connector.
1 = The device uses the same physical reference clock that the platform
provides on the connector.
Link Training (LTRN): Indicates that the Physical Layer LTSSM is in the
Configuration or Recovery state, or that 1b was written to the Retrain Link bit
but Link training has not yet begun. Hardware clears this bit when the LTSSM
exits the Configuration/Recovery state once Link training is complete.
11
10
RO
RO
0b
0b
Undefined: The value read from this bit is undefined. In previous versions of
this specification, this bit was used to indicate a Link Training Error. System
software must ignore the value read from this bit. System software is permitted
to write any value to this bit.
176
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
Negotiated Link Width (NLW): Indicates negotiated link width. This field is
valid only when the link is in the L0, L0s, or L1 states (after link width
negotiation is successfully completed).
01h = x1
04h = ‘x4 — This is not a supported PCIe Gen2.0 link width. Link width x4 is only
valid when PCIe Gen1.1 I/O card is used in the secondary port.
9:4
RO
00h
08h = x8 — This is not a supported PCIe Gen2.0 link width. Link width x8 is only
valid when PCIe Gen1.1 I/O card is used in the secondary port.
10h = x16
All other encodings are reserved.
Current Link Speed (CLS): This field indicates the negotiated Link speed of the
given PCI Express Link.
0001b = 2.5 GT/s PCI Express Link
0010b = 5 GT/s PCI Express Link
3:0
RO
0h
All other encodings are reserved. The value in this field is undefined when the
Link is not up.
6.41
SLOTCAP—Slot Capabilities
B/D/F/Type:
0/1/0/PCI
Address Offset: B4–B7h
Default Value:
Access:
Size:
00040000h
RWO, RO
32 bits
PCI Express Slot related registers.
Default
Value
Bit
Access
Description
Physical Slot Number (PSN): Indicates the physical slot number attached to
this Port.
31:19
18
RWO
RO
0000h
1b
Reserved
Electromechanical Interlock Present (EIP): When set to 1b, this bit
indicates that an Electromechanical Interlock is implemented on the chassis for
this slot.
17
RO
0b
Slot Power Limit Scale (SPLS): Specifies the scale used for the Slot Power
Limit Value.
00 = 1.0x
01 = 0.1x
16:15
RWO
00b
10 = 0.01x
11 = 0.001x
If this field is written, the link sends a Set_Slot_Power_Limit message.
Slot Power Limit Value (SPLV): In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot. Power limit (in
Watts) is calculated by multiplying the value in this field by the value in the Slot
Power Limit Scale field.
14:7
6:5
RWO
RO
00h
00b
If this field is written, the link sends a Set_Slot_Power_Limit message.
Reserved
Datasheet
177
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
Power Indicator Present (PIP): When set to 1b, this bit indicates that a
Power Indicator is electrically controlled by the chassis for this slot.
4
3
2
RO
RO
RO
0b
0b
0b
Attention Indicator Present (AIP): When set to 1b, this bit indicates that an
Attention Indicator is electrically controlled by the chassis.
MRL Sensor Present (MSP): When set to 1b, this bit indicates that an MRL
Sensor is implemented on the chassis for this slot.
Power Controller Present (PCP): When set to 1b, this bit indicates that a
software programmable Power Controller is implemented for this slot/adapter
(depending on form factor).
1
0
RO
RO
0b
0b
Attention Button Present (ABP): When set to 1b, this bit indicates that an
Attention Button for this slot is electrically controlled by the chassis.
6.42
SLOTCTL—Slot Control
B/D/F/Type:
0/1/0/PCI
Address Offset: B8–B9h
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
PCI Express Slot related registers.
Default
Value
Bit
Access
Description
15:13
RO
000b
Reserved
Data Link Layer State Changed Enable (DLLSCE): If the Data Link Layer
Link Active capability is implemented, when set to 1b, this field enables software
notification when Data Link Layer Link Active field is changed.
12
11
RO
0b
0b
If the Data Link Layer Link Active capability is not implemented, this bit is
permitted to be read-only with a value of 0b.
Electromechanical Interlock Control (EIC): If an Electromechanical
Interlock is implemented, a write of 1b to this field causes the state of the
interlock to toggle. A write of 0b to this field has no effect. A read to this register
always returns a 0.
RO
Power Controller Control (PCC): If a Power Controller is implemented, this
field when written sets the power state of the slot per the defined encodings.
Reads of this field must reflect the value from the latest write, unless software
issues a write without waiting for the previous command to complete in which
case the read value is undefined.
Depending on the form factor, the power is turned on/off either to the slot or
within the adapter. Note that in some cases the power controller may
autonomously remove slot power or not respond to a power-up request based on
a detected fault condition, independent of the Power Controller Control setting.
10
RO
0b
The defined encodings are:
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities register is set
to 0b, then writes to this field have no effect and the read value of this field is
undefined.
178
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
Default
Value
Bit
Access
Description
Power Indicator Control (PIC): If a Power Indicator is implemented, writes to
this field set the Power Indicator to the written state. Reads of this field must
reflect the value from the latest write, unless software issues a write without
waiting for the previous command to complete in which case the read value is
undefined.
00 = Reserved
01 = On
9:8
RO
00b
10 = Blink
11 = Off
If the Power Indicator Present bit in the Slot Capabilities register is 0b, this field
is permitted to be read-only with a value of 00b.
Attention Indicator Control (AIC): If an Attention Indicator is implemented,
writes to this field set the Attention Indicator to the written state.
Reads of this field must reflect the value from the latest write, unless software
issues a write without waiting for the previous command to complete in which
case the read value is undefined. If the indicator is electrically controlled by
chassis, the indicator is controlled directly by the downstream port through
implementation specific mechanisms.
7:6
RO
00b
00 = Reserved
01 = On
10 = Blink
11 = Off
If the Attention Indicator Present bit in the Slot Capabilities register is 0b, this
field is permitted to be read only with a value of 00b.
5:4
3
RO
00b
0b
Reserved
Presence Detect Changed Enable (PDCE): When set to 1b, this bit enables
software notification on a presence detect changed event.
RW
MRL Sensor Changed Enable (MSCE): When set to 1b, this bit enables
software notification on a MRL sensor changed event.
2
RO
0b
Default value of this field is 0b. If the MRL Sensor Present field in the Slot
Capabilities register is set to 0b, this bit is permitted to be read-only with a value
of 0b.
Power Fault Detected Enable (PFDE): When set to 1b, this bit enables
software notification on a power fault event.
1
0
RO
RO
0b
0b
Default value of this field is 0b. If Power Fault detection is not supported, this bit
is permitted to be read-only with a value of 0b
Button Pressed Enable (ABPE): When set to 1b, this bit enables software
notification on an attention button pressed event.
Datasheet
179
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.43
SLOTSTS—Slot Status
B/D/F/Type:
0/1/0/PCI
Address Offset: BA–BBh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
PCI Express Slot related registers.
Default
Value
Bit
Access
Description
15:7
RO
RO
0000000b Reserved
Presence Detect State (PDS): This bit indicates the presence of an adapter
in the slot, reflected by the logical "OR" of the Physical Layer in-band presence
detect mechanism and, if present, any out-of-band presence detect
mechanism defined for the slot's corresponding form factor. Note that the in-
band presence detect mechanism requires that power be applied to an adapter
for its presence to be detected.
6
0b
0 = Slot Empty
1 = Card Present in Slot
This register must be implemented on all Downstream Ports that implement
slots. For Downstream Ports not connected to slots (where the Slot
Implemented bit of the PCI Express Capabilities Register is 0b), this bit must
return 1b.
5:4
3
RO
00b
0b
Reserved
Detect Changed (PDC): This bit is set when the value reported in Presence
Detect State is changed.
RWC
MRL Sensor Changed (MSC): If an MRL sensor is implemented, this bit is set
when a MRL Sensor state change is detected. If an MRL sensor is not
implemented, this bit must not be set.
2
1
0
RO
RO
RO
0b
0b
0b
Power Fault Detected (PFD): If a Power Controller that supports power fault
detection is implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware capability, it is
possible that a power fault can be detected at any time, independent of the
Power Controller Control setting or the occupancy of the slot. If power fault
detection is not supported, this bit must not be set.
Attention Button Pressed (ABP): If an Attention Button is implemented,
this bit is set when the attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
180
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.44
RCTL—Root Control
B/D/F/Type:
0/1/0/PCI
Address Offset: BC–BDh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
Default
Value
Bit
Access
Description
15:4
RO
000h
Reserved
PME Interrupt Enable (PMEIE):
0 = No interrupts are generated as a result of receiving PME messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit of the Root Status Register. A PME interrupt is also
generated if the PME Status bit of the Root Status Register is set when this
bit is set from a cleared state.
3
2
1
0
RW
0b
0b
0b
0b
System Error on Fatal Error Enable (SEFEE): Controls the Root Complex's
response to fatal errors.
0 = No SERR generated on receipt of fatal error.
RW
RW
RW
1 = Indicates that an SERR should be generated if a fatal error is reported by
any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
System Error on Non-Fatal Uncorrectable Error Enable (SENFUEE):
Controls the Root Complex's response to non-fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-fatal error is reported
by any of the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
System Error on Correctable Error Enable (SECEE): Controls the Root
Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a correctable error is reported
by any of the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
Datasheet
181
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.45
RSTS—Root Status
B/D/F/Type:
0/1/0/PCI
Address Offset: C0–C3h
Default Value:
Access:
Size:
00000000h
RO, RWC
32 bits
This register provides information about PCI Express Root Complex specific
parameters.
Default
Value
Bit
Access
Description
31:18
RO
0000h Reserved
PME Pending (PMEP): Indicates that another PME is pending when the PME
Status bit is set. When the PME Status bit is cleared by software; the PME is
delivered by hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by hardware if no
more PMEs are pending.
17
RO
0b
PME Status (PMES): Indicates that PME was asserted by the requestor ID
indicated in the PME Requestor ID field. Subsequent PMEs are kept pending until
the status register is cleared by writing a 1 to this field.
16
RWC
RO
0b
PME Requestor ID (PMERID): Indicates the PCI requestor ID of the last PME
requestor.
15:0
0000h
6.46
PELC—PCI Express Legacy Control
B/D/F/Type:
0/1/0/PCI
Address Offset: EC–EFh
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
This register controls functionality that is needed by Legacy (non-PCI Express aware)
OSs during run time.
Default
Value
Bit
Access
Description
0000000
0h
31:3
RO
Reserved
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received (Assert_PMEGPE and
Deassert_PMEGPE messages on DMI). This enables the MCH to support
PMEs on the PCI Express port under legacy OSs.
2
1
RW
RO
0b
0b
Reserved
General Message GPE Enable (GENGPE):
0 = Do not forward received GPE assert/de-assert messages.
1 = Forward received GPE assert/de-assert messages. These general GPE
message can be received via the PCI Express port from an external Intel
device and will be subsequently forwarded to the ICH (via Assert_GPE and
Deassert_GPE messages on DMI).
0
RW
0b
182
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.47
VCECH—Virtual Channel Enhanced Capability
Header
B/D/F/Type:
0/1/0/MMR
Address Offset: 100–103h
Default Value:
Access:
Size:
14010002h
RO
32 bits
This register indicates PCI Express device Virtual Channel capabilities. Extended
capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability
structures.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): The Link Declaration Capability is the next
in the PCI Express extended capabilities list.
31:20
RO
RO
RO
140h
PCI Express Virtual Channel Capability Version (PCIEVCCV): Hardwired to
1 to indicate compliances with the 1.1 version of the PCI Express specification.
19:16
15:0
1h
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0002 h identifies this linked list item
(capability structure) as being for PCI Express Virtual Channel registers.
0002h
6.48
PVCCAP1—Port VC Capability Register 1
B/D/F/Type:
0/1/0/MMR
Address Offset: 104–107h
Default Value:
Access:
Size:
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Default
Value
Bit
Access
Description
31:7
RO
00000h Reserved
Low Priority Extended VC Count (LPEVCC): Indicates the number of
(extended) Virtual Channels in addition to the default VC belonging to the low-
priority VC (LPVC) group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
6:4
RO
000b
The value of 0 in this field implies strict VC arbitration.
3
RO
RO
0b
Reserved
Extended VC Count (EVCC): Indicates the number of (extended) Virtual
Channels in addition to the default VC supported by the device.
2:0
000b
Datasheet
183
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.49
PVCCAP2—Port VC Capability Register 2
B/D/F/Type:
0/1/0/MMR
Address Offset: 108–10Bh
Default Value:
Access:
Size:
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Default
Value
Bit
Access
Description
VC Arbitration Table Offset (VCATO): Indicates the location of the VC
Arbitration Table. This field contains the zero-based offset of the table in
DQWORDS (16 bytes) from the base address of the Virtual Channel Capability
Structure. A value of 0 indicates that the table is not present (due to fixed VC
priority).
31:24
RO
RO
00h
23:0
0000h Reserved
6.50
PVCCTL—Port VC Control
B/D/F/Type:
0/1/0/MMR
Address Offset: 10C–10Dh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:4
RO
RW
RO
000h
Reserved
VC Arbitration Select (VCAS): This field will be programmed by software to
the only possible value as indicated in the VC Arbitration Capability field. Since
there is no other VC supported than the default, this field is reserved.
3:1
0
000b
0b
Reserved
184
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.51
VC0RCAP—VC0 Resource Capability
B/D/F/Type:
0/1/0/MMR
Address Offset: 110–113h
Default Value:
Access:
Size:
00000001h
RO
32 bits
Default
Bit
Access
Description
Value
0000h Reserved
Reject Snoop Transactions (RSNPT):
31:16
RO
RO
RO
0 = Transactions with or without the No Snoop bit set within the Transaction
Layer Packet header are allowed on this VC.
1 = When Set, any transaction for which the No Snoop attribute is applicable but
is not Set within the TLP Header will be rejected as an Unsupported Request.
15
0b
14:8
0000h Reserved
Port Arbitration Capability: Indicates types of Port Arbitration supported by
the VC resource. This field is valid for all Switch Ports, Root Ports that support
peer-to-peer traffic, and RCRBs, but not for PCI Express Endpoint devices or
Root Ports that do not support peer to peer traffic.
Each bit location within this field corresponds to a Port Arbitration Capability
defined below. When more than one bit in this field is Set, it indicates that the
VC resource can be configured to provide different arbitration services.
Software selects among these capabilities by writing to the Port Arbitration
Select field (see below).
Defined bit positions are:
7:0
RO
01h
Bit[0]
= Default = 01b; Non-configurable hardware-fixed arbitration
scheme, e.g., Round Robin (RR)
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
= Weighted Round Robin (WRR) arbitration with 32 phases
= WRR arbitration with 64 phases
= WRR arbitration with 128 phases
= Time-based WRR with 128 phases
= WRR arbitration with 256 phases
Bits[6:7] = Reserved
MCH default indicates "Non-configurable hardware-fixed arbitration scheme".
Datasheet
185
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.52
VC0RCTL—VC0 Resource Control
B/D/F/Type:
0/1/0/MMR
Address Offset: 114–117h
Default Value:
Access:
Size:
800000FFh
RO, RW
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Default
Value
Bit
Access
Description
VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as VC0 can
never be disabled.
31
RO
RO
RO
RO
1b
0h
30:27
26:24
23:20
Reserved
VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0, this is
hardwired to 0 and read only.
000b
0000h Reserved
Port Arbitration Select: This field configures the VC resource to provide a
particular Port Arbitration service. This field is valid for RCRBs, Root Ports that
support peer to peer traffic, and Switch Ports, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer traffic.
19:17
16:8
RW
RO
000b
00h
The permissible value of this field is a number corresponding to one of the
asserted bits in the Port Arbitration Capability field of the VC resource.
Reserved
TC/VC0 Map (TCVC0M): Indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions with
the TC labels are targeted at the given Link.
7:1
0
RW
RO
7Fh
1b
TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.
186
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.53
VC0RSTS—VC0 Resource Status
B/D/F/Type:
0/1/0/MMR
Address Offset: 11A–11Bh
Default Value:
Access:
Size:
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Default
Value
Bit
Access
Description
15:2
RO
RO
RO
0000h Reserved
VC0 Negotiation Pending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set
by default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state.
1
1b
0b
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
Reserved
6.54
RCLDECH—Root Complex Link Declaration
Enhanced
B/D/F/Type:
0/1/0/MMR
Address Offset: 140–143h
Default Value:
Access:
Size:
00010005h
RO
32 bits
This capability declares links from this element (PCI Express) to other elements of the
root complex component to which it belongs. See PCI Express specification for link/
topology declaration requirements.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This is the last capability in the PCI Express
extended capabilities list.
31:20
RO
RO
RO
000h
Link Declaration Capability Version (LDCV): Hardwired to 1 to indicate
compliances with the 1.1 version of the PCI Express specification.
19:16
15:0
1h
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0005h identifies this linked list item
(capability structure) as being for PCI Express Link Declaration Capability.
0005h
Datasheet
187
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.55
ESD—Element Self Description
B/D/F/Type:
0/1/0/MMR
Address Offset: 144–147h
Default Value:
Access:
Size:
02000100h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Default
Value
Bit
Access
Description
Port Number (PN): Specifies the port number associated with this element
with respect to the component that contains this element. This port number
value is utilized by the egress port of the component to provide arbitration to
this Root Complex Element.
31:24
RO
02h
Component ID (CID): Identifies the physical component that contains this
Root Complex Element.
23:16
15:8
RWO
RO
00h
01h
Number of Link Entries (NLE): Indicates the number of link entries following
the Element Self Description. This field reports 1 (to Egress port only as we don't
report any peer-to-peer capabilities in our topology).
7:4
3:0
RO
RO
0h
0h
Reserved
Element Type (ET): Indicates Configuration Space Element.
6.56
LE1D—Link Entry 1 Description
B/D/F/Type:
0/1/0/MMR
Address Offset: 150–153h
Default Value:
Access:
Size:
00000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
Target Port Number (TPN): Specifies the port number associated with the
element targeted by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
31:24
RO
00h
Target Component ID (TCID): Identifies the physical or logical component
that is targeted by this link entry.
23:16
15:2
1
RWO
RO
00h
0000h Reserved
Link Type (LTYP): Indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
RO
0b
Link Valid (LV):
0
RWO
0b
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
188
Datasheet
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.57
LE1A—Link Entry 1 Address
B/D/F/Type:
0/1/0/MMR
Address Offset: 158-15Fh
Default Value:
Access:
Size:
0000000000000000h
RO, RWO
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
0000000
0h
63:32
RO
Reserved
Link Address (LA): Memory mapped base address of the RCRB that is the
target element (Egress Port) for this link entry.
31:12
11:0
RWO
RO
00000h
000h
Reserved
6.58
PESSTS—PCI Express* Sequence Status
B/D/F/Type:
0/1/0/MMR
Address Offset: 218–21Fh
Default Value:
Access:
Size:
0000000000000FFFh
RO
64 bits
PCI Express status reporting that is required by the PCI Express specification.
Default
Value
Bit
Access
Description
63:60
RO
RO
0h
Reserved
Next Transmit Sequence Number (NTSN): Value of the NXT_TRANS_SEQ
counter. This counter represents the transmit Sequence number to be applied to
the next Transaction Layer Packet to be transmitted onto the Link for the first
time.
59:48
000h
47:44
43:32
31:28
27:16
RO
RO
RO
RO
0h
000h
0h
Reserved
Next Packet Sequence Number (NPSN): Packet sequence number to be
applied to the next Transaction Layer Packet to be transmitted or re-transmitted
onto the Link.
Reserved
Next Receive Sequence Number (NRSN): This is the sequence number
associated with the Transaction Layer Packet that is expected to be received
next.
000h
15:12
11:0
RO
RO
0h
Reserved
Last Acknowledged Sequence Number (LASN): This is the sequence
number associated with the last acknowledged Transaction Layer Packet.
FFFh
Datasheet
189
Host-Primary PCI Express* Bridge Registers (D1:F0)
§ §
190
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7
Intel Manageability Engine
Subsystem PCI (D3:F0,F3)
This chapter provides the register descriptions for Device 3 (D3), Functions 0 (F0) and
3 (F3).
7.1
HECI Function in ME Subsystem (D3:F0)
Device 3 contains registers for the Intel Manageability Engine. The table below lists the
PCI configuration registers in order of ascending offset address.
Note:
The following sections describe Device 3 configuration registers only.
Table 13.
HECI Function in ME Subsystem (D3:F0) Register Address Map
Address
Offset
Default
Value
Symbol
Register Name
Access
0–3h
4–5h
6–7h
ID
Identifiers
Command
29E48086h
0000h
RO
RO, RW
RO
CMD
STS
Device Status
0010h
See register
description
8h
RID
Revision ID
RO
9–Bh
Ch
CC
CLS
Class Code
0C8001h
00h
RO
RO
RO
RO
Cache Line Size
Master Latency Timer
Header Type
Dh
MLT
00h
Eh
HTYPE
80h
0000000000
000004h
10–17h
HECI_MBAR HECI MMIO Base Address
RO, RW
2C–2Fh
34h
SS
CAP
INTR
MGNT
MLAT
HFS
PID
Sub System Identifiers
Capabilities Pointer
00000000h
50h
RWO
RO
3C–3Dh
3Eh
Interrupt Information
0100h
00h
RO, RW
RO
Minimum Grant
3Fh
Maximum Latency
00h
RO
40–43h
50–51h
52–53h
Host Firmware Status
00000000h
8C01h
C803h
RO
PCI Power Management Capability ID
PCI Power Management Capabilities
RO
PC
RO
PCI Power Management Control And
Status
RWC, RO,
RW
54–55h
8C–8Dh
8E–8Fh
PMCS
MID
MC
0008h
0005h
0080h
Message Signaled Interrupt Identifiers
RO
Message Signaled Interrupt Message
Control
RO, RW
Message Signaled Interrupt Message
Address
90–93h
94–97h
MA
00000000h
00000000h
RW, RO
RW
Message Signaled Interrupt Upper
Address (Optional)
MUA
Message Signaled Interrupt Message
Data
98–99h
A0h
MD
0000h
00h
RW
RW
HIDM
HECI Interrupt Delivery Mode
Datasheet
191
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.1
ID—Identifiers
B/D/F/Type:
0/3/0/PCI
Address Offset: 0–3h
Default Value:
Access:
Size:
29E48086h
RO
32 bits
Default
Value
Bit
Access
Description
Device ID (DID): Device ID (DID): This field indicates what device number
assigned by Intel.
31:16
15:0
RO
RO
29E4h
Vendor ID (VID): Vendor ID (VID): This field indicates Intel is the vendor,
assigned by the PCI SIG.
8086h
7.1.2
CMD—Command
B/D/F/Type:
0/3/0/PCI
Address Offset: 4–5h
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:11
10
RO
RW
RO
00000b Reserved
Interrupt Disable (ID): Disables this device from generating PCI line based
interrupts. This bit does not have any effect on MSI operation.
0b
9:3
00h
Reserved
Bus Master Enable (BME): Controls the HECI host controller's ability to act as
a system memory master for data transfers. When this bit is cleared, HECI bus
master activity stops and any active DMA engines return to an idle condition.
This bit is made visible to firmware through the H_PCI_CSR register, and
changes to this bit may be configured by the H_PCI_CSR register to generate an
ME MSI.
2
RW
0b
0 = HECI is blocked from generating MSI to the host processor.
Note that this bit does not block HECI accesses to ME-UMA, i.e. writes or reads
to the host and ME circular buffers through the read window and write window
registers still cause ME backbone transactions to ME-UMA.
Memory Space Enable (MSE): Controls access to the HECI host controller’s
memory mapped register space.
1
0
RW
RO
0b
0b
Reserved
192
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.3
STS—Device Status
B/D/F/Type:
0/3/0/PCI
Address Offset: 6–7h
Default Value:
Access:
Size:
0010h
RO
16 bits
Default
Value
Bit
Access
Description
15:5
4
RO
RO
0h
Reserved
Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to
1.
1b
Interrupt Status (IS): Indicates the interrupt status of the device
1 = Asserted
3
RO
RO
0b
2:0
000b
Reserved
7.1.4
RID—Revision ID
B/D/F/Type:
0/3/0/PCI
Address Offset: 8h
Default Value:
Access:
Size:
see table below
RO
8 bits
Default
Value
Bit
Access
Description
Revision ID (RID): This field indicates stepping of the HECI host controller.
Refer to the Intel® X38 Express Chipset Specification Update for the value of
this register.
See
Description
7:0
RO
7.1.5
CC—Class Code
B/D/F/Type:
0/3/0/PCI
Address Offset: 9–Bh
Default Value:
Access:
Size:
0C8001h
RO
24 bits
Default
Value
Bit
Access
Description
Base Class Code (BCC): Indicates the base class code of the HECI host
controller device.
23:16
15:8
7:0
RO
RO
RO
0ch
Sub Class Code (SCC): Indicates the sub class code of the HECI host controller
device.
80h
01h
Programming Interface (PI): Indicates the programming interface of the
HECI host controller device.
Datasheet
193
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.6
CLS—Cache Line Size
B/D/F/Type:
0/3/0/PCI
Address Offset: Ch
Default Value:
Access:
Size:
00h
RO
8 bits
Default
Value
Bit
Access
RO
Description
7:0
00h
Cache Line Size (CLS): Not implemented, hardwired to 0.
7.1.7
MLT—Master Latency Timer
B/D/F/Type:
0/3/0/PCI
Address Offset: Dh
Default Value:
Access:
Size:
00h
RO
8 bits
Default
Value
Bit
Access
RO
Description
Master Latency Timer (MLT): Not implemented, hardwired to 0.
7:0
00h
7.1.8
HTYPE—Header Type
B/D/F/Type:
0/3/0/PCI
Address Offset: Eh
Default Value:
Access:
Size:
80h
RO
8 bits
Default
Value
Bit
Access
Description
Multi-Function Device (MFD): Indicates the HECI host controller is part of a
multi-function device.
7
RO
RO
1b
Header Layout (HL): Indicates that the HECI host controller uses a target
device layout.
6:0
0000000b
194
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.9
HECI_MBAR—HECI MMIO Base Address
B/D/F/Type:
0/3/0/PCI
Address Offset: 10–17h
Default Value:
Access:
Size:
0000000000000004h
RO, RW
64 bits
Default
Value
Bit
Access
Description
0000000
63:4
RW
0000000 Base Address (BA): Base address of register memory space.
0h
3
RO
RO
0b
Prefetchable (PF): Indicates that this range is not pre-fetchable
Type (TP): Indicates that this range can be mapped anywhere in 64-bit address
space.
2:1
10b
Resource Type Indicator (RTE): Indicates a request for register memory
space.
0
RO
0b
7.1.10
SS—Sub System Identifiers
B/D/F/Type:
0/3/0/PCI
Address Offset: 2C–2Fh
Default Value:
Access:
Size:
00000000h
RWO
32 bits
Default
Value
Bit
Access
Description
Subsystem ID (SSID): Indicates the sub-system identifier. This field should be
31:16
RWO
RWO
0000h programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
Subsystem Vendor ID (SSVID): Indicates the sub-system vendor identifier.
0000h This field should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared by PLTRST#.
15:0
Datasheet
195
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.11
CAP—Capabilities Pointer
B/D/F/Type:
0/3/0/PCI
Address Offset: 34h
Default Value:
Access:
Size:
50h
RO
8 bits
Default
Value
Bit
Access
Description
Capability Pointer (CP): Indicates the first capability pointer offset. It points
to the PCI power management capability offset.
7:0
RO
50h
7.1.12
INTR—Interrupt Information
B/D/F/Type:
0/3/0/PCI
Address Offset: 3C–3Dh
Default Value:
Access:
Size:
0100h
RO, RW
16 bits
Default
Value
Bit
Access
Description
Interrupt Pin (IPIN): This indicates the interrupt pin the HECI host controller
uses. The value of 01h selects INTA# interrupt pin. Note: As HECI is an internal
device in the MCH, the INTA# pin is implemented as an INTA# message to the
ICH.
15:8
RO
01h
Interrupt Line (ILINE): Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this
register.
7:0
RW
00h
7.1.13
MGNT—Minimum Grant
B/D/F/Type:
0/3/0/PCI
Address Offset: 3Eh
Default Value:
Access:
Size:
00h
RO
8 bits
Default
Value
Bit
Access
RO
Description
Grant (GNT): Not implemented, hardwired to 0.
7:0
00h
196
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.14
MLAT—Maximum Latency
B/D/F/Type:
0/3/0/PCI
Address Offset: 3Fh
Default Value:
Access:
Size:
00h
RO
8 bits
Default
Value
Bit
Access
RO
Description
Latency (LAT): Not implemented, hardwired to 0.
7:0
00h
7.1.15
HFS—Host Firmware Status
B/D/F/Type:
0/3/0/PCI
Address Offset: 40–43h
Default Value:
Access:
Size:
00000000h
RO
32 bits
Default
Value
Bit
Access
Description
Firmware Status Host Access (FS_HA): Indicates current status of the
firmware for the HECI controller. This field is the host's read only access to the
FS field in the ME Firmware Status AUX register.
0000000
0h
31:0
RO
7.1.16
PID—PCI Power Management Capability ID
B/D/F/Type:
0/3/0/PCI
Address Offset: 50–51h
Default Value:
Access:
Size:
8C01h
RO
16 bits
Default
Value
Bit
Access
Description
Next Capability (NEXT): Indicates the location of the next capability item in
the list. This is the Message Signaled Interrupts capability.
15:8
7:0
RO
RO
8Ch
01h
Cap ID (CID): Indicates that this pointer is a PCI power management.
Datasheet
197
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.17
PC—PCI Power Management Capabilities
B/D/F/Type:
0/3/0/PCI
Address Offset: 52–53h
Default Value:
Access:
Size:
C803h
RO
16 bits
Default
Value
Bit
Access
Description
PME_Support (PSUP): Indicates the states that can generate PME#.
15:11
RO
11001b
HECI can assert PME# from any D-state except D1 or D2 which are not
supported by HECI.
10
9
RO
RO
0b
0b
D2_Support (D2S): The D2 state is not supported for the HECI host controller.
D1_Support (D1S): The D1 state is not supported for the HECI host controller.
Aux_Current (AUXC): Reports the maximum Suspend well current required
when in the D3COLD state.
8:6
5
RO
RO
000b
0b
Device Specific Initialization (DSI): Indicates whether device-specific
initialization is required.
4
3
RO
RO
0b
0b
Reserved
PME Clock (PMEC): Indicates that PCI clock is not required to generate PME#.
Version (VS): Indicates support for Revision 1.2 of the PCI Power Management
Specification.
2:0
RO
011b
7.1.18
PMCS—PCI Power Management Control And Status
B/D/F/Type:
0/3/0/PCI
Address Offset: 54–55h
Default Value:
Access:
Size:
0008h
RWC, RO, RW
16 bits
Default
Value
Bit
Access
Description
PME Status (PMES): The PME Status bit in HECI space can be set to '1' by ME
FW performing a write into AUX register to set PMES.
This bit is cleared by host processor writing a '1' to it.
ME cannot clear this bit.
15
RWC
0b
Host processor writes with value '0' have no effect on this bit.
This bit is reset to '0' by MRST#
14:9
8
RO
RW
RO
000000b Reserved
PME Enable (PMEE): This bit is read/write, under control of host SW. It does
not directly have an effect on PME events. However, this bit is shadowed into
AUX space so ME FW can monitor it. The ME FW is responsible for ensuring that
FW does not cause the PME-S bit to transition to '1' while the PMEE bit is '0',
indicating that host SW had disabled PME.
0b
This bit is reset to '0' by MRST#
7:4
0000b Reserved
198
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
Default
Value
Bit
Access
Description
No_Soft_Reset (NSR): This bit indicates that when the HECI host controller is
transitioning from D3hot to D0 due to power state command, it does not perform
an internal reset.
3
2
RO
RO
1b
0b
Reserved
Power State (PS): This field is used both to determine the current power state
of the HECI host controller and to set a new power state. The values are:
00 = D0 state
1:0
RW
00b
11 = D3HOT state
The D1 and D2 states are not supported for this HECI host controller. When in
the D3HOT state, the HBA’s configuration space is available, but the register
memory spaces are not. Additionally, interrupts are blocked.
7.1.19
MID—Message Signaled Interrupt Identifiers
B/D/F/Type:
0/3/0/PCI
Address Offset: 8C–8Dh
Default Value:
Access:
Size:
0005h
RO
16 bits
Default
Value
Bit
Access
Description
Next Pointer (NEXT): Indicates the next item in the list. This can be other
capability pointers (such as PCI-X or PCI-Express) or it can be the last item in
the list.
15:8
7:0
RO
RO
00h
05h
Capability ID (CID): Capabilities ID indicates MSI.
7.1.20
MC—Message Signaled Interrupt Message Control
B/D/F/Type:
0/3/0/PCI
Address Offset: 8E–8Fh
Default Value:
Access:
Size:
0080h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:8
7
RO
RO
00h
Reserved
64 Bit Address Capable (C64): Specifies whether capable of generating 64-bit
messages.
1b
6:4
3:1
RO
RO
000b
000b
Multiple Message Enable (MME): Not implemented, hardwired to 0.
Multiple Message Capable (MMC): Not implemented, hardwired to 0.
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not
used to generate interrupts.
0
RW
0b
Datasheet
199
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.21
MA—Message Signaled Interrupt Message Address
B/D/F/Type:
0/3/0/PCI
Address Offset: 90–93h
Default Value:
Access:
Size:
00000000h
RW, RO
32 bits
Default
Value
Bit
Access
Description
0000000 Address (ADDR): Lower 32 bits of the system specified message address,
31:2
1:0
RW
RO
0h
always DW aligned.
00b
Reserved
7.1.22
MUA—Message Signaled Interrupt Upper Address
(Optional)
B/D/F/Type:
0/3/0/PCI
Address Offset: 94–97h
Default Value:
Access:
Size:
00000000h
RW
32 bits
Default
Value
Bit
Access
Description
0000000 Upper Address (UADDR): Upper 32 bits of the system specified message
31:0
RW
0h address. This register is optional and only implemented if MC.C64=1.
7.1.23
MD—Message Signaled Interrupt Message Data
B/D/F/Type:
0/3/0/PCI
Address Offset: 98–99h
Default Value:
Access:
Size:
0000h
RW
16 bits
Default
Value
Bit
Access
Description
Data (Data): This 16-bit field is programmed by system software if MSI is
15:0
RW
0000h enabled. Its content is driven onto the FSB during the data phase of the MSI
memory write transaction.
200
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.1.24
HIDM—HECI Interrupt Delivery Mode
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
A0h
00h
RW
8 bits
00h
Size:
BIOS Optimal Default
This register is used to select interrupt delivery mechanism for HECI to Host processor
interrupts.
Default
Value
Bit
Access
Description
7:2
RO
0h
Reserved
HECI Interrupt Delivery Mode (HIDM): These bits control what type of
interrupt the HECI will send when ME FW writes to set the M_IG bit in AUX
space. They are interpreted as follows:
1:0
RW
00b
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
Datasheet
201
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2
KT IO/ Memory Mapped Device Specific Registers
[D3:F3]
Table 14.
KT IO/Memory Mapped Register Address Map
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
0h
0h
0h
1h
1h
2h
2h
3h
4h
5h
6h
7h
KTRxBR
KTTHR
KTDLLR
KTIER
KT Receive Buffer
00h
00h
00h
00h
00h
01h
00h
03h
00h
00h
00h
00h
RO/V
WO
KT Transmit Holding
KT Divisor Latch LSB
KT Interrupt Enable
KT Divisor Latch MSB
KT Interrupt Identification
KT FIFO Control
RW/V
RW/V,RO/V
RW/V
KTDLMR
KTIIR
RO
KTFCR
KTLCR
KTMCR
KTLSR
KTMSR
KTSCR
WO
KT Line Control
RW
KT Modem Control
KT Line Status
RO, RW
RO, RO/CR
RO, RO/CR
RW
KT Modem Status
KT Scratch
7.2.1
KTRxBR—KT Receive Buffer
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 0h
Default Value:
Access:
Size:
00h
RO/V
8 bits
This implements the KT Receiver Data register. Host access to this address, depends on
the state of the DLAB bit {KTLCR[7]). It must be 0 to access the KTRxBR.
RxBR:
Host reads this register when FW provides it the receive data in non-FIFO mode. In
FIFO mode, host reads to this register translate into a read from ME memory (RBR
FIFO).
Note:
Reset: Host System Reset or D3->D0 transition.
Default
Value
Bit
Access
Description
Receiver Buffer Register (RBR): Implements the Data register of the Serial
Interface. If the Host does a read, it reads from the Receive Data Buffer.
7:0
RO/V
00h
202
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.2
KTTHR—KT Transmit Holding
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 0h
Default Value:
Access:
Size:
00h
WO
8 bits
This implements the KT Transmit Data register. Host access to this address, depends on
the state of the DLAB bit {KTLCR[7]). It must be 0 to access the KTTHR.
THR:
When host wants to transmit data in the non-FIFO mode, it writes to this register. In
FIFO mode, writes by host to this address cause the data byte to be written by
hardware to ME memory (THR FIFO).
Note:
Bit
Reset: Host System Reset or D3->D0 transition.
Default
Access
Description
Value
Transmit Holding Register (THR): Implements the Transmit Data register of
the Serial Interface. If Host does a write, it writes to the Transmit Holding
Register.
7:0
WO
00h
7.2.3
KTDLLR—KT Divisor Latch LSB
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 0h
Default Value:
Access:
Size:
00h
RW/V
8 bits
This register implements the KT DLL register. Host can Read/Write to this register only
when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the
KTRBR depending on Read or Write.
This is the standard Serial Port Divisor Latch register. This register is only for software
compatibility and does not affect performance of the hardware.
Note:
Reset: Host System Reset or D3->D0 transition.
Default
Value
Bit
Access
RW/V
Description
7:0
00h
Divisor Latch LSB (DLL): Implements the DLL register of the Serial Interface.
Datasheet
203
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.4
KTIER—KT Interrupt Enable
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 1h
Default Value:
Access:
Size:
00h
RW/V, RO/V
8 bits
This implements the KT Interrupt Enable register. Host access to this address, depends
on the state of the DLAB bit {KTLCR[7]). It must be "0" to access this register. The bits
enable specific events to interrupt the Host. See bit specific definition.
Note:
Reset: Host System Reset or D3 -> D0 transition.
Default
Value
Bit
Access
Description
7:4
3
RO/V
RW/V
0h
Reserved
MSR (IER2): When set, this bit enables bits in Modem Status register to cause
an interrupt to host
0b
0b
0b
0b
LSR (IER1): When set, this bit enables bits in Receiver Line Status Register to
cause an Interrupt to Host
2
1
0
RW/V
RW/V
RW/V
THR (IER1): When set, this bit enables interrupt to be sent to Host when the
tranmit Holding register is empty
DR (IER0): When set, Received Data Ready (or Receive FIFO Timeout)
interrupts are enabled to be sent to Host.
7.2.5
KTDLMR—KT Divisor Latch MSB
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 1h
Default Value:
Access:
Size:
00h
RW/V
8 bits
Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this
bit is 0, Host accesses the KTIER.
This is the standard Serial interface's Divisor Latch register's MSB. This register is only
for software compatibility and does not affect performance of the hardware.
Note:
Reset: Host System Reset or D3->D0 transition.
Default
Value
Bit
Access
Description
Divisor Latch MSB (DLM): Implements the Divisor Latch MSB register of the
Serial Interface.
7:0
RW/V
00h
204
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.6
KTIIR—KT Interrupt Identification
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 2h
Default Value:
Access:
Size:
01h
RO
8 bits
The KT IIR register prioritizes the interrupts from the function into 4 levels and records
them in the IIR_STAT field of the register. When Host accesses the IIR, hardware
freezes all interrupts and provides the priority to the Host. Hardware continues to
monitor the interrupts but does not change its current indication until the Host read is
over. Table in the Host Interrupt Generation section shows the contents.
Note:
Bit
Reset: See specific Bit descriptions
Default
Access
Description
Value
FIFO Enable (FIEN1): This bit is connected by hardware to bit 0 in the FCR
register.
7
RO
0b
Reset: Host System Reset or D3->D0 transition
FIFO Enable (FIEN0): This bit is connected by hardware to bit 0 in the FCR
register.
6
RO
RO
0b
Reset: Host System Reset or D3->D0 transition
5:4
00b
Reserved
IIR STATUS (IIRSTS): These bits are asserted by the hardware according to
the source of the interrupt and the priority level. Refer to the section on Host
Interrupt Generation for a table of values.
3:1
0
RO
RO
000b
1b
Reset: ME system Reset
Interrupt Status (INTSTS): When "0" indicates pending interrupt to Host
When "1" indicates no pending interrupt to Host.
Reset: Host system Reset or D3->D0 transition
Datasheet
205
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.7
KTFCR—KT FIFO Control
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 2h
Default Value:
Access:
Size:
00h
WO
8 bits
When Host writes to this address, it writes to the KTFCR. The FIFO control Register of
the serial interface is used to enable the FIFO's, set the receiver FIFO trigger level and
clear FIFO's under the direction of the Host.
When Host reads from this address, it reads the KTIIR.
Reset: Host System Reset or D3->D0 transition.
Note:
Default
Value
Bit
Access
Description
Receiver Trigger Level (RTL): Trigger level in bytes for the RCV FIFO. Once
the trigger level number of bytes is reached, an interrupt is sent to the Host.
00 = 01
01 = 04
10 = 08
11 = 14
7:6
WO
00b
5:4
3
WO
WO
00b
0b
Reserved
RDY Mode (RDYM): This bit has no affect on hardware performance.
XMT FIFO Clear (XFIC): When the Host writes one to this bit, the hardware
will clear the XMT FIFO. This bit is self-cleared by hardware.
2
1
WO
WO
0b
0b
RCV FIFO Clear (RFIC): When the Host writes one to this bit the hardware will
clear the RCV FIFO. This bit is self-cleared by hardware.
FIFO Enable (FIE): When set, this bit indicates that the KT interface is working
in FIFO node. When this bit value is changed, the RCV and XMT FIFO are cleared
by hardware.
0
WO
0b
206
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.8
KTLCR—KT Line Control
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 3h
Default Value:
Access:
Size:
03h
RW
8 bits
The line control register specifies the format of the asynchronous data communications
exchange and sets the DLAB bit. Most bits in this register have no affect on hardware
and are only used by the FW.
Note:
Reset: Host System Reset or D3->D0 transition.
Default
Value
Bit
Access
Description
Divisor Latch Address Bit (DLAB): This bit is set when the Host wants to
read/write the Divisor Latch LSB and MSB Registers. This bit is cleared when the
Host wants to access the Receive Buffer Register or the Transmit Holding
Register or the Interrupt Enable Register.
7
RW
0b
6
5:4
3
RW
RW
RW
RW
RW
0b
00b
0b
Break Control (BC): This bit has no affect on hardware.
Parity Bit Mode (PBM): This bit has no affect on hardware.
Parity Enable (PE): This bit has no affect on hardware.
Stop Bit Select (SBS): This bit has no affect on hardware.
Word Select Byte (WSB): This bit has no affect on hardware.
2
0b
1:0
11b
Datasheet
207
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.9
KTMCR—KT Modem Control
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 4h
Default Value:
Access:
Size:
00h
RO, RW
8 bits
The Modem Control Register controls the interface with the modem. Since the FW
emulates the modem, the Host communicates to the FW via this register. Register has
impact on hardware when the Loopback mode is on.
Note:
Reset: Host system Reset or D3->D0 transition.
Default
Value
Bit
Access
Description
7:5
RO
000b
Reserved
Loop Back Mode (LBM): When set by Host, this bit indicates that the serial
port is in loop Back mode. This means that the data that is transmitted by the
host should be received. Helps in debug of the interface.
4
3
2
1
0
RW
0b
0b
0b
0b
0b
Output 2 (OUT2): This bit has no affect on hardware in normal mode. In loop
back mode the value of this bit is written by hardware to Modem Status Register
bit 7.
RW
RW
RW
RW
Output 1 (OUT1): This bit has no affect on hardware in normal mode. In loop
back mode the value of this bit is written by hardware to Modem Status Register
bit 6.
Request to Send Out (RTSO): This bit has no affect on hardware in normal
mode. In loopback mode, the value of this bit is written by hardware to Modem
Status Register bit 4.
Data Terminal Ready Out (DRTO): This bit has no affect on hardware in
normal mode. In loopback mode, the value in this bit is written by hardware to
Modem Status Register Bit 5.
208
Datasheet
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.10
KTLSR—KT Line Status
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 5h
Default Value:
Access:
Size:
00h
RO, RO/CR
8 bits
This register provides status information of the data transfer to the Host. Error
indication, etc., are provided by the hardware(HW)/firmware(FW) to the host via this
register.
Note:
Reset: Host system reset or D3->D0 transition.
Default
Value
Bit
Access
Description
RX FIFO Error (RXFER): This bit is cleared in non FIFO mode. Bit is connected
to the BI bit in FIFO mode.
7
6
RO
RO
0b
Transmit Shift Register Empty (TEMT): This bit is connected by hardware to
bit 5 (THRE) of this register
0b
0b
Transmit Holding Register Empty (THRE): The bit is always set when the
mode (FIFO/Non-FIFO) is changed by the Host. This bit is active only when the
THR operation is enabled by the FW.
This bit has acts differently in the different modes:
5
RO
•
Non FIFO Mode: This bit is cleared by hardware when the Host writes to the THR
registers and set by hardware when the FW reads the THR register.
•
FIFO Mode: This bit is set by hardware when the THR FIFO is empty, and cleared by
hardware when the THR FIFO is not empty.
This bit is reset on Host system reset or D3->D0 transition.
Break Interrupt (BI): This bit is cleared by hardware when the LSR register is
being read by the Host.
This bit is set by hardware in two cases:
4
RO/CR
0b
•
FIFO Mode: The FW sets the BI bit by setting the SBI bit in the KTRIVR register (See
KT AUX registers)
•
Non FIFO Mode: the FW sets the BI bit by setting the BIA bit in the KTRxBR register
(see KT AUX registers)
3:2
1
RO
00b
0b
Reserved
Overrun Error (OE): This bit is cleared by hardware when the LSR register is
being read by the Host. The FW typically sets this bit, but it is cleared by
hardware when the host reads the LSR.
RO/CR
Data Ready (DR):
•
Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared by
hardware when the RBR register is being Read by the Host.
0
RO
0b
•
FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared by
hardware when the RBR FIFO is empty.
This bit is reset on Host System Reset or D3->D0 transition
Datasheet
209
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
7.2.11
KTMSR—KT Modem Status
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 6h
Default Value:
Access:
Size:
00h
RO, RO/CR
8 bits
The functionality of the Modem is emulated by the FW. This register provides the status
of the current state of the control lines from the modem.
Note:
Reset: Host system Reset or D3->D0 transition.
Default
Value
Bit
Access
Description
Data Carrier Detect (DCD): In Loop Back mode this bit is connected by
hardware to the value of MCR bit 3
7
6
5
4
RO
RO
RO
RO
0b
Ring Indicator (RI): In Loop Back mode this bit is connected by hardware to
the value of MCR bit 2.
0b
0b
0b
Data Set Ready (DSR): In Loop Back mode this bit is connected by hardware
to the value of MCR bit 0.
Clear To Send (CTS): In Loop Back mode this bit is connected by hardware to
the value of MCR bit 1.
Delta Data Carrier Detect (DDCD): This bit is set when bit 7 is changed. This
bit is cleared by hardware when the MSR register is being read by the HOST
driver.
3
2
RO/CR
RO/CR
0b
0b
Trailing Edge of Read Detector (TERI): This bit is set when bit 6 is changed
from 1 to 0. This bit is cleared by hardware when the MSR register is being read
by the Host driver.
Delta Data Set Ready (DDSR): This bit is set when bit 5 is changed. This bit is
cleared by hardware when the MSR register is being read by the Host driver.
1
0
RO/CR
RO/CR
0b
0b
Delta Clear To Send (DCTS): This bit is set when bit 4 is changed. This bit is
cleared by hardware when the MSR register is being read by the Host driver.
7.2.12
KTSCR—KT Scratch
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 7h
Default Value:
Access:
Size:
00h
RW
8 bits
This register has no affect on hardware. This is for the programmer to hold data
temporarily.
Note:
Reset: Host system reset or D3->D0 transition
Default
Value
Bit
Access
RW
Description
7:0
00h
Scratch Register Data (SCRD):
§ §
210
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8
Host-Secondary PCI Express*
Bridge Registers (D6:F0)
Device 6 contains the controls associated with the PCI Express root port that is the
intended attach point for external devices. In addition, it also functions as the virtual
PCI-to-PCI bridge. The table below provides an address map of the D1:F0 registers
listed by address offset in ascending order. This chapter provides a detailed bit
description of the registers.
Warning:
When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits:
Reserved and Preserved:
• Reserved for future RW implementations; software must preserve value read for
writes to bits.
• Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Note:
Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first disable the link, then program the registers, and then re-
enable the link (which will cause a full-retrain with the new settings).
Table 15.
Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 1
of 3)
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
0–1h
2–3h
4–5h
6–7h
VID1
DID1
Vendor Identification
8086h
29E9h
0000h
0010h
RO
RO
Device Identification
PCI Command
PCI Status
PCICMD1
PCISTS1
RO, RW
RO, RWC
See register
description
8h
RID1
Revision Identification
RO
9–Bh
Ch
CC1
Class Code
060400h
00h
RO
RW
CL1
Cache Line Size
Eh
HDR1
Header Type
01h
RO
18h
19h
1Ah
1Ch
1Dh
PBUSN1
SBUSN1
SUBUSN1
IOBASE1
IOLIMIT1
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
I/O Base Address
I/O Limit Address
00h
RO
00h
RW
00h
RW
F0h
RO, RW
RW, RO
00h
Datasheet
211
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Table 15.
Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 2
of 3)
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
1E–1Fh
20–21h
22–23h
24–25h
26–27h
28–2Bh
2C–2Fh
34h
SSTS1
MBASE1
MLIMIT1
PMBASE1
PMLIMIT1
Secondary Status
0000h
FFF0h
RO, RWC
RW, RO
RW, RO
RW, RO
RO, RW
RW
Memory Base Address
Memory Limit Address
0000h
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
FFF1h
0001h
PMBASEU1 Prefetchable Memory Base Address Upper
PMLIMITU1 Prefetchable Memory Limit Address Upper
00000000h
00000000h
88h
RW
CAPPTR1
Capabilities Pointer
RO
3Ch
INTRLINE1 Interrupt Line
00h
RW
3Dh
INTRPIN1
BCTRL1
Interrupt Pin
01h
RO
3E–3Fh
80–83h
Bridge Control
0000h
RO, RW
RO
PM_CAPID1 Power Management Capabilities
PM_CS1 Power Management Control/Status
C8039001h
RO, RW,
RW/P
84–87h
00000008h
88–8Bh
8C–8Fh
90–91h
92–93h
94–97h
98–99h
A0–A1h
A2–A3h
A4–A7h
A8–A9h
AA–ABh
AC–AFh
SS_CAPID Subsystem ID and Vendor ID Capabilities
SS Subsystem ID and Subsystem Vendor ID
MSI_CAPID Message Signaled Interrupts Capability ID
0000800Dh
00008086h
A005h
RO
RWO
RO
MC
MA
Message Control
Message Address
Message Data
0000h
RW, RO
RO, RW
RW
00000000h
0000h
MD
PE_CAPL
PE_CAP
DCAP
DCTL
DSTS
LCAP
PCI Express Capability List
PCI Express Capabilities
Device Capabilities
Device Control
0010h
RO
0142h
RO, RWO
RO
00008000h
0000h
RW, RO
RO, RWC
RO, RWO
Device Status
0000h
Link Capabilities
03214D02h
RO, RW,
RW/SC
B0–B1h
LCTL
Link Control
0000h
B2–hB3
B4–B7h
B8–B9h
BA–BBh
BC–BDh
C0–C3h
EC–EFh
LSTS
SLOTCAP
SLOTCTL
SLOTSTS
RCTL
Link Status
1000h
00040000h
0000h
RWC, RO
RWO, RO
RO, RW
Slot Capabilities
Slot Control
Slot Status
0000h
RO, RWC
RO, RW
Root Control
0000h
RSTS
Root Status
00000000h
00000000h
RO, RWC
RO, RW
PELC
PCI Express Legacy Control
Virtual Channel Enhanced Capability
Header
100–103h
VCECH
14010002h
RO
212
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Table 15.
Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 3
of 3)
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
104–107h
108–10Bh
10C–10Dh
110–113h
114–117h
11A–11Bh
140–143h
144–147h
150–153h
PVCCAP1
PVCCAP2
PVCCTL
VC0RCAP
VC0RCTL
VC0RSTS
RCLDECH
ESD
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
00000000h
00000000h
0000h
RO
RO
RO, RW
RO
VC0 Resource Capability
VC0 Resource Control
00000000h
800000FFh
0002h
RO, RW
RO
VC0 Resource Status
Root Complex Link Declaration Enhanced
Element Self Description
Link Entry 1 Description
00010005h
03000100h
00000000h
RO
RO, RWO
RO, RWO
LE1D
0000000000
000000h
158–15Fh
LE1A
Link Entry 1 Address
RO, RWO
8.1
VID1—Vendor Identification
B/D/F/Type:
0/6/0/PCI
Address Offset: 0–1h
Default Value:
Access:
Size:
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identify any PCI
device.
Default
Value
Bit
Access
RO
Description
15:0
8086h Vendor Identification (VID1): PCI standard identification for Intel.
Datasheet
213
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.2
DID1—Device Identification
B/D/F/Type:
0/6/0/PCI
Address Offset: 2–3h
Default Value:
Access:
Size:
29E9h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Default
Value
Bit
Access
Description
Device Identification Number (DID1(UB)): Identifier assigned to the MCH
device #6 (virtual PCI-to-PCI bridge, PCI Express port).
15:8
7:4
RO
RO
RO
29h
Device Identification Number (DID1(HW)): Identifier assigned to the MCH
device #6 (virtual PCI-to-PCI bridge, PCI Express port).
Eh
9h
Device Identification Number (DID1(LB)): Identifier assigned to the MCH
device #6 (virtual PCI-to-PCI bridge, PCI Express port).
3:0
8.3
PCICMD1—PCI Command
B/D/F/Type:
0/6/0/PCI
Address Offset: 4–5h
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:11
RO
00h
Reserved
INTA Assertion Disable (INTAAD):
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any INTA
emulation interrupts already asserted must be de-asserted when this bit is
set.
10
9
RW
0b
0b
This bit only affects interrupts generated by the device (PCI INTA from a PME
event) controlled by this command register. It does not affect upstream MSIs,
upstream PCI INTA-INTD assert and de-assert messages.
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented. Hardwired
to 0.
RO
214
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
SERR# Message Enable (SERRE1): This bit controls Device 6 SERR#
messaging. The MCH communicates the SERR# condition by sending a SERR
message to the ICH. This bit, when set, enables reporting of non-fatal and fatal
errors detected by the device to the Root Complex. Note that errors are reported
if enabled either through this bit or through the PCI-Express specific bits in the
Device Control Register.
8
RW
0b
0 = The SERR message is generated by the MCH for Device 6 only under
conditions enabled individually through the Device Control Register.
1 = The MCH is enabled to generate SERR messages which will be sent to the
ICH for specific Device 6 error conditions generated/detected on the primary
side of the virtual PCI to PCI bridge (not those received by the secondary
side). The status of SERRs generated is reported in the PCISTS1 register.
7
6
RO
RW
RO
0b
0b
0b
Reserved
Parity Error Response Enable (PERRE): Controls whether or not the Master
Data Parity Error bit in the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5:3
Reserved
Bus Master Enable (BME): Controls the ability of the PCI Express port to
forward Memory and I/O Read/Write Requests in the upstream direction.
0 = This device is prevented from making memory or IO requests to its primary
bus. Note that according to PCI Specification, as MSI interrupt messages are
in-band memory writes, disabling the bus master enable bit prevents this
device from generating MSI interrupt messages or passing them from its
secondary bus to its primary bus. Upstream memory writes/reads, IO
writes/reads, peer writes/reads, and MSIs will all be treated as illegal cycles.
Writes are forwarded to memory address C0000h with byte enables de-
asserted. Reads will be forwarded to memory address C0000h and will
return Unsupported Request status (or Master abort) in its completion
packet.
2
RW
0b
1 = This device is allowed to issue requests to its primary bus. Completions for
previously issued memory read requests on the primary bus will be issued
when the data is available.
This bit does not affect forwarding of Completions from the primary interface to
the secondary interface.
Memory Access Enable (MAE):
0 = All of device #6's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges defined in the
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
1
0
RW
RW
0b
0b
IO Access Enable (IOAE):
0 = All of device #6's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1
registers.
Datasheet
215
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.4
PCISTS1—PCI Status
B/D/F/Type:
0/6/0/PCI
Address Offset: 6–7h
Default Value:
Access:
Size:
0010h
RO, RWC
16 bits
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the MCH.
Default
Value
Bit
Access
Description
Detected Parity Error (DPE): Not Applicable or Implemented. Hardwired to 0.
Parity (generating poisoned Transaction Layer Packets) is not supported on the
primary side of this device.
15
RO
0b
Signaled System Error (SSE): This bit is set when this Device sends a SERR
due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR
Enable bit in the Command register is 1. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not affect this field).
14
RWC
0b
Received Master Abort Status (RMAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a master abort does not exist on primary side of
this device.
13
12
RO
RO
RO
RO
0b
0b
Received Target Abort Status (RTAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a target abort does not exist on primary side of
this device.
Signaled Target Abort Status (STAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a target abort does not exist on primary side of
this device.
11
0b
DEVSELB Timing (DEVT): This device is not the subtractively decoded device
on bus 0. This bit field is therefore hardwired to 00 to indicate that the device
uses the fastest possible decode.
10:9
00b
Master Data Parity Error (PMDPE): Because the primary side of the PCI
Express's virtual peer-to-peer bridge is integrated with the MCH functionality,
there is no scenario where this bit will get set. Because hardware will never set
this bit, it is impossible for software to have an opportunity to clear this bit or
otherwise test that it is implemented. The PCI specification defines it as a R/WC,
but for our implementation an RO definition behaves the same way and will meet
all Microsoft testing requirements.
8
RO
0b
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
7
6
RO
RO
0b
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60MHz capability (CAP66): Not Applicable or Implemented. Hardwired to
0.
5
4
RO
RO
0b
1b
Capabilities List (CAPL): Indicates that a capabilities list is present. Hardwired
to 1.
INTA Status (INTAS): Indicates that an interrupt message is pending
internally to the device. Only PME sources feed into this status bit (not PCI INTA-
INTD assert and de-assert messages). The INTA Assertion Disable bit,
PCICMD1[10], has no effect on this bit.
3
RO
RO
0b
2:0
000b
Reserved
216
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.5
RID1—Revision Identification
B/D/F/Type:
0/6/0/PCI
Address Offset: 8h
Default Value:
Access:
Size:
see table below
RO
8 bits
This register contains the revision number of the MCH device 6. These bits are read
only and writes to this register have no effect.
Default
Value
Bit
Access
Description
Revision Identification Number (RID1): This is an 8-bit value that
indicates the revision identification number for the MCH Device 0. Refer to the
Intel® X38 Express Chipset Specification Update for the value of this register.
see
description
7:0
RO
8.6
CC1—Class Code
B/D/F/Type:
0/6/0/PCI
Address Offset: 9–Bh
Default Value:
Access:
Size:
060400h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
Default
Value
Bit
Access
Description
Base Class Code (BCC): Indicates the base class code for this device. This
code has the value 06h, indicating a Bridge device.
23:16
15:8
RO
RO
06h
Sub-Class Code (SUBCC): Indicates the sub-class code for this device. The
code is 04h indicating a PCI to PCI Bridge.
04h
00h
Programming Interface (PI): Indicates the programming interface of this
device. This value does not specify a particular register set layout and provides
no practical use for this device.
7:0
RO
Datasheet
217
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.7
CL1—Cache Line Size
B/D/F/Type:
0/6/0/PCI
Address Offset: Ch
Default Value:
Access:
Size:
00h
RW
8 bits
Default
Value
Bit
Access
Description
Cache Line Size (Scratch pad): Implemented by PCI Express devices as a
read-write field for legacy compatibility purposes but has no impact on any PCI
Express device functionality.
7:0
RW
00h
8.8
HDR1—Header Type
B/D/F/Type:
0/6/0/PCI
Address Offset: Eh
Default Value:
Access:
Size:
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Default
Value
Bit
Access
Description
Header Type Register (HDR): Returns 01h to indicate that this is a single
function device with bridge header layout.
7:0
RO
01h
8.9
PBUSN1—Primary Bus Number
B/D/F/Type:
0/6/0/PCI
Address Offset: 18h
Default Value:
Access:
Size:
00h
RO
8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
Default
Value
Bit
Access
Description
Primary Bus Number (BUSN): Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device
#6 is an internal device and its primary bus is always 0, these bits are read only
and are hardwired to 0.
7:0
RO
00h
218
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
0/6/0/PCI
Address Offset: 19h
Default Value:
Access:
Size:
00h
RW
8 bits
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge. This number is programmed by the PCI configuration software to allow mapping
of configuration cycles to PCI Express.
Default
Value
Bit
Access
Description
Secondary Bus Number (BUSN): This field is programmed by configuration
software with the bus number assigned to PCI Express.
7:0
RW
00h
8.11
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
0/6/0/PCI
Address Offset: 1Ah
Default Value:
Access:
Size:
00h
RW
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express.
Default
Value
Bit
Access
Description
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device #6 bridge. When only a single PCI device resides on the PCI
Express segment, this register will contain the same value as the SBUSN1
register.
7:0
RW
00h
Datasheet
219
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.12
IOBASE1—I/O Base Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 1Ch
Default Value:
Access:
Size:
F0h
RO, RW
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
Default
Value
Bit
Access
Description
I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O
addresses passed by bridge 1 to PCI Express.
7:4
3:0
RW
RO
Fh
0h
Reserved
8.13
IOLIMIT1—I/O Limit Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 1Dh
Default Value:
Access:
Size:
00h
RW, RO
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
Default
Value
Bit
Access
Description
I/O Address Limit (IOLIMIT): Corresponds to A[15:12] of the I/O address
limit of device #6. Devices between this upper limit and IOBASE1 will be passed
to the PCI Express hierarchy associated with this device.
7:4
3:0
RW
RO
0h
0h
Reserved
220
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.14
SSTS1—Secondary Status
B/D/F/Type:
0/6/0/PCI
Address Offset: 1E–1Fh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.
Default
Value
Bit
Access
Description
Detected Parity Error (DPE): This bit is set by the Secondary Side for a Type 1
Configuration Space header device whenever it receives a Poisoned Transaction
Layer Packet, regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
15
RWC
RWC
RWC
0b
Received System Error (RSE): This bit is set when the Secondary Side for a
Type 1 configuration space header device receives an ERR_FATAL or
ERR_NONFATAL.
14
13
0b
0b
Received Master Abort (RMA): This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Unsupported Request
Completion Status.
Received Target Abort (RTA): This bit is set when the Secondary Side for
Type 1 Configuration Space Header Device (for requests initiated by the Type 1
Header Device itself) receives a Completion with Completer Abort Completion
Status.
12
RWC
0b
Signaled Target Abort (STA): Not Applicable or Implemented. Hardwired to 0.
The MCH does not generate Target Aborts (the MCH will never complete a
request using the Completer Abort Completion status).
11
RO
RO
0b
10:9
00b
DEVSELB Timing (DEVT): Not Applicable or Implemented. Hardwired to 0.
Master Data Parity Error (SMDPE): When set, indicates that the MCH
received across the link (upstream) a Read Data Completion Poisoned
Transaction Layer Packet (EP=1). This bit can only be set when the Parity Error
Enable bit in the Bridge Control register is set.
8
RWC
0b
7
6
RO
RO
0b
0b
Fast Back-to-Back (FB2B): Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66): Not Applicable or Implemented. Hardwired to
0.
5
RO
RO
0b
4:0
00h
Reserved
Datasheet
221
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.15
MBASE1—Memory Base Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 20–21h
Default Value:
Access:
Size:
FFF0h
RW, RO
16 bits
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
Default
Value
Bit
Access
Description
Memory Address Base (MBASE): Corresponds to A[31:20] of the lower limit
of the memory range that will be passed to PCI Express.
15:4
3:0
RW
RO
FFFh
0h
Reserved
222
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.16
MLIMIT1—Memory Limit Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 22–23h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode, address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB
aligned memory block.
Note:
Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express address ranges (typically where control/status memory-
mapped I/O data structures of the controller will reside) and PMBASE and PMLIMIT are
used to map prefetchable address ranges (typically device local memory). This
segregation allows application of USWC space attribute to be performed in a true plug-
and-play manner to the prefetchable address range for improved processor- PCI
Express memory access performance.
Note:
Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges
(i.e., prevent overlap with each other and/or with the ranges covered with the main
memory). There is no provision in the MCH hardware to enforce prevention of overlap
and operations of the system in the case of overlap are not ensured.
Default
Value
Bit
Access
Description
Memory Address Limit (MLIMIT): Corresponds to A[31:20] of the upper limit
of the address range passed to PCI Express.
15:4
3:0
RW
RO
000h
0h
Reserved
Datasheet
223
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.17
PMBASE1—Prefetchable Memory Base Address
Upper
B/D/F/Type:
0/6/0/PCI
Address Offset: 24–25h
Default Value:
Access:
Size:
FFF1h
RW, RO
16 bits
This register in conjunction with the corresponding Upper Base Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
Default
Value
Bit
Access
Description
Prefetchable Memory Base Address (MBASE): Corresponds to A[31:20] of
the lower limit of the memory range that will be passed to PCI Express.
15:4
RW
RO
FFFh
64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region base address are contained in the Prefetchable Memory base
Upper Address register at 28h.
3:0
1h
224
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.18
PMLIMIT1—Prefetchable Memory Limit Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 26–27h
Default Value:
Access:
Size:
0001h
RO, RW
16 bits
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Default
Value
Bit
Access
Description
Prefetchable Memory Address Limit (PMLIMIT): Corresponds to A[31:20]
of the upper limit of the address range passed to PCI Express.
15:4
RW
RO
000h
64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region limit address are contained in the Prefetchable Memory Base
Limit Address register at 2Ch
3:0
1h
Datasheet
225
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.19
PMBASEU1—Prefetchable Memory Base Address
Upper
B/D/F/Type:
0/6/0/PCI
Address Offset: 28–2Bh
Default Value:
Access:
Size:
00000000h
RW
32 bits
The functionality associated with this register is present in the PCI Express design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
Default
Value
Bit
Access
Description
Prefetchable Memory Base Address (MBASEU): Corresponds to A[63:32] of
the lower limit of the prefetchable memory range that will be passed to PCI
Express.
0000000
0h
31:0
RW
226
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.20
PMLIMITU1—Prefetchable Memory Limit Address
Upper
B/D/F/Type:
0/6/0/PCI
Address Offset: 2C–2Fh
Default Value:
Access:
Size:
00000000h
RW
32 bits
The functionality associated with this register is present in the PCI Express design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the
ones that can be designated as a USWC (i.e., prefetchable) from the processor
perspective.
Default
Value
Bit
Access
Description
Prefetchable Memory Address Limit (MLIMITU): This field corresponds to
A[63:32] of the upper limit of the prefetchable Memory range that will be passed
to PCI Express.
0000000
0h
31:0
RW
Datasheet
227
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
0/6/0/PCI
Address Offset: 34h
Default Value:
Access:
Size:
88h
RO
8 bits
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Default
Value
Bit
Access
Description
First Capability (CAPPTR1): The first capability in the list is the Subsystem ID
and Subsystem Vendor ID Capability.
7:0
RO
88h
8.22
INTRLINE1—Interrupt Line
B/D/F/Type:
0/6/0/PCI
Address Offset: 3Ch
Default Value:
Access:
Size:
00h
RW
8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Default
Value
Bit
Access
Description
Interrupt Connection (INTCON): Used to communicate interrupt line routing
information.
7:0
RW
00h
8.23
INTRPIN1—Interrupt Pin
B/D/F/Type:
0/6/0/PCI
Address Offset: 3Dh
Default Value:
Access:
Size:
01h
RO
8 bits
This register specifies which interrupt pin this device uses.
Default
Value
Bit
Access
Description
Interrupt Pin (INTPIN): As a single function device, the PCI Express device
specifies INTA as its interrupt pin. 01h=INTA.
7:0
RO
01h
228
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.24
BCTRL1—Bridge Control
B/D/F/Type:
0/6/0/PCI
Address Offset: 3E–3Fh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface as well as
some bits that affect the overall behavior of the "virtual" Host-PCI Express bridge
embedded within MCH.
Default
Value
Bit
Access
Description
15:12
11
RO
RO
0h
Reserved
Discard Timer SERR# Enable (DTSERRE): Not Applicable or Implemented.
Hardwired to 0.
0b
0b
0b
0b
0b
Discard Timer Status (DTSTS): Not Applicable or Implemented. Hardwired to
0.
10
9
RO
RO
RO
RO
Secondary Discard Timer (SDT): Not Applicable or Implemented. Hardwired
to 0.
Primary Discard Timer (PDT): Not Applicable or Implemented. Hardwired to
0.
8
Fast Back-to-Back Enable (FB2BEN): Not Applicable or Implemented.
Hardwired to 0.
7
Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the
corresponding PCI Express Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
6
5
RW
RO
0b
0b
Master Abort Mode (MAMODE): Does not apply to PCI Express. Hardwired to
0.
VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI bridge to provide 16-
bit decoding of VGA I/O address precluding the decoding of alias addresses
every 1 KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also
set to 1, enabling VGA I/O decoding and forwarding by the bridge.
4
3
RW
RW
0b
0b
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
VGA Enable (VGAEN): Controls the routing of processor initiated transactions
targeting VGA compatible I/O and memory address ranges. See the VGAEN/
MDAP table in device 0, offset 97h[0].
ISA Enable (ISAEN): Needed to exclude legacy resource decode to route ISA
resources to legacy decode path. Modifies the response by the MCH to an I/O
access issued by the processor that target ISA I/O addresses. This applies only
to I/O addresses that are enabled by the IOBASE and IOLIMIT registers.
2
RW
0b
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express.
1 = MCH will not forward to PCI Express any I/O transactions addressing the last
768 bytes in each 1 KB block even if the addresses are within the range
defined by the IOBASE and IOLIMIT registers.
Datasheet
229
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
SERR Enable (SERREN):
0 = No forwarding of error messages from secondary side to primary side that
could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
1
RW
0b
0b
Parity Error Response Enable (PEREN): Controls whether or not the Master
Data Parity Error bit in the Secondary Status register is set when the MCH
receives across the link (upstream) a Read Data Completion Poisoned
Transaction Layer Packet.
0
RW
0 = Master Data Parity Error bit in Secondary Status register can NOT be set.
1 = Master Data Parity Error bit in Secondary Status register CAN be set.
8.25
PM_CAPID1—Power Management Capabilities
B/D/F/Type:
0/6/0/PCI
Address Offset: 80–83h
Default Value:
Access:
Size:
C8039001h
RO
32 bits
Default
Value
Bit
Access
Description
PME Support (PMES): This field indicates the power states in which this device
may indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This
device is not required to do anything to support D3hot and D3cold, it simply
must report that those states are supported. Refer to the PCI Power
Management 1.1 specification for encoding explanation and other power
management details.
31:27
RO
19h
D2 Power State Support (D2PSS): Hardwired to 0 to indicate that the D2
power management state is NOT supported.
26
25
RO
RO
RO
0b
0b
D1 Power State Support (D1PSS): Hardwired to 0 to indicate that the D1
power management state is NOT supported.
Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are no
3.3Vaux auxiliary current requirements.
24:22
000b
Device Specific Initialization (DSI): Hardwired to 0 to indicate that special
initialization of this device is NOT required before generic class device driver is to
use it.
21
RO
0b
20
19
RO
RO
0b
0b
Auxiliary Power Source (APS): Hardwired to 0.
PME Clock (PMECLK): Hardwired to 0 to indicate this device does NOT support
PMEB generation.
PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this function
complies with revision 1.2 of the PCI Power Management Interface Specification.
18:16
15:8
7:0
RO
RO
RO
011b
90h
Pointer to Next Capability (PNC): This contains a pointer to the next item in
the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI) capability at 90h.
Capability ID (CID): Value of 01h identifies this linked list item (capability
structure) as being for PCI Power Management registers.
01h
230
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.26
PM_CS1—Power Management Control/Status
B/D/F/Type:
0/6/0/PCI
Address Offset: 84–87h
Default Value:
Access:
Size:
00000008h
RO, RW, RW/P
32 bits
Default
Value
Bit
Access
Description
31:16
15
RO
RO
0000h Reserved
PME Status (PMESTS): Indicates that this device does not support PMEB
0b
00b
0h
generation from D3cold.
Data Scale (DSCALE): Indicates that this device does not support the power
14:13
12:9
RO
RO
management data register.
Data Select (DSEL): Indicates that this device does not support the power
management data register.
PME Enable (PMEE): Indicates that this device does not generate PMEB
assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
8
RW/P
RO
0b
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:2
0000b Reserved
Power State (PS): Indicates the current power state of this device and can be
used to set the device into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The device
must return to the D0 state in order to be fully-functional.
1:0
RW
00b
When the Power State is other than D0, the bridge will Master Abort (i.e. not
claim) any downstream cycles (with exception of type 0 config cycles).
Consequently, these unclaimed cycles will go down DMI and come back up as
Unsupported Requests, which the MCH logs as Master Aborts in Device 0
PCISTS[13]
There is no additional hardware functionality required to support these Power
States.
Datasheet
231
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.27
SS_CAPID—Subsystem ID and Vendor ID
Capabilities
B/D/F/Type:
0/6/0/PCI
Address Offset: 88–8Bh
Default Value:
Access:
Size:
0000800Dh
RO
32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides.
Because this device is an integrated part of the system and not an add-in device, it is
anticipated that this capability will never be used. However, it is necessary because
Microsoft will test for its presence.
Default
Value
Bit
Access
Description
31:16
15:8
RO
RO
0000h Reserved
Pointer to Next Capability (PNC): This contains a pointer to the next item in
80h
0Dh
the capabilities list which is the PCI Power Management capability.
Capability ID (CID): Value of 0Dh identifies this linked list item (capability
7:0
RO
structure) as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
8.28
SS—Subsystem ID and Subsystem Vendor ID
B/D/F/Type:
0/6/0/PCI
Address Offset: 8C–8Fh
Default Value:
Access:
Size:
00008086h
RWO
32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These
values must be preserved through power management transitions and a hardware
reset.
Default
Value
Bit
Access
Description
Subsystem ID (SSID): Identifies the particular subsystem and is assigned by
the vendor.
31:16
RWO
RWO
0000h
Subsystem Vendor ID (SSVID): Identifies the manufacturer of the subsystem
8086h and is the same as the vendor ID which is assigned by the PCI Special Interest
Group.
15:0
232
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.29
MSI_CAPID—Message Signaled Interrupts
Capability ID
B/D/F/Type:
0/6/0/PCI
Address Offset: 90–91h
Default Value:
Access:
Size:
A005h
RO
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This contains a pointer to the next item in
the capabilities list which is the PCI Express capability.
15:8
7:0
RO
RO
A0h
Capability ID (CID): Value of 05h identifies this linked list item (capability
structure) as being for MSI registers.
05h
8.30
MC—Message Control
B/D/F/Type:
0/6/0/PCI
Address Offset: 92–93h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
Default
Value
Bit
Access
Description
15:8
RO
RO
00h
Reserved
64-bit Address Capable (64AC): Hardwired to 0 to indicate that the function
does not implement the upper 32 bits of the Message Address register and is
incapable of generating a 64-bit memory address.
7
0b
Multiple Message Enable (MME): System software programs this field to
indicate the actual number of messages allocated to this device. This number
will be equal to or less than the number actually requested.
6:4
RW
RO
RW
000b
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC): System software reads this field to
determine the number of messages being requested by this device. The value of
000b equates to 1 message requested.
3:1
0
000b
0b
000 = 1 message requested
All other encodings are reserved.
MSI Enable (MSIEN): Controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME messages. INTA will not be
generated and INTA Status (PCISTS1[3]) will not be set.
Datasheet
233
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.31
MA—Message Address
B/D/F/Type:
0/6/0/PCI
Address Offset: 94–97h
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
Default
Value
Bit
Access
Description
Message Address (MA): Used by system software to assign an MSI address to
the device. The device handles an MSI by writing the padded contents of the MD
register to this address.
0000000
0h
31:2
1:0
RW
RO
Force DWord Align (FDWA): Hardwired to 0 so that addresses assigned by
system software are always aligned on a DWord address boundary.
00b
8.32
MD—Message Data
B/D/F/Type:
0/6/0/PCI
Address Offset: 98–99h
Default Value:
Access:
Size:
0000h
RW
16 bits
Default
Value
Bit
Access
Description
Message Data (MD): Base message data pattern assigned by system software
and used to handle an MSI from the device.
15:0
RW
0000h
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16-bits are always
set to 0. The lower 16-bits are supplied by this register.
8.33
PE_CAPL—PCI Express* Capability List
B/D/F/Type:
0/6/0/PCI
Address Offset: A0–A1h
Default Value:
Access:
Size:
0010h
RO
16 bits
This register enumerates the PCI Express capability structure.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This value terminates the capabilities list.
The Virtual Channel capability and any other PCI Express specific capabilities
that are reported via this mechanism are in a separate capabilities list located
entirely within PCI Express Extended Configuration Space.
15:8
7:0
RO
RO
00h
Capability ID (CID): Identifies this linked list item (capability structure) as
being for PCI Express registers.
10h
234
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.34
PE_CAP—PCI Express* Capabilities
B/D/F/Type:
0/6/0/PCI
Address Offset: A2–A3h
Default Value:
Access:
Size:
0142h
RO, RWO
16 bits
This register indicates PCI Express device capabilities.
Default
Value
Bit
Access
Description
15:14
13:9
RO
RO
00b
Reserved
Interrupt Message Number (IMN): Not Applicable or Implemented.
Hardwired to 0.
00h
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is connected to an integrated
component or is disabled.
8
RWO
1b
1 = The PCI Express Link associated with this port is connected to a slot.
Device/Port Type (DPT): Hardwired to 4h to indicate root port of PCI Express
Root Complex.
7:4
3:0
RO
RO
4h
2h
PCI Express Capability Version (PCIECV): Hardwired to 2h to indicate
compliance to the PCI Express Capabilities Register Expansion ECN.
8.35
DCAP—Device Capabilities
B/D/F/Type:
0/6/0/PCI
Address Offset: A4–A7h
Default Value:
Access:
Size:
00008000h
RO
32 bits
This register indicates PCI Express device capabilities.
Default
Value
Bit
Access
Description
31:16
RO
RO
0000h Reserved
Role Based Error Reporting (RBER): This bit indicates that this device
implements the functionality defined in the Error Reporting ECN as required by
the PCI Express 1.1 specification.
15
1b
14:6
5
RO
RO
000h
0b
Reserved
Extended Tag Field Supported (ETFS): Hardwired to indicate support for 5-
bit Tags as a Requestor.
Phantom Functions Supported (PFS): Not Applicable or Implemented.
Hardwired to 0.
4:3
2:0
RO
RO
00b
Max Payload Size (MPS): Hardwired to indicate 128B max supported payload
for Transaction Layer Packets (TLP).
000b
Datasheet
235
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.36
DCTL—Device Control
B/D/F/Type:
0/6/0/PCI
Address Offset: A8–A9h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Default
Value
Bit
Access
Description
15:8
RO
0h
Reserved
Max Payload Size (MPS):
000 = 128B max supported payload for Transaction Layer Packets (TLP). As a
receiver, the Device must handle TLPs as large as the set value; as
transmitter, the Device must not generate TLPs exceeding the set value.
7:5
RW
000b
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to support compliance
testing.
4
3
RO
0b
0b
Reserved
Unsupported Request Reporting Enable (URRE): When set, this bit allows
signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the Root Control register
when detecting an unmasked Unsupported Request (UR). An ERR_CORR is
signaled when an unmasked Advisory Non-Fatal UR is received. An ERR_FATAL
or ERR_NONFATAL is sent to the Root Control register when an uncorrectable
non-Advisory UR is received with the severity bit set in the Uncorrectable Error
Severity register.
RW
Fatal Error Reporting Enable (FERE): When set, this bit enables signaling of
ERR_FATAL to the Root Control register due to internally detected errors or error
messages received across the link. Other bits also control the full scope of
related error reporting.
2
1
0
RW
RW
RW
0b
0b
0b
Non-Fatal Error Reporting Enable (NERE): When set, this bit enables
signaling of ERR_NONFATAL to the Rool Control register due to internally
detected errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
Correctable Error Reporting Enable (CERE): When set, this bit enables
signaling of ERR_CORR to the Root Control register due to internally detected
errors or error messages received across the link. Other bits also control the full
scope of related error reporting.
236
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.37
DSTS—Device Status
B/D/F/Type:
0/6/0/PCI
Address Offset: AA–ABh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
Default
Value
Bit
Access
Description
15:6
RO
RO
RO
000h
Reserved
Transactions Pending (TP):
0 = All pending transactions (including completions for any outstanding non-
posted requests on any used virtual channel) have been completed.
1 = Indicates that the device has transaction(s) pending (including completions
for any outstanding non-posted requests for all used Traffic Classes).
5
4
0b
0b
Reserved
Unsupported Request Detected (URD): When set, this bit indicates that the
Device received an Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
Register.
3
RWC
0b
Additionally, the Non-Fatal Error Detected bit or the Fatal Error Detected bit is
set according to the setting of the Unsupported Request Error Severity bit. In
production systems setting the Fatal Error Detected bit is not an option as
support for AER will not be reported.
Fatal Error Detected (FED): When set, this bit indicates that fatal error(s)
were detected. Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register. When Advanced Error
Handling is enabled, errors are logged in this register regardless of the settings
of the uncorrectable error mask register.
2
1
0
RWC
RWC
RWC
0b
0b
0b
Non-Fatal Error Detected (NFED): When set, this bit indicates that non-fatal
error(s) were detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register
regardless of the settings of the uncorrectable error mask register.
Correctable Error Detected (CED): When set, this bit indicates that
correctable error(s) were detected. Errors are logged in this register regardless
of whether error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this register
regardless of the settings of the correctable error mask register.
Datasheet
237
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.38
LCAP—Link Capabilities
B/D/F/Type:
0/6/0/PCI
Address Offset: AC–AFh
Default Value:
Access:
Size:
03214D02h
RO, RWO
32 bits
This register indicates PCI Express device specific capabilities.
Default
Value
Bit
Access
Description
Port Number (PN): This field indicates the PCI Express port number for the
given PCI Express link. Matches the value in Element Self Description[31:24].
31:24
23:22
RO
RO
03h
000b
Reserved
Link Bandwidth Notification Capability: A value of 1b indicates support for
the Link Bandwidth Notification status and interrupt mechanisms. This capability
is required for all Root Ports and Switch downstream ports supporting Links
wider than x1 and/or multiple Link speeds.
21
RO
1b
This field is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
Data Link Layer Link Active Reporting Capable (DLLLARC): For a
Downstream Port, this bit must be set to 1b if the component supports the
optional capability of reporting the DL_Active state of the Data Link Control and
Management State Machine.
20
19
RO
RO
0b
0b
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
Surprise Down Error Reporting Capable (SDERC): For a Downstream Port,
this bit must be set to 1b if the component supports the optional capability of
detecting and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this optional capability,
this bit must be hardwired to 0b.
Clock Power Management (CPM): A value of 1b in this bit indicates that the
component tolerates the removal of any reference clock(s) when the link is in
the L1 and L2/3 Ready link states. A value of 0b indicates the component does
not have this capability and that reference clock(s) must not be removed in
these link states.
18
RO
0b
This capability is applicable only in form factors that support "clock request"
(CLKREQ#) capability.
For a multi-function device, each function indicates its capability independently.
Power Management configuration software must only permit reference clock
removal if all functions of the multifunction device indicate a 1b in this bit.
L1 Exit Latency (L1ELAT): Indicates the length of time this Port requires to
complete the transition from L1 to L0. The value 010 b indicates the range of 2
us to less than 4 us.
17:15
RWO
010b
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.
238
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
L0s Exit Latency (L0SELAT): Indicates the length of time this Port requires to
complete the transition from L0s to L0.
000 = Less than 64 ns
001 = 64ns to less than 128ns
010 = 128ns to less than 256 ns
011 = 256ns to less than 512ns
100 = 512ns to less than 1us
101 = 1 us to less than 2 us
110 = 2 us – 4 us
14:12
RO
100b
111 = More than 4 us
Active State Link PM Support (ASLPMS): : The MCH supports ASPM L0s and
L1.
11:10
9:4
RWO
RO
11b
10h
Max Link Width (MLW): Indicates the maximum number of lanes supported
for this link.
10h = x16
Max Link Speed (MLS): Supported Link Speed - This field indicates the
supported Link speed(s) of the associated Port.
0001b = 2.5GT/s Link speed supported
0010b = 5.0GT/s and 2.5GT/s Link speeds supported
All other encodings are reserved.
3:0
RO
2h
Datasheet
239
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.39
LCTL—Link Control
B/D/F/Type:
0/6/0/PCI
Address Offset: B0–B1h
Default Value:
Access:
Size:
0000h
RO, RW, RW/SC
16 bits
This register allows control of PCI Express link.
Default
Value
Bit
Access
Description
15:12
RO
0000000b Reserved
Link Autonomous Bandwidth Interrupt Enable: When Set, this bit enables
the generation of an interrupt to indicate that the Link Autonomous Bandwidth
Status bit has been set.
11
RW
0b
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
Link Bandwidth Management Interrupt Enable: When Set, this bit enables
the generation of an interrupt to indicate that the Link Bandwidth Management
Status bit has been set.
10
RW
R0
0b
0b
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Hardware Autonomous Width Disable: When Set, this bit disables
hardware from changing the Link width for reasons other than attempting to
correct unreliable Link operation by reducing Link width.
9
Devices that do not implement the ability autonomously to change Link width
are permitted to hardwire this bit to 0b.
The MCH does not support autonomous width change. So, this bit is "RO".
Enable Clock Power Management (ECPM): Applicable only for form factors
that support a "Clock Request" (CLKREQ#) mechanism, this enable functions
as follows:
0 = Clock power management is disabled and device must hold CLKREQ#
signal low
1 = The device is permitted to use CLKREQ# signal to power manage link clock
according to protocol defined in appropriate form factor specification.
8
RO
0b
Default value of this field is 0b.
Components that do not support Clock Power Management (as indicated by a
0b value in the Clock Power Management bit of the Link Capabilities Register)
must hardwire this bit to 0b.
Extended Synch (ES):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the L0s
state and when in the Recovery state.
7
RW
0b
This mode provides external devices (e.g., logic analyzers) monitoring the Link
time to achieve bit and symbol lock before the link enters L0 and resumes
communication.
This is a test mode only and may cause other undesired side effects such as
buffer overflows or underruns.
240
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
Common Clock Configuration (CCC):
0 = Indicates that this component and the component at the opposite end of
this Link are operating with asynchronous reference clock.
6
RW
0b
1 = Indicates that this component and the component at the opposite end of
this Link are operating with a distributed common reference clock.
The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and
the N_FTS value advertised during link training.
Retrain Link (RL):
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from
L0, L0s, or L1 states to the Recovery state.
This bit always returns 0 when read.
5
RW/SC
0b
This bit is cleared automatically (no need to write a 0).
It is permitted to write 1b to this bit while simultaneously writing modified
values to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the
LTSSM is already in Recovery or Configuration, the modified values are not
required to affect the Link training that's already in progress.
Link Disable (LD):
0 = Normal operation.
1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via
Recovery) from L0, L0s, or L1 states. Link retraining happens
automatically on 0 to 1 transition, just like when coming out of reset.
4
RW
0b
Writes to this bit are immediately reflected in the value read from the bit,
regardless of actual Link state.
3
2
RO
0b
0b
Read Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte.
RW
Reserved
Active State PM (ASPM): Controls the level of active state power
management supported on the given link.
00 = Disabled
1:0
RW
00b
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
Datasheet
241
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.40
LSTS—Link Status
B/D/F/Type:
0/6/0/PCI
Address Offset: B2–B3h
Default Value:
Access:
Size:
1000h
RWC, RO
16 bits
This register indicates PCI Express link status.
Default
Value
Bit
Access
Description
Link Autonomous Bandwidth Status (LABWS): This bit is set to 1b by
hardware to indicate that hardware has autonomously changed link speed or
width, without the port transitioning through DL_Down status, for reasons other
than to attempt to correct unreliable link operation.
15
RWC
0b
This bit must be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was indicated as an autonomous
change.
Link Bandwidth Management Status (LBWMS): This bit is set to 1b by
hardware to indicate that either of the following has occurred without the port
transitioning through DL_Down status:
A link retraining initiated by a write of 1b to the Retrain Link bit has completed.
NOTE: This bit is Set following any write of 1b to the Retrain Link bit, including
when the Link is in the process of retraining for some other reason.
14
RWC
0b
Hardware has autonomously changed link speed or width to attempt to correct
unreliable link operation, either through an LTSSM timeout or a higher level
process
This bit must be set if the Physical Layer reports a speed or width change was
initiated by the downstream component that was not indicated as an
autonomous change.
Data Link Layer Link Active (Optional) (DLLLA): This bit indicates the
status of the Data Link Control and Management State Machine. It returns a 1b
to indicate the DL_Active state, 0b otherwise.
13
12
RO
RO
0b
1b
This bit must be implemented if the corresponding Data Link Layer Active
Capability bit is implemented. Otherwise, this bit must be hardwired to 0b.
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of the presence of a
reference on the connector.
1 = The device uses the same physical reference clock that the platform
provides on the connector.
Link Training (LTRN): This bit indicates that the Physical Layer LTSSM is in the
Configuration or Recovery state, or that 1b was written to the Retrain Link bit
but Link training has not yet begun. Hardware clears this bit when the LTSSM
exits the Configuration/Recovery state once Link training is complete.
11
10
RO
RO
0b
0b
Undefined: The value read from this bit is undefined. In previous versions of
this specification, this bit was used to indicate a Link Training Error. System
software must ignore the value read from this bit. System software is permitted
to write any value to this bit.
242
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
Negotiated Link Width (NLW): Indicates negotiated link width. This field is
valid only when the link is in the L0, L0s, or L1 states (after link width
negotiation is successfully completed).
01h = x1
04h = ‘x4 — This is not a supported PCIe Gen2.0 link width. Link width x4 is only
valid when PCIe Gen1.1 I/O card is used in the secondary port.
9:4
RO
00h
08h = x8 — This is not a supported PCIe Gen2.0 link width. Link width x8 is only
valid when PCIe Gen1.1 I/O card is used in the secondary port.
10h = x16
All other encodings are reserved.
Current Link Speed (CLS): This field indicates the negotiated Link speed of the
given PCI Express Link.
Defined encodings are:
3:0
RO
0h
0001b = 5.0 GT/s PCI Express Link
0010b = 5 GT/s PCI Express Link
All other encodings are reserved. The value in this field is undefined when the
Link is not up.
8.41
SLOTCAP—Slot Capabilities
B/D/F/Type:
0/6/0/PCI
Address Offset: B4–B7h
Default Value:
Access:
Size:
00040000h
RWO, RO
32 bits
PCI Express Slot related registers.
Default
Value
Bit
Access
Description
Physical Slot Number (PSN): Indicates the physical slot number attached to
this Port.
31:19
18
RWO
RO
0000h
1b
Reserved
Electromechanical Interlock Present (EIP): When set to 1b, this bit
indicates that an Electromechanical Interlock is implemented on the chassis for
this slot.
17
RO
0b
Slot Power Limit Scale (SPLS): Specifies the scale used for the Slot Power
Limit Value.
00 = 1.0x
01 = 0.1x
16:15
RWO
00b
10 = 0.01x
11 = 0.001x
If this field is written, the link sends a Set_Slot_Power_Limit message.
Slot Power Limit Value (SPLV): In combination with the Slot Power Limit
Scale value, specifies the upper limit on power supplied by slot. Power limit (in
Watts) is calculated by multiplying the value in this field by the value in the Slot
Power Limit Scale field.
14:7
RWO
00h
If this field is written, the link sends a Set_Slot_Power_Limit message.
Datasheet
243
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
6:5
4
RO
RO
00b
0b
Reserved
Power Indicator Present (PIP): When set to 1b, this bit indicates that a
Power Indicator is electrically controlled by the chassis for this slot.
Attention Indicator Present (AIP): When set to 1b, this bit indicates that an
Attention Indicator is electrically controlled by the chassis.
3
2
RO
RO
0b
0b
MRL Sensor Present (MSP): When set to 1b, this bit indicates that an MRL
Sensor is implemented on the chassis for this slot.
Power Controller Present (PCP): When set to 1b, this bit indicates that a
software programmable Power Controller is implemented for this slot/adapter
(depending on form factor).
1
0
RO
RO
0b
0b
Attention Button Present (ABP): When set to 1b, this bit indicates that an
Attention Button for this slot is electrically controlled by the chassis.
8.42
SLOTCTL—Slot Control
B/D/F/Type:
0/6/0/PCI
Address Offset: B8–B9h
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
PCI Express Slot related registers.
Default
Value
Bit
Access
Description
15:13
RO
000b
Reserved
Data Link Layer State Changed Enable (DLLSCE): If the Data Link Layer
Link Active capability is implemented, when set to 1b, this field enables software
notification when Data Link Layer Link Active field is changed.
12
11
RO
0b
0b
If the Data Link Layer Link Active capability is not implemented, this bit is
permitted to be read-only with a value of 0b.
Electromechanical Interlock Control (EIC): If an Electromechanical
Interlock is implemented, a write of 1b to this field causes the state of the
interlock to toggle. A write of 0b to this field has no effect. A read to this register
always returns a 0.
RO
Power Controller Control (PCC): If a Power Controller is implemented, this
field when written sets the power state of the slot per the defined encodings.
Reads of this field must reflect the value from the latest write, unless software
issues a write without waiting for the previous command to complete in which
case the read value is undefined.
Depending on the form factor, the power is turned on/off either to the slot or
within the adapter. Note that in some cases the power controller may
autonomously remove slot power or not respond to a power-up request based on
a detected fault condition, independent of the Power Controller Control setting.
10
RO
0b
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities register is set
to 0b, then writes to this field have no effect and the read value of this field is
undefined.
244
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
Default
Value
Bit
Access
Description
Power Indicator Control (PIC): If a Power Indicator is implemented, writes to
this field set the Power Indicator to the written state. Reads of this field must
reflect the value from the latest write, unless software issues a write without
waiting for the previous command to complete in which case the read value is
undefined.
00 = Reserved
01 = On
9:8
RO
00b
10 = Blink
11 = Off
If the Power Indicator Present bit in the Slot Capabilities register is 0b, this field
is permitted to be read-only with a value of 00b.
Attention Indicator Control (AIC): If an Attention Indicator is implemented,
writes to this field set the Attention Indicator to the written state.
Reads of this field must reflect the value from the latest write, unless software
issues a write without waiting for the previous command to complete in which
case the read value is undefined. If the indicator is electrically controlled by
chassis, the indicator is controlled directly by the downstream port through
implementation specific mechanisms.
7:6
RO
00b
00 = Reserved
01 = On
10 = Blink
11 = Off
If the Attention Indicator Present bit in the Slot Capabilities register is 0b, this
field is permitted to be read only with a value of 00b.
5:4
3
RO
00b
0b
Reserved
Presence Detect Changed Enable (PDCE): When set to 1b, this bit enables
software notification on a presence detect changed event.
RW
MRL Sensor Changed Enable (MSCE): When set to 1b, this bit enables
software notification on a MRL sensor changed event.
2
RO
0b
Default value of this field is 0b. If the MRL Sensor Present field in the Slot
Capabilities register is set to 0b, this bit is permitted to be read-only with a value
of 0b.
Power Fault Detected Enable (PFDE): When set to 1b, this bit enables
software notification on a power fault event.
1
0
RO
RO
0b
0b
Default value of this field is 0b. If Power Fault detection is not supported, this bit
is permitted to be read-only with a value of 0b
Button Pressed Enable (ABPE): When set to 1b, this bit enables software
notification on an attention button pressed event.
Datasheet
245
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.43
SLOTSTS—Slot Status
B/D/F/Type:
0/6/0/PCI
Address Offset: BA–BBh
Default Value:
Access:
Size:
0000h
RO, RWC
16 bits
PCI Express Slot related registers.
Default
Value
Bit
Access
Description
15:7
RO
RO
0000000b Reserved
Presence Detect State (PDS): This bit indicates the presence of an adapter
in the slot, reflected by the logical "OR" of the Physical Layer in-band presence
detect mechanism and, if present, any out-of-band presence detect
mechanism defined for the slot's corresponding form factor. Note that the in-
band presence detect mechanism requires that power be applied to an adapter
for its presence to be detected.
6
0b
0 = Slot Empty
1 = Card Present in Slot
This register must be implemented on all Downstream Ports that implement
slots. For Downstream Ports not connected to slots (where the Slot
Implemented bit of the PCI Express Capabilities Register is 0b), this bit must
return 1b.
5:4
3
RO
00b
0b
Reserved
Detect Changed (PDC): This bit is set when the value reported in Presence
Detect State is changed.
RWC
MRL Sensor Changed (MSC): If an MRL sensor is implemented, this bit is set
when a MRL Sensor state change is detected. If an MRL sensor is not
implemented, this bit must not be set.
2
1
0
RO
RO
RO
0b
0b
0b
Power Fault Detected (PFD): If a Power Controller that supports power fault
detection is implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware capability, it is
possible that a power fault can be detected at any time, independent of the
Power Controller Control setting or the occupancy of the slot. If power fault
detection is not supported, this bit must not be set.
Attention Button Pressed (ABP): If an Attention Button is implemented,
this bit is set when the attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
246
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.44
RCTL—Root Control
B/D/F/Type:
0/6/0/PCI
Address Offset: BC–BDh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
Default
Value
Bit
Access
Description
15:4
RO
000h
Reserved
PME Interrupt Enable (PMEIE):
0 = No interrupts are generated as a result of receiving PME messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit of the Root Status Register. A PME interrupt is also
generated if the PME Status bit of the Root Status Register is set when this
bit is set from a cleared state.
3
2
1
0
RW
0b
0b
0b
0b
System Error on Fatal Error Enable (SEFEE): Controls the Root Complex's
response to fatal errors.
0 = No SERR generated on receipt of fatal error.
RW
RW
RW
1 = Indicates that an SERR should be generated if a fatal error is reported by
any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
System Error on Non-Fatal Uncorrectable Error Enable (SENFUEE):
Controls the Root Complex's response to non-fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-fatal error is reported
by any of the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
System Error on Correctable Error Enable (SECEE): Controls the Root
Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a correctable error is reported
by any of the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
Datasheet
247
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.45
RSTS—Root Status
B/D/F/Type:
0/6/0/PCI
Address Offset: C0–C3h
Default Value:
Access:
Size:
00000000h
RO, RWC
32 bits
This register provides information about PCI Express Root Complex specific
parameters.
Default
Value
Bit
Access
Description
31:18
RO
0000h Reserved
PME Pending (PMEP): Indicates that another PME is pending when the PME
Status bit is set. When the PME Status bit is cleared by software; the PME is
delivered by hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by hardware if no
more PMEs are pending.
17
RO
0b
PME Status (PMES): Indicates that PME was asserted by the requestor ID
indicated in the PME Requestor ID field. Subsequent PMEs are kept pending until
the status register is cleared by writing a 1 to this field.
16
RWC
RO
0b
PME Requestor ID (PMERID): Indicates the PCI requestor ID of the last PME
requestor.
15:0
0000h
8.46
PELC—PCI Express Legacy Control
B/D/F/Type:
0/6/0/PCI
Address Offset: EC–EFh
Default Value:
Access:
Size:
00000000h
RO, RW
32 bits
This register controls functionality that is needed by Legacy (non-PCI Express aware)
OSs during run time.
Default
Value
Bit
Access
Description
0000000
0h
31:3
RO
Reserved
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received (Assert_PMEGPE and
Deassert_PMEGPE messages on DMI). This enables the MCH to support
PMEs on the PCI Express port under legacy OSs.
2
1
RW
RO
0b
0b
Reserved
General Message GPE Enable (GENGPE):
0 = Do not forward received GPE assert/de-assert messages.
1 = Forward received GPE assert/de-assert messages. These general GPE
message can be received via the PCI Express port from an external Intel
device and will be subsequently forwarded to the ICH (via Assert_GPE and
Deassert_GPE messages on DMI).
0
RW
0b
248
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.47
VCECH—Virtual Channel Enhanced Capability
Header
B/D/F/Type:
0/6/0/MMR
Address Offset: 100–103h
Default Value:
Access:
Size:
14010002h
RO
32 bits
This register indicates PCI Express device Virtual Channel capabilities. Extended
capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability
structures.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): The Link Declaration Capability is the next
in the PCI Express extended capabilities list.
31:20
RO
RO
RO
140h
PCI Express Virtual Channel Capability Version (PCIEVCCV): Hardwired to
1 to indicate compliances with the 1.1 version of the PCI Express specification.
19:16
15:0
1h
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0002h identifies this linked list item
(capability structure) as being for PCI Express Virtual Channel registers.
0002h
8.48
PVCCAP1—Port VC Capability Register 1
B/D/F/Type:
0/6/0/MMR
Address Offset: 104–107h
Default Value:
Access:
Size:
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Default
Value
Bit
Access
Description
31:7
RO
00000h Reserved
Low Priority Extended VC Count (LPEVCC): This field indicates the number
of (extended) Virtual Channels in addition to the default VC belonging to the low-
priority VC (LPVC) group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
6:4
RO
000b
The value of 0 in this field implies strict VC arbitration.
3
RO
RO
0b
Reserved
Extended VC Count (EVCC): This field indicates the number of (extended)
Virtual Channels in addition to the default VC supported by the device.
2:0
000b
Datasheet
249
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.49
PVCCAP2—Port VC Capability Register 2
B/D/F/Type:
0/6/0/MMR
Address Offset: 108–10Bh
Default Value:
Access:
Size:
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Default
Value
Bit
Access
Description
VC Arbitration Table Offset (VCATO): This field indicates the location of the
VC Arbitration Table. This field contains the zero-based offset of the table in
DQWORDS (16 bytes) from the base address of the Virtual Channel Capability
Structure. A value of 0 indicates that the table is not present (due to fixed VC
priority).
31:24
RO
RO
00h
23:0
0000h Reserved
8.50
PVCCTL—Port VC Control
B/D/F/Type:
0/6/0/MMR
Address Offset: 10C–10Dh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:4
RO
RW
RO
000h
Reserved
VC Arbitration Select (VCAS): This field will be programmed by software to
the only possible value as indicated in the VC Arbitration Capability field. Since
there is no other VC supported than the default, this field is reserved.
3:1
0
000b
0b
Reserved
250
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.51
VC0RCAP—VC0 Resource Capability
B/D/F/Type:
0/6/0/MMR
Address Offset: 110–113h
Default Value:
Access:
Size:
00000001h
RO
32 bits
Default
Bit
Access
Description
Value
0000h Reserved
Reject Snoop Transactions (RSNPT):
31:16
RO
RO
RO
0 = Transactions with or without the No Snoop bit set within the Transaction
Layer Packet header are allowed on this VC.
1 = When Set, any transaction for which the No Snoop attribute is applicable but
is not Set within the TLP Header will be rejected as an Unsupported Request.
15
0b
14:8
0000h Reserved
Port Arbitration Capability: Indicates types of Port Arbitration
supported by the VC resource. This field is valid for all Switch Ports, Root Ports
that support peer-to-peer traffic, and RCRBs, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer traffic.
Each bit location within this field corresponds to a Port Arbitration Capability
defined below. When more than one bit in this field is Set, it indicates that the
VC resource can be configured to provide different arbitration services.
Software selects among these capabilities by writing to the Port Arbitration
Select field (see below).
7:0
RO
01h
Bit[0]
= Default = 01b; Non-configurable hardware-fixed arbitration
scheme, e.g., Round Robin (RR)
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
= Weighted Round Robin (WRR) arbitration with 32 phases
= WRR arbitration with 64 phases
= WRR arbitration with 128 phases
= Time-based WRR with 128 phases
= WRR arbitration with 256 phases
Bits[6:7] = Reserved
MCH default indicates "Non-configurable hardware-fixed arbitration scheme".
Datasheet
251
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.52
VC0RCTL—VC0 Resource Control
B/D/F/Type:
0/6/0/MMR
Address Offset: 114–117h
Default Value:
Access:
Size:
800000FFh
RO, RW
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Default
Value
Bit
Access
Description
VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as VC0 can
never be disabled.
31
RO
RO
RO
RO
1b
0h
30:27
26:24
23:20
Reserved
VC0 ID (VC0ID): This field assigns a VC ID to the VC resource. For VC0 this is
hardwired to 0 and read only.
000b
0000h Reserved
Port Arbitration Select: This field configures the VC resource to provide a
particular Port Arbitration service. This field is valid for RCRBs, Root Ports that
support peer to peer traffic, and Switch Ports, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer traffic.
19:17
16:8
RW
RO
000b
00h
The permissible value of this field is a number corresponding to one of the
asserted bits in the Port Arbitration Capability field of the VC resource.
Reserved
TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic Classes) that are
mapped to the VC resource. Bit locations within this field correspond to TC
values. For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that multiple
TCs are mapped to the VC resource. To remove one or more TCs from the TC/VC
Map of an enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
7:1
0
RW
RO
7Fh
1b
TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.
252
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.53
VC0RSTS—VC0 Resource Status
B/D/F/Type:
0/6/0/MMR
Address Offset: 11A–11Bh
Default Value:
Access:
Size:
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Default
Value
Bit
Access
Description
15:2
RO
RO
RO
0000h Reserved
VC0 Negotiation Pending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set
by default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state.
1
1b
0b
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
Reserved
8.54
RCLDECH—Root Complex Link Declaration
Enhanced
B/D/F/Type:
0/6/0/MMR
Address Offset: 140–143h
Default Value:
Access:
Size:
00010005h
RO
32 bits
This capability declares links from this element (PCI Express) to other elements of the
root complex component to which it belongs. See PCI Express specification for link/
topology declaration requirements.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This is the last capability in the PCI Express
extended capabilities list.
31:20
RO
RO
RO
000h
Link Declaration Capability Version (LDCV): Hardwired to 1 to indicate
compliances with the 1.1 version of the PCI Express specification.
19:16
15:0
1h
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0005h identifies this linked list item
(capability structure) as being for PCI Express Link Declaration Capability.
0005h
Datasheet
253
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.55
ESD—Element Self Description
B/D/F/Type:
0/6/0/MMR
Address Offset: 144–147h
Default Value:
Access:
Size:
03000100h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Default
Value
Bit
Access
Description
Port Number (PN): This field specifies the port number associated with this
element with respect to the component that contains this element. This port
number value is used by the egress port of the component to provide arbitration
to this Root Complex Element.
31:24
RO
03h
Component ID (CID): This field indicates the physical component that contains
this Root Complex Element.
23:16
15:8
RWO
RO
00h
01h
Number of Link Entries (NLE): This field indicates the number of link entries
following the Element Self Description. This field reports 1 (to Egress port only
as we don't report any peer-to-peer capabilities in our topology).
7:4
3:0
RO
RO
0h
0h
Reserved
Element Type (ET): This field indicates Configuration Space Element.
254
Datasheet
Host-Secondary PCI Express* Bridge Registers (D6:F0)
8.56
LE1D—Link Entry 1 Description
B/D/F/Type:
0/6/0/MMR
Address Offset: 150–153h
Default Value:
Access:
Size:
00000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
Target Port Number (TPN): This field specifies the port number associated
with the element targeted by this link entry (Egress Port). The target port
number is with respect to the component that contains this element as specified
by the target component ID.
31:24
RO
00h
Target Component ID (TCID): This field identifies the physical or logical
component that is targeted by this link entry.
23:16
15:2
RWO
RO
00h
0000h Reserved
Link Type (LTYP): This bit indicates that the link points to memory–mapped
1
0
RO
0b
space (for RCRB). The link address specifies the 64-bit base address of the
target RCRB.
Link Valid (LV):
RWO
0b
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
8.57
LE1A—Link Entry 1 Address
B/D/F/Type:
0/6/0/MMR
Address Offset: 158–15Fh
Default Value:
Access:
Size:
0000000000000000h
RO, RWO
64 bits
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
Default
Value
Bit
Access
Description
0000000
0h
63:32
RO
Reserved
Link Address (LA): This field provides the memory mapped base address of
the RCRB that is the target element (Egress Port) for this link entry.
31:12
11:0
RWO
RO
00000h
000h
Reserved
§ §
Datasheet
255
Host-Secondary PCI Express* Bridge Registers (D6:F0)
256
Datasheet
Direct Media Interface (DMI) RCRB
9
Direct Media Interface (DMI)
RCRB
This Root Complex Register Block (RCRB) controls the MCH-ICH9 serial interconnect.
The base address of this space is programmed in DMIBAR in D0:F0 configuration space.
Table 16 provides an address map of the DMI registers listed by address offset in
ascending order.
Note:
IMPORTANT: All RCRB register space needs to remain organized as shown here.
Table 16.
Direct Media Interface Register Address Map
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
DMI Virtual Channel Enhanced
Capability
0–3h
DMIVCECH
04010002h
RO
4–7h
DMIPVCCAP1 DMI Port VC Capability Register 1
DMIPVCCTL DMI Port VC Control
00000001h
0000h
RWO, RO
RO, RW
RO
C–Dh
10–13h
14–17h
1A–1Bh
1C–1Fh
20–23h
26–27h
84–87h
88–89h
8A–8Bh
DMIVC0RCAP DMI VC0 Resource Capability
DMIVC0RCTL0 DMI VC0 Resource Control
DMIVC0RSTS DMI VC0 Resource Status
DMIVC1RCAP DMI VC1 Resource Capability
DMIVC1RCTL1 DMI VC1 Resource Control
DMIVC1RSTS DMI VC1 Resource Status
00000001h
800000FFh
0002h
RO, RW
RO
00008001h
01000000h
0002h
RO
RW, RO
RO
DMILCAP
DMILCTL
DMILSTS
DMI Link Capabilities
DMI Link Control
DMI Link Status
00012C41h
0000h
RO, RWO
RW, RO
RO
0001h
Datasheet
257
Direct Media Interface (DMI) RCRB
9.1
DMIVCECH—DMI Virtual Channel Enhanced
Capability
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 0–3h
Default Value:
Access:
Size:
04010002h
RO
32 bits
This register indicates DMI Virtual Channel capabilities.
Default
Value
Bit
Access
Description
Pointer to Next Capability (PNC): This field contains the offset to the next
PCI Express capability structure in the linked list of capabilities (Link Declaration
Capability).
31:20
RO
040h
PCI Express Virtual Channel Capability Version (PCIEVCCV): Hardwired
to 1 to indicate compliances with the 1.1 version of the PCI Express
specification.
19:16
15:0
RO
RO
1h
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0002 h identifies this linked list item
(capability structure) as being for PCI Express Virtual Channel registers.
0002h
9.2
DMIPVCCAP1—DMI Port VC Capability Register 1
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 4–7h
Default Value:
Access:
Size:
00000001h
RWO, RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Default
Value
Bit
Access
Description
31:7
RO
0000000h Reserved
Low Priority Extended VC Count (LPEVCC): Indicates the number of
(extended) Virtual Channels in addition to the default VC belonging to the low-
priority VC (LPVC) group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
6:4
RO
000b
The value of 0 in this field implies strict VC arbitration.
3
RO
0b
Reserved
Extended VC Count (EVCC): Indicates the number of (extended) Virtual
Channels in addition to the default VC supported by the device.
2:0
RWO
001b
The Private Virtual Channel is not included in this count.
258
Datasheet
Direct Media Interface (DMI) RCRB
9.3
DMIPVCCTL—DMI Port VC Control
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: C–Dh
Default Value:
Access:
Size:
0000h
RO, RW
16 bits
Default
Value
Bit
Access
Description
15:4
RO
RW
RO
000h
Reserved
VC Arbitration Select (VCAS): This field will be programmed by software to
the only possible value as indicated in the VC Arbitration Capability field.
3:1
0
000b
0b
See the PCI express specification for more details
Reserved
9.4
DMIVC0RCAP—DMI VC0 Resource Capability
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 10–13h
Default Value:
Access:
Size:
00000001h
RO
32 bits
Default
Value
Bit
Access
Description
31:16
RO
0s
Reserved
Reject Snoop Transactions (REJSNPT):
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
15
RO
0b
1 = When Set, any transaction for which the No Snoop attribute is applicable but
is not Set within the TLP Header will be rejected as an Unsupported Request.
14:8
7:0
RO
RO
00h
01h
Reserved
Port Arbitration Capability (PAC): Having only bit 0 set indicates that the
only supported arbitration scheme for this VC is non-configurable hardware-
fixed.
Datasheet
259
Direct Media Interface (DMI) RCRB
9.5
DMIVC0RCTL0—DMI VC0 Resource Control
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 14–17h
Default Value:
Access:
Size:
800000FFh
RO, RW
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Default
Value
Bit
Access
Description
Virtual Channel 0 Enable (VC0E): For VC0 this is hardwired to 1 and read
only as VC0 can never be disabled.
31
RO
RO
RO
RO
1b
0h
30:27
26:24
23:20
Reserved
Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0
this is hardwired to 0 and read only.
000b
0h
Reserved
Port Arbitration Select (PAS): This field configures the VC resource to provide
a particular Port Arbitration service. Valid value for this field is a number
corresponding to one of the asserted bits in the Port Arbitration Capability field
of the VC resource. Because only bit 0 of that field is asserted.
19:17
16:8
RW
RO
000b
000h
This field will always be programmed to 1.
Reserved
Traffic Class / Virtual Channel 0 Map (TCVC0M): This field indicates the TCs
(Traffic Classes) that are mapped to the VC resource. Bit locations within this
field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC resource.
When more than one bit in this field is set, it indicates that multiple TCs are
mapped to the VC resource. In order to remove one or more TCs from the TC/VC
Map of an enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
7:1
0
RW
RO
7Fh
1b
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M): Traffic Class 0 is always
routed to VC0.
260
Datasheet
Direct Media Interface (DMI) RCRB
9.6
DMIVC0RSTS—DMI VC0 Resource Status
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 1A–1Bh
Default Value:
Access:
Size:
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Default
Value
Bit
Access
Description
15:2
RO
RO
RO
0000h Reserved
Virtual Channel 0 Negotiation Pending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set
by default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state.
1
1b
0b
It is cleared when the link successfully exits the FC_INIT2 state.
BIOS Requirement: Before using a Virtual Channel, software must check
whether the VC Negotiation Pending fields for that Virtual Channel are cleared in
both Components on a Link.
0
Reserved
9.7
DMIVC1RCAP—DMI VC1 Resource Capability
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 1C–1Fh
Default Value:
Access:
Size:
00008001h
RO
32 bits
Default
Value
Bit
Access
Description
31:16
RO
00h
Reserved
Reject Snoop Transactions (REJSNPT):
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
15
RO
1b
1 = When Set, any transaction for which the No Snoop attribute is applicable but
is not Set within the TLP Header will be rejected as an Unsupported Request.
14:8
7:0
RO
RO
00h
01h
Reserved
Port Arbitration Capability (PAC): Having only bit 0 set indicates that the
only supported arbitration scheme for this VC is non-configurable hardware-
fixed.
Datasheet
261
Direct Media Interface (DMI) RCRB
9.8
DMIVC1RCTL1—DMI VC1 Resource Control
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 20–23h
Default Value:
Access:
Size:
01000000h
RW, RO
32 bits
This register controls the resources associated with PCI Express Virtual Channel 1.
Default
Value
Bit
Access
Description
Virtual Channel 1 Enable (VC1E):
31
RW
RO
RW
RO
0b
0h
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled.
30:27
26:24
23:20
Reserved
Virtual Channel 1 ID (VC1ID): This field assigns a VC ID to the VC resource.
Assigned value must be non-zero. This field can not be modified when the VC is
already enabled.
001b
0h
Reserved
Port Arbitration Select (PAS): This field configures the VC resource to
provide a particular Port Arbitration service. Valid value for this field is a number
corresponding to one of the asserted bits in the Port Arbitration Capability field
of the VC resource.
19:17
16:8
RW
RO
000b
000h
Reserved
Traffic Class / Virtual Channel 1 Map (TCVC1M): This field indicates the TCs
(Traffic Classes) that are mapped to the VC resource. Bit locations within this
field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC resource.
When more than one bit in this field is set, it indicates that multiple TCs are
mapped to the VC resource. To remove one or more TCs from the TC/VC Map of
an enabled VC, software must ensure that no new or outstanding transactions
with the TC labels are targeted at the given Link.
7:1
0
RW
RO
00h
0b
Traffic Class 0 / Virtual Channel 1 Map (TC0VC1M): Traffic Class 0 is
always routed to VC0.
262
Datasheet
Direct Media Interface (DMI) RCRB
9.9
DMIVC1RSTS—DMI VC1 Resource Status
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 26–27h
Default Value:
Access:
Size:
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Default
Value
Bit
Access
Description
15:2
RO
RO
RO
0000h Reserved
Virtual Channel 1 Negotiation Pending (VC1NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
1
0
1b
0b
Reserved
9.10
DMILCAP—DMI Link Capabilities
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 84–87h
Default Value:
Access:
Size:
00012C41h
RO, RWO
32 bits
This register indicates DMI specific capabilities.
Default
Value
Bit
Access
Description
31:18
RO
0000h Reserved
L1 Exit Latency (L1SELAT): This field indicates the length of time this Port
requires to complete the transition from L1 to L0.
17:15
RWO
010b
010 = 2 µs to less than 4 µs
All other encodings are reserved.
L0s Exit Latency (L0SELAT): This field indicates the length of time this Port
requires to complete the transition from L0s to L0.
14:12
11:10
9:4
RWO
RO
010b
11b
04h
1h
010 = 128 ns to less than 256 ns
All other encodings are reserved.
Active State Link PM Support (ASLPMS): L0s & L1 entry supported.
Max Link Width (MLW): This field indicates the maximum number of lanes
supported for this link.
RO
04h = x4
All other encodings are reserved.
3:0
RO
Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.
Datasheet
263
Direct Media Interface (DMI) RCRB
9.11
DMILCTL—DMI Link Control
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 88–89h
Default Value:
Access:
Size:
0000h
RW, RO
16 bits
This register allows control of DMI.
Default
Value
Bit
Access
Description
15:8
RO
00h
Reserved
Extended Synch (EXTSYNC):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the L0s
state and when in the Recovery state.
7
RW
0b
6:3
2
RO
0h
0b
Reserved
RW
Far-End Digital Loopback (FEDLB):
Active State Power Management Support (ASPMS): This field controls the
level of active state power management supported on the given link.
00 = Disabled
1:0
RW
00b
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
9.12
DMILSTS—DMI Link Status
B/D/F/Type:
0/0/0/DMIBAR
Address Offset: 8A–8Bh
Default Value:
Access:
Size:
0001h
RO
16 bits
This register indicates DMI status.
Default
Value
Bit
Access
Description
15:4
RO
RO
0s
Reserved
Negotiated Speed (NSPD): This field indicates negotiated link speed.
1h = 2.5 Gb/s
3:0
1h
All other encodings are reserved.
§ §
264
Datasheet
Functional Description
10 Functional Description
10.1
Host Interface
The MCH supports Intel® CoreTM2 Duo and Intel® Core™2 Quad processors. The cache
line size is 64 bytes. Source synchronous transfer is used for the address and data
signals. The address signals are double pumped and a new address can be generated
every other bus clock. At 200/267/333MHz bus clock the address signals run at 667MT/
s. The data is quad pumped and an entire 64B cache line can be transferred in two bus
clocks. At 200/266/333MHz bus clock, the data signals run at 800/1066/1333MT/s for
a maximum bandwidth of 6.4/8.5/10.6GB/s.
10.1.1
10.1.2
10.1.3
10.1.4
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
FSB OOQ Depth
The MCH supports only one outstanding deferred transaction on the FSB.
FSB GTL+ Termination
The MCH integrates GTL+ termination resistors on die.
FSB Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data
from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the MCH. HDINV[3:0]# indicate if the corresponding 16 bits of data are
inverted on the bus for each quad pumped data phase:
HDINV#[3:0]
Data Bits
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HD[15:0]#
HD[31:16]#
HD[47:32]#
HD[63:48]#
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more
than 8 of the 16 signals would normally be driven low on the bus, the corresponding
HDINV# signal will be asserted, and the data will be inverted prior to being driven on
the bus. When the processor or the MCH receives data, it monitors HDINV#[3:0] to
determine if the corresponding data segment should be inverted.
Datasheet
265
Functional Description
Table 17.
Host Interface 4X, 2X, and 1X Signal Groups
Signals
Associated Clock or Strobe
Signal Group
ADS#, BNR#, BPRI#, DEFER#,
DBSY#, DRDY#, HIT#, HITM#,
LOCK#, RS[2:0]#, TRDY#,
RESET, BR0#
BCLK
1X
HA[16:3]#, REQ[4:0]#
HA[35:17]#
ADSTB[0]#
2X
4X
ADSTB[1]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
10.1.5
APIC Cluster Mode Support
APIC Cluster mode support is required for backwards compatibility with existing
software, including various operating systems.
The MCH supports three types of interrupt re-direction:
• Physical
• Flat-Logical
• Clustered-Logical
266
Datasheet
Functional Description
10.2
System Memory Controller
The system memory controller supports both DDR2 and DDR3 protocols with two
independent 64 bit wide channels each accessing one or two DIMMs. It supports a
maximum of two un-buffered ECC or non-ECC DDR2 DIMMs or two un-buffered non-
ECC DDR3 DIMMs per channel thus allowing up to four device ranks per channel.
10.2.1
System Memory Organization Modes
The system memory controller supports two memory organization modes, Single
Channel and Dual Channel.
10.2.1.1
Single Channel Mode
In this mode, all memory cycles are directed to a single channel.
Single channel mode is used when either Channel A or Channel B DIMMs are populated
in any order, but not both.
10.2.1.2
Dual Channel Modes
10.2.1.2.1
Dual Channel Symmetric Mode
This mode provides maximum performance on real applications. Addresses are ping-
ponged between the channels after each cache line (64 byte boundary). If there are
two requests, and the second request is to an address on the opposite channel from the
first, that request can be sent before data from the first request has returned. If two
consecutive cache lines are requested, both may be retrieved simultaneously, since
they are guaranteed to be on opposite channels.
Dual channel symmetric mode is used when both Channel A and Channel B DIMMs are
populated in any order with the total amount of memory in each channel being the
same, but the DRAM device technology and width may vary from one channel to the
other.
Table 18 is a sample dual channel symmetric memory configuration showing the rank
organization.
Table 18.
Sample System Memory Dual Channel Symmetric Organization Mode
Cumulative Top
Address in
Cumulative Top
Address in
Channel 0
Population
Channel 1
Population
Rank
Channel 0
Channel 1
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
Datasheet
267
Functional Description
10.2.1.2.2
Dual Channel Asymmetric Mode with Intel® Flex Memory Mode Enabled
In this addressing mode the lowest DRAM memory is mapped to dual channel operation
and the top most DRAM memory is mapped to single channel operation. In this mode
the system can run at one zone of dual channel mode and one zone of single channel
mode simultaneously across the whole memory array.
This mode is used when Intel® Flex Memory Mode is enabled and both Channel A and
Channel B DIMMs are populated in any order with the total amount of memory in each
channel being different.
Table 19 is a sample dual channel asymmetric memory configuration showing the rank
organization with Intel® Flex Memory Mode Enabled.
Table 19.
Sample System Memory Dual Channel Asymmetric Organization Mode with
Intel® Flex Memory Mode Enabled
Cumulative top
address in
Cumulative top
address in
Channel 0
population
Channel 1
population
Rank
Channel 0
Channel 1
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
0 MB
2048 MB
2048 MB
2048 MB
1024 MB
0 MB
2304 MB
2304 MB
2048 MB
1024 MB
256 MB
512 MB
512 MB
512 MB
512 MB
10.2.1.2.3
Dual Channel Asymmetric Mode with Intel® Flex Memory Mode Disabled
In this addressing mode addresses start in channel 0 and stay there until the end of the
highest rank in channel 0, and then addresses continue from the bottom of channel 1
to the top.
This mode is used when Intel® Flex Memory Mode is disabled and both Channel A and
Channel B DIMMs are populated in any order with the total amount of memory in each
channel being different.
Table 20 is a sample dual channel asymmetric memory configuration showing the rank
organization with Intel® Flex Memory Mode Disabled:
Table 20.
Sample System Memory Dual Channel Asymmetric Organization Mode with
Intel® Flex Memory Mode Disabled
Cumulative top
address in
Cumulative top
address in
Channel 0
population
Channel 1
population
Rank
Channel 0
Channel 1
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
1280 MB
1280 MB
1024 MB
512 MB
0 MB
0 MB
2304 MB
2304 MB
2304 MB
1792 MB
256 MB
512 MB
512 MB
512 MB
512 MB
268
Datasheet
Functional Description
10.2.2
System Memory Technology Supported
The MCH supports the following DDR2 and DDR3 Data Transfer Rates, DIMM Modules,
and DRAM Device Technologies:
• DDR2 Data Transfer Rates: 667 (PC2-5300) and 800 (PC2-6400)
• DDR3 Data Transfer Rates: 800 (PC3-6400), 1066 (PC3-8500), and 1333 (PC3-
10600)
• DDR2 DIMM Modules:
— Raw Card C - Single Sided x16 un-buffered non-ECC
— Raw Card D - Single Sided x8 un-buffered non-ECC
— Raw Card E - Double Sided x8 un-buffered non-ECC
— Raw Card F - Single Sided x8 un-buffered ECC
— Raw Card G - Double Sided x8 un-buffered ECC
• DDR3 DIMM Modules:
— Raw Card A - Single Sided x8 un-buffered non-ECC
— Raw Card B - Double Sided x8 un-buffered non-ECC
— Raw Card C - Single Sided x16 un-buffered non-ECC
— Raw Card F - Double Sided x16 un-buffered non-ECC
• DDR2 and DDR3 DRAM Device Technology: 512-Mb and 1-Gb
Table 21.
Supported DIMM Module Configurations
# of
# of
Physical
Device
Ranks
# of
Raw
Card
DRAM
Device
# of
DRAM
Devices
Row/
Col
Memory
Type
DIMM
Capacity
DRAM
Organization
Banks Page
Inside Size
DRAM
Version
Technology
Address
Bits
256MB
512MB
512MB
1GB
512Mb
1Gb
32M X 16
64M X 16
64M X 8
128M X 8
64M X 8
4
4
1
1
1
1
2
13/10
13/10
14/10
14/10
14/10
4
8
4
8
4
8K
8K
8K
8K
8K
C
512Mb
1Gb
8
D
8
1GB
512Mb
16
E
F
DDR2
2GB
512MB
1GB
1Gb
512Mb
1Gb
128M X 8
64M X 8
128M X 8
64M X 8
128M X 8
16
9
2
1
1
2
2
14/10
14/10
14/10
14/10
14/10
8
4
8
4
8
8K
8K
8K
8K
8K
667 and
800
9
1GB
512Mb
1Gb
18
18
G
2GB
512MB
1GB
512Mb
1Gb
64M X 8
128M X 8
64M X 8
8
8
1
1
2
2
1
1
2
2
13/10
14/10
13/10
14/10
12/10
13/10
12/10
13/10
8
8
8
8
8
8
8
8
8K
8K
8K
8K
8K
8K
8K
8K
A
B
C
F
1GB
512Mb
1Gb
16
16
4
DDR3
2GB
128M X 8
32M X 16
64M X 16
32M X 16
64M X 16
800 and
1066
256MB
512MB
512MB
1GB
512Mb
1Gb
4
512Mb
1Gb
8
8
Datasheet
269
Functional Description
10.2.3
Error Checking and Correction
Table 22 is used to calculate the syndrome. Numbers in parentheses indicate the data
content of that bit position. For example, bit position 36 holds the data originally in
data bit 32.
Table 22.
Syndrome Bit Values
Syndrome Bit >
7
6
5
4
3
2
1
0
Data Bit
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
2
X
3
X
X
X
X
X
4
X
X
X
X
X
X
X
X
X
5
X
X
X
X
X
X
6
7
X
X
X
X
X
8
X
X
X
X
9
10
11
12
X
X
X
X
X
X
X
X
X
X
X
X
13
14
15
16
X
X
X
X
X
X
X
X
X
17
18
19
20
X
X
X
X
X
21
22
23
X
X
X
24
X
X
X
25
X
X
X
26 (CB2)
27 (CB5)
28 (26)
29 (27)
30 (28)
31 (29)
32 (30)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
270
Datasheet
Functional Description
Table 22.
Syndrome Bit Values
Syndrome Bit >
Data Bit
7
6
5
4
3
2
1
0
33 (31)
34 (CB3)
35 (CB4)
36 (32)
37 (33)
38 (34)
39 (35)
40 (36)
41 (37)
42 (38)
43 (39)
44 (40)
45 (41)
46 (42)
47 (43)
48 (44)
49 (45)
50 (46)
51 (47)
52 (48)
53 (49)
54 (50)
55 (51)
56 (52)
57 (53)
58 (54)
59 (55)
60 (56)
61 (57)
62 (CB6)
63 (CB1)
CB0 (58)
CB1 (59)
CB2 (60)
CB3 (61)
CB4 (62)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Datasheet
271
Functional Description
Table 22.
Syndrome Bit Values
Syndrome Bit >
Data Bit
7
6
5
4
3
2
1
0
CB5 (63)
CB6 (CB7)
CB7 (CB0)
X
X
X
X
X
X
X
Every data bit appears in either exactly 3 or exactly 5 check bit and syndrome bit
equations. Every check bit appears en exactly 1 syndrome bit equation. This leads to
six cases.
1. If the data comes back exactly as it was written, then the calculated check byte will
match the stored check byte, and the syndrome will be all 0s.
2. If exactly one check bit is flipped between the time it is written and the time it is
read back, then the syndrome will contain exactly one 1. Since the check byte is
not returned to the requesting agent, no action is necessary.
3. If exactly one data bit is flipped between the time it is written and the time it is
read back, then the syndrome will contain either exactly three 1s or exactly five 1s.
The syndrome can then be decoded as a pointer to the bit that flipped using the
same check byte generation table in reverse. If the syndrome contains 1s that
match the locations of all three or all five Xs in a given row, then that is the bit
which should be flipped before the QWord is returned to the requesting agent.
4. If exactly two bits flipped, there will be a nonzero even number of 1s in the
syndrome. It cannot be determined which bits flipped based on that syndrome, but
a multi-bit error will be recorded along with the address at which the error
occurred. In addition, bits 0 and 31 of each DWord are forced to 0 in the returned
data in case this read was a TLB fetch. This ensures that the table entry is invalid,
such that additional data corruption can be avoided.
5. If an even number of bits greater than two flipped, there will be an even number of
1s in the syndrome, but that even number could be zero, such that detection of this
scenario is not ensured. If the syndrome contains a nonzero number of 1s, it
cannot be distinguished from scenario 4 above.
6. It is possible for an odd number of bits greater than one to flip between the time
the data is written and the time it is read back. This scenario will always be
detected, but the resulting syndrome could appear to be a multi-bit error treated
similarly to scenario 4, or it could be misinterpreted as a single bit error
indistinguishable from scenario 2. The data cannot be corrected, though if it
appears to be a single-bit error, the algorithm will flip the bit that corresponds to
the syndrome generated, thus an additional bit may be corrupted.
Fortunately, soft error rates are low enough that it is extremely unlikely that there
would be more than one soft error in the same QWord, so scenarios 5 and 6 are very
rare.
272
Datasheet
Functional Description
10.3
PCI Express*
See Section 1.2 for a list of PCI Express features, and the PCI Express specification for
further details.
This MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in Device 1 and Device 6 configuration space and three Root
Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the
Intel ICH9 attach ports.
10.3.1
PCI Express* Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 2.5 GHz results in 5 Gb/s each direction, which
provides a 500 MB/s communications channel in each direction (1000 MB/s total).
10.3.1.1
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
10.3.1.2
10.3.1.3
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry.
Datasheet
273
Functional Description
10.4
Thermal Sensor
There are several registers that need to be configured to support the MCH thermal
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the MCH. If the Catastrophic Trip Point is crossed, then the
MCH will instantly turn off all clocks inside the device. Customers may optionally enable
the Hot Trip Point to generate SMI #. Customers will be required to then write their own
SMI# handler in BIOS that will speed up the MCH (or system) fan to cool the part.
10.4.1
PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip
point is crossed. The ERRSTS register can be inspected for the SMI alert.
Register
Symbol
Register
Start
Register
End
Default
Value
Register Name
Access
Error Status
ERRSTS
SMICMD
C8
CC
C9
0000h
0000h
RWC/S, RO
RO, RW
SMI Command
CD
10.4.2
MCHBAR Thermal Sensor Registers
The Digital Thermometer Configuration Registers reside in the MCHBAR configuration
space.
Register
Symbol
Register
Start
Register
End
Default
Value
Register Name
Access
RW/L, RW,
RS/WC
Thermal Sensor Control 1
TSC1
CD8
CD8
00h
Thermal Sensor Control 2
Thermal Sensor Status
TSC2
TSS
CD9
CDA
CD9
CDA
00h
00h
RO, RW/L
RO
Thermal Sensor Temperature Trip
Point
TSTTP
TCO
CDC
CE2
CE4
CDF
CE2
CE4
00000000h
00h
RO, RW, RW/L
RW/L/K, RW/L
Thermal Calibration Offset
Hardware Throttle Control
RW/L, RO,
RW/L/K
THERM1
00h
TCO Fuses
THERM3
TIS
CE6
CEA
CF1
CE6
CEB
CF1
00h
0000h
00h
RO, RS/WC
RO, RWC
RO, RW
Thermal Interrupt Status
Thermal SMI Command
TSMICMD
274
Datasheet
Functional Description
10.5
10.6
Power Management
Power Management Feature List:
• ACPI 1.0b support
• ACPI S0, S1, S3 (Cold), S5, C0, C1, and C2 states
• Enhanced power management state transitions for increasing time processor
spends in low power states
• PCI Express Link States: L0, L0s, L2/L3 Ready, L3
Clocking
The MCH has a total of 3 PLLs providing many times that many internal clocks. The
PLLs are:
• Host PLL – Generates the main core clocks in the host clock domain. Can also be
used to generate memory core clocks. Uses the Host clock (H_CLKIN) as a
reference.
• Memory I/O PLL - Optionally generates low jitter clocks for memory I/O interface,
as opposed to from Host PLL. Uses the Host FSB differential clock (HPL_CLKINP/
HPL_CLKINN) as a reference. Low jitter clock source from memory I/O PLL is
required for DDR667 and higher frequencies.
• PCI Express PLL – Generates all PCI Express related clocks, including the Direct
Media that connect to the ICH. This PLL uses the 100 MHz clock (EXP_CLKNP/
EXP2_CLKNP) as a reference.
CK505 is the clocking chip required for the platform.
Datasheet
275
Functional Description
Figure 10.
System Clocking Diagram
Processor Diff Pair
CK505
C1
Processor
56- Pin SSOP
Processor Diff Pair
C2
Processor
Memory
Diff Pair
XDP
C3/S7
Dual
x16 PCI Express
PCI Express
DIffPair
S6
st PCI Express
1
PCI Express
nd PCI Express
DIff Pair
2
S5
MCH
PCI Express DIff Pair
DMI
S4
LAN(Nineveh)
PCI Express
DIff Pair
PCI Express Slot
S3
PCI Express
DIff Pair
PCI Express DIff Pair
S2
SATA Diff Pair
S1
D1
DOT 96MHz Diff Pair
USB 48MHz
U1
R1
REF 14MHz
REF 14MHz
SIO LPC
PCI 33MHz
Intel® ICH9
PCI 33MHz
PCI Down Device
P1
PCI 33MHz
PCI 33MHz
TPM LPC
OSC
P2
P3
32.768kHz
Signal Name
Ref.
BCLK, ITPCLK, HCLK
C1- C3
PCI 33MHz
PCI 33MHz
SATACLK, ICHCLK,
NC
NC
P4
S1-S7
MCHCLK, LANCLK,
PCI Slot
P5
P6
PCI 33MHz
PCIECLK
D1
DOTCLK
U1
USBCLK
P1-P6
PCICLK
R1
REFCLK
§ §
276
Datasheet
Electrical Characteristics
11 Electrical Characteristics
This chapter contains the DC specifications for the MCH.
11.1
Absolute Minimum and Maximum Ratings
Table 23 specifies the MCH absolute maximum and minimum ratings. Within functional
operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time its reliability will be severely degraded or not function
when returned to conditions within the functional operating condition limits.
Although the MCH contains protective circuitry to resist damage from static electric
discharge, precautions should always be taken to avoid high static voltages or electric
fields.
Table 23.
Absolute Minimum and Maximum Ratings
Symbol
Tstorage
Parameter
Storage Temperature
Min
Max
Unit Notes
-55
150
°C
1
MCH Core
1.25 V Core Supply Voltage with respect to
VSS
VCC
-0.3
1.375
V
Host Interface (800/1066/1333 MHz)
System Bus Input Voltage with respect to
VSS
VTT_FSB
-0.3
-0.3
1.32
V
V
1.25 V Host PLL Analog Supply Voltage with
respect to VSS
VCCA_HPLL
1.375
System Memory Interface (DDR2 667/800 MHz, DDR3 800/1066/1333 MHz)
1.8 V DDR2 / 1.5 V DDR3 System Memory
Supply Voltage with respect to VSS
VCC_DDR
VCC_CKDDR
VCCA_MPLL
-0.3
-0.3
-0.3
4.0
4.0
V
V
V
1.8 V DDR2 / 1.5 V DDR3 Clock System
Memory Supply Voltage with respect to VSS
1.25 V System Memory PLL Analog Supply
Voltage with respect to VSS
1.375
Datasheet
277
Electrical Characteristics
Table 23.
Absolute Minimum and Maximum Ratings
Symbol
Parameter
Min
Max
Unit Notes
PCI Express* / DMI Interface
1.25 V PCI Express* and DMI Supply
Voltage with respect to VSS
VCC_EXP
VCCA_EXP
-0.3
-0.3
-0.3
-0.3
1.375
3.63
V
V
V
V
3.3 V PCI Express* Analog Supply Voltage
with respect to VSS
1.25 V Primary PCI Express* PLL Analog
Supply Voltage with respect to VSS
VCCAPLL_EXP
VCCAPLL_EXP2
1.375
1.375
1.25 V Secondary PCI Express* PLL Analog
Supply Voltage with respect to VSS
Controller Link Interface
VCC_CL
1.25 V Supply Voltage with respect to VSS
-0.3
-0.3
1.375
3.63
V
V
CMOS Interface
3.3 V CMOS Supply Voltage with respect to
VSS
VCC3_3
NOTE:
1.
Possible damage to the MCH may occur if the MCH temperature exceeds 150 °C. Intel does
not ensure functionality for parts that have exceeded temperatures above 150 °C due to
specification violation.
278
Datasheet
Electrical Characteristics
11.2
Current Consumption
Table 24 shows the current consumption for the MCH in the Advanced Configuration
and Power Interface (ACPI) S0 state. Icc max values are determined on a per-interface
basis, at the highest frequencies for each interface. Sustained current values or Max
current values cannot occur simultaneously on all interfaces. Sustained Values are
measured sustained RMS maximum current consumption and includes leakage
estimates. The measurements are made with fast silicon at 96° C Tcase temperature,
at the Max voltage listed in Table 26. The Max values are maximum theoretical pre-
silicon calculated values. In some cases, the Sustained measured values have exceeded
the Max theoretical values.
Table 24.
Symbol
Current Consumption in S0
Parameter
Signal Names Sustained
Max
Unit
Notes
1.25 V Core Supply Current (Discrete
Gfx)
IVCC
VCC
6.06
2.06
521
7.27
A
1,2
DDR2 System Memory Interface
(1.8 V) Supply Current
IVCC_DDR2
IVCC_CKDDR2
IVCC_DDR3
IVCC_CKDDR3
IVCC_EXP
VCC_DDR
VCC_CKDDR
VCC_DDR
VCC_CKDDR
VCC_EXP
2.57
581
A
mA
A
1, 2, 3
DDR2 System Memory Clock Interface
(1.8 V) Supply Current
DDR3 System Memory Interface
(1.5 V) Supply Current
1.53
334
1.61
367
1, 2, 3
2
DDR3 System Memory Clock Interface
(1.5 V) Supply Current
mA
A
1.25 V PCI Express* and DMI Supply
Current
5.12
6.65
IVCC_CL
1.25 V Controller Supply Current
VCC_CL
2.20
387
2.80
580
A
2
1
IVTT_FSB
System Bus Supply Current
VTT_FSB
mA
3.3 V PCI Express* and DMI Analog
Supply Current
IVCCA_EXP
IVCC3_3
VCCA_EXP
VCC3_3
167
0.5
48
175
16
mA
mA
mA
mA
mA
3.3 V CMOS Supply Current
1.25 V PCI Express* and DMI PLL
Analog Supply Current
IVCCAPLL_EXP
IVCCA_HPLL
IVCCA_MPLL
VCCAPLL_EXP
VCCA_HPLL
VCCA_MPLL
53
1.25 V Host PLL Supply Current
18
26
1.25 V System Memory PLL Analog
Supply Current
97
146
NOTES:
1.
2.
3.
Measurements are for current coming through chipset’s supply pins.
Rail includes DLLs (and FSB sense amps on VCC).
Sustained Measurements are combined because one voltage regulator on the platform
supplies both rails on the MCH.
Datasheet
279
Electrical Characteristics
11.3
Signal Groups
The signal description includes the type of buffer used for the particular signal.
Type
Description
PCI Express interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications and are AC coupled. The buffers are not
PCI
Express* 3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2Vmax. Single-ended
maximum = 1.25 V. Single-ended minimum = 0 V.
Direct Media Interface signals. These signals are compatible with PCI Express 1.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3 V tolerant. Differential voltage spec = (|D+ – D-|) * 2 = 1.2 Vmax. Single-
DMI
ended maximum = 1.25 V. Single-ended minimum = 0 V.
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete
details.
GTL+
Host Clock Signal Level buffers. Current mode differential pair. Differential typical
HCSL
swing = (|D+ – D-|) * 2 = 1.4 V. Single ended input tolerant from -0.35 V to 1.2 V.
Typical crossing voltage 0.35 V.
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
SSTL-1.8
Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V
tolerant.
SSTL-1.5
CMOS
CMOS buffers
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
Analog
280
Datasheet
Electrical Characteristics
Table 25.
Signal Groups
Signal Type
Signals
Notes
Host Interface Signal Groups
FSB_ADSB, FSB_BNRB, FSB_DBSYB, FSB_DINVB_3:0,
FSB_DRDYB, FSB_AB_35:3, FSB_ADSTBB_1:0, FSB_DB_63:0,
FSB_DSTBPB_3:0, FSB_DSTBNB_3:0, FSB_HITB, FSB_HITMB,
FSB_REQB_4:0
GTL+ Input/Outputs
GTL+ Common
Clock Outputs
FSB_BPRIB, FSB_BREQ0B, FSB_CPURSTB, FSB_DEFERB,
FSB_TRDYB, FSB_RSB_2:0
Analog Host I/F Ref
& Comp. Signals
FSB_RCOMP, FSB_SCOMP, FSB_SCOMPB, FSB_SWING,
FSB_DVREF, FSB_ACCVREF
GTL+ Input
FSB_LOCKB, BSEL2:0
PCI Express* Graphics Interface Signal Groups
PCI Express* Input
PCI Express* Interface: PEG_RXN_15:0, PEG_RXP_15:0
PCI Express* Output PCI Express* Interface: PEG_TXN_15:0, PEG_TXP_15:0
Analog PCI Express*
Compensation
Signals
EXP_COMPO, EXP_COMPI
Direct Media Interface Signal Groups
DMI Input
DMI_RXP_3:0, DMI_RXN_3:0
DMI_TXP_3:0, DMI_TXN_3:0
DMI Output
System Memory Interface Signal Groups
DDR_A_DQ_63:0, DDR_A_DQS_7:0, DDR_A_DQSB_7:0
SSTL-1.8 / SSTL-1.5 DDR_B_DQ_63:0, DDR_B_DQS_7:0, DDR_B_DQSB_7:0
1
Input/Output
DDR_A_CB_7:0, DDR_A_DQS_8, DDR_A_DQSB_8
DDR_B_CB_7:0, DDR_B_DQS_8, DDR_B_DQSB_8
DDR_A_CK_5:0, DDR_A_CKB_5:0, DDR_A_CSB_3:0,
DDR3_A_CSB_1, DDR_A_CKE_3:0, DDR_A_ODT_3:0,
DDR_A_MA_14:0, DDR3_A_MA_0, DDR_A_BS_2:0,
DDR_A_RASB, DDR_A_CASB, DDR_A_WEB, DDR3_A_WEB,
DDR_A_DM_7:0
SSTL-1.8 / SSTL-1.5
Output
DDR_B_CK_5:0, DDR_B_CKB_5:0, DDR_B_CSB_3:0,
DDR_B_CKE_3:0, DDR_B_ODT_3:0, DDR3_B_ODT_3,
DDR_B_MA_14:0, DDR_B_BS_2:0, DDR_B_RASB,
DDR_B_CASB, DDR_B_WEB, DDR_B_DM_7:0
DDR3_DRAMRST
CMOS Input
DDR3_DRAM_PWROK
Reference and
Comp. Voltages
DDR_RCOMPXPD, DDR_RCOMPXPU, DDR_RCOMPYPD,
DDR_RCOMPYPU, DDR_VREF
Controller Link Signal Groups
CMOS I/O OD
CMOS Input
CL_DATA, CL_CLK
CL_RSTB, CL_PWROK
Analog Controller
Link Reference
Voltage
CL_VREF
Datasheet
281
Electrical Characteristics
Table 25.
Signal Groups
Signal Type
Clocks
Signals
Notes
HPL_CLKINP, HPL_CLKINN, EXP_CLKINP, EXP_CLKINN,
DPL_REFCLKINN, DPL_REFCLKINP
HCSL
Reset, and Miscellaneous Signal Groups
CMOS Input
EXP_SLR, PWROK, RSTINB
ICH_SYNCB
CMOS Output
I/O Buffer Supply Voltages
System Bus Input
VTT_FSB
Supply Voltage
1.25 V PCI Express*
VCC_EXP
Supply Voltages
3.3 V PCI Express*
Analog Supply
Voltage
VCCA_EXP
VCC_DDR
1.8 V DDR2 / 1.5 V
DDR3 Supply
Voltage
1.8 V DDR2 / 1.5 V
DDR3 Clock Supply
Voltage
VCC_CKDDR
1.25 V MCH Core
Supply Voltage
VCC
1.25 V Controller
Supply Voltage
VCC_CL
3.3 V CMOS Supply
Voltage
VCC3_3
PLL Analog Supply
Voltages
VCCA_HPLL, VCCAPLL_EXP, VCCA_MPLL
NOTES:
1.
CB_7:0, DQS[8], and DQSB[8] ECC signals are only for DDR2
282
Datasheet
Electrical Characteristics
11.4
Buffer Supply and DC Characteristics
11.4.1
I/O Buffer Supply Voltages
The I/O buffer supply voltage is measured at the MCH package pins. The tolerances
shown in Table 26 are inclusive of all noise from DC up to 20 MHz. In the lab, the
voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of
3 dB/decade above 20 MHz under all operating conditions.
Table 26 indicates which supplies are connected directly to a voltage regulator or to a
filtered voltage rail. For voltages that are connected to a filter, they should me
measured at the input of the filter.
If the recommended platform decoupling guidelines cannot be met, the system
designer will have to make tradeoffs between the voltage regulator output DC tolerance
and the decoupling performance of the capacitor network to stay within the voltage
tolerances listed in Table 26.
Table 26.
I/O Buffer Supply Voltage
Symbol
Parameter
Min
Nom
Max
Unit Notes
VCC_DDR
VCC_DDR
DDR2 I/O Supply Voltage
DDR3 I/O Supply Voltage
DDR2 Clock Supply Voltage
DDR3 Clock Supply Voltage
PCI-Express* Supply Voltage
1.7
1.8
1.5
1.9
V
V
1.425
1.7
1.575
1.9
VCC_CKDDR
VCC_CKDDR
VCC_EXP
1.8
V
V
V
1
1
1.425
1.188
1.5
1.575
1.313
1.25
PCI-Express* Analog Supply
Voltage
VCCA_EXP
3.135
1.14
3.3
1.2
3.465
1.26
V
V
1
2
1.2 V System Bus Input Supply
Voltage
VTT_FSB
VCC
1.1 V System Bus Input Supply
Voltage
1.045
1.188
1.1
1.155
1.313
V
V
MCH Core Supply Voltage
1.25
VCC_CL
VCC3_3
Controller Supply Voltage
CMOS Supply Voltage
1.188
3.135
1.25
3.3
1.313
3.465
V
V
VCCA_HPLL,
VCCAPLL_EXP,
VCCA_MPLL
Various PLL Analog Supply
Voltages
1.188
1.25
1.313
V
1
NOTES:
1.
These rails are filtered from other voltage rails on the platform and should be measured at
the input of the filter.
2.
MCH supports both VTT =1.2 V nominal and VTT =1.1 V nominal depending on the
identified processor.
Datasheet
283
Electrical Characteristics
11.4.2
General DC Characteristics
Platform Reference Voltages at the top of Table 27 are specified at DC only. VREF
measurements should be made with respect to the supply voltage.
Table 27.
DC Characteristics
Symbol
Parameter
Min
Nom
Max
Unit
Notes
Reference Voltages
Host Data, Address, and
Common Clock Signal
Reference Voltages
0.666 x
VTT_FSB
–2%
0.666 x
VTT_FSB
+2%
FSB_DVREF
FSB_ACCVREF
0.666 x
VTT_FSB
V
V
0.25 x
VTT_FSB
+2%
Host Compensation
Reference Voltage
0.25 x VTT_FSB
–2%
0.25 x
VTT_FSB
FSB_SWING
CL_VREF
Controller Link Reference
Voltage
0.270 x
VCC_CL
0.279 x
VCC_CL
0.287 x
VCC_CL
V
V
DDR2/DDR3 Reference
Voltage
0.49 x
VCC_DDR
0.50 x
VCC_DDR
0.51 x
VCC_DDR
DDR_VREF
Host Interface
(0.666 x
VTT_FSB) –
0.1
VIL_H
VIH_H
VOL_H
VOH_H
IOL_H
Host GTL+ Input Low Voltage
-0.10
0
V
V
Host GTL+ Input High
Voltage
(0.666 x
VTT_FSB) + 0.1
VTT_FSB
VTT_FSB + 0.1
(0.25 x
VTT_FSB) +
0.1
Host GTL+ Output Low
Voltage
—
VTT_FSB – 0.1
—
—
—
—
V
Host GTL+ Output High
Voltage
VTT_FSB
V
VTT_FSBmax *
(1–0.25) /
Rttmin
Host GTL+ Output Low
Current
Rttmin =
47.5 Ω
mA
VOL
Vpad<
Vtt_FSB
<
Host GTL+ Input Leakage
Current
ILEAK_H
—
—
45
μA
CPAD
Host GTL+ Input Capacitance
2.0
—
—
2.5
2.5
pF
pF
Host GTL+ Input Capacitance
(common clock)
CPCKG
0.90
DDR2 System Memory Interface
DDR_VREF –
0.125
VIL(DC)
VIH(DC)
VIL(AC)
VIH(AC)
VOL
DDR2 Input Low Voltage
DDR2 Input High Voltage
DDR2 Input Low Voltage
DDR2 Input High Voltage
DDR2 Output Low Voltage
—
—
—
—
—
—
V
V
V
V
V
DDR_VREF +
0.125
—
DDR_VREF –
0.20
—
DDR_VREF +
0.20
—
0.2 *
VCC_DDR
—
1
VOH
DDR2 Output High Voltage
Input Leakage Current
Input Leakage Current
0.8 * VCC_DDR
—
—
—
—
V
1
4
5
ILeak
ILeak
—
—
±20
±550
µA
µA
284
Datasheet
Electrical Characteristics
Table 27.
Symbol
DC Characteristics
Parameter
Min
Nom
Max
Unit
Notes
DQ/DQS/DQSB DDR2 Input/
Output Pin Capacitance
CI/O
1.0
—
4.0
pF
DDR3 System Memory Interface
DDR_VREF –
0.100
VIL(DC)
VIH(DC)
VIL(AC)
VIH(AC)
VOL
DDR3 Input Low Voltage
DDR3 Input High Voltage
DDR3 Input Low Voltage
DDR3 Input High Voltage
DDR3 Output Low Voltage
—
—
—
—
—
—
V
V
V
V
V
DDR_VREF +
0.100
—
DDR_VREF –
0.175
—
DDR_VREF +
0.175
—
0.2 *
VCC_DDR
—
1
VOH
DDR3 Output High Voltage
Input Leakage Current
Input Leakage Current
0.8 * VCC_DDR
—
—
—
—
V
1
4
5
ILeak
ILeak
—
—
±20
±550
µA
µA
DQ/DQS/DQSB DDR3 Input/
Output Pin Capacitance
CI/O
1.0
—
4.0
pF
1.25V PCI Express* Interface 2.0
Differential Peak to Peak
VTX-DIFF P-P
0.800
—
1.2
V
2
3
Output Voltage
AC Peak Common Mode
VTX_CM-ACp
—
80
—
100
—
20
120
1.2
mV
Output Voltage
ZTX-DIFF-DC
VRX-DIFF p-p
DC Differential TX Impedance
Differential Peak to Peak
Input Voltage
0.175
V
AC Peak Common Mode Input
Voltage
VRX_CM-ACp
—
—
150
mV
Input Clocks
VIL
Input Low Voltage
-0.150
0.660
0.300
N/A
0
0.710
N/A
N/A
—
N/A
0.850
0.550
0.140
3
V
V
VIH
Input High Voltage
VCROSS(ABS)
VCROSS(REL)
CIN
Absolute Crossing Voltage
Range of Crossing Points
Input Capacitance
V
6,7,8
V
1
pF
CL_DATA, CL_CLK
VIL
Input Low Voltage
—
0.427
—
—
—
—
—
0.277
—
V
V
VIH
Input High Voltage
Input Leakage Current
Input Capacitance
ILEAK
CIN
20
μA
pF
—
1.5
Output Low Current (CMOS
Outputs)
@VOL_HI
max
IOL
—
6.0
—
—
—
—
—
1.0
—
mA
mA
V
Output High Current (CMOS
Outputs)
@VOH_HI
min
IOH
VOL
VOH
Output Low Voltage (CMOS
Outputs)
0.06
—
Output High Voltage (CMOS
Outputs)
0.6
V
Datasheet
285
Electrical Characteristics
Table 27.
Symbol
DC Characteristics
Parameter
Min
Nom
Max
Unit
Notes
PWROK, CL_PWROK, RSTIN#
VIL
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
—
2.7
—
—
—
—
—
0.3
—
V
V
VIH
ILEAK
CIN
±1
6.0
mA
pF
—
CL_RST#
VIL
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
—
1.17
—
—
—
—
—
0.13
—
V
V
VIH
ILEAK
CIN
±20
5.0
μA
pF
—
ICH_SYNCB
Output Low Current (CMOS
Outputs)
@VOL_HI
max
IOL
—
-2.0
—
—
—
—
—
2.0
—
mA
mA
V
Output High Current (CMOS
Outputs)
@VOH_HI
min
IOH
VOL
VOH
Output Low Voltage (CMOS
Outputs)
0.33
—
Output High Voltage (CMOS
Outputs)
2.97
V
EXP_SLR, EXP_EN
(0.63 x VTT) –
0.1
VIL
Input Low Voltage
-0.10
0
V
V
(0.63 x
VTT)+0.1
VIH
Input High Voltage
VTT
VTT +0.1
VOL
<
ILEAK
CIN
Input Leakage Current
—
2
—
—
20
μA
Vpad<
Vtt
Input Capacitance
2.5
pF
NOTES:
1.
2.
Determined with 2x MCH Buffer Strength Settings into a 50 Ω to 0.5xVCC_DDR test load.
Specified at the measurement point into a timing and voltage compliance test load as
shown in Transmitter compliance eye diagram of PCI Express* specification and measured
over any 250 consecutive TX Uls.
3.
Specified at the measurement point over any 250 consecutive Uls. The test load shown in
Receiver compliance eye diagram of PCI Express* spec should be used as the RX device
when taking measurements.
4.
5.
6.
Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and
DDR_B_DQ_63:0 signals.
Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0,
DDR_B_DQS_7:0, and DDR_B_DQSB_7:0 signals.
Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals
falling edge of BCLK1.
7.
8.
VHavg is the statistical average of the VH measured by the oscilloscope.
The crossing point must meet the absolute and relative crossing point specifications
simultaneously. Refer to the appropriate processor datasheet for further information.
§ §
286
Datasheet
Ballout and Package Information
12 Ballout and Package
Information
This chapter provides the ballout and package dimensions for the MCH.
12.1
Ballout Information
Figure 11, Figure 12, and Figure 13 provide the MCH ballout as viewed from the top
side of the package. Table 28 provides a ballout list arranged alphabetically by signal
name. Table 29 provides a ballout list arranged numerically by ball number.
Note:
Notes for Figure 11, Figure 12, Figure 13, Table 28 and Table 29.
1. Balls that are listed as RSVD are reserved.
2. Some balls marked as reserved (RSVD) are used in XOR testing. See Chapter 13
for details.
3. Balls that are listed as NC are No Connects.
Datasheet
287
Ballout and Package Information
Figure 11.
MCH Ballout Diagram (Top View Left – Columns 45–31)
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
TEST0
NC
VCC_CKDDR VCC_CKDDR
VCC_CKDDR VCC_CKDDR
VCC_DDR
VSS
VCC_DDR
VSS
VCC_DDR
BE
BD
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
BE
BD
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
DDR_A_
CSB_1
DDR_A_
WEB
DDR_A_
MA_10
DDR3_A_
MA0
DDR_B_
ODT_0
DDR_B_
RASB
DDR_RCOM
PYPD
DDR3_A_
WEB
DDR_A_
BS_0
DDR_A_
MA_0
DDR_B_CSB
_2
VCC_CKDDR VCC_CKDDR
VSS
VCC_DDR
VCC_DDR
DDR3_A_CS DDR_A_ODT DDR_RCOM DDR_A_CAS
DDR_A_
CSB_2
DDR_A_
RASB
DDR_A_
BS_1
DDR_B_
CSB_1
DDR_B_
ODT_1
DDR_B_
ODT_2
DDR_B_
CASB
DDR_A_
MA_1
B_1
_0
PYPU
B
DDR_A_
MA_13
DDR_A_
ODT_2
DDR_A_
CSB_0
DDR3_B_
ODT3
DDR_B_
CSB_3
DDR_B_
MA_13
DDR_B_CSB
_0
DDR_A_CSB
_3
DDR_A_ODT DDR_B_DM DDR_B_DQ_ DDR_B_DQ_
DDR_B_
ODT_3
DDR_B_
CKB_5
DDR_B_
WEB
VCC_DDR
VSS
VSS
VSS
_1
_4
32
36
DDR_A_ODT
_3
DDR_A_DQ_
36
DDR_B_DQ DDR_B_DQ_
DDR_B_
DQ_37
DDR_B_
CK_5
DDR_B_
CKB_2
VSS
VSS
VSS
S_4
33
DDR_A_DQ_
32
DDR_B_
DQ_39
DDR_B_
DQ_38
DDR_B_
DQSB_4
DDR_B_
DQ_44
DDR_A_
CKB_2
DDR_B_
CK_2
DDR_A_
CK_3
VSS
VSS
DDR_A_
DM_4
DDR_A_
DQ_33
DDR_A_
DQ_37
DDR_A_
DQS_4
DDR_A_
DQSB_4
DDR_B_
DQ_35
DDR_B_
DQ_34
DDR_A_
CKB_5
DDR_A_
CK_5
DDR_A_
CK_2
DDR_A_
CK_0
DDR_A_
CKB_3
VSS
VSS
VSS
DDR_A_
DQ_34
DDR_A_DQ_
35
DDR_A_
DQ_38
DDR_A_
DQ_39
DDR_B_
DQ_40
DDR_B_
DQ_45
DDR_A_
CKB_0
DDR_B_
CK_3
VSS
VSS
VSS
VSS
DDR_A_
DQ_45
DDR_A_
DQ_44
DDR_B_
DQSB_5
DDR_B_
DQS_5
DDR_B_DQ_
41
DDR_B_
DQ_42
DDR_B_
CKB_3
VSS
RSVD
VSS
VSS
DDR_A_
DM_5
DDR_A_
DQ_41
DDR_A_
DQ_40
DDR_B_
DQ_47
DDR_B_
DQ_46
DDR_B_
DM_5
DDR_A_
CB_1
DDR_B_
DQ_43
RSVD
DDR_A_DQ
S_5
DDR_A_
DQSB_5
VSS
RSVD
VSS
DDR_A_
DQ_42
DDR_A_
DQ_43
DDR_A_
DQ_47
DDR_A_DQ_
46
DDR_A_DQ
S_8
DDR_A_
DQSB_8
DDR_A_
CB_5
DDR_A_
CB_0
VSS
VSS
DDR_B_
CB_0
DDR_B_
CB_5
DDR_A_
CB_7
DDR_A_
CB_2
DDR_A_
CB_3
DDR_A_
CB_6
DDR_A_
CB_4
VSS
VSS
VSS
VCC_CL
DDR_B_
CB_1
DDR_B_
CB_4
VSS
DDR_B_
DQS_8
DDR_B_
DQSB_8
DDR_B_
DQ_53
DDR_B_
DQ_48
DDR_B_
DQ_52
VSS
VSS
VSS
VSS
VSS
VSS
VCC_CL
VCC_CL
AH
AG
AF
AE
AD
AC
AB
AA
Y
AH
AG
AF
AE
AD
AC
AB
AA
Y
DDR_B_CB_
7
DDR_B_CB_ DDR_B_CB_ DDR_B_CB_ DDR_B_DQ
DDR_B_DQ
SB_6
DDR_B_
DM_6
DDR_B_
DQ_49
VSS
VSS
RSVD
2
6
3
S_6
DDR_A_
DQ_53
DDR_A_DQ_
52
VSS
DDR_A_
DM_6
DDR_A_
DQ_49
DDR_A_
DQ_48
DDR_B_
DQ_54
DDR_B_
DQ_50
DDR_B_
DQ_51
DDR_B_DQ_ DDR_B_DQ_ DDR_B_DQ_
VSS
VSS
RSVD
VSS
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
60
61
55
DDR_A_
DQS_6
DDR_A_
DQSB_6
DDR_A_
DQ_54
DDR_B_
DQ_56
DDR_B_
DQ_57
DDR_B_
DM_7
DDR_B_
DQSB_7
VSS
VSS
VSS
VSS
DDR_A_
DQ_51
DDR_A_
DQ_50
DDR_A_
DQ_60
DDR_A_
DQ_55
DDR_B_
DQ_62
DDR_B_
DQ_63
DDR_B_
DQS_7
VSS
VSS
DDR_A_
DQ_57
DDR_A_
DQ_56
DDR_A_
DM_7
DDR_A_
DQ_61
DDR_B_
DQ_59
DDR_B_
DQ_58
VSS
VSS
VSS
FSB_AB_34
FSB_AB_32
FSB_AB_29
VSS
VSS
DDR_A_
DQSB_7
DDR_A_
DQS_7
DDR_A_
DQ_62
FSB_AB_33
VSS
FSB_AB_35
FSB_AB_31
VSS
DDR_A_
DQ_63
DDR_A_
DQ_58
VSS
FSB_
DDR_A_
DQ_59
FSB_RSB_1 FSB_TRDYB
VSS
FSB_AB_22
FSB_AB_23
FSB_AB_30
VSS
VSS
FSB_AB_25
FSB_AB_27
VSS
RSVD
RSVD
VSS_W31
VCC_CL
BREQ0B
W
W
FSB_
ADSTBB_1
VSS
FSB_AB_28
FSB_HITMB
FSB_BNRB
FSB_DBSYB
VSS
FSB_DRDYB
FSB_AB_24
FSB_AB_26
V
U
V
U
FSB_ADSB
FSB_
DEFERB
FSB_LOCKB
VSS
VSS
FSB_AB_21
VSS
FSB_AB_17
FSB_AB_20
VSS
FSB_AB_18
FSB_AB_10
VSS
FSB_AB_19
VSS
RSVD
RSVD
VSS
VSS
VCCAUX
T
R
P
N
T
R
P
N
FSB_RSB_0
FSB_DB_2
FSB_HITB
FSB_DB_0
FSB_DB_4
FSB_RSB_2
FSB_DB_1
VSS
FSB_AB_14
FSB_AB_16
FSB_AB_9
FSB_AB_11
VSS
FSB_AB_13
FSB_AB_4
FSB_AB_8
FSB_AB_5
VSS
VSS
FSB_AB_12
VSS
FSB_DB_28
VSS
FSB_DB_30
FSB_DB_31
FSB_
ADSTBB_0
FSB_DB_5
FSB_DB_3
FSB_DB_7
FSB_AB_15
M
L
M
L
FSB_
DINVB_0
FSB_
REQB_2
FSB_DB_6
FSB_AB_7
VSS
VSS
FSB_DB_19
VSS
FSB_DB_27 FSB_DB_29
VSS
FSB_
DSTBNB_0
FSB_
REQB_3
VSS
VSS
FSB_AB_6
FSB_DB_21 FSB_DB_24
VSS
FSB_DB_33
K
J
K
J
FSB_
DSTBPB_0
FSB_DB_8
VSS
FSB_DB_10
FSB_
REQB_4
FSB_
VSS
FSB_DB_12
VSS
FSB_DB_9
VSS
FSB_BPRIB
FSB_DB_20
VSS
FSB_DB_25
FSB_DB_34
DSTBPB_1
H
H
FSB_REQB_
1
FSB_
DSTBNB_1
FSB_DB_13
FSB_DB_11
VSS
FSB_DB_22 FSB_DB_23
VSS
VSS
G
F
G
F
FSB_AB_3
FSB_DB_14
VSS
FSB_DB_17 FSB_DB_16
VSS
FSB_DB_48
FSB_DB_63
VSS
FSB_DB_26
VTT_FSB
FSB_DB_32
VTT_FSB
FSB_DINVB
_1
FSB_DB_15 FSB_DB_50
FSB_DB_61
E
D
C
E
D
C
FSB_
VSS
FSB_
CPURSTB
FSB_DB_52 FSB_DB_53
FSB_DB_57 FSB_DB_54
VSS
FSB_DB_59
VSS
VSS
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
DSTBNB_3
FSB_
VSS
FSB_
DSTBPB_3
VSS
NC
FSB_DB_51
FSB_DB_60 FSB_DB_58
REQB_0
FSB_
DINVB_3
VSS
FSB_DB_18 FSB_DB_55
FSB_DB_56
FSB_DB_49
FSB_DB_62
VTT_FSB
VTT_FSB
B
A
B
A
TEST3
NC
VSS
VSS
VSS
VSS
VTT_FSB
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
288
Datasheet
Ballout and Package Information
Figure 12.
MCH Ballout Diagram (Top View Middle – Columns 30–16)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DDR_B_
MA_8
DDR_A_
DQ_19
VSS
VCC_DDR
VSS
VCC_DDR
VSS
VCC_DDR
VSS
BE
BE
BD
BC
BB
BA
AY
AW
DDR_A_
MA_6
DDR_A
DDR_A_
CKE_0
DDR_B_
MA_4
DDR_B_
CKE_1
DDR_B_
CKE_0
_MA_11
BD
DDR_A_
MA_8
DDR_A_
CKE_3
DDR_B_
MA_1
DDR_B_
MA_14
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VSS
BC
DDR_A_
MA_2
DDR_A_
MA_3
DDR_A_
MA_5
DDR_A_
MA_12
DDR_A_
BS_2
DDR_A_
CKE_2
DDR_B_
BS_0
DDR3_DRA
MRSTB
DDR_B_
MA_2
DDR_B_
MA_5
DDR_B_
MA_6
DDR_B_
MA_9
DDR_B_
BS_2
DDR_B_
CKE_2
DDR_A_
DQ_18
BB
BA
AY
AW
DDR_A_
MA_4
DDR_A_
MA_9
DDR_A_MA_
14
DDR_B_
MA_3
DDR_B_
MA_11
DDR_B_CKE
_3
DDR_B_
CK_4
DDR_B_
CKB_4
DDR_A_
MA_7
DDR_B_
DM_3
DDR_A_
CKE_1
DDR_B_
MA_0
DDR_A_
DQ_25
DDR_B_
MA_7
DDR_B_
MA_12
DDR_B_
DQ_16
VCC_DDR
DDR_B_
CK_0
DDR_B_
DQ_24
DDR_B_
MA_10
DDR_B_
BS_1
DDR_A_
DQ_31
DDR_A_
DQ_29
DDR_B_
DM_2
VSS
VSS
VSS
VSS
VSS
VSS
DDR_B_
CKB_0
DDR_B_
DQ_27
DDR_B_
DQ_25
DDR_A_
DQSB_3
DDR_A_
DQ_28
DDR_B_
DQ_17
VSS
VSS
VSS
AV
AU
AV
AU
DDR_B_
DQ_26
DDR_B_
DQ_30
DDR_A_
DQ_27
DDR_A_
DQS_3
DDR_B_
DQ_19
DDR_B_
DQ_22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT
AR
AP
AN
AT
AR
AP
AN
DDR_B_
CK_1
DDR_B_
DQS_3
DDR_B_
DQSB_3
DDR_B_
DQ_23
DDR_B_
DQ_21
VSS
VSS
VSS
VSS
VSS
DDR_B_
CKB_1
DDR_B_
DQ_31
DDR_B_
DQ_29
DDR_A_
DM_3
DDR_B_
DQ_18
DDR_B_
DQSB_2
VSS
VSS
VSS
DDR_A_
CK_1
DDR_A_
CK_4
DDR_B_
DQ_28
DDR_A_
DQ_26
DDR_A_
DQ_30
DDR_A_
DQ_24
DDR_B_
DQS_2
DDR_B_
DQ_20
RSVD
RSVD
DDR_A_
CKB_1
DDR_A_
CKB_4
VCC_CL
VCC_CL
RSVD
VSS
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VSS
PWROK
VCC_CL
RSTINB
VCC_CL
VSS
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
RSVD
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCCAUX
VCC_CL
RSVD
RSVD
VCC
VCC_CL
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC_CL
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC_CL
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC_CL
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC_CL
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC_CL
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC_CL
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC_CL
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC_CL
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC_CL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_CL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W
W
VCC
V
V
VCC
U
U
T
T
VCCAUX
VCCAUX
VCCAUX
VSS
VCCAUX
VSS
VCCAUX
VSS
VCCAUX
VSS
RSVD
VSS
VSS
RSVD
VCC
VSS
VCC
R
R
HPL_
CLKINN
HPL_CLKINP
RSVD
RSVD_P19
ICH_SYNCB
P
N
M
P
N
M
FSB_DINVB
_2
FSB_
DSTBPB_2
FSB_DB_37
FSB_DB_35
VSS
FSB_DB_42
VSS
VSS
VSS
VSS
RSVD
VSS
RSVD
VSS
VSS
FSB_
DSTBNB_2
VSS
VTT_FSB
BSEL0
ALLZTEST
RSVD_M19
RSVD
VCC3_3_
L16
FSB_DB_36
VSS
FSB_DB_41
FSB_DB_40
VTT_FSB
VTT_FSB
FSB_DB_43 FSB_DB_44
VSS
VSS
XORTEST
RSVD
VSS
RSVD
RSVD
VSS
L
K
J
L
K
J
VTT_FSB
FSB_DB_46
RSVD
EXP_SLR
RSVD_K16
FSB_DB_39
FSB_DB_38
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
FSB_DB_45
FSB_DB_47
VSS
VSS
VSS
VSS
VSS
RSVD
RSVD
TCEN
VSS
VSS
VSS
RSVD_H16
H
H
VCC3_3_
G16
MTYPE
G
F
G
F
VTT_FSB
VTT_FSB
VCC_E25
VSS_F22
BSEL1
VSS
RSVD
VSS
BSEL2
VSS
VTT_FSB
VSS
FSB_DVREF
PEG_TXN_0
VSS
E
E
FSB_
ACCVREF
EXP_CLKIN
N
VTT_FSB
VSS
FSB_SCOMP
VCCA_HPL
VCCA_HPL
VSS_D24
VSS_C24
VSS
VSS_D22
VSS
VSS_D21
VCCA_EXP
VSS
EXP_CLKINP
PEG_TXP_0
VCCR_EXP
D
D
FSB_
SCOMPB
FSB_RCOMP
VSS_C23
VCC_C18
C
B
C
B
VSS
29
VCCA_MPL
27
VCC_B25
25
VSS_B21
21
RSVD
19
VSS_B17
17
VCCAPLL_
EXP
VTT_FSB
30
FSB_SWING
28
VSS
26
VSS_A24
24
VCC3_3
23
VSS
22
VSS
18
PEG_RXP_0
16
A
A
20
Datasheet
289
Ballout and Package Information
Figure 13.
MCH Ballout Diagram (Top View Left – Columns 15–1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DDR_A_
DQ_11
DDR_A_
DQ_3
VSS
VSS
VSS
VSS
NC
TEST1
BE
BE
BD
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
DDR_A_
DDR_A_
DQ_16
DDR_A_
DQ_14
DDR_A_
DQ_8
DDR_A_
DQ_6
DDR_A_
DQ_1
DDR_A_DQ_
4
VSS
RSVD
VSS
NC
DQ_22
BD
BC
BB
BA
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
DDR_A_
DM_2
DDR_A_
DM_1
DDR_A_
DQ_13
DDR_A_DQ
SB_0
DDR_A_
DQ_0
VSS
VSS
VSS
VSS
DDR_A_
DQ_23
DDR_A_
DQ_17
DDR_A_
DQ_21
DDR_A_
DQ_10
DDR_A_
DQ_15
DDR_A_
DQ_9
DDR_A_DQ_
2
DDR_A_
DQ_7
DDR_A_
DM_0
DDR_A_
DQ_5
VSS_BB3
DDR_A_
DQS_2
DDR_A_
DQ_20
DDR_A_
DQS_1
DDR_A_
DQ_12
DDR_A_DQ
S_0
VSS_BA5
VSS_BA4
DDR_A_
DQSB_2
DDR_B_
DQ_9
DDR_B_
DQ_8
DDR_A_
DQSB_1
DDR_B_
DM_0
DDR_B_
DQ_1
DDR_
RCOMPXPD
DDR_
RCOMPXPU
VSS
VSS_AY3
VSS_AY1
VSS
DDR_B_
DQ_13
DDR_B_
DQ_12
DDR_B_
DQ_7
DDR_B_
DQS_0
DDR_B_
DQ_0
DDR_B_
DQ_5
VSS
VSS
VSS
VSS
VSS_AW2
DDR_B_
DQ_11
DDR_B_
DQ_4
VSS
VSS
VSS
VSS
DDR_VREF
VSS
VSS
VSS
PEG2_TXP_
14
VCCA_EXP2
DDR_B_
DQ_10
DDR_B_
DM_1
DDR_B_
DQ_3
DDR_B_
DQ_2
DDR_B_
DQSB_0
DDR_
RCOMPVOL
DDR_RCOM
PVOH
PEG2_
TXP_13
PEG2_TXN_
14
VSS
VSS
VSS
VSS
DDR_B_
DQS_1
DDR_B_
DQSB_1
DDR_B_
DQ_6
VCCAPLL_
EXP2
PEG2_
TXN_13
PEG2_TXP_
12
VSS
VSS
VSS
VSS
DDR_B_
DQ_15
PEG2_
RXN_15
PEG2_
RXP_15
PEG2_
TXP_15
PEG2_
TXN_15
PEG2_
TXP_11
PEG2_TXN_
12
VSS
RSVD
RSVD
VCCR_EXP
DDR_B_
DQ_14
DDR3_DRA
M_PWROK
EXP2_
COMPI
EXP2_
COMPO
PEG2_
TXN_11
PEG2_TXP_
10
RSVD
VSS
VSS
VSS
PEG2_
TXP_9
PEG2_TXN_
10
RSVD
VSS
PEG2_
RXP_13
PEG2_
RXN_13
PEG2_
RXN_14
PEG2_
RXP_14
PEG2_
TXN_9
PEG2_TXP_
8
CL_PWROK
VSS
VSS
VSS
VSS
PEG2_
RXN_12
PEG2_
RXP_12
PEG2_
TXP_7
PEG2_TXN_
8
CL_DATA
CL_CLK
VSS
VSS
VSS
VSS
VCCR_EXP
AK
AJ
AK
AJ
PEG2_
TXN_7
PEG2_TXP_
6
VSS
PEG2_
RXN_9
PEG2_
PEG2_
PEG2_
PEG2_
PEG2_
TXP_5
PEG2_TXN_
6
VCC_CL
VCC
VCC_CL
VSS
VSS
VSS
VSS
RXP_10
RXN_10
RXP_11
RXN_11
AH
AG
AF
AE
AD
AC
AB
AH
AG
AF
AE
AD
AC
AB
PEG2_
RXP_9
PEG2_
TXN_5
PEG2_TXP_
4
CL_VREF
VSS
CL_RSTB
VSS
VSS
VSS
VSS
PEG2_TXP_
3
PEG2_TXN_
4
VCCR_EXP
EXP2_
CLKINP
PEG2_
RXP_6
PEG2_
RXN_7
PEG2_
RXP_7
PEG2_
RXP_8
PEG2_
RXN_8
PEG2_
TXN_3
PEG2_TXP_
2
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCC
VSS
VSS
VCC_EXP
VSS
VSS
EXP2_
CLKINN
PEG2_
RXN_6
PEG2_
TXP_1
PEG2_TXN_
2
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VSS
VSS
VSS
PEG2_
RXP_3
PEG2_
RXP_4
PEG2_
RXN_4
PEG2_
RXN_5
PEG2_
RXP_5
PEG2_
TXN_1
VSS
VSS
VCCR_EXP
VCC_EXT_
PLL
PEG2_
RXN_3
PEG2_TXP_
0
PEG2_TXN_
0
VCCR_EXP
VCCR_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VSS
VCC_EXP
VCC_EXP
VCC_EXP
PEG2_
RXN_0
PEG2_
RXN_1
PEG2_
RXP_1
PEG2_RXN_ PEG2_RXP_
VCCR_EXP
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
2
2
AA
Y
AA
Y
VCC_EXP
VCC_EXP
PEG2_
RXP_0
VCCR_EXP
VCCR_EXP
VSS
VSS
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VSS
VCC_EXP
VSS
VCC_EXP
VCC_EXP
W
V
U
T
W
V
U
T
VCCR_EXP
RSVD
DMI_TXN_3
DMI_TXP_3
DMI_RXP_3 DMI_RXN_3
VCC_EXP
VCC_EXP
VCC_EXP
VSS
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN_2
VSS
VCC_EXP
VCCR_EXP
VCCR_EXP
VSS
VSS
VSS
RSVD
VSS
VSS
VSS
EXP_COMPO
EXP_COMPI
DMI_RXN_1 DMI_RXP_1
VSS
DMI_TXN_0 DMI_RXN_2
VSS
DMI_TXP_0
DMI_TXP_2
R
P
R
P
DMI_RXP_2 DMI_TXN_1
VSS
PEG_
RXN_15
PEG_
RXP_15
VCC_N15
VSS_M15
VSS
PEG_RXP_4
PEG_RXN_4
RSVD
VSS
RSVD
VSS
VSS
VSS
VSS
VSS
DMI_RXP_0
DMI_TXP_1
N
M
L
N
M
L
PEG_
RXP_12
PEG_
RXN_13
PEG_
RXP_13
PEG_
TXP_15
VSS
DMI_RXN_0
VSS
VCCR_EXP
PEG_RXN_1
2
PEG_
TXP_14
PEG_
TXN_15
PEG_RXP_3 PEG_RXN_6
VSS
VSS
VSS
PEG_
RXN_11
PEG_
RXP_11
PEG_
TXN_14
PEG_
RXP_14
VSS
PEG_RXN_3
VSS
PEG_RXP_6
VSS
VSS
K
J
K
J
PEG_
TXP_13
PEG_RXN_1
4
VSS
PEG_
PEG_
RSVD_H15
RSVD_G15
VSS
PEG_RXP_2
PEG_RXP_5
VSS
VSS
PEG_RXN_7
PEG_RXP_7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCR_EXP
TXN_13
TXP_12
H
G
F
H
G
F
PEG_
PEG_RXN_2 PEG_RXN_5
PEG_RXN_9
VSS
VSS
TXN_12
PEG_
PEG_
TXP_10
VSS
PEG_TXP_2
VSS
VSS
VSS
PEG_RXP_9
VSS
TXP_11
PEG_
TXN_11
PEG_TXP_1
VSS
PEG_TXN_4
VSS
PEG_TXN_6
PEG_RXP_8
VSS
E
D
E
D
PEG_
TXN_10
PEG_
RXP_10
PEG_TXN_1
PEG_RXN_1
PEG_TXN_2
VCCR_EXP
PEG_TXP_4
PEG_TXN_5
PEG_TXP_6
VCCR_EXP
VSS
PEG_RXN_8
VSS
PEG_
RXN_10
VSS
PEG_TXP_8
PEG_TXN_8
PEG_TXN_9
VSS
VSS
NC
C
B
A
C
B
A
PEG_RXN_0
PEG_RXP_1
PEG_TXP_3
PEG_TXP_5
PEG_TXP_7
PEG_TXP_9
VSS
VSS
VSS
PEG_TXN_3
VSS
PEG_TXN_7
VSS
TEST2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
290
Datasheet
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
ALLZTEST
M21
DDR_A_DM_4
DDR_A_DM_5
DDR_A_DM_6
DDR_A_DM_7
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQ_40
AU44
AN44
AE44
AB40
BC4
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
DDR_A_DQS_0
DDR_A_DQS_1
DDR_A_DQS_2
DDR_A_DQS_3
DDR_A_DQS_4
DDR_A_DQS_5
DDR_A_DQS_6
DDR_A_DQS_7
DDR_A_DQS_8
DDR_A_DQSB_0
DDR_A_DQSB_1
DDR_A_DQSB_2
DDR_A_DQSB_3
DDR_A_DQSB_4
DDR_A_DQSB_5
DDR_A_DQSB_6
DDR_A_DQSB_7
DDR_A_DQSB_8
DDR_A_MA_0
AN42
AL44
AL42
AP42
AP45
AL40
AL41
AE41
AE42
AC42
AC45
AF42
AF45
AD40
AC39
AB42
AB43
Y42
BSEL0
M22
BSEL1
F21
BSEL2
F18
CL_CLK
AK14
AK15
AL13
AG11
AG14
BC37
BB36
BB26
BB41
AL33
AN35
AK38
AK35
AK33
AL34
AK34
AK39
AT33
AN28
AT34
AV31
AN27
AT35
AR33
AM28
AV35
AT31
AM27
AT36
BD25
AY24
BB25
BC24
BA40
BD42
BB39
AY43
BB5
CL_DATA
BD4
CL_PWROK
BB8
CL_RSTB
BE8
CL_VREF
BD3
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_A_CASB
DDR_A_CB_0
DDR_A_CB_1
DDR_A_CB_2
DDR_A_CB_3
DDR_A_CB_4
DDR_A_CB_5
DDR_A_CB_6
DDR_A_CB_7
DDR_A_CK_0
DDR_A_CK_1
DDR_A_CK_2
DDR_A_CK_3
DDR_A_CK_4
DDR_A_CK_5
DDR_A_CKB_0
DDR_A_CKB_1
DDR_A_CKB_2
DDR_A_CKB_3
DDR_A_CKB_4
DDR_A_CKB_5
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3
DDR_A_DM_0
DDR_A_DM_1
DDR_A_DM_2
DDR_A_DM_3
BB4
BD7
BB7
BD9
BB10
BB12
BE12
BA9
BC9
BD11
BB11
BD13
BB14
BB16
BE16
BA13
BB13
BD15
BB15
AN19
AY21
AN22
AT22
AV19
AW19
AN21
AW22
AV42
AU43
AR44
AR42
AW42
AU41
AR41
AR40
AN41
W42
AC40
AB39
AA41
Y45
BA6
BA11
BA15
AT21
AT43
AM43
AD43
AA42
AL38
BC6
AY11
AY15
AV21
AT42
AM42
AD42
AA44
AL36
BC36
BB31
BB30
BB29
BC10
BC14
AP21
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
Datasheet
291
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
DDR_A_RASB
DDR_A_WEB
BA29
BB28
BD29
AY27
BC28
BA27
BD37
BD27
BB27
BA42
BA25
BB43
AY41
BA41
AW44
BB38
BD39
BB24
AW23
BB18
BB32
AK45
AJ44
DDR_B_CSB_0
DDR_B_CSB_1
DDR_B_CSB_2
DDR_B_CSB_3
DDR_B_DM_0
DDR_B_DM_1
DDR_B_DM_2
DDR_B_DM_3
DDR_B_DM_4
DDR_B_DM_5
DDR_B_DM_6
DDR_B_DM_7
DDR_B_DQ_0
DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7
DDR_B_DQ_8
DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15
DDR_B_DQ_16
DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQ_24
DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31
DDR_B_DQ_32
BA31
BB35
BC32
BA35
AY8
DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39
DDR_B_DQ_40
DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47
DDR_B_DQ_48
DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55
DDR_B_DQ_56
DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63
DDR_B_DQS_0
DDR_B_DQS_1
DDR_B_DQS_2
DDR_B_DQS_3
DDR_B_DQS_4
DDR_B_DQS_5
DDR_B_DQS_6
DDR_B_DQS_7
DDR_B_DQS_8
DDR_B_DQSB_0
DDR_B_DQSB_1
DDR_B_DQSB_2
DDR_B_DQSB_3
DDR_B_DQSB_4
AW38
AT38
AT40
AY38
AW36
AV39
AV40
AR36
AP36
AP35
AN33
AV36
AR34
AN39
AN40
AH34
AG33
AE39
AE38
AH33
AH36
AE40
AE33
AD39
AD36
AB32
AB38
AE35
AE34
AC36
AC34
AW10
AR13
AN18
AR25
AW39
AP39
AG39
AC33
AH43
AT10
AR12
AP16
AR24
AV38
AT13
AW16
AY25
AY40
AN36
AG35
AD35
AW8
AY7
AT11
AT12
AV8
DDR_B_BS_0
DDR_B_BS_1
DDR_B_BS_2
DDR_B_CASB
DDR_B_CB_0
DDR_B_CB_1
DDR_B_CB_2
DDR_B_CB_3
DDR_B_CB_4
DDR_B_CB_5
DDR_B_CB_6
DDR_B_CB_7
DDR_B_CK_0
DDR_B_CK_1
DDR_B_CK_2
DDR_B_CK_3
DDR_B_CK_4
DDR_B_CK_5
DDR_B_CKB_0
DDR_B_CKB_1
DDR_B_CKB_2
DDR_B_CKB_3
DDR_B_CKB_4
DDR_B_CKB_5
DDR_B_CKE_0
DDR_B_CKE_1
DDR_B_CKE_2
DDR_B_CKE_3
AW6
AR11
AW11
AY12
AY13
AT15
AV15
AW12
AW13
AN15
AP15
AY16
AV16
AP19
AT19
AN16
AR16
AT18
AR18
AW25
AV25
AT27
AV27
AN24
AP24
AT25
AP27
AY39
AG42
AG40
AJ42
AK42
AG41
AG44
AW30
AR28
AV33
AR31
AY30
AW34
AV30
AP28
AW33
AP31
AY28
AY34
BD17
BD19
BB17
BA17
292
Datasheet
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
DDR_B_DQSB_5
DDR_B_DQSB_6
DDR_B_DQSB_7
DDR_B_DQSB_8
DDR_B_MA_0
DDR_B_MA_1
DDR_B_MA_2
DDR_B_MA_3
DDR_B_MA_4
DDR_B_MA_5
DDR_B_MA_6
DDR_B_MA_7
DDR_B_MA_8
DDR_B_MA_9
DDR_B_MA_10
DDR_B_MA_11
DDR_B_MA_12
DDR_B_MA_13
DDR_B_MA_14
DDR_B_ODT_0
DDR_B_ODT_1
DDR_B_ODT_2
DDR_B_ODT_3
DDR_B_RASB
DDR_B_WEB
AP40
AG38
AD33
AH42
AY22
BC22
BB22
BA21
BD21
BB21
BB20
AY19
BE20
BB19
AW24
BA19
AY18
BA33
BC18
BD33
BB34
BB33
AY35
BD31
AY31
AT6
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
EXP_CLKINN
EXP_CLKINP
EXP_COMPI
EXP_COMPO
EXP_SLR
P4
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35
FSB_ACCVREF
FSB_ADSB
FSB_ADSTBB_0
FSB_ADSTBB_1
FSB_BNRB
FSB_BPRIB
FSB_BREQ0B
FSB_CPURSTB
FSB_DB_0
AB34
W36
AA33
AA35
AA40
AB35
AA38
D27
U44
M40
V34
U42
H38
W44
D35
P42
V7
R6
P3
T1
V11
R7
N2
R2
V10
D18
D19
R10
T10
K19
AD14
AE14
AN10
AN8
F43
M38
M36
K38
L40
N36
N40
R36
N39
N34
N38
R39
K42
R35
T40
T36
T34
T38
P43
W38
V38
V39
W34
V35
W33
V43
EXP2_CLKINN
EXP2_CLKINP
EXP2_COMPI
EXP2_COMPO
FSB_AB_3
FSB_DB_1
N41
N44
M42
N42
M45
L44
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_AB_4
FSB_DB_5
FSB_AB_5
FSB_DB_6
FSB_AB_6
FSB_DB_7
L42
FSB_AB_7
FSB_DB_8
J43
FSB_AB_8
FSB_DB_9
H42
J41
DDR_RCOMPVOH
DDR_RCOMPVOL
DDR_RCOMPXPD
DDR_RCOMPXPU
DDR_RCOMPYPD
DDR_RCOMPYPU
DDR_VREF
FSB_AB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
AT7
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
G42
H45
G44
F41
AY6
AY5
BC42
BB42
AV7
E42
F38
DDR3_A_CSB_1
DDR3_A_MA0
DDR3_A_WEB
DDR3_B_ODT3
BB44
BD35
BC40
BA37
F39
B43
L36
G38
K35
G36
G35
K34
H33
F33
DDR3_DRAM_PWR
OK
AN11
DDR3_DRAMRSTB BB23
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
M4
T8
R5
V6
N5
T7
L34
N33
L33
Datasheet
293
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63
FSB_DBSYB
FSB_DEFERB
FSB_DINVB_0
FSB_DINVB_1
FSB_DINVB_2
FSB_DINVB_3
FSB_DRDYB
FSB_DSTBNB_0
FSB_DSTBNB_1
FSB_DSTBNB_2
FSB_DSTBNB_3
N31
M31
F31
K31
H31
M30
L30
N30
G30
H30
K28
L28
N24
L25
L24
H24
K24
G24
F35
A38
E41
C42
D44
D43
D38
B42
B39
D39
C36
D36
C37
E37
B35
E35
T42
T39
L41
E40
N28
B37
U41
K43
G34
M25
D41
FSB_DSTBPB_0
FSB_DSTBPB_1
FSB_DSTBPB_2
FSB_DSTBPB_3
FSB_DVREF
FSB_HITB
J44
PEG_RXN_14
PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
J2
H34
N25
C40
E27
R42
V42
T45
C26
C44
G40
L39
K36
H39
R44
W41
R41
D28
C28
A28
W40
P30
P28
P16
G19
BE2
BD45
BD1
B45
B1
N10
A16
B13
H13
L13
N13
H12
K11
G10
E6
FSB_HITMB
FSB_LOCKB
FSB_RCOMP
FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_SCOMP
FSB_SCOMPB
FSB_SWING
FSB_TRDYB
HPL_CLKINN
HPL_CLKINP
ICH_SYNCB
MTYPE
F7
D2
K7
M11
M7
K3
N8
E17
D14
D12
A12
E11
C10
E9
NC
A8
NC
C4
NC
B4
NC
D3
NC
E4
NC
A44
B15
C14
G13
K13
M13
G12
L12
H10
D5
G2
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
H4
K4
L2
D16
E15
E13
B11
D10
B9
G6
D8
C2
B7
K8
C6
L10
M8
B3
F3
294
Datasheet
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
PEG2_RXN_0
PEG2_RXN_1
PEG2_RXN_2
PEG2_RXN_3
PEG2_RXN_4
PEG2_RXN_5
PEG2_RXN_6
PEG2_RXN_7
PEG2_RXN_8
PEG2_RXN_9
PEG2_RXN_10
PEG2_RXN_11
PEG2_RXN_12
PEG2_RXN_13
PEG2_RXN_14
PEG2_RXN_15
PEG2_RXP_0
PEG2_RXP_1
PEG2_RXP_2
PEG2_RXP_3
PEG2_RXP_4
PEG2_RXP_5
PEG2_RXP_6
PEG2_RXP_7
PEG2_RXP_8
PEG2_RXP_9
PEG2_RXP_10
PEG2_RXP_11
PEG2_RXP_12
PEG2_RXP_13
PEG2_RXP_14
PEG2_RXP_15
PEG2_TXN_0
PEG2_TXN_1
PEG2_TXN_2
PEG2_TXN_3
PEG2_TXN_4
PEG2_TXN_5
PEG2_TXN_6
PEG2_TXN_7
F5
PEG2_TXN_8
PEG2_TXN_9
PEG2_TXN_10
PEG2_TXN_11
PEG2_TXN_12
PEG2_TXN_13
PEG2_TXN_14
PEG2_TXN_15
PEG2_TXP_0
PEG2_TXP_1
PEG2_TXP_2
PEG2_TXP_3
PEG2_TXP_4
PEG2_TXP_5
PEG2_TXP_6
PEG2_TXP_7
PEG2_TXP_8
PEG2_TXP_9
PEG2_TXP_10
PEG2_TXP_11
PEG2_TXP_12
PEG2_TXP_13
PEG2_TXP_14
PEG2_TXP_15
PWROK
AK1
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_G15
RSVD_H15
RSVD_M19
RSVD_P19
TCEN
TEST0
TEST1
TEST2
TEST3
VCC
V12
H1
AL5
T33
J5
AM3
AN5
AP1
T12
L5
R33
M1
R22
AA13
AA11
AA7
AR5
R19
AT3
P21
AP6
N21
AB12
AC10
AC7
AD12
AE11
AE6
AB3
N18
AD4
AE2
N12
N11
AF4
M16
L19
AG2
AH4
AJ2
K22
AH13
AH10
AH6
AK13
AL10
AL7
K21
AK4
H21
AL2
G22
F19
AM4
AN2
AP4
B19
G15
H15
AP11
W12
AA10
AA6
AR2
AT4
M19
P19
AU2
AP7
G21
BE45
BE1
AC13
AC11
AC6
AE13
AE10
AE7
AM19
AM18
L18
RSTINB
RSVD
A2
RSVD
BC2
A45
RSVD
AP34
AP12
AN31
AN30
AN25
AN13
AN12
AM32
AM25
AM14
AL28
AH28
AG32
AG28
AD32
W32
V32
AH26
AH24
AH22
AH20
AH19
AH18
AH17
AG27
AG25
AG23
AG21
AG19
AG18
AG17
AG15
AF28
AF26
RSVD
VCC
AG12
AH11
AH7
AK12
AL11
AL6
RSVD
VCC
RSVD
VCC
RSVD
VCC
RSVD
VCC
RSVD
VCC
RSVD
VCC
AP10
AB1
RSVD
VCC
RSVD
VCC
AC4
AD3
AE5
RSVD
VCC
RSVD
VCC
RSVD
VCC
AF1
RSVD
VCC
AG5
AH3
AJ5
RSVD
VCC
RSVD
VCC
RSVD
VCC
Datasheet
295
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF24
AF22
AF20
AF18
AF17
AE28
AE27
AE25
AE23
AE21
AE19
AE18
AE17
AD28
AD26
AD24
AD22
AD20
AD18
AD17
AC28
AC27
AC25
AC23
AC21
AC19
AC18
AC17
AB28
AB26
AB24
AB22
AB20
AB18
AB17
AB15
AA28
AA27
AA25
AA23
AA21
AA19
AA18
AA17
Y28
VCC
Y26
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
AM23
AM22
AL30
AL27
AL25
AL24
AL23
AL22
AL21
AL19
AL18
AL16
AK31
AJ29
AJ28
AJ27
AJ26
AJ25
AJ24
AJ23
AJ22
AJ21
AJ20
AJ19
AJ18
AJ17
AH31
AH29
AH15
AH14
AG31
AG29
AF29
AE31
AE29
AD31
AD29
AC31
AC29
AB31
AB29
AA31
AA29
Y29
VCC
Y24
VCC
Y22
VCC
Y20
VCC
Y18
VCC
Y17
VCC
W28
W27
W25
W23
W21
W19
W18
W17
V28
V26
V24
V22
V20
V18
V17
U28
U27
U26
U25
U24
U23
U22
U21
U20
U19
U18
U17
R18
R16
B25
C18
BE44
BE43
BD44
BD43
BC45
BC44
V31
AM30
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_B25
VCC_C18
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CL
VCC_CL
W29
296
Datasheet
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VCC_CL
V29
BE40
BE36
BE32
BE28
BE24
BE22
BC38
BC34
BC30
BC26
BC23
BC20
AY45
AY23
E25
AD11
AD10
AD8
AD7
AB11
AB10
AB8
AB7
AB6
AB4
AA5
AA4
AA2
Y4
VCC_EXP
VCC_EXP
VCC_EXT_PLL
VCC_N15
VCC3_3
T4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BE30
BE26
BE23
BE18
BE14
BE10
BE6
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_E25
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
T3
AB13
N15
A23
G16
L16
VCC3_3_G16
VCC3_3_L16
VCCA_EXP
VCCA_EXP2
VCCA_HPL
VCCA_HPL
VCCA_MPL
VCCAPLL_EXP
VCCAPLL_EXP2
VCCAUX
D20
AU5
D26
D25
B27
A20
AR10
U29
T31
R30
R28
R27
R25
R24
R23
AP3
AK3
AF3
AE15
AD15
AC15
AC3
AB14
AA15
AA14
W15
V15
V14
T15
T14
M3
BE3
BD2
BC43
BC16
BC12
BC8
BC3
BC1
VCCAUX
BB2
VCCAUX
AY36
AY33
AY10
AW40
AW35
AW31
AW28
AW27
AW21
AW18
AW15
AW7
AW4
AV45
AV43
AV34
AV28
AV24
AV23
AV22
AV18
AV13
AV12
AV11
AV10
AV6
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VCCR_EXP
VSS
Y3
Y1
W11
W10
W8
W7
W5
W4
W2
H3
V4
C16
C12
C8
V3
V1
U5
B2
AV4
U4
VSS
BE38
BE34
AV3
U2
VSS
AV1
Datasheet
297
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL39
AL35
AL12
AL8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF21
AF19
AE36
AE32
AE26
AE24
AE22
AE20
AE12
AE8
AT45
AT39
AT30
AT28
AT24
AT23
AT16
AT8
AL4
AK43
AK40
AK36
AK32
AK11
AK10
AK8
AT1
AR39
AR38
AR35
AR30
AR27
AR23
AR22
AR21
AR19
AR15
AR8
AE4
AD45
AD38
AD34
AD27
AD25
AD23
AD21
AD19
AD13
AD6
AK7
AK6
AJ41
AJ4
AH45
AH40
AH39
AH38
AH35
AH32
AH27
AH25
AH23
AH21
AH12
AH8
AR7
AD1
AR6
AC43
AC38
AC35
AC32
AC26
AC24
AC22
AC20
AC14
AC12
AC8
AR4
AP43
AP38
AP33
AP30
AP25
AP23
AP22
AP18
AP13
AP8
AH1
AG36
AG34
AG26
AG24
AG22
AG20
AG13
AG10
AG8
AC1
AN38
AN34
AN23
AN7
AB45
AB36
AB33
AB27
AB25
AB23
AB21
AB19
AA39
AA36
AA34
AN6
AG7
AN4
AG6
AM45
AM24
AM21
AM16
AM1
AG4
AF43
AF27
AF25
AF23
298
Datasheet
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
Signal Name
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA32
AA26
AA24
AA22
AA20
AA12
AA8
Y43
Y27
Y25
Y23
Y21
Y19
W39
W35
W26
W24
W22
W20
W14
W13
W6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R11
R8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K45
K40
K39
K33
K30
K23
K18
K15
K12
K10
K6
R4
P45
P32
P27
P25
P24
P23
P22
P18
P14
P1
K1
J3
N35
N27
N23
N22
N19
N16
N7
H43
H40
H36
H35
H23
H22
H19
H18
H11
H8
N6
N4
V45
V40
V36
V33
V27
V25
V23
V21
V19
V13
V8
M43
M39
M35
M34
M33
M28
M24
M23
M18
M12
M10
M6
H7
H6
G39
G33
G31
G23
G18
G11
G8
G7
T43
T35
T32
T13
T11
T6
G4
L38
L35
L31
L23
L21
L15
L11
L8
F45
F40
F36
F34
F24
F23
F16
F15
F13
F12
F11
R40
R38
R34
R21
R13
R12
L7
L6
L4
Datasheet
299
Ballout and Package Information
Table 28.
MCH
Table 28.
MCH
Ballout Sorted By Name
Ballout Sorted By Name
Signal Name
Ball #
Signal Name
Ball #
VSS
F10
F8
VSS_B21
VSS_BA4
VSS_BA5
VSS_BB3
VSS_C23
VSS_C24
VSS_D21
VSS_D22
VSS_D24
VSS_F22
VSS_H16
VSS_K16
VSS_M15
VSS_W31
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
XORTEST
B21
BA4
BA5
BB3
C23
C24
D21
D22
D24
F22
H16
K16
M15
W31
M27
L27
K27
K25
H28
H27
H25
G28
G27
G25
F30
F28
F27
F25
E33
E31
E29
D33
D32
D31
D30
C32
B33
B31
A32
A30
L22
VSS
VSS
F6
VSS
F1
VSS
E21
E19
E5
VSS
VSS
VSS
D42
D34
D29
D23
D17
D15
D13
D11
D7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D4
VSS
C45
C43
C38
C34
C30
C22
C20
C9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C3
VSS
C1
VSS
B44
B29
A43
A40
A36
A34
A26
A22
A18
A14
A10
A6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A3
VSS_A24
VSS_AW2
VSS_AY1
VSS_AY3
VSS_B17
A24
AW2
AY1
AY3
B17
NOTE: See list of notes at
beginning of chapter.
300
Datasheet
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
BE45
BE44
BE43
BE40
BE38
BE36
BE34
BE32
BE30
BE28
BE26
BE24
BE23
BE22
BE20
BE18
BE16
BE14
BE12
BE10
BE8
TEST0
BD7
DDR_A_DQ_6
DDR_A_DQ_1
DDR_A_DQ_4
VSS
BB31
BB30
BB29
BB28
BB27
BB26
BB25
BB24
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_5
DDR_A_MA_12
DDR_A_BS_2
DDR_A_CKE_2
DDR_B_BS_0
VCC_CKDDR
VCC_CKDDR
VCC_DDR
VSS
BD4
BD3
BD2
BD1
NC
VCC_DDR
VSS
BC45
BC44
BC43
BC42
BC40
BC38
BC37
BC36
BC34
BC32
BC30
BC28
BC26
BC24
BC23
BC22
BC20
BC18
BC16
BC14
BC12
BC10
BC9
VCC_CKDDR
VCC_CKDDR
VSS
VCC_DDR
VSS
DDR_RCOMPYPD
DDR3_A_WEB
VCC_DDR
DDR3_DRAMRST
B
BB23
VCC_DDR
VSS
BB22
BB21
BB20
BB19
BB18
BB17
BB16
BB15
BB14
BB13
BB12
BB11
BB10
BB8
DDR_B_MA_2
DDR_B_MA_5
DDR_B_MA_6
DDR_B_MA_9
DDR_B_BS_2
DDR_B_CKE_2
DDR_A_DQ_18
DDR_A_DQ_23
DDR_A_DQ_17
DDR_A_DQ_21
DDR_A_DQ_10
DDR_A_DQ_15
DDR_A_DQ_9
DDR_A_DQ_2
DDR_A_DQ_7
DDR_A_DM_0
DDR_A_DQ_5
VSS_BB3
VCC_DDR
VSS
DDR_A_BS_0
DDR_A_MA_0
VCC_DDR
VCC_DDR
DDR_B_MA_8
VSS
DDR_B_CSB_2
VCC_DDR
DDR_A_DQ_19
VSS
DDR_A_MA_8
VCC_DDR
DDR_A_DQ_11
VSS
DDR_A_CKE_3
VCC_DDR
DDR_A_DQ_3
VSS
DDR_B_MA_1
VCC_DDR
BE6
BE4
4.75
DDR_B_MA_14
VSS
BE3
VSS
BB7
BE2
NC
DDR_A_DM_2
VSS
BB5
BE1
TEST1
BB4
BD45
BD44
BD43
BD42
BD39
BD37
BD35
BD33
BD31
BD29
BD27
BD25
BD21
BD19
BD17
BD15
BD13
BD11
BD9
NC
DDR_A_DM_1
DDR_A_DQ_13
VSS
BB3
VCC_CKDDR
VCC_CKDDR
DDR_A_CSB_1
DDR_A_WEB
DDR_A_MA_10
DDR3_A_MA0
DDR_B_ODT_0
DDR_B_RASB
DDR_A_MA_6
DDR_A_MA_11
DDR_A_CKE_0
DDR_B_MA_4
DDR_B_CKE_1
DDR_B_CKE_0
DDR_A_DQ_22
DDR_A_DQ_16
DDR_A_DQ_14
DDR_A_DQ_8
BB2
VSS
BC8
BA42
BA41
BA40
BA37
BA35
BA33
BA31
BA29
BA27
BA25
BA21
BA19
BA17
BA15
BA13
BA11
DDR_A_MA_13
DDR_A_ODT_2
DDR_A_CSB_0
DDR3_B_ODT3
DDR_B_CSB_3
DDR_B_MA_13
DDR_B_CSB_0
DDR_A_MA_4
DDR_A_MA_9
DDR_A_MA_14
DDR_B_MA_3
DDR_B_MA_11
DDR_B_CKE_3
DDR_A_DQS_2
DDR_A_DQ_20
DDR_A_DQS_1
BC6
DDR_A_DQSB_0
DDR_A_DQ_0
VSS
BC4
BC3
BC2
RSVD
BC1
VSS
BB44
BB43
BB42
BB41
BB39
BB38
BB36
BB35
BB34
BB33
BB32
DDR3_A_CSB1
DDR_A_ODT_0
DDR_RCOMPYPU
DDR_A_CASB
DDR_A_CSB_2
DDR_A_RASB
DDR_A_BS_1
DDR_B_CSB_1
DDR_B_ODT_1
DDR_B_ODT_2
DDR_B_CASB
Datasheet
301
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
BA9
DDR_A_DQ_12
DDR_A_DQS_0
VSS_BA5
AW33
AW31
AW30
AW28
AW27
AW25
AW24
AW23
AW22
AW21
AW19
AW18
AW16
AW15
AW13
AW12
AW11
AW10
AW8
DDR_B_CKB_2
VSS
AV15
AV13
AV12
AV11
AV10
AV8
DDR_B_DQ_11
VSS
BA6
BA5
DDR_B_CK_0
VSS
VSS
BA4
VSS_BA4
VSS
AY45
AY43
AY41
AY40
AY39
AY38
AY36
AY35
AY34
AY33
AY31
AY30
AY28
AY27
AY25
AY24
AY23
AY22
AY21
AY19
AY18
AY16
AY15
AY13
AY12
AY11
AY10
AY8
VCC_DDR
VSS
VSS
DDR_A_CSB_3
DDR_A_ODT_1
DDR_B_DM_4
DDR_B_DQ_32
DDR_B_DQ_36
VSS
DDR_B_DQ_24
DDR_B_MA_10
DDR_B_BS_1
DDR_A_DQ_31
VSS
DDR_B_DQ_4
DDR_VREF
VSS
AV7
AV6
AV4
VSS
AV3
VSS
DDR_A_DQ_29
VSS
AV1
VSS
DDR_B_ODT_3
DDR_B_CKB_5
VSS
AU44
AU43
AU41
AU5
DDR_A_DM_4
DDR_A_DQ_33
DDR_A_DQ_37
VCCA_EXP2
VSS
DDR_B_DM_2
VSS
DDR_B_WEB
DDR_B_CK_4
DDR_B_CKB_4
DDR_A_MA_7
DDR_B_DM_3
DDR_A_CKE_1
VCC_DDR
DDR_B_DQ_13
DDR_B_DQ_12
DDR_B_DQ_7
DDR_B_DQS_0
DDR_B_DQ_0
VSS
AU3
AU2
PEG2_TXP_14
VSS
AT45
AT43
AT42
AT40
AT39
AT38
AT36
AT35
AT34
AT33
AT31
AT30
AT28
AT27
AT25
AT24
AT23
AT22
AT21
AT19
AT18
AT16
AT15
AT13
AT12
AT11
AT10
AT8
DDR_A_DQS_4
DDR_A_DQSB_4
DDR_B_DQ_35
VSS
AW7
AW6
DDR_B_DQ_5
VSS
DDR_B_MA_0
DDR_A_DQ_25
DDR_B_MA_7
DDR_B_MA_12
DDR_B_DQ_16
DDR_A_DQSB_2
DDR_B_DQ_9
DDR_B_DQ_8
DDR_A_DQSB_1
VSS
AW4
AW2
VSS_AW2
DDR_B_DQ_34
DDR_A_CKB_5
DDR_A_CK_5
DDR_A_CK_2
DDR_A_CK_0
DDR_A_CKB_3
VSS
AV45
AV43
AV42
AV40
AV39
AV38
AV36
AV35
AV34
AV33
AV31
AV30
AV28
AV27
AV25
AV24
AV23
AV22
AV21
AV19
AV18
AV16
VSS
VSS
DDR_A_DQ_32
DDR_B_DQ_39
DDR_B_DQ_38
DDR_B_DQSB_4
DDR_B_DQ_44
DDR_A_CKB_2
VSS
VSS
DDR_B_DQ_26
DDR_B_DQ_30
VSS
DDR_B_DM_0
DDR_B_DQ_1
DDR_RCOMPXPD
DDR_RCOMPXPU
VSS_AY3
AY7
DDR_B_CK_2
DDR_A_CK_3
DDR_B_CKB_0
VSS
AY6
VSS
AY5
DDR_A_DQ_27
DDR_A_DQS_3
DDR_B_DQ_19
DDR_B_DQ_22
VSS
AY3
AY1
VSS_AY1
DDR_B_DQ_27
DDR_B_DQ_25
VSS
AW44
AW42
AW40
AW39
AW38
AW36
AW35
AW34
DDR_A_ODT_3
DDR_A_DQ_36
VSS
VSS
DDR_B_DQ_10
DDR_B_DM_1
DDR_B_DQ_3
DDR_B_DQ_2
DDR_B_DQSB_0
VSS
DDR_B_DQS_4
DDR_B_DQ_33
DDR_B_DQ_37
VSS
VSS
DDR_A_DQSB_3
DDR_A_DQ_28
VSS
DDR_B_CK_5
DDR_B_DQ_17
302
Datasheet
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
AT7
DDR_RCOMPVOL
DDR_RCOMPVOH
PEG2_TXP_13
PEG2_TXN_14
VSS
AP35
AP34
AP33
AP31
AP30
AP28
AP27
AP25
AP24
AP23
AP22
AP21
AP19
AP18
AP16
AP15
AP13
AP12
AP11
AP10
AP8
DDR_B_DQ_42
RSVD
AN19
AN18
AN16
AN15
AN13
AN12
DDR_A_DQ_24
DDR_B_DQS_2
DDR_B_DQ_20
DDR_B_DQ_14
RSVD
AT6
AT4
VSS
AT3
DDR_B_CKB_3
VSS
AT1
AR44
AR42
AR41
AR40
AR39
AR38
AR36
AR35
AR34
AR33
AR31
AR30
AR28
AR27
AR25
AR24
AR23
AR22
AR21
AR19
AR18
AR16
AR15
AR13
AR12
AR11
AR10
AR8
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_38
DDR_A_DQ_39
VSS
DDR_B_CKB_1
DDR_B_DQ_31
VSS
RSVD
DDR3_DRAM_PW
ROK
AN11
AN10
AN8
EXP2_COMPI
EXP2_COMPO
VSS
DDR_B_DQ_29
VSS
AN7
VSS
VSS
AN6
VSS
DDR_B_DQ_40
VSS
DDR_A_DM_3
DDR_B_DQ_18
VSS
AN5
PEG2_TXN_11
VSS
AN4
DDR_B_DQ_45
DDR_A_CKB_0
DDR_B_CK_3
VSS
AN2
PEG2_TXP_10
VSS
DDR_B_DQSB_2
DDR_B_DQ_15
VSS
AM45
AM43
AM42
AM32
AM30
AM28
AM27
AM25
AM24
AM23
AM22
AM21
AM19
AM18
AM16
AM14
AM4
DDR_A_DQS_5
DDR_A_DQSB_5
RSVD
DDR_B_CK_1
VSS
RSVD
PEG2_RXN_15
PEG2_RXP_15
VSS
VCC_CL
DDR_B_DQS_3
DDR_B_DQSB_3
VSS
DDR_A_CKB_1
DDR_A_CKB_4
RSVD
AP7
PEG2_TXP_15
PEG2_TXN_15
PEG2_TXP_11
VCCR_EXP
PEG2_TXN_12
DDR_A_DM_5
DDR_A_DQ_41
DDR_A_DQ_40
DDR_B_DQ_47
DDR_B_DQ_46
VSS
VSS
AP6
VSS
VSS
AP4
VCC_CL
VSS
AP3
VCC_CL
DDR_B_DQ_23
DDR_B_DQ_21
VSS
AP1
VSS
AN44
AN42
AN41
AN40
AN39
AN38
AN36
AN35
AN34
AN33
AN31
AN30
AN28
AN27
AN25
AN24
AN23
AN22
AN21
PWROK
RSTINB
DDR_B_DQS_1
DDR_B_DQSB_1
DDR_B_DQ_6
VCCAPLL_EXP2
VSS
VSS
RSVD
PEG2_TXP_9
PEG2_TXN_10
VSS
AM3
DDR_B_DM_5
DDR_A_CB_1
VSS
AM1
AR7
VSS
AL44
AL42
AL41
AL40
AL39
AL38
AL36
AL35
AL34
AL33
AL30
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_47
DDR_A_DQ_46
VSS
AR6
VSS
AR5
PEG2_TXN_13
VSS
DDR_B_DQ_43
RSVD
AR4
AR2
PEG2_TXP_12
DDR_A_DQ_45
VSS
RSVD
AP45
AP43
AP42
AP40
AP39
AP38
AP36
DDR_A_CK_1
DDR_A_CK_4
RSVD
DDR_A_DQS_8
DDR_A_DQSB_8
VSS
DDR_A_DQ_44
DDR_B_DQSB_5
DDR_B_DQS_5
VSS
DDR_B_DQ_28
VSS
DDR_A_CB_5
DDR_A_CB_0
VCC_CL
DDR_A_DQ_26
DDR_A_DQ_30
DDR_B_DQ_41
Datasheet
303
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
AL28
AL27
AL25
AL24
AL23
AL22
AL21
AL19
AL18
AL16
AL13
AL12
AL11
AL10
AL8
RSVD
AJ42
AJ41
AJ29
AJ28
AJ27
AJ26
AJ25
AJ24
AJ23
AJ22
AJ21
AJ20
AJ19
AJ18
AJ17
AJ5
DDR_B_CB_4
VSS
AH13
AH12
AH11
AH10
AH8
PEG2_RXN_9
VSS
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
PEG2_TXN_7
VSS
PEG2_RXP_10
PEG2_RXN_10
VSS
VCC_CL
VCC_CL
VCC_CL
AH7
PEG2_RXP_11
PEG2_RXN_11
PEG2_TXP_5
PEG2_TXN_6
VSS
VCC_CL
AH6
VCC_CL
AH4
VCC_CL
AH3
VCC_CL
AH1
CL_PWROK
VSS
AG44
AG42
AG41
AG40
AG39
AG38
AG36
AG35
AG34
AG33
AG32
AG31
AG29
AG28
AG27
AG26
AG25
AG24
AG23
AG22
AG21
AG20
AG19
AG18
AG17
AG15
AG14
AG13
AG12
AG11
AG10
AG8
DDR_B_CB_7
DDR_B_CB_2
DDR_B_CB_6
DDR_B_CB_3
DDR_B_DQS_6
DDR_B_DQSB_6
VSS
PEG2_RXP_13
PEG2_RXN_13
VSS
AL7
PEG2_RXN_14
PEG2_RXP_14
PEG2_TXN_9
VSS
AL6
AJ4
AL5
AJ2
PEG2_TXP_6
VSS
DDR_B_DM_6
VSS
AL4
AH45
AH43
AH42
AH40
AH39
AH38
AH36
AH35
AH34
AH33
AH32
AH31
AH29
AH28
AH27
AH26
AH25
AH24
AH23
AH22
AH21
AH20
AH19
AH18
AH17
AH15
AH14
AL2
PEG2_TXP_8
DDR_B_CB_0
VSS
DDR_B_DQS_8
DDR_B_DQSB_8
VSS
DDR_B_DQ_49
RSVD
AK45
AK43
AK42
AK40
AK39
AK38
AK36
AK35
AK34
AK33
AK32
AK31
AK15
AK14
AK13
AK12
AK11
AK10
AK8
VCC_CL
VCC_CL
RSVD
DDR_B_CB_5
VSS
VSS
VSS
DDR_A_CB_7
DDR_A_CB_2
VSS
DDR_B_DQ_53
VSS
VCC
VSS
DDR_B_DQ_48
DDR_B_DQ_52
VSS
VCC
DDR_A_CB_3
DDR_A_CB_6
DDR_A_CB_4
VSS
VSS
VCC
VCC_CL
VCC_CL
RSVD
VSS
VCC
VCC_CL
VSS
CL_DATA
CL_CLK
VSS
VCC
VCC
VCC
PEG2_RXN_12
PEG2_RXP_12
VSS
VSS
VCC
VCC
VCC
VSS
CL_VREF
VSS
VSS
VCC
VSS
VSS
PEG2_RXP_9
CL_RSTB
VSS
AK7
VSS
VCC
AK6
VSS
VCC
AK4
PEG2_TXP_7
VCCR_EXP
PEG2_TXN_8
DDR_B_CB_1
VCC
VSS
AK3
VCC
AG7
VSS
AK1
VCC_CL
VCC_CL
AG6
VSS
AJ44
AG5
PEG2_TXN_5
304
Datasheet
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
AG4
VSS
AE17
AE15
AE14
AE13
AE12
AE11
AE10
AE8
VCC
AD7
VCC_EXP
VSS
AG2
PEG2_TXP_4
DDR_A_DQ_53
VSS
VCCR_EXP
EXP2_CLKINP
PEG2_RXP_6
VSS
AD6
AF45
AF43
AF42
AF29
AF28
AF27
AF26
AF25
AF24
AF23
AF22
AF21
AF20
AF19
AF18
AF17
AF4
AD4
PEG2_TXP_1
PEG2_TXN_2
VSS
AD3
DDR_A_DQ_52
VCC_CL
VCC
AD1
PEG2_RXN_7
PEG2_RXP_7
VSS
AC45
AC43
AC42
AC40
AC39
AC38
AC36
AC35
AC34
AC33
AC32
AC31
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AC22
AC21
AC20
AC19
AC18
AC17
AC15
AC14
AC13
AC12
AC11
AC10
AC8
DDR_A_DQ_51
VSS
VSS
DDR_A_DQ_50
DDR_A_DQ_60
DDR_A_DQ_55
VSS
VCC
AE7
PEG2_RXP_8
PEG2_RXN_8
PEG2_TXN_3
VSS
VSS
AE6
VCC
AE5
VSS
AE4
DDR_B_DQ_62
VSS
VCC
AE2
PEG2_TXP_2
VSS
VSS
AD45
AD43
AD42
AD40
AD39
AD38
AD36
AD35
AD34
AD33
AD32
AD31
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD15
AD14
AD13
AD12
AD11
AD10
AD8
DDR_B_DQ_63
DDR_B_DQS_7
VSS
VCC
DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DQ_54
DDR_B_DQ_56
VSS
VSS
VCC
VCC_CL
VCC_CL
VCC
VCC
PEG2_TXP_3
VCCR_EXP
PEG2_TXN_4
DDR_A_DM_6
DDR_A_DQ_49
DDR_A_DQ_48
DDR_B_DQ_54
DDR_B_DQ_50
DDR_B_DQ_51
VSS
AF3
DDR_B_DQ_57
DDR_B_DM_7
VSS
VCC
AF1
VSS
AE44
AE42
AE41
AE40
AE39
AE38
AE36
AE35
AE34
AE33
AE32
AE31
AE29
AE28
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
VCC
DDR_B_DQSB_7
RSVD
VSS
VCC
VCC_CL
VSS
VCC_CL
VCC
VCC
VSS
VSS
VCC
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_55
VSS
VCC
VCC
VSS
VCC
VCC
VCCR_EXP
VSS
VSS
VCC_CL
VCC_CL
VCC
VCC
PEG2_RXP_3
VSS
VSS
VCC
PEG2_RXP_4
PEG2_RXN_4
VSS
VCC
VSS
VSS
VCC
VCC
VCC
AC7
PEG2_RXN_5
PEG2_RXP_5
PEG2_TXN_1
VCCR_EXP
VSS
VSS
VCCR_EXP
EXP2_CLKINN
VSS
AC6
VCC
AC4
VSS
AC3
VCC
PEG2_RXN_6
VCC_EXP
VCC_EXP
VCC_EXP
AC1
VSS
AB45
AB43
AB42
VSS
VCC
DDR_A_DQ_57
DDR_A_DQ_56
VCC
Datasheet
305
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
AB40
AB39
AB38
AB36
AB35
AB34
AB33
AB32
AB31
AB29
AB28
AB27
AB26
AB25
AB24
AB23
AB22
AB21
AB20
AB19
AB18
AB17
AB15
AB14
AB13
AB12
AB11
AB10
AB8
DDR_A_DM_7
DDR_A_DQ_61
DDR_B_DQ_59
VSS
AA31
AA29
AA28
AA27
AA26
AA25
AA24
AA23
AA22
AA21
AA20
AA19
AA18
AA17
AA15
AA14
AA13
AA12
AA11
AA10
AA8
AA7
AA6
AA5
AA4
AA2
Y45
VCC_CL
VCC_CL
VCC
W44
W42
W41
W40
W39
W38
W36
W35
W34
W33
W32
W31
W29
W28
W27
W26
W25
W24
W23
W22
W21
W20
W19
W18
W17
W15
W14
W13
W12
W11
W10
W8
FSB_BREQ0B
DDR_A_DQ_59
FSB_RSB_1
FSB_TRDYB
VSS
VCC
FSB_AB_34
FSB_AB_29
VSS
VSS
VCC
FSB_AB_22
FSB_AB_30
VSS
VSS
DDR_B_DQ_58
VCC_CL
VCC_CL
VCC
VCC
VSS
FSB_AB_25
FSB_AB_27
RSVD
VCC
VSS
VSS
VCC
VSS_W31
VCC_CL
VCC
VCC
VCC
VSS
VCC
VCC
VCCR_EXP
VCCR_EXP
PEG2_RXN_0
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
PEG2_RXN_1
PEG2_RXP_1
VSS
VCC
VSS
VSS
VCC
VCC
VCC
PEG2_RXN_2
PEG2_RXP_2
VCC_EXP
VCC_EXP
VCC_EXP
DDR_A_DQ_63
VSS
VSS
VCC
VCC
VCCR_EXP
VCC_EXT_PLL
PEG2_RXN_3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
PEG2_TXP_0
PEG2_TXN_0
DDR_A_DQSB_7
DDR_A_DQS_7
DDR_A_DQ_62
FSB_AB_33
VSS
VCC
VCC
VCCR_EXP
VSS
Y43
VSS
Y42
DDR_A_DQ_58
VCC_CL
VCC
PEG2_RXP_0
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VSS
AB7
Y29
AB6
Y28
AB4
Y27
VSS
AB3
Y26
VCC
W7
AB1
Y25
VSS
W6
AA44
AA42
AA41
AA40
AA39
AA38
AA36
AA35
AA34
AA33
AA32
Y24
VCC
W5
VCC_EXP
VCC_EXP
VCC_EXP
VSS
Y23
VSS
W4
Y22
VCC
W2
Y21
VSS
V45
V43
V42
V40
V39
V38
V36
V35
Y20
VCC
FSB_AB_28
FSB_HITMB
VSS
FSB_AB_35
VSS
Y19
VSS
Y18
VCC
FSB_AB_32
VSS
Y17
VCC
FSB_AB_24
FSB_AB_23
VSS
Y4
VCC_EXP
VCC_EXP
VCC_EXP
FSB_AB_31
VSS
Y3
Y1
FSB_AB_26
306
Datasheet
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
V34
V33
V32
V31
V29
V28
V27
V26
V25
V24
V23
V22
V21
V20
V19
V18
V17
V15
V14
V13
V12
V11
V10
V8
FSB_ADSTBB_1
VSS
U5
VCC_EXP
VCC_EXP
VCC_EXP
FSB_LOCKB
VSS
R19
R18
R16
R13
R12
R11
R10
R8
RSVD
U4
VCC
RSVD
U2
VCC
VCC_CL
VCC_CL
VCC
T45
T43
T42
T40
T39
T38
T36
T35
T34
T33
T32
T31
T15
T14
T13
T12
T11
T10
T8
VSS
VSS
FSB_DBSYB
FSB_AB_17
FSB_DEFERB
FSB_AB_20
FSB_AB_18
VSS
VSS
VSS
EXP_COMPI
VSS
VCC
VSS
R7
DMI_TXP_0
DMI_TXN_0
DMI_RXN_2
VSS
VCC
R6
VSS
R5
VCC
FSB_AB_19
RSVD
R4
VSS
R2
DMI_TXP_2
VSS
VCC
VSS
P45
P43
P42
P32
P30
P28
P27
P25
P24
P23
P22
P21
P19
P18
P16
P14
P4
VSS
VCCAUX
VCCR_EXP
VCCR_EXP
VSS
FSB_AB_21
FSB_DB_0
VSS
VCC
VCC
VCCR_EXP
VCCR_EXP
VSS
HPL_CLKINN
HPL_CLKINP
VSS
RSVD
VSS
RSVD
EXP_COMPO
DMI_RXN_1
DMI_RXP_1
VSS
VSS
DMI_TXN_3
DMI_TXP_3
VSS
VSS
T7
VSS
T6
VSS
V7
DMI_RXP_3
DMI_RXN_3
VCC_EXP
VCC_EXP
VCC_EXP
FSB_ADSB
FSB_BNRB
FSB_DRDYB
VCCAUX
VCC
T4
VCC_EXP
VCC_EXP
DMI_TXN_2
FSB_RSB_0
FSB_HITB
FSB_RSB_2
VSS
RSVD
V6
T3
RSVD_P19
VSS
V4
T1
V3
R44
R42
R41
R40
R39
R38
R36
R35
R34
R33
R30
R28
R27
R25
R24
R23
R22
R21
ICH_SYNCB
VSS
V1
U44
U42
U41
U29
U28
U27
U26
U25
U24
U23
U22
U21
U20
U19
U18
U17
DMI_RXP_2
DMI_TXN_1
VSS
P3
FSB_AB_14
VSS
P1
N44
N42
N41
N40
N39
N38
N36
N35
N34
N33
N31
N30
N28
FSB_DB_2
FSB_DB_4
FSB_DB_1
FSB_AB_9
FSB_AB_11
FSB_AB_13
FSB_AB_8
VSS
FSB_AB_10
FSB_AB_16
VSS
VCC
VCC
VCC
RSVD
VCC
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
RSVD
VCC
VCC
VCC
FSB_AB_12
FSB_DB_28
FSB_DB_30
FSB_DB_37
FSB_DINVB_2
VCC
VCC
VCC
VCC
VSS
Datasheet
307
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
N27
N25
N24
N23
N22
N21
N19
N18
N16
N15
N13
N12
N11
N10
N8
VSS
M11
M10
M8
PEG_RXP_12
VSS
K39
K38
K36
K35
K34
K33
K31
K30
K28
K27
K25
K24
K23
K22
K21
K19
K18
K16
K15
K13
K12
K11
K10
K8
VSS
FSB_DSTBPB_2
FSB_DB_42
VSS
FSB_AB_6
FSB_REQB_3
FSB_DB_21
FSB_DB_24
VSS
PEG_RXN_13
PEG_RXP_13
VSS
M7
VSS
M6
RSVD
M4
DMI_RXN_0
VCCR_EXP
PEG_TXP_15
FSB_DB_6
FSB_DB_7
FSB_DINVB_0
FSB_AB_7
FSB_REQB_2
VSS
VSS
M3
FSB_DB_33
VSS
RSVD
M1
VSS
L44
L42
L41
L40
L39
L38
L36
L35
L34
L33
L31
L30
L28
L27
L25
L24
L23
L22
L21
L19
L18
L16
L15
L13
L12
L11
L10
L8
FSB_DB_40
VTT_FSB
VTT_FSB
FSB_DB_46
VSS
VCC_N15
PEG_RXP_4
RSVD
RSVD
PEG_RXN_15
PEG_RXP_15
VSS
RSVD
FSB_DB_19
VSS
RSVD
N7
EXP_SLR
VSS
N6
VSS
FSB_DB_27
FSB_DB_29
VSS
N5
DMI_RXP_0
VSS
VSS_K16
VSS
N4
N2
DMI_TXP_1
FSB_DB_5
VSS
FSB_DB_36
FSB_DB_41
VTT_FSB
FSB_DB_43
FSB_DB_44
VSS
PEG_RXN_3
VSS
M45
M43
M42
M40
M39
M38
M36
M35
M34
M33
M31
M30
M28
M27
M25
M24
M23
M22
M21
M19
M18
M16
M15
M13
M12
PEG_RXP_6
VSS
FSB_DB_3
FSB_ADSTBB_0
VSS
PEG_RXN_11
PEG_RXP_11
VSS
K7
FSB_AB_4
FSB_AB_5
VSS
XORTEST
VSS
K6
K4
PEG_TXN_14
PEG_RXP_14
VSS
RSVD
K3
VSS
RSVD
K1
VSS
VCC3_3_L16
VSS
J44
J43
J41
J5
FSB_DSTBPB_0
FSB_DB_8
FSB_DB_10
PEG_TXP_13
VSS
FSB_DB_31
FSB_DB_35
VSS
PEG_RXP_3
PEG_RXN_6
VSS
VTT_FSB
FSB_DSTBNB_2
VSS
J3
PEG_RXN_12
VSS
J2
PEG_RXN_14
FSB_DB_12
VSS
H45
H43
H42
H40
H39
H38
H36
H35
H34
H33
VSS
L7
VSS
BSEL0
L6
VSS
FSB_DB_9
VSS
ALLZTEST
RSVD_M19
VSS
L5
PEG_TXP_14
VSS
L4
FSB_REQB_4
FSB_BPRIB
VSS
L2
PEG_TXN_15
VSS
RSVD
K45
K43
K42
K40
VSS_M15
PEG_RXN_4
VSS
FSB_DSTBNB_0
FSB_AB_15
VSS
VSS
FSB_DSTBPB_1
FSB_DB_25
308
Datasheet
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
Ball #
Signal Name
H31
H30
H28
H27
H25
H24
H23
H22
H21
H19
H18
H16
H15
H13
H12
H11
H10
H8
FSB_DB_34
FSB_DB_39
VTT_FSB
VTT_FSB
VTT_FSB
FSB_DB_45
VSS
G13
G12
G11
G10
G8
PEG_RXN_2
PEG_RXN_5
VSS
E37
E35
E33
E31
E29
E27
E25
E21
E19
E17
E15
E13
E11
E9
FSB_DB_61
FSB_DB_63
VTT_FSB
PEG_RXP_7
VSS
VTT_FSB
VTT_FSB
G7
VSS
FSB_DVREF
VCC_E25
VSS
G6
PEG_RXN_9
VSS
VSS
G4
RSVD
G2
PEG_TXN_12
VSS
VSS
VSS
F45
F43
F41
F40
F39
F38
F36
F35
F34
F33
F31
F30
F28
F27
F25
F24
F23
F22
F21
F19
F18
F16
F15
F13
F12
F11
F10
F8
PEG_TXN_0
PEG_TXP_1
PEG_TXP_2
PEG_TXN_4
PEG_TXN_6
PEG_RXP_8
VSS
VSS
FSB_AB_3
FSB_DB_14
VSS
VSS_H16
RSVD_H15
PEG_RXP_2
PEG_RXP_5
VSS
FSB_DB_17
FSB_DB_16
VSS
E6
E5
PEG_RXN_7
VSS
FSB_DB_48
VSS
E4
PEG_TXN_11
FSB_DB_52
FSB_DB_53
VSS
D44
D43
D42
D41
D39
D38
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
H7
VSS
FSB_DB_26
FSB_DB_32
VTT_FSB
VTT_FSB
VTT_FSB
VTT_FSB
VSS
H6
VSS
H4
PEG_TXN_13
VCCR_EXP
PEG_TXP_12
FSB_DB_13
FSB_DB_11
FSB_REQB_1
VSS
FSB_DSTBNB_3
FSB_DB_57
FSB_DB_54
FSB_DB_59
FSB_CPURSTB
VSS
H3
H1
G44
G42
G40
G39
G38
G36
G35
G34
G33
G31
G30
G28
G27
G25
G24
G23
G22
G21
G19
G18
G16
G15
VSS
VSS_F22
BSEL1
VTT_FSB
FSB_DB_20
FSB_DB_22
FSB_DB_23
FSB_DSTBNB_1
VSS
VTT_FSB
RSVD
VTT_FSB
BSEL2
VTT_FSB
VSS
VSS
VSS
FSB_SCOMP
FSB_ACCVREF
VCCA_HPL
VCCA_HPL
VSS_D24
VSS
VSS
VSS
FSB_DB_38
VTT_FSB
VTT_FSB
VTT_FSB
FSB_DB_47
VSS
VSS
VSS
VSS
VSS
F7
PEG_RXP_9
VSS
VSS_D22
VSS_D21
VCCA_EXP
EXP_CLKINP
EXP_CLKINN
VSS
F6
RSVD
F5
PEG_TXP_11
PEG_TXP_10
VSS
TCEN
F3
MTYPE
F1
VSS
E42
E41
E40
FSB_DB_15
FSB_DB_50
FSB_DINVB_1
VCC3_3_G16
RSVD_G15
PEG_TXP_0
VSS
Datasheet
309
Ballout and Package Information
Table 29.
MCH
Table 29.
MCH
Ballout Sorted By Ball
Ballout Sorted By Ball
Ball #
Signal Name
Ball #
Signal Name
D14
D13
D12
D11
D10
D8
PEG_TXN_1
VSS
B37
B35
B33
B31
B29
B27
B25
B21
B19
B17
B15
B13
B11
B9
FSB_DINVB_3
FSB_DB_62
VTT_FSB
VTT_FSB
VSS
PEG_TXN_2
VSS
PEG_TXP_4
PEG_TXP_6
VSS
VCCA_MPL
VCC_B25
VSS_B21
RSVD
D7
D5
PEG_RXN_8
VSS
D4
D3
PEG_TXN_10
PEG_RXP_10
VSS
VSS_B17
PEG_RXN_0
PEG_RXP_1
PEG_TXP_3
PEG_TXP_5
PEG_TXP_7
PEG_TXN_9
PEG_TXP_9
VSS
D2
C45
C44
C43
C42
C40
C38
C37
C36
C34
C32
C30
C28
C26
C24
C23
C22
C20
C18
C16
C14
C12
C10
C9
FSB_REQB_0
VSS
FSB_DB_51
FSB_DSTBPB_3
VSS
B7
B4
B3
FSB_DB_60
FSB_DB_58
VSS
B2
B1
NC
A45
A44
A43
A40
A38
A36
A34
A32
A30
A28
A26
A24
A23
A22
A20
A18
A16
A14
A12
A10
A8
TEST3
VTT_FSB
VSS
NC
VSS
FSB_SCOMPB
FSB_RCOMP
VSS_C24
VSS_C23
VSS
VSS
FSB_DB_49
VSS
VSS
VTT_FSB
VTT_FSB
FSB_SWING
VSS
VSS
VCC_C18
VCCR_EXP
PEG_RXN_1
VCCR_EXP
PEG_TXN_5
VSS
VSS_A24
VCC3_3
VSS
VCCAPLL_EXP
VSS
C8
VCCR_EXP
PEG_TXP_8
PEG_TXN_8
VSS
C6
PEG_RXP_0
VSS
C4
C3
PEG_TXN_3
VSS
C2
PEG_RXN_10
VSS
C1
PEG_TXN_7
VSS
B45
B44
B43
B42
B39
NC
A6
VSS
A3
VSS
FSB_DB_18
FSB_DB_55
FSB_DB_56
A2
TEST2
NOTE: See list of notes at
beginning of chapter.
310
Datasheet
Ballout and Package Information
12.2
Package Information
The MCH is available in a 40 mm [1.57 in] x 40 mm [1.57 in] Flip Chip Ball Grid Array
(FC-BGA) package with an integrated heat spreader (IHS) and 1300 solder balls.
Figure 14 shows the package drawing.
Figure 14.
MCH Package Drawing
Datasheet
311
Ballout and Package Information
312
Datasheet
Testability
13 Testability
In the MCH, testability for Automated Test Equipment (ATE) board level testing has
been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one
input pin connected to it which allows for pad to ball to trace connection testing.
The XOR testing methodology is to boot the part using straps to enter XOR mode (A
description of the boot process follows). Once in XOR mode, all of the pins of an XOR
chain are driven to logic 1. This action will force the output of that XOR chain to either
a 1 if the number of the pins making up the chain is even or a 0 if the number of the
pins making up the chain is odd.
Once a valid output is detected on the XOR chain output, a walking 0 pattern is moved
from one end of the chain to the other. Every time the walking 0 is applied to a pin on
the chain, the output will toggle. If the output does not toggle, there is a disconnect
somewhere between die, package, and board and the system can be considered a
failure.
13.1
XOR Test Mode Initialization
Figure 15.
XOR Test Mode Initialization Cycles
CL_PWROK
PWROK
CL_RST#
RSTIN#
STRAP PINS
HCLKP/GCLKP
HCLKN/GCLKN
XOR inputs
X
XOR output
Datasheet
313
Testability
The above figure shows the wave forms to be able to boot the part into XOR mode. The
straps that need to be controlled during this boot process are BSEL[2:0], RSVD (Ball
L18), EXP_SLR, and XORTEST.
On the X38 Express Chipset platforms, all strap values must be driven before PWROK
asserts. BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic value in
any order will do. XORTEST must be driven to 0.
Not all of the pins will be used in all implementations. Due to the need to minimize test
points and unnecessary routing, the XOR Chain 14 is dynamic depending on the values
of EXP_SLR, and RSVD (Ball L18). See Figure 30 for what parts of XOR Chain 14
become valid XOR inputs depending on the use of EXP_SLR and RSVD (Ball L18).
13.2
XOR Chain Definition
The MCH has 15 XOR chains. The XOR chain outputs are driven out on the following
output pins. During fullwidth testing, XOR chain outputs will be visible on both pins.
Table 30.
XOR Chain 14 Functionality
RSVD (Ball L18)
EXP_SLR
XOR Chain 14
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
1
0
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
1
0
0
1
1
1
0
1
0
1
EXP_RXP[15:8]
EXP_RXN[15:8]
EXP_TXP[15:8]
EXP_TXN[15:8]
EXP_RXP[7:0]
EXP_RXN[7:0]
EXP_TXP[7:0]
EXP_TXN[7:0]
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
314
Datasheet
Testability
Table 31.
XOR Chain Outputs
XOR Chain
Output Pins
Coordinate Location
xor_out0
xor_out1
xor_out2
xor_out3
xor_out4
xor_out5
xor_out6
xor_out7
xor_out8
xor_out9
xor_out10
xor_out11
xor_out12
xor_out13
xor_out14
ALLZTEST
XORTEST
ICH_SYNCB
RSVD
M21
L22
P16
N18
AN12
AM14
F21
RSVD
RSVD
BSEL1
BSEL2
F18
RSVD
AN13
AP12
K19
RSVD
EXP_SLR
RSVD
L18
BSEL0
M22
H21
G22
RSVD
RSVD
13.3
XOR Chains
This section provides the XOR chains.
Datasheet
315
Testability
13.3.1
XOR Chains for DDR2 (No ECC)
Table 32.
XOR Chain 0 (DDR2,
NoECC)
Table 32.
XOR Chain 0 (DDR2,
NoECC)
Pin
Count
Ball
Signal Name
Pin
Count
Ball
#
Signal Name
#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
K28
K24
F31
L30
G30
N24
H31
H30
L28
M30
N30
K31
L25
E42
F41
G42
G44
H42
J43
FSB_DB_40
FSB_DB_46
FSB_DB_32
FSB_DB_36
FSB_DB_38
FSB_DB_42
FSB_DB_34
FSB_DB_39
FSB_DB_41
FSB_DB_35
FSB_DB_37
FSB_DB_33
FSB_DB_43
FSB_DB_15
FSB_DB_14
FSB_DB_11
FSB_DB_13
FSB_DB_9
FSB_DB_8
FSB_DB_12
FSB_DB_7
FSB_DB_5
FSB_DB_3
FSB_DB_6
FSB_DB_10
FSB_DB_0
FSB_DB_1
FSB_DB_4
FSB_DB_2
M21
ALLZTEST
1
B39
D44
B42
D39
C42
C36
A38
B35
D38
E41
D43
D36
E35
E37
F35
C37
F33
B43
F39
F38
H33
G36
G38
G35
L36
L33
L34
N33
N31
K34
M31
K35
L24
H24
G24
FSB_DB_56
FSB_DB_52
FSB_DB_55
FSB_DB_57
FSB_DB_51
FSB_DB_58
FSB_DB_49
FSB_DB_62
FSB_DB_54
FSB_DB_50
FSB_DB_53
FSB_DB_59
FSB_DB_63
FSB_DB_61
FSB_DB_48
FSB_DB_60
FSB_DB_26
FSB_DB_18
FSB_DB_17
FSB_DB_16
FSB_DB_25
FSB_DB_22
FSB_DB_20
FSB_DB_23
FSB_DB_19
FSB_DB_29
FSB_DB_27
FSB_DB_28
FSB_DB_30
FSB_DB_24
FSB_DB_31
FSB_DB_21
FSB_DB_44
FSB_DB_45
FSB_DB_47
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
H45
L42
M45
M42
L44
J41
P42
N41
N42
N44
Table 33.
XOR Chain 1 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
L22
XORTEST
1
2
H39
K42
FSB_REQB_4
FSB_AB_15
316
Datasheet
Testability
Table 33.
XOR Chain 1 (DDR2,
NoECC)
Table 34.
XOR Chain 2 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball
#
Signal Name
3
G40
K36
F43
FSB_REQB_1
FSB_REQB_3
FSB_AB_3
P16
ICH_SYNCB
4
5
1
2
G34
H34
W41
R42
W40
V42
M25
N25
K43
J44
FSB_DSTBNB_1
FSB_DSTBPB_1
FSB_RSB_1
6
M36
K38
M38
L40
FSB_AB_5
7
FSB_AB_6
3
8
FSB_AB_4
4
FSB_HITB
9
FSB_AB_7
5
FSB_TRDYB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C44
M40
N40
L39
FSB_REQB_0
FSB_ADSTBB_0
FSB_AB_9
6
FSB_HITMB
7
FSB_DSTBNB_2
FSB_DSTBPB_2
FSB_DSTBNB_0
FSB_DSTBPB_0
FSB_LOCKB
8
FSB_REQB_2
FSB_AB_8
9
N36
N39
N38
R35
N34
R39
R36
T34
10
11
12
13
14
FSB_AB_11
FSB_AB_13
FSB_AB_16
FSB_AB_12
FSB_AB_14
FSB_AB_10
FSB_AB_19
FSB_AB_21
FSB_AB_17
FSB_AB_25
FSB_AB_30
FSB_AB_20
FSB_AB_26
FSB_AB_27
FSB_AB_22
FSB_ADSTBB_1
FSB_AB_31
FSB_AB_18
FSB_AB_34
FSB_AB_32
FSB_AB_23
FSB_AB_29
FSB_AB_24
FSB_AB_33
FSB_AB_28
FSB_AB_35
T45
U42
H38
D35
FSB_BNRB
FSB_BPRIB
FSB_CPURSTB
Table 35.
XOR Chain 3 (DDR2,
NoECC)
P43
Pin
Count
Ball
#
T40
Signal Name
W34
W36
T38
N18
RSVD
1
2
D41
C40
B37
E40
T39
R44
U41
T42
R41
N28
L41
W44
U44
FSB_DSTBNB_3
FSB_DSTBPB_3
FSB_DINVB_3
FSB_DINVB_1
FSB_DEFERB
FSB_RSB_0
V35
W33
W38
V34
AA33
T36
3
4
5
6
7
FSB_DRDYB
FSB_DBSYB
AB35
AA35
V38
AB34
V39
AA40
V43
AA38
8
9
FSB_RSB_2
10
11
12
13
FSB_DINVB_2
FSB_DINVB_0
FSB_BREQ0B
FSB_ADSB
Datasheet
317
Testability
Table 36.
XOR Chain 4 (DDR2,
NoECC)
Table 37.
XOR Chain 5 (DDR2,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
AN12
RSVD
AM14
RSVD
1
AY41
BB39
BD42
BD37
BB43
BC36
BA27
BB30
BB29
BA29
AV35
AT34
AT33
AN28
AR33
AM28
BD29
BB31
BB28
BC28
AY27
AY24
BB25
AV21
AP21
AY15
BC14
AY11
BC10
BC6
DDR_A_ODT_1
DDR_A_CSB_1
DDR_A_CSB_0
DDR_A_MA_10
DDR_A_ODT_0
DDR_A_MA_0
DDR_A_MA_9
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_CKB_2
DDR_A_CK_2
DDR_A_CK_0
DDR_A_CK_1
DDR_A_CKB_0
DDR_A_CKB_1
DDR_A_MA_6
DDR_A_MA_1
DDR_A_MA_5
DDR_A_MA_8
DDR_A_MA_7
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_DQSB_3
DDR_A_DM_3
DDR_A_DQSB_2
DDR_A_DM_2
DDR_A_DQSB_1
DDR_A_DM_1
DDR_A_DQSB_0
DDR_A_DM_0
1
2
AA44
AB40
AD42
AE44
AM42
AN44
AT42
AU44
BA42
BB41
BD39
BB36
BB38
BC37
BA25
BD27
BB26
BB27
AK15
AK14
DDR_A_DQSB_7
DDR_A_DM_7
DDR_A_DQSB_6
DDR_A_DM_6
DDR_A_DQSB_5
DDR_A_DM_5
DDR_A_DQSB_4
DDR_A_DM_4
DDR_A_MA_13
DDR_A_CASB
DDR_A_WEB
DDR_A_BS_1
DDR_A_RASB
DDR_A_BS_0
DDR_A_MA_14
DDR_A_MA_11
DDR_A_BS_2
DDR_A_MA_12
CL_DATA
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
17
18
19
20
CL_CLK
Table 38.
XOR Chain 6 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
F21
BSEL1
1
2
3
4
5
6
7
8
9
AA42
Y42
DDR_A_DQS_7
DDR_A_DQ_58
DDR_A_DQ_62
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_63
DDR_A_DQ_61
AA41
AB42
AB43
W42
AC40
Y45
BB5
AB39
318
Datasheet
Testability
Table 38.
XOR Chain 6 (DDR2,
NoECC)
Table 38.
XOR Chain 6 (DDR2,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AD43
AC42
AC39
AE41
AD40
AC45
AF42
AF45
AE42
AM43
AL40
AN41
AN42
AP42
AL41
AP45
AL42
AL44
AT43
AU43
AU41
AV42
AR41
AR40
AR44
AW42
AR42
AT21
AY21
AW19
AN21
AW22
AT22
AN22
AN19
AV19
BA15
BB16
BD15
DDR_A_DQS_6
DDR_A_DQ_50
DDR_A_DQ_55
DDR_A_DQ_48
DDR_A_DQ_54
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_49
DDR_A_DQS_5
DDR_A_DQ_46
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_44
DDR_A_DQ_47
DDR_A_DQ_45
DDR_A_DQ_43
DDR_A_DQ_42
DDR_A_DQS_4
DDR_A_DQ_33
DDR_A_DQ_37
DDR_A_DQ_32
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQ_34
DDR_A_DQ_36
DDR_A_DQ_35
DDR_A_DQS_3
DDR_A_DQ_25
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQ_27
DDR_A_DQ_26
DDR_A_DQ_24
DDR_A_DQ_28
DDR_A_DQS_2
DDR_A_DQ_18
DDR_A_DQ_22
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
BE16
BB14
BB15
BA13
BD13
BB13
BA11
BC9
DDR_A_DQ_19
DDR_A_DQ_17
DDR_A_DQ_23
DDR_A_DQ_20
DDR_A_DQ_16
DDR_A_DQ_21
DDR_A_DQS_1
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQ_11
DDR_A_DQ_8
DDR_A_DQ_12
DDR_A_DQ_10
DDR_A_DQ_9
DDR_A_DQS_0
DDR_A_DQ_7
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_6
DDR_A_DQ_1
DDR_A_DQ_0
DDR_A_DQ_5
DDR_A_DQ_4
BD11
BB11
BE12
BD9
BA9
BB12
BB10
BA6
BB7
BB8
BE8
BD7
BD4
BC4
BB4
BD3
Table 39.
XOR Chain 7 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
F18
BSEL2
1
2
3
4
5
6
7
8
AW44
AY43
BA41
BB39
AV31
AT31
AT36
AT35
DDR_A_ODT_3
DDR_A_CSB_3
DDR_A_ODT_2
DDR_A_CSB_2
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CKB_5
DDR_A_CK_5
Datasheet
319
Testability
Table 39.
XOR Chain 7 (DDR2,
NoECC)
Table 40.
XOR Chain 8 (DDR2,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
9
AN27
AM27
BC24
BB25
DDR_A_CK_4
DDR_A_CKB_4
DDR_A_CKE_3
DDR_A_CKE_2
29
30
31
AT13
AT10
AY8
DDR_B_DM_1
DDR_B_DQSB_0
DDR_B_DM_0
10
11
12
Table 41.
XOR Chain 9 (DDR2,
NoECC)
Table 40.
XOR Chain 8 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
AP12
RSVD
AN13
RSVD
1
2
AD33
AD35
AG38
AG35
AP40
AN36
AV38
AY40
BA33
BD31
BB32
AY31
AY18
BA19
BC18
BB18
BB24
AW23
DDR_B_DQSB_7
DDR_B_DM_7
DDR_B_DQSB_6
DDR_B_DM_6
DDR_B_DQSB_5
DDR_B_DM_5
DDR_B_DQSB_4
DDR_B_DM_4
DDR_B_MA_13
DDR_B_RASB
DDR_B_CASB
DDR_B_WEB
1
BB34
BD33
BB35
BA31
AV30
AW30
AW33
AR28
AP28
AV33
BB21
BB22
BD21
BC22
AW24
BB20
BB19
BE20
BA21
AY19
BD17
AY22
BD19
AR24
AY25
AP16
AW16
AR12
DDR_B_ODT_1
DDR_B_ODT_0
DDR_B_CSB_1
DDR_B_CSB_0
DDR_B_CKB_0
DDR_B_CK_0
DDR_B_CKB_2
DDR_B_CK_1
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_MA_5
DDR_B_MA_2
DDR_B_MA_4
DDR_B_MA_1
DDR_B_MA_10
DDR_B_MA_6
DDR_B_MA_9
DDR_B_MA_8
DDR_B_MA_3
DDR_B_MA_7
DDR_B_CKE_0
DDR_B_MA_0
DDR_B_CKE_1
DDR_B_DQSB_3
DDR_B_DM_3
DDR_B_DQSB_2
DDR_B_DM_2
DDR_B_DQSB_1
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DDR_B_MA_12
DDR_B_MA_11
DDR_B_MA_14
DDR_B_BS_2
DDR_B_BS_0
DDR_B_BS_1
Table 42.
XOR Chain 10 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
K19
EXP_SLR
1
2
3
4
AC33
AC36
AB32
AB38
DDR_B_DQS_7
DDR_B_DQ_62
DDR_B_DQ_58
DDR_B_DQ_59
320
Datasheet
Testability
Table 42.
XOR Chain 10 (DDR2,
NoECC)
Table 42.
XOR Chain 10 (DDR2,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
5
AE34
AD36
AE35
AD39
AC34
AG39
AE38
AE33
AE39
AH33
AH34
AH36
AG33
AE40
AP39
AP35
AN39
AP36
AV36
AR34
AN40
AR36
AN33
AW39
AV39
AT40
AT38
AV40
AY39
AW38
AW36
AY38
AR25
AV27
AP27
AT25
AT27
AW25
AP24
DDR_B_DQ_61
DDR_B_DQ_57
DDR_B_DQ_60
DDR_B_DQ_56
DDR_B_DQ_63
DDR_B_DQS_6
DDR_B_DQ_51
DDR_B_DQ_55
DDR_B_DQ_50
DDR_B_DQ_52
DDR_B_DQ_48
DDR_B_DQ_53
DDR_B_DQ_49
DDR_B_DQ_54
DDR_B_DQS_5
DDR_B_DQ_42
DDR_B_DQ_46
DDR_B_DQ_41
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_47
DDR_B_DQ_40
DDR_B_DQ_43
DDR_B_DQS_4
DDR_B_DQ_38
DDR_B_DQ_35
DDR_B_DQ_34
DDR_B_DQ_39
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_37
DDR_B_DQ_36
DDR_B_DQS_3
DDR_B_DQ_27
DDR_B_DQ_31
DDR_B_DQ_30
DDR_B_DQ_26
DDR_B_DQ_24
DDR_B_DQ_29
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AN24
AV25
AN18
AT19
AP19
AN16
AT18
AR18
AV16
AR16
AY16
AR13
AV15
AT15
AW13
AN15
AY13
AW12
AP15
AY12
AW10
AW8
DDR_B_DQ_28
DDR_B_DQ_25
DDR_B_DQS_2
DDR_B_DQ_19
DDR_B_DQ_18
DDR_B_DQ_20
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQ_17
DDR_B_DQ_21
DDR_B_DQ_16
DDR_B_DQS_1
DDR_B_DQ_11
DDR_B_DQ_10
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_9
DDR_B_DQ_12
DDR_B_DQ_15
DDR_B_DQ_8
DDR_B_DQS_0
DDR_B_DQ_0
DDR_B_DQ_2
DDR_B_DQ_7
DDR_B_DQ_1
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_3
DDR_B_DQ_4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
AT11
AW11
AY7
AW6
AR11
AT12
AV8
Table 43.
XOR Chain 11 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
L18
RSVD
1
2
3
AY35
BA35
BB33
DDR_B_ODT_3
DDR_B_CSB_3
DDR_B_ODT_2
Datasheet
321
Testability
Table 43.
XOR Chain 11 (DDR2,
NoECC)
Table 45.
XOR Chain 13 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball
#
Signal Name
4
5
BC32
AY34
AW34
AY28
AY30
AP31
AR31
BA17
BB17
DDR_B_CSB_2
DDR_B_CKB_5
DDR_B_CK_5
DDR_B_CKB_4
DDR_B_CK_4
DDR_B_CKB_3
DDR_B_CK_3
DDR_B_CKE_3
DDR_B_CKE_2
H21
RSVD
6
1
A8
B7
PEG_TXN_7
PEG_TXP_7
PEG_RXN_7
PEG_RXP_7
PEG_TXN_6
PEG_TXP_6
PEG_RXN_6
PEG_RXP_6
PEG_TXN_5
PEG_TXP_5
PEG_RXN_5
PEG_RXP_5
PEG_TXN_4
PEG_TXP_4
PEG_RXN_4
PEG_RXP_4
PEG_TXN_3
PEG_TXP_3
PEG_RXN_3
PEG_RXP_3
PEG_TXN_2
PEG_TXP_2
PEG_RXN_2
PEG_RXP_2
PEG_TXN_1
PEG_TXP_1
PEG_RXN_1
PEG_RXP_1
PEG_TXN_0
PEG_TXP_0
PEG_RXN_0
PEG_RXP_0
PEG_TXN_15
PEG_TXP_15
PEG_RXN_15
PEG_RXP_15
PEG_TXN_14
7
2
8
3
H10
G10
E9
9
4
10
11
12
5
6
D8
7
L12
K11
C10
B9
8
Table 44.
XOR Chain 12 (DDR2,
NoECC)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Pin
Count
Ball
#
Signal Name
G12
H12
E11
D10
M13
N13
A12
B11
K13
L13
D12
E13
G13
H13
D14
E15
C14
B13
E17
D16
B15
A16
L2
M22
BSEL0
1
2
V10
V11
V7
V6
R2
T1
DMI_TXP_3
DMI_TXN_3
DMI_RXP_3
DMI_RXN_3
DMI_TXP_2
DMI_TXN_2
DMI_RXP_2
DMI_RXN_2
DMI_TXP_1
DMI_TXN_1
DMI_RXP_1
DMI_RXN_1
DMI_TXP_0
DMI_TXN_0
DMI_RXP_0
DMI_RXN_0
3
4
5
6
7
P4
8
R5
N2
P3
9
10
11
12
13
14
15
16
T7
T8
R7
R6
N5
M4
M1
N10
N8
K4
322
Datasheet
Testability
Table 45.
XOR Chain 13 (DDR2,
NoECC)
Table 46.
XOR Chain 14 (DDR2,
NoECC)
Pin
Count
Ball
#
Pin
Count
Signal Name
Ball #
Signal Name
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
L5
J2
PEG_TXP_14
PEG_RXN_14
PEG_RXP_14
PEG_TXN_13
PEG_TXP_13
PEG_RXN_13
PEG_RXP_13
PEG_TXN_12
PEG_TXP_12
PEG_RXN_12
PEG_RXP_12
PEG_TXN_11
PEG_TXP_11
PEG_RXN_11
PEG_RXP_11
PEG_TXN_10
PEG_TXP_10
PEG_RXN_10
PEG_RXP_10
PEG_TXN_9
PEG_TXP_9
PEG_RXN_9
PEG_RXP_9
PEG_TXN_8
PEG_TXP_8
PEG_RXN_8
PEG_RXP_8
6
AJ2
AD12
AE13
AG5
AH4
AC7
AC6
AF1
PEG2_TXP_6
PEG2_RXN_6
PEG2_RXP_6
PEG2_TXN_5
PEG2_TXP_5
PEG2_RXN_5
PEG2_RXP_5
PEG2_TXN_4
PEG2_TXP_4
PEG2_RXN_4
PEG2_RXP_4
PEG2_TXN_3
PEG2_TXP_3
PEG2_RXN_3
PEG2_RXP_3
PEG2_TXN_2
PEG2_TXP_2
PEG2_RXN_2
PEG2_RXP_2
PEG2_TXN_1
PEG2_TXP_1
PEG2_RXN_1
PEG2_RXP_1
PEG2_TXN_0
PEG2_TXP_0
PEG2_RXN_0
PEG2_RXP_0
PEG2_TXN_15
PEG2_TXP_15
PEG2_RXN_15
PEG2_RXP_15
PEG2_TXN_14
PEG2_TXP_14
PEG2_RXN_14
PEG2_RXP_14
PEG2_TXN_13
PEG2_TXP_13
PEG2_RXN_13
PEG2_RXP_13
7
K3
H4
J5
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
M8
M7
G2
H1
L10
M11
E4
F5
AG2
AC10
AC11
AE5
AF4
K8
K7
D3
F3
AB12
AC13
AD3
AE2
C2
D2
B4
B3
G6
F7
AA7
AA6
AC4
AD4
AA11
AA10
AB1
C4
C6
D5
E6
AB3
AA13
W12
AP6
AP7
Table 46.
XOR Chain 14 (DDR2,
NoECC)
AP11
AP10
AT3
Pin
Count
Ball #
Signal Name
G22
RSVD
AU2
AL7
1
2
3
4
5
AJ5
AK4
PEG2_TXN_7
PEG2_TXP_7
PEG2_RXN_7
PEG2_RXP_7
PEG2_TXN_6
AL6
AR5
AT4
AE11
AE10
AH3
AL10
AL11
Datasheet
323
Testability
Table 46.
XOR Chain 14 (DDR2,
NoECC)
Pin
Count
Ball #
Signal Name
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AP1
AR2
PEG2_TXN_12
PEG2_TXP_12
PEG2_RXN_12
PEG2_RXP_12
PEG2_TXN_11
PEG2_TXP_11
PEG2_RXN_11
PEG2_RXP_11
PEG2_TXN_10
PEG2_TXP_10
PEG2_RXN_10
PEG2_RXP_10
PEG2_TXN_9
PEG2_TXP_9
PEG2_RXN_9
PEG2_RXP_9
PEG2_TXN_8
PEG2_TXP_8
PEG2_RXN_8
PEG2_RXP_8
AK13
AK12
AN5
AP4
AH6
AH7
AM3
AN2
AH10
AH11
AL5
AM4
AH13
AG12
AK1
AL2
AE6
AE7
324
Datasheet
Testability
13.3.2
XOR Chains for DDR2 (ECC)
Table 47.
XOR Chain 0 (DDR2,
ECC)
Table 47.
XOR Chain 0 (DDR2,
ECC)
Pin
Count
Ball
Signal Name
Pin
Count
Ball
#
Signal Name
#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
K28
K24
F31
L30
G30
N24
H31
H30
L28
M30
N30
K31
L25
E42
F41
G42
G44
H42
J43
FSB_DB_40
FSB_DB_46
FSB_DB_32
FSB_DB_36
FSB_DB_38
FSB_DB_42
FSB_DB_34
FSB_DB_39
FSB_DB_41
FSB_DB_35
FSB_DB_37
FSB_DB_33
FSB_DB_43
FSB_DB_15
FSB_DB_14
FSB_DB_11
FSB_DB_13
FSB_DB_9
FSB_DB_8
FSB_DB_12
FSB_DB_7
FSB_DB_5
FSB_DB_3
FSB_DB_6
FSB_DB_10
FSB_DB_0
FSB_DB_1
FSB_DB_4
FSB_DB_2
M21
ALLZTEST
1
B39
D44
B42
D39
C42
C36
A38
B35
D38
E41
D43
D36
E35
E37
F35
C37
F33
B43
F39
F38
H33
G36
G38
G35
L36
L33
L34
N33
N31
K34
M31
K35
L24
H24
G24
FSB_DB_56
FSB_DB_52
FSB_DB_55
FSB_DB_57
FSB_DB_51
FSB_DB_58
FSB_DB_49
FSB_DB_62
FSB_DB_54
FSB_DB_50
FSB_DB_53
FSB_DB_59
FSB_DB_63
FSB_DB_61
FSB_DB_48
FSB_DB_60
FSB_DB_26
FSB_DB_18
FSB_DB_17
FSB_DB_16
FSB_DB_25
FSB_DB_22
FSB_DB_20
FSB_DB_23
FSB_DB_19
FSB_DB_29
FSB_DB_27
FSB_DB_28
FSB_DB_30
FSB_DB_24
FSB_DB_31
FSB_DB_21
FSB_DB_44
FSB_DB_45
FSB_DB_47
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
H45
L42
M45
M42
L44
J41
P42
N41
N42
N44
Datasheet
325
Testability
Table 48.
XOR Chain 1 (DDR2,
ECC)
Table 49.
XOR Chain 2 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball
#
L22
XORTEST
Signal Name
P16
ICH_SYNCB
1
H39
K42
G40
K36
F43
FSB_REQB_4
FSB_AB_15
FSB_REQB_1
FSB_REQB_3
FSB_AB_3
2
1
2
G34
H34
W41
R42
W40
V42
M25
N25
K43
J44
FSB_DSTBNB_1
FSB_DSTBPB_1
FSB_RSB_1
3
4
5
3
6
M36
K38
M38
L40
FSB_AB_5
4
FSB_HITB
7
FSB_AB_6
5
FSB_TRDYB
8
FSB_AB_4
6
FSB_HITMB
9
FSB_AB_7
7
FSB_DSTBNB_2
FSB_DSTBPB_2
FSB_DSTBNB_0
FSB_DSTBPB_0
FSB_LOCKB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C44
M40
N40
L39
FSB_REQB_0
FSB_ADSTBB_0
FSB_AB_9
8
9
10
11
12
13
14
FSB_REQB_2
FSB_AB_8
T45
U42
H38
D35
N36
N39
N38
R35
N34
R39
R36
T34
FSB_BNRB
FSB_AB_11
FSB_AB_13
FSB_AB_16
FSB_AB_12
FSB_AB_14
FSB_AB_10
FSB_AB_19
FSB_AB_21
FSB_AB_17
FSB_AB_25
FSB_AB_30
FSB_AB_20
FSB_AB_26
FSB_AB_27
FSB_AB_22
FSB_ADSTBB_1
FSB_AB_31
FSB_AB_18
FSB_AB_34
FSB_AB_32
FSB_AB_23
FSB_AB_29
FSB_AB_24
FSB_AB_33
FSB_AB_28
FSB_AB_35
FSB_BPRIB
FSB_CPURSTB
Table 50.
XOR Chain 3 (DDR2,
ECC)
P43
Pin
Count
Ball
#
Signal Name
T40
W34
W36
T38
N18
RSVD
1
2
D41
C40
B37
E40
T39
R44
U41
T42
R41
N28
L41
W44
U44
FSB_DSTBNB_3
FSB_DSTBPB_3
FSB_DINVB_3
FSB_DINVB_1
FSB_DEFERB
FSB_RSB_0
V35
W33
W38
V34
AA33
T36
3
4
5
6
AB35
AA35
V38
AB34
V39
AA40
V43
AA38
7
FSB_DRDYB
FSB_DBSYB
8
9
FSB_RSB_2
10
11
12
13
FSB_DINVB_2
FSB_DINVB_0
FSB_BREQ0B
FSB_ADSB
326
Datasheet
Testability
Table 51.
XOR Chain 4 (DDR2,
ECC)
Table 51.
XOR Chain 4 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
37
38
39
BC10
BC6
DDR_A_DM_1
DDR_A_DQSB_0
DDR_A_DM_0
AN12
RSVD
BB5
1
AK35
AL33
AK34
AK33
AK39
AN35
AL34
AK38
AY41
BB39
BD42
BD37
BB43
BC36
BA27
BB30
BB29
BA29
AV35
AT34
AT33
AN28
AR33
AM28
BD29
BB31
BB28
BC28
AY27
AY24
BB25
AV21
AP21
AY15
BC14
AY11
DDR_A_CB_3
DDR_A_CB_0
DDR_A_CB_6
DDR_A_CB_4
DDR_A_CB_7
DDR_A_CB_1
DDR_A_CB_5
DDR_A_CB_2
DDR_A_ODT_1
DDR_A_CSB_1
DDR_A_CSB_0
DDR_A_MA_10
DDR_A_ODT_0
DDR_A_MA_0
DDR_A_MA_9
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_CKB_2
DDR_A_CK_2
DDR_A_CK_0
DDR_A_CK_1
DDR_A_CKB_0
DDR_A_CKB_1
DDR_A_MA_6
DDR_A_MA_1
DDR_A_MA_5
DDR_A_MA_8
DDR_A_MA_7
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_DQSB_3
DDR_A_DM_3
DDR_A_DQSB_2
DDR_A_DM_2
DDR_A_DQSB_1
2
Table 52.
XOR Chain 5 (DDR2,
ECC)
3
4
Pin
Count
Ball #
Signal Name
5
6
AM14
RSVD
7
8
1
2
AA44
AB40
AD42
AE44
AL36
AM42
AN44
AT42
AU44
BA42
BB41
BD39
BB36
BB38
BC37
BA25
BD27
BB26
BB27
AK15
AK14
DDR_A_DQSB_7
DDR_A_DM_7
DDR_A_DQSB_6
DDR_A_DM_6
DDR_A_DQSB_8
DDR_A_DQSB_5
DDR_A_DM_5
DDR_A_DQSB_4
DDR_A_DM_4
DDR_A_MA_13
DDR_A_CASB
DDR_A_WEB
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DDR_A_BS_1
DDR_A_RASB
DDR_A_BS_0
DDR_A_MA_14
DDR_A_MA_11
DDR_A_BS_2
DDR_A_MA_12
CL_DATA
CL_CLK
Datasheet
327
Testability
Table 53.
XOR Chain 6 (DDR2,
ECC)
Table 53.
XOR Chain 6 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
AR42
AT21
AY21
AW19
AN21
AW22
AT22
AN22
AN19
AV19
BA15
BB16
BD15
BE16
BB14
BB15
BA13
BD13
BB13
BA11
BC9
DDR_A_DQ_35
DDR_A_DQS_3
DDR_A_DQ_25
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQ_27
DDR_A_DQ_26
DDR_A_DQ_24
DDR_A_DQ_28
DDR_A_DQS_2
DDR_A_DQ_18
DDR_A_DQ_22
DDR_A_DQ_19
DDR_A_DQ_17
DDR_A_DQ_23
DDR_A_DQ_20
DDR_A_DQ_16
DDR_A_DQ_21
DDR_A_DQS_1
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQ_11
DDR_A_DQ_8
DDR_A_DQ_12
DDR_A_DQ_10
DDR_A_DQ_9
DDR_A_DQS_0
DDR_A_DQ_7
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_6
DDR_A_DQ_1
DDR_A_DQ_0
DDR_A_DQ_5
DDR_A_DQ_4
F21
BSEL1
1
AA42
Y42
DDR_A_DQS_7
DDR_A_DQ_58
DDR_A_DQ_62
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_63
DDR_A_DQ_61
DDR_A_DQS_6
DDR_A_DQ_50
DDR_A_DQ_55
DDR_A_DQ_48
DDR_A_DQ_54
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_49
DDR_A_DQS_8
DDR_A_DQS_5
DDR_A_DQ_46
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_44
DDR_A_DQ_47
DDR_A_DQ_45
DDR_A_DQ_43
DDR_A_DQ_42
DDR_A_DQS_4
DDR_A_DQ_33
DDR_A_DQ_37
DDR_A_DQ_32
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQ_34
DDR_A_DQ_36
2
3
AA41
AB42
AB43
W42
4
5
6
7
AC40
Y45
8
9
AB39
AD43
AC42
AC39
AE41
AD40
AC45
AF42
AF45
AE42
AL38
AM43
AL40
AN41
AN42
AP42
AL41
AP45
AL42
AL44
AT43
AU43
AU41
AV42
AR41
AR40
AR44
AW42
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BD11
BB11
BE12
BD9
BA9
BB12
BB10
BA6
BB7
BB8
BE8
BD7
BD4
BC4
BB4
BD3
328
Datasheet
Testability
Table 55.
XOR Chain 8 (DDR2,
ECC)
Table 54.
XOR Chain 7 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
AP28
AV33
BB21
BB22
BD21
BC22
AW24
BB20
BB19
BE20
BA21
AY19
BD17
AY22
BD19
AR24
AY25
AP16
AW16
AR12
AT13
AT10
AY8
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_MA_5
DDR_B_MA_2
DDR_B_MA_4
DDR_B_MA_1
DDR_B_MA_10
DDR_B_MA_6
DDR_B_MA_9
DDR_B_MA_8
DDR_B_MA_3
DDR_B_MA_7
DDR_B_CKE_0
DDR_B_MA_0
DDR_B_CKE_1
DDR_B_DQSB_3
DDR_B_DM_3
DDR_B_DQSB_2
DDR_B_DM_2
DDR_B_DQSB_1
DDR_B_DM_1
DDR_B_DQSB_0
DDR_B_DM_0
F18
BSEL2
1
2
AW44
AY43
BA41
BB39
AV31
AT31
AT36
AT35
AN27
AM27
BC24
BB25
DDR_A_ODT_3
DDR_A_CSB_3
DDR_A_ODT_2
DDR_A_CSB_2
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CKB_5
DDR_A_CK_5
DDR_A_CK_4
DDR_A_CKB_4
DDR_A_CKE_3
DDR_A_CKE_2
3
4
5
6
7
8
9
10
11
12
Table 55.
XOR Chain 8 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
AN13
RSVD
1
2
AG42
AG44
AG41
AK45
AJ42
DDR_B_CB_2
DDR_B_CB_7
DDR_B_CB_6
DDR_B_CB_0
DDR_B_CB_4
DDR_B_CB_3
DDR_B_CB_1
DDR_B_CB_5
DDR_B_ODT_1
DDR_B_ODT_0
DDR_B_CSB_1
DDR_B_CSB_0
DDR_B_CKB_0
DDR_B_CK_0
DDR_B_CKB_2
DDR_B_CK_1
Table 56.
XOR Chain 9 (DDR2,
ECC)
3
4
Pin
Count
5
Ball #
Signal Name
6
AG40
AJ44
AP12
RSVD
7
8
AK42
BB34
BD33
BB35
BA31
AV30
AW30
AW33
AR28
1
2
3
4
5
6
7
8
AD33
AD35
AG38
AG35
AH42
AP40
AN36
AV38
DDR_B_DQSB_7
DDR_B_DM_7
9
10
11
12
13
14
15
16
DDR_B_DQSB_6
DDR_B_DM_6
DDR_B_DQSB_8
DDR_B_DQSB_5
DDR_B_DM_5
DDR_B_DQSB_4
Datasheet
329
Testability
Table 56.
XOR Chain 9 (DDR2,
ECC)
Table 57.
XOR Chain 10 (DDR2,
ECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
9
AY40
BA33
BD31
BB32
AY31
AY18
BA19
BC18
BB18
BB24
AW23
DDR_B_DM_4
DDR_B_MA_13
DDR_B_RASB
DDR_B_CASB
DDR_B_WEB
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
AP35
AN39
AP36
AV36
AR34
AN40
AR36
AN33
AW39
AV39
AT40
AT38
AV40
AY39
AW38
AW36
AY38
AR25
AV27
AP27
AT25
AT27
AW25
AP24
AN24
AV25
AN18
AT19
AP19
AN16
AT18
AR18
AV16
AR16
AY16
AR13
AV15
AT15
AW13
DDR_B_DQ_42
DDR_B_DQ_46
DDR_B_DQ_41
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_47
DDR_B_DQ_40
DDR_B_DQ_43
DDR_B_DQS_4
DDR_B_DQ_38
DDR_B_DQ_35
DDR_B_DQ_34
DDR_B_DQ_39
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_37
DDR_B_DQ_36
DDR_B_DQS_3
DDR_B_DQ_27
DDR_B_DQ_31
DDR_B_DQ_30
DDR_B_DQ_26
DDR_B_DQ_24
DDR_B_DQ_29
DDR_B_DQ_28
DDR_B_DQ_25
DDR_B_DQS_2
DDR_B_DQ_19
DDR_B_DQ_18
DDR_B_DQ_20
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQ_17
DDR_B_DQ_21
DDR_B_DQ_16
DDR_B_DQS_1
DDR_B_DQ_11
DDR_B_DQ_10
DDR_B_DQ_13
10
11
12
13
14
15
16
17
18
19
DDR_B_MA_12
DDR_B_MA_11
DDR_B_MA_14
DDR_B_BS_2
DDR_B_BS_0
DDR_B_BS_1
Table 57.
XOR Chain 10 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
K19
EXP_SLR
1
2
AC33
AC36
AB32
AB38
AE34
AD36
AE35
AD39
AC34
AG39
AE38
AE33
AE39
AH33
AH34
AH36
AG33
AE40
AH43
AP39
DDR_B_DQS_7
DDR_B_DQ_62
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_61
DDR_B_DQ_57
DDR_B_DQ_60
DDR_B_DQ_56
DDR_B_DQ_63
DDR_B_DQS_6
DDR_B_DQ_51
DDR_B_DQ_55
DDR_B_DQ_50
DDR_B_DQ_52
DDR_B_DQ_48
DDR_B_DQ_53
DDR_B_DQ_49
DDR_B_DQ_54
DDR_B_DQS_8
DDR_B_DQS_5
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
330
Datasheet
Testability
Table 57.
XOR Chain 10 (DDR2,
ECC)
Table 59.
XOR Chain 12 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball
#
Signal Name
60
61
62
63
64
65
66
67
68
69
70
71
72
73
AN15
AY13
AW12
AP15
AY12
AW10
AW8
DDR_B_DQ_14
DDR_B_DQ_9
DDR_B_DQ_12
DDR_B_DQ_15
DDR_B_DQ_8
DDR_B_DQS_0
DDR_B_DQ_0
DDR_B_DQ_2
DDR_B_DQ_7
DDR_B_DQ_1
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_3
DDR_B_DQ_4
M22
BSEL0
1
2
V10
V11
V7
V6
R2
T1
DMI_TXP_3
DMI_TXN_3
DMI_RXP_3
DMI_RXN_3
DMI_TXP_2
DMI_TXN_2
DMI_RXP_2
DMI_RXN_2
DMI_TXP_1
DMI_TXN_1
DMI_RXP_1
DMI_RXN_1
DMI_TXP_0
DMI_TXN_0
DMI_RXP_0
DMI_RXN_0
3
4
AT11
AW11
AY7
5
6
7
P4
AW6
8
R5
N2
P3
AR11
AT12
AV8
9
10
11
12
13
14
15
16
T7
T8
R7
R6
N5
M4
Table 58.
XOR Chain 11 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
L18
RSVD
Table 60.
XOR Chain 13 (DDR2,
ECC)
1
2
AY35
BA35
BB33
BC32
AY34
AW34
AY28
AY30
AP31
AR31
BA17
BB17
DDR_B_ODT_3
DDR_B_CSB_3
DDR_B_ODT_2
DDR_B_CSB_2
DDR_B_CKB_5
DDR_B_CK_5
DDR_B_CKB_4
DDR_B_CK_4
DDR_B_CKB_3
DDR_B_CK_3
DDR_B_CKE_3
DDR_B_CKE_2
Pin
Count
Ball
#
Signal Name
3
4
H21
RSVD
5
6
1
2
A8
B7
PEG_TXN_7
PEG_TXP_7
PEG_RXN_7
PEG_RXP_7
PEG_TXN_6
PEG_TXP_6
PEG_RXN_6
PEG_RXP_6
PEG_TXN_5
PEG_TXP_5
PEG_RXN_5
PEG_RXP_5
7
8
3
H10
G10
E9
9
4
10
11
12
5
6
D8
7
L12
K11
C10
B9
8
9
10
11
12
G12
H12
Datasheet
331
Testability
Table 60.
XOR Chain 13 (DDR2,
ECC)
Table 60.
XOR Chain 13 (DDR2,
ECC)
Pin
Count
Ball
#
Pin
Count
Ball
#
Signal Name
Signal Name
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
E11
D10
M13
N13
A12
B11
K13
L13
D12
E13
G13
H13
D14
E15
C14
B13
E17
D16
B15
A16
L2
PEG_TXN_4
PEG_TXP_4
PEG_RXN_4
PEG_RXP_4
PEG_TXN_3
PEG_TXP_3
PEG_RXN_3
PEG_RXP_3
PEG_TXN_2
PEG_TXP_2
PEG_RXN_2
PEG_RXP_2
PEG_TXN_1
PEG_TXP_1
PEG_RXN_1
PEG_RXP_1
PEG_TXN_0
PEG_TXP_0
PEG_RXN_0
PEG_RXP_0
PEG_TXN_15
PEG_TXP_15
PEG_RXN_15
PEG_RXP_15
PEG_TXN_14
PEG_TXP_14
PEG_RXN_14
PEG_RXP_14
PEG_TXN_13
PEG_TXP_13
PEG_RXN_13
PEG_RXP_13
PEG_TXN_12
PEG_TXP_12
PEG_RXN_12
PEG_RXP_12
PEG_TXN_11
PEG_TXP_11
PEG_RXN_11
52
53
54
55
56
57
58
59
60
61
62
63
64
K7
D3
F3
PEG_RXP_11
PEG_TXN_10
PEG_TXP_10
PEG_RXN_10
PEG_RXP_10
PEG_TXN_9
PEG_TXP_9
PEG_RXN_9
PEG_RXP_9
PEG_TXN_8
PEG_TXP_8
PEG_RXN_8
PEG_RXP_8
C2
D2
B4
B3
G6
F7
C4
C6
D5
E6
Table 61.
XOR Chain 14 (DDR2,
ECC)
Pin
Count
Ball #
Signal Name
G22
RSVD
1
2
AJ5
AK4
PEG2_TXN_7
PEG2_TXP_7
PEG2_RXN_7
PEG2_RXP_7
PEG2_TXN_6
PEG2_TXP_6
PEG2_RXN_6
PEG2_RXP_6
PEG2_TXN_5
PEG2_TXP_5
PEG2_RXN_5
PEG2_RXP_5
PEG2_TXN_4
PEG2_TXP_4
PEG2_RXN_4
PEG2_RXP_4
PEG2_TXN_3
PEG2_TXP_3
M1
N10
N8
3
AE11
AE10
AH3
AJ2
4
K4
5
L5
6
J2
7
AD12
AE13
AG5
AH4
AC7
AC6
AF1
K3
8
H4
9
J5
10
11
12
13
14
15
16
17
18
M8
M7
G2
H1
AG2
AC10
AC11
AE5
L10
M11
E4
F5
AF4
K8
332
Datasheet
Testability
Table 61.
XOR Chain 14 (DDR2,
ECC)
Table 61.
XOR Chain 14 (DDR2,
ECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
AB12
AC13
AD3
AE2
PEG2_RXN_3
PEG2_RXP_3
PEG2_TXN_2
PEG2_TXP_2
PEG2_RXN_2
PEG2_RXP_2
PEG2_TXN_1
PEG2_TXP_1
PEG2_RXN_1
PEG2_RXP_1
PEG2_TXN_0
PEG2_TXP_0
PEG2_RXN_0
PEG2_RXP_0
PEG2_TXN_15
PEG2_TXP_15
PEG2_RXN_15
PEG2_RXP_15
PEG2_TXN_14
PEG2_TXP_14
PEG2_RXN_14
PEG2_RXP_14
PEG2_TXN_13
PEG2_TXP_13
PEG2_RXN_13
PEG2_RXP_13
PEG2_TXN_12
PEG2_TXP_12
PEG2_RXN_12
PEG2_RXP_12
PEG2_TXN_11
PEG2_TXP_11
PEG2_RXN_11
PEG2_RXP_11
PEG2_TXN_10
PEG2_TXP_10
PEG2_RXN_10
PEG2_RXP_10
PEG2_TXN_9
58
59
60
61
62
63
64
AM4
AH13
AG12
AK1
PEG2_TXP_9
PEG2_RXN_9
PEG2_RXP_9
PEG2_TXN_8
PEG2_TXP_8
PEG2_RXN_8
PEG2_RXP_8
AA7
AL2
AA6
AE6
AC4
AD4
AA11
AA10
AB1
AE7
AB3
AA13
W12
AP6
AP7
AP11
AP10
AT3
AU2
AL7
AL6
AR5
AT4
AL10
AL11
AP1
AR2
AK13
AK12
AN5
AP4
AH6
AH7
AM3
AN2
AH10
AH11
AL5
Datasheet
333
Testability
13.3.3
XOR Chains for DDR3 (No ECC)
Table 62.
XOR Chain 0 (DDR3,
NoECC)
Table 62.
XOR Chain 0 (DDR3,
NoECC)
Pin
Count
Ball
Signal Name
Pin
Count
Ball
#
Signal Name
#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
K28
K24
F31
L30
G30
N24
H31
H30
L28
M30
N30
K31
L25
E42
F41
G42
G44
H42
J43
FSB_DB_40
FSB_DB_46
FSB_DB_32
FSB_DB_36
FSB_DB_38
FSB_DB_42
FSB_DB_34
FSB_DB_39
FSB_DB_41
FSB_DB_35
FSB_DB_37
FSB_DB_33
FSB_DB_43
FSB_DB_15
FSB_DB_14
FSB_DB_11
FSB_DB_13
FSB_DB_9
FSB_DB_8
FSB_DB_12
FSB_DB_7
FSB_DB_5
FSB_DB_3
FSB_DB_6
FSB_DB_10
FSB_DB_0
FSB_DB_1
FSB_DB_4
FSB_DB_2
M21
ALLZTEST
1
B39
D44
B42
D39
C42
C36
A38
B35
D38
E41
D43
D36
E35
E37
F35
C37
F33
B43
F39
F38
H33
G36
G38
G35
L36
L33
L34
N33
N31
K34
M31
K35
L24
H24
G24
FSB_DB_56
FSB_DB_52
FSB_DB_55
FSB_DB_57
FSB_DB_51
FSB_DB_58
FSB_DB_49
FSB_DB_62
FSB_DB_54
FSB_DB_50
FSB_DB_53
FSB_DB_59
FSB_DB_63
FSB_DB_61
FSB_DB_48
FSB_DB_60
FSB_DB_26
FSB_DB_18
FSB_DB_17
FSB_DB_16
FSB_DB_25
FSB_DB_22
FSB_DB_20
FSB_DB_23
FSB_DB_19
FSB_DB_29
FSB_DB_27
FSB_DB_28
FSB_DB_30
FSB_DB_24
FSB_DB_31
FSB_DB_21
FSB_DB_44
FSB_DB_45
FSB_DB_47
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
H45
L42
M45
M42
L44
J41
P42
N41
N42
N44
Table 63.
XOR Chain 1 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
L22
XORTEST
1
2
H39
K42
FSB_REQB_4
FSB_AB_15
334
Datasheet
Testability
Table 63.
XOR Chain 1 (DDR3,
NoECC)
Table 64.
XOR Chain 2 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball
#
Signal Name
3
G40
K36
F43
FSB_REQB_1
FSB_REQB_3
FSB_AB_3
P16
ICH_SYNCB
4
5
1
2
G34
H34
W41
R42
W40
V42
M25
N25
K43
J44
FSB_DSTBNB_1
FSB_DSTBPB_1
FSB_RSB_1
6
M36
K38
M38
L40
FSB_AB_5
7
FSB_AB_6
3
8
FSB_AB_4
4
FSB_HITB
9
FSB_AB_7
5
FSB_TRDYB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C44
M40
N40
L39
FSB_REQB_0
FSB_ADSTBB_0
FSB_AB_9
6
FSB_HITMB
7
FSB_DSTBNB_2
FSB_DSTBPB_2
FSB_DSTBNB_0
FSB_DSTBPB_0
FSB_LOCKB
8
FSB_REQB_2
FSB_AB_8
9
N36
N39
N38
R35
N34
R39
R36
T34
10
11
12
13
14
FSB_AB_11
FSB_AB_13
FSB_AB_16
FSB_AB_12
FSB_AB_14
FSB_AB_10
FSB_AB_19
FSB_AB_21
FSB_AB_17
FSB_AB_25
FSB_AB_30
FSB_AB_20
FSB_AB_26
FSB_AB_27
FSB_AB_22
FSB_ADSTBB_1
FSB_AB_31
FSB_AB_18
FSB_AB_34
FSB_AB_32
FSB_AB_23
FSB_AB_29
FSB_AB_24
FSB_AB_33
FSB_AB_28
FSB_AB_35
T45
U42
H38
D35
FSB_BNRB
FSB_BPRIB
FSB_CPURSTB
Table 65.
XOR Chain 3 (DDR3,
NoECC)
P43
Pin
Count
Ball
#
T40
Signal Name
W34
W36
T38
N18
RSVD
1
2
D41
C40
B37
E40
T39
R44
U41
T42
R41
N28
L41
W44
U44
FSB_DSTBNB_3
FSB_DSTBPB_3
FSB_DINVB_3
FSB_DINVB_1
FSB_DEFERB
FSB_RSB_0
V35
W33
W38
V34
AA33
T36
3
4
5
6
7
FSB_DRDYB
FSB_DBSYB
AB35
AA35
V38
AB34
V39
AA40
V43
AA38
8
9
FSB_RSB_2
10
11
12
13
FSB_DINVB_2
FSB_DINVB_0
FSB_BREQ0B
FSB_ADSB
Datasheet
335
Testability
Table 66.
XOR Chain 4 (DDR3,
NoECC)
Table 67.
XOR Chain 5 (DDR3,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
AN12
RSVD
AM14
RSVD
1
AY41
BB39
BD42
BB44
BD37
BB43
BD35
BC36
BA27
BB30
BB29
BA29
AV35
AT34
AT33
AN28
AR33
AM28
BD29
BB31
BB28
BC28
AY27
AY24
BB25
AV21
AP21
AY15
BC14
AY11
BC10
BC6
DDR_A_ODT_1
DDR_A_CSB_1
DDR_A_CSB_0
DDR3_A_CSB_1
DDR_A_MA_10
DDR_A_ODT_0
DDR3_A_MA0
DDR_A_MA_0
DDR_A_MA_9
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_CKB_2
DDR_A_CK_2
DDR_A_CK_0
DDR_A_CK_1
DDR_A_CKB_0
DDR_A_CKB_1
DDR_A_MA_6
DDR_A_MA_1
DDR_A_MA_5
DDR_A_MA_8
DDR_A_MA_7
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_DQSB_3
DDR_A_DM_3
DDR_A_DQSB_2
DDR_A_DM_2
DDR_A_DQSB_1
DDR_A_DM_1
DDR_A_DQSB_0
DDR_A_DM_0
1
2
AA44
AB40
AD42
AE44
AM42
AN44
AT42
AU44
BA42
BB41
BD39
BB36
BC40
BB38
BC37
BA25
BD27
BB26
BB27
AK15
AK14
DDR_A_DQSB_7
DDR_A_DM_7
DDR_A_DQSB_6
DDR_A_DM_6
DDR_A_DQSB_5
DDR_A_DM_5
DDR_A_DQSB_4
DDR_A_DM_4
DDR_A_MA_13
DDR_A_CASB
DDR_A_WEB
DDR_A_BS_1
DDR3_A_WEB
DDR_A_RASB
DDR_A_BS_0
DDR_A_MA_14
DDR_A_MA_11
DDR_A_BS_2
DDR_A_MA_12
CL_DATA
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
10
11
12
13
14
15
16
17
18
19
20
21
CL_CLK
Table 68.
XOR Chain 6 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
F21
BSEL1
1
2
AA42
Y42
DDR_A_DQS_7
DDR_A_DQ_58
DDR_A_DQ_62
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_63
DDR_A_DQ_61
DDR_A_DQS_6
3
AA41
AB42
AB43
W42
AC40
Y45
4
BB5
5
6
7
8
9
AB39
AD43
10
336
Datasheet
Testability
Table 68.
XOR Chain 6 (DDR3,
NoECC)
Table 68.
XOR Chain 6 (DDR3,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
AC42
AC39
AE41
AD40
AC45
AF42
AF45
AE42
AM43
AL40
AN41
AN42
AP42
AL41
AP45
AL42
AL44
AT43
AU43
AU41
AV42
AR41
AR40
AR44
AW42
AR42
AT21
AY21
AW19
AN21
AW22
AT22
AN22
AN19
AV19
BA15
BB16
BD15
BE16
DDR_A_DQ_50
DDR_A_DQ_55
DDR_A_DQ_48
DDR_A_DQ_54
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_49
DDR_A_DQS_5
DDR_A_DQ_46
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_44
DDR_A_DQ_47
DDR_A_DQ_45
DDR_A_DQ_43
DDR_A_DQ_42
DDR_A_DQS_4
DDR_A_DQ_33
DDR_A_DQ_37
DDR_A_DQ_32
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQ_34
DDR_A_DQ_36
DDR_A_DQ_35
DDR_A_DQS_3
DDR_A_DQ_25
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQ_27
DDR_A_DQ_26
DDR_A_DQ_24
DDR_A_DQ_28
DDR_A_DQS_2
DDR_A_DQ_18
DDR_A_DQ_22
DDR_A_DQ_19
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
BB14
BB15
BA13
BD13
BB13
BA11
BC9
DDR_A_DQ_17
DDR_A_DQ_23
DDR_A_DQ_20
DDR_A_DQ_16
DDR_A_DQ_21
DDR_A_DQS_1
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQ_11
DDR_A_DQ_8
DDR_A_DQ_12
DDR_A_DQ_10
DDR_A_DQ_9
DDR_A_DQS_0
DDR_A_DQ_7
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_6
DDR_A_DQ_1
DDR_A_DQ_0
DDR_A_DQ_5
DDR_A_DQ_4
BD11
BB11
BE12
BD9
BA9
BB12
BB10
BA6
BB7
BB8
BE8
BD7
BD4
BC4
BB4
BD3
Table 69.
XOR Chain 7 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
F18
BSEL2
1
2
3
4
5
6
7
8
9
AW44
AY43
BA41
BB39
AV31
AT31
AT36
AT35
AN27
DDR_A_ODT_3
DDR_A_CSB_3
DDR_A_ODT_2
DDR_A_CSB_2
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CKB_5
DDR_A_CK_5
DDR_A_CK_4
Datasheet
337
Testability
Table 69.
XOR Chain 7 (DDR3,
NoECC)
Table 70.
XOR Chain 8 (DDR3,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
10
11
12
13
AM27
BC24
BB25
BB23
DDR_A_CKB_4
DDR_A_CKE_3
DDR_A_CKE_2
DDR3_DRAMRSTB
29
30
31
AT13
AT10
AY8
DDR_B_DM_1
DDR_B_DQSB_0
DDR_B_DM_0
Table 71.
XOR Chain 9 (DDR3,
NoECC)
Table 70.
XOR Chain 8 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball #
Signal Name
AP12
RSVD
AN13
RSVD
1
2
AD33
AD35
AG38
AG35
AP40
AN36
AV38
AY40
BA33
BD31
BB32
AY31
AY18
BA19
BC18
BB18
BB24
AW23
DDR_B_DQSB_7
DDR_B_DM_7
DDR_B_DQSB_6
DDR_B_DM_6
DDR_B_DQSB_5
DDR_B_DM_5
DDR_B_DQSB_4
DDR_B_DM_4
DDR_B_MA_13
DDR_B_RASB
DDR_B_CASB
DDR_B_WEB
1
BB34
BD33
BB35
BA31
AV30
AW30
AW33
AR28
AP28
AV33
BB21
BB22
BD21
BC22
AW24
BB20
BB19
BE20
BA21
AY19
BD17
AY22
BD19
AR24
AY25
AP16
AW16
AR12
DDR_B_ODT_1
DDR_B_ODT_0
DDR_B_CSB_1
DDR_B_CSB_0
DDR_B_CKB_0
DDR_B_CK_0
DDR_B_CKB_2
DDR_B_CK_1
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_MA_5
DDR_B_MA_2
DDR_B_MA_4
DDR_B_MA_1
DDR_B_MA_10
DDR_B_MA_6
DDR_B_MA_9
DDR_B_MA_8
DDR_B_MA_3
DDR_B_MA_7
DDR_B_CKE_0
DDR_B_MA_0
DDR_B_CKE_1
DDR_B_DQSB_3
DDR_B_DM_3
DDR_B_DQSB_2
DDR_B_DM_2
DDR_B_DQSB_1
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DDR_B_MA_12
DDR_B_MA_11
DDR_B_MA_14
DDR_B_BS_2
DDR_B_BS_0
DDR_B_BS_1
Table 72.
XOR Chain 10 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
K19
EXP_SLR
1
2
3
4
AC33
AC36
AB32
AB38
DDR_B_DQS_7
DDR_B_DQ_62
DDR_B_DQ_58
DDR_B_DQ_59
338
Datasheet
Testability
Table 72.
XOR Chain 10 (DDR3,
NoECC)
Table 72.
XOR Chain 10 (DDR3,
NoECC)
Pin
Count
Pin
Count
Ball #
Signal Name
Ball #
Signal Name
5
AE34
AD36
AE35
AD39
AC34
AG39
AE38
AE33
AE39
AH33
AH34
AH36
AG33
AE40
AP39
AP35
AN39
AP36
AV36
AR34
AN40
AR36
AN33
AW39
AV39
AT40
AT38
AV40
AY39
AW38
AW36
AY38
AR25
AV27
AP27
AT25
AT27
AW25
AP24
DDR_B_DQ_61
DDR_B_DQ_57
DDR_B_DQ_60
DDR_B_DQ_56
DDR_B_DQ_63
DDR_B_DQS_6
DDR_B_DQ_51
DDR_B_DQ_55
DDR_B_DQ_50
DDR_B_DQ_52
DDR_B_DQ_48
DDR_B_DQ_53
DDR_B_DQ_49
DDR_B_DQ_54
DDR_B_DQS_5
DDR_B_DQ_42
DDR_B_DQ_46
DDR_B_DQ_41
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_47
DDR_B_DQ_40
DDR_B_DQ_43
DDR_B_DQS_4
DDR_B_DQ_38
DDR_B_DQ_35
DDR_B_DQ_34
DDR_B_DQ_39
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_37
DDR_B_DQ_36
DDR_B_DQS_3
DDR_B_DQ_27
DDR_B_DQ_31
DDR_B_DQ_30
DDR_B_DQ_26
DDR_B_DQ_24
DDR_B_DQ_29
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AN24
AV25
AN18
AT19
AP19
AN16
AT18
AR18
AV16
AR16
AY16
AR13
AV15
AT15
AW13
AN15
AY13
AW12
AP15
AY12
AW10
AW8
DDR_B_DQ_28
DDR_B_DQ_25
DDR_B_DQS_2
DDR_B_DQ_19
DDR_B_DQ_18
DDR_B_DQ_20
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQ_17
DDR_B_DQ_21
DDR_B_DQ_16
DDR_B_DQS_1
DDR_B_DQ_11
DDR_B_DQ_10
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_9
DDR_B_DQ_12
DDR_B_DQ_15
DDR_B_DQ_8
DDR_B_DQS_0
DDR_B_DQ_0
DDR_B_DQ_2
DDR_B_DQ_7
DDR_B_DQ_1
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_3
DDR_B_DQ_4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
AT11
AW11
AY7
AW6
AR11
AT12
AV8
Table 73.
XOR Chain 11 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
L18
RSVD
1
2
3
AY35
BA35
BB33
DDR_B_ODT_3
DDR_B_CSB_3
DDR_B_ODT_2
Datasheet
339
Testability
Table 73.
XOR Chain 11 (DDR3,
NoECC)
Table 75.
XOR Chain 13 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
Pin
Count
Ball
#
Signal Name
4
5
BA37
BC32
AY34
AW34
AY28
AY30
AP31
AR31
BA17
BB17
DDR3_B_ODT3
DDR_B_CSB_2
DDR_B_CKB_5
DDR_B_CK_5
DDR_B_CKB_4
DDR_B_CK_4
DDR_B_CKB_3
DDR_B_CK_3
DDR_B_CKE_3
DDR_B_CKE_2
H21
RSVD
6
1
A8
B7
PEG_TXN_7
PEG_TXP_7
PEG_RXN_7
PEG_RXP_7
PEG_TXN_6
PEG_TXP_6
PEG_RXN_6
PEG_RXP_6
PEG_TXN_5
PEG_TXP_5
PEG_RXN_5
PEG_RXP_5
PEG_TXN_4
PEG_TXP_4
PEG_RXN_4
PEG_RXP_4
PEG_TXN_3
PEG_TXP_3
PEG_RXN_3
PEG_RXP_3
PEG_TXN_2
PEG_TXP_2
PEG_RXN_2
PEG_RXP_2
PEG_TXN_1
PEG_TXP_1
PEG_RXN_1
PEG_RXP_1
PEG_TXN_0
PEG_TXP_0
PEG_RXN_0
PEG_RXP_0
PEG_TXN_15
PEG_TXP_15
PEG_RXN_15
PEG_RXP_15
PEG_TXN_14
7
2
8
3
H10
G10
E9
9
4
10
11
12
13
5
6
D8
7
L12
K11
C10
B9
8
9
Table 74.
XOR Chain 12 (DDR3,
NoECC)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
G12
H12
E11
D10
M13
N13
A12
B11
K13
L13
D12
E13
G13
H13
D14
E15
C14
B13
E17
D16
B15
A16
L2
Pin
Count
Ball
#
Signal Name
M22
BSEL0
1
2
V10
V11
V7
V6
R2
T1
DMI_TXP_3
DMI_TXN_3
DMI_RXP_3
DMI_RXN_3
DMI_TXP_2
DMI_TXN_2
DMI_RXP_2
DMI_RXN_2
DMI_TXP_1
DMI_TXN_1
DMI_RXP_1
DMI_RXN_1
DMI_TXP_0
DMI_TXN_0
DMI_RXP_0
DMI_RXN_0
3
4
5
6
7
P4
8
R5
N2
P3
9
10
11
12
13
14
15
16
T7
T8
R7
R6
N5
M4
M1
N10
N8
K4
340
Datasheet
Testability
Table 75.
XOR Chain 13 (DDR3,
NoECC)
Table 76.
XOR Chain 14 (DDR3,
NoECC)
Pin
Count
Ball
#
Pin
Count
Signal Name
Ball #
Signal Name
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
L5
J2
PEG_TXP_14
PEG_RXN_14
PEG_RXP_14
PEG_TXN_13
PEG_TXP_13
PEG_RXN_13
PEG_RXP_13
PEG_TXN_12
PEG_TXP_12
PEG_RXN_12
PEG_RXP_12
PEG_TXN_11
PEG_TXP_11
PEG_RXN_11
PEG_RXP_11
PEG_TXN_10
PEG_TXP_10
PEG_RXN_10
PEG_RXP_10
PEG_TXN_9
PEG_TXP_9
PEG_RXN_9
PEG_RXP_9
PEG_TXN_8
PEG_TXP_8
PEG_RXN_8
PEG_RXP_8
6
AJ2
AD12
AE13
AG5
AH4
AC7
AC6
AF1
PEG2_TXP_6
PEG2_RXN_6
PEG2_RXP_6
PEG2_TXN_5
PEG2_TXP_5
PEG2_RXN_5
PEG2_RXP_5
PEG2_TXN_4
PEG2_TXP_4
PEG2_RXN_4
PEG2_RXP_4
PEG2_TXN_3
PEG2_TXP_3
PEG2_RXN_3
PEG2_RXP_3
PEG2_TXN_2
PEG2_TXP_2
PEG2_RXN_2
PEG2_RXP_2
PEG2_TXN_1
PEG2_TXP_1
PEG2_RXN_1
PEG2_RXP_1
PEG2_TXN_0
PEG2_TXP_0
PEG2_RXN_0
PEG2_RXP_0
PEG2_TXN_15
PEG2_TXP_15
PEG2_RXN_15
PEG2_RXP_15
PEG2_TXN_14
PEG2_TXP_14
PEG2_RXN_14
PEG2_RXP_14
PEG2_TXN_13
PEG2_TXP_13
PEG2_RXN_13
PEG2_RXP_13
7
K3
H4
J5
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
M8
M7
G2
H1
L10
M11
E4
F5
AG2
AC10
AC11
AE5
AF4
K8
K7
D3
F3
AB12
AC13
AD3
AE2
C2
D2
B4
B3
G6
F7
AA7
AA6
AC4
AD4
AA11
AA10
AB1
C4
C6
D5
E6
AB3
AA13
W12
AP6
AP7
Table 76.
XOR Chain 14 (DDR3,
NoECC)
AP11
AP10
AT3
Pin
Count
Ball #
Signal Name
G22
RSVD
AU2
AL7
1
2
3
4
5
AJ5
AK4
PEG2_TXN_7
PEG2_TXP_7
PEG2_RXN_7
PEG2_RXP_7
PEG2_TXN_6
AL6
AR5
AT4
AE11
AE10
AH3
AL10
AL11
Datasheet
341
Testability
Table 76.
XOR Chain 14 (DDR3,
NoECC)
Pin
Count
Ball #
Signal Name
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AP1
AR2
PEG2_TXN_12
PEG2_TXP_12
PEG2_RXN_12
PEG2_RXP_12
PEG2_TXN_11
PEG2_TXP_11
PEG2_RXN_11
PEG2_RXP_11
PEG2_TXN_10
PEG2_TXP_10
PEG2_RXN_10
PEG2_RXP_10
PEG2_TXN_9
PEG2_TXP_9
PEG2_RXN_9
PEG2_RXP_9
PEG2_TXN_8
PEG2_TXP_8
PEG2_RXN_8
PEG2_RXP_8
AK13
AK12
AN5
AP4
AH6
AH7
AM3
AN2
AH10
AH11
AL5
AM4
AH13
AG12
AK1
AL2
AE6
AE7
§ §
342
Datasheet
相关型号：
82Z1D-Z33-BA0/753L
Potentiometer, Conductive Plastic, 0.25W, 250000ohm, 10% +/-Tol, -1000,1000ppm/Cel, 1 Turn(s), 6363, ROHS COMPLIANT
BOURNS
82Z1D-Z33-BA0/754L
Potentiometer, Conductive Plastic, 0.25W, 500000ohm, 10% +/-Tol, -1000,1000ppm/Cel, 1 Turn(s), 6363, ROHS COMPLIANT
BOURNS
82_MMBX-S50-0-1/111_NE
RF Connector, 1 Contact(s), Female, Board Mount, Surface Mount Terminal, Jack
AMPHENOL
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