A80376-20 [INTEL]
Microprocessor, 32-Bit, 20MHz, CMOS, CPGA88, PGA-88;
| 型号： | A80376-20 |
| 厂家： | 
INTEL |
| 描述： | Microprocessor, 32-Bit, 20MHz, CMOS, CPGA88, PGA-88 时钟 外围集成电路 装置 |
| 文件： | 总95页 (文件大小：1086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
376TM HIGH PERFORMANCE
32-BIT EMBEDDED PROCESSOR
Y
Y
Y
Full 32-Bit Internal Architecture
Ð 8-, 16-, 32-Bit Data Types
Ð 8 General Purpose 32-Bit Registers
Ð Extensive 32-Bit Instruction Set
Complete Intel Development Support
Ð C, PL/M, Assembler
Ð ICETM-376, In-Circuit Emulator
Ð iRMK Real Time Kernel
Ð iSDM Debug Monitor
Ð DOS Based Debug
High Performance 16-Bit Data Bus
Ð 16 or 20 MHz CPU Clock
Ð Two-Clock Bus Cycles
Y
Extensive Third-Party Support:
Ð Languages: C, Pascal, FORTRAN,
BASIC and ADA*
Ð Hosts: VMS*, UNIX*, MS-DOS*, and
Others
Ð Real-Time Kernels
Ð 16 Mbytes/Sec Bus Bandwidth
Y
Y
16 Mbyte Physical Memory Size
High Speed Numerics Support with the
80387SX
Y
Y
Low System Cost with the 82370
Integrated System Peripheral
Y
Y
High Speed CHMOS IV Technology
Available in 100 Pin Plastic Quad Flat-
Pack Package and 88-Pin Pin Grid Array
On-Chip Debugging Support Including
Break Point Registers
Ý
(See Packaging Outlines and Dimensions 231369)
INTRODUCTION
The 376 32-bit embedded processor is designed for high performance embedded systems. It provides the
performance benefits of a highly pipelined 32-bit internal architecture with the low system cost associated with
16-bit hardware systems. The 80376 processor is based on the 80386 and offers a high degree of compatibil-
ity with the 80386. All 80386 32-bit programs not dependent on paging can be executed on the 80376 and all
80376 programs can be executed on the 80386. All 32-bit 80386 language translators can be used for
software development. With proper support software, any 80386-based computer can be used to develop and
test 80376 programs. In addition, any 80386-based PC-AT* compatible computer can be used for hardware
prototyping for designs based on the 80376 and its companion product the 82370.
240182–48
80376 Microarchitecture
Intel, iRMK, ICE, 376, 386, Intel386, iSDM, Intel1376 are trademarks of Intel Corp.
*UNIX is a registered trademark of AT&T.
ADA is a registered trademark of the U.S. Government, Ada Joint Program Office.
PC-AT is a registered trademark of IBM Corporation.
VMS is a trademark of Digital Equipment Corporation.
MS-DOS is a trademark of MicroSoft Corporation.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
December 1990
Order Number: 240182-004
376 EMBEDDED PROCESSOR
1.0 PIN DESCRIPTION
240182–52
Figure 1.1. 80376 100-Pin Quad Flat-Pack Pin Out (Top View)
Table 1.1. 100-Pin Plastic Quad Flat-Pack Pin Assignments
Address
Data
Control
N/C
V
CC
V
SS
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
18
51
52
53
54
55
56
58
59
60
61
62
64
65
66
70
72
73
74
75
76
79
80
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
1
100
99
96
95
94
93
92
90
89
88
87
86
83
82
81
ADS
BHE
BLE
BUSY
CLK2
D/C
16
19
17
34
15
24
36
28
3
20
27
8
9
2
5
1
2
3
4
5
6
7
8
9
0
1
10
21
32
39
42
48
57
69
71
84
91
97
11
12
13
14
22
35
41
49
50
63
67
68
77
78
85
98
2
29
30
31
43
44
45
46
47
3
4
5
ERROR
FLT
6
7
HLDA
HOLD
INTR
LOCK
M/IO
NA
8
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
9
40
26
23
6
38
37
7
10
11
12
13
14
15
NMI
PEREQ
READY
RESET
W/R
33
25
2
376 EMBEDDED PROCESSOR
Top View
(Component Side)
240182–49
Bottom View
(Pin Side)
240182–2
Figure 1.2. 80376 88-Pin Grid Array Pin Out
3
376 EMBEDDED PROCESSOR
Table 1.2. 88-Pin Grid Array Pin Assignments
Pin
2H
9B
8A
8B
7A
7B
6A
6B
5A
5B
4B
4A
3B
2D
1E
Label
Pin
Label
Pin
2L
Label
M/IO
Pin
11A
13A
13C
13L
1N
Label
CLK2
12D
12E
13E
12F
13F
12G
13G
13H
12H
13J
12J
12K
13K
12L
12M
11M
10M
1K
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
18
17
16
15
14
13
12
11
10
9
CC
CC
CC
CC
CC
CC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
5M
1J
LOCK
ADS
15
14
13
12
11
10
9
1H
2G
1G
2F
READY
NA
HOLD
HLDA
PEREQ
BUSY
ERROR
INTR
13N
11B
2C
7N
7M
8N
9M
8M
6M
2B
12B
1C
2M
3N
5N
10N
1A
3A
1D
8
1M
4N
7
6
8
NMI
9N
5
7
RESET
11N
2A
4
6
V
V
V
V
V
V
V
V
V
3
5
CC
CC
CC
CC
CC
CC
CC
CC
CC
12A
1B
2
4
2E
1
3
1F
13B
13M
2N
0
2
9A
10A
10B
12C
13D
A
A
A
A
A
23
22
21
20
19
1
2J
BLE
BHE
W/R
D/C
2K
6N
4M
12N
1L
3M
N/C
4
376 EMBEDDED PROCESSOR
The following table lists a brief description of each pin on the 80376. The following definitions are used in
these descriptions:
The named signal is active LOW.
Input signal.
Output signal.
I
O
I/O Input and Output signal.
No electrical connection.
Ð
Symbol
Type
Name and Function
CLK2
I
CLK2 provides the fundamental timing for the 80376. For additional
information see Clock in Section 4.1.
RESET
I
RESET suspends any operation in progress and places the 80376 in a
known reset state. See Interrupt Signals in Section 4.1 for additional
information.
D
15
–D
I/O
DATA BUS inputs data during memory, I/O and interrupt acknowledge
read cycles and outputs data during memory and I/O write cycles. See
Data Bus in Section 4.1 for additional information.
0
A
–A
O
O
ADDRESS BUS outputs physical memory or port I/O addresses. See
Address Bus in Section 4.1 for additional information.
23
1
W/R
D/C
WRITE/READ is a bus cycle definition pin that distinguishes write
cycles from read cycles. See Bus Cycle Definition Signals in Section
4.1 for additional information.
O
DATA/CONTROL is a bus cycle definition pin that distinguishes data
cycles, either memory or I/O, from control cycles which are: interrupt
acknowledge, halt, and instruction fetching. See Bus Cycle Definition
Signals in Section 4.1 for additional information.
M/IO
O
O
MEMORY I/O is a bus cycle definition pin that distinguishes memory
cycles from input/output cycles. See Bus Cycle Definition Signals in
Section 4.1 for additional information.
LOCK
BUS LOCK is a bus cycle definition pin that indicates that other
system bus masters are denied access to the system bus while it is
active. See Bus Cycle Definition Signals in Section 4.1 for additional
information.
ADS
NA
O
ADDRESS STATUS indicates that a valid bus cycle definition and
address (W/R, D/C, M/IO, BHE, BLE and A –A ) are being driven at
23 1
the 80376 pins. See Bus Control Signals in Section 4.1 for additional
information.
I
I
NEXT ADDRESS is used to request address pipelining. See Bus
Control Signals in Section 4.1 for additional information.
READY
BUS READY terminates the bus cycle. See Bus Control Signals in
Section 4.1 for additional information.
BHE, BLE
O
BYTE ENABLES indicate which data bytes of the data bus take part in
bus cycle. See Address Bus in Section 4.1 for additional
a
information.
HOLD
I
BUS HOLD REQUEST input allows another bus master to request
control of the local bus. See Bus Arbitration Signals in Section 4.1
for additional information.
5
376 EMBEDDED PROCESSOR
Symbol
Type
Name and Function
HLDA
O
BUS HOLD ACKNOWLEDGE output indicates that the 80376 has
surrendered control of its local bus to another bus master. See Bus
Arbitration Signals in Section 4.1 for additional information.
INTR
NMI
I
I
INTERRUPT REQUEST is a maskable input that signals the 80376 to
suspend execution of the current program and execute an interrupt
acknowledge function. See Interrupt Signals in Section 4.1 for
additional information.
NON-MASKABLE INTERRUPT REQUEST is a non-maskable input
that signals the 80376 to suspend execution of the current program
and execute an interrupt acknowledge function. See Interrupt Signals
in Section 4.1 for additional information.
BUSY
ERROR
PEREQ
FLT
I
I
BUSY signals a busy condition from a processor extension. See
Coprocessor Interface Signals in Section 4.1 for additional
information.
ERROR signals an error condition from a processor extension. See
Coprocessor Interface Signals in Section 4.1 for additional
information.
I
PROCESSOR EXTENSION REQUEST indicates that the processor
extension has data to be transferred by the 80376. See Coprocessor
Interface Signals in Section 4.1 for additional information.
I
FLOAT, when active, forces all bidirectional and output signals,
including HLDA, to the float condition. FLOAT is not available on the
PGA package. See Float for additional information.
N/C
Ð
NO CONNECT should always remain unconnected. Connection of a
N/C pin may cause the processor to malfunction or be incompatible
with future steppings of the 80376.
a
SYSTEM POWER provides the 5V nominal D.C. supply input.
V
V
I
I
CC
SS
SYSTEM GROUND provides 0V connection from which all inputs and
outputs are measured.
sists of the execution unit and instruction unit. The
2.0 ARCHITECTURE OVERVIEW
execution unit contains the eight 32-bit general reg-
isters which are used for both address calculation
and data operations and a 64-bit barrel shifter used
to speed shift, rotate, multiply, and divide operations.
The instruction unit decodes the instruction opcodes
and stores them in the decoded instruction queue
for immediate use by the execution unit.
The 80376 supports the protection mechanisms
needed by sophisticated multitasking embedded
systems and real-time operating systems. The use
of these protection mechanisms is completely op-
tional. For embedded applications not needing pro-
tection, the 80376 can easily be configured to pro-
vide a 16 Mbyte physical address space.
The Memory Management Unit (MMU) consists of a
segmentation and protection unit. Segmentation al-
lows the managing of the logical address space by
providing an extra addressing component, one that
allows easy code and data relocatability, and effi-
cient sharing.
Instruction pipelining, high bus bandwidth, and a
very high performance ALU ensure short average
instruction execution times and high system
throughput. The 80376 is capable of execution at
sustained rates of 2.5–3.0 million instructions per
second.
The protection unit provides four levels of protection
for isolating and protecting applications and the op-
erating system from each other. The hardware en-
forced protection allows the design of systems with
a high degree of integrity and simplifies debugging.
The 80376 offers on-chip testability and debugging
features. Four break point registers allow conditional
or unconditional break point traps on code execution
or data accesses for powerful debugging of even
ROM based systems. Other testability features in-
clude self-test and tri-stating of output buffers during
RESET.
Finally, to facilitate high performance system hard-
ware designs, the 80376 bus interface offers ad-
dress pipelining and direct Byte Enable signals for
each byte of the data bus.
The Intel 80376 embedded processor consists of a
central processing unit, a memory management unit
and a bus interface. The central processing unit con-
6
376 EMBEDDED PROCESSOR
2.1 Register Set
The 80376 has twenty-nine registers as shown in Figure 2.1. These registers are grouped into the following six
categories:
240182–47
240182–5
Figure 2.1. 80376 Base Architecture Registers
7
376 EMBEDDED PROCESSOR
General Registers: The eight 32-bit general pur-
pose registers are used to contain arithmetic and
logical operands. Four of these (EAX, EBX, ECX and
EDX) can be used either in their entirety as 32-bit
registers, as 16-bit registers, or split into pairs of
separate 8-bit registers.
System Address Registers: These four special
registers reference the tables or segments support-
ed by the 80376/80386 protection model. These ta-
bles or segments are:
GDTR (Global Descriptor Table Register),
IDTR (Interrupt Descriptor Table Register),
LDTR (Local Descriptor Table Register),
TR (Task State Segment Register).
Segment Registers: Six 16-bit special purpose reg-
isters select, at any given time, the segments of
memory that are immediately addressable for code,
stack, and data.
Debug Registers: The six programmer accessible
debug registers provide on-chip support for debug-
ging. The use of the debug registers is described in
Section 2.11 Debugging Support.
Flags and Instruction Pointer Registers: These
two 32-bit special purpose registers in Figure 2.1
record or control certain aspects of the 80376 proc-
essor state. The EFLAGS register includes status
and control bits that are used to reflect the outcome
of many instructions and modify the semantics of
some instructions. The Instruction Pointer, called
EIP, is 32 bits wide. The Instruction Pointer controls
instruction fetching and the processor automatically
increments it after executing an instruction.
EFLAGS REGISTER
The flag Register is
a 32-bit register named
EFLAGS. The defined bits and bit fields within
EFLAGS, shown in Figure 2.2, control certain opera-
tions and indicate the status of the 80376 processor.
The function of the flag bits is given in Table 2.1.
Control Register: The 32-bit control register, CR0,
is used to control Coprocessor Emulation.
240182–3
240182–4
240182–5
Figure 2.2. Status and Control Register Bit Functions
8
376 EMBEDDED PROCESSOR
Table 2.1. Flag Definitions
Function
Bit Position
Name
CF
0
2
Carry FlagÐSet on high-order bit carry or borrow; cleared otherwise.
PF
Parity FlagÐSet if low-order 8 bits of result contain an even number
of 1-bits; cleared otherwise.
4
AF
Auxiliary Carry FlagÐSet on carry from or borrow to the low order
four bits of AL; cleared otherwise.
6
7
ZF
SF
Zero FlagÐSet if result is zero; cleared otherwise.
Sign FlagÐSet equal to high-order bit of result (0 if positive, 1 if
negative).
8
9
TF
IF
Single Step FlagÐOnce set, a single step interrupt occurs after the
next instruction executes. TF is cleared by the single step interrupt.
Interrupt-Enable FlagÐWhen set, external interrupts signaled on the
INTR pin will cause the CPU to transfer control to an interrupt vector
specified location.
10
DF
OF
Direction FlagÐCauses string instructions to auto-increment (default)
the appropriate index registers when cleared. Setting DF causes auto-
decrement.
11
Overflow FlagÐSet if the operation resulted in a carry/borrow into
the sign bit (high-order bit) of the result but did not result in a
carry/borrow out of the high-order bit or vice-versa.
12, 13
IOPL
I/O Privilege LevelÐIndicates the maximum CPL permitted to
execute I/O instructions without generating an exception 13 fault or
consulting the I/O permission bit map. It also indicates the maximum
CPL value allowing alteration of the IF bit.
14
16
NT
RF
Nested TaskÐIndicates that the execution of the current task is
nested within another task (see Task Switching).
Resume FlagÐUsed in conjunction with debug register breakpoints. It
is checked at instruction boundaries before breakpoint processing. If
set, any debug fault is ignored on the next instruction. It is reset at the
successful completion of any instruction except IRET, POPF, and
those instructions causing task switches.
CONTROL REGISTER
The 80376 has a 32-bit control register called CR0 that is used to control coprocessor emulation. This register
is shown in Figures, 2.1 and 2.2. The defined CR0 bits are described in Table 2.2. Bits 0, 4 and 31 of CR0 have
fixed values in the 80376. These values cannot be changed. Programs that load CR0 should always load bits
0, 4 and 31 with values previously there to be compatible with the 80386.
Table 2.2. CR0 Definitions
Bit Position
Name
Function
1
MP
Monitor Coprocessor ExtensionÐAllows WAIT instructions to cause
a processor extension not present exception (number 7).
2
3
EM
TS
Emulate Processor ExtensionÐWhen set, this bit causes a
processor extension not present exception (number 7) on ESC
instructions to allow processor extension emulation.
Task SwitchedÐWhen set, this bit indicates the next instruction using
a processor extension will cause exception 7, allowing software to test
whether the current processor extension context belongs to the
current task (see Task Switching).
9
376 EMBEDDED PROCESSOR
2.2 Instruction Set
2.3 Memory Organization
The instruction set is divided into nine categories of
operations:
Memory on the 80376 is divided into 8-bit quantities
(bytes), 16-bit quantities (words), and 32-bit quanti-
ties (dwords). Words are stored in two consecutive
bytes in memory with the low-order byte at the low-
est address. Dwords are stored in four consecutive
bytes in memory with the low-order byte at the low-
est address. The address of a word or Dword is the
byte address of the low-order byte. For maximum
performance word and dword values should be at
even physical addresses.
Data Transfer
Arithmetic
Shift/Rotate
String Manipulation
Bit Manipulation
Control Transfer
High Level Language Support
Operating System Support
Processor Control
In addition to these basic data types the 80376 proc-
essor supports segments. Memory can be divided
up into one or more variable length segments, which
can be shared between programs.
These 80376 processor instructions are listed in Ta-
ble 8.1 80376 Instruction Set and Clock Count
Summary.
ADDRESS SPACES
All 80376 processor instructions operate on either 0,
1, 2 or 3 operands; an operand resides in a register,
in the instruction itself, or in memory. Most zero op-
erand instructions (e.g. CLI, STI) take only one byte.
One operand instructions generally are two bytes
long. The average instruction is 3.2 bytes long.
Since the 80376 has a 16-byte prefetch instruction
queue an average of 5 instructions can be pre-
fetched. The use of two operands permits the follow-
ing types of common instructions:
The 80376 has three types of address spaces: logi-
cal, linear, and physical. A logical address (also
known as a virtual address) consists of a selector
and an offset. A selector is the contents of a seg-
ment register. An offset is formed by summing all of
the addressing components (BASE, INDEX, and
DISPLACEMENT), discussed in Section 2.4 Ad-
dressing Modes, into an effective address.
Every selector has a logical base address associat-
ed with it that can be up to 32 bits in length. This 32-
bit logical base address is added to either a 32-bit
offset address or a 16-bit offset address (by using
the address length prefix )to form a final 32-bit lin-
ear address. This final linear address is then trun-
cated so that only the lower 24 bits of this address
are used to address the 16 Mbytes physical memory
address space. The logical base address is stored
in one of two operating system tables (i.e. the Local
Descriptor Table or Global Descriptor Table).
Register to Register
Memory to Register
Immediate to Register
Memory to Memory
Register to Memory
Immediate to Memory
The operands are either 8-, 16- or 32-bit long.
Figure 2.3 shows the relationship between the vari-
ous address spaces.
10
376 EMBEDDED PROCESSOR
240182–6
Figure 2.3. Address Translation
ister is used. The segment register is automatically
chosen according to the rules of Table 2.3 (Segment
Register Selection Rules). In general, data refer-
ences use the selector contained in the DS register,
stack references use the SS register and instruction
fetches use the CS register. The contents of the In-
struction Pointer provide the offset. Special segment
override prefixes allow the explicit use of a given
segment register, and override the implicit rules list-
ed in Table 2.3. The override prefixes also allow the
use of the ES, FS and GS segment registers.
SEGMENT REGISTER USAGE
The main data structure used to organize memory is
the segment. On the 80376, segments are variable
sized blocks of linear addresses which have certain
attributes associated with them. There are two main
types of segments, code and data. The simplest use
of segments is to have one code and data segment.
Each segment is 16 Mbytes in size overlapping each
other. This allows code and data to be directly ad-
dressed by the same offset.
In order to provide compact instruction encoding
and increase processor performance, instructions
do not need to explicitly specify which segment reg-
There are no restrictions regarding the overlapping
of the base addresses of any segments. Thus, all 6
segments could have the base address set to zero.
Further details of segmentation are discussed in
Section 3.0 Architecture.
11
376 EMBEDDED PROCESSOR
Table 2.3. Segment Register Selection Rules
Type of
Implied (Default)
Segment Use
Segment Override
Prefixes Possible
Memory Reference
Code Fetch
CS
SS
None
None
Destination of PUSH, PUSHF, INT,
CALL, PUSHA Instructions
Source of POP, POPA, POPF, IRET,
RET Instructions
SS
ES
None
None
Destination of STOS,
MOVS, REP STOS,
REP MOVS Instructions
(DI is Base Register)
Other Data References,
with Effective Address
Using Base Register of:
[
[
[
[
[
[
[
[
]
]
]
EAX
EBX
ECX
EDX
DS
DS
DS
DS
DS
DS
SS
SS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
CS, SS, ES, FS, GS
]
]
]
ESI
EDI
]
]
EBP
ESP
ment base address and an effective address. The
effective address is calculated by summing any
combination of the following three address elements
(see Figure 2.3):
2.4 Addressing Modes
The 80376 provides a total of 8 addressing modes
for instructions to specify operands. The addressing
modes are optimized to allow the efficient execution
of high level languages such as C and FORTRAN,
and they cover the vast majority of data references
needed by high-level languages.
DISPLACEMENT: an 8-, 16- or 32-bit immediate val-
ue following the instruction.
BASE: The contents of any general purpose regis-
ter. The base registers are generally used by compil-
ers to point to the start of the local variable area.
Note that if theAddress Length Prefix is used, only
BX and BP can be used as a BASE register.
Two of the addressing modes provide for instruc-
tions that operate on register or immediate oper-
ands:
Register Operand Mode: The operand is located in
one of the 8-, 16- or 32-bit general registers.
INDEX: The contents of any general purpose regis-
ter except for ESP. The index registers are used to
access the elements of an array, or a string of char-
acters. The index register’s value can be multiplied
by a scale factor, either 1, 2, 4 or 8. The scaled index
is especially useful for accessing arrays or struc-
tures. Note that if the Address Length Prefix is
used, no Scaling is available and only the registers
SI and DI can be used to INDEX.
Immediate Operand Mode: The operand is includ-
ed in the instruction as part of the opcode.
The remaining 6 modes provide a mechanism for
specifying the effective address of an operand. The
linear address consists of two components: the seg-
12
376 EMBEDDED PROCESSOR
Combinations of these 3 components make up the 6
additional addressing modes. There is no perform-
ance penalty for using any of these addressing com-
binations, since the effective address calculation is
pipelined with the execution of other instructions.
The one exception is the simultaneous use of BASE
and INDEX components which requires one addi-
tional clock.
2. Register Indirect Mode: A BASE register con-
tains the address of the operand.
3. Based Mode: A BASE register’s contents is add-
ed to a DISPLACEMENT to form the operand’s
offset.
4. Scaled Index Mode: An INDEX register’s con-
tents is multiplied by a SCALING factor which is
added to a DISPLACEMENT to form the oper-
and’s offset.
As shown in Figure 2.4, the effective address (EA) of
an operand is calculated according to the following
formula:
5. Based Scaled Index Mode: The contents of an
INDEX register is multiplied by a SCALING factor
and the result is added to the contents of a BASE
register to obtain the operand’s offset.
e
a
BASE
DISPLACEMENT
c
Register
a
scaling)
EA
(INDEX
Register
6. Based Scaled Index Mode with Displacement:
The contents of an INDEX register are multiplied
by a SCALING factor, and the result is added to
the contents of a BASE register and a DISPLACE-
MENT to form the operand’s offset.
1. Direct Mode: The operand’s offset is contained
as part of the instruction as an 8-, 16- or 32-bit
DISPLACEMENT.
240182–7
Figure 2.4. Addressing Mode Calculations
13
376 EMBEDDED PROCESSOR
GENERATING 16-BIT ADDRESSES
blers. The Operand Length and Address Length Pre-
fixes can be applied separately or in combination to
any instruction.
The 80376 executes code with a default length for
operands and addresses of 32 bits. The 80376 is
also able to execute operands and addresses of 16
bits. This is specified through the use of override
prefixes. Two prefixes, the Operand Length Prefix
and the Address Length Prefix, override the de-
fault 32-bit length on an individual instruction basis.
These prefixes are automatically added by assem-
The 80376 normally executes 32-bit code and uses
either 8- or 32-bit displacements, and any register
can be used as based or index registers. When exe-
cuting 16-bit code (by prefix overrides), the displace-
ments are either 8 or 16 bits, and the base and index
register conform to the 16-bit model. Table 2.4 illus-
trates the differences.
Table 2.4. BASE and INDEX Registers for 16- and 32-Bit Addresses
16-Bit Addressing
BX, BP
32-Bit Addressing
BASE REGISTER
INDEX REGISTER
Any 32-Bit GP Register
SI, DI
Any 32-Bit GP Register
except ESP
SCALE FACTOR
DISPLACMENT
None
1, 2, 4, 8
0, 8, 16 Bits
0, 8, 32 Bits
2.5 Data Types
The 80376 supports all of the data types commonly used in high level languages:
Bit:
A single bit quantity.
Bit Field:
A group of up to 32 contiguous bits, which spans a maximum of four
bytes.
Bit String:
A set of contiguous bits, on the 80376 bit strings can be up to 16 Mbits
long.
Byte:
A signed 8-bit quantity.
An unsigned 8-bit quantity.
A signed 16-bit quantity.
Unsigned Byte:
Integer (Word):
Long Integer (Double Word):
A signed 32-bit quantity. All operations assume a 2’s complement
representation.
Unsigned Integer (Word):
An unsigned 16-bit quantity.
Unsigned Long Integer
(Double Word):
An unsigned 32-bit quantity.
A signed 64-bit quantity.
Signed Quad Word:
Unsigned Quad Word:
Pointer:
An unsigned 64-bit quantity.
A 16- or 32-bit offset only quantity which indirectly references another
memory location.
Long Pointer:
A full pointer which consists of a 16-bit segment selector and either a
16- or 32-bit offset.
Char:
A byte representation of an ASCII Alphanumeric or control character.
String:
A contiguous sequence of bytes, words or dwords. A string may
contain between 1 byte and 16 Mbytes.
BCD:
A byte (unpacked) representation of decimal digits 0–9.
Packed BCD:
A byte (packed) representation of two decimal digits 0–9 storing one
digit in each nibble.
14
376 EMBEDDED PROCESSOR
When the 80376 is coupled with a numerics Coprocessor such as the 80387SX then the following
common Floating Point types are supported.
Floating Point:
A signed 32-, 64- or 80-bit real number representation. Floating point
numbers are supported by the 80387SX numerics coprocessor.
Figure 2.5 illustrates the data types supported by the 80376 processor and the 80387SX coprocessor.
240182–8
Figure 2.5. 80376 Supported Data Types
15
376 EMBEDDED PROCESSOR
2.6 I/O Space
struction immediately following the interrupted in-
struction. On the other hand the return address from
an exception/fault routine will always point at the
instruction causing the exception and include any
leading instruction prefixes. Table 2.5 summarizes
the possible interrupts for the 80376 and shows
where the return address points to.
The 80376 has two distinct physical address
spaces: physical memory and I/O. Generally, pe-
ripherals are placed in I/O space although the
80376 also supports memory-mapped peripherals.
The I/O space consists of 64 Kbytes which can be
divided into 64K 8-bit ports, 32K 16-bit ports, or any
combination of ports which add to no more than 64
Kbytes. The M/IO pin acts as an additional address
line, thus allowing the system designer to easily de-
termine which address space the processor is ac-
cessing. Note that the I/O address refers to a physi-
cal address.
The 80376 has the ability to handle up to 256 differ-
ent interrupts/exceptions. In order to service the in-
terrupts, a table with up to 256 interrupt vectors
must be defined. The interrupt vectors are simply
pointers to the appropriate interrupt service routine.
The interrupt vectors are 8-byte quantities, which are
put in an Interrupt Descriptor Table. Of the 256 pos-
sible interrupts, 32 are reserved for use by Intel and
the remaining 224 are free to be used by the system
designer.
The I/O ports are accessed by the IN and OUT in-
structions, with the port address supplied as an im-
mediate 8-bit constant in the instruction or in the DX
register. All 8-bit and 16-bit port addresses are zero
extended on the upper address lines. The I/O in-
structions cause the M/IO pin to be driven LOW. I/O
port addresses 00F8H through 00FFH are reserved
for use by Intel.
INTERRUPT PROCESSING
When an interrupt occurs the following actions hap-
pen. First, the current program address and the
Flags are saved on the stack to allow resumption of
the interrupted program. Next, an 8-bit vector is sup-
plied to the 80376 which identifies the appropriate
entry in the interrupt table. The table contains either
an Interrupt Gate, a Trap Gate or a Task Gate that
will point to an interrupt procedure or task. The user
supplied interrupt service routine is executed. Final-
ly, when an IRET instruction is executed the old
processor state is restored and program execution
resumes at the appropriate instruction.
2.7 Interrupts and Exceptions
Interrupts and exceptions alter the normal program
flow in order to handle external events, report errors
or exceptional conditons. The difference between in-
terrupts and exceptions is that interrupts are used to
handle asynchronous external events while excep-
tions handle instruction faults. Although a program
can generate a software interrupt via an INT N in-
struction, the processor treats software interrupts as
exceptions.
The 8-bit interrupt vector is supplied to the 80376 in
several different ways: exceptions supply the inter-
rupt vector internally; software INT instructions con-
tain or imply the vector; maskable hardware inter-
rupts supply the 8-bit vector via the interrupt ac-
knowledge bus sequence. Non-Maskable hardware
interrupts are assigned to interrupt vector 2.
Hardware interrupts occur as the result of an exter-
nal event and are classified into two types: maskable
or non-maskable. Interrupts are serviced after the
execution of the current instruction. After the inter-
rupt handler is finished servicing the interrupt, exe-
cution proceeds with the instruction immediately af-
ter the interrupted instruction.
Maskable Interrupt
Maskable interrupts are the most common way to
respond to asynchronous external hardware events.
A hardware interrupt occurs when the INTR is pulled
HIGH and the Interrupt Flag bit (IF) is enabled. The
processor only responds to interrupts between in-
structions (string instructions have an ‘‘interrupt win-
dow’’ between memory moves which allows inter-
rupts during long string moves). When an interrupt
occurs the processor reads an 8-bit vector supplied
by the hardware which identifies the source of the
interrupt (one of 224 user defined interrupts).
Exceptions are classified as faults, traps, or aborts
depending on the way they are reported, and wheth-
er or not restart of the instruction causing the excep-
tion is suported. Faults are exceptions that are de-
tected and serviced before the execution of the
faulting instruction. Traps are exceptions that are
reported immediately after the execution of the in-
struction which caused the problem. Aborts are ex-
ceptions which do not permit the precise location of
the instruction causing the exception to be deter-
mined. Thus, when an interrupt service routine has
been completed, execution proceeds from the in-
16
376 EMBEDDED PROCESSOR
Table 2.5. Interrupt Vector Assignments
Return Address
Points to
Instruction Which
Can Cause
Interrupt
Number
Function
Type
Faulting
Exception
Instruction
Divide Error
0
1
2
3
4
5
6
7
DIV, IDIV
Yes
Yes
No
FAULT
TRAP*
NMI
Debug Exception
NMI Interrupt
Any Instruction
INT 2 or NMI
INT
One-Byte Interrupt
Interrupt on Overflow
Array Bounds Check
Invalid OP-Code
Device Not Available
Double Fault
No
TRAP
INTO
No
TRAP
BOUND
Yes
Yes
Yes
FAULT
FAULT
FAULT
ABORT
Any Illegal Instruction
ESC, WAIT
Any Instruction That Can
Generate an Exception
8
Coprocessor Segment Overrun
Invalid TSS
9
10
ESC
No
Yes
Yes
Yes
Yes
Ð
ABORT
FAULT
FAULT
FAULT
FAULT
Ð
JMP, CALL, IRET, INT
Segment Register Instructions
Stack References
Any Memory Reference
Ð
Segment Not Present
Stack Fault
11
12
General Protection Fault
Intel Reserved
13
14–15
16
Coprocessor Error
Intel Reserved
ESC, WAIT
Yes
FAULT
17–32
0–255
Two-Byte Interrupt
INT n
No
TRAP
*Some debug exceptions may report both traps on the previous instruction, and faults on the next instruction.
Interrupts through Interrupt Gates automatically re-
set IF, disabling INTR requests. Interrupts through
Trap Gates leave the state of the IF bit unchanged.
Interrupts through a Task Gate change the IF bit ac-
cording to the image of the EFLAGs register in the
task’s Task State Segment (TSS). When an IRET
instruction is executed, the original state of the IF bit
is restored.
tion is executed or the processor is reset. If NMI
occurs while currently servicing an NMI, its presence
will be saved for servicing after executing the first
IRET instruction. The disabling of INTR requests de-
pends on the gate in IDT location 2.
Software Interrupts
A third type of interrupt/exception for the 80376 is
the software interrupt. An INT n instruction causes
the processor to execute the interrupt service rou-
Non-Maskable Interrupt
th
Non-maskable interrupts provide a method of servic-
ing very high priority interrupts. When the NMI input
is pulled HIGH it causes an interrupt with an internal-
ly supplied vector value of 2. Unlike a normal hard-
ware interrupt no interrupt acknowledgement se-
quence is performed for an NMI.
tine pointed to by the n vector in the interrupt table.
A special case of the two byte software interrupt
INT n is the one byte INT 3, or breakpoint interrupt.
By inserting this one byte instruction in a program,
the user can set breakpoints in his program as a
debugging tool.
While executing the NMI servicing procedure, the
80376 will not service any further NMI request, or
INT requests, until an interrupt return (IRET) instruc-
17
376 EMBEDDED PROCESSOR
A final type of software interrupt, is the single step
interrupt. It is discussed in Single-Step Trap (page
22).
DOUBLE FAULT
A Double fault (exception 8) results when the proc-
essor attempts to invoke an exception service rou-
tine for the segment exceptions (10, 11, 12 or 13),
but in the process of doing so, detects an exception.
INTERRUPT AND EXCEPTION PRIORITIES
Interrupts are externally-generated events. Maska-
ble Interrupts (on the INTR input) and Non-Maskable
Interrupts (on the NMI input) are recognized at in-
struction boundaries. When NMI and maskable
INTR are both recognized at the same instruction
boundary, the 80376 invokes the NMI service rou-
tine first. If, after the NMI service routine has been
invoked, maskable interrupts are still enabled, then
the 80376 will invoke the appropriate interrupt serv-
ice routine.
2.8 Reset and Initialization
When the processor is Reset the registers have the
values shown in Table 2.7. The 80376 will then start
executing instructions near the top of physical mem-
ory, at location 0FFFFF0H. A short JMP should be
executed within the segment defined for power-up
(see Table 2.7). The GDT should then be initialized
for a start-up data and code segment followed by a
far JMP that will load the segment descriptor cache
with the new descriptor values. The IDT table, after
reset, is located at physical address 0H, with a limit
of 256 entries.
As the 80376 executes instructions, it follows a con-
sistent cycle in checking for exceptions, as shown in
Table 2.6. This cycle is repeated as each instruction
is executed, and occurs in parallel with instruction
decoding and execution.
RESET forces the 80376 to terminate all execution
and local bus activity. No instruction execution or
bus activity will occur as long as Reset is active.
Between 350 and 450 CLK2 periods after Reset be-
comes inactive, the 80376 will start executing in-
structions at the top of physical memory.
INSTRUCTION RESTART
The 80376 fully supports restarting all instructions
after faults. If an exception is detected in the instruc-
tion to be executed (exception categories 4 through
9 in Table 2.6), the 80376 device invokes the appro-
priate exception service routine. The 80376 is in a
state that permits restart of the instruction.
Table 2.6. Sequence of Exception Checking
Consider the case of the 80376 having just completed an instruction. It then performs the following checks
before reaching the point where the next instruction is completed:
1. Check for Exception 1 Traps from the instruction just completed (single-step via Trap Flag, or Data
Breakpoints set in the Debug Registers).
2. Check for external NMI and INTR.
3. Check for Exception 1 Faults in the next instruction (Instruction Execution Breakpoint set in the
Debug Registers for the next instruction).
4. Check for Segmentation Faults that prevented fetching the entire next instruction (exceptions 11 or
13).
5. Check for Faults decoding the next instruction (exception 6 if illegal opcode; or exception 13 if
e
instruction is longer than 15 bytes, or privilege violation (i.e. not at IOPL or at CPL
0).
e
e
1 (exception 7 if both are 1).
6. If WAIT opcode, check if TS
1 and MP
e
e
1 (exception 7 if either are 1).
7. If ESCape opcode for numeric coprocessor, check if EM
1 or TS
8. If WAIT opcode or ESCape opcode for numeric coprocessor, check ERROR input signal (exception
16 if ERROR input is asserted).
9. Check for Segmentation Faults that prevent transferring the entire memory quantity (exceptions 11,
12, 13).
18
376 EMBEDDED PROCESSOR
Table 2.7. Register Values after Reset
Flag Word (EFLAGS) uuuu0002H
(Note 1)
(Note 2)
Machine Status Word (CR0)
Instruction Pointer (EIP)
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Extra Segment (FS)
Extra Segment (GS)
EAX Register
uuuuuuu1H
0000FFF0H
F000H
(Note 3)
(Note 4)
0000H
0000H
0000H
(Note 4)
0000H
0000H
0000H
(Note 5)
(Note 6)
(Note 7)
EDX Register
Component and Stepping ID
Undefined
All Other Registers
NOTES:
1. EFLAG Register. The upper 14 bits of the EFLAGS register are undefined, all defined
flag bits are zero.
2. CR0: The defined 4 bits in the CR0 is equal to 1H.
3. The Code Segment Register (CS) will have its Base Address set to 0FFFF0000H and
Limit set to 0FFFFH.
4. The Data and Extra Segment Registers (DS and ES) will have their Base Address set
to 000000000H and Limit set to 0FFFFH.
5. If self-test is selected, the EAX should contain a 0 value. If a value of 0 is not found
the self-test has detected a flaw in the part.
6. EDX register always holds component and stepping identifier.
7. All unidentified bits are Intel Reserved and should not be used.
2.9 Initialization
Because the 80376 processor starts executing in protected mode, certain precautions need be taken during
initialization. Before any far jumps can take place the GDT and/or LDT tables need to be setup and their
respective registers loaded. Before interrupts can be initialized the IDT table must be setup and the IDTR must
be loaded. The example code is shown below:
; ****************************************************************
;
; This is an example of startup code to put either an 80376,
; 80386SX or 80386 into flat mode. All of memory is treated as
; simple linear RAM. There are no interrupt routines. The
; Builder creates the GDT-alias and IDT-alias and places them,
; by default, in GDT[1] and GDT[2]. Other entries in the GDT
; are specified in the Build file. After initialization it jumps
; to a C startup routine. To use this template, change this jmp
; address to that of your code, or make the label of your code
; ‘c startup‘.
;
; This code was assembled and built using version 1.2 of the
; Intel RLL utilities and Intel 386ASM assembler.
;
;
;
***
This code was tested
***
; ****************************************************************
19
376 EMBEDDED PROCESSOR
NAME FLAT
EXTRN
; name of the object module
c startup:near ; this is the label jmped to after init
pe flag
data selc
equ 1
equ 20h
; assume code is GDT[3], data GDT[4]
; Segment base at 0ffffff80h
INIT CODE
SEGMENT ER PUBLIC USE32
PUBLIC GDT DESC
gdt desc
PUBLIC
dq
?
START
start:
cld
; clear direction flag
; check for processor (80376) at reset
; use SMSW rather than MOV for speed
smsw bx
test bl,1
jnz pestart
realstart
db 66h
; is an 80386 and in real mode
; force the next operand into 32-bit mode.
mov eax,offset gdt desc ; move address of the GDT descriptor into eax
xor ebx,ebx
mov bh,ah
move bl,al
db 67h
; clear ebx
; load 8 bits of address into bh
; load 8 bits of address into bl
db 66h
lgdt cs:[ebx]
smsw ax
; use the 32-bit form of LGDT to load
; the 32-bits of address into the GDTR
; go into protected mode (set PE bit)
or al,pe flag
lmsw ax
jmp next
; flush prefetch queue
pestart:
mov ebx,offset gdt desc
xor eax,eax
mov ax,bx
; lower portion of address only
lgdt cs:[eax]
xor ebx,ebx
mov b1,data selc
mov ds,bx
; initialize data selectors
; GDT[3]
mov ss,bx
mov es,bx
mov fs,bx
mov gs,bx
jmp pejump
next:
xor ebx,ebx
mov b1,data selc
mov ds,bx
mov ss,bx
mov es,bx
mov fs,bx
mov gs,bx
db 66h
; initialize data selectors
; GDT[3]
; for the 80386, need to make a 32-bit jump
; but the 80376 is already 32-bit.
pejump:
jmp far ptr c startup
org 70h
jmp short start
; only if segment base is at 0ffffff80h
INIT CODE ENDS
END
20
376 EMBEDDED PROCESSOR
This code should be linked into your application for boot loadable code. The following build file illustrates how
this is accomplished.
FLAT; Ð build program id
SEGMENT
*segments (dpl40),
phantom code (dpl40),
phantom data (dpl40),
Ð Give all user segments a DPL of 0.
Ð These two segments are created by
Ð the builder when the FLAT control is used.
init code (base40ffffff80h); Ð Put startup code at the reset vector area.
GATE
g13 (entry413, dpl40, trap),
Ð trap gate disables interrupts
i32 (entry432, dpl40, interrupt), Ð interrupt gates doesn’t
TABLE
Ð create GDT
GDT (LOCATION 4 GDT DESC,
Ð In a buffer starting at GDT DESC,
Ð BLD386 places the GDT base and
Ð GDT limit values. Buffer must be
Ð 6 bytes long. The base and limit
Ð values are places in this buffer
Ð as two bytes of limit plus
Ð four bytes of base in the format
Ð required for use by the LGDT
Ð instruction.
ENTRY 4 (3: phantom code ,
4: phantom data ,
5:code32,
Ð Explicitly place segment
Ð entries into the GDT.
6:data,
7:init code)
);
TASK
MAIN TASK
(
DPL 4 0,
DATA 4 DATA,
Ð Task privilege level is 0.
Ð Points to a segment that
Ð indicates initial DS value.
Ð Entry point is main, which
Ð must be a public id.
CODE 4 main,
STACKS 4 (DATA),
Ð Segment id points to stack
Ð segment. Sets the initial SS:ESP.
Ð Disable interrupts.
NO INTENABLED,
PRESENT
);
Ð Present bit in TSS set to 1.
MEMORY
(RANGE 4 (EPROM 4 ROM(0ffff8000h..0ffffffffh),
DRAM 4 RAM(0..0ffffh)),
ALLOCATE 4 (EPROM 4 (MAIN TASK)));
END
asm386 flatsim.a38 debug
asm386 application.a38 debug
bnd386 application.obj,flatsim.obj nolo debug oj (application.bnd)
bld386 application.bnd bf (flatsim.bld) bl flat
Commands to assemble and build a boot-loadable application named ‘‘application.a38’’. The initialization code
is called ‘‘flatsim.a38’’, and build file is called ‘‘application.bld’’.
21
376 EMBEDDED PROCESSOR
2.10 Self-Test
2.11 Debugging Support
The 80376 has the capability to perform a self-test.
The self-test checks the function of all of the Control
ROM and most of the non-random logic of the part.
Approximately one-half of the 80376 can be tested
during self-test.
The 80376 provides several features which simplify
the debugging process. The three categories of on-
chip debugging aids are:
1. The code execution breakpoint opcode (0CCH).
2. The single-step capability provided by the TF bit
in the flag register, and
Self-Test is initiated on the 80376 when the RESET
pin transitions from HIGH to LOW, and the BUSY pin
20
is LOW. The self-test takes about 2 clocks, or ap-
3. The code and data breakpoint capability provided
by the Debug Registers DR0–3, DR6, and DR7.
proximately 33 ms with a 16 MHz 80376 processor.
At the completion of self-test the processor per-
forms reset and begins normal operation. The part
has successfully passed self-test if the contents of
the EAX register is zero. If the EAX register is not
zero then the self-test has detected a flaw in the
part. If self-test is not selected after reset, EAX may
be non-zero after reset.
BREAKPOINT INSTRUCTION
A single-byte software interrupt (Int 3) breakpoint in-
struction is available for use by software debuggers.
The breakpoint opcode is 0CCh, and generates an
exception 3 trap when executed.
DEBUG REGISTERS
240182–9
240182–10
240182–5
Figure 2.6. Debug Registers
22
376 EMBEDDED PROCESSOR
SINGLE-STEP TRAP
3.0 ARCHITECTURE
If the single-step flag (TF, bit 8) in the EFLAG regis-
ter is found to be set at the end of an instruction, a
single-step exception occurs. The single-step ex-
ception is auto vectored to exception number 1.
The Intel 80376 Embedded Processor has a physi-
24
cal address space of 16 Mbytes (2 bytes) and al-
lows the running of virtual memory programs of al-
c
most unlimited size (16 Kbytes
16 Mbytes or
38
256 Gbytes (2 bytes)). In addition the 80376 pro-
vides a sophisticated memory management and a
hardware-assisted protection mechanism.
The Debug Registers are an advanced debugging
feature of the 80376. They allow data access break-
points as well as code execution breakpoints. Since
the breakpoints are indicated by on-chip registers,
an instruction execution breakpoint can be placed in
ROM code or in code shared by several tasks, nei-
ther of which can be supported by the INT 3 break-
point opcode.
3.1 Addressing Mechanism
The 80376 uses two components to form the logical
address, a 16-bit selector which determines the lin-
ear base address of a segment, and a 32-bit effec-
tive address. The selector is used to specify an
index into an operating system defined table (see
Figure 3.1). The table contains the 32-bit base ad-
dress of a given segment. The linear address is
formed by adding the base address obtained from
the table to the 32-bit effective address. This value
is truncated to 24 bits to form the physical address,
which is then placed on the address bus.
The 80376 contains six Debug Registers, consisting
of four breakpoint address registers and two break-
point control registers. Initially after reset, break-
points are in the disabled state; therefore, no break-
points will occur unless the debug registers are
programmed. Breakpoints set up in the Debug
Registers are auto-vectored to exception 1.
Figure 2.6 shows the breakpoint status and control
registers.
240182–11
Figure 3.1. Address Calculation
23
376 EMBEDDED PROCESSOR
3.2 Segmentation
Each of the tables have a register associated with it:
GDTR, LDTR and IDTR; see Figure 3.2. The LGDT,
LLDT and LIDT instructions load the base and limit
of the Global, Local and Interrupt Descriptor Tables
into the appropriate register. The SGDT, SLDT and
SIDT store these base and limit values. These are
privileged instructions.
Segmentation is one method of memory manage-
ment and provides the basis for protection in the
80376. Segments are used to encapsulate regions
of memory which have common attributes. For ex-
ample, all of the code of a given program could be
contained in a segment, or an operating system ta-
ble may reside in a segment. All information about
each segment, is stored in an 8-byte data structure
called a descriptor. All of the descriptors in a system
are contained in tables recognized by hardware.
TERMINOLOGY
The following terms are used throughout the discus-
sion of descriptors, privilege levels and protection:
PL:
Privilege LevelÐOne of the four hierarchical
privilege levels. Level 0 is the most privileged
level and level 3 is the least privileged.
RPL: Requestor Privilege LevelÐThe privilege
level of the original supplier of the selector.
RPL is determined by the least two significant
bits of a selector.
DPL: Descriptor Privilege LevelÐThis is the least
privileged level at which a task may access
that descriptor (and the segment associated
with that descriptor). Descriptor Privilege Lev-
el is determined by bits 6:5 in the Access
Right Byte of a descriptor.
240182–12
Figure 3.2. Descriptor Table Registers
Global Descriptor Table
CPL: Current Privilege LevelÐThe privilege level
at which a task is currently executing, which
equals the privilege level of the code seg-
ment being executed. CPL can also be deter-
mined by examining the lowest 2 bits of the
CS register, except for conforming code seg-
ments.
The Global Descriptor Table (GDT) contains de-
scriptors which are possibly available to all of the
tasks in a system. The GDT can contain any type of
segment descriptor except for interrupt and trap de-
scriptors. Every 80376 system contains a GDT. A
simple 80376 system contains only 2 entries in the
GDT; a code and a data descriptor. For maximum
performance, descriptor tables should begin on
even addresses.
EPL: Effective Privilege LevelÐThe effective
privilege level is the least privileged of the
RPL and the DPL. EPL is the numerical maxi-
mum of RPL and DPL.
The first slot of the Global Descriptor Table corre-
sponds to the null selector and is not used. The null
selector defines a null pointer value.
Task: One instance of the execution of a program.
Tasks are also referred to as processes.
DESCRIPTOR TABLES
Local Descriptor Table
The descriptor tables define all of the segments
which are used in an 80376 system. There are three
types of tables on the 80376 which hold descriptors:
the Global Descriptor Table, Local Descriptor Table,
and the Interrupt Decriptor Table. All of the tables
are variable length memory arrays, they can range in
size between 8 bytes and 64 Kbytes. Each table can
hold up to 8192 8-byte descriptors. The upper 13
bits of a selector are used as an index into the de-
scriptor table. The tables have registers associated
with them which hold the 32-bit linear base address,
and the 16-bit limit of each table.
LDTs contain descriptors which are associated with
a given task. Generally, operating systems are de-
signed so that each task has a separate LDT. The
LDT may contain only code, data, stack, task gate,
and call gate descriptors. LDTs provide a mecha-
nism for isolating a given task’s code and data seg-
ments from the rest of the operating system, while
the GDT contains descriptors for segments which
are common to all tasks. A segment cannot be ac-
cessed by a task if its segment descriptor does not
exist in either the current LDT or the GDT. This pro-
24
376 EMBEDDED PROCESSOR
vides both isolation and protection for a task’s seg-
ments, while still allowing global data to be shared
among tasks.
ment, the 20-bit length and granularity of the seg-
ment, the protection level, read, write or execute
privileges, and the type of segment. All of the attri-
bute information about a segment is contained in 12
bits in the segment descriptor. Figure 3.3 shows the
general format of a descriptor. All segments on the
the 80376 have three attribute fields in common: the
Present bit (P), the Descriptor Privilege Level bits
Unlike the 6-byte GDT or IDT registers which contain
a base address and limit, the visible portion of the
LDT register contains only a 16-bit selector. This se-
lector refers to a Local Descriptor Table descriptor in
the GDT (see Figure 2.1).
e
(DPL) and the Segment bit (S). P 1 if the segment
is loaded in physical memory, if P
e
0 then any
attempt to access the segment causes a not present
exception (exception 11). The DPL is a two-bit field
which specifies the protection level, 0–3, associated
with a segment.
INTERRUPT DESCRIPTOR TABLE
The third table needed for 80376 systems is the In-
terrupt Descriptor Table. The IDT contains the de-
scriptors which point to the location of up to 256
interrupt service routines. The IDT may contain only
task gates, interrupt gates and trap gates. The IDT
should be at least 256 bytes in size in order to hold
the descriptors for the 32 Intel Reserved Interrupts.
Every interrupt used by a system must have an entry
in the IDT. The IDT entries are referenced by INT
instructions, external interrupt vectors, and excep-
tions.
The 80376 has two main categories of segments:
system segments, and non-system segments (for
code and data). The segment bit, S, determines if a
given segment is a system segment, a code seg-
ment or a data segment. If the S bit is 1 then the
segment is either a code or data segment, if it is 0
then the segment is a system segment.
Note that although the 80376 is limited to
a
24
16-Mbyte Physical address space (2 ), its base ad-
dress allows a segment to be placed anywhere in a
4-Gbyte linear address space. When writing code for
the 80376, users should keep code portability to an
80386 processor (or other processors with a larger
physical address space) in mind. A segment base
address can be placed anywhere in this 4-Gbyte lin-
ear address space, but a physical address will be
DESCRIPTORS
The object to which the segment selector points to
is called a descriptor. Descriptors are eight-byte
quantities which contain attributes about a given
region of linear address space. These attributes in-
clude the 32-bit logical base address of the seg-
31
0
BYTE
ADDRESS
SEGMENT BASE 15 . . . 0
A
SEGMENT LIMIT 15 . . . 0
0
a
BASE
31 . . . 24
LIMIT
19 . . . 16
BASE
23 . . . 16
4
G 1 0 V
L
P
DPL
S
TYPE
A
BASE Base Address of the segment
LIMIT The length of the segment
e
Descriptor Privilege Level 0–3
e
Not Present
P
DPL
S
Present Bit
1
Present
0
e
e
Code or Data Descriptor
Segment Descriptor:
0
System Descriptor,
1
TYPE Type of Segment
Accessed Bit
Granularity Bit
A
G
e
e
1
0
Segment length is 4 Kbyte Granular
Segment length is byte granular
0
AVL
Bit must be zero (0) for compatibility with future processors
Available field for user or OS
Figure 3.3. Segment Descriptors
31
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
ACCESS
0
A
BASE
31 . . . 24
LIMIT
19 . . . 16
BASE
23 . . . 16
a
4
G
1
0
V
L
RIGHTS
BYTE
Granularity Bit
e
e
G
0
1
0
Segment length is 4 Kbyte granular
Segment length is byte granular
Bit must be zero (0) for compatibility with future processors
AVL Available field for user or OS
Figure 3.4. Code and Data Descriptors
25
376 EMBEDDED PROCESSOR
Table 3.1. Access Rights Byte Definition for Code and Data Descriptors
Bit
Name
Function
Position
e
e
7
Present (P)
P
P
1
0
Segment is mapped into physical memory.
No mapping to physical memory exits
Segment privilege attribute used in privilege tests.
6–5
4
Descriptor Privilege
Level (DPL)
Segment
e
e
S
S
1
0
Code or Data (includes stacks) segment descriptor
System Segment Descriptor or Gate Descriptor
Descriptor (S)
e
3
2
Executable (E)
Expansion
E
0
Descriptor type is data segment:
0 Expand up segment, offsets must be limit.
l
1 Expand down segment, offsets must be limit.
If
s
e
e
ED
ED
Data
Segment
Direction (ED)
Writable (W)
e
e
e
1,
1
W
W
0
Data segment may not be written into.
Data segment may be written into.
(S
E
e
1
*
*
0)
e
e
3
2
Executable (E)
Conforming (C)
E
C
1
Descriptor type is code segment:
Code segment may only be executed when
t
CPL DPL and CPL remains unchanged.
If
1
Code
Segment
e
e
e
1,
1
0
Readable (R)
Accessed (A)
R
R
0
1
Code segment may not be read.
Code segment may be read.
(S
E
e
1)
e
e
A
A
0
1
Segment has not been accessed.
Segment selector has been loaded into segment register
or used by selector test instructions.
generated that is a truncated version of this linear
address. Truncation will be to the maximum number
of address bits. It is recommended to place EPROM
at the highest physical address and DRAM at the
lowest physical addresses.
80376 system descriptors (which are the same as
80386 descriptor types 2, 5, 9, B, C, E and F) contain
a 32-bit logical base address and a 20-bit segment
limit.
Selector Fields
e
Code and Data Descriptors (S 1)
A selector has three fields: Local or Global Descrip-
tor Table Indicator (TI), Descriptor Entry Index (In-
dex), and Requestor ( the selector’s) Privilege Level
(RPL) as shown in Figure 3.6. The TI bit selects ei-
ther the Global Descriptor Table or the Local De-
scriptor Table. The Index selects one of 8K descrip-
tors in the appropriate descriptor table. The RPL bits
allow high speed testing of the selector’s privilege
attributes.
Figure 3.4 shows the general format of a code and
data descriptor and Table 3.1 illustrates how the bits
in the Access Right Byte are interpreted.
Code and data segments have several descriptor
fields in common. The accessed bit, A, is set when-
ever the processor accesses a descriptor. The gran-
ularity bit, G, specifies if a segment length is 1-byte-
granular or 4-Kbyte-granular. Base address bits
31–24, which are normally found in 80386 descrip-
tors, are not made externally available on the 80376.
They do not affect the operation of the 80376. The
Segment Descriptor Cache
In addition to the selector value, every segment reg-
ister has a segment descriptor cache register asso-
ciated with it. Whenever a segment register’s con-
tents are changed, the 8-byte descriptor associated
with that selector is automatically loaded (cached)
on the chip. Once loaded, all references to that seg-
ment use the cached descriptor information instead
of reaccessing the descriptor. The contents of the
descriptor cache are not visible to the programmer.
Since descriptor caches only change when a seg-
ment register is changed, programs which modify
the descriptor tables must reload the appropriate
A
31
–A field should be set to allow an 80386 to
24
correctly execute with EPROM at the upper 4096
Mbytes of physical memory.
e
System Descriptor Formats (S
0)
System segments describe information about oper-
ating system tables, tasks, and gates. Figure 3.5
shows the general format of system segment de-
scriptors, and the various types of system segments.
segment registers after changing
value.
a descriptor’s
26
376 EMBEDDED PROCESSOR
31
16
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
BASE
31 . . . 24
LIMIT
19 . . . 16
BASE
23 . . . 16
a
4
G
0
0
0
P
DPL
0
TYPE
Type
Defines
Invalid
Reserved
LDT
Reserved
Reserved
Task Gate (80376/80386 Task)
Reserved
Reserved
Type
8
9
A
B
C
D
E
F
Defines
Invalid
Available 80376/80386 TSS
Undefined (Intel Reserved)
Busy 80376/80386 TSS
80376/80386 Call Gate
Undefined (Intel Reserved)
80376/80386 Interrupt Gate
80376/80386 Trap Gate
0
1
2
3
4
5
6
7
Figure 3.5. System Descriptors
240182–13
Figure 3.6. Example Descriptor Selection
ÐData stored in a segment with privilege level p
can be accessed only by code executing at a
privilege level at least as privileged as p.
3.3 Protection
The 80376 offers extensive protection features.
These protection features are particularly useful in
sophisticated embedded applications which use
multitasking real-time operating systems. For sim-
pler embedded applications these protection capa-
bilities can be easily bypassed by making all applica-
tions run at privilege level (PL) 0.
ÐA code segment/procedure with privilege level p
can only be called by a task executing at the
same or a lesser privilege level than p.
PRIVILEGE LEVELS
At any point in time, a task on the 80376 always
executes at one of the four privilege levels. The Cur-
rent Privilege Level (CPL) specifies what the task’s
privilege level is. A task’s CPL may only be changed
RULES OF PRIVILEGE
The 80376 controls access to both data and proce-
dures between levels of a task, according to the fol-
lowing rules.
27
376 EMBEDDED PROCESSOR
by control transfers through gate descriptors to a
code segment with a different privilege level. Thus,
Any time an instruction loads a data segment regis-
ter (DS, ES, FS, GS) the 80376 makes protection
validation checks. Selectors loaded in the DS, ES,
FS, GS registers must refer only to data segment or
readable code segments.
e
an application program running at PL 3 may call an
operating system routine at PL 1 (via a gate) which
e
would cause the task’s CPL to be set to 1 until the
operating system routine was finished.
Finally the privilege validation checks are performed.
The CPL is compared to the EPL and if the EPL is
more privileged than the CPL, an exception 13 (gen-
eral protection fault) is generated.
Selector Privilege (RPL)
The privilege level of a selector is specified by the
RPL field. The selector’s RPL is only used to estab-
lish a less trusted privilege level than the current
privilege level of the task for the use of a segment.
This level is called the task’s effective privilege level
(EPL). The EPL is defined as being the least privi-
leged (numerically larger) level of a task’s CPL and a
selector’s RPL. The RPL is most commonly used to
verify that pointers passed to an operating system
procedure do not access data that is of higher privi-
lege than the procedure that originated the pointer.
Since the originator of a selector can specify any
RPL value, the Adjust RPL (ARPL) instruction is pro-
vided to force the RPL bits to the originator’s CPL.
The rules regarding the stack segment are slightly
different than those involving data segments. In-
structions that load selectors into SS must refer to
data segment descriptors for writeable data seg-
ments. The DPL and RPL must equal the CPL of all
other descriptor types or a privilege level violation
will cause an exception 13. A stack not present fault
causes an exception 12.
PRIVILEGE LEVEL TRANSFERS
Inter-segment control transfers occur when a selec-
tor is loaded in the CS register. For a typical system
most of these transfers are simply the result of a call
or a jump to another routine. There are five types of
control transfers which are summarized in Table 3.2.
Many of these transfers result in a privilege level
transfer. Changing privilege levels is done only by
control transfers, using gates, task switches, and in-
terrupt or trap gates.
I/O Privilege
The I/O privilege level (IOPL) lets the operating sys-
e
tem code executing at CPL 0 define the least privi-
leged level at which I/O instructions can be used. An
exception 13 (General Protection Violation) is gener-
ated if an I/O instruction is attempted when the CPL
of the task is less privileged than the IOPL. The
IOPL is stored in bits 13 and 14 of the EFLAGS reg-
ister. The following instructions cause an exception
13 if the CPL is greater than IOPL: IN, INS, OUT,
OUTS, STI, CLI and LOCK prefix.
Control transfers can only occur if the operation
which loaded the selector references the correct de-
scriptor type. Any violation of these descriptor usage
rules will cause an exception 13.
CALL GATES
Descriptor Access
Gates provide protected indirect CALLs. One of the
major uses of gates is to provide a secure method of
privilege transfers within a task. Since the operating
system defines all of the gates in a system, it can
ensure that all gates only allow entry into a few trust-
ed procedures.
There are basically two types of segment acces-
sess: those involving code segments such as con-
trol transfers, and those involving data accesses.
Determining the ability of a task to access a seg-
ment involves the type of segment to be accessed,
the instruction used, the type of descriptor used and
CPL, RPL, and DPL as described above.
28
376 EMBEDDED PROCESSOR
Table 3.2. Descriptor Types Used for Control Transfer
Descriptor
Referenced
Descriptor
Table
Control Transfer Types
Operation Types
Intersegment within the same privilege level
JMP, CALL, RET, IRET* Code Segment GDT/LDT
Intersegment to the same or higher privilege level CALL
Interrupt within task may change CPL
Call Gate
GDT/LDT
IDT
Interrupt Instruction,
Exception, External
Interrupt
Trap or
Interrupt
Gate
Intersegment to a lower privilege level
(changes task CPL)
RET, IRET*
CALL, JMP
CALL, JMP
Code Segment GDT/LDT
Task State
Segment
GDT
Task Switch
Task Gate
Task Gate
GDT/LDT
IDT
IRET**
Interrupt Instruction,
Exception, External
Interrupt
e
e
*NT (Nested Task bit of flag register)
**NT (Nested Task bit of flag register)
0
1
29
376 EMBEDDED PROCESSOR
NOTE:
BIT M
Ð
must b
e
e
Type
Type
240182–14
Figure 3.7. 80376 TSS And TSS Registers
30
376 EMBEDDED PROCESSOR
interrupted. The current executing task’s state is
saved in the TSS and the old task state is restored
from its TSS.
TASK SWITCHING
A very important attribute of any multi-tasking oper-
ating system is its ability to rapidly switch between
tasks or processes. The 80376 directly supports this
operation by providing a task switch instruction in
hardware. The 80376 task switch operation saves
the entire state of the machine (all of the registers,
address space, and a link to the previous task),
loads a new execution state, performs protection
checks, and commences execution in the new task.
Like transfer of control by gates, the task switch op-
eration is invoked by executing an inter-segment
JMP or CALL instruction which refers to a Task
State Segment (TSS), or a task gate descriptor in
the GDT or LDT. An INT n instruction, exception,
trap or external interrupt may also invoke the task
switch operation if there is a task gate descriptor in
the associated IDT descriptor slot. For simple appli-
cations, the TSS and task switching may not be
used. The TSS or task switch will not be used or
occur if no task gates are present in the GDT, LDT
or IDT.
Several bits in the flag register and CR0 register give
information about the state of a task which is useful
to the operating system. The Nested Task bit, NT,
e
controls the function of the IRET instruction. If NT
0 the IRET instruction performs the regular return. If
e
back to the previous task. The NT bit is set or reset
NT
1, IRET performs a task switch operation
in the following fashion:
When a CALL or INT instruction initiates a task
switch, the new TSS will be marked busy and
the back link field of the new TSS set to the old
TSS selector. The NT bit of the new task is set
by CALL or INT initiated task switches. An inter-
rupt that does not cause a task switch will clear
NT (The NT bit will be restored after execution
of the interrupt handler). NT may also be set or
cleared by POPF or IRET instructions.
The 80376 task state segment is marked busy by
changing the descriptor type field from TYPE 9 to
TYPE 0BH. Use of a selector that references a busy
task state segment causes an exception 13.
The TSS descriptor points to a segment (see Figure
3.7) containing the entire 80376 execution state. A
task gate descriptor contains a TSS selector. The
limit of an 80376 TSS must be greater than 64H, and
can be as large as 16 Mbytes. In the additional TSS
space, the operating system is free to store addition-
al information as the reason the task is inactive, the
time the task has spent running, and open files be-
longing to the task. For maximum performance, TSS
should start on an even address.
The coprocessor’s state is not automatically saved
when a task switch occurs. The Task Switched Bit,
TS, in the CR0 register helps deal with the coproces-
sor’s state in a multi-tasking environment. Whenever
the 80376 switches tasks, it sets the TS bit. The
80376 detects the first use of a processor extension
instruction after a task switch and causes the proc-
essor extension not available exception 7. The ex-
ception handler for exception 7 may then decide
whether to save the state of the coprocessor.
Each Task must have a TSS associated with it. The
current TSS is identified by a special register in the
80376 called the Task State Segment Register (TR).
This register contains a selector referring to the task
state segment descriptor that defines the current
TSS. A hidden base and limit register associated
with the TSS descriptor is loaded whenever TR is
loaded with a new selector. Returning from a task is
accomplished by the IRET instruction. When IRET is
executed, control is returned to the task which was
The T bit in the 80376 TSS indicates that the proc-
essor should generate a debug exception when
e
new task a debug exception 1 will be generated.
switching to a task. If T
1 then upon entry to a
240182–15
I/O Ports Accessible 2
x
9, 12, 13, 15, 20
x
24, 27, 33, 34, 40, 41, 48, 50, 52, 53, 58
x
60, 62, 63, 96
x
127
Figure 3.8. Sample I/O Permission Bit Map
31
376 EMBEDDED PROCESSOR
It is not necessary for the I/O permission map to
represent all the I/O addresses. I/O addresses not
spanned by the map are treated as if they had one-
bits in the map. The I/O map base should be at
least one byte less than the TSS limit and the last
byte beyond the I/O mapping information must con-
tain all 1’s.
PROTECTION AND I/O PERMISSION BIT MAP
The I/O instructions that directly refer to addresses
in the processor’s I/O space are IN, INS, OUT and
OUTS. The 80376 has the ability to selectively trap
references to specific I/O addresses. The structure
that enables selective trapping is the I/O Permis-
sion Bit Map in the TSS segment (see Figures 3.7
and 3.8). The I/O permission map is a bit vector.
The size of the map and its location in the TSS seg-
ment are variable. The processor locates the I/O
permission map by means of the I/O map base field
in the fixed portion of the TSS. The I/O map base
field is 16 bits wide and contains the offset of the
beginning of the I/O permission map.
Because the I/O permission map is in the TSS seg-
ment, different tasks can have different maps. Thus,
the operating system can allocate ports to a task by
changing the I/O permission map in the task’s TSS.
IMPORTANT IMPLEMENTATION NOTE:
Beyond the last byte of I/O mapping information in
the I/O permission bit map must be a byte contain-
ing all 1’s. The byte of all 1’s must be within the
limit of the 80376’s TSS segment (see Figure 3.7).
If an I/O instruction (IN, INS, OUT or OUTS) is en-
countered, the processor first checks whether
s
CPL
IOPL. If this condition is true, the I/O opera-
tion may proceed. If not true, the processor checks
the I/O permission map.
4.0 FUNCTIONAL DATA
The Intel 80376 embedded processor features a
straightforward functional interface to the external
hardware. The 80376 has separate parallel buses
for data and address. The data bus is 16 bits in
width, and bidirectional. The address bus outputs
24-bit address values using 23 address lines and
two-byte enable signals.
Each bit in the map corresponds to an I/O port byte
address; for example, the bit for port 41 is found at
a
c
e
I/O map base 5 linearly, (5
8 40), bit offset
1. The processor tests all the bits that correspond to
the I/O addresses spanned by an I/O operation; for
example, a double word operation tests four bits cor-
responding to four adjacent byte addresses. If any
tested bit is set, the processor signals a general pro-
tection exception. If all the tested bits are zero, the
I/O operations may proceed.
The 80376 has two selectable address bus cycles:
pipelined and non-pipelined. The pipelining option
allows as much time as possible for data access by
240182–16
Figure 4.1. Functional Signal Groups
32
376 EMBEDDED PROCESSOR
starting the pending bus cycle before the present
bus cycle is finished. A non-pipelined bus cycle
gives the highest bus performance by executing ev-
ery bus cycle in two processor clock cycles. For
maximum design flexibility, the address pipelining
option is selectable on a cycle-by-cycle basis.
processor from its system (all other output pins are
in a float condition).
4.1 Signal Description Overview
Ahead is a brief description of the 80376 input and
output signals arranged by functional groups.
The processor’s bus cycle is the basic mechanism
for information transfer, either from system to proc-
essor, or from processor to system. 80376 bus cy-
cles perform data transfer in a minimum of only two
clock periods. On a 16-bit data bus, the maximum
80376 transfer bandwidth at 16 MHz is therefore
16 Mbytes/sec. However, any bus cycle will be ex-
tended for more than two clock periods if external
hardware withholds acknowledgement of the cycle.
The signal descriptions sometimes refer to A.C. tim-
ing parameters, such as ‘‘t Reset Setup Time’’ and
25
‘‘t Reset Hold Time.’’ The values of these parame-
26
ters can be found in Tables 6.4 and 6.5.
CLOCK (CLK2)
CLK2 provides the fundamental timing for the
80376. It is divided by two internally to generate the
internal processor clock used for instruction execu-
tion. The internal clock is comprised of two
The 80376 can relinquish control of its local buses
to allow mastership by other devices, such as direct
memory access (DMA) channels. When relin-
quished, HLDA is the only output pin driven by the
80376, providing near-complete isolation of the
240182–17
Figure 4.2. CLK2 Signal and Internal Processor Clock
33
376 EMBEDDED PROCESSOR
phases, ‘‘phase one’’ and ‘‘phase two’’. Each CLK2
period is a phase of the internal clock. Figure 4.2
illustrates the relationship. If desired, the phase of
the internal processor clock can be synchronized to
a known phase by ensuring the falling edge of the
RESET signal meets the applicable setup and hold
During coprocessor I/O transfers, A –A are driv-
22 16
en LOW, and A is driven HIGH so that this ad-
23
dress line can be used by external logic to generate
the coprocessor select signal. Thus, the I/O address
driven by the 80376 for coprocessor commands is
8000F8H, and the I/O address driven by the 80376
processor for coprocessor data is 8000FCH or
8000FEH.
times t and t
25
.
26
DATA BUS (D –D )
15 0
The address bus is capable of addressing 16 Mbytes
of physical memory space (000000H through
0FFFFFFH), and 64 Kbytes of I/O address space
(000000H through 00FFFFH) for programmed I/O.
The address bus is active HIGH and will float during
bus hold acknowledge.
These three-state bidirectional signals provide the
general purpose data path between the 80376 and
other devices. The data bus outputs are active HIGH
and will float during bus hold acknowledge. Data bus
reads require that read-data setup and hold times
t
21
ation.
and t be met relative to CLK2 for correct oper-
22
The Byte Enable outputs BHE and BLE directly indi-
cate which bytes of the 16-bit data bus are involved
with the current transfer. BHE applies to D –D
15
8
and BLE applies to D –D . If both BHE and BLE are
0
ADDRESS BUS (BHE, BLE, A –A )
23 1
7
asserted, then 16 bits of data are being transferred.
See Table 4.1 for a complete decoding of these sig-
nals. The byte enables are active LOW and will float
during bus hold acknowledge.
These three-state outputs provide physical memory
addresses or I/O port addresses. A –A are LOW
during I/O transfers except for I/O transfers auto-
matically generated by coprocessor instructions.
23
16
Table 4.1. Byte Enable Definitions
Function
BHE
BLE
0
0
1
1
0
1
0
1
Word Transfer
Byte Transfer on Upper Byte of the Data Bus, D –D
15
8
Byte Transfer on Lower Byte of the Data Bus, D –D
7
0
Never Occurs
34
376 EMBEDDED PROCESSOR
BUS CYCLE DEFINITION SIGNALS
(W/R, D/C, M/IO, LOCK)
BUS CONTROL SIGNALS
(ADS, READY, NA)
These three-state outputs define the type of bus cy-
cle being performed: W/R distinguishes between
write and read cycles, D/C distinguishes between
data and control cycles, M/IO distinguishes between
memory and I/O cycles, and LOCK distinguishes be-
tween locked and unlocked bus cycles. All of these
signals are active LOW and will float during bus ac-
knowledge.
The following signals allow the processor to indicate
when a bus cycle has begun, and allow other system
hardware to control address pipelining and bus cycle
termination.
Address Status (ADS)
This three-state output indicates that a valid bus cy-
cle definition and address (W/R, D/C, M/IO, BHE,
BLE and A –A ) are being driven at the 80376
The primary bus cycle definition signals are W/R,
D/C and M/IO, since these are the signals driven
valid as ADS (Address Status output) becomes ac-
tive. The LOCK signal is driven valid at the same
time the bus cycle begins, which due to address
pipelining, could be after ADS becomes active. Ex-
act bus cycle definitions, as a function of W/R, D/C
and M/IO are given in Table 4.2.
23
1
pins. ADS is an active LOW output. Once ADS is
driven active, valid address, byte enables, and defi-
nition signals will not change. In addition, ADS will
remain active until its associated bus cycle begins
(when READY is returned for the previous bus cycle
when running pipelined bus cycles). ADS will float
during bus hold acknowledge. See sections Non-
Pipelined Bus Cycles and Pipelined Bus Cycles
for additional information on how ADS is asserted
for different bus states.
LOCK indicates that other system bus masters are
not to gain control of the system bus while it is ac-
tive. LOCK is activated on the CLK2 edge that be-
gins the first locked bus cycle (i.e., it is not active at
the same time as the other bus cycle definition pins)
and is deactivated when ready is returned to the end
of the last bus cycle which is to be locked. The be-
ginning of a bus cycle is determined when READY is
returned in a previous bus cycle and another is
pending (ADS is active) or the clock in which ADS is
driven active if the bus was idle. This means that it
follows more closely with the write data rules when it
is valid, but may cause the bus to be locked longer
than desired. The LOCK signal may be explicitly acti-
vated by the LOCK prefix on certain instructions.
LOCK is always asserted when executing the XCHG
instruction, during descriptor updates, and during the
interrupt acknowledge sequence.
Transfer Acknowledge (READY)
This input indicates the current bus cycle is com-
plete, and the active bytes indicated by BHE and
BLE are accepted or provided. When READY is
sampled active during a read cycle or interrupt ac-
knowledge cycle, the 80376 latches the input data
and terminates the cycle. When READY is sampled
active during a write cycle, the processor terminates
the bus cycle.
Table 4.2. Bus Cycle Definition
M/IO
D/C
0
W/R
Bus Cycle Type
INTERRUPT ACKNOWLEDGE
Does Not Occur
Locked?
Yes
0
0
0
0
1
1
0
1
0
1
0
1
0
Ð
1
I/O DATA READ
No
No
No
No
1
I/O DATA WRITE
0
MEMORY CODE READ
0
HALT:
Address
SHUTDOWN:
e
0
e
2
Address
e
e
e
e
BHE
BLE
1
BHE
BLE
1
0
0
1
1
1
1
0
1
MEMORY DATA READ
MEMORY DATA WRITE
Some Cycles
Some Cycles
35
376 EMBEDDED PROCESSOR
READY is ignored on the first bus state of all bus
cycles, and sampled each bus state thereafter until
asserted. READY must eventually be asserted to ac-
knowledge every bus cycle, including Halt Indication
and Shutdown Indication bus cycles. When being
sampled, READY must always meet setup and hold
HOLD is a level-sensitive, active HIGH, synchronous
input. HOLD signals must always meet setup and
hold times t and t for correct operation.
23
24
Bus Hold Acknowledge (HLDA)
times t and t for correct operation.
19 20
When active (HIGH), this output indicates the 80376
has relinquished control of its local bus in response
to an asserted HOLD signal, and is in the bus Hold
Acknowledge state.
Next Address Request (NA)
This is used to request pipelining. This input indi-
cates the system is prepared to accept new values
of BHE, BLE, A –A , W/R, D/C and M/IO from the
The Bus Hold Acknowledge state offers near-com-
plete signal isolation. In the Hold Acknowledge
state, HLDA is the only signal being driven by the
80376. The other output signals or bidirectional sig-
23
1
80376 even if the end of the current cycle is not
being acknowledged on READY. If this input is ac-
tive when sampled, the next bus cycle’s address and
status signals are driven onto the bus, provided the
next bus request is already pending internally. NA is
ignored in clock cycles in which ADS or READY is
activated. This signal is active LOW and must satisfy
nals (D –D , BHE, BLE, A –A , W/R, D/C, M/IO,
23
15
0
1
LOCK and ADS) are in a high-impedance state so
the requesting bus master may control them. These
pins remain OFF throughout the time that HLDA re-
mains active (see Table 4.3). Pull-up resistors may
be desired on several signals to avoid spurious ac-
tivity when no bus master is driving them. See Re-
sistor Recommendations for additional informa-
tion.
setup and hold times t and t for correct opera-
16
15
tion. See Pipelined Bus Cycles and Read and
Write Cycles for additional information.
BUS ARBITRATION SIGNALS (HOLD, HLDA)
When the HOLD signal is made inactive, the 80376
will deactivate HLDA and drive the bus. One rising
edge on the NMI input is remembered for processing
after the HOLD input is negated.
This section describes the mechanism by which the
processor relinquishes control of its local buses
when requested by another bus master device. See
Entering and Exiting Hold Acknowledge for addi-
tional information.
Table 4.3. Output Pin State during HOLD
Pin Value
Pin Names
Bus Hold Request (HOLD)
1
Float
HLDA
LOCK, M/IO, D/C, W/R,
This input indicates some device other than the
80376 requires bus mastership. When control is
ADS, A –A , BHE, BLE,
1
23
granted, the 80376 floats
A
–A , BHE, BLE,
23 1
–D , LOCK, M/IO, D/C, W/R and ADS, and
D
15
–D
0
D
15
0
then activates HLDA, thus entering the bus hold ac-
knowledge state. The local bus will remain granted
to the requesting master until HOLD becomes inac-
tive. When HOLD becomes inactive, the 80376 will
deactivate HLDA and drive the local bus (at the
same time), thus terminating the hold acknowledge
condition.
Hold Latencies
The maximum possible HOLD latency depends on
the software being executed. The actual HOLD la-
tency at any time depends on the current bus activi-
ty, the state of the LOCK signal (internal to the CPU)
activated by the LOCK prefix, and interrupts. The
80376 will not honor a HOLD request until the cur-
rent bus operation is complete.
HOLD must remain asserted as long as any other
device is a local bus master. External pull-up resis-
tors may be required when in the hold acknowledge
state since none of the 80376 floated outputs have
internal pull-up resistors. See Resistor Recommen-
dations for additional information. HOLD is not rec-
ognized while RESET is active but is recognized dur-
ing the time between the high-to-low transistion of
RESET and the first instruction fetch. If RESET is
asserted while HOLD is asserted, RESET has priori-
ty and places the bus into an idle state, rather than
the hold acknowledge (high-impedance) state.
The 80376 breaks 32-bit data or I/O accesses into 2
internally locked 16-bit bus cycles; the LOCK signal
is not asserted. The 80376 breaks unaligned 16-bit
or 32-bit data or I/O accesses into 2 or 3 internally
locked 16-bit bus cycles. Again the LOCK signal is
not asserted but a HOLD request will not be recog-
nized until the end of the entire transfer.
36
376 EMBEDDED PROCESSOR
Wait states affect HOLD latency. The 80376 will not
honor a HOLD request until the end of the current
bus operation, no matter how many wait states are
required. Systems with DMA where data transfer is
critical must insure that READY returns sufficiently
soon.
The F(N)INIT, F(N)CLEX coprocessor instructions
are allowed to execute even if BUSY is active, since
these instructions are used for coprocessor initializa-
tion and exception-clearing.
BUSY is an active LOW, level-sensitive asynchro-
nous signal. Setup and hold times, t and t , rela-
29
30
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This pin is pro-
vided with a weak internal pull-up resistor of around
20 KX to V so that it will not float active when left
CC
unconnected.
COPROCESSOR INTERFACE SIGNALS
(PEREQ, BUSY, ERROR)
In the following sections are descriptions of signals
dedicated to the numeric coprocessor interface. In
addition to the data bus, address bus, and bus cycle
definition signals, these following signals control
communication between the 80376 and the
80387SX processor extension.
BUSY serves an additional function. If BUSY is sam-
pled LOW at the falling edge of RESET, the 80376
processor performs an internal self-test (see Bus
Activity During and Following Reset. If BUSY is
sampled HIGH, no self-test is performed.
Coprocessor Request (PEREQ)
Coprocessor Error (ERROR)
When asserted (HIGH), this input signal indicates a
coprocessor request for a data operand to be trans-
ferred to/from memory by the 80376. In response,
the 80376 transfers information between the co-
processor and memory. Because the 80376 has in-
ternally stored the coprocessor opcode being exe-
cuted, it performs the requested data transfer with
the correct direction and memory address.
When asserted (LOW), this input signal indicates
that the previous coprocessor instruction generated
a coprocessor error of a type not masked by the
coprocessor’s control register. This input is automat-
ically sampled by the 80376 when a coprocessor
instruction is encountered, and if active, the 80376
generates exception 16 to access the error-handling
software.
PEREQ is a level-sensitive active HIGH asynchro-
nous signal. Setup and hold times, t and t , rela-
Several coprocessor instructions, generally those
which clear the numeric error flags in the coproces-
sor or save coprocessor state, do execute without
the 80376 generating exception 16 even if
ERROR is active. These instructions are FNINIT,
FNCLEX, FNSTSW, FNSTSWAX, FNSTCW,
FNSTENV and FNSAVE.
29
30
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This signal is
provided with a weak internal pull-down resistor of
around 20 KX to ground so that it will not float active
when left unconnected.
Coprocessor Busy (BUSY)
ERROR is an active LOW, level-sensitive asynchro-
nous signal. Setup and hold times t and t , rela-
29
30
When asserted (LOW), this input indicates the co-
processor is still executing an instruction, and is not
yet able to accept another. When the 80376 en-
counters any coprocessor instruction which oper-
ates on the numerics stack (e.g. load, pop, or arith-
metic operation), or the WAIT instruction, this input
is first automatically sampled until it is seen to be
inactive. This sampling of the BUSY input prevents
overrunning the execution of a previous coprocessor
instruction.
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This pin is pro-
vided with a weak internal pull-up resistor of around
20 KX to V so that it will not float active when left
CC
unconnected.
37
376 EMBEDDED PROCESSOR
INTERRUPT SIGNALS (INTR, NMI, RESET)
Interrupt Latency
The time that elapses before an interrupt request is
serviced (interrupt latency) varies according to sev-
eral factors. This delay must be taken into account
by the interrupt source. Any of the following factors
can affect interrupt latency:
The following descriptions cover inputs that can in-
terrupt or suspend execution of the processor’s cur-
rent instruction stream.
Maskable Interrupt Request (INTR)
1. If interrupts are masked, and INTR request will
not be recognized until interrupts are reenabled.
When asserted, this input indicates a request for in-
terrupt service, which can be masked by the 80376
Flag Register IF bit. When the 80376 responds to
the INTR input, it performs two interrupt acknowl-
edge bus cycles and, at the end of the second,
2. If an NMI is currently being serviced, an incoming
NMI request will not be recognized until the 80376
encounters the IRET instruction.
3. An interrupt request is recognized only on an in-
struction boundary of the 80376 Execution Unit
except for the following cases:
latches an 8-bit interrupt vector on D –D to identify
0
7
the source of the interrupt.
Ð Repeat string instructions can be interrupted
after each iteration.
INTR is an active HIGH, level-sensitive asynchro-
nous signal. Setup and hold times, t and t , rela-
27
28
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. To assure rec-
ognition of an INTR request, INTR should remain
active until the first interrupt acknowledge bus cycle
begins. INTR is sampled at the beginning of every
instruction. In order to be recognized at a particular
instruction boundary, INTR must be active at least
eight CLK2 clock periods before the beginning of the
execution of the instruction. If recognized, the 80376
will begin execution of the interrupt.
Ð If the instruction loads the Stack Segment reg-
ister, an interrupt is not processed until after
the following instruction, which should be an
ESP load. This allows the entire stack pointer
to be loaded without interruption.
Ð If an instruction sets the interrupt flag (enabling
interrupts), an interrupt is not processed until
after the next instruction.
The longest latency occurs when the interrupt re-
quest arrives while the 80376 processor is exe-
cuting a long instruction such as multiplication, di-
vision or a task-switch.
Non-Maskable Interrupt Request (NMI)
4. Saving the Flags register and CS:EIP registers.
This input indicates a request for interrupt service
which cannot be masked by software. The non-
maskable interrupt request is always processed ac-
cording to the pointer or gate in slot 2 of the interrupt
table. Because of the fixed NMI slot assignment, no
interrupt acknowledge cycles are performed when
processing NMI.
5. If interrupt service routine requires a task switch,
time must be allowed for the task switch.
6. If the interrupt service routine saves registers that
are not automatically saved by the 80376.
RESET
NMI is an active HIGH, rising edge-sensitive asyn-
,
This input signal suspends any operation in progress
and places the 80376 in a known reset state. The
80376 is reset by asserting RESET for 15 or more
CLK2 periods (80 or more CLK2 periods before re-
questing self-test). When RESET is active, all other
input pins except FLT are ignored, and all other bus
pins are driven to an idle bus state as shown in Ta-
ble 4.4. If RESET and HOLD are both active at a
point in time, RESET takes priority even if the 80376
was in a Hold Acknowledge state prior to RESET
active.
chronous signal. Setup and hold times, t and t
27
28
relative to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. To assure rec-
ognition of NMI, it must be inactive for at least eight
CLK2 periods, and then be active for at least eight
CLK2 periods before the beginning of the execution
of an instruction.
Once NMI processing has begun, no additional
NMI’s are processed until after the next IRET in-
struction, which is typically the end of the NMI serv-
ice routine. If NMI is re-asserted prior to that time,
however, one rising edge on NMI will be remem-
bered for processing after executing the next IRET
instruction.
RESET is an active HIGH, level-sensitive synchro-
nous signal. Setup and hold times, t and t , must
25
26
be met in order to assure proper operation of the
80376.
38
376 EMBEDDED PROCESSOR
Each bus cycle is composed of at least two bus
states. Each bus state requires one processor clock
period. Additional bus states added to a single bus
cycle are called wait states. See Bus Functional
Description for additional information.
Table 4.4. Pin State (Bus Idle) during RESET
Pin Name
Signal Level during RESET
ADS
1
D
–D
Float
15
0
BHE, BLE
–A
0
1
0
1
0
1
0
4.3 Memory and I/O Spaces
A
23
1
Bus cycles may access physical memory space or
I/O space. Peripheral devices in the system may ei-
ther be memory-mapped, or I/O-mapped, or both.
As shown in Figure 4.3, physical memory addresses
range from 000000H to 0FFFFFFH (16 Mbytes) and
I/O addresses from 000000H to 00FFFFH
(64 Kbytes). Note the I/O addresses used by the
automatic I/O cycles for coprocessor communica-
tion are 8000F8H to 8000FFH, beyond the address
range of programmed I/O, to allow easy generation
W/R
D/C
M/IO
LOCK
HLDA
of a coprocessor chip select signal using the A
and M/IO signals.
23
4.2 Bus Transfer Mechanism
All data transfers occur as a result of one or more
bus cycles. Logical data operands of byte and word
lengths may be transferred without restrictions on
physical address alignment. Any byte boundary may
be used, although two physical bus cycles are per-
formed as required for unaligned operand transfers.
OPERAND ALIGNMENT
With the flexibility of memory addressing on the
80376, it is possible to transfer a logical operand
that spans more than one physical Dword or word of
memory or I/O. Examples are 32-bit Dword or 16-bit
word operands beginning at addresses not evenly
divisible by 2.
The 80376 processor address signals are designed
to simplify external system hardware. BHE and BLE
provide linear selects for the two bytes of the 16-bit
data bus.
Operand alignment and size dictate when multiple
bus cycles are required. Table 4.6 describes the
transfer cycles generated for all combinations of log-
ical operand lengths and alignment.
Byte Enable outputs BHE and BLE are asserted
when their associated data bus bytes are involved
with the present bus cycle, as listed in Table 4.5.
Table 4.6. Transfer Bus Cycles
for Bytes, Words and Dwords
Byte-Length of Logical Operand
Table 4.5. Byte Enables and Associated
Data and Operand Bytes
1
2
4
Byte Enable
Associated Data Bus Signals
Physical Byte
Address in
Memory
(Low-Order
Bits)
BHE
BLE
D –D (Byte 1ÐMost Significant)
D –D (Byte 0ÐLeast Significant)
xx 00 01 10 11 00 01 10 11
15
8
7
0
Transfer
Cycles
b
w
lb,
hb
w
hb, lw, hb, hw, mw,
l,b hw lb, lw hb,
mw
lb
e
e
Key:
b
w
byte transfer
word transfer
e
l
low-order portion
e
e
e
m
x
h
mid-order portion
don’t care
high-order portion
39
376 EMBEDDED PROCESSOR
240182–18
NOTE:
Since A is HIGH during automatic communication with coprocessor, A HIGH and M/IO LOW can be used to easily
23
generate a coprocessor select signal.
23
Figure 4.3. Physical Memory and I/O Spaces
5. Read from I/O space (or coprocessor)
4.4 Bus Functional Description
6. Write to I/O space (or coprocessor)
7. Interrupt acknowledge (always locked)
8. Indicate halt, or indicate shutdown
The 80376 has separate, parallel buses for data and
address. The data bus is 16 bits in width, and bidi-
rectional. The address bus provides a 24-bit value
using 23 signals for the 23 upper-order address bits
and 2 Byte Enable signals to directly indicate the
active bytes. These buses are interpreted and con-
trolled by several definition signals.
Table 4.2 shows the encoding of the bus cycle defi-
nition signals for each bus cycle. See Bus Cycle
Definition Signals for additonal information.
When the 80376 bus is not performing one of the
activities listed above, it is either Idle or in the Hold
Acknowledge state, which may be detected by ex-
ternal circuitry. The idle state can be identified by the
80376 giving no further assertions on its address
strobe output (ADS) since the beginning of its most
recent bus cycle, and the most recent bus cycle hav-
ing been terminated. The hold acknowledge state is
identified by the 80376 asserting its hold acknowl-
edge (HLDA) output.
The definition of each bus cycle is given by three
signals: M/IO, W/R and D/C. At the same time, a
valid address is present on the byte enable signals,
BHE and BLE, and the other address signals
A
23
–A . A status signal, ADS, indicates when the
1
80376 issues a new bus cycle definition and ad-
dress.
Collectively, the address bus, data bus and all asso-
ciated control signals are referred to simply as ‘‘the
bus’’. When active, the bus performs one of the bus
cycles below:
The shortest time unit of bus activity is a bus state. A
bus state is one processor clock period (two CLK2
periods) in duration. A complete data transfer occurs
during a bus cycle, composed of two or more bus
states.
1. Read from memory space
2. Locked read from memory space
3. Write to memory space
4. Locked write to memory space
40
376 EMBEDDED PROCESSOR
240182–19
Figure 4.4. Fastest Read Cycles with Non-Pipelined Timing
The fastest 80376 bus cycle requires only two bus
states. For example, three consecutive bus read cy-
cles, each consisting of two bus states, are shown
by Figure 4.4. The bus states in each cycle are
named T1 and T2. Any memory or I/O address may
be accessed by such a two-state bus cycle, if the
external hardware is fast enough.
selectable on a cycle-by-cycle basis with the Next
Address (NA) input.
When pipelining is selected the address (BHE, BLE
and A –A ) and definition (W/R, D/C, M/IO and
23
1
LOCK) of the next cycle are available before the end
of the current cycle. To signal their availability, the
80376 address status output (ADS) is asserted. Fig-
ure 4.5 illustrates the fastest read cycles with pipe-
lined timing.
Every bus cycle continues until it is acknowledged
by the external system hardware, using the 80376
READY input. Acknowledging the bus cycle at the
end of the first T2 results in the shortest bus cycle,
requiring only T1 and T2. If READY is not immedi-
ately asserted however, T2 states are repeated in-
definitely until the READY input is sampled active.
Note from Figure 4.5 the fastest bus cycles using
pipelining require only two bus states, named T1P
and T2P. Therefore pipelined cycles allow the same
data bandwidth as non-pipelined cycles, but ad-
dress-to-data access time is increased by one
T-state time compared to that of a non-pipelined cy-
cle.
The pipelining option provides a choice of bus cycle
timings. Pipelined or non-pipelined cycles are
41
376 EMBEDDED PROCESSOR
240182–20
Figure 4.5. Fastest Read Cycles with Pipelined Timing
ment for the speed of any external device. External
hardware, which has decoded the address and bus
cycle type, asserts the READY input at the appropri-
ate time.
READ AND WRITE CYCLES
Data transfers occur as a result of bus cycles, classi-
fied as read or write cycles. During read cycles, data
is transferred from an external device to the proces-
sor. During write cycles, data is transferred from the
processor to an external device.
At the end of the second bus state within the bus
cycle, READY is sampled. At that time, if external
hardware acknowledges the bus cycle by asserting
READY, the bus cycle terminates as shown in Figure
4.6. If READY is negated as in Figure 4.7, the 80376
executes another bus state (a wait state) and
READY is sampled again at the end of that state.
This continues indefinitely until the cycle is acknowl-
edged by READY asserted.
Two choices of bus cycle timing are dynamically se-
lectable: non-pipelined or pipelined. After an idle bus
state, the processor always uses non-pipelined tim-
ing. However the NA (Next Address) input may be
asserted to select pipelined timing for the next bus
cycle. When pipelining is selected and the 80376
has a bus request pending internally, the address
and definition of the next cycle is made available
even before the current bus cycle is acknowledged
by READY.
When the current cycle is acknowledged, the 80376
terminates it. When a read cycle is acknowledged,
the 80376 latches the information present at its data
pins. When a write cycle is acknowledged, the write
data of the 80376 remains valid throughout phase
one of the next bus state, to provide write data hold
time.
Terminating a read or write cycle, like any bus cycle,
requires acknowledging the cycle by asserting the
READY input. Until acknowledged, the processor in-
serts wait states into the bus cycle, to allow adjust-
42
376 EMBEDDED PROCESSOR
240182–21
Idle states are shown here for diagram variety only. Write cycles are not always followed by an idle state. An active bus
cycle can immediately follow the write cycle.
Figure 4.6. Various Non-Pipelined Bus Cycles (Zero Wait States)
During read or write cycles, the data bus behaves as
follows. If the cycle is a read, the 80376 floats its
Non-Pipelined Bus Cycles
Any bus cycle may be performed with non-pipelined
timing. For example, Figure 4.6 shows a mixture of
non-pipelined read and write cycles. Figure 4.6
shows that the fastest possible non-pipelined cycles
have two bus states per bus cycle. The states are
named T1 and T2. In phase one of T1, the address
signals and bus cycle definition signals are driven
valid and, to signal their availability, address strobe
(ADS) is simultaneously asserted.
data signals to allow driving by the external device
being addressed. The 80376 requires that all data
bus pins be at a valid logic state (HIGH or LOW)
at the end of each read cycle, when READY is
asserted. The system MUST be designed to
meet this requirement. If the cycle is a write, data
signals are driven by the 80376 beginning in phase
two of T1 until phase one of the bus state following
cycle acknowledgement.
43
376 EMBEDDED PROCESSOR
240182–22
Idle states are shown here for diagram variety only. Write cycles are not always followed by an idle state. An active bus
cycle can immediately follow the write cycle.
Figure 4.7. Various Non-Pipelined Bus Cycles (Various Number of Wait States)
Figure 4.7 illustrates non-pipelined bus cycles with
one wait state added to Cycles 2 and 3. READY is
sampled inactive at the end of the first T2 in Cycles
2 and 3. Therefore Cycles 2 and 3 have T2 repeated
again. At the end of the second T2, READY is sam-
pled active.
last one, as shown in Figure 4.7, Cycles 2 and 3. If
NA is sampled active during a T2 other than the last
one, the next state would be T2I or T2P instead of
another T2.
When address pipelining is not used, the bus states
and transitions are completely illustrated by Figure
4.8. The bus transitions between four possible
When address pipelining is not used, the address
and bus cycle definition remain valid during all wait
states. When wait states are added and it is desir-
able to maintain non-pipelined timing, it is necessary
to negate NA during each T2 state except the
states, T1, T2, T , and T . Bus cycles consist of T1
h
i
and T2, with T2 being repeated for wait states. Oth-
erwise the bus may be idle, T , or in the hold ac-
knowledge state T .
i
h
44
376 EMBEDDED PROCESSOR
240182–23
Bus States:
T1Ðfirst clock of a non-pipelined bus cycle (80376 drives new address and asserts ADS).
T2Ðsubsequent clocks of a bus cycle when NA has not been sampled asserted in the current bus cycle.
TiÐidle state.
ThÐhold acknowledge state (80376 asserts HLDA).
The fastest bus cycle consists of two states: T1 and T2.
Four basic bus states describe bus operation when not using pipelined address.
Figure 4.8. 80376 Bus States (Not Using Pipelined Address)
Bus cycles always begin with T1. T1 always leads to
T2. If a bus cycle is not acknowledged during T2 and
NA is inactive, T2 is repeated. When a cycle is ac-
knowledged during T2, the following state will be T1
of the next bus cycle if a bus request is pending
nally pending bus cycle before the current bus cycle
is acknowledged with READY asserted. ADS is as-
serted by the 80376 when the next address is is-
sued. The pipelining option is controlled on a cycle-
by-cycle basis with the NA input signal.
internally, or T if there is no bus request pending, or
T
i
if the HOLD input is being asserted.
Once a bus cycle is in progress and the current ad-
dress has been valid for at least one entire bus
state, the NA input is sampled at the end of every
phase one until the bus cycle is acknowledged. Dur-
ing non-pipelined bus cycles NA is sampled at the
end of phase one in every T2. An example is Cycle 2
in Figure 4.9, during which NA is sampled at the end
of phase one of every T2 (it was asserted once dur-
ing the first T2 and has no further effect during that
bus cycle).
h
Use of pipelining allows the 80376 to enter three
additional bus states not shown in Figure 4.8. Figure
4.12 is the complete bus state diagram, including
pipelined cycles.
Pipelined Bus Cycles
Pipelining is the option of requesting the address
and the bus cycle definition of the next inter-
45
376 EMBEDDED PROCESSOR
240182–24
Following any idle bus state (Ti), bus cycles are non-pipelined. Within non-pipelined bus cycles, NA is only sampled
during wait states. Therefore, to begin pipelining during a group of non-pipelined bus cycles requires a non-pipelined
cycle with at least one wait state (Cylcle 2 above).
Figure 4.9. Transitioning to Pipelining during Burst of Bus Cycles
If NA is sampled active, the 80376 is free to drive the
address and bus cycle definition of the next bus cy-
cle, and assert ADS, as soon as it has a bus request
internally pending. It may drive the next address as
early as the next bus state, whether the current bus
cycle is acknowledged at that time or not.
ledged by READY asserted, T2P will be entered
as soon as the 80376 does drive the next address
and status. External hardware should therefore
observe the ADS output as confirmation the next
address and status are actually being driven on
the bus.
2. Any address and status which are validated by a
pulse on the 80376 ADS output will remain stable
on the address pins for at least two processor
clock periods. The 80376 cannot produce a new
address and status more frequently than every
two processor clock periods (see Figures 4.9,
4.10 and 4.11).
Regarding the details of pipelining, the 80376 has
the following characteristics:
1. The next address and status may appear as early
as the bus state after NA was sampled active (see
Figures 4.9 or 4.10). In that case, state T2P is
entered immediately. However, when there is not
an internal bus request already pending, the next
address and status will not be available immedi-
ately after NA is asserted and T2I is entered in-
stead of T2P (see Figure 4.11 Cycle 3). Provided
the current bus cycle isn’t yet acknow-
3. Only the address and bus cycle definition of the
very next bus cycle is available. The pipelining ca-
pability cannot look further than one bus cycle
ahead (see Figure 4.11, Cycle 1).
46
376 EMBEDDED PROCESSOR
240182–25
Following any idle bus state (Ti) the bus cycle is always non-pipelined and NA is only sampled during wait states. To
start, address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (cycle 1 above).
The pipelined cycles (2, 3, 4 above) are shown with various numbers of wait states.
Figure 4.10. Fastest Transition to Pipelined Bus Cycle Following Idle Bus State
The complete bus state transition diagram, including
pipelining is given by Figure 4.12. Note it is a super-
set of the diagram for non-pipelined only, and the
three additional bus states for pipelining are drawn
in bold.
a pipelined bus cycle T1P. From an idle state, T , the
i
first bus cycle must begin with T1, and is therefore a
non-pipelined bus cycle. The next bus cycle will be
pipelined, however, provided NA is asserted and the
first bus cycle ends in a T2P state (the address and
status for the next bus cycle is driven during T2P).
The fastest path from an idle state to a pipelined bus
cycle is shown in bold below:
The fastest bus cycle with pipelining consists of just
two bus states, T1P and T2P (recall for non-pipe-
lined it is T1 and T2). T1P is the first bus state of a
pipelined cycle.
T , T , T1–T2–T2P,
i i
T1P–T2P,
idle non-pipelined
states cycle
pipelined
cycle
Initiating and Maintaining Pipelined Bus Cycles
Using the state diagram Figure 4.12, observe the
transitions from an idle state, T , to the beginning of
i
47
376 EMBEDDED PROCESSOR
240182–26
Figure 4.11. Details of Address Pipelining during Cycles with Wait States
T1–T2–T2P are the states of the bus cycle that es-
tablishes address pipelining for the next bus cycle,
which begins with T1P. The same is true after a bus
hold state, shown below:
The transition to pipelined address is shown func-
tionally by Figure 4.10, Cycle 1. Note that Cycle 1 is
used to transition into pipelined address timing for
the subsequent Cycles 2, 3 and 4, which are pipe-
lined. The NA input is asserted at the appropriate
time to select address pipelining for Cycles 2, 3 and
4.
T , T , T ,
h
T1–T2–T2P,
T1P–T2P,
h
h
hold aknowledge non-pipelined
states cycle
pipelined
cycle
Once a bus cycle is in progress and the current ad-
dress and status has been valid for one entire bus
state, the NA input is sampled at the end of every
phase one until the bus cycle is acknowledged.
48
376 EMBEDDED PROCESSOR
240182–27
Bus States:
T1Ðfirst clock of a non-pipelined bus cycle (80376 drives new address, status and asserts ADS).
T2Ðsubsequent clocks of a bus cycle when NA has not been sampled asserted in the current bus cycle.
T2IÐsubsequent clocks of a bus cycle when NA has been sampled asserted in the current bus cycle but there is not yet
an internal bus request pending (80376 will not drive new address, status or assert ADS).
T2PÐsubsequent clocks of a bus cycle when NA has been sampled asserted in the current bus cycle and there is an
internal bus request pending (80376 drives new address, status and asserts ADS).
T1PÐfirst clock of a pipelined bus cycle.
TiÐidle state.
ThÐhold acknowledge state (80376 asserts HLDA).
Asserting NA for pipelined bus cycles gives access to three more bus states: T2I, T2P and T1P.
Using pipelining the fastest bus cycle consists of T1P and T2P.
Figure 4.12. 80376 Processor Complete Bus States (Including Pipelining)
49
376 EMBEDDED PROCESSOR
Sampling begins in T2 during Cycle 1 in Figure 4.10.
Once NA is sampled active during the current cycle,
the 80376 is free to drive a new address and bus
cycle definition on the bus as early as the next bus
state. In Figure 4.10, Cycle 1 for example, the next
address and status is driven during state T2P. Thus
Cycle 1 makes the transition to pipelined timing,
since it begins with T1 but ends with T2P. Because
the address for Cycle 2 is available before Cycle 2
begins, Cycle 2 is called a pipelined bus cycle, and it
begins with T1P. Cycle 2 begins as soon as READY
asserted terminates Cycle 1.
pipelining ending after Cycle 4 because Cycle 4
ends in T2I. This indicates the 80376 didn’t have an
internal bus request prior to the acknowledgement
of Cycle 4. If a cycle ends with a T2 or T2I, the next
cycle will not be pipelined.
Realistically, pipelining is almost always maintained
as long as NA is sampled asserted. This is so be-
cause in the absence of any other request, a code
prefetch request is always internally pending until
the instruction decoder and code prefetch queue are
completely full. Therefore pipelining is maintained
for long bursts of bus cycles, if the bus is available
(i.e., HOLD inactive) and NA is sampled active in
each of the bus cycles.
Examples of transition bus cycles are Figure 4.10,
Cycle 1 and Figure 4.9, Cycle 2. Figure 4.10 shows
transition during the very first cycle after an idle bus
state, which is the fastest possible transition into ad-
dress pipelining. Figure 4.9, Cycle 2 shows a tran-
sition cycle occurring during a burst of bus cycles. In
any case, a transition cycle is the same whenever it
occurs: it consists at least of T1, T2 (NA is asserted
at that time), and T2P (provided the 80376 has an
internal bus request already pending, which it almost
always has). T2P states are repeated if wait states
are added to the cycle.
INTERRUPT ACKNOWLEDGE (INTA) CYCLES
In repsonse to an interrupt request on the INTR in-
put when interrupts are enabled, the 80376 performs
two interrupt acknowledge cycles. These bus cycles
are similar to read cycles in that bus definition sig-
nals define the type of bus activity taking place, and
each cycle continues until acknowledged by READY
sampled active.
Note that only three states (T1, T2 and T2P) are
required in a bus cycle performing a transition from
non-pipelined into pipelined timing, for example Fig-
ure 4.10, Cycle 1. Figure 4.10, Cycles 2, 3 and 4
show that pipelining can be maintained with two-
state bus cycles consisting only of T1P and T2P.
The state of A distinguishes the first and second
2
interrupt acknowledge cycles. The byte address
driven during the first interrupt acknowledge cycle is
4 (A –A , A , BLE LOW, A and BHE HIGH). The
23
3
1
2
byte address driven during the second interrupt ac-
knowledge cycle is 0 (A –A , BLE LOW and BHE
HIGH).
23
1
Once a pipelined bus cycle is in progress, pipelined
timing is maintained for the next cycle by asserting
NA and detecting that the 80376 enters T2P during
the current bus cycle. The current bus cycle must
end in state T2P for pipelining to be maintained in
the next cycle. T2P is identified by the assertion of
ADS. Figures 4.9 and 4.10 however, each show
The LOCK output is asserted from the beginning of
the first interrupt acknowledge cycle until the end of
the second interrupt acknowledge cycle. Four idle
bus states, T , are inserted by the 80376 between
i
the two interrupt acknowledge cycles for compatibil-
ity with the interrupt specification T
of the
RHRL
8259A Interrupt Controller and the 82370 Integrated
Peripheral.
50
376 EMBEDDED PROCESSOR
240182–28
Interrupt Vector (0–255) is read on D0–D7 at end of second Interrupt Acknowledge bus cycle.
Because each Interrupt Acknowledge bus cycle is followed by idle bus states, asserting NA has no practical effect.
Choose the approach which is simplest for your system hardware design.
Figure 4.13. Interrupt Acknowledge Cycles
During both interrupt acknowledge cycles, D –D
15
0
HALT INDICATION CYCLE
float. No data is read at the end of the first interrupt
acknowledge cycle. At the end of the second inter-
rupt acknowledge cycle, the 80376 will read an ex-
The 80376 execution unit halts as a result of execut-
ing a HLT instruction. Signaling its entrance into the
halt state, a halt indication cycle is performed. The
halt indication cycle is identified by the state of the
bus definition signals and a byte address of 2. See
the Bus Cycle Definition Signals section. The halt
indication cycle must be acknowledged by READY
asserted. A halted 80376 resumes execution when
INTR (if interrupts are enabled), NMI or RESET is
asserted.
ternal interrupt vector from D –D of the data bus.
0
7
The vector indicates the specific interrupt number
(from 0–255) requiring service.
51
376 EMBEDDED PROCESSOR
240182–29
Figure 4.14. Example Halt Indication Cycle from Non-Pipelined Cycle
SHUTDOWN INDICATION CYCLE
ENTERING AND EXITING HOLD
ACKNOWLEDGE
The 80376 shuts down as a result of a protection
fault while attempting to process a double fault. Sig-
naling its entrance into the shutdown state, a shut-
down indication cycle is performed. The shutdown
indication cycle is identified by the state of the bus
definition signals shown in Bus Cycle Definition
Signals and a byte address of 0. The shutdown indi-
cation cycle must be acknowledged by READY as-
serted. A shutdown 80376 resumes execution when
NMI or RESET is asserted.
The bus hold acknowledge state, T , is entered in
h
response to the HOLD input being asserted. In the
bus hold acknowledge state, the 80376 floats all
outputs or bidirectional signals, except for HLDA.
HLDA is asserted as long as the 80376 remains in
the bus hold acknowledge state. In the bus hold ac-
knowledge state, all inputs except HOLD and RE-
SET are ignored.
52
376 EMBEDDED PROCESSOR
240182–30
Figure 4.15. Example Shutdown Indication Cycle from Non-Pipelined Cycle
may be entered from a bus idle state as in Figure state will be T1 if a bus request is internally pending,
T
h
4.16 or after the acknowledgement of the current
physical bus cycle if the LOCK signal is not asserted,
as in Figures 4.17 and 4.18.
as in Figures 4.17 and 4.18. T is exited in response
h
to RESET being asserted.
If a rising edge occurs on the edge-triggered NMI
input while in T , the event is remembered as a non-
T
is exited in response to the HOLD input being
negated. The following state will be T as in Figure
h
h
maskable interrupt 2 and is serviced when T is exit-
h
ed unless the 80376 is reset before T is exited.
i
4.16 if no bus request is pending. The following bus
h
53
376 EMBEDDED PROCESSOR
240182–31
NOTE:
For maximum design flexibility the 80376 has no internal pull-up resistors on its outputs. Your design may require an
external pullup on ADS and other 80376 outputs to keep them negated during float periods.
Figure 4.16. Requesting Hold from Idle Bus
When an 80376 in a PQFP surface-mount package
is used without a socket, it cannot be removed from
RESET DURING HOLD ACKNOWLEDGE
RESET being asserted takes priority over HOLD be-
ing asserted. If RESET is asserted while HOLD re-
mains asserted, the 80376 drives its pins to defined
states during reset, as in Table 4.5, Pin State Dur-
ing Reset, and performs internal reset activity as
usual.
the printed circuit board. The FLT input allows the
80376 to be electrically isolated to allow testing of
external circuitry. This technique is known as ONCE
for ‘‘ON-Circuit Emulation’’.
ENTERING AND EXITING FLOAT
If HOLD remains asserted when RESET is inactive,
the 80376 enters the hold acknowledge state before
performing its first bus cycle, provided HOLD is still
asserted when the 80376 processor would other-
wise perform its first bus cycle. If HOLD remains as-
serted when RESET is inactive, the BUSY input is
still sampled as usual to determine whether a self
test is being requested.
FLT is an asynchronous, active-low input. It is recog-
nized on the rising edge of CLK2. When recognized,
it aborts the current bus cycle and floats the outputs
of the 80376 (Figure 4.20). FLT must be held low for
a minimum of 16 CLK2 cycles. Reset should be as-
serted and held asserted until after FLT is deassert-
ed. This will ensure that the 80376 will exit float in a
valid state.
Asserting the FLT input unconditionally aborts the
current bus cycle and forces the 80376 into the
FLOAT mode. Since activating FLT unconditionally
forces the 80376 into FLOAT mode, the 80376 is not
FLOAT
Activating the FLT input floats all 80376 bidirectional
and output signals, including HLDA. Asserting FLT
isolates the 80376 from the surrounding circuitry.
54
376 EMBEDDED PROCESSOR
240182–32
NOTE:
HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t and t ) require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
23 24
Figure 4.17. Requesting Hold from Active Bus (NA Inactive)
guaranteed to enter FLOAT in a valid state. After
deactivating FLT, the 80376 is not guaranteed to
exit FLOAT mode in a valid state. This is not a prob-
lem as the FLT pin is meant to be used only during
ONCE. After exiting FLOAT, the 80376 must be re-
set to return it to a valid state. Reset should be as-
serted before FLT is deasserted. This will ensure
that the 80376 will exit float in a valid state.
ed. A bus cycle in progress can be aborted at any
stage, or idle states or bus hold acknowledge states
discontinued so that the reset state is established.
RESET should remain asserted for at least 15 CLK2
periods to ensure it is recognized throughout the
80376, and at least 80 CLK2 periods if a 80376 self-
test is going to be requested at the falling edge. RE-
SET asserted pulses less than 15 CLK2 periods may
not be recognized. RESET pulses less than 80 CLK2
periods followed by a self-test may cause the self-
test to report a failure when no true failure exists.
FLT has an internal pull-up resistor, and if it is not
used it should be unconnected.
BUS ACTIVITY DURING AND FOLLOWING
RESET
Provided the RESET falling edge meets setup and
hold times t and t , the internal processor clock
25
26
phase is defined at that time as illustrated by Figure
4.19 and Figure 6.7.
RESET is the highest priority input signal, capable of
interrupting any processor activity when it is assert-
55
376 EMBEDDED PROCESSOR
240182–33
NOTE:
HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t and t ) require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
23 24
Figure 4.18. Requesting Hold from Idle Bus (NA Active)
An 80376 self-test may be requested at the time RE-
SET goes inactive by having the BUSY input at a
problem, the 80376 attempts to proceed with the
reset sequence afterwards.
LOW level as shown in Figure 4.19. The self-test
20
a
requires (2
approximately 60) CLK2 periods to
After the RESET falling edge (and after the self-test
if it was requested) the 80376 performs an internal
initialization sequence for approximately 350 to 450
CLK2 periods.
complete. The self-test duration is not affected by
the test results. Even if the self-test indicates a
56
376 EMBEDDED PROCESSOR
240182–34
NOTES:
1. BUSY should be held stable for 8 CLK2 periods before and after the CLK2 period in which RESET falling edge
occurs.
2. If self-test is requested, the 80376 outputs remain in their reset state as shown here.
Figure 4.19. Bus Activity from Reset until First Code Fetch
240182–53
Figure 4.20. Entering and Exiting FLOAT
57
376 EMBEDDED PROCESSOR
4.5 Self-Test Signature
As the 80376 begins supporting a coprocessor in-
struction, it tests the BUSY and ERROR signals to
determine if the coprocessor can accept its next in-
struction. Thus, the BUSY and ERROR inputs elimi-
nate the need for any ‘‘preamble’’ bus cycles for
communication between processor and coproces-
sor. The 80387SX can be given its command op-
code immediately. The dedicated signals provide
instruction synchronization, and eliminate the need
of using the 80376 WAIT opcode (9BH) for 80387SX
instruction synchronization (the WAIT opcode was
required when the 8086 or 8088 was used with the
8087 coprocessor).
Upon completion of self-test (if self-test was re-
quested by driving BUSY LOW at the falling edge of
RESET) the EAX register will contain a signature of
00000000H indicating the 80376 passed its self-test
of microcode and major PLA contents with no prob-
lems detected. The passing signature in EAX,
00000000H, applies to all 80376 revision levels. Any
non-zero signature indicates the 80376 unit is faulty.
4.6 Component and Revision
Identifiers
Custom coprocessors can be included in 80376
based systems by memory-mapped or I/O-mapped
To assist 80376 users, the 80376 after reset holds a
component identifier and revision identifier in its DX
register. The upper 8 bits of DX hold 33H as identifi-
cation of the 80376 component. (The lower nibble,
03H, refers to the Intel386TM architecture. The up-
per nibble, 30H, refers to the third member of the
Intel386 family). The lower 8 bits of DX hold an
8-bit unsigned binary number related to the compo-
nent revision level. The revision identifier will, in gen-
eral, chronologically track those component step-
pings which are intended to have certain improve-
ments or distinction from previous steppings. The
80376 revision identifier will track that of the 80386
where possible.
interfaces. Such coprocessor interfaces allow
a
completely custom protocol, and are not limited to a
set of coprocessor protocol ‘‘primitives’’. Instead,
memory-mapped or I/O-mapped interfaces may use
all applicable 80376 instructions for high-speed co-
processor communication. The BUSY and ERROR
inputs of the 80376 may also be used for the custom
coprocessor interface, if such hardware assist is de-
sired. These signals can be tested by the 80376
WAIT opcode (9BH). The WAIT instruction will wait
until the BUSY input is inactive (interruptable by an
NMI or enabled INTR input), but generates an ex-
ception 16 fault if the ERROR pin is active when the
BUSY goes (or is) inactive. If the custom coproces-
sor interface is memory-mapped, protection of the
addresses used for the interface can be provided
with the segmentation mechanism of the 80376. If
the custom interface is I/O-mapped, protection of
the interface can be provided with the 80376 IOPL
(I/O Privilege Level) mechanism.
The revision identifier is intended to assist 80376
users to a practical extent. However, the revision
identifier value is not guaranteed to change with ev-
ery stepping revision, or to follow a completely uni-
form numerical sequence, depending on the type or
intention of revision, or manufacturing materials re-
quired to be changed. Intel has sole discretion over
these characteristics of the component.
The 80387SX numeric coprocessor interface is I/O
mapped as shown in Table 4.8. Note that the
80387SX coprocessor interface addresses are be-
yond the 0H-0FFFFH range for programmed I/O.
When the 80376 supports the 80387SX coproces-
sor, the 80376 automatically generates bus cycles to
the coprocessor interface addresses.
Table 4.7. Component and
Revision Identifier History
80376 Stepping Name
Revision Identifier
A0
B
05H
08H
Table 4.8 Numeric Coprocessor Port Addresses
Address in 80376
I/O Space
80387SX
Coprocessor Register
4.7 Coprocessor Interfacing
8000F8H
8000FCH
8000FEH
Opcode Register
Operand Register
Operand Register
The 80376 provides an automatic interface for the
Intel 80387SX numeric floating-point coprocessor.
The 80387SX coprocessor uses an I/O mapped in-
terface driven automatically by the 80376 and as-
sisted by three dedicated signals: BUSY, ERROR
and PEREQ.
58
376 EMBEDDED PROCESSOR
Table 5.2. 80376
SOFTWARE TESTING FOR COPROCESSOR
PRESENCE
Maximum Allowable Ambient
Temperature at Various Airflows
When software is used to test coprocessor
(80387SX) presence, it should use only the following
coprocessor opcodes: FNINIT, FNSTCW and
FNSTSW. To use other coprocessor opcodes when
a coprocessor is known to be not present, first set
T ( C) vs Airflow-ft/min (m/sec)
A
§
200 400 600 800 1000
Package i
0
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
jc
100-Lead 7.5 70 78
Fine Pitch
85
90
90
95
92
98
93
99
e
EM
1 in the 80376 CR0 register.
88-Pin
PGA
2.5 70 81
5.0 PACKAGE THERMAL
SPECIFICATIONS
The Intel 80376 embedded processor is specified
for operation when case temperature is within the
range of 0 C–115 C for both the ceramic 88-pin
PGA package and the plastic 100-pin PQFP pack-
age. The case temperature may be measured in any
environment, to determine whether the 80376 is
within specified operating range. The case tempera-
ture should be measured at the center of the top
surface.
6.0 ELECTRICAL SPECIFICATIONS
§
§
The following sections describe recommended elec-
trical connections for the 80376, and its electrical
specifications.
6.1 Power and Grounding
The 80376 is implemented in CHMOS IV technology
and has modest power requirements. However, its
high clock frequency and 47 output buffers (address,
data, control, and HLDA) can cause power surges
as multiple output buffers drive new signal levels
simultaneously. For clean on-chip power distribution
The ambient temperature is guaranteed as long as
is not violated. The ambient temperature can be
T
c
calculated from the i and i from the following
jc
ja
equations:
e
e
e
a
b
a
T
T
T
T
P*i
P*i
J
c
jc
at high frequency, 14 V and 18 V pins separate-
CC SS
ly feed functional units of the 80376.
T
A
C
j
ja
Power and ground connections must be made to all
external V and GND pins of the 80376. On the
circuit board, all V pins should be connected on a
b
]
i
jc
[
T
P* i
a
ja
CC
CC
plane and all V pins should be connected on
Values for i and i are given in Table 5.1 for the
ja
jc
V
CC
a GND plane.
SS
100-lead fine pitch. i is given at various airflows.
ja
Table 5.2 shows the maximum T allowable (without
a
exceeding T ) at various airflows. Note that T can
c
a
be improved further by attaching ‘‘fins’’ or a ‘‘heat
sink’’ to the package. P is calculated using the maxi-
POWER DECOUPLING RECOMMENDATIONS
mum cold I of 305 mA and the maximum V
cc
5.5V for both packages.
of
CC
Liberal decoupling capacitors should be placed near
the 80376. The 80376 driving its 24-bit address bus
and 16-bit data bus at high frequencies can cause
transient power surges, particularly when driving
large capacitive loads. Low inductance capacitors
and interconnects are recommended for best high
frequency electrical performance. Inductance can
be reduced by shortening circuit board traces be-
tween the 80376 and decoupling capacitors as
much as possible.
Table 5.1. 80376 Package Thermal
Characteristics Thermal Resistances
( C/Watt) i and i
§
jc
ja
i
Versus Airflow-ft/min (m/sec)
ja
Package
i
0
200 400 600 800 1000
jc
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
100-Lead 7.5 34.5 29.5 25.5 22.5 21.5 21.0
Fine Pitch
RESISTOR RECOMMENDATIONS
88-Pin
PGA
2.5 29.0 22.5 17.0 14.5 12.5 12.0
The ERROR, FLT and BUSY inputs have internal
pull-up resistors of approximately 20 KX and the
PEREQ input has an internal pull-down resistor of
approximately 20 KX built into the 80376 to keep
these signals inactive when the 80387SX is not
present in the system (or temporarily removed from
its socket).
59
376 EMBEDDED PROCESSOR
In typical designs, the external pull-up resistors
shown in Table 6.1 are recommended. However, a
particular design may have reason to adjust the re-
sistor values recommended here, or alter the use of
pull-up resistors in other ways.
If not using address pipelining connect the NA pin to
.
a pull-up resistor in the range of 20 KX to V
CC
6.2 Absolute Maximum Ratings
Table 6.2. Maximum Ratings
Table 6.1. Recommended
Resistor Pull-Ups to V
CC
Parameter
Maximum Rating
Pin Signal Pull-Up Value
Purpose
b
b
a
65 C to 150 C
Storage Temperature
§
§
g
16 ADS
20 KX 10% Lightly Pull ADS
a
65 C to 120 C
Case Temperature
under Bias
§
§
Inactive during 80376
Hold Acknowledge
States
b
b
a
0.5V to 6.5V
Supply Voltage with
Respect to V
SS
g
26 LOCK 20 KX 10% Lightly Pull LOCK
Inactive during 80376
Hold Acknowledge
a
0.5)V
Voltage on Other Pins
0.5V to (V
CC
Table 6.2 gives a stress ratings only, and functional
operation at the maximums is not guaranteed. Func-
tional operating conditions are given in Section 6.3,
D.C. Specifications, and Section 6.4, A.C. Specifi-
cations.
States
OTHER CONNECTION RECOMMENDATIONS
For reliable operation, always connect unused in-
puts to an appropriate signal level. N/C pins should
always remain unconnected. Connection of N/C
Extended exposure to the Maximum Ratings may af-
fect device reliability. Furthermore, although the
80376 contains protective circuitry to resist damage
from static electric discharge, always take precau-
tions to avoid high static voltages or electric fields.
pins to V
or V
will result in incompatibility
CC SS
with future steppings of the 80376.
Particularly when not using interrupts or bus hold (as
when first prototyping), prevent any chance of spuri-
ous activity by connecting these associated inputs to
GND:
ÐINTR
ÐNMI
ÐHOLD
60
376 EMBEDDED PROCESSOR
6.3 D.C. Specifications
ADVANCE INFORMATION SUBJECT TO CHANGE
Table 6.3: 80376 D.C. Characteristics
e
e
g
5V 10%; T
Functional Operating Range: V
0 C to 115 C for 88-pin PGA or 100-pin PQFP
§
§
CC
CASE
Symbol
Parameter
Input LOW Voltage
Min
Max
Unit
(1)
V
(1)
V
(1)
V
(1)
V
b
a
V
V
V
V
V
0.3
0.8
IL
a
Input HIGH Voltage
2.0
V
0.3
IH
CC
b
a
CLK2 Input LOW Voltage
CLK2 Input HIGH Voltage
Output LOW Voltage
0.3
0.8
ILC
IHC
OL
b
a
0.3
V
0.8
V
CC
CC
(1)
(1)
e
I
I
4 mA:
5 mA:
A
–A , D –D
0
0.45
0.45
V
OL
OL
23
1
15
e
BHE, BLE, W/R,
D/C, M/IO, LOCK,
ADS, HLDA
V
V
OH
Output High Voltage
(1)
(1)
e b
e b
I
I
1 mA:
A
–A , D –D
15
2.4
V
V
OH
OH
23
1
0
b
0.2 mA:
V
V
0.5
0.5
CC
A
–A , D –D
15
23
1
0
(1)
(1)
e b
e b
I
I
I
0.9 mA: BHE, BLE, W/R,
D/C, M/IO, LOCK,
ADS, HLDA
2.4
V
V
OH
OH
LI
b
0.18 mA: BHE, BLE, W/R,
D/C, M/IO, LOCK
ADS, HLDA
CC
(1)
s
s
g
Input Leakage Current
(For All Pins except
PEREQ, BUSY, FLT and ERROR)
15
mA, 0V
V
V
CC
IN
(1, 2)
(3)
e
2.4V
I
I
Input Leakage Current
(PEREQ Pin)
200
mA, V
mA, V
IH
IL
IH
IL
b
e
0.45V
Input Leakage Current
(BUSY and ERROR Pins)
400
(1)
s
s
V
g
I
I
Output Leakage Current
15
mA, 0.45V
V
LO
CC
OUT
CC
Supply Current
(4)
e
e
e
e
CLK2
CLK2
32 MHz
40 MHz
275
305
mA, I typ
CC
mA, I typ
175 mA
200 mA
(4)
CC
(5)
e
e
e
C
C
C
Input Capacitance
10
12
20
pF, F
pF, F
pF, F
1 MHz
1 MHz
1 MHz
IN
C
C
C
(5)
(5)
Output or I/O Capacitance
CLK2 Capacitance
OUT
CLK
NOTES:
1. Tested at the minimum operating frequency of the device.
2. PEREQ input has an internal pull-down resistor.
3. BUSY, FLT and ERROR inputs each have an internal pull-up resistor.
4. I max measurement at worse case load, V and temperature (0 C).
§
CC
5. Not 100% tested.
CC
61
376 EMBEDDED PROCESSOR
The A.C. specifications given in Table 6.4 consist of
output delays, input setup requirements and input
hold requirements. All A.C. specifications are rela-
tive to the CLK2 rising edge crossing the 2.0V level.
smallest acceptable sampling window. Within the
sampling window, a synchronous input signal must
be stable for correct 80376 processor operation.
Outputs NA, W/R, D/C, M/IO, LOCK, BHE, BLE,
A.C. specification measurement is defined by Figure
6.1. Inputs must be driven to the voltage levels indi-
cated by Figure 6.1 when A.C. specifications are
measured. 80376 output delays are specified with
minimum and maximum limits measured as shown.
The minimum 80376 delay times are hold times pro-
vided to external circuitry. 80376 input setup and
hold times are specified as minimums, defining the
A
–A and HLDA only change at the beginning of
23 1
phase one. D –D (write cycles) only change at the
15
0
beginning of phase two. The READY, HOLD, BUSY,
ERROR, PEREQ and D –D (read cycles) inputs
are sampled at the beginning of phase one. The NA,
INTR and NMI inputs are sampled at the beginning
of phase two.
15
0
240182–35
LEGEND:
AÐMaximum Output Delay Spec.
BÐMinimum Output Delay Spec.
CÐMinimum Input Setup Spec.
DÐMinimum Input Hold Spec.
Figure 6.1. Drive Levels and Measurement Points for A.C. Specifications
62
376 EMBEDDED PROCESSOR
6.4 A.C. Specifications
Table 6.4. 80376 A.C. Characteristics at 16 MHz
e
e
g
5V 10%; T
Functional Operating Range: V
0 C to 115 C for 88-pin PGA or 100-pin PQFP
§
§
CC
CASE
Symbol
Parameter
Operating Frequency
CLK2 Period
Min
Max
Unit
MHz
ns
Figure
Notes
4
16
Half CLK2 Freq
t
t
t
t
t
t
t
t
t
t
31
9
125
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.5
6.6
6.5
1
(3)
CLK2 HIGH Time
CLK2 HIGH Time
CLK2 LOW Time
CLK2 LOW Time
CLK2 Fall Time
ns
At 2
2a
2b
3a
3b
4
(3)
b
0.8)V
5
ns
At (V
CC
(3)
9
ns
At 2V
(3)
7
ns
At 0.8V
(3)
b
0.8)V to 0.8V
8
ns
(V
CC
(3)
b
0.8)
CLK2 Rise Time
8
ns
0.8V to (V
5
CC
(4)
120 pF
e
e
A
A
–A Valid Delay
1
4
4
4
36
40
36
ns
C
L
6
23
23
(1)
–A Float Delay
1
ns
7
(4)
BHE, BLE, LOCK
Valid Delay
ns
C
75 pF
75 pF
120 pF
8
L
(1)
t
t
t
t
t
BHE, BLE, LOCK
Float Delay
4
6
6
4
4
40
33
35
40
35
33
ns
ns
ns
ns
ns
6.6
6.5
6.6
6.5
6.6
9
(4)
e
e
e
W/R, M/IO, D/C,
ADS Valid Delay
C
L
10
11
12
13
(1)
W/R, M/IO, D/C,
ADS Float Delay
(4)
D
Valid Delay
–D Write Data
C
L
15
0
(1)
D
Float Delay
–D Write Data
15
0
(4)
75 pF
t
t
t
t
t
t
t
t
t
t
t
HLDA Valid Delay
NA Setup Time
NA Hold Time
4
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.6
6.4
6.6
6.4
6.4
6.4
6.4
6.4
6.4
6.7
6.7
C
L
14
15
16
19
20
21
22
23
24
25
26
21
19
4
READY Setup Time
READY Hold Time
Setup Time D –D Read Data
15 0
9
Hold Time D –D Read Data
15 0
6
HOLD Setup Time
HOLD Hold Time
RESET Setup Time
RESET Hold Time
26
5
13
4
63
376 EMBEDDED PROCESSOR
Table 6.4. 80376 A.C. Characteristics at 16 MHz (Continued)
e
e
g
5V 10%; T
Functional Operating Range: V
0 C to 115 C for 88-pin PGA or 100-pin PQFP
§ §
CC
CASE
Symbol
Parameter
Min
Max
Unit
ns
Figure
6.4
Notes
(2)
t
t
t
NMI, INTR Setup Time
NMI, INTR Hold Time
16
16
16
27
28
29
(2)
(2)
ns
6.4
PEREQ, ERROR, BUSY, FLT
Setup Time
ns
6.4
(2)
t
PEREQ, ERROR, BUSY, FLT
Hold Time
5
ns
6.4
30
NOTES:
1. Float condition occurs when maximum output current becomes less than I
tested.
in magnitude. Float delay is not 100%
LO
2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes,
to assure recognition within a specific CLK2 period.
3. These are not tested. They are guaranteed by design characterization.
4. Tested with C set to 50 pF and derated to support the indicated distributed capacitive load. See Figures 6.8 through 6.10
L
for capacitive derating curves.
5. The 80376 does not have t or t timing specifications.
17 18
Table 6.5. 80376 A.C. Characteristics at 20 MHz
e
e
g
5V 10%; T
Functional Operating Range: V
0 C to 115 C for 88-pin PGA or 100-pin PQFP
§
§
CC
CASE
Max
20
Symbol
Parameter
Min
4
Unit
MHz
ns
Figure
Notes
Operating Frequency
CLK2 Period
Half CLK2 Frequency
t
t
t
t
t
t
t
t
t
t
25
8
125
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.5
6.6
6.5
1
(3)
CLK2 HIGH Time
CLK2 HIGH Time
CLK2 LOW Time
CLK2 LOW Time
CLK2 Fall Time
CLK2 Rise Time
ns
At 2V
2a
2b
3a
3b
4
(3)
b
0.8)V
5
ns
At (V
CC
(3)
8
ns
At 2V
(3)
6
ns
At 0.8V
(3)
b
0.8V) to 0.8V
8
8
ns
(V
CC
(3)
b
0.8)
ns
0.8V to (V
5
CC
(4)
120 pF
e
e
A
A
–A Valid Delay
1
4
4
4
30
ns
C
L
6
23
23
(1)
–A Float Delay
1
ns
7
(4)
BHE, BLE, LOCK
Valid Delay
30
32
28
26
30
38
27
ns
C
75 pF
8
L
(1)
t
t
t
t
t
t
BHE, BLE, LOCK
Float Delay
4
6
6
6
4
4
ns
ns
ns
ns
ns
ns
6.6
6.5
6.5
6.6
6.5
6.6
9
(4)
e
e
M/IO, D/C
Valid Delay
C
C
75 pF
75 pF
10a
10b
11
12
13
L
L
(4)
W/R, ADS
Valid Delay
(1)
W/R, M/IO, D/C,
ADS Float Delay
e
D
Valid Delay
–D Write Data
C
L
120 pF
15
0
(1)
D
Float Delay
–D Write Data
15
0
64
376 EMBEDDED PROCESSOR
Table 6.5. 80376 A.C. Characteristics at 20 MHz (Continued)
e
e
g
5V 10%; T
Functional Operating Range: V
0 C to 115 C for 88-pin PGA or 100-pin PQFP
§
§
CC
CASE
Min
4
Symbol
Parameter
HLDA Valid Delay
Max
Unit
Figure
6.5
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.7
6.7
6.4
6.4
6.4
Notes
(4)
e
75 pF
t
t
t
t
t
t
t
t
t
t
t
t
t
t
28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
14
15
16
19
20
21
22
23
24
25
26
27
28
29
L
NA Setup Time
5
NA Hold Time
12
12
4
READY Setup Time
READY Hold Time
D
D
–D Read Data Setup Time
0
9
15
15
–D Read Data Hold Time
0
6
HOLD Setup Time
HOLD Hold Time
17
5
RESET Setup Time
RESET Hold Time
NMI, INTR Setup Time
NMI, INTR Hold Time
12
4
(2)
(2)
(2)
16
16
14
PEREQ, ERROR, BUSY, FLT
Setup Time
(2)
t
PEREQ, ERROR, BUSY, FLT
Hold Time
5
ns
6.4
30
NOTES:
1. Float condition occurs when maximum output current becomes less than I
tested.
in magnitude. Float delay is not 100%
LO
2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes,
to assure recognition within a specific CLK2 period.
3. These are not tested. They are guaranteed by design characterization.
4. Tested with C set to 50 pF and derated to support the indicated distributed capacitive load. See Figures 6.8 through 6.10
L
for capacitive derating curves.
5. The 80376 does not have t or t timing specifications.
17 18
A.C. TEST LOADS
A.C. TIMING WAVEFORMS
240182–36
240182–37
Figure 6.2. A.C. Test Loads
Figure 6.3. CLK2 Waveform
65
376 EMBEDDED PROCESSOR
240182–38
Figure 6.4. A.C. Timing WaveformsÐInput Setup and Hold Timing
240182–39
Figure 6.5. A.C. Timing WaveformsÐOutput Valid Delay Timing
66
376 EMBEDDED PROCESSOR
240182–40
Figure 6.6. A.C. Timing WaveformsÐOutput Float Delay and HLDA Valid Delay Timing
240182–41
The second internal processor phase following RESET high-to-low transition (provided t and t are met) is U2.
25 26
Figure 6.7. A.C. Timing WaveformsÐRESET Setup and Hold Timing, and Internal Phase
67
376 EMBEDDED PROCESSOR
240182–43
240182–42
Figure 6.9. Typical Output Valid Delay versus
Load Capacitance at Maximum Operating
Figure 6.8. Typical Output Valid Delay versus
Load Capacitance at Maximum Operating
e
e
Temperature (C
75 pF)
L
Temperature (C
120 pF)
L
240182–44
Figure 6.10. Typical Output Rise
Time versus Load Capacitance at
Maximum Operating Temperature
240182–45
Figure 6.11. Typical I vs Frequency
CC
68
376 EMBEDDED PROCESSOR
3. The emulation processor receives the RESET sig-
nal 2 or 4 CLK2 cycles later than an 80376 would,
and responds to RESET later. Correct phase of
the response is guaranteed.
6.5 Designing for the ICETM-376
Emulator
The 376 embedded processor in-circuit emulator
product is the ICE-376 emulator. Use of the emula-
tor requires the target system to provide a socket
that is compatible with the ICE-376 emulator. The
80376 offers two different probes for emulating user
systems: an 88-pin PGA probe and a 100-pin fine
pitch flat-pack probe. The 100-pin fine pitch flat-
pack probe requires a socket, called the 100-pin
PQFP, which is available from 3-M Textool (part
number 2-0100-07243-000). The ICE-376 emulator
probe attaches to the target system via an adapter
which replaces the 80376 component in the target
system. Because of the high operating frequency of
80376 systems and of the ICE-376 emulator, there is
no buffering between the 80376 emulation proces-
sor in the ICE-376 emulator probe and the target
system. A direct result of the non-buffered intercon-
nect is that the ICE-376 emulator shares the ad-
dress and data bus with the user’s system, and the
RESET signal is intercepted by the ICE emulator
hardware. In order for the ICE-376 emulator to be
functional in the user’s system without the Optional
Isolation Board (OIB) the designer must be aware of
the following conditions:
In addition to the above considerations, the ICE-376
emulator processor module has several electrical
and mechanical characteristics that should be taken
into consideration when designing the 80376 sys-
tem.
Capacitive Loading: ICE-376 adds up to 27 pF to
each 80376 signal.
Drive Requirements: ICE-376 adds one FAST TTL
load on the CLK2, control, address, and data lines.
These loads are within the processor module and
are driven by the 80376 emulation processor, which
has standard drive and loading capability listed in
Tables 6.3 and 6.4.
Power Requirements: For noise immunity and
CMOS latch-up protection the ICE-376 emulator
processor module is powered by the user system.
The circuitry on the processor module draws up to
1.4A including the maximum 80376 I
user 80376 socket.
from the
CC
1. The bus controller must only enable data trans-
ceivers onto the data bus during valid read cycles
of the 80376, other local devices or other bus
masters.
80376 Location and Orientation: The ICE-376 em-
ulator processor module may require lateral clear-
ance. Figure 6.12 shows the clearance requirements
of the iMP adapter and Figure 6.13 shows the clear-
ance requirements of the 88-pin PGA adapter. The
2. Before another bus master drives the local proc-
essor address bus, the other master must gain
control of the address bus by asserting HOLD and
receiving the HLDA response.
240182–46
Figure 6.12. Preliminary ICETM-376 Emulator User Cable with PQFP Adapter
69
376 EMBEDDED PROCESSOR
240182–50
Figure 6.13. ICETM-376 Emulator User Cable with 88-Pin PGA Adapter
optional isolation board (OIB), which provides extra
electrical buffering and has the same lateral clear-
ance requirements as Figures 6.12 and 6.13, adds
an additional 0.5 inches to the vertical clearance re-
quirement. This is illustrated in Figure 6.14.
on the user’s bus. The OIB allows the ICE-376 emu-
lator to function in user systems with faults (shorted
signals, etc.). After electrical verification the OIB
may be removed. When the OIB is installed, the user
system must have a maximum CLK2 frequency of 20
MHz.
Optional Isolation Board (OIB) and the CLK2
speed reduction: Due to the unbuffered probe de-
sign, the ICE-376 emulator is susceptible to errors
240182–51
Figure 6.14. ICETM-376 Emulator User Cable with OIB and PQFP Adapter
70
376 EMBEDDED PROCESSOR
7. The 80376 has no paging mechanism.
7.0 DIFFERENCES BETWEEN THE
80376 AND THE 80386
8. The 80376 starts executing code in what corre-
sponds to the 80386 protected mode. The 80386
starts execution in real mode, which is then used
to enter protected mode.
The following are the major differences between the
80376 and the 80386.
1. The 80376 generates byte selects on BHE and
BLE (like the 8086 and 80286 microprocessors)
to distinguish the upper and lower bytes on its
16-bit data bus. The 80386 uses four-byte selects,
BE0–BE3, to distinguish between the different
bytes on its 32-bit bus.
9. The 80386 has a virtual-86 mode that allows the
execution of a real mode 8086 program as a task
in protected mode. The 80376 has no virtual-86
mode.
10. The 80386 maps a 48-bit logical address into a
32-bit physical address by segmentation and
paging. The 80376 maps its 48-bit logical ad-
dress into a 24-bit physical address by segmen-
tation only.
2. The 80376 has no bus sizing option. The 80386
can select between either a 32-bit bus or a 16-bit
bus by use of the BS16 input. The 80376 has a
16-bit bus size.
11. The 80376 uses the 80387SX numerics coproc-
essor for floating point operations, while the
80386 uses the 80387 coprocessor.
3. The NA pin operation in the 80376 is identical to
that of the NA pin on the 80386 with one excep-
tion: the NA pin of the 80386 cannot be activated
on 16-bit bus cycles (where BS16 is LOW in the
80386 case), whereas NA can be activated on
any 80376 bus cycle.
12. The 80386 can execute from 16-bit code seg-
ments. The 80376 can only execute from 32-bit
code Segments.
13. The 80376 has an input called FLT which three-
states all bidirectional and output pins, including
HLDA, when asserted. It is used with ON Circuit
Emulation (ONCE).
4. The contents of all 80376 registers at reset are
identical to the contents of the 80386 registers at
reset, except the DX register. The DX register
contains a component-stepping identifier at reset,
i.e.
e
e
e
e
in 80386, after reset DH
03H indicates 80386
revision number;
8.0 INSTRUCTION SET
DL
in 80376, after reset DH
DL
This section describes the 376 embedded processor
instruction set. Table 8.1 lists all instructions along
with instruction encoding diagrams and clock
counts. Further details of the instruction encoding
are then provided in the following sections, which
completely describe the encoding structure and the
definition of all fields occurring within 80376 instruc-
tions.
33H indicates 80376
revision number.
5. The 80386 uses A and M/IO as a select for
31
numerics coprocessor. The 80376 uses the
A
23
sor.
and M/IO to select its numerics coproces-
6. The 80386 prefetch unit fetches code in four-
byte units. The 80376 prefetch unit reads two
bytes as one unit (like the 80286 microproces-
sor). In BS16 mode, the 80386 takes two con-
secutive bus cycles to complete a prefetch re-
quest. If there is a data read or write request
after the prefetch starts, the 80386 will fetch
all four bytes before addressing the new re-
quest.
8.1 80376 Instruction Encoding and
Clock Count Summary
To calculate elapsed time for an instruction, multiply
the instruction clock count, as listed in Table 8.1 be-
low, by the processor clock period (e.g. 50 ns for an
80376 operating at 20 MHz). The actual clock count
of an 80376 program will average 10% more
71
376 EMBEDDED PROCESSOR
e
than the calculated clock count due to instruction
sequences which execute faster than they can be
fetched from memory.
Ðn
number of times repeated.
e
Ðm
number of components in the next instruc-
tion executed, where the entire displacement (if
any) counts as one component, the entire im-
mediate data (if any) counts as one component,
and all other bytes of the instruction and pre-
fix(es) each count as one component.
Instruction Clock Count Assumptions:
1. The instruction has been prefetched, decoded,
and is ready for execution.
2. Bus cycles do not require wait states.
Misaligned or 32-Bit Operand Accesses:
3. There are no local bus HOLD requests delaying
processor acess to the bus.
Ð If instructions accesses a misaligned 16-bit oper-
and or 32-bit operand on even address add:
4. No exceptions are detected during instruction ex-
ecution.
2* clocks for read or write.
4** clocks for read and write.
5. If an effective address is calculated, it does not
use two general register components. One regis-
ter, scaling and displacement can be used within
the clock counts showns. However, if the effec-
tive address calculation uses two general register
components, add 1 clock to the clock count
shown.
Ð If instructions accesses a 32-bit operand on odd
address add:
4* clocks for read or write.
8** clocks for read and write.
Wait States:
6. Memory reference instruction accesses byte or
aligned 16-bit operands.
Wait states add 1 clock per wait state to instruction
execution for each data access.
Instruction Clock Count Notation
Ð If two clock counts are given, the smaller refers to
a register operand and the larger refers to a
memory operand.
72
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
GENERAL DATA TRANSFER
e
MOV
Move:
Register to Register/Memory
1 0 0 0 1 0 0 w
1 0 0 0 1 0 1 w
1 1 0 0 0 1 1 w
mod reg
mod reg
r/m
r/m
2/2*
2/4*
2/2*
2
0/1*
0/1*
0/1*
2
a
a
a
Register/Memory to Register
Immediate to Register/Memory
mod 0 0 0 r/m immediate data
reg immediate data
Immediate to Register (Short Form)
Memory to Accumulator (Short Form)
Accumulator to Memory (Short Form)
Register/Memory to Segment Register
Segment Register to Register/Memory
1 0 1 1 w
1 0 1 0 0 0 0 w
1 0 1 0 0 0 1 w
1 0 0 0 1 1 1 0
1 0 0 0 1 1 0 0
full displacement
full displacement
mod sreg3 r/m
mod sreg3 r/m
4*
1*
a
a
2*
1*
22/23*
2/2*
0/6*
0/1*
a,b,c
a
e
MOVSX
Move with Sign Extension
Register from Register/Memory
0 0 0 0 1 1 1 1
1 0 1 1 1 1 1 w mod reg
r/m
r/m
3/6*
3/6*
0/1*
0/1*
a
a
e
MOVZX
Move with Zero Extension
Register from Register/Memory
0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 1 1 0 1 1 w mod reg
mod 1 1 0 r/m
e
PUSH
Push:
Register/Memory
7/9*
4
2/4*
2
a
a
a
a
a
a
Register (Short Form)
0 1 0 1 0
reg
Segment Register (ES, CS, SS or DS)
0 0 0 sreg2 1 1 0
0 0 0 0 1 1 1 1
0 1 1 0 1 0 s 0
0 1 1 0 0 0 0 0
4
2
Segment Register (FS or GS)
Immediate
1 0 sreg3 0 0 0
immediate data
4
2
4
2
e
PUSHA
Push All
Pop
34
16
e
POP
Register/Memory
1 0 0 0 1 1 1 1
mod 0 0 0 r/m
7/9*
6
2/4*
2
a
a
Register (Short Form)
0 1 0 1 1
reg
Segment Register (ES, SS or DS)
0 0 0 sreg 2 1 1 1
0 0 0 0 1 1 1 1
0 1 1 0 0 0 0 1
25
25
40
6
a, b, c
a, b, c
a
Segment Register (FS or GS)
1 0 sreg 3 0 0 1
6
e
e
POPA
XCHG
Pop All
16
Exchange
Register/Memory with Register
1 0 0 0 0 1 1 w
mod reg
r/m
3/5**
0/2**
a, m
Register with Accumulator (Short Form)
1 0 0 1 0
reg
3
0
e
IN
Input from:
Fixed Port
1 1 1 0 0 1 0 w
1 1 1 0 1 1 0 w
port number
6*
26*
7*
1*
1*
1*
1*
f,k
f,l
Variable Port
f,k
f,l
27*
e
OUT
Output to:
Fixed Port
1 1 1 0 0 1 1 w
1 1 1 0 1 1 1 w
1 0 0 0 1 1 0 1
port number
4*
1*
1*
f,k
f,l
24*
Variable Port
5*
1*
1*
f,k
f,l
26*
e
LEA
Load EA to Register
mod reg
r/m
2
73
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
SEGMENT CONTROL
e
e
e
LDS
LES
LFS
Load Pointer to DS
Load Pointer to ES
Load Pointer to FS
1 1 0 0 0 1 0 1
1 1 0 0 0 1 0 0
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
mod reg
mod reg
r/m
r/m
26*
26*
29*
29*
26*
6*
6*
6*
6*
6*
a, b, c
a, b, c
a, b, c
a, b, c
a, b, c
1 0 1 1 0 1 0 0
1 0 1 1 0 1 0 1
1 0 1 1 0 0 1 0
mod reg
mod reg
mod reg
r/m
r/m
r/m
e
LGS Load Pointer to GS
e
LSS
Load Pointer to SS
FLAG CONTROL
e
e
CLC
CLD
Clear Carry Flag
1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 0
1 1 1 1 1 0 1 0
0 0 0 0 1 1 1 1
1 1 1 1 0 1 0 1
1 0 0 1 1 1 1 1
1 0 0 1 1 1 0 1
1 0 0 1 1 1 0 0
1 0 0 1 1 1 1 0
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 1
2
2
8
5
2
2
7
4
3
2
2
8
Clear Direction Flag
e
CLI
Clear Interrupt Enable Flag
f
e
CLTS
CMC
Clear Task Switched Flag
Complement Carry Flag
0 0 0 0 0 1 1 0
e
e
e
LAHF
POPF
Load AH into Flag
Pop Flags
e
a, g
a
e
PUSHF
Push Flags
e
SAHF
Store AH into Flags
Set Carry Flag
e
STC
STD
e
Set Direction Flag
e
STI
Set Interrupt Enable Flag
f
ARITHMETIC
e
ADD
Add
Register to Register
0 0 0 0 0 0 d w
0 0 0 0 0 0 0 w
0 0 0 0 0 0 1 w
1 0 0 0 0 0 s w
0 0 0 0 0 1 0 w
mod reg
mod reg
mod reg
r/m
2
7**
6*
Register to Memory
r/m
r/m
2**
1*
a
a
a
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (Short Form)
mod 0 0 0 r/m immediate data
immediate data
2/7**
2
0/2**
e
ADC
Add with Carry
Register to Register
0 0 0 1 0 0 d w
0 0 0 1 0 0 0 w
0 0 0 1 0 0 1 w
1 0 0 0 0 0 s w
0 0 0 1 0 1 0 w
mod reg
mod reg
mod reg
r/m
r/m
r/m
2
7**
6*
Register to Memory
2**
1*
a
a
a
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (Short Form)
mod 0 1 0 r/m immediate data
immediate data
2/7**
2
0/2**
e
INC
Increment
Register/Memory
1 1 1 1 1 1 1 w
mod 0 0 0 r/m
2/6**
0/2**
a
Register (Short Form)
0 1 0 0 0
reg
2
e
SUB
Subtract
Register from Register
0 0 1 0 1 0 d w
mod reg
r/m
2
74
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
Of Data
Cycles
Clock
Counts
Instruction
Format
Notes
ARITHMETIC (Continued)
Register from Memory
0 0 1 0 1 0 0 w mod reg
0 0 1 0 1 0 1 w mod reg
r/m
r/m
7**
6*
2**
1
a
a
a
Memory from Register
Immediate from Register/Memory
Immediate from Accumulator (Short Form)
1 0 0 0 0 0 s w mod 1 0 1 r/m immediate data
2/7**
2
0/1**
0 0 1 0 1 1 0 w
immediate data
e
SBB
Subtract with Borrow
Register from Register
0 0 0 1 1 0 d w mod reg
0 0 0 1 1 0 0 w mod reg
0 0 0 1 1 0 1 w mod reg
r/m
r/m
r/m
2
7**
6*
Register from Memory
2**
1*
a
a
a
Memory from Register
Immediate from Register/Memory
Immediate from Accumulator (Short Form)
1 0 0 0 0 0 s w mod 0 1 1 r/m immediate data
2/7**
2
0/2**
0 0 0 1 1 1 0 w
immediate data
e
DEC
Decrement
Register/Memory
1 1 1 1 1 1 1 w reg 0 0 1
r/m
2/6**
0/2**
a
Register (Short Form)
0 1 0 0 1
reg
2
e
CMP
Compare
Register with Register
0 0 1 1 1 0 d w mod reg
0 0 1 1 1 0 0 w mod reg
0 0 1 1 1 0 1 w mod reg
r/m
r/m
r/m
2
5*
6**
2/5*
2
Memory with Register
1*
a
a
a
Register with Memory
2**
Immediate with Register/Memory
Immediate with Accumulator (Short Form)
1 0 0 0 0 0 s w mod 1 1 1 r/m immediate data
0 0 1 1 1 1 0 w immediate data
0/1*
e
e
e
e
e
e
NEG
AAA
AAS
DAA
DAS
MUL
Change Sign
1 1 1 1 0 1 1 w mod 0 1 1 r/m
0 0 1 1 0 1 1 1
2/6*
4
0/2*
a
ASCII Adjust for Add
ASCII Adjust for Subtract
Decimal Adjust for Add
Decimal Adjust for Subtract
Multiply (Unsigned)
0 0 1 1 1 1 1 1
4
0 0 1 0 0 1 1 1
4
0 0 1 0 1 1 1 1
4
Accumulator with Register/Memory
1 1 1 1 0 1 1 w mod 1 0 0 r/m
MultiplierÐByte
ÐWord
12–17/15–20
12–25/15–28*
12–41/17–46*
0/1
0/1*
0/2*
a,n
a,n
a,n
ÐDoubleword
e
IMUL
Integer Multiply (Signed)
Accumulator with Register/Memory
1 1 1 1 0 1 1 w mod 1 0 1 r/m
MultiplierÐByte
ÐWord
12–17/15–20
12–25/15–28*
12–41/17–46*
0/1
0/1*
0/2*
a,n
a,n
a,n
ÐDoubleword
Register with Register/Memory
0 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1 mod reg
r/m
MultiplierÐByte
ÐWord
12–17/15–20
12–25/15–28*
12–41/17–46*
0/1
0/1*
0/2*
a,n
a,n
a,n
ÐDoubleword
Register/Memory with Immediate to Register 0 1 1 0 1 0 s 1 mod reg
r/m immediate data
ÐWord
13–26/14–27*
13–42/16–45*
0/1*
0/2*
a,n
a,n
ÐDoubleword
75
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
Of Data
Cycles
Clock
Counts
Instruction
Format
Notes
ARITHMETIC (Continued)
e
DIV
Divide (Unsigned)
Accumulator by Register/Memory
1 1 1 1 0 1 1 w mod 1 1 0 r/m
DivisorÐByte
ÐWord
14/17
22/25*
38/43*
0/1
0/1*
0/2*
a, o
a, o
a, o
ÐDoubleword
e
IDIV
Integer Divide (Signed)
Accumulator by Register/Memory
1 1 1 1 0 1 1 w mod 1 1 1 r/m
DivisorÐByte
ÐWord
19/22
27/30*
43/48*
0/1
0/1
a, o
a, o
a, o
ÐDoubleword
0/2*
e
e
e
e
AAD
AAM
CBW
CWD
ASCII Adjust for Divide
ASCII Adjust for Multiply
Convert Byte to Word
1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0
1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0
1 0 0 1 1 0 0 0
19
17
3
Convert Word to Double Word 1 0 0 1 1 0 0 1
2
LOGIC
Shift Rotate Instructions
Not Through Carry (ROL, ROR, SAL, SAR, SHL, and SHR)
Register/Memory by 1
Register/Memory by CL
1 1 0 1 0 0 0 w mod TTT
1 1 0 1 0 0 1 w mod TTT
r/m
3/7**
3/7**
3/7**
0/2**
0/2**
0/2**
a
a
a
r/m
Register/Memory by Immediate Count 1 1 0 0 0 0 0 w mod TTT
r/m immed 8-bit data
Through Carry (RCL and RCR)
Register/Memory by 1
Register/Memory by CL
1 1 0 1 0 0 0 w mod TTT
1 1 0 1 0 0 1 w mod TTT
r/m
9/10**
9/10**
9/10**
0/2**
10/2**
0/2**
a
a
a
r/m
Register/Memory by Immediate Count 1 1 0 0 0 0 0 w mod TTT
r/m immed 8-bit data
T T T Instruction
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
ROL
ROR
RCL
RCR
SHL/SAL
SHR
SAR
e
SHLD
Shift Left Double
Register/Memory by Immediate
0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 mod reg
0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 mod reg
r/m immed 8-bit data
r/m
3/7**
3/7**
0/2**
0/2**
Register/Memory by CL
e
SHRD
Shift Right Double
Register/Memory by Immediate
Register/Memory by CL
0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 mod reg
0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 1 mod reg
r/m immed 8-bit data
r/m
3/7**
3/7**
0/2**
0/2**
e
AND
And
Register to Register
0 0 1 0 0 0 d w mod reg
r/m
2
76
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
LOGIC (Continued)
Register to Memory
0 0 1 0 0 0 0 w mod reg
0 0 1 0 0 0 1 w mod reg
r/m
r/m
7**
6*
2**
1*
a
a
a
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (Short Form)
1 0 0 0 0 0 0 w mod 1 0 0 r/m immediate data
0 0 1 0 0 1 0 w immediate data
2/7**
2
0/2**
e
TEST
And Function to Flags, No Result
Register/Memory and Register
1 0 0 0 0 1 0 w mod reg
r/m
2/5*
2/5*
0/1*
0/1*
a
a
Immediate Data and Register/Memory
1 1 1 1 0 1 1 w mod 0 0 0 r/m immediate data
1 0 1 0 1 0 0 w immediate data
Immediate Data and Accumulator
(Short Form)
2
e
OR
Or
Register to Register
0 0 0 0 1 0 d w mod reg
0 0 0 0 1 0 0 w mod reg
0 0 0 0 1 0 1 w mod reg
r/m
r/m
r/m
2
7**
6*
Register to Memory
2**
1*
a
a
a
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (Short Form)
1 0 0 0 0 0 0 w mod 0 0 1 r/m immediate data
0 0 0 0 1 1 0 w immediate data
2/7**
2
0/2**
e
XOR
Exclusive Or
Register to Register
0 0 1 1 0 0 d w mod reg
0 0 1 1 0 0 0 w mod reg
0 0 1 1 0 0 1 w mod reg
r/m
r/m
r/m
2
7**
6*
Register to Memory
2**
1*
a
a
a
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (Short Form)
1 0 0 0 0 0 0 w mod 1 1 0 r/m immediate data
0 0 1 1 0 1 0 w immediate data
2/7**
2
0/2**
e
NOT
Invert Register/Memory
1 1 1 1 0 1 1 w mod 0 1 0 r/m
2/6**
0/2**
2*
a
a
STRING MANIPULATION
e
CMPS
Compare Byte Word
1 0 1 0 0 1 1 w
0 1 1 0 1 1 0 w
10*
9**
29**
1**
1**
a,f,k
a,f,l
e
INS
Input Byte/Word from DX Port
e
e
e
e
e
LODS
MOVS
OUTS
SCAS
STOS
Load Byte/Word to AL/AX/EAX 1 0 1 0 1 1 0 w
5*
1*
a
a
Move Byte Word
1 0 1 0 0 1 0 w
0 1 1 0 1 1 1 w
1 0 1 0 1 1 1 w
7**
2**
8**
28**
1**
1**
a,f,k
a,f,l
Output Byte/Word to DX Port
Scan Byte Word
7*
1*
a
Store Byte/Word from
AL/AX/EX
1 0 1 0 1 0 1 w
1 1 0 1 0 1 1 1
4*
5*
1*
1*
a
a
e
XLAT
Translate String
REPEATED STRING MANIPULATION
Repeated by Count in CX or ECX
e
REPE CMPS
Compare String
a
(Find Non-Match)
1 1 1 1 0 0 1 1
1 0 1 0 0 1 1 w
5
9n**
2n**
a
77
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
REPEATED STRING MANIPULATION (Continued)
e
REPNE CMPS
Compare String
a
(Find Match)
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 1
1 1 1 1 0 0 1 1
1 1 1 1 0 0 1 1
1 1 1 1 0 0 1 1
1 0 1 0 0 1 1 w
0 1 1 0 1 1 0 w
1 0 1 0 1 1 0 w
1 0 1 0 0 1 0 w
0 1 1 0 1 1 1 w
5
9n**
6n*
6n*
2n**
a
a
7
1n*
1n*
a,f,k
a,f,l
e
REP INS
Input String
a
27
5
e
e
e
a
REP LODS
REP MOVS
REP OUTS
Load String
Move String
Output String
6n*
1n*
a
a
a
7
4n**
5n*
5n*
2n**
a
6
1n*
1n*
a,f,k
a,f,l
a
26
5
e
REPE SCAS
Scan String
a
(Find Non-AL/AX/EAX)
1 1 1 1 0 0 1 1
1 0 1 0 1 1 1 w
8n*
1n*
a
e
REPNE SCAS
Scan String
a
a
(Find AL/AX/EAX)
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 1
1 0 1 0 1 1 1 w
1 0 1 0 1 0 1 w
5
5
8n*
5n*
1n*
1n*
a
a
e
REP STOS
Store String
BIT MANIPULATION
e
e
a
a
BSF
BSR
Scan Bit Forward
Scan Bit Reverse
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 0 mod reg
1 0 1 1 1 1 0 1 mod reg
r/m
r/m
10
10
3n**
3n**
2n**
2n**
a
a
e
BT
Test Bit
Register/Memory, Immediate
Register/Memory, Register
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 0 0 r/m immed 8-bit data
1 0 1 0 0 0 1 1 mod reg r/m
3/6*
0/1*
0/1*
a
a
3/12*
e
BTC
Test Bit and Complement
Register/Memory, Immediate
Register/Memory, Register
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 1 1 r/m immed 8-bit data
1 0 1 1 1 0 1 1 mod reg r/m
6/8*
0/2*
0/2*
a
a
6/13*
e
BTR
Test Bit and Reset
Register/Memory, Immediate
Register/Memory, Register
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 1 0 r/m immed 8-bit data
1 0 1 1 0 0 1 1 mod reg r/m
6/8*
0/2*
0/2*
a
a
6/13*
e
BTS
Test Bit and Set
Register/Memory, Immediate
Register/Memory, Register
CONTROL TRANSFER
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 0 1 r/m immed 8-bit data
1 0 1 0 1 0 1 1 mod reg r/m
6/8*
0/2*
0/2*
a
a
6/13*
e
CALL
Call
a
Direct within Segment
1 1 1 0 1 0 0 0 full displacement
9
m*
2
j
Register/Memory
a
a
m
Indirect within Segment
1 1 1 1 1 1 1 1 mod 0 1 0 r/m
9
m/12
2/3
9
a, j
a
Direct Intersegment
1 0 0 1 1 0 1 0 unsigned full offset, selector
42
m
c, d, j
78
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
CONTROL TRANSFER (Continued)
(Direct Intersegment)
a
a
8x
Via Call Gate to Same Privilege Level
Via Call Gate to Different Privilege Level,
(No Parameters)
64
98
m
13
13
a,c,d,j
a,c,d,j
a,c,d,j
a,c,d,j
m
Via Call Gate to Different Privilege Level,
(x Parameters)
a
a
a
13 4x
106
m
From 386 Task to 386 TSS
Indirect Intersegment
392
124
10
a
a
1 1 1 1 1 1 1 1 mod 0 1 1
r/m
46
m
m
a,c,d,j
Via Call Gate to Same Privilege Level
Via Call Gate to Different Privilege Level,
(No Parameters)
68
14
14
a,c,d,j
a,c,d,j
a,c,d,j
a,c,d,j
a
102
m
Via Call Gate to Different Privilege Level,
(x Parameters)
a
a
a
14 4x
110
8x
399
m
From 386 Task to 386 TSS
130
e
JMP
Short
Direct within Segment
Unconditional Jump
a
a
1 1 1 0 1 0 1 1 8-bit displacement
1 1 1 0 1 0 0 1 full displacement
7
7
m
j
j
m
a
a
m
Register/Memory Indirect within Segment 1 1 1 1 1 1 1 1 mod 1 0 0
r/m
9
m/14
2/4
5
a,j
c,d,j
a
Direct Intersegment
1 1 1 0 1 0 1 0 unsigned full offset, selector
37
m
a
Via Call Gate to Same Privilege Level
From 386 Task to 386 TSS
53
m
9
a,c,d,j
a,c,d,j
395
124
a
a
Indirect Intersegment
1 1 1 1 1 1 1 1 mod 1 0 1
r/m
37
m
m
9
a,c,d,j
Via Call Gate to Same Privilege Level
From 386 Task to 386 TSS
59
13
a,c,d,j
a,c,d,j
401
124
79
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
CONTROL TRANSFER (Continued)
e
RET
Return from CALL:
a
a
a
a
Within Segment
1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0
1 1 0 0 1 0 1 1
1 1 0 0 1 0 1 0
12
12
36
36
m
m
m
m
2
2
4
4
a,j,p
a,j,p
Within Segment Adding Immediate to SP
Intersegment
16-bit displ
16-bit displ
a,c,d,j,p
a,c,d,j,p
Intersegment Adding Immediate to SP
to Different Privilege Level
Intersegment
80
80
4
4
c,d,j,p
c,d,j,p
Intersegment Adding Immediate to SP
CONDITIONAL JUMPS
NOTE: Times Are Jump ‘‘Taken or Not Taken’’
e
JO
Jump on Overflow
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 0 0 0
full displacement
full displacement
full displacement
full displacement
full displacement
full displacement
full displacement
e
JNO
Jump on Not Overflow
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 0 0 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 0 0 1
e
JB/JNAE
Jump on Below/Not Above or Equal
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 0 1 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 0 1 0
e
JNB/JAE
Jump on Not Below/Above or Equal
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 0 1 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 0 1 1
e
JE/JZ
Jump on Equal/Zero
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 1 0 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 1 0 0
e
JNE/JNZ
Jump on Not Equal/Not Zero
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 1 0 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 1 0 1
e
JBE/JNA
Jump on Below or Equal/Not Above
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 1 1 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 1 1 0
e
JNBE/JA
Jump on Not Below or Equal/Above
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 0 1 1 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 0 1 1 1
full displacement
full displacement
e
JS
Jump on Sign
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 0 0 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 0 0 0
80
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
CONDITIONAL JUMPS (Continued)
e
JNS
Jump on Not Sign
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 0 0 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 0 0 1
full displacement
full displacement
full displacement
full displacement
full displacement
full displacement
full displacement
e
JP/JPE
Jump on Parity/Parity Even
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 0 1 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 0 1 0
e
JNP/JPO
Jump on Not Parity/Parity Odd
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 0 1 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 0 1 1
e
JL/JNGE
Jump on Less/Not Greater or Equal
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 1 0 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 1 0 0
e
JNL/JGE
Jump on Not Less/Greater or Equal
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 1 0 1
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 1 0 1
e
JLE/JNG
Jump on Less or Equal/Not Greater
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 1 1 0
0 0 0 0 1 1 1 1
8-bit displ
7
7
m or 3
m or 3
j
j
1 0 0 0 1 1 1 0
e
JNLE/JG
Jump on Not Less or Equal/Greater
a
a
a
8-Bit Displacement
Full Displacement
0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 1 1 0 0 0 1 1
8-bit displ
1 0 0 0 1 1 1 1
8-bit displ
7
7
9
m or 3
m or 3
m or 5
j
j
j
e
JECXZ
Jump on ECX Zero
(Address Size Prefix Differentiates JCXZ from JECXZ)
e
a
a
a
LOOP
Loop ECX Times
1 1 1 0 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 0 0 0 0 0
8-bit displ
8-bit displ
8-bit displ
11
11
11
m
m
m
j
j
j
e
LOOPZ/LOOPE
Loop with
Zero/Equal
e
LOOPNZ/LOOPNE
Loop While
Not Zero
CONDITIONAL BYTE SET
NOTE: Times Are Register/Memory
e
SETO
Set Byte on Overflow
To Register/Memory
0 0 0 0 1 1 1 1
1 0 0 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 1 0 0 1 0
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
4/5*
4/5*
4/5*
0/1*
0/1*
0/1*
a
a
a
e
SETNO
Set Byte on Not Overflow
To Register/Memory
0 0 0 0 1 1 1 1
e
SETB/SETNAE
Set Byte on Below/Not Above or Equal
To Register/Memory
0 0 0 0 1 1 1 1
81
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
CONDITIONAL BYTE SET (Continued)
e
SETNB
Set Byte on Not Below/Above or Equal
To Register/Memory
0 0 0 0 1 1 1 1
1 0 0 1 0 0 1 1
1 0 0 1 0 1 0 0
1 0 0 1 0 1 0 1
1 0 0 1 0 1 1 0
1 0 0 1 0 1 1 1
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
1 0 0 1 1 0 1 0
1 0 0 1 1 0 1 1
1 0 0 1 1 1 0 0
0 1 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 1 1 1 1 1
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
mod 0 0 0 r/m
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
4/5*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
0/1*
a
a
a
a
a
a
a
a
a
a
a
a
a
e
SETE/SETZ
Set Byte on Equal/Zero
To Register/Memory
0 0 0 0 1 1 1 1
e
e
e
SETNE/SETNZ
SETBE/SETNA
SETNBE/SETA
Set Byte on Not Equal/Not Zero
To Register/Memory 0 0 0 0 1 1 1 1
Set Byte on Below or Equal/Not Above
To Register/Memory 0 0 0 0 1 1 1 1
Set Byte on Not Below or Equal/Above
To Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
e
SETS
Set Byte on Sign
To Register/Memory
e
SETNS
Set Byte on Not Sign
To Register/Memory
e
SETP/SETPE
Set Byte on Parity/Parity Even
To Register/Memory 0 0 0 0 1 1 1 1
e
SETNP/SETPO
SETL/SETNGE
SETNL/SETGE
SETLE/SETNG
SETNLE/SETG
Set Byte on Not Parity/Parity Odd
To Register/Memory 0 0 0 0 1 1 1 1
e
e
e
e
Set Byte on Less/Not Greater or Equal
To Register/Memory 0 0 0 0 1 1 1 1
Set Byte on Not Less/Greater or Equal
To Register/Memory 0 0 0 0 1 1 1 1
Set Byte on Less or Equal/Not Greater
To Register/Memory 0 0 0 0 1 1 1 1
Set Byte on Not Less or Equal/Greater
To Register/Memory
0 0 0 0 1 1 1 1
1 1 0 0 1 0 0 0
e
ENTER
Enter Procedure
Leave Procedure
16-bit displacement, 8-bit level
e
e
l
L
L
L
0
1
1
10
14
a
a
a
1
a b
17 8(n 1)
b
4(n 1)
e
LEAVE
1 1 0 0 1 0 0 1
6
a
82
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
INTERRUPT INSTRUCTIONS
e
INT
Interrupt:
Type Specified
1 1 0 0 1 1 0 1
type
Via Interrupt or Trap Gate
to Same Privilege Level
Via Interrupt or Trap Gate
to Different Privilege Level
71
14
14
c,d,j,p
c,d,j,p
c,d,j,p
111
467
From 386 Task to 386 TSS via Task Gate
140
Type 3
1 1 0 0 1 1 0 0
Via Interrupt or Trap Gate
to Same Privilege Level
Via Interrupt or Trap Gate
to Different Privilege Level
71
14
14
c,d,j,p
c,d,j,p
c,d,j,p
111
308
From 386 Task to 386 TSS via Task Gate
138
e
INTO
Interrupt 4 if Overflow Flag Set
1 1 0 0 1 1 1 0
e
If OF
1:
0
3
e
If OF
Via Interrupt or Trap Gate
to Same Privilege Level
Via Interrupt or Trap Gate
to Different Privilege Level
71
14
14
c,d,j,p
c,d,j,p
c,d,j,p
111
413
From 386 Task to 386 TSS via Task Gate
138
83
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
Of Data
Cycles
Clock
Counts
Instruction
Format
Notes
INTERRUPT INSTRUCTIONS (Continued)
e
Bound
Out of Range
0 1 1 0 0 0 1 0
mod reg r/m
Interrupt 5 if Detect Value
if in Range
10
0
a,c,d,j,o,p
if Out of Range:
Via Interrupt or Trap Gate
to Same Privilege Level
Via Interrupt or Trap Gate
to Different Privilege Level
71
14
14
c,d,j,p
c,d,j,p
c,d,j,p
111
398
From 386 Task to 386 TSS via Task Gate
138
INTERRUPT RETURN
e
IRET
Interrupt Return
1 1 0 0 1 1 1 1
To the Same Privilege Level (within Task)
To Different Privilege Level (within Task)
42
86
5
5
a,c,d,j,p
a,c,d,j,p
From 386 Task to 386 TSS
328
138
c,d,j,p
PROCESSOR CONTROL
e
HLT
HALT
1 1 1 1 0 1 0 0
5
b
e
MOV
Move to and from Control/Debug/Test Registers
CR0
from register
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 0
0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1
0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1
1 1 eee reg
1 1 eee reg
1 1 eee reg
1 1 eee reg
1 1 eee reg
1 1 eee reg
10
6
b
b
b
b
b
b
Register from CR0
DR0–3 from Register
DR6–7 from Register
Register from DR6–7
Register from DR0–3
22
16
14
22
e
NOP No Operation
1 0 0 1 0 0 0 0
1 0 0 1 1 0 1 1
3
6
e
WAIT Wait until BUSY Pin is Negated
84
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
PROCESSOR EXTENSION INSTRUCTIONS
Processor Extension Escape
1 1 0 1 1 T T T mod L L L r/m
See 80387SX Data Sheet
a
TTT and LLL bits are opcode
information for coprocessor.
PREFIX BYTES
Address Size Prefix
0 1 1 0 0 1 1 1
1 1 1 1 0 0 0 0
0 1 1 0 0 1 1 0
0
0
0
e
LOCK
Bus Lock Prefix
f
Operand Size Prefix
Segment Override Prefix
CS:
0 0 1 0 1 1 1 0
0 0 1 1 1 1 1 0
0 0 1 0 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0
0
0
0
0
0
DS:
ES:
FS:
GS:
SS:
PROTECTION CONTROL
e
e
e
ARPL
Adjust Requested Privilege Level
From Register/Memory
0 1 1 0 0 0 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
mod reg
r/m
20/21**
17/18*
13**
2**
1*
a
a,c,i,p
a,e
e
LAR
Load Access Rights
From Register/Memory
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1
mod reg
r/m
LGDT
Load Global Descriptor
Table Register
mod 0 1 0 r/m
mod 0 1 1 r/m
3*
e
LIDT
Load Interrupt Descriptor
Table Register
13**
3*
a,e
LLDT
Load Local Descriptor
Table Register to
Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 1
mod 0 1 0 r/m
mod 1 1 0 r/m
24/28*
10/13*
5*
1*
a,c,e,p
a,e
e
LMSW Load Machine Status Word
From Register/Memory
e
e
LSL
LTR
Load Segment Limit
From Register/Memory
mod reg
r/m
Byte-Granular Limit
Page-Granular Limit
24/27*
29/32*
2*
2*
a,c,i,p
a,c,i,p
Load Task Register
From Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1
mod 0 0 1 r/m
mod 0 0 0 r/m
mod 0 0 1 r/m
27/31*
11*
4*
3*
3*
a,c,e,p
e
SGDT Store Global Descriptor
Table Register
a
a
e
SIDT
Store Interrupt Descriptor
Table Register
11*
e
SLDT
Store Local Descriptor Table Register
To Register/Memory 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 0 0 0 r/m
2/2*
4*
a
85
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary (Continued)
Number
of Data
Cycles
Clock
Counts
Instruction
Format
Notes
PROTECTION CONTROL (Continued)
e
SMSW
Store Machine
Status Word
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
mod 1 0 0 r/m
mod 0 0 1 r/m
2/2*
2/2*
1*
1*
a, c
a
e
STR
Store Task Register
To Register/Memory
e
VERR
VERW
Verify Read Accesss
Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
mod 1 0 0 r/m
mod 1 0 1 r/m
10/11**
15/16**
2**
2**
a,c,i,p
a,c,i,p
e
Verify Write Accesss
NOTES:
a. Exception 13 fault (general violation) will occur if the memory operand in CS, DS, ES, FS or GS cannot be used due to
either a segment limit violation or access rights violation. If a stack limit is violated, and exception 12 (stack segment limit
violation or not present) occurs.
b. For segment load operations, the CPL, RPL and DPL must agree with the privilege rules to avoid an exception 13 fault
(general protection violation). The segments’s descriptor must indicate ‘‘present’’ or exception 11 (CS, DS, ES, FS, GS not
present). If the SS register is loaded and a stack segment not present is detected, an exception 12 (stack segment limit
violation or not present occurs).
c. All segment descriptor accesses in the GDT or LDT made by this instruction will automatically assert LOCK to maintain
descriptor integrity in multiprocessor systems.
d. JMP, CALL, INT, RET and IRET instructions referring to another code segment will cause an exception 13 (general
protection violation) if an applicable privilege rule is volated.
e. An exception 13 fault occurs if CPL is greater than 0.
f. An exception 13 fault occurs if CPL is greater than IOPL.
g. The IF bit of the flag register is not updated if CPL is greater than IOPL. The IOPL field of the flag register is updated only
e
if CPL
0.
h. Any violation of privelege rules as applied to the selector operand does not cause a protection exception; rather, the zero
flag is cleared.
i. If the coprocessor’s memory operand violates a segment limit or segment access rights, an exception 13 fault (general
protection exception) will occur before the ESC instruction is executed. An exception 12 fault (stack segment limit violation
or no present) will occur if the stack limit is violated by the operand’s starting address.
j. The destination of a JMP, CALL, INT, RET or IRET must be in the defined limit of a code segment or an exception 13 fault
(general protection violation) will occur.
s
l
k. If CPL
l. If CPL
IOPL
IOPL
m. LOCK is automatically asserted, regardless of the presence or absence of the LOCK prefix.
n. The 80376 uses an early-out multiply algorithm. The actual number of clocks depends on the position of the most signifi-
cant bit in the operand (multiplier). Clock counts given are minimum to maximum. To calculate actual clocks use the follow-
ing formula:
k
e
l
0 then 12 clocks (where m is the multiplier)
e
a
[
0 then max ( log
]
, 3)
Actual Clock
if m
if m
m
9 clocks:
2
l
l
o. An exception may occur, depending on the value of the operand.
p. LOCK is asserted during descriptor table accesses.
86
376 EMBEDDED PROCESSOR
encodings of the mod r/m byte indicate a second
addressing byte, the scale-index-base byte, follows
the mod r/m byte to fully specify the addressing
mode.
8.2 INSTRUCTION ENCODING
Overview
All instruction encodings are subsets of the general
instruction format shown in Figure 8.1. Instructions
consist of one or two primary opcode bytes, possibly
an address specifier consisting of the ‘‘mod r/m’’
byte and ‘‘scaled index’’ byte, a displacement if re-
quired, and an immediate data field if required.
Addressing modes can include a displacement im-
mediately following the mod r/m byte, or scaled in-
dex byte. If a displacement is present, the possible
sizes are 8, 16 or 32 bits.
If the instruction specifies an immediate operand,
the immediate operand follows any displacement
bytes. The immediate operand, if specified, is always
the last field of the instruction.
Within the primary opcode or opcodes, smaller en-
coding fields may be defined. These fields vary ac-
cording to the class of operation. The fields define
such information as direction of the operation, size
of the displacements, register encoding, or sign ex-
tension.
Figure 8.1 illustrates several of the fields that can
appear in an instruction, such as the mod field and
the r/m field, but the Figure does not show all fields.
Several smaller fields also appear in certain instruc-
tions, sometimes within the opcode bytes them-
selves. Table 8.2 is a complete list of all fields ap-
pearing in the 80376 instruction set. Further ahead,
following Table 8.2, are detailed tables for each
field.
Almost all instructions referring to an operand in
memory have an addressing mode byte following
the primary opcode byte(s). This byte, the mod r/m
byte, specifies the address mode to be used. Certain
T T T T T T T T T T T T T T T T mod T T T r/m ss index base d32 16
l
8
none data32 16
l
8
none
l
l
l
l
7
0 7
ä
0
7 6 5 3 2 0
ä
7 6 5 3 2 0
ä
X
Y X
Y X
YX
ä
Y X
ä
Y
opcode
‘‘mod r/m’’
byte
‘‘s-i-b’’
byte
address
displacement
(4, 2, 1 bytes
or none)
immediate
data
(one or two bytes)
(T represents an
opcode bit.)
X
ä
Y
(4, 2, 1 bytes
or none)
register and address
mode specifier
Figure 8.1. General Instruction Format
Table 8.2. Fields within 80376 Instructions
Description
Field Name
Number of Bits
w
Specifies if Data is Byte or Full Size (Full Size is either 16 or 32 Bits
Specifies Direction of Data Operation
1
d
1
s
reg
Specifies if an Immediate Data Field Must be Sign-Extended
General Register Specifier
Address Mode Specifier (Effective Address can be a General Register)
1
3
2 for mod;
3 for r/m
mod r/m
ss
Scale Factor for Scaled Index Address Mode
General Register to be used as Index Register
General Register to be used as Base Register
Segment Register Specifier for CS, SS, DS, ES
Segment Register Specifier for CS, SS, DS, ES, FS, GS
For Conditional Instructions, Specifies a Condition Asserted
or a Condition Negated
2
3
3
2
3
index
base
sreg2
sreg3
tttn
4
Note: Table 8.1 shows encoding of individual instructions.
87
376 EMBEDDED PROCESSOR
Encoding of reg Field When w Field
is not Present in Instruction
16-Bit Extensions of the
Instruction Set
Register Selected
Two prefixes, the operand size prefix (66H) and the
effective address size prefix (67H), allow overriding
individually the default selection of operand size and
effective address size. These prefixes may precede
any opcode bytes and affect only the instruction
they precede. If necessary, one or both of the prefix-
es may be placed before the opcode bytes. The
presence of the operand size prefix (66H) and the
effective address prefix will allow 16-bit data opera-
tion and 16-bit effective address calculations.
Register Selected
with 66H Prefix
reg Field
During 32-Bit
Data Operations
000
001
010
011
100
101
110
111
AX
CX
DX
BX
SP
BP
SI
EAX
ECX
EDX
EBX
ESP
EBP
ESI
For instructions with more than one prefix, the order
of prefixes is unimportant.
DI
EDI
Encoding of reg Field When w Field
is Present in Instruction
Unless specified otherwise, instructions with 8-bit
and 16-bit operands do not affect the contents of
the high-order bits of the extended registers.
Register Specified by reg Field
with 66H Prefix
Function of w Field
reg
Encoding of Instruction Fields
e
e
1)
(when w
0)
(when w
Within the instruction are several fields indicating
register selection, addressing mode and so on.
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
ENCODING OF OPERAND LENGTH (w) FIELD
For any given instruction performing a data opera-
tion, the instruction will execute as a 32-bit opera-
tion. Within the constraints of the operation size, the
w field encodes the operand size as either one byte
or the full operation size, as shown in the table be-
low.
DI
Register Specified by reg Field
without 66H Prefix
Operand Size
Normal
w Field
with 66H Prefix
Operand Size
Function of w Field
0
1
8 Bits
16 Bits
8 Bits
32 Bits
reg
e
e
1)
(when w
0)
(when w
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
ENCODING OF THE GENERAL
REGISTER (reg) FIELD
The general register is specified by the reg field,
which may appear in the primary opcode bytes, or as
the reg field of the ‘‘mod r/m’’ byte, or as the r/m
field of the ‘‘mod r/m’’ byte.
EDI
88
376 EMBEDDED PROCESSOR
ENCODING OF THE SEGMENT
REGISTER (sreg) FIELD
ENCODING OF ADDRESS MODE
Except for special instructions, such as PUSH or
POP, where the addressing mode is pre-determined,
the addressing mode for the current instruction is
specified by addressing bytes following the primary
opcode. The primary addressing byte is the ‘‘mod
r/m’’ byte, and a second byte of addressing informa-
tion, the ‘‘s-i-b’’ (scale-index-base) byte, can be
specified.
The sreg field in certain instructions is a 2-bit field
allowing one of the CS, DS, ES or SS segment regis-
ters to be specified. The sreg field in other instruc-
tions is a 3-bit field, allowing the FS and GS segment
registers to be specified also.
2-Bit sreg2 Field
Segment
The s-i-b byte (scale-index-base byte) is specified
when using 32-bit addressing mode and the ‘‘mod
2-Bit
Register
sreg2 Field
Selected
e
e
r/m’’ byte has r/m
100 and mod
00, 01 or 10.
When the sib byte is present, the 32-bit addressing
mode is a function of the mod, ss, index, and base
fields.
00
01
10
11
ES
CS
SS
DS
The primary addressing byte, the ‘‘mod r/m’’ byte,
also contains three bits (shown as TTT in Figure 8.1)
sometimes used as an extension of the primary op-
code. The three bits, however, may also be used as
a register field (reg).
3-Bit sreg3 Field
Segment
Register
Selected
3-Bit
sreg3 Field
When calculating an effective address, either 16-bit
addressing or 32-bit addressing is used. 16-bit ad-
dressing uses 16-bit address components to calcu-
late the effective address while 32-bit addressing
uses 32-bit address components to calculate the ef-
fective address. When 16-bit addressing is used, the
‘‘mod r/m’’ byte is interpreted as a 16-bit addressing
mode specifier. When 32-bit addressing is used, the
‘‘mod r/m’’ byte is interpreted as a 32-bit addressing
mode specifier.
000
001
010
011
100
101
110
111
ES
CS
SS
DS
FS
GS
do not use
do not use
Tables on the following three pages define all en-
codings of all 16-bit addressing modes and 32-bit
addressing modes.
89
376 EMBEDDED PROCESSOR
Encoding of Normal Address Mode with ‘‘mod r/m’’ byte (no ‘‘s-i-b’’ byte present):
mod r/m
Effective Address
mod r/m
Effective Address
a
[
]
]
]
]
[
[
[
]
]
]
]
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
DS: EAX
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
DS: EAX d32
a
[
DS: ECX
DS: ECX d32
a
[
DS: EDX
DS: EDX d32
a
[
DS: EBX d32
[
DS: EBX
s-i-b is present
DS:d32
s-i-b is present
a
[
[
[
]
SS: EBP d32
a
[
]
]
]
]
DS: ESI
DS: ESI d32
a
DS: EDI d32
[
DS: EDI
a
[
[
[
[
]
]
]
]
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
DS: EAX d8
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
a
DS: ECX d8
a
DS: EDX d8
a
DS: EBX d8
s-i-b is present
a
[
[
[
]
SS: EBP d8
a
]
]
DS: ESI d8
a
DS: EDI d8
Register Specified by reg or r/m
during Normal Data Operations:
function of w field
mod r/m
e
(when w 0)
e
(when w 1)
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
AL
CL
DL
BL
AH
CH
DH
BH
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
Register Specified by reg or r/m
during 16-Bit Data Operations: (66H Prefix)
function of w field
mod r/m
e
(when w 0)
e
(when w 1)
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
AL
CL
DL
BL
AH
CH
DH
BH
AX
CX
DX
BX
SP
BP
SI
DI
90
376 EMBEDDED PROCESSOR
Encoding of 16-bit Address Mode with ‘‘mod r/m’’ Byte Using 67H Prefix
mod r/m
Effective Address
mod r/m
Effective Address
a
a
a
a
a
a
]
]
]
]
[
[
[
[
]
]
]
]
[
[
[
[
[
[
[
[
]
]
]
]
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
DS: BX SI
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
DS: BX SI d16
a
a
DS: BX DI
DS: BX DI d16
a
a
SS: BP SI
SS: BP SI d16
a
SS: BP DI
a
SS: BP DI d16
a
[
]
]
DS: SI
DS: SI d16
a
[
DS: DI
DS:d16
[
DS: BX
DS: DI d16
a
SS: BP d16
a
DS: BX d16
]
a
a
a
a
a
]
]
]
]
[
[
[
[
[
[
[
[
]
]
]
]
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
DS: BX SI d8
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
registerÐsee below
a
DS: BX DI d8
a
SS: BP SI d8
a
SS: BP DI d8
a
DS: SI d8
a
DS: DI d8
a
SS: BP d8
a
DS: BX d8
91
376 EMBEDDED PROCESSOR
Encoding of 32-bit Address Mode (‘‘mod r/m’’ byte and ‘‘s-i-b’’ byte present):
mod base
Effective Address
ss
Scale Factor
a
[
[
[
[
[
[
[
[
]
]
]
]
]
00 000
00 001
00 010
00 011
00 100
00 101
00 110
00 111
DS: EAX (scaled index)
00
01
10
11
x1
x2
x4
x8
a
DS: ECX (scaled index)
a
DS: EDX (scaled index)
a
DS: EBX (scaled index)
a
SS: ESP (scaled index)
a
]
DS: d32 (scaled index)
index
Index Register
a
]
]
DS: ESI (scaled index)
a
DS: EDI (scaled index)
000
001
010
011
100
101
110
111
EAX
ECX
a a
[ ]
DS: EAX (scaled index) d8
01 000
01 001
01 010
01 011
01 100
01 101
01 110
01 111
EDX
EBX
a
a
a
a
a
a
a
[
[
[
[
[
[
[
]
]
]
]
]
DS: ECX (scaled index) d8
a
DS: EDX (scaled index) d8
no index reg**
EBP
ESI
a
DS: EBX (scaled index) d8
a
SS: ESP (scaled index) d8
a
SS: EBP (scaled index) d8
EDI
a
]
]
DS: ESI (scaled index) d8
a
a
DS: EDI (scaled index) d8
**IMPORTANT NOTE:
When index field is 100, indicating ‘‘no index register,’’ then
ss field MUST equal 00. If index is 100 and ss does not
equal 00, the effective address is undefined.
a a
[ ]
DS: EAX (scaled index) d32
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
a
a
a
a
a
a
a
[
[
[
[
[
[
[
]
]
]
]
]
DS: ECX (scaled index) d32
a
DS: EDX (scaled index) d32
a
DS: EBX (scaled index) d32
a
SS: ESP (scaled index) d32
a
SS: EBP (scaled index) d32
a
]
]
DS: ESI (scaled index) d32
a
a
DS: EDI (scaled index) d32
NOTE:
Mod field in ‘‘mod r/m’’ byte; ss, index, base fields in
‘‘s-i-b’’ byte.
92
376 EMBEDDED PROCESSOR
ENCODING OF OPERATION
DIRECTION (d) FIELD
Mnemonic
Condition
tttn
O
NO
B/NAE
NB/AE
E/Z
NE/NZ
BE/NA
NBE/A
S
Overflow
No Overflow
Below/Not Above or Equal
Not Below/Above or Equal
Equal/Zero
Not Equal/Not Zero
Below or Equal/Not Above
Not Below or Equal/Above
Sign
Not Sign
Parity/Parity Even
Not Parity/Parity Odd
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
In many two-operand instructions the d field is pres-
ent to indicate which operand is considered the
source and which is the destination.
d
Direction of Operation
k
0
Register/Memory - - Register
‘‘reg’’ Field Indicates Source Operand;
‘‘mod r/m’’ or ‘‘mod ss index base’’ Indicates
Destination Operand
NS
k
P/PE
NP/PO
L/NGE
NL/GE
LE/NG
NLE/G
1
Register - - Register/Memory
‘‘reg’’ Field Indicates Destination Operand;
‘‘mod r/m’’ or ‘‘mod ss index base’’ Indicates
Source Operand
Less Than/Not Greater or Equal 1100
Not Less Than/Greater or Equal 1101
Less Than or Equal/Greater Than 1110
Not Less or Equal/Greater Than 1111
ENCODING OF SIGN-EXTEND (s) FIELD
The s field occurs primarily to instructions with im-
mediate data fields. The s field has an effect only if
the size of the immediate data is 8 bits and is being
placed in a 16-bit or 32-bit destination.
ENCODING OF CONTROL OR DEBUG
REGISTER (eee) FIELD
For the loading and storing of the Control and Debug
registers.
Effect on
Immediate Data8
Effect on
Immediate Data 16 32
s
l
When Interpreted as Control Register Field
0 None
None
eee Code
Reg Name
000
010
011
CR0
Reserved
Reserved
1 Sign-Extend Data8 to Fill
16-Bit or 32-Bit Destination
None
Do not use any other encoding
ENCODING OF CONDITIONAL
TEST (tttn) FIELD
When Interpreted as Debug Register Field
eee Code
Reg Name
For the conditional instructions (conditional jumps
and set on condition), tttn is encoded with n indicat-
000
001
010
011
110
111
DR0
DR1
DR2
DR3
DR6
DR7
e
e
ing to use the condition (n 0) or its negation (n 1),
and ttt giving the condition to test.
Do not use any other encoding
93
376 EMBEDDED PROCESSOR
9.0 REVISION HISTORY
The sections significantly revised since version -003 are:
Section 1.0
Section 4.4
Section 4.6
Section 5.0
Added FLT pin.
Added description of FLOAT operation and ONCE Mode. Figure 4.20 is new.
Added revision identifier information for change to CHMOS IV manufacturing process.
Both packages now specified for 0 C–115 C case temperature operation. Thermal resist-
ance values changed.
I Max. specifications changed from 400 mA (cold) and 360 mA (hot) to 275 mA (cold, 16
CC
§
§
Section 6.3
Section 6.4
MHz) and 305 mA (cold, 20 MHz).
HLDA Valid Delay, t , min. changed from 6 ns to 4 ns. Added 20 MHz A.C. specifications in
14
Table 6.5. Replaced Capacitive Derating Curves in Figures 6.8–6.10 to reflect new manufac-
turing process. Replaced I vs. Frequency data (Figure 6.11) to reflect new specifications.
CC
The sections significantly revised since version -002 are:
Section 1.0 Modified table 1.1. to list pins in alphabetical order.
The sections significantly revised since version -001 are:
Section 2.0
Section 2.1
Section 2.1
Figure 2.0 was updated to show the 16-bit registers SI, DI, BP and SP.
Figure 2.2 was updated to show the correct bit polarity for bit 4 in the CR0 register.
Tables 2.1 and 2.2 were updated to include additional information on the EFLAGs and CR0
registers.
Section 2.3
Section 2.6
Figure 2.3 was updated to more accurately reflect the addressing mechanism of the 80376.
In the subsection Maskable Interrupt a paragraph was added to describe the effect of
interrupt gates on the IF EFLAGs bit.
Section 2.8
Table 2.7 was updated to reflect the correct power up condition of the CR0 register.
Section 2.10
Figure 2.6 was updated to show the correct bit positions of the BT, BS and BD bits in the
DR6 register.
Section 3.0
Section 3.2
Figure 3.1 was updated to clearly show the address calculation process.
The subsection DESCRIPTORS was elaborated upon to clearly define the relationship be-
tween the linear address space and physical address space of the 80376.
Section 3.2
Section 3.3
Figures 3.3 and 3.4 were updated to show the AVL bit field.
The last sentence in the first paragraph of subsection PROTECTION AND I/O PERMIS-
SION BIT MAP was deleted. This was an incorrect statement.
Section 4.1
In the Subsection ADDRESS BUS (BHE, BLE, A –A last sentence in the first paragraph
23 1
was updated to reflect the numerics operand addresses as 8000FCH and 8000FEH. Be-
cause the 80376 sometimes does a double word I/O access a second access to 8000FEH
can be seen.
Section 4.1
Section 4.2
The Subsection Hold Lantencies was updated to describe how 32-bit and unaligned ac-
cesses are internally locked but do not assert the LOCK signal.
Table 4.6 was updated to show the correct active data bits during a BLE assertion.
94
376 EMBEDDED PROCESSOR
9.0 REVISION HISTORY (Continued)
Section 4.4
This section was updated to correctly reflect the pipelining of the address and status of the
80376 as opposed to ‘‘Address Pipelining’’ which occurs on processors such as the 80286.
Section 4.6
Section 4.7
Table 4.7 was updated to show the correct Revision number, 05H.
Table 4.8 was updated to show the numerics operand register 8000FEH. This address is
seen when the 80376 does a DWORD operation to the port address 8000FCH.
Section 5.0
Section 6.2
In the first paragraph the case temperatures were updated to reflect the 0 C–115 C for the
§
§
ceramic package and 0 C–110 C for the plastic package.
§
§
Table 6.2 was updated to reflect the Case Temperature under Bias specification of 65 C–
b
§
120 C.
§
Figure 6.8 vertical axis was updated to reflect ‘‘Output Valid Delay (ns)’’.
Section 6.4
Section 6.4
Section 8.1
Section 8.2
Figure 6.11 was updated to show typical I
vs Frequency for the 80376.
CC
The clock counts and opcodes for various instructions were updated to their correct values.
The section INSTRUCTION ENCODING was appended to the data sheet.
95
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