AC80566UC005DE_技术文档

Intel^®Atom™ Processor Z5xx^∆

Series

Datasheet

— For the Intel^®Atom™ Processor Z550, Z540^∆, Z530^∆, Z520^∆,

Z515^∆, Z510^∆, and Z500^∆on 45 nm process technology

March 2009

Document Number: 319535-002US

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family, not across different processor families. See http://www.intel.com/products/processor_number for details.

Intel^®Virtualization Technology (Intel^®VT) requires a computer system with an enabled Intel^®processor, BIOS, virtual machine

monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will

vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be

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Intel^®, Intel^®Atom, Intel^®Centrino^®Atom^TM, Intel SpeedStep^®, Intel^®Virtualization Technology (Intel^®VT), Intel^®Thermal

Monitor, Intel^®Streaming SIMD Extensions 2 and 3 (Intel SSE2 and Intel SSE3), Intel^®Burst Performance Technology (Intel^®

BPT), Intel^®Hyper-Threading Technology (Intel^®HT Technology), and the Intel logo are trademarks of Intel Corporation in the

U.S. and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction.....................................................................................................7

1.1

1.2

1.3

Major Features.......................................................................................7

Terminology ..........................................................................................8

References ..........................................................................................10

2

Low Power Features ........................................................................................11

2.1

Clock Control and Low-Power States .......................................................11

2.1.1 Package/Core Low-Power State Descriptions ...............................13

2.2

2.3

2.4

2.5

Dynamic Cache Sizing...........................................................................20

Enhanced Intel SpeedStep® Technology..................................................21

Enhanced Low-Power States ..................................................................22

FSB Low Power Enhancements ...............................................................23

2.5.1

2.5.2

Split V_TT.................................................................................23

CMOS Front Side Bus...............................................................23

2.6

Intel® Burst Performance Technology (Intel® BPT)...................................24

3

Electrical Specifications....................................................................................25

3.1

3.2

3.3

FSB, GTLREF, and CMREF......................................................................25

Power and Ground Pins .........................................................................25

Decoupling Guidelines...........................................................................26

3.3.1

3.3.2

V_CCDecoupling........................................................................26

FSB AGTL+ Decoupling ............................................................26

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

3.13

FSB Clock (BCLK[1:0]) and Processor Clocking .........................................26

Voltage Identification and Power Sequencing............................................26

Catastrophic Thermal Protection.............................................................29

Reserved and Unused Pins.....................................................................29

FSB Frequency Select Signals (BSEL[2:0])...............................................29

FSB Signal Groups................................................................................29

CMOS Asynchronous Signals..................................................................31

Maximum Ratings.................................................................................31

Processor DC Specifications ...................................................................32

AGTL+ FSB Specifications......................................................................43

4

5

Package Mechanical Specifications and Pin Information.........................................45

4.1

Package Mechanical Specifications ..........................................................45

4.1.1 Processor Package Weight ........................................................45

4.2

4.3

Processor Pinout Assignment..................................................................47

Signal Description ................................................................................54

Thermal Specifications and Design Considerations ...............................................63

5.1 Thermal Specifications ..........................................................................66

5.1.1

5.1.2

5.1.3

Thermal Diode ........................................................................66

Intel® Thermal Monitor............................................................68

Digital Thermal Sensor.............................................................70

Datasheet

3

5.1.4

5.1.5

Out of Specification Detection ...................................................70

PROCHOT# Signal Pin..............................................................70

Figures

Figure 1. Thread Low-Power States....................................................................12

Figure 2. Package Low-Power States..................................................................12

Figure 3. Deep Power Down Technology Entry Sequence.......................................18

Figure 4. Deep Power Down Technology Exit Sequence.........................................18

Figure 5. Exit Latency Table..............................................................................19

Figure 6. Active V_ccand I_ccLoadline ...................................................................38

Figure 7. Deeper Sleep V_CCand I_CCLoadline........................................................39

Figure 8. Package Mechanical Drawing...............................................................46

Figure 9. Pinout Diagram (Top View, Left Side) ...................................................47

Figure 10. Pinout Diagram (Top View, Right Side)................................................47

Tables

Table 1. References.........................................................................................10

Table 2. Coordination of Thread Low-Power States at the Package/Core Level..........13

Table 3. Voltage Identification Definition ............................................................26

Table 4. BSEL[2:0] Encoding for BCLK Frequency ................................................29

Table 5. FSB Pin Groups...................................................................................30

Table 6. Processor Absolute Maximum Ratings ....................................................32

Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor Z550,

Z540, Z530, Z520, and Z510...............................................................33

Table 8. Voltage and Current Specifications for the Intel® Atom™ Processor Z500 ...35

Table 9. Voltage and Current Specifications for the Intel® Atom™ Processor Z515 ...36

Table 10. FSB Differential BCLK Specifications.....................................................40

Table 11. AGTL+/CMOS Signal Group DC Specifications........................................41

Table 12. Legacy CMOS Signal Group DC Specifications........................................42

Table 13. Open Drain Signal Group DC Specifications...........................................42

Table 14. Pinout Arranged by Signal Name .........................................................49

Table 15. Signal Description .............................................................................54

Table 16. Power Specifications for Intel® Atom™ Processors Z550, Z540, Z530,

Z520, and Z510 ...............................................................................64

Table 17. Power Specifications for Intel^®Atom™ Processors Z515 and Z500............65

Table 18. Thermal Diode Interface.....................................................................67

Table 19. Thermal Diode Parameters Using Transistor Model .................................67

4

Datasheet

Revision History

Document

Number

Revision

Number

Description

Revision Date

319535

001

002

• Initial release.

April 2008

• Updated information about Intel^®Atom processors

March 2009

Z515 and Z550.

• Added Intel^®Atom processor Z550 specifications to

Table 7

• Changed VccBoot value to VccLFM in Table 7 and

Table 8.

• Added new Table 9, Voltage and Current

Specifications for Intel^®Atom processor Z515.

• Removed EMTTM references as it is not a supported

feature.

§

Datasheet

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6

Datasheet

Introduction

1 Introduction

The Intel^®Atom™ processor Z5xx series is built on a new 45-nanometer Hi-k low

power micro-architecture and 45 nm process technology—the first generation of low-

power IA-32 micro-architecture specially designed for the new class of Mobile Internet

Devices (MIDs). The Intel Atom processor Z5xx series supports the Intel® System

Controller Hub (Intel® SCH), a single-chip component designed for low-power

operation.

This document contains electrical, mechanical, and thermal specifications for Intel

Atom processors Z550, Z540, Z530, Z520, Z515, Z510, and Z500.

Note: In this document, Intel Atom processor Z5xx series refers to the Intel Atom

processors Z550, Z540, Z530, Z520, Z515, Z510, and Z500.

Note: In this document, the Intel Atom processor Z5xx series is referred to as “processor”.

The Intel® System Controller Hub (Intel® SCH) is referred to as the “Intel® SCH”.

1.1

Major Features

The following list provides some of the key features on this processor:

• New single-core processor for mobile devices offering enhanced performance

• On die, primary 32-kB instructions cache and 24-kB write-back data cache

• 100-MHz and 133-MHz Source-Synchronous front side bus (FSB)

⎯ 100 MHz: Intel Atom processor Z515, Z510, and Z500

⎯ 133 MHz: Intel Atom processor Z550, Z540, Z530, and Z520.

• Supports Hyper-Threading Technology 2-threads

• On die 512-kB, 8-way L2 cache

• Support for IA 32-bit architecture

• Intel® Virtualization Technology (Intel® VT)

• Intel® Streaming SIMD Extensions 2 and 3 (Intel SSE2 and Intel SSE3) and

Supplemental Streaming SIMD Extensions 3 (SSSE3) support

• Supports new CMOS FSB signaling for reduced power

• Micro-FCBGA8 packaging technologies

• Thermal management support using TM1 and TM2

• On die Digital Thermal Sensor (DTS) for thermal management support using

Thermal Monitor (TM1 and TM2)

• FSB Lane Reversal for flexible routing

• Supports C0/C1(e)/C2(e)/C4(e) power states

• Intel Deep Power Down Technology (C6)

• L2 Dynamic Cache Sizing

• New Split-V_TTsupport for lowest processor power state

• Advanced power management features including Enhanced Intel SpeedStep®

Technology

• Execute Disable Bit support for enhanced security

• Intel® Burst Performance Technology (Intel® BPT) (Intel Atom processor Z515

only)

Datasheet

7

Introduction

1.2

Terminology

Term

Definition

#

A “#” symbol after a signal name refers to an active low signal, indicating

a signal is in the active state when driven to a low level. For example,

when RESET# is low, a reset has been requested. Conversely, when NMI

is high, a non-maskable interrupt has occurred. In the case of signals

where the name does not imply an active state but describes part of a

binary sequence (such as address or data), the “#” symbol implies that

the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’,

and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level,

L= Low logic level).

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the Intel® SCH chipset components).

AGTL+

Advanced Gunning Transceiver Logic is used to refer to Assisted GTL+

signaling technology on some Intel processors.

Intel® Burst

Performance

Technology

(Intel® BPT)

Enables on-demand performance, without impacting or raising MID

thermal design point.

BFM

Burst Frequency Mode

CMOS

Complementary Metal-Oxide Semiconductor

Storage

Conditions

Refers to a non-operational state—the processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor landings should not

be connected to any supply voltages, or have any I/Os biased, or receive

any clocks. Upon exposure to “free air” (that is, unsealed packaging or a

device removed from packaging material) the processor must be handled

in accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Enhanced Intel

SpeedStep®

Technology

Technology that provides power management capabilities to low power

devices.

Processor Core

Processor core die with integrated L1 and L2 cache. All AC timing and

signal integrity specifications are at the pads of the processor core.

Intel

Virtualization

Technology

Processor virtualization which when used in conjunction with Virtual

Machine Monitor software enables multiple, robust independent software

environments inside a single platform.

TDP

Thermal Design Power

V_CC

The processor core power supply.

Voltage Regulator

VR

V_SS

The processor ground

V_CCHFM

V_CCLFM

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

8

Datasheet

Introduction

Term

Definition

Default V_CCVoltage for Initial Power Up

V_{CC BOOT}

,

V_CCP

AGTL+ Termination Voltage

PLL Supply voltage

V_CCPC6

V_CCA

V_CCDPPWDN

V_CCDPRSLP

V_CCF

V_CCat Deep Power Down Technology (C6)

V_CCat Deeper Sleep (C4)

Fuse Power Supply

I_CCDES

I_CCDESfor Intel Atom processors Z5xx Series Recommended Design Target

power delivery (Estimated)

I_CC

I_CCfor Intel Atom processors Z5xx Series is the number that can be use

as a reflection on a battery life estimates

I

I_CCAuto-Halt

AH,

I_SGNT

I_DSLP

I_CCStop-Grant

I_CCDeep Sleep

dI_CC

I_CCA

P_AH

V_CCPower Supply Current Slew Rate at Processor Package Pin (Estimated)

/dt

I_CCfor V_CCASupply

Auto Halt Power

P_SGNT

P_DPRSLP

P_DC6

T_J

Stop Grant Power

Deeper Sleep Power

Deep Power Down Technology (C6).

Junction Temperature

Datasheet

9

Introduction

1.3

References

Material and concepts available in the following documents may be beneficial when

reading this document.

Table 1. References

Document

Document Number

Intel® System Controller Hub (Intel® SCH) Datasheet

http://www.intel.com/desi

gn/chipsets/embedded/SC

HUS15W/techdocs.htm

Intel® Atom™ Processor Z5xx Series Specification Update

http://www.intel.com/desi

gn/chipsets/embedded/SC

HUS15W/techdocs.htm

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture

http://www.intel.com/pro

ducts/processor/

manuals/index.htm

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

AP-485, Intel® Processor Identification and CPUID Instruction

Application Note

http://www.intel.com/desi

gn/processor/applnots/24

1618.htm

§

10

Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low-Power States

The processor supports low power states at the thread level and the core/package

level. Thread states (TCx) loosely correspond to ACPI processor power states (Cx). A

thread may independently enter the TC1/AutoHALT, TC1/MWAIT, TC2, TC4, or TC6

low power states, but this does not always cause a power state transition. Only when

both threads request a low-power state (TCx) greater than the current processor state

will a transition occur. The central power management logic ensures the entire

processor enters the new common processor power state. For processor power states

higher than C1, this would be done by initiating a P_LVLx (P_LVL2 and P_LVL3) I/O

read to the chipset by both threads. Package states are states that require external

intervention and typically map back to processor power states. Package states for the

processor include Normal (C0, C1), Stop Grant and Stop Grant Snoop (C2), Deeper

Sleep (C4), and Deep Power Down Technology (C6).

The processor implements two software interfaces for requesting low power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI

P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O

reads are converted to equivalent MWAIT C-state requests inside the processor and do

not directly result in I/O reads on the processor FSB. The monitor address does not

need to be setup before using the P_LVLx I/O read interface. The sub-state hints used

for each P_LVLx read can be configured in a software programmable MSR by BIOS. If

a thread encounters a chipset break event while STPCLK# is asserted, then it asserts

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to

system logic that individual threads should return to the C0 state and the processor

should return to the Normal state.

Figure 1 shows the thread low-power states. Figure 2 shows the package low-power

states. Table 2 provides a mapping of thread low-power states to package low power

states.

Datasheet

11

Low Power Features

Figure 1. Thread Low-Power States

Figure 2. Package Low-Power States

12

Datasheet

Low Power Features

Table 2. Coordination of Thread Low-Power States at the Package/Core Level

Thread 0

TC0

TC1¹

TC2

TC4/TC6

Thread 1

TC0

TC1¹

TC2

Normal (C0)

AutoHalt (C1)

Normal (C0)

AutoHalt (C1)

Stop-Grant (C2)

Normal (C0)

AutoHalt (C1)

Stop-Grant (C2)

Deeper Sleep

TC4/TC6

Normal (C0)

AutoHalt (C1)

Stop-Grant (C2) (C4)/Deep Power

Down (C6)

NOTE:

1.

AutoHALT or MWAIT/C1

To enter a package/core state, both threads must share a common low power state. If

the threads are not in a common low power state, the package state will resolve to

the highest common power C-state.

2.1.1

Package/Core Low-Power State Descriptions

The following state descriptions assume that both threads are in a common low power

state. For cases when only one thread is in a low power state no change in power

state will occur.

2.1.1.1

Normal States (C0, C1)

These are the normal operating states for the processor. The processor remains in the

Normal state when the processor/core is in the C0, C1/AutoHALT, or C1/MWAIT

states. C0 is the active execution state.

2.1.1.1.1 C1/AutoHalt Powerdown State

C1/AutoHALT is a low-power state entered when one thread executes the HALT

instruction while the other is in the TC1 or greater thread state. The processor will

transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or

FSB interrupt messages. RESET# will cause the processor to immediately initialize

itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more

information.

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system de-asserts the STPCLK# interrupt, the processor

will return to the HALT state.

While in AutoHALT Powerdown state, the processor will process bus snoops. The

processor will enter an internal snoopable sub-state (not shown in Figure 1) to process

the snoop and then return to the AutoHALT Powerdown state.

Datasheet

13

Low Power Features

2.1.1.1.2 C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when one thread executes the MWAIT(C1)

instruction while the other thread is in the TC1 or greater thread state. Processor

behavior in the MWAIT state is identical to the AutoHALT state except that Monitor

events can cause the processor to return to the C0 state. See the Intel® 64 and IA-32

Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-

M and Volume 2B: Instruction Set Reference, N-Z, for more information.

2.1.1.2

C2 State

Individual threads of the dual-threaded processor can enter the TC2 state by initiating

a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction. Once both threads have

C2 as a common state, the processor will transition to the C2 state—however, the

processor will not issue a Stop-Grant Acknowledge special bus cycle unless the

STPCLK# pin is also asserted by the chipset.

While in the C2 state, the processor will process bus snoops. The processor will enter

a snoopable sub-state described the following section (and shown in Figure 1), to

process the snoop and then return to the C2 state.

2.1.1.2.1 Stop-Grant State

When the STPCLK# pin is asserted, each thread of the processors enters the Stop-

Grant state within 1384 bus clocks after the response phase of the processor-issued

Stop-Grant Acknowledge special bus cycle. When the STPCLK# pin is de-asserted, the

core returns to its previous low-power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should

be driven to the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor will

stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#,

SLP#, DPSLP#, and DPRSTP# pins must be de-asserted prior to RESET# de-assertion.

When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be de-

asserted after the de-assertion of SLP#.

While in Stop-Grant state, the processor will service snoops and latch interrupts

delivered on the FSB. The processor will latch SMI#, INIT#, and LINT[1:0] interrupts

and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. The PBE#

signal will be asserted if there is any pending interrupt or Monitor event latched within

the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear

will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the

entire processor should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop

on the FSB (see Section 2.1.1.2.2). A transition to the Sleep state (see

Section 2.1.1.3.1) occurs with the assertion of the SLP# signal.

14

Datasheet

Low Power Features

2.1.1.2.2 Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this

state until the snoop on the FSB has been serviced (whether by the processor or

another agent on the FSB) or the interrupt has been latched. The processor returns to

the Stop-Grant state once the snoop has been serviced or the interrupt has been

latched.

2.1.1.3

C4 State

Individual threads of the processor can enter the C4 state by initiating a P_LVL4 I/O

read to the P_BLK or an MWAIT(C4) instruction. Attempts to request C3 will also

covert to C4 requests. If both processor threads are in C4, the central power

management logic will request that the entire processor enter the Deeper Sleep

package low-power state using the sequence through the Sleep and Deep Sleep states

all described in the following sections.

To enable the package level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing

and Intel Enhanced Deeper Sleep state fields must be configured in the

PMG_CST_CONFIG_CONTROL MSR. Refer to Section 2.1.1.3.3 for further details on

Intel Enhanced Deeper Sleep state.

2.1.1.3.1 Sleep State

The Sleep state is a low-power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state and is only

a transition state for Intel Atom processor Z5xx series. The SLP# pin should only be

asserted when the processor is in the Stop-Grant state. SLP# assertion while the

processor is not in the Stop-Grant state is out of specification and may result in

unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP#, or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before

the processor has returned to the Stop-Grant state will result in unpredictable

behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor will reset itself, ignoring

the transition through Stop-Grant state. If RESET# is driven active while the processor

is in the Sleep state, the SLP# and STPCLK# signals should be de-asserted

immediately after RESET# is asserted to ensure the processor correctly executes the

Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin (see Section 2.1.1.3.2).

While the processor is in the Sleep state, the SLP# pin must be de-asserted if another

asynchronous FSB event occurs.

Datasheet

15

Low Power Features

2.1.1.3.2 Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the

Sleep state and is also only a transition state for the Intel Atom processor Z5xx series.

BCLK may be stopped during the Deep Sleep state for additional platform level power

savings. As an example, BCLK stop/restart timings on appropriate chipset-based

platforms with the CK540 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs

of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must start toggling BCLK within 10 BCLK

periods within DPSLP# de-assertion.

To re-enter the Sleep state, the DPSLP# pin must be de-asserted. BCLK can be re-

started after DPSLP# de-assertion as described above. A period of 15 microseconds

(to allow for PLL stabilization) must occur before the processor can be considered to

be in the Sleep state. Once in the Sleep state, the SLP# pin must be de-asserted to

re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep

state, it will not respond to interrupts or snoop transactions. Any transition on an

input signal before the processor has returned to Stop-Grant state will result in

unpredictable behavior.

2.1.1.3.3 Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state, but further reduces core

voltage levels. One of the potential lower core voltage levels is achieved by entering

the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of

the DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level

is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of

Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of

the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely

shut down. Refer to Section 2.1.1.3.4 for further details on reducing the L2 cache and

entering Intel Enhanced Deeper Sleep state.

In response to entering Deeper Sleep, the processor drives the VID code

corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.

Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP#

de-assertion when the core requests a package state other than C4 or the core

requests a processor performance state other than the lowest operating point.

16

Datasheet

Low Power Features

2.1.1.3.4 Intel® Atom™ Processor Z5xx Series C5

As mentioned previously in this document, each C-state has latency and transitory

power costs associated with entering/exiting idle states. When the processor is

interrupted, it must awake to service requests. If these requests occur at a high

frequency, it is possible that more power will be consumed entering/exiting the states

than will be saved. To alleviate this concern, the Intel Atom processor Z5xx series

implements a new state called “Intel Atom processor Z5xx series C5”. The Intel Atom

processor Z5xx series C5 is not exposed to software. The only way to enter the C5

state is using a hardware promotion of C4 (with the cache ways shrunk to zero).

When the processor is in C4, the chipset assumes the processor has data in its cache.

Often, the processor has fully flushed its cache. To avoid waking up the processor to

service snoops when there is no data in its caches, the processor will automatically

promote C4 requests to C5 (when the cache is flushed). The chipset treats C5 as a

non-snoopable state. Therefore, all snoops will be completed from the I/O DMA

masters without waking up the processor.

While similar, the Intel Atom processor Z5xx series C5 differs from the Core 2 Duo

T5000/T7000 C5 implementation. In the Intel Atom processor Z5xx series C5, the V_CC

will not be powered below the retention of caches voltage— there is no need to

initialize the processor’s caches on a C5 exit, and C5 is not architecturally enumerated

to software. This state is the same as the Intel Atom processor Z5xx series C5 state.

2.1.1.4

C6 State

C6 is a new low power state being introduced on the Intel Atom processor Z5xx

series. C6 behavior is the same as Intel Enhanced Deeper Sleep with the addition of

an on-die SRAM. This memory saves the processor state allowing the processor to

lower its main core voltage closer to 0 V. It is important to note that V_CCcannot be

lower while only 1 (one) thread is in C6 state.

The processor threads can enter the C6 state by initiating a P_LVL6 I/O read to the

P_BLK or an MWAIT(C6) instruction. To enter C6, the processor’s caches must be

flushed. The primary method to enter C6 used by newer operating systems (that

support MWAIT) will be through the MWAIT instruction.

When the thread enters C6, it saves the processor state that is relevant to the

processor context in an on-die SRAM that resides on a separate power plane V_CCP(I/O

power supply). This allows the core V_CCto be lowered to any arbitrary voltage

including 0 V. The microcode performs the save and restore of the processor state on

entry and exit from C6 respectively.

To improve the amount of power reduction possible in the Deep Power Down

Technology state, a split V_TTis implemented. See Section 2.5.1 for additional

information.

Datasheet

17

Low Power Features

2.1.1.4.1 Intel® Deep Power Down Technology State (Package C6 State)

When both threads have entered the C6 state and the L2 cache has been shrunk down

to zero ways, the processor will enter the Package Deep Power Down Technology

state. To do so, the processor saves its architectural states in the on-die SRAM that

resides in the V_CCPdomain. At this point, the core V_CCwill be dropped to the lowest

core voltage (closer to 0.3 V). The processor is now in an extremely low-power state.

While in this state, the processor does not need to be snooped as all the caches were

flushed before entering the C6 state.

The Deep Power Down Technology exit sequence is triggered by the chipset when it

detects a break event. It de-asserts the DPRSTP#, DPSLP#, SLP#, and STPCLK# pins

to return to C0. At DPSLP# de-assertion, the core V_CCramps up to the LFM value and

the processor starts up its internal PLLs. At SLP# de-assertion the processor is reset

and the architectural state is read back into the threads from an on-die SRAM.

Refer to Figure 3 and Figure 4 for Deep Power Down Technology entry sequence and

exit sequences.

Figure 3. Deep Power Down Technology Entry Sequence

NOTE: Deep Power Down Technology is referred to as C6 in the above figure.

Figure 4. Deep Power Down Technology Exit Sequence

Ucode reset

and state

restore

(TC1)

TC0

DPSL#

deassert

SLP#

deassert

DPRST#

deassert

H/W

Reset

Package

C6

STPCLK#

deassert

TC0

Ucode reset

and state

restore

(TC0)

18

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Low Power Features

Figure 5 shows the relative exit latencies of the package sleep states discussed above.

Note: Figure 5 uses pre-silicon estimates. Silicon based data will be provided in a future

revision of this document.

Figure 5. Exit Latency Table

C0 (HFM)

TDP

C2

C1

Similar to C1 but Intel®

SCH blocks interrupts

Both threads halted

Most clocks off

C0 (LFM)

C1E

C1 plus frequency and

VID at LFM

C4

C6

C2 plus PLLs off; VID =

cache retention Vcc

Some L2 cache off

C2 plus PLLs off; VID =

C6 powerdown Vcc

L2 cache off

0

0.1

1

10

100

Latency (µs)

Datasheet

19

Low Power Features

2.2

Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable

number of L2 cache ways upon each Deeper Sleep entry under the following

conditions:

• The C0 timer that tracks continuous residency in the Normal package state has

not expired. This timer is cleared during the first entry into Deeper Sleep to allow

consecutive Deeper Sleep entries to shrink the L2 cache as needed.

• The FSB speed to processor core speed ratio is below the predefined L2 shrink

threshold.

The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in

the BBL_CR_CTL3 MSR. The C0 timer is referenced through the

CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2

cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the

FSB speed to processor core speed ratio is above the predefined L2 shrink threshold,

then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not

be taken into account for Dynamic Cache Sizing decisions.

Upon STPCLK# de-assertion, the core exiting Intel Enhanced Deeper Sleep state or C6

will expand the L2 cache to two ways and invalidate previously disabled cache ways. If

the L2 cache reduction conditions stated above still exist when the core returns to C4

then package enters Intel Enhanced Deeper Sleep state or C6, then the L2 will be

shrunk to zero again. If the core requests a processor performance state resulting in a

higher ratio than the predefined L2 shrink threshold, the C0 timer expires, and then

the whole L2 will be expanded upon the next interrupt event.

In addition, the processor supports Full Shrink on L2 cache. When the MWAIT C6

instruction is executed with a hint=0x2 in ECX[3:0], the micro code will shrink all the

active ways of the L2 cache in one step. This ensures that the package enters C6

immediately when it is in TC6 instead of iterating until the cache is reduced to zero.

The operating system (OS) is expected to use this hint when it wants to enter the

lowest power state and can tolerate the longer entry latency.

L2 cache shrink prevention may be enabled as needed on occasion through an

MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not

enter Intel Deeper Sleep state or C6 since the L2 cache remains valid and in full size.

20

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Low Power Features

2.3

Enhanced Intel SpeedStep® Technology

The processor features Enhanced Intel SpeedStep Technology. The following are the

key features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points providing optimal performance at

the lowest power.

• Voltage and frequency selection is software controlled by writing to processor

MSRs:

⎯ If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins and the PLL then locks to the

new frequency.

⎯ If the target frequency is lower than the current frequency, the PLL locks to

the new frequency and the V_CCis changed through the VID pin mechanism.

⎯ Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition

completes.

• The processor controls voltage ramp rates internally to ensure glitch free

transitions.

• Low transition latency and a large number of transitions are possible per second:

⎯ Processor core (including L2 cache) is unavailable for up to 10 μs during the

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel Thermal Monitor mode:

⎯ When the on-die thermal sensor indicates that the die temperature is too high,

the processor can automatically perform a transition to a lower frequency and

voltage specified in a software programmable MSR.

⎯ The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up transition to the previous frequency and voltage point

occurs.

⎯ An interrupt is generated for the up and down Intel Thermal Monitor

transitions enabling better system level thermal management.

• Enhanced thermal management features:

⎯ Digital Thermal Sensor and Out of Specification detection

⎯ Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in

case of unsuccessful TM2 transition.

Datasheet

21

Low Power Features

2.4

Enhanced Low-Power States

Enhanced low-power states (C1E, C2E, C4E) optimize for power by forcibly reducing

the performance state of the processor when it enters a package low-power state.

Instead of directly transitioning into the package low-power state, the enhanced

package low-power state first reduces the performance state of the processor by

performing an Enhanced Intel SpeedStep Technology transition down to the lowest

operating point. Upon receiving a break event from the package low-power state,

control will be returned to software while an Enhanced Intel SpeedStep Technology

transition up to the initial operating point occurs. The advantage of this feature is that

it significantly reduces leakage while in the Stop-Grant and Deeper Sleep states.

Note: Long-term reliability cannot be assured unless all the Enhanced Low-Power States are

enabled.

The processor implements two software interfaces for requesting enhanced package

low-power states: MWAIT instruction extensions with sub-state hints and using BIOS

by configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-

power states to enhanced package low-power states.

Caution: Enhanced Stop-Grant and Enhanced Deeper Sleep must be enabled using the

BIOS for the processor to remain within specification. Not complying with this

guideline may affect the long-term reliability of the processor.

Enhanced Intel SpeedStep Technology transitions are multi-step processes that

require clocked control. These transitions cannot occur when the processor is in the

Sleep or Deep Sleep package low-power states since processor clocks are not active in

these states. Enhanced Deeper Sleep is an exception to this rule when the Hard C4E

configuration is enabled in the IA32_MISC_ENABLES MSR. This Enhanced Deeper

Sleep state configuration will lower core voltage to the Deeper Sleep level while in

Deeper Sleep and, upon exit, will automatically transition to the lowest operating

voltage and frequency to reduce snoop service latency. The transition to the lowest

operating point or back to the original software requested point may not be

instantaneous. Furthermore, upon very frequent transitions between active and idle

states, the transitions may lag behind the idle state entry resulting in the processor

either executing for a longer time at the lowest operating point or running idle at a

high operating point. Observations and analyses show this behavior should not

significantly impact total power savings or performance score while providing power

benefits in most other cases.

22

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Low Power Features

2.5

FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On Die Termination disabling

• Low V_CCP(I/O termination voltage)

• Split V_TT

• CMOS Front Side Bus

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control

input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking

allows a reciprocal power reduction in chipset address and control input buffers when

the processor de-asserts its BR0# pin. The On-Die Termination on the processor FSB

buffers is disabled when the signals are driven low, resulting in additional power

savings. The low I/O termination voltage is on a dedicated voltage plane independent

of the core voltage, enabling low I/O switching power at all times.

2.5.1

Split V_TT

Split V_TTis an enhancement designed to support the C6 power state. As deeper ACPI

C-states are reached, leakage power becomes the only remaining source of power in

the processor core. The goal of C6 is to eliminate leakage power by completely

removing voltage from the processor core. The goal is aided by the introduction of

Split V_TT.

As the name Split V_TTimplies, a motherboard using the processor may support a split

V_TTrail. This split rail implementation will allow power to be removed from

approximately 90% of the I/O pins while in C6. These pins are powered by one Split

V_TTrail. The only pins that remain powered are those needed to awake from the C6

state. These pins are powered by the second Split V_TTrail. To enter this power saving

mode (while in C6), the Intel® SCH asserts SLPIOVR# which gates an external FET.

This situation results in an approximately 30% reduction in leakage current used.

2.5.2

CMOS Front Side Bus

The processor has a hybrid signaling mode—where data and address busses run in

CMOS mode and strobe signals operate in GTL mode. The reason to use GTL on strobe

signals is to improve signal integrity. The implementation of a CMOS bus offers

substantial power savings when compared with the traditional AGTL+ bus.

Datasheet

23

Low Power Features

2.6

Intel® Burst Performance Technology (Intel®

BPT)

The processor supports ACPI Performance States (P-States). The P-state referred to as

P0 will be a request for Intel® Burst Performance Technology (Intel® BPT). Intel BPT

opportunistically, and automatically, allows the processor to run faster than the

marked frequency if the part is operating within the thermal design limits of the

platform. Intel BPT mode provides more performance on demand without impacting or

raising MID thermals. Intel BPT can be enabled or disabled by BIOS.

§

24

Datasheet

Electrical Specifications

3 Electrical Specifications

This chapter contains signal group descriptions, absolute maximum ratings, voltage

identification, and power sequencing. The chapter also includes DC specifications.

3.1

FSB, GTLREF, and CMREF

The processor supports two kinds of signalling protocol: Complementary Metal Oxide

Semiconductor (CMOS), and Advanced Gunning Transceiver Logic (AGTL+).

The “CMOS FSB” terminology used in this document refers to a hybrid signaling mode,

where data and address busses run in CMOS mode and strobe signals operate in GTL

mode. The reason to use GTL on strobe signals is to improve signal integrity.

The termination voltage level for the processor CMOS and AGTL+ signals is

V_CCP= 1.05 V (nominal). Due to speed improvements to data and address bus, signal

integrity and platform design methods have become more critical than with previous

processor families.

The CMOS data and address busses require a reference voltage (CMREF) that is used

by the receivers to determine if a signal is a logical 0 or a logical 1. CMREF is only

applicable to data and address signals—not to the sideband signals listed in Table 5.

CMREF must be generated on the system board. In CMOS mode, there is no receiver-

side termination to I/O voltage (V_CCP).

The AGTL+ inputs, including the sideband signals listed in Table 5, require a reference

voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or

a logical 1. GTLREF must be generated on the system board. Termination resistors are

provided on the processor silicon and are terminated to its I/O voltage (V_CCP). The

appropriate chipset will also provide on-die termination, thus eliminating the need to

terminate the bus on the system board for most AGTL+ signals.

The CMOS bus depends on reflected wave switching and the AGTL+ bus depends on

incident wave switching. Timing calculations for CMOS and AGTL+ signals are based

on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB,

including trace lengths, is highly recommended when designing a system.

3.2

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of VCC

(power) and VSS (ground) inputs. All power pins must be connected to V_CCpower

planes while all VSS pins must be connected to system ground planes. Use of multiple

power and ground planes is recommended to reduce I*R drop. The processor VCC pins

must be supplied by the voltage determined by the VID (Voltage ID) pins.

Datasheet

25

Electrical Specifications

3.3

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large average current swings between low and full power states.

This may cause voltages on power planes to sag below their minimum values if bulk

decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors,

supplies current during longer lasting changes in current demand by the component

(such as, coming out of an idle condition). Similarly, they act as storage well for

current when entering an idle condition from a running condition. Care must be taken

in the board design to ensure that the voltage provided to the processor remains

within the specifications listed in Table 7, Table 7, and Table 7. Failure to do so can

result in timing violations or reduced lifetime of the component.

3.3.1

V_CCDecoupling

V_CCregulator solutions need to provide bulk capacitance with a low Effective Series

Resistance (ESR) and keep a low interconnect resistance from the regulator to the

socket. Bulk decoupling for the large current swings when the part is powering on or

entering/exiting low-power states must be provided by the voltage regulator solution.

3.3.2

FSB AGTL+ Decoupling

The processor integrates signal termination on the die. Decoupling must also be

provided by the system motherboard for proper AGTL+ bus operation.

3.4

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of

the processor. As in previous generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at

its default ratio at manufacturing. The processor uses a differential clocking

implementation.

3.5

Voltage Identification and Power Sequencing

The processor uses seven voltage identification pins (VID[6:0]) to support automatic

selection of power supply voltages. The VID pins for the processor are CMOS outputs

driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding

to the state of VID[6:0]. A “1” (one) in this refers to a high-voltage level and a “0”

(zero) refers to low-voltage level.

Power source characteristics must be stable whenever the supply to the voltage

regulator is stable.

Table 3. Voltage Identification Definition

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1.2000

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Datasheet

Electrical Specifications

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

Datasheet

27

Electrical Specifications

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

28

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Electrical Specifications

3.6

3.7

3.8

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection.

An external thermal sensor should also be used to protect the processor and the

system against excessive temperatures. Even with the activation of THERMTRIP#,

which halts all processor internal clocks and activity, leakage current can be high

enough such that the processor cannot be protected in all conditions without the

removal of power to the processor. If the external thermal sensor detects a

catastrophic processor temperature of 120°C (maximum), or if the THERMTRIP#

signal is asserted, the V_CCsupply to the processor must be turned off within 500 ms to

prevent permanent silicon damage due to thermal runaway of the processor.

THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted.

Reserved and Unused Pins

RSVD[3:0] must be tied directly to V_CCP(1.05 V)—non C6 rail to ensure proper

operation of the processor. All other RSVD signals can be left as No Connect.

Connection of these pins to V_CC, V_SS, or to any other signal (including each other) can

result in component malfunction or incompatibility with future processors. See

Section 4.2 for a pin listing of the processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected.

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 4.

Table 4. BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1]

BSEL[0]

BCLK Frequency

L

H

133 MHz

100 MHz

H

NOTE: All other bus selections reserved.

3.9

FSB Signal Groups

To simplify the following discussion, the FSB signals have been combined into groups

by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF

as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+

input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+

Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when

driving.

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29

Electrical Specifications

Implementation of a source synchronous data bus determines the need to specify two

sets of timing parameters. One set is for common clock signals which are dependent

upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so on.) and the second set

is for the source synchronous signals which are relative to their respective strobe lines

(data and address) as well as the rising edge of BCLK0. Asynchronous signals are still

present (A20M#, IGNNE#, and so on.) and can become active at any time during the

clock cycle. Table 5 identifies which signals are common clock, source synchronous,

and asynchronous.

Table 5. FSB Pin Groups

Signal Group

Type

Signals1

AGTL+ Common

Clock Input

Synchronous

to BCLK[1:0]

BPRI#, DEFER#, PREQ#4, RESET#, RS[2:0]#,

TRDY#, DPWR#

AGTL+ Common

Clock I/O

Synchronous

to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#,

HIT#, HITM#, LOCK#, PRDY#

CMOS Source

Synchronous I/O

Synchronous

to assoc.

strobe

Signals

Associated Strobe

ADSTB0#

REQ[4:0]#, A[16:3]#

A[31:17]#

ADSTB1#

D[15:0]#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

D[31:16]#

D[47:32]#

D[63:48]#

Strobes always use AGTL signaling—data pins are

CMOS only.

AGTL+ Strobes

CMOS Input

Synchronous

to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Asynchronous

DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,

LINT1/ NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Open Drain Output

Open Drain I/O

CMOS Output

Asynchronous

FERR#, THERMTRIP#, IERR#

PROCHOT#3

VID[6:0], BSEL[2:0]

TCK, TDI, TMS, TRST#

CMOS Input

Synchronous

to TCK

Open Drain Output

Synchronous

to TCK

TDO

FSB Clock

Clock

BCLK[1:0]

Power/Other

COMP[3:0], HFPLL, CMREF, GTLREF, /DCLK, /ADK,

THERMDA, THERMDC, VCC, VCCA, VCCP,

VCC_SENSE, VSS, VSS_SENSE, VCCFUSE, VCCPC6

NOTES:

1.

2.

Refer to Chapter 4 for signal descriptions and termination requirements.

In processor systems where there is no debug port implemented on the system board,

these signals are used to support a debug port interposer. In systems with the debug

port implemented on the system board, these signals are no connects.

PROCHOT# signal type is open drain output and CMOS input.

3.

4.

On die termination differs from other AGTL+ signals.

30

Datasheet

Electrical Specifications

3.10

CMOS Asynchronous Signals

CMOS input signals are shown in Table 5. Legacy output FERR#, IERR#, and other

non- AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers.

These signals do not have setup or hold time specifications in relation to BCLK[1:0].

However, all of the CMOS signals are required to be asserted for more than 5 BCLKs

for the processor to recognize them. See Section 3.12 for the DC specifications for the

CMOS signal groups.

3.11

Maximum Ratings

Table 6 specifies absolute maximum and minimum ratings. Within functional operation

limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Datasheet

31

Electrical Specifications

Table 6. Processor Absolute Maximum Ratings

Symbol

T_STORAGE

Parameter

Min.

Max.

Unit

Notes¹

Processor Storage Temperature

-40

85

°C

2, 3, 4

Any Processor Supply Voltage

with Respect to V_SS

V_{CC, VCCP, VCCPC6}

-0.3

-0.1

1.10

1.575

1.10

V

5

PLL power supply

VCCA

AGTL+ Buffer DC Input Voltage

with Respect to V_SS

VinAGTL+

CMOS Buffer DC Input Voltage

with Respect to V_SS

VinAsynch_CMOS

-0.1

1.10

V

NOTES:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal

specifications must be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias.

Storage within these limits will not affect the long term reliability of the device. For

functional operation, refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long term reliability of the

processor.

3.

4.

5.

The V_CCmaximum supported by the process is 1.2 V but the parameter can change

(burn in voltage is higher).

3.12

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core

(pads) unless noted otherwise. See Chapter 4 for the pin signal definitions and signal

pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The

DC specifications for these signals are listed in Table 11. DC specifications for the

CMOS group are listed in Table 12.

Table 11 through Table 13 list the DC specifications for the processor and are valid

only while meeting specifications for junction temperature, clock frequency, and input

voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer

to the highest and lowest core operating frequencies supported on the processor.

Active mode load line specifications apply in all states except in the Deep Sleep and

Deeper Sleep states. V_CC,BOOTis the default voltage driven by the voltage regulator at

power up in order to set the VID values. Unless specified otherwise, all specifications

for the processor are at T_J= 90 °C. Care should be taken to read all notes associated

with each parameter.

32

Datasheet

Electrical Specifications

Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor Z550,

Z540, Z530, Z520, and Z510

Symbol

FSB

Parameter

Min.

Typ.

Max.

Unit

Notes¹¹

BCLK Frequency

100.00

—

133.35

MHz

Frequency

V_CCHFM

V_CC@ Highest Frequency Mode (HFM)

V_CC@ Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

PLL Supply voltage

AVID

0.8

—

1.10

AVID

—

V

1, 2, 10

1, 2

V_CCLFM

V_{CC BOOT}

—

V_CCLFM

1.05

1.5

2, 6

,

V_CCP

1.00

1.425

0.30

0.75

1.00

1.15

1.575

0.40

1.0

12, 14

V_CCPC6

V_CCA

V_CCDPPWDN

V_CCDPRSLP

V_CCF

V_CC@ Deep Power Down Technology (C6)

V_CC@ Deeper Sleep (C4)

0.35

—

13

1, 2

Fuse Power Supply

1.05

1.10

I_CCfor Processors Recommended Design

Target (Estimated) for Z540, Z550

I_CCDES

—

4.0

3.5

—

A

I_CCfor Processors Recommended Design

Target (Estimated) for Z530, Z520, Z510

I_CCDES

Processor

Core Frequency/Voltage

Number

—

HFM: 2.0 GHz

Z550

3.5

1.5

—

A

3, 4

LFM: 0.80 GHz

HFM: 1.86 GHz

Z540

3.2

1.5

3, 4

LFM: 0.80 GHz

I_CC

Z530

Z520

Z510

HFM: 1.60 GHz

LFM: 0.80 GHz

HFM: 1.33 GHz

LFM: 0.80 GHz

HFM: 1.10 GHz

LFM: 0.60 GHz

2.50

1.25

2.50

1.25

2.50

1.25

—

A

3, 4

I_CCAuto-Halt and Stop-Grant

HFM: 1.1 – 2.0 GHz @ 1.10 Volts

LFM: 0.6 – 0.8 GHz @ 0.85 Volts

I

AH,

—

2.0

1.3

3, 4

I_SGNT

At 50° C

3, 4

I_DPRSLP

I_CCDeeper Sleep (C4)

—

0.2

2.5

A

V_CCPower Supply Current Slew Rate at

Processor Package Pin (Estimated)

dI_CC

I_CCA

A/µs

5, 7

/dt

I_CCfor V_CCASupply

—

130

2.5

mA

A

I_CCP+ I_CCPC6

I_CCP+ I_CCPC6before V_CCStable

8

Datasheet

33

Electrical Specifications

Symbol

Parameter

I_CCP+ I_CCPC6after V_CCStable

NOTES:

Min.

Typ.

Max.

Unit

Notes¹¹

I_CCP+ I_CCPC6

—

1.5

A

9

1.

Each processor is programmed with a maximum valid voltage identification value (VID),

which is set at manufacturing and can not be altered. Individual maximum VID values

are calibrated during manufacturing such that two processors at the same frequency

may have different settings within the VID range. Note that this differs from the VID

employed by the processor during a power management event (Thermal Monitor 2,

Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical AVID range is

0.75 V to 1.1 V.

2.

The voltage specifications are assumed to be measured across VCC_SENSE and

VSS_SENSE pins at the socket with a 100-MHz bandwidth oscilloscope, 1.5-pF

maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of

ground wire on the probe should be less than 5 mm. Ensure external noise from the

system is not coupled in the scope probe.

3.

4.

5.

6.

7.

Specified at 90°C T .

Specified at the nominal V_CC.

J

Measured at the bulk capacitors on the motherboard.

V_CC,BOOTtolerance is shown in Figure 6 and Figure 7.

Based on simulations and averaged over the duration of any change in current.

Specified by design/characterization at nominal V_CC. Not 100% tested.

This is a power-up peak current specification, which is applicable when V_CCPis high and

V_{CC_CORE}is low.

8.

9.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand

V_{CC_CORE}are high.

10. The V_CCmaximum supported by the process is 1.1 V but the parameter can change

(burn in voltage is higher).

11. Unless otherwise noted, all specifications in this table are based on estimates and

simulations or empirical data. These specifications will be updated with characterized

data from silicon measurements at a later date.

12. V_CCPmay be turned off during C6 power state— V_CCPC6must always be powered on to

1.05 V -5/+10% on all power states.

13. The V_CCpower supply needs to be set to 0.3V during C6 power state.

14. V_CCP(voltage rail which is turned off in C6, with SPLIT VTT Enabled) should ramp to

1.05 V while exiting C6 (Deep Power Down Technology State) at least 5µs before

V_{CC_CORE}ramps to LFM VID. In addition, V_CCPC6rail should remain at 1.05 -5/+10%

during V_CCPramp coming out of C6.

34

Datasheet

Electrical Specifications

Table 8. Voltage and Current Specifications for the Intel® Atom™ Processor

Z500

Symbol

FSB

Parameter

Min.

Typ.

Max.

Unit

Notes¹¹

BCLK Frequency

—

100.0

-—

MHz

Frequency

V_CCHFM

V_CCLFM

V_CC,BOOT

V_CCP

V_CC@ Highest Frequency Mode (HFM)

V_CC@ Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

AVID

0.75

—

0.85

AVID

—

V

1, 2, 10

1, 2

V_CCLFM

1.05

1.5

2, 6

1.00

1.425

0.30

0.75

1.15

1.575

0.40

0.85

12, 14

V_CCPC6

AGTL+ Termination Voltage

V_CCA

PLL Supply Voltage

V_CCDPPWDN

V_CCDPRSLP

V_CCat Deep Power Down Technology (C6)

V_CCat Deeper Sleep (C4)

0.35

—

13

1, 2

I_CCfor Processors Recommended Design Target

(Estimated)

I_CCDES

—

2.0

—

A

Processor

Core Frequency/Voltage

Number

—

I_CC

Z500

HFM: 0.8 GHz

LFM: 0.6 GHz

0.8

0.6

—

A

3, 4

I_AH

HFM: 0.8 GHz @ 0.85 Volts

LFM: 0.6 GHz @ 0.75 Volts

0.7

0.5

,

3, 4

I_SGNT

At 50°C

3, 4

I_DPRSLP

I_CCDeeper Sleep (C4)

—

0.11

2.5

A

V_CCPower Supply Current Slew Rate at

Processor Package Pin (Estimated)

dI_CC

I_CCA

A/µs

5, 7

/dt

I_CCfor V_CCASupply

—

130

2.5

1.5

mA

A

I_CCP+ I_CCPC6

I_CCP+ I_CCPC6 before V_CCStable

I_CCP+ I_CCPC6 after V_CCStable

8

9

A

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID),

which is set at manufacturing and can not be altered. Individual maximum VID values

are calibrated during manufacturing such that two processors at the same frequency

may have different settings within the VID range. Note that this differs from the VID

employed by the processor during a power management event (Thermal Monitor 2,

Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical AVID range is

0.75 V to 0.85 V.

2.

The voltage specifications are assumed to be measured across VCC_SENSE and

VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum

probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground

wire on the probe should be less than 5 mm. Ensure external noise from the system is

not coupled in the scope probe.

3.

4.

5.

Specified at 90°C T .

Specified at the nominal V_CC.

Measured at the bulk capacitors on the motherboard.

J

Datasheet

35

Electrical Specifications

6.

7.

V_CC,BOOTtolerance is shown in Figure 6 and Figure 7.

Based on simulations and averaged over the duration of any change in current.

Specified by design/characterization at nominal V_CC. Not 100% tested.

This is a power-up peak current specification, which is applicable when V_CCPis high and

V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand

V_{CC_CORE}are high.

8.

9.

10. The V_CCmaximum supported by the process is 1.1 V but the parameter can change

(burn in voltage is higher).

11. Unless otherwise noted, all specifications in this table are based on estimates and

simulations or empirical data. These specifications will be updated with characterized

data from silicon measurements at a later date.

12. V_CCPmay be turned off during C6 power state—V_CCPC6must always be powered on to

1.05 V ±5% on all power states.

13. The V_CCpower supply needs to be set to 0.3 — 0.4 V during C6 power state.

14. V_CCP(voltage rail which is turned off in C6, with SPLIT VTT Enabled) should ramp to

1.05 V while exiting C6 (Deep Power Down Technology State) at least 5 µs before

V_{CC_CORE}ramps to LFM VID. In addition, V_CCPC6rail should remain at 1.05 (-5/+10%)

during V_CCPramp coming out of C6.

Table 9. Voltage and Current Specifications for the Intel® Atom™ Processor Z515

Symbol

FSB

Parameter

Min.

—

Typ.

100.0

—

Max.

—

Unit

MHz

V

Notes¹¹

BCLK Frequency

Frequency

V @ Burst Frequency Mode (BFM)

V_CCBFM

AVID

1.1

1, 2, 10

V_CCHFM

V_CCLFM

V_CCBOOT

V_CCP

V @ Highest Frequency Mode (HFM)

V @ Lowest Frequency Mode (LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

AVID

0.75

—

1.1

AVID

—

V

1, 2, 10

1, 2

V_CCLFM

1.05

1.5

2, 6

1.00

1.425

0.30

0.75

1.15

1.575

0.40

0.85

12, 14

V_CCPC6

AGTL+ Termination Voltage

V_CCA

PLL Supply Voltage

V_CCDPPWDN

V_CCPRSLP

V @ Deep Power Down Technology (C6)

V @ Deeper Sleep (C4)

0.35

—

13

1, 2

I for Processors Recommended Design Target

(Estimated)

I_CCDES

—

2.0

—

A

Processor

Core Frequency/Voltage

Number

—

I_CC

Z515

BFM: 1.2 GHz

HFM: 0.8 GHz

LFM: 0.6 GHz

2.5

0.8

0.6

—

A

3, 4, 15

BFM: 1.2 GHz @ AVID Volts

HFM: 0.8 GHz @ AVID Volts

LFM: 0.6 GHz @ AVID Volts

0.9

0.7

0.5

I_AH

,

—

A

3, 4

I_SGNT

@ 50°C

3, 4

I_DPRSLP

I_CCDeeper Sleep (C4)

0.11

36

Datasheet

Electrical Specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes¹¹

V Power Supply Current Slew Rate @ Processor

Package Pin (Estimated)

dI_CC

I_CCA

—

2.5

A/µs

5, 7

/dt

I_CCAfor V Supply

—

130

2.5

1.5

mA

A

I_CCP+ I_CCPC6

I_CCP+ I_CCPC6before V Stable

I_CCP+ I_CCPC6after V Stable

8

9

A

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID),

which is set at manufacturing and can not be altered. Individual maximum VID values

are calibrated during manufacturing such that two processors at the same frequency

may have different settings within the VID range. Note that this differs from the VID

employed by the processor during a power management event (Thermal Monitor 2,

Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical AVID range is

0.75 V to 0.85 V.

2.

The voltage specifications are assumed to be measured across VCC_SENSE and

VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum

probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground

wire on the probe should be less than 5 mm. Ensure external noise from the system is

not coupled in the scope probe.

3.

4.

5.

6.

7.

Specified at 90°C T .

Specified at the nominal V_CC.

J

Measured at the bulk capacitors on the motherboard.

V_CC,BOOTtolerance is shown in Figure 6 and Figure 7.

Based on simulations and averaged over the duration of any change in current.

Specified by design/characterization at nominal V_CC. Not 100% tested.

This is a power-up peak current specification, which is applicable when V_CCPis high and

V_{CC_CORE}is low.

8.

9.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand

V_{CC_CORE}are high.

10. The V_CCmaximum supported by the process is 1.1 V but the parameter can change

(burn in voltage is higher).

11. Unless otherwise noted, all specifications in this table are based on estimates and

simulations or empirical data. These specifications will be updated with characterized

data from silicon measurements at a later date.

12. V_CCPmay be turned off during C6 power state—V_CCPC6must always be powered on to

1.05 V ±5% on all power states.

13. The V_CCpower supply needs to be set to 0.3 to 0.4 V during C6 power state.

14. V_CCP(voltage rail which is turned off in C6, with SPLIT VTT Enabled) should ramp to

1.05 V while exiting C6 (Deep Power Down Technology State) at least 5 µs before

V_{CC_CORE}ramps to LFM VID. In addition, V_CCPC6rail should remain at 1.05 (-5/+10%)

during V_CCPramp coming out of C6.

15. The Intel Atom processor Z515 enables Intel® Burst Performance Technology (Intel®

BPT).

Datasheet

37

Electrical Specifications

Figure 6. Active V_ccand I_ccLoadline

38

Datasheet

Electrical Specifications

Figure 7. Deeper Sleep V_CCand I_CCLoadline

Datasheet

39

Electrical Specifications

Table 10. FSB Differential BCLK Specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

Figure

Notes¹

V_IH

Input High Voltage

—

1.15

V

7, 8

V_IL

V_CROSS

ΔV_CROSS

V_SWING

I_LI

Input Low Voltage

—

0.3

—

-0.3

0.55

140

—

V

7, 8

Crossing Voltage

2, 7, 9

Range of Crossing Points

Differential Output Swing

Input Leakage Current

Pad Capacitance

—

mV

µA

pF

2, 7, 5

300

-5

—

6

3

4

—

+5

Cpad

1.2

1.45

2.0

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to

the falling edge of BCLK1.

3.

4.

5.

6.

7.

8.

9.

For Vin between 0 V and V_IH.

Cpad includes die capacitance only. No package parasitics are included.

ΔV_CROSSis defined as the total variation of all crossing voltages as defined in note 2.

Measurement taken from differential waveform.

Measurement taken from single-ended waveform.

“Steady state” voltage, not including Overshoots or Undershoots.

Only applies to the differential rising edge (BCLK0 rising and BCLK1 falling).

40

Datasheet

Electrical Specifications

Table 11. AGTL+/CMOS Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min.

Typ.

Max.

Unit

Notes¹

V_CCP

V_CCPC6

GTLREF

CMREF

R_COMP

1.00

—

1.05

1.10

—

V

Ω

12

6

I/O Voltage for C6

GTL Reference Voltage

CMOS Reference Voltage

Compensation Resistor

Termination Resistor

2/3 V_CCP

1/2 V_CCP

27.5

—

6

27.23

—

27.78

—

10

11

R_ODT

55

GTLREF+0.10

or

CMREF+0.10

V_IH

Input High Voltage

Input Low Voltage

V_CCP

V_CCP+0.10

V

3, 6

2, 4

GTLREF–0.10

or

V_IL

-0.10

0

CMREF–0.10

V_CCP

V_OH

R_TT

Output High Voltage

V_CCP–0.10

V_CCP

55

V

6

46 [SS]

46 [CC]

61 [SS]

64 [CC]

Termination Resistance

Ω

7, 13

R_ON(GTL

mode)

GTL Buffer on Resistance

CMOS Buffer on Resistance

21

25

50

29

Ω

5

42 [SS]

42 [CC]

55 [SS]

58 [CC]

R_ON(CMOS

mode)

5, 13

I_LI

Input Leakage Current

Pad Capacitance

—

±100

2.75

µA

pF

8

9

Cpad

1.8

2.1

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

V_ILis defined as the maximum voltage level at a receiving agent that will be interpreted

as a logical low value.

3.

4.

5.

V_IHis defined as the minimum voltage level at a receiving agent that will be interpreted

as a logical high value.

V_IHand V_OHmay experience excursions above V_CCP. However, input signal drivers must

comply with the signal quality specifications.

This is the pull-down driver resistance. Measured at 0.31*V_CCP. R_ON(minimum) =

0.4*R_TT, R_ON(typical) = 0.455*R_TT, R_ON(maximum) = 0.51*R_TT. R_TTtypical value of 55 Ω

is used for R_ONtypical/minimum/maximum calculations.

6.

7.

GTLREF and CMREF should be generated from V_CCPwith a 1% tolerance resistor divider.

The V_CCPreferred to in these specifications is the instantaneous V_CCP

.

R_TTis the on-die termination resistance measured at V_OLof the AGTL+ output driver.

Measured at 0.31*V_CCP. R_TTis connected to V_CCPon die.

8.

9.

Specified with on die R_TTand R_ONare turned off. Vin between 0 and V_CCP

Cpad includes die capacitance only. No package parasitics are included.

.

10. There is an external resistor on the comp0 and comp2 pins.

11. On die termination resistance, measured at 0.33*V_CCP

12. _CCP=V_CCPC6 during normal operation. When in C6 state, V_CCP=0 V while V_CCPC6=1.05 V.

.

V

13. SS: source synchronous pins such as quad-pumped data bus and double-pumped

address bus which require a clock strobe. CC: Common clock pins.

Datasheet

41

Electrical Specifications

Table 12. Legacy CMOS Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min.

Typ.

Max.

Unit

Notes¹

V_CCP

V_CCPC6

V_IH

1.00

1.05

V_CCP

0.00

V_CCP

0

1.10

V

8

2

4

3

5

6

I/O Voltage for C6

Input High Voltage

Input Low Voltage CMOS

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Input Leakage Current

Pad Capacitance

0.7*V_CCP

-0.10

0.9*V_CCP

-0.10

1.5

VCCP+0.1

0.3*V_CCP

V_CCP+0.1

0.1*V_CCP

4.1

V

V_IL

V

V_OH

V

V_OL

V

I_OH

—

mA

µA

pF

I_OL

1.5

—

4.1

I_LI

—

± 100

2.55

Cpad1

1.6

2.1

Pad Capacitance for CMOS

Input

Cpad2

0.95

1.2

1.45

7

NOTES:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V_CCPreferred to in these specifications refers to instantaneous V_CCP

.

Measured at 0.1*V_CCP

Measured at 0.9*V_CCP

.

For Vin between 0V and V_CCP. Measured when the driver is tri-stated.

Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package

parasitics are included.

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics

are included.

7.

8.

V

_CCPC6 = V_CCPduring normal operation and a specific tolerance may be added for this

later.

Table 13. Open Drain Signal Group DC Specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes¹

V_OH

V_OL

Output High Voltage

Output Low Voltage

Output Low Current

Output Leakage Current

Pad Capacitance

V_CCP-–5%

V_CCP

—

V_CCP+5%

0.20

V

3

0

I_OL

16

—

50

mA

µA

pF

2

4

5

I_LO

—

±200

2.45

Cpad

1.9

2.2

NOTES:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2 V.

V_OHis determined by value of the external pull-up resistor to V_CCP

.

For Vin between 0 V and V_OH.

Cpad includes die capacitance only. No package parasitics are included.

42

Datasheet

Electrical Specifications

3.13

AGTL+ FSB Specifications

Termination resistors are not required for most AGTL+ signals, as these are integrated

into the processor silicon.

Valid high and low levels are determined by the input buffers which compare a signal’s

voltage with a reference voltage called GTLREF (known as V_REFin previous

documentation).

Table 11 lists the GTLREF and CMREF specifications. The AGTL+ and CMOS reference

voltages (GTLREF and CMREF) should be generated on the system board using high

precision voltage divider circuits. It is important that the system board impedance is

held to the specified tolerance, and that the intrinsic trace capacitance for the AGTL+

signal group traces is known and well- controlled.

§

Datasheet

43

Electrical Specifications

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44

Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin

Information

This chapter describes the package specifications, pinout assignments, and signal

descriptions.

4.1

Package Mechanical Specifications

The processor will be available in 512 KB, 441 pins in FCBGA8 package. The package

dimensions are shown in Figure 8.

4.1.1

Processor Package Weight

The Intel Atom processor Z5xx series package weight is 0.475 g.

Datasheet

45

Package Mechanical Specifications and Pin Information

Figure 8. Package Mechanical Drawing

46

Datasheet

Package Mechanical Specifications and Pin Information

4.2

Processor Pinout Assignment

Figure 9 and Figure 10 are graphic representations of the processor pinout

assignments. Table 14 lists the pinout by signal name.

Figure 9. Pinout Diagram (Top View, Left Side)

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

1

2

VSS/NCTF

D[61]#

DSTBN[3]#

D[51]#

VSS

THERMTRIP#

1

2

VSS/NCTF

D[60]#

D[59]#

D[62]#

VCC

VID[6]

3

4

VSS/NCTF

D[48]#

D[45]#

D[36]#

D[54]#

D[52]#

D[40]#

D[35]#

VSS

D[49]#

VCCP

VSS

DINV[3]#

VSS

THRMDA

VSS

3

4

VSS/NCTF

D[50]#

D[46]#

D[47]#

D[53]#

VSS

D[57]#

D[56]#

D[32]#

D[37]#

D[63]#

D[55]#

VSS

DSTBP[3]#

VSS

D[58]#

VSS

THRMDC

VCC

5

6

7

D[33]#

VSS

7

8

VSS

VCCP

VCC

8

9

VCCP

VSS

9

10

VSS

VCCP

VCC

10

DSTBN[2]

#

DSTBP[2]

#

11

VSS

VCCP

VSS

11

12

13

D[44]#

D[43]#

VSS

DINV[2]#

COMP[0]

VSS

VCCP

VCC

12

13

D[42]#

D[34]#

D[39]#

D[41]#

COMP[1]

14

15

16

14

15

16

RSVD

VCCP

VSS

D[38]#

VSS

RSVD

VSS

VCCP

VCC

17

18

19

20

D[27]#

D[24]#

RSVD

VCCP

VSS

17

18

19

20

D[30]#

D[18]#

VSS

D[26]#

D[19]#

VSS

VCCP

VCC

D[31]#

D[28]#

DSTBN[1]

#

21

DSTBP[1]#

VSS

VCCP

VSS

21

22

23

24

25

26

27

D[20]#

D[29]#

GTLREF

VSS

DINV[1]#

D[16]#

VSS

VCCP

VSS

VCC

22

23

24

25

26

27

28

29

D[23]#

D[22]#

D[1]#

D[25]#

D[21]#

D[11]#

D[5]#

VSS

VCCP

D[14]#

VSS

D[17]#

D[15]#

D[9]#

VSS

CMREF

D[6]#

VCCP

DRDY#

VCCP

D[12]#

VSS

D[0]#

VSS

TEST3

VSS

28 VSS/NCTF

D[13]#

DINV[0]#

DSTBN[0]#

BSEL[2]

29

VSS/NCTF

VSS

30

VSS/NCTF

D[4]#

D[3]#

DSTBP[0]#

D[8]#

TEST4

30

31

VSS/NCTF

D[10]#

D[7]#

D[2]#

DPWR#

TEST2

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

Figure 10. Pinout Diagram (Top View, Right Side)

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

Datasheet

47

Package Mechanical Specifications and Pin Information

1

2

TMS

TDO

STPCLK#

IERR#

BPM[0]#

VSS/NCTF

VSS/NCT

F

VID[5]

TDI

TCK

SLP#

DPRSTP#

BPM[1]#

2

3

VSS

VID[0]

VSS

RESET#

VSS

VID[3]

VSS

PROCHOT#

VCCPC6

VCCP

VSS

BPM[2]#

PREQ#

VSS

BPM[3]#

A[19]#

RSVD

VSS/NCTF

A[17]#

A[26]#

A[21]#

A[31]#

A[23]#

A[16]#

A[7]#

3

4

VID[1]

VCC

VID[2]

VCC

VCCP

VSS

VID[4]

VSS

TRST#

VSS

PWRGOOD

DPSLP#

VSS

PRDY#

RSVD

A[29]#

VSS

VSS/NCTF

A[22]#

A[28]#

A[25]#

A[18]#

A[30]#

A[10]#

A[8]#

4

5

6

7

8

VCC

VCCPC6

VCCP

VSS

RSVD

VSS

8

9

VSS

RSVD

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

VCC

VSS

RSVD

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

VSS

ADSTB[1]#

A[27]#

A[12]#

A[15]#

ADSTB[0]#

A[5]#

VCC

VSS

A[20]#

A[24]#

COMP[2]

A[11]#

REQ[2]#

A[3]#

VSS

VCCP

VSS

VCC

VSS

VCCP

COMP[3]

VSS

VCC

VSS

VCCP

VCC

VSS

VCCP

VSS

A[13]#

REQ[4]#

A[9]#

VCC

VSS

A[14]#

A[4]#

VSS

VCCP

VSS

VCC

VSS

VCCP

VSS

REQ[1]#

LOCK#

VCC

BPRI#

RSVD

A[6]#

VSS

REQ[3]#

RSVD

VSS

BNR#

TRDY#

VSS

REQ[0]#

DEFER#

VSS/NCTF

VCCP

BCLK[1]

VCCP

LINT1

SMI#

FERR#

RS[2]#

RS[1]#

ADS#

BR0#

VSS

VCCPC6

VSS

RSVD

IGNNE#

VSS

RS[0]#

DBSY#

VSS/NCTF

BCLK[0]

HITM#

VSS/NCT

F

30

31

BSEL[0]

VCCA

RSVD

A20M#

HIT#

30

31

TEST1

BSEL[1]

VSS

LINT0

INIT#

VSS/NCTF

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

48

Datasheet

Package Mechanical Specifications and Pin Information

Table 14. Pinout Arranged by Signal Name

Signal Name

A[3]#

Ball #

E22

A22

D21

E24

B17

A18

B23

A16

E18

D15

B19

A20

D17

B15

B5

Signal Name

ADS#

Ball #

C26

D19

D11

P29

Signal Name

D[9]#

Ball #

AC28

AD31

AF27

AD27

AG28

AB25

AC26

AE24

AC24

AJ20

AE20

AJ22

AF25

AH25

AH23

AH19

AF23

AE18

AH17

AD19

AJ24

AJ18

AF19

AE8

A[4]#

ADSTB[0]#

ADSTB[1]#

BCLK[0]

BCLK[1]

BNR#

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

D[29]#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

A[5]#

A[6]#

A[7]#

R28

H25

F1

A[8]#

A[9]#

BPM[0]#

BPM[1]#

BPM[2]#

BPM[3]#

BPRI#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A20M#

E2

F5

D3

G24

C28

G26

R30

M31

U28

AE26

AE14

AD13

E16

BR0#

RSVD

BSEL[0]

BSEL[1]

BSEL[2]

CMREF[1]

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

A12

D5

E12

B9

A6

B13

E14

A10

B7

F15

Y27

D[1]#

AH27

Y31

D[2]#

D13

A8

D[3]#

AC30

AE30

AF29

AA26

AB31

W30

AD7

D[4]#

AH15

AF9

C4

D[5]#

A14

B11

G30

D[6]#

AH9

D[7]#

AE10

AJ16

D[8]#

Datasheet

49

Package Mechanical Specifications and Pin Information

Signal Name

D[39]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#

DBSY#

Ball #

AF13

AF7

Signal Name

DPRSTP#

DPSLP#

Ball #

G2

Signal Name

REQ[4]#

RESET#

RS[0]#

RS[1]#

RS[2]#

RSVD

Ball #

B21

M5

G6

AF15

AH13

AJ14

AJ12

AH7

AJ8

DPWR#

V31

W28

AA28

AF21

AH11

AB1

AA30

AH21

AF11

AA4

J28

D27

E28

E26

K29

D9

DRDY#

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

FERR#

RSVD

D7

AJ10

AH5

AB5

AJ6

RSVD

E8

RSVD

E10

L30

J30

E6

RSVD

Y1

RSVD

AF5

RSVD

G28

AJ26

E30

F29

H1

RSVD

AE16

AF17

AD15

AD17

A26

K27

J2

AG4

AF3

GTLREF

RSVD

HIT#

RSVD

AC6

AE6

AE4

W4

HITM#

RSVD

IERR#

RSVD

IGNNE#

INIT#

H27

F31

H31

L28

D25

E4

RSVD

SLP#

AC2

AE2

AD1

AA2

AC4

D29

B27

AE28

AE22

AE12

Y5

LINT0

SMI#

J26

K1

LINT1

STPCLK#

TCK

LOCK#

L2

PRDY#

TDI

N2

PREQ#

F7

TDO

M1

PROCHOT#

PWRGOOD

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

H5

TEST1

TEST2

TEST3

TEST4

THERMTRIP#

THRMDA

P31

T31

V27

U30

T1

DEFER#

DINV[0]#

DINV[1]#

DINV[2]#

DINV[3]#

G4

B25

D23

E20

A24

T5

50

Datasheet

Package Mechanical Specifications and Pin Information

Signal Name

THRMDC

TMS

Ball #

U4

Signal Name

VCC

Ball #

R22

Signal Name

VCCP

Ball #

AB11

AB13

AB15

AB17

AB19

AB21

AB23

H11

H13

H15

H17

H19

H21

H23

J10

P1

VCC

R24

VCCP

TRDY#

TRST#

VCC

F25

J4

VCC

U6

VCCP

VCC

U8

VCCP

L8

VCC

U10

U12

U14

U16

U18

U20

U22

U24

W8

VCCP

VCC

L10

L12

L14

L16

L18

L20

L22

L24

N6

VCC

VCCP

VCC

VCCP

VCC

VCCP

VCC

VCCP

VCC

VCCP

VCC

VCCP

VCC

VCCP

VCC

VCCP

VCC

W10

W12

W14

W16

W18

W20

W22

W24

N30

AA8

AA10

AA12

AA16

AA18

AA20

AA22

AB7

AB9

VCCP

VCC

N8

VCC

VCCP

VCC

N10

N12

N14

N16

N18

N20

N22

N24

R6

VCC

VCCP

J12

VCC

VCCP

J14

VCC

VCCP

J18

VCC

VCCP

J20

VCC

VCCP

J22

VCC

VCCP

L26

VCC

VCCA

VCCP

N26

R26

U26

W26

AA14

J16

VCC

VCCP

VCC

VCCP

VCC

R8

VCCP

VCC

R10

R12

R14

R16

R18

R20

VCCP

VCC

VCCP

VCC

VCCPC6

H7

VCC

H9

VCC

J8

VCC

M27

Datasheet

51

Package Mechanical Specifications and Pin Information

Signal Name

VCC_SENSE

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

VSS

Ball #

W2

Signal Name

VSS

Ball #

AD29

AF1

Signal Name

VSS

Ball #

C22

C24

C30

D1

P5

VSS/NCTF

VSS

R4

AF31

AG2

AG6

AG8

AG10

AG12

AG14

AG16

AG18

AG20

AG22

AG24

AG26

AG30

AH3

AH29

AJ4

VSS/NCTF

VSS

N4

K5

D31

F3

L4

VSS

R2

VSS

F9

U2

VSS

F11

F13

F17

F19

F21

F23

F27

G8

K31

A4

VSS

VSS/NCTF

VSS

A28

VSS

AA6

AA24

AB3

AB27

AB29

AC8

AC10

AC12

AC14

AC16

AC18

AC20

AC22

AD3

AD5

AD9

AD11

AD21

AD23

AD25

VSS

VSS/NCTF

VSS

G10

G12

G14

G16

G18

G20

G22

H3

VSS

AJ28

B3

VSS

B29

VSS

C2

VSS

C6

VSS

H29

J6

VSS

C8

VSS

C10

VSS

J24

K3

VSS

C12

VSS

C14

VSS

K7

VSS

C16

VSS

K9

VSS

C18

VSS

K11

K13

VSS

C20

VSS

52

Datasheet

Package Mechanical Specifications and Pin Information

Signal Name

VSS

Ball #

K15

K17

K19

K21

K23

K25

L6

Signal Name

VSS

Ball #

P15

P17

P19

P21

P23

P25

P27

T3

Signal Name

VSS

Ball #

V13

V15

V17

V19

V21

V23

V25

V29

W6

VSS

M3

VSS

M7

T7

VSS

M9

T9

VSS

Y3

M11

M13

M15

M17

M19

M21

M23

M25

M29

N28

P3

T11

T13

T15

T17

T19

T21

T23

T25

T27

T29

V3

VSS

Y7

VSS

Y9

VSS

Y11

Y13

Y15

Y17

Y19

Y21

Y23

Y25

Y29

V1

VSS

P7

V5

VSS_SENSE

P9

V7

P11

P13

V9

V11

Datasheet

53

4.3

Signal Description

Table 15. Signal Description

Signal Name

Type

Description

A[31:3]# (Address) defines a 2³²-byte physical memory address

space. In subphase 1 (one) of the address phase, these pins

transmit the address of a transaction.

In sub-phase 2, these pins transmit transaction type information.

These signals must connect the appropriate pins of both agents

on the processor FSB. A[31:3]# are source synchronous signals

and are latched into the receiving buffers by ADSTB[1:0]#.

Address signals are used as straps which are sampled before

RESET# is de-asserted.

A[31:3]#

I/O

If A20M# (Address-20 Mask) is asserted, the processor masks

physical address bit 20 (A20#) before looking up a line in any

internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address

wrap-around at the 1-MB boundary. Assertion of A20M# is only

supported in real mode.

A20M#

I

A20M# is an asynchronous signal. However, to ensure recognition

of this signal following an input/output write instruction, it must

be valid along with the TRDY# assertion of the corresponding

input/output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus

agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal loop, or deferred

reply ID match operations associated with the new transaction.

ADS#

I/O

Address strobes are used to latch A[31:3]# and REQ[4:0]# on

their rising and falling edges. Strobes are associated with signals

as shown below.

ADSTB[1:0]#

Signals

REQ[4:0]#, A[16:3]#

A[31:17]#

Associated Strobe

ADSTB[0]#

ADSTB[1]#

The differential pair BCLK (Bus Clock) determines the FSB

frequency. All FSB agents must receive these signals to drive

their outputs and latch their inputs.

BCLK[1:0]

BNR#

I

All external timing parameters are specified with respect to the

rising edge of BCLK0 crossing VCROSS.

BNR# (Block Next Request) is used to assert a bus stall by any

bus agent who is unable to accept new bus transactions. During a

bus stall, the current bus owner cannot issue any new

transactions.

I/O

54

Datasheet

Package Mechanical Specifications and Pin Information

Signal Name

Type

Description

BPM[0]#

BPM[1]#

BPM[2]#

BPM[3]#

O

I/O

O

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor which

indicate the status of breakpoints and programmable counters

used for monitoring processor performance. BPM[3:0]# should

connect the appropriate pins of all FSB agents. This includes

debug or performance monitoring tools.

I/O

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the FSB. It must connect the appropriate pins of both FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes

the other agent to stop issuing new requests, unless such

requests are part of an ongoing locked operation. The priority

agent keeps BPRI# asserted until all of its requests are completed

then releases the bus by de-asserting BPRI#.

BPRI#

BR0#

I

BR0# is used by the processor to request the bus. The arbitration

is done between the processor (Symmetric Agent) and Intel®

SCH (High Priority Agent).

I/O

BSEL[2:0] (Bus Select) are used to select the processor input

clock frequency. Table 4 defines the possible combinations of the

signals and the frequency associated with each combination. The

required frequency is determined by the processor, chipset and

clock synthesizer. All agents must operate at the same frequency.

The processor operates at 400-MHz or 533-MHz system bus

frequency100-MHz or 133-MHz BCLK frequency, respectively).

BSEL[2:0]

COMP[3:0]

O

COMP[3:0] must be terminated on the system board using

precision (1% tolerance) resistors.

PWR

D[63:0]# (Data) are the data signals. These signals provide a 64-

bit data path between the FSB agents, and must connect the

appropriate pins on both agents. The data driver asserts DRDY#

to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four

times in a common clock period. D[63:0]# are latched off the

falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group

of 16 data signals correspond to a pair of one DSTBP# and one

DSTBN#. The following table shows the grouping of data signals

to data strobes and DINV#.

D[63:0]#

I/O

Quad-Pumped Signal Groups

Data Group

DSTBN#/DSTBP#

DINV#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DINV# pins determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DINV#

signal. When the DINV# signal is active, the corresponding data

group is inverted and therefore sampled active high.

DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the FSB to indicate that the data bus is in use.

The data bus is released after DBSY# is de-asserted. This signal

must connect the appropriate pins on both FSB agents.

DBSY#

I/O

Datasheet

55

Signal Name

Type

Description

DEFER# is asserted by an agent to indicate that a transaction

cannot be guaranteed in-order completion. Assertion of DEFER#

is normally the responsibility of the addressed memory or

Input/Output agent. This signal must connect the appropriate pins

of both FSB agents.

DEFER#

I

DINV[3:0]# (Data Bus Inversion) are source synchronous and

indicates the polarity of the D[63:0]# signals. The DINV[3:0]#

signals are activated when the data on the data bus is inverted.

The bus agent will invert the data bus signals if more than half

the bits, within the covered group, would change level in the next

cycle. DINV[3:0]# assignment to data bus signals is shown

below.

DINV[3:0]#

I

Bus Signal

Data Bus Signals

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DPRSTP# when asserted on the platform causes the processor to

transition from the Deep Sleep State to the Deeper Sleep state.

In order to return to the Deep Sleep State, DPRSTP# must be de-

asserted. DPRSTP# is driven by the SCH chipset.

DPRSTP#

I

DPSLP# when asserted on the platform causes the processor to

transition from the Sleep State to the Deep Sleep state. In order

to return to the Sleep State, DPSLP# must be de-asserted.

DPSLP# is driven by the SCH chipset.

DPSLP#

DPWR#

I

DPWR# is a control signal from the Intel® SCH used to reduce

power on the processor data bus input buffers.

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be de-asserted to insert idle

clocks. This signal must connect the appropriate pins of both FSB

agents.

DRDY#

I/O

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

DINV[0]#, DSTBN[0]#

DINV[1]#, DSTBN[1]#

DINV[2]#, DSTBN[2]#

DINV[3]#, DSTBN[3]#

DSTBN[3:0]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

DINV[0]#, DSTBP[0]#

DINV[1]#, DSTBP[1]#

DINV[2]#, DSTBP[2]#

DINV[3]#, DSTBP[3]#

DSTBP[3:0]#

I/O

56

Datasheet

Package Mechanical Specifications and Pin Information

Signal Name

Type

Description

FERR# (Floating-point Error) PBE# (Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#.

When STPCLK# is not asserted, FERR#/PBE# indicates a floating

point when the processor detects an unmasked floating-point

error. FERR# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using

MSDOS*- type floating-point error reporting. When STPCLK# is

asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The

assertion of FERR#/PBE# indicates that the processor should be

returned to the Normal state. When FERR#/PBE# is asserted,

indicating a break event, it will remain asserted until STPCLK# is

de-asserted. Assertion of PREQ# when STPCLK# is active will also

cause an FERR# break event.

FERR#/PBE#

O

For additional information on the pending break event

functionality, including identification of support of the feature and

enable/disable information, refer to Volume 3 of the Intel® 64

and IA-32 Architectures Software Developer's Manuals and the

Intel® Processor Identification and CPUID Instruction Application

Note.

CMREF determines the signal reference level for CMOS input pins.

CMREF should be set at 1/2 V_CCP. CMREF is used by the CMOS

receivers to determine if a signal is a logical 0 or logical 1.

CMREF

PWR

If not using CMOS, then all CMREF and GTLREF should be

provided with 2/3 V_CCP

.

GTLREF determines the signal reference level for AGTL+ input

pins. GTLREF should be set at 2/3 V_CCP. GTLREF is used by the

AGTL+ receivers to determine if a signal is a logical 0 or logical

GTLREF

PWR

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT#

and HITM# together to indicate that it requires a snoop stall,

which can be continued by reasserting HIT# and HITM# together.

HIT#

HITM#

IERR# (Internal Error) is asserted by a processor as the result of

an internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may

optionally be converted to an external error signal (for example,

NMI) by system core logic. The processor will keep IERR#

asserted until the assertion of RESET# or INIT#.

IERR#

O

IGNNE# (Ignore Numeric Error) is asserted to force the processor

to ignore a numeric error and continue to execute non-control

floating-point instructions. If IGNNE# is de-asserted, the

processor generates an exception on a non-control floating-point

instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0)

is set.

IGNNE#

I

IGNNE# is an asynchronous signal. However, to ensure

recognition of this signal following an Input/Output write

instruction, it must be valid along with the TRDY# assertion of the

corresponding Input/Output Write bus transaction.

Datasheet

57

Signal Name

Type

Description

INIT# (Initialization), when asserted, resets integer registers

inside the processor without affecting its internal caches or

floating-point registers. The processor then begins execution at

the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests

during INIT# assertion. INIT# is an asynchronous signal.

However, to ensure recognition of this signal following an

Input/Output Write instruction, it must be valid along with the

TRDY# assertion of the corresponding Input/Output Write bus

transaction. INIT# must connect the appropriate pins of both FSB

agents.

INIT#

I

If INIT# is sampled active on the active to inactive transition of

RESET#, the processor reverses its FSB data and address signals

internally to ease mother board layout for systems where the

chipset is on the other side of the mother board.

D[63:0] => D[0:63]

A[31:3] => A[3:31]

DINV[3:0]# is also reversed.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate

pins of all APIC Bus agents. When the APIC is disabled, the LINT0

signal becomes INTR, a maskable interrupt request signal, and

LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are

backward compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

LINT[1:0]

I

Both of these signals must be software configured using BIOS

programming of the APIC register space to be used either as

NMI/INTR or LINT[1:0]. Because the APIC is enabled by default

after Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# indicates to the system that a transaction must occur

automatically. This signal must connect the appropriate pins of

both FSB agents. For a locked sequence of transactions, LOCK# is

asserted from the beginning of the first transaction to the end of

the last transaction.

LOCK#

I/O

When the priority agent asserts BPRI# to arbitrate for ownership

of the FSB, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the FSB

throughout the bus locked operation and ensure the automatic

operation of the lock.

The Probe Ready Signal used by debug tools to request debug

operation of the processor.

PRDY#

PREQ#

O

I

Probe Request Signal used by debug tools to request debug

operation of the processor.

58

Datasheet

Package Mechanical Specifications and Pin Information

Signal Name

Type

Description

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the

processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC)

has been activated, if enabled. As an input, assertion of

PROCHOT#

I/O,

PROCHOT# by the system will activate the TCC, if enabled. The

TCC will remain active until the system de-asserts PROCHOT#.

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and

power supplies are stable and within their specifications. “Clean”

implies that the signal will remain low (capable of sinking leakage

current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal

must then transition monotonically to a high state. PWRGOOD can

be driven inactive at any time, but clocks and power must again

be stable before a subsequent rising edge of PWRGOOD.

PWRGOOD

I

The PWRGOOD signal must be supplied to the processor—it is

used to protect internal circuits against voltage sequencing

issues. It should be driven high throughout boundary scan

operation.

REQ[4:0]# (Request Command) must connect the appropriate

pins of both FSB agents. They are asserted by the current bus

owner to define the currently active transaction type. These

signals are source synchronous to ADSTB[0]#.

REQ[4:0]#

RESET#

I/O

Asserting the RESET# signal resets the processor to a known

state and invalidates its internal caches without writing back any

of their contents. For a power-on Reset, RESET# must stay active

for at least two milliseconds after V_CCand BCLK have reached

their proper specifications. On observing active RESET#, both FSB

agents will de-assert their outputs within two clocks. All processor

straps must be valid within the specified setup time before

RESET# is de-asserted.

I

RS[2:0]# (Response Status) are driven by the response agent

(the agent responsible for completion of the current transaction),

and must connect the appropriate pins of both FSB agents.

RS[2:0]#

RSVD

RSVD[3:0] pins E10, E8, D7 and D9 must be tied directly to V_CCP

Reserved to ensure proper operation of the processor. All other RSVD

signals can be left as No Connects.

SLP# (Sleep), when asserted in Stop-Grant state, causes the

processor to enter the Sleep state. During Sleep state, the

processor stops providing internal clock signals to all units,

leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state will not recognize snoops or interrupts.

The processor will recognize only assertion of the RESET# signal,

de-assertion of SLP#, and removal of the BCLK input while in

SLP#

I

Sleep state. If SLP# is de-asserted, the processor exits Sleep

state and returns to Stop-Grant state, restarting its internal clock

signals to the bus and processor core units. If DPSLP# is asserted

while in the Sleep state, the processor will exit the Sleep state

and transition to the Deep Sleep state.

Datasheet

59

Signal Name

Type

Description

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt,

the processor saves the current state and enters System

Management Mode (SMM). An SMI Acknowledge transaction is

issued, and the processor begins program execution from the

SMM handler. If SMI# is asserted during the de-assertion of

RESET# the processor will tri-state its outputs.

SMI#

I

STPCLK# (Stop Clock), when asserted, causes the processor to

enter a low power Stop-Grant state. The processor issues a Stop-

Grant Acknowledge transaction, and stops providing internal clock

signals to all processor core units except the FSB and APIC units.

The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is de-

asserted, the processor restarts its internal clock to all units and

resumes execution. The assertion of STPCLK# has no effect on

the bus clock—STPCLK# is an asynchronous input.

STPCLK#

I

TCK (Test Clock) provides the clock input for the processor Test

Bus (also known as the Test Access Port).

TCK

TDI

I

TDI (Test Data In) transfers serial test data into the processor.

TDI provides the serial input needed for JTAG specification

support.

TDO (Test Data Out) transfers serial test data out of the

processor. TDO provides the serial output needed for JTAG

specification support.

TDO

O

TEST[1:4]

Test Signals. All TEST signals can be left as No Connects.

The processor protects itself from catastrophic overheating by use

of an internal thermal sensor. This sensor is set well above the

normal operating temperature to ensure that there are no false

trips. The processor will stop all execution when the junction

temperature exceeds approximately 120°C. This condition is

signaled to the system by the THERMTRIP# (Thermal Trip) pin.

THRMTRIP#

O

THRMDA

THRMDC

PWR

Thermal Diode — Anode

Thermal Diode — Cathode

TMS (Test Mode Select) is a JTAG specification support signal

used by debug tools.

TMS

I

TRDY# (Target Ready) is asserted by the target to indicate that it

is ready to receive a write or implicit writeback data transfer.

TRDY# must connect the appropriate pins of both FSB agents.

TRDY#

TRST# (Test Reset) resets the Test Access Port (TAP) logic.

TRST# must be driven low during power on Reset.

TRST#

VCCA

I

VCCA provides isolated power for the internal processor core

PLLs.

PWR

VCC

VSS

PWR

GND

Processor core power supply

Processor core ground node.

60

Datasheet

Package Mechanical Specifications and Pin Information

Signal Name

Type

Description

GND

Non Critical to Function

VSS/NCTF

VID[6:0] (Voltage ID) pins are used to support automatic

selection of power supply voltages (V_CC). Unlike some previous

generations of processors, these are CMOS signals that are driven

by the processor. The voltage supply for these pins must be valid

before the VR can supply V_CCto the processor. Conversely, the VR

output must be disabled until the voltage supply for the VID pins

becomes valid. The VID pins are needed to support the processor

voltage specification variations. See Table 3 for definitions of

these pins. The VR must supply the voltage that is requested by

the pins, or disable itself.

VID[6:0]

O

Processor I/O Power Supply which needs to turn off in Deep

Power Down Technology (C6) state if Split V_TTis incorporated.

VCCP

PWR

Processor I/O Power Supply which needs to remain on in Deep

Power Down Technology (C6) state.

VCCPC6

VCC_SENSE is an isolated low impedance connection to the

processor core power (V_CC). It can be used to sense or measure

power near the silicon with little noise.

VCC_SENSE

VSS_SENSE

O

VSS_SENSE is an isolated low impedance connection to processor

core V_SS. It can be used to sense or measure ground near the

silicon with little noise.

§

Datasheet

61

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62

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

The processor requires a thermal solution to maintain temperatures within operating

limits as set forth in Section 5.1. Any attempt to operate the processor outside these

operating limits may result in permanent damage to the processor and potentially

other components in the system. As processor technology changes, thermal

management becomes increasingly crucial when building computer systems.

Maintaining the proper thermal environment is critical to reliable, long-term system

operation. A complete thermal solution includes both component and system level

thermal management features. Component level thermal solutions include active or

passive heat spreaders or heat exchangers attached to the exposed processor die. The

solution should make firm contact to the die while maintaining processor mechanical

specifications such as pressure. A typical system level thermal solution may consist of

a system fan used to evacuate or pull air through the system in conjunction with a

multi-component heat spreader used to reduce the temperature of the processor and

other components while maintaining as uniform a skin temperature as possible.

Alternatively, the processor may be in a fan-less system, but would likely still use a

multi-component heat spreader.

Note: Trading thermal solutions also involves trading performance.

To allow for the optimal operation and long-term reliability of Intel processor-based

systems, the system/processor thermal solution should be designed such that the

processor remains within the minimum and maximum junction temperature (T_J)

specifications at the corresponding thermal design power (TDP) value listed in

Table 16 and Table 17. Thermal solutions not designed to provide this level of thermal

capability may affect the long-term reliability of the processor and system.

Refer to the Intel Centrino Atom Platform Thermal Application Note document for

more details on processor and system level cooling approaches.

The maximum junction temperature is defined by an activation of the processor Intel

Thermal Monitor. Refer to Section 5.1.2 for more details. Analysis indicates that real

applications are unlikely to cause the processor to consume the theoretical maximum

power dissipation for sustained time periods. Intel recommends that complete thermal

solution designs target the TDP indicated in Table 16 and Table 17. The Intel Thermal

Monitor feature is designed to help protect the processor in the unlikely event that an

application exceeds the TDP recommendation for a sustained period of time. For more

details on the usage of this feature, refer to Section 5.1.2. In all cases the Intel

Thermal Monitor feature must be enabled for the processor to remain within

specification.

Datasheet

63

Table 16. Power Specifications for Intel® Atom™ Processors Z550, Z540, Z530, Z520,

and Z510

Symbol

Processor

Number

Core Frequency and

Voltage

Thermal Design

Power

Unit

Notes

Z510

Z520

Z530

Z540

Z550

1.1 GHz and HFM V_CC

0.6 GHZ and LFM V_CC

2.0 W

W

@ 90°C

1, 4

1.33 GHz and HFM V_CC

0.8 GHZ and LFM V_CC

2.0 W

2.2 W with HT enabled

W

@ 90°C

1, 4, 6

@ 90°C

1, 4, 6

@ 90°C

1, 4, 6

@ 90°C

1, 4, 6

1.60 GHz and HFM V_CC

0.8 GHZ and LFM V_CC

2.0 W

2.2 W with HT enabled

TDP

1.86 GHz and HFM V_CC

0.8 GHZ and LFM V_CC

2.4 W

2.64 W with HT enabled

1.86 GHz and HFM V_CC

0.8 GHZ and LFM V_CC

2.4 W

2.64 W with HT enabled

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

P_AH,

Auto Halt, Stop Grant Power

@ HFM V_CC

—

@ 70°C

P_SGNT

1.0

0.7

0.5

W

2

@ LFM V_CC

P_DPRSLP

P_DC6

T_J

Deeper Sleep Power

—

0

—

@ 50°C

2, 5

Deep Power Down Technology (C6)

Junction Temperature

0.1

90

W

@ 50°C

2

°C

3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP

is not the maximum theoretical power the processor can generate.

2.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to

operate within specifications.

5.

6.

Deep Sleep state is mapped to Deeper Sleep State.

Intel Hyper-Threading Technology requires a computer system with an Intel processor

supporting Hyper-Threading Technology and an HT Technology enabled chipset, BIOS

and operating system. Hyper-threading technology is available on select Intel Atom™

processor components (Z520=1.33 GHz, Z530=1.60 GHz,

Z540=1.86 GHz, and Z550=2 GHz). HT Technology can add 200 mW of power above

TDP, so 1.33 GHz and 1.6 GHz processors can have 2.2 W of power and a 1.86 GHz

processor can have 2.64 W of power when multi-threaded applications are run.

64

Datasheet

Thermal Specifications and Design Considerations

Table 17. Power Specifications for Intel^®Atom™ Processors Z515 and Z500

Processor

Number

Core Frequency and

Voltage

Thermal Design

Power

Symbol

Unit

Notes

Z500/Z515 0.8 GHz and HFM V_CC

Z500/Z515 0.6 GHz and LFM V_CC

0.65

@ 90°C

TDP

W

1, 4, 6, 7

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Auto Halt, Stop Grant Power

@ HFM V_CC

@ 70°C

P_AH,

—

0.6

0.5

W

2, 6, 7

P_SGNT

@ LFM VCC

P_DPRSLP

P_DC6

T_J

Deeper Sleep Power

—

0

—

0.3

0.08

90

W

°C

2, 5

2

Deep Power Down Technology (C6)

Junction Temperature

3, 4

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP

is not the maximum theoretical power the processor can generate.

2.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

3.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

4.

The Intel Thermal Monitor automatic mode must be enabled for the processor to

operate within specifications.

5.

6.

7.

Deep Sleep state is mapped to Deeper Sleep State.

Intel Atom processor Z515 enables Intel® Burst Performance Technology.

Intel® HT Technology requires a computer system with an Intel processor supporting

Hyper-Threading Technology and an

Intel® HT Technology enabled chipset, BIOS, and operating system. The Intel Atom

processor Z500 does not support Intel® HT Technology while the Intel Atom processor

Z515 supports Intel® HT Technology.

Datasheet

65

5.1

Thermal Specifications

The processor incorporates three methods of monitoring die temperature—Digital

Thermal Sensor, Intel Thermal Monitor, and the Thermal Diode. The Intel Thermal

Monitor (detailed in Section 5.1.2) must be used to determine when the maximum

specified processor junction temperature has been reached.

5.1.1

Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is

used as a thermal “diode”, with its collector shorted to ground. The thermal diode can

be read by an off-die analog/digital converter (a thermal sensor) located on the

motherboard or a stand-alone measurement kit. The thermal diode may be used to

monitor the die temperature of the processor for thermal management or

instrumentation purposes but is not a reliable indication that the maximum operating

temperature of the processor has been reached. When using the thermal diode, a

temperature offset value must be read from a processor MSR and applied. See

Section 5.1.2 for more details. See Section 5.1.3 for thermal diode usage

recommendation when the PROCHOT# signal is not asserted.

The reading of the external thermal sensor (on the motherboard) connected to the

processor thermal diode signals will not necessarily reflect the temperature of the

hottest location on the die. This is due to inaccuracies in the external thermal sensor,

on-die temperature gradients between the location of the thermal diode and the

hottest location on the die, and time based variations in the die temperature

measurement. Time based variations can occur when the sampling rate of the thermal

diode (by the thermal sensor) is slower than the rate at which the T_Jtemperature can

change.

Offset between the thermal diode based temperature reading and the Intel Thermal

Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic

mode activation of the thermal control circuit. This temperature offset must be taken

into account when using the processor thermal diode to implement power

management events. This offset is different than the diode T_OFFSETvalue programmed

into the processor Model Specific Register (MSR).

Table 18. and Table 19 provide the diode interface and specifications. Transistor

model parameters shown in Table 19 provide more accurate temperature

measurements when the diode ideality factor is closer to the maximum or minimum

limits. Contact your external sensor supplier for their recommendation. The thermal

diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to

predict the behavior of the Thermal Monitor.

66

Datasheet

Thermal Specifications and Design Considerations

Table 18. Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

T5

U4

Thermal diode anode

Thermal diode cathode

Table 19. Thermal Diode Parameters Using Transistor Model

Symbol

Parameter

Forward Bias Current

Min.

Typ.

Max.

Unit

Notes

IFW

IE

5

—

200

μA

1

Emitter Current

5

nQ

Transistor Ideality

0.997

0.25

2.79

1.001

—

1.015

0.65

6.24

2, 3, 4

2, 3

2, 5

Beta

R_T

Series Resistance

4.52

Ω

NOTES:

1.

Intel does not support or recommend operation of the thermal diode under reverse

bias.

2.

3.

4.

Characterized across a temperature range of 50–100 °C.

Not 100% tested. Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

qV /n kT

BE

Q

I_C= I_S* (e

–1)

Where I_S= saturation current, q = electronic charge, V_BE= voltage across the

transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and

T = absolute temperature (Kelvin).

5. The series resistance, R_T, provided in the Diode Model Table (Table 19) can be used for


型号：	AC80566UC005DE
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 1100MHz, CMOS, PBGA441, 外围集成电路
文件：	总71页 (文件大小：784K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AC80566UC005DE [INTEL]

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