AGID022R38A1E1V [INTEL]
Micro Peripheral IC,;
| 型号： | AGID022R38A1E1V |
| 厂家： | 
INTEL |
| 描述： | Micro Peripheral IC, |
| 文件： | 总94页 (文件大小：814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel Agilex Device Data Sheet
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Contents
Contents
Intel® Agilex™ Device Data Sheet...............................................................................................................................................3
Electrical Characteristics...................................................................................................................................................... 4
Operating Conditions..................................................................................................................................................4
Switching Characteristics....................................................................................................................................................21
Core Performance Specifications.................................................................................................................................22
Periphery Performance Specifications..........................................................................................................................30
E-Tile Transceiver Performance Specifications...............................................................................................................39
P-Tile Transceiver Performance Specifications...............................................................................................................43
HPS Performance Specifications................................................................................................................................. 47
Configuration Specifications................................................................................................................................................81
General Configuration Timing Specifications.................................................................................................................81
POR Specifications....................................................................................................................................................81
External Configuration Clock Source Requirements....................................................................................................... 82
JTAG Configuration Timing.........................................................................................................................................82
AS Configuration Timing............................................................................................................................................83
Avalon® Streaming (Avalon®-ST) Configuration Timing................................................................................................. 85
Configuration Bit Stream Sizes...................................................................................................................................87
Maximum Configuration Time Estimation.....................................................................................................................87
I/O Timing....................................................................................................................................................................... 87
Programmable IOE Delay................................................................................................................................................... 88
Glossary.......................................................................................................................................................................... 88
Document Revision History for the Intel Agilex Device Data Sheet............................................................................................92
Intel Agilex Device Data Sheet
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Intel® Agilex™ Device Data Sheet
This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for
Intel® Agilex™ devices.
Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Intel's
discretion.
Table 1.
Data Sheet Status for Intel Agilex Devices
Variant
Data Status
Intel Agilex F-series
Intel Agilex I-series
Advance
Advance
Table 2.
Intel Agilex Device Grades and Speed Grades Supported
For specification status, see the Data Sheet Status table
Device Grade
Speed Grade Supported
Extended
–E1V (fastest)
–E2V
–E3V
–E3E
–E4F
Industrial
–I1V
continued...
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks
of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel
assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
ISO
9001:2015
Registered
*Other names and brands may be claimed as the property of others.
Intel® Agilex™ Device Data Sheet
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Device Grade
Speed Grade Supported
–I2V
–I3V
–I3E
The suffix after the speed grade denotes the power options offered in Intel Agilex devices.
•
•
•
V—standard power (VID)
E—lower power (VID)
F—fixed voltage
Related Information
Package and Thermal Resistance website
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel Agilex devices.
Operating Conditions
Intel Agilex devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Intel Agilex devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel Agilex devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
Caution:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
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Table 3.
Absolute Maximum Rating for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Condition
Minimum
–0.5
Maximum
1.14
Unit
V
VCC
Core voltage power supply
—
—
VCCP
Periphery circuitry power
supply
–0.5
1.14
V
VCCPT
Power supply for I/O PLL
and I/O pre-driver
—
–0.5
2.08
V
VCCR_CORE
CRAM power supply
—
–0.5
–0.5
2.08
1.21
V
V
VCCH
Transceiver digital power
supply
E-tile and P-tile devices
VCCH_SDM
SDM block transceiver
digital power sense
E-tile and P-tile devices
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
1.21
2.01
2.08
1.07
2.4
V
V
V
V
V
V
V
V
VCCIO_PIO_SDM
VCCIO_SDM
VCCL_SDM
SDM block I/O bank power
sense of Bank 3A
—
—
—
—
—
—
—
SDM block configuration
pins power supply
SDM block core voltage
power supply
VCCFUSEWR_SDM
VCCPLLDIG_SDM
VCCPLL_SDM
VCCBAT
SDM block fuse writing
power supply
SDM block PLL digital
power supply
1.07
2.08
2.08
SDM block PLL analog
power supply
Battery back-up power
supply (For design security
volatile key register)
VCCADC
ADC voltage sensor power
supply
—
–0.5
2.08
V
VCCIO_PIO
VCCA_PLL
I/O bank power supply
—
—
–0.5
–0.5
2.01
2.08
V
V
I/O clock network power
supply
continued...
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Symbol
VCCRT_GXE
VCC_HSSI_GXE
Description
Condition
E-tile devices
Minimum
–0.5
Maximum
1.21
Unit
V
Transceiver power supply
E-tile digital signal power
supply
E-tile devices
–0.5
1.21
V
VCCRTPLL_GXE
Transceiver PLL power
supply
E-tile devices
–0.5
1.21
V
VCCH_GXE
Analog power supply
E-tile devices
E-tile devices
–0.5
–0.5
1.47
3.41
V
V
VCCCLK_GXE
LVPECL REFCLK power
supply
VCCRT_GXP
Transceiver power supply
P-tile devices
P-tile devices
–0.5
–0.5
1.21
1.21
V
V
VCC_HSSI_GXP
P-tile digital signal power
supply
VCCFUSE_GXP
VCCCLK_GXP
P-tile efuse power supply
P-tile devices
P-tile devices
–0.5
–0.5
1.21
2.46
V
V
P-tile I/O buffer power
supply
VCCH_GXP
High voltage power for
transceiver
P-tile devices
—
–0.5
–0.5
2.46
1.21
V
V
VCCL_HPS
HPS core voltage and
periphery circuitry power
supply
VCCPLLDIG_HPS
VCCPLL_HPS
VCCIO_HPS
VI
HPS PLL digital power
supply
—
—
—
–0.5
–0.5
–0.5
1.21
2.08
2.08
V
V
V
HPS PLL analog power
supply
HPS I/O buffers power
supply
DC Input Voltage
VCCIO_PIO = 1.2 V
VCCIO_PIO = 1.5 V
–0.3
0
1.56
1.7
V
V
V
VCCIO_SDM, VCCIO_HPS = 1.8
V
–0.3
2.19
(1) (2)
IOUT
DC output current per pin
VCCIO_PIO = 1.2 V, 1.5 V (3)
–15
15
mA
continued...
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Symbol
Description
Condition
Minimum
Maximum
Unit
VCCIO_SDM, VCCIO_HPS = 1.8
V
–20
20
mA
(4)
TJ
Absolute junction
temperature
—
–55
–55
125
150
°C
°C
TSTG
Storage temperature
—
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following tables and undershoot to –1.1 V when
using VCCIO_HPS/ VCCIO_SDM of 1.8 V and –0.3 V when using VCCIO_PIO of 1.2 V for input currents less than 100 mA and periods
shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal
is equivalent to 100% duty cycle.
For example, when using 1.2 V I/O standard, a signal that overshoots to 1.71 V can only be at 1.71 V for ~3% over the
lifetime of the device.
No overshooting beyond 1.7 V and undershooting below 0 V is allowed when using VCCIO_PIO = 1.5 V.
(1)
(2)
(3)
Total current per I/O bank must not exceed 100 mA.
Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.
The maximum current allowed through any I/O bank pin when the device is not turned on or during power-up/power-down conditions
is 10 mA. The voltage level must not exceed 1.2 V.
(4)
The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down
conditions is 40 mA. The voltage level must not exceed 1.89 V.
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Table 4.
Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 1.2 V I/O)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
For specification status, see the Data Sheet Status table
Symbol
Description
Condition (V)
Overshoot Duration as % at TJ
= 100°C
Unit
Vi (AC)
AC input voltage
VCCIO_PIO + 0.30
100
%
%
%
%
%
%
VCCIO_PIO + 0.35
VCCIO_PIO + 0.40
VCCIO_PIO + 0.45
VCCIO_PIO + 0.50
> VCCIO_PIO + 0.50
37
9
3
1
No Overshoot Allowed
Table 5.
Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 1.8 V I/O)
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
For specification status, see the Data Sheet Status table
Symbol
Description
Condition (V)
Overshoot Duration as % at TJ
= 100°C
Unit
%
Vi (AC)
AC input voltage
VCCIO_SDM + 0.30, VCCIO_HPS
0.30
+
+
+
+
+
+
100
VCCIO_SDM + 0.35, VCCIO_HPS
0.35
60
%
VCCIO_SDM + 0.40, VCCIO_HPS
0.40
30
%
VCCIO_SDM + 0.45, VCCIO_HPS
0.45
20
%
VCCIO_SDM + 0.50, VCCIO_HPS
0.50
10
%
VCCIO_SDM + 0.55, VCCIO_HPS
0.55
6
%
>VCCIO_SDM + 0.55, >VCCIO_HPS
+ 0.55
No Overshoot Allowed
%
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When using 1.2 V VCCIO_PIO, for an overshoot of 1.56 V, the percentage of high time for the overshoot can be as high as 100%
over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the
device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.
Figure 1.
Intel Agilex Devices Overshoot Duration
1.76 V
1.56 V
1.2 V
DT
T
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel Agilex devices.
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Recommended Operating Conditions
Table 6.
Recommended Operating Conditions for Intel Agilex Devices
This table lists the steady-state voltage values expected for Intel Agilex devices. Power supply ramps must all be strictly monotonic, without plateaus.
For specification status, see the Data Sheet Status table
Symbol
Description
Condition
Minimum(5)
(Typical) – 3%
0.776
Typical
0.685 – 0.90(7)
0.8
Maximum(5)
(Typical) + 3%
0.824
Unit
V
VCC
Core voltage power
supply
–1V, –2V, –3V, –3E(6)
–4F
V
VCCP
Periphery circuitry
power supply
–1V, –2V, –3V, –3E(6)
(Typical) – 3%
0.776
0.685 – 0.90(7)
0.8
(Typical) + 3%
0.824
V
–4F
—
V
VCCPT
Power supply for I/O
PLL and I/O pre-driver
1.71
1.8
1.89
V
VCCR_CORE
VCCH
CRAM power supply
—
1.14
0.87
1.2
0.9
1.26
0.93
V
V
Transceiver digital
power supply
E-tile and P-tile
devices
VCCH_SDM
SDM block transceiver
digital power sense
E-tile and P-tile
devices
0.87
0.9
0.93
V
VCCIO_PIO_SDM
SDM block I/O bank
power sense of Bank
3A
1.5 V
1.2 V
—
1.455
1.14
1.71
1.5
1.2
1.8
1.545
1.26
1.89
V
V
V
VCCIO_SDM
SDM block
configuration pins
power supply
continued...
(5)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
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Symbol
VCCL_SDM
Description
Condition
Minimum(5)
Typical
Maximum(5)
Unit
SDM block core
voltage power supply
—
—
—
—
—
0.776
0.8
0.824
V
VCCFUSEWR_SDM
VCCPLLDIG_SDM
VCCPLL_SDM
SDM block fuse writing
power supply
1.75
0.776
1.71
1
1.8
0.8
1.8
—
1.85
0.824
1.89
1.8
V
V
V
V
SDM block PLL digital
power supply
SDM block PLL analog
power supply
(8)
VCCBAT
Battery back-up power
supply (For design
security volatile key
register)
VCCADC
ADC voltage sensor
power supply
—
1.71
1.8
1.89
V
VCCIO_PIO
I/O bank power supply 1.5 V
1.2 V
1.455
1.14
1.14
1.5
1.2
1.2
1.545
1.26
1.26
V
V
V
VCCA_PLL
I/O clock network
power supply
—
(9)
VI
DC input voltage
VCCIO_PIO = 1.2 V
–0.3
—
VCCIO_PIO + 0.3
V
continued...
(5)
(6)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
The use of Power Management Bus (PMBus*™) voltage regulator dedicated to Intel Agilex SmartVID devices is mandatory. The PMBus
voltage regulator and Intel Agilex SmartVID devices are connected via PMBus.
(7)
(8)
The typical value is based on the SmartVID programmed value.
You need to always power up VCCBAT. If you do not use the design security feature in Intel Agilex devices, connect VCCBAT to a 1.8 V
power supply. Intel Agilex power-on reset (POR) circuitry monitors VCCBAT
.
(9)
This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the
maximum value.
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Symbol
Description
Condition
Minimum(5)
Typical
Maximum(5)
Unit
V
VCCIO_PIO = 1.5 V
0
—
—
1.7
VCCIO_SDM, VCCIO_HPS
1.8 V
=
–0.3
VCCIO_SDM + 0.3,
VCCIO_HPS + 0.3
V
VO
TJ
Output voltage
—
0
0
—
—
—
—
VCCIO_PIO
100
V
Operating junction
temperature
Extended
Industrial
Standard POR
°C
°C
—
–40(10)
250 μs
100
(11) (12) (13)
tRAMP
Power supply ramp
time
100 ms
(5)
This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The
voltage ripple includes both regulator DC ripple and the dynamic noise.
(10)
E-tile supports an operating temperature range of –40°C to 100°C. However, the E-tile transceivers may experience a higher error
rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended
operating temperature range for E-tile protocol-compliant transceiver links is –20°C to 100°C. The maximum temperature ramp rate
is 2°C per minute.
(11)
This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL =
0 and tRAMP specifications for fast POR when HPS_PORSEL = 1.
(12)
(13)
tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
To support AS fast mode, all power supplies to the Intel Agilex device must be fully ramped-up within 10 ms to the recommended
operating conditions.
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Transceiver Power Supply Operating Conditions
Table 7.
E-Tile Transceiver Power Supply Operating Conditions
For specification status, see the Data Sheet Status table
Symbol
Description
Typical DC Level Recommended DC Recommended VR Recommended AC
Maximum (DC
Setpoint + Ripple
+ AC Transient)
Unit
(V)
Setpoint (% of
Vnominal
Ripple (% of
Vnominal
Transient (% of
)
)
Vnominal)
(% of Vnominal
)
(14)
VCCRT_GXE
Transceiver power
supply
0.9
0.9
0.9
1.1
2.5
± 0.5%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
± 2.5%
± 2.5%
± 2.5%
± 3%
V
V
V
V
V
VCC_HSSI_GXE
VCCRTPLL_GXE
VCCH_GXE
E-tile digital signal
power supply
± 3%
± 3%
± 3%
± 5%
(14)
Transceiver PLL
power supply
Analog power
supply
± 0.5%
± 0.5%
± 2%
VCCCLK_GXE
LVPECL REFCLK
power supply
± 3.5%
Table 8.
P-Tile Transceiver Power Supply Operating Conditions
The specifications below should be met at the board vias directly connected to the package power balls. Place the VR sense point in the FPGA pinfield (in the
package shadow), as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.
For specification status, see the Data Sheet Status table
Symbol
Description
Typical DC Level Recommended DC Recommended VR Recommended AC
Maximum (DC
Setpoint + Ripple
+ AC Transient)
Unit
(V)
Setpoint (% of
Vnominal
Ripple (% of
Vnominal
Transient (% of
Vnominal
)
)
)
(% of Vnominal
)
VCCRT_GXP
Transceiver power
supply
0.9
0.9
± 0.5%
± 0.5%
± 2.5%
± 2.5%
± 3%
V
VCC_HSSI_GXP
P-tile digital signal
power supply
± 3%
V
continued...
(14)
The difference between VCCRT/VCCRTPLL and VCCH should be no less than 200 mV.
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Symbol
Description
Typical DC Level Recommended DC Recommended VR Recommended AC
Maximum (DC
Setpoint + Ripple
+ AC Transient)
Unit
(V)
Setpoint (% of
Vnominal
Ripple (% of
Vnominal
Transient (% of
)
)
Vnominal)
(% of Vnominal
)
VCCFUSE_GXP
P-tile efuse power
supply
0.9
1.8
1.8
± 0.5%
± 0.5%
± 0.5%
± 2.5%
± 3%
V
V
V
VCCCLK_GXP
P-tile I/O buffer
power supply
± 0.5%
± 0.5%
± 2%
± 2%
± 3%
± 3%
VCCH_GXP
High voltage power
for Transceiver
HPS Power Supply Operating Conditions
Table 9. HPS Power Supply Operating Conditions for Intel Agilex Devices
This table lists the steady-state voltage and current values expected for Intel Agilex system-on-a-chip (SoC) devices with ARM-based hard processor system
(HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Intel Agilex Devices table for the
steady-state voltage values expected from the FPGA portion of the Intel Agilex SoC devices.
For specification status, see the Data Sheet Status table
Symbol
VCCL_HPS
Description
Condition
Minimum
Typical
Maximum
Unit
HPS core voltage and
periphery circuitry
power supply
Performance boost,
fixed voltage: –1V
0.87
0.9
0.93
V
SmartVID: –1V, –2V, –
3V, –3E
(Typical) – 3%
0.685 – 0.85
(Typical) + 3%
V
Fixed voltage: –4F
0.776
0.87
0.8
0.9
0.824
0.93
V
V
VCCPLLDIG_HPS
HPS PLL digital power
supply (can be
Performance boost,
fixed voltage: –1V
connected to VCCL_HPS
)
SmartVID: –1V, –2V, –
3V, –3E
(Typical) – 3%
0.685 – 0.85
(Typical) + 3%
V
Fixed voltage: –4F
1.8 V
0.776
1.71
0.8
1.8
0.824
1.89
V
V
VCCPLL_HPS
HPS PLL analog power
supply
VCCIO_HPS
HPS I/O buffers power 1.8 V
supply
1.71
1.8
1.89
V
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Related Information
•
Recommended Operating Conditions on page 10
Provides the steady-state voltage values for the FPGA portion of the device.
•
HPS Clock Performance on page 47
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Intel FPGA Power and Thermal Calculator and the Intel Quartus®
Prime Power Analyzer feature.
Use the Intel FPGA Power and Thermal Calculator before you start your design to estimate the supply current for your design.
The Intel FPGA Power and Thermal Calculator provides a magnitude estimate of the device power because these currents vary
greatly with the usage of the resources.
The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you
complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Table 10.
I/O Pin Leakage Current for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Input pin
Tri-stated I/O pin
Condition
Min
Max
250
250
Unit
µA
II
VI = 0 V to VCCIO_PIO (MAX)
VO = 0 V to VCCIO_PIO (MAX)
–250
–250
IOZ
µA
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.
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Table 11.
Bus Hold Parameters for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Parameter
Symbol
Condition
VCCIO_PIO (V)
1.2
Unit
Min
Max
Bus-hold, low, sustaining
current
ISUSL
ISUSH
IODL
VIN > VIL (max)
30
—
µA
µA
µA
µA
V
Bus-hold, high, sustaining
current
VIN < VIH (min)
0 V < VIN < VCCIO_PIO
0 V < VIN < VCCIO_PIO
—
–30
—
—
Bus-hold, low, overdrive
current
1,200
–1,200
0.9
Bus-hold, high, overdrive
current
IODH
—
Bus-hold trip point
VTRIP
0.3
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to
the calibration block.
Table 12.
OCT Calibration Accuracy Specifications for Intel Agilex Devices
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
These specifications require RZQ reference accuracy of 240 Ω ±1%.
For specification status, see the Data Sheet Status table
Symbol
34-Ω and 40-Ω RS
Description
Condition (V)
VCCIO_PIO = 1.2
Calibration Accuracy
Unit
Internal series termination with
calibration (34-Ω and 40-Ω
setting)
±15
%
50-Ω and 60-Ω RT
Internal parallel termination with SSTL-12 and HSTL-12 I/O
–10 to +60
±15
%
calibration (50-Ω and 60-Ω
setting)
standards
POD12 I/O standard
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OCT Without Calibration Resistance Tolerance Specifications
Table 13.
OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices
This table lists the Intel Agilex OCT without calibration resistance tolerance to PVT changes.
For specification status, see the Data Sheet Status table
Symbol
34-Ω and 40-Ω RS
Description
Condition (V)
VCCIO_PIO = 1.2
Calibration Accuracy
Unit
Internal series termination
without calibration (34-Ω and
40-Ω setting)
–30 to +60
%
100-Ω RD
Internal differential termination
(100-Ω setting)
VCCIO_PIO = 1.5
±40
%
Pin Capacitance
Table 14.
Pin Capacitance for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Input/output capacitance of I/O pins
Maximum
2.5(15)
Unit
CIO
pF
Internal Weak Pull-Up Resistor
All I/O pins, except configuration and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration
I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.
Table 15.
Internal Weak Pull-Up Resistor Values for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Condition (V)
Min
Typ
Max
Unit
RPU
Value of the I/O pin
pull-up resistor before
and during
VCCIO_PIO = 1.2 ±5%
3
10
30
kΩ
configuration, as well
as user mode if you
(15)
This value refers to die-level pin capacitance without the device package.
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Symbol
Description
Condition (V)
Min
Typ
Max
Unit
have enabled the
programmable pull-up
resistor option.
Related Information
Intel Agilex Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH
and IOL) for various I/O standards supported by Intel Agilex devices.
For minimum voltage values, use the minimum VCCIO_PIO values. For maximum voltage values, use the maximum VCCIO_PIO
values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Related Information
Recommended Operating Conditions on page 10
Single-Ended I/O Standards Specifications
Table 16.
Single-Ended I/O Standards Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
I/O Standard
VCCIO_PIO (V)
VIL (V)
VIH (V)
Min
Typ
Max
Min
Max
Min
0.65 × VCCIO_PIO
Max
1.2 V LVCMOS (16)
1.14
1.2
1.26
–0.3
0.35 × VCCIO_PIO
VCCIO_PIO + 0.3
Related Information
1.2 V I/O Interface Voltage Level Compatibility section, Intel Agilex General Purpose I/O and LVDS SERDES User Guide
Provides output voltage swing calculation examples.
(16)
Refer to Intel Agilex General Purpose I/O and LVDS SERDES User Guide for output voltage swing calculation example.
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Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
Table 17.
Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
I/O Standard
VCCIO_PIO (V)
VREF (V)
Typ
VTT (V)
Typ
Min
Typ
Max
Min
Max
Min
Max
SSTL-12
HSTL-12
HSUL-12
POD12
1.14
1.2
1.26
0.49 ×
VCCIO_PIO
0.5 × VCCIO_PIO
0.51 ×
VCCIO_PIO
0.475 ×
VCCIO_PIO
0.5 × VCCIO_PIO
0.525 ×
VCCIO_PIO
1.14
1.14
1.14
1.2
1.2
1.2
1.26
1.26
1.26
0.47 ×
VCCIO_PIO
0.5 × VCCIO_PIO
0.5 × VCCIO_PIO
0.53 ×
VCCIO_PIO
0.475 ×
VCCIO_PIO
0.5 × VCCIO_PIO
0.525 ×
VCCIO_PIO
0.49 ×
VCCIO_PIO
0.51 ×
VCCIO_PIO
—
—
—
—
Internally
calibrated
—
—
VCCIO_PIO
—
Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
Table 18.
Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
I/O Standard
VIL(DC) (V)
Max
VIH(DC) (V)
Min
VIL(AC) (V)
Max
VIH(AC) (V)
Min
SSTL-12
HSTL-12
HSUL-12
VREF – 0.075
VREF – 0.080
VREF – 0.100
VREF – 0.055
VREF + 0.075
VREF + 0.080
VREF + 0.100
VREF + 0.055
VREF – 0.100
VREF – 0.150
VREF – 0.135
VREF – 0.070
VREF + 0.100
VREF + 0.150
VREF + 0.135
VREF + 0.070
POD12(17)
Note:
For output voltage swing calculation example, refer to the Intel Agilex General Purpose I/O and LVDS SERDES User Guide.
(17)
This specification is defined over internal Vref range from 0.6 × VCCIO_PIO to 0.92 × VCCIO_PIO
.
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Related Information
1.2 V I/O Interface Voltage Level Compatibility section, Intel Agilex General Purpose I/O and LVDS SERDES User Guide
Provides output voltage swing calculation examples.
Differential SSTL, HSTL, and HSUL I/O Standards Specifications
Table 19.
Differential SSTL, HSTL, and HSUL I/O Standards Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
I/O
Standard
VCCIO_PIO (V)
VILdiff(DC) VIHdiff(DC) VILdiff(AC) VIHdiff(AC)
VIX(AC) (V)
Typ
VOX(AC) (V)
(V)
(V)
Min
0.15
(V)
Max
–0.2
(V)
Min
0.2
Min
Typ
Max
Max
–0.15
Min
Max
Min
Typ
Max
SSTL-12
HSTL-12
HSUL-12
1.14
1.2
1.26
0.5 ×
VCCIO_PIO
– 0.12
0.5 ×
VCCIO_PIO
0.5 ×
VCCIO_PIO
+ 0.12
0.5 ×
VCCIO_PIO
– 0.12
0.5 ×
VCCIO_PIO
0.5 ×
VCCIO_PIO
+ 0.12
1.14
1.14
1.2
1.2
1.26
1.26
–0.16
–0.2
0.16
0.2
–0.3
0.3
0.5 ×
VCCIO_PIO
– 0.12
0.5 ×
VCCIO_PIO
0.5 ×
VCCIO_PIO
+ 0.12
0.5 ×
VCCIO_PIO
– 0.12
0.5 ×
VCCIO_PIO
0.5 ×
VCCIO_PIO
+ 0.12
–0.27
0.27
0.5 ×
VCCIO_PIO
– 0.12
0.5 ×
VCCIO_PIO
0.5 ×
VCCIO_PIO
+ 0.12
0.5 ×
VCCIO_PIO
– 0.12
0.5 ×
VCCIO_PIO
0.5 ×
VCCIO_PIO
+ 0.12
Differential POD I/O Standards Specifications
Table 20.
Differential POD I/O Standards Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
I/O Standard
VCCIO_PIO (V)
VILdiff(DC) (V)
Max
VIHdiff(DC) (V)
VILdiff(AC) (V)
VIHdiff(AC) (V)
Min
VIX(AC) (%)(18)
Min
Typ
Max
Min
Max
Max
POD12
1.14
1.2
1.26
–0.11
0.11
–0.14
0.14
25
(18)
Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
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Differential I/O Standards Specifications
Table 21.
Differential I/O Standards Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
I/O
Standard
VCCIO_PIO (V)
Typ
VID (mV)(19)
VICM(DC) (V)
VOD (V)(20) (21)
Typ
VOCM (V)(20)
Typ
Min
Max
Min
Max
Min
Conditio
n
Max
Min
Max
Min
Max
True
Differenti
al
Signaling
(Transmi
tter &
1.455
1.5
1.2
1.545
100
600
600
0.3
Data rate
≤700
Mbps
1.4
0.247
—
0.454
0.99
1.1
1.21
0.9
Data rate
>700
Mbps
1.4
Receiver)
(22)
True
Differenti
al
Signaling
(Receiver
only)(22)
1.14
1.26
100
0.3
0.9
Data rate
≤700
Mbps
1.1
1.1
—
—
—
—
—
—
Data rate
>700
Mbps
Switching Characteristics
This section provides the performance characteristics of Intel Agilex core and periphery blocks.
(19)
(20)
(21)
(22)
The minimum VID value is applicable over the entire common mode range, VCM
RL range: 90 ≤ RL ≤ 110 Ω.
.
The specification is only applicable to default VOD setting.
The True Differential Signaling input buffer is supported on 1.2V and 1.5V VCCIO_PIO bank. The maximum input voltage driven into the
True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.
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Core Performance Specifications
Clock Tree Specifications
Table 22.
Clock Tree Performance for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Parameter
Performance
–2V
Unit
–1V
1,100
–3V, –3E, –4F
Programmable clock routing
1,000
780
MHz
I/O PLL Specifications
Table 23.
I/O PLL Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Parameter
Condition
Min
10
Typ
—
Max
Unit
MHz
MHz
MHz
MHz
fIN
Input clock frequency
–1V
–2V
1,100(23)
900(23)
750(23)
325
10
—
–3V, –3E, –4F
—
10
—
fINPFD
Input clock frequency
to the PFD
10
—
fVCO
I/O PLL VCO operating –1V
600
600
600
0.5
1
—
—
—
—
—
1,600
1,434
1,250
10
MHz
MHz
MHz
MHz
range
–2V
–3V, –3E, –4F
fCLBW
I/O PLL closed-loop
bandwidth
I/O bank I/O PLL
Fabric-feeding I/O PLL
10
MHz
continued...
(23)
This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
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Symbol
tEINDUTY
Parameter
Condition
Min
Typ
Max
Unit
Input clock or external
feedback clock input
duty cycle
—
40
—
60
%
fOUT
Output frequency for
internal clock (C
counter)
–1V
–2V
—
—
—
—
—
—
45
—
—
—
—
—
—
50
1,100
900
750
800
720
650
55
MHz
MHz
MHz
MHz
MHz
MHz
%
–3V, –3E, –4F
fOUT_EXT
Output frequency for
external clock output
–1V
–2V
–3V, –3E, –4F
—
tOUTDUTY
Duty cycle for
dedicated external
clock output (when set
to 50%)
(24)
tFCOMP
External feedback
clock compensation
time
—
—
—
5
ns
fDYCONFIGCLK
Dynamic configuration
clock for mgmt_clk
—
—
—
—
—
—
100
1
MHz
ms
tLOCK
Time required to lock
from end-of-device
configuration or
deassertion of areset
tDLOCK
Time required to lock
dynamically (after
switchover or
reconfiguring any non-
post-scale counters/
delays)
—
—
—
—
—
—
1
ms
tPLL_PSERR
Accuracy of PLL phase
shift
±50
ps
continued...
(24)
Not applicable for fabric-feeding I/O PLL.
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
tARESET
Minimum pulse width
on the areset signal
—
10
—
—
ns
tREFPJ
Reference phase jitter
(rms)
Carrier frequency: 100
MHz with integrated
bandwidth of 10 kHz
to 50 MHz
—
—
1.42
ps
tREFPN
Reference phase
noise(25)
10 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–90
–100
–110
–120
–130
–138
–142
–144
17.5
175
dBc/Hz
dBc/Hz
100 Hz
1 KHz
dBc/Hz
10 KHz
100 KHz
1 MHz
dBc/Hz
dBc/Hz
dBc/Hz
10 MHz
100 MHz
dBc/Hz
dBc/Hz
(24)
(26)
tOUTPJ_DC
Period jitter for
dedicated clock output
fREF < 100 MHz
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
(26)
fREF ≥ 100 MHz
(24)
(26)
tOUTCCJ_DC
Cycle-to-cycle jitter
for dedicated clock
output
fREF < 100 MHz
17.5
175
(26)
fREF ≥ 100 MHz
(27)
(26)
tOUTPJ_IO
Period jitter for clock
output on the regular
I/O
fREF < 100 MHz
60
(26)
fREF ≥ 100 MHz
600
ps (p-p)
continued...
(25)
The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100
MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK
phase noise at 100 MHz + (20 × log10 (f/100))
(26)
(27)
fREF is fIN/N, specification applies when N = 1.
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory
Output Clock Jitter Specifications for Intel Agilex Devices table.
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Symbol
Parameter
Condition
Min
—
Typ
—
Max
60
Unit
(27)
(26)
tOUTCCJ_IO
Cycle-to-cycle jitter
for clock output on the
regular I/O
fREF < 100 MHz
fREF ≥ 100 MHz
fREF < 100 MHz
fREF ≥ 100 MHz
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
(26)
—
—
600
17.5
175
(24)
(26)
(26)
tCASC_OUTPJ_DC
Period jitter for
dedicated clock output
in cascaded PLLs
—
—
—
—
Related Information
Memory Output Clock Jitter Specifications on page 39
Provides more information about the external memory interface clock output jitter specifications.
DSP Block Specifications
Table 24.
DSP Block Performance Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Mode
Performance
Unit
–1V
–2V
–3V, –3E
–4F
Fixed-point 18 × 19
multiplication mode
900
771
676
600
MHz
MHz
Fixed-point 27 × 27
900
900
771
771
676
676
600
600
multiplication mode(28)
Fixed-point 18 × 19
MHz
multiplier adder mode(28)
continued...
(28)
When Chainout is enabled but systolic registers are not used, the performance specifications for the following speed grades are as
follows:
• –1V: 675 MHz
• –2V: 578 MHz
• –3V and –3E: 507 MHz
• –4F: 450 MHz
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Mode
Performance
Unit
–1V
–2V
–3V, –3E
–4F
Fixed-point 18 × 19
900
771
676
600
MHz
multiplier adder summed
with 36-bit input mode
Fixed-point 18 × 19
systolic mode
900
900
771
771
676
676
600
600
MHz
MHz
Fixed-point 18 × 19
complex multiplication
mode
Fixed-point four 9 × 9
900
750
750
750
771
579
579
579
676
507
507
507
600
475
475
475
MHz
MHz
MHz
MHz
multiplier adder mode(28)
FP32 floating-point
multiplication mode
FP32 floating-point adder
or subtract mode
FP32 floating-point
multiplier adder or
subtract mode
FP32 floating-point
multiplier accumulate
mode
750
750
579
579
507
507
475
475
MHz
MHz
Addition or subtraction of
two FP16 floating-point
multiplication mode
FP32 floating-point
complex multiplication
750
750
750
750
579
579
579
579
507
507
507
507
475
475
475
475
MHz
MHz
MHz
MHz
FP32 floating-point direct
vector dot product
FP16 floating-point
complex multiplication
FP16 floating-point direct
vector dot product
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Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from
an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block
clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX
.
Table 25.
Memory Block Performance Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Memory
Mode
Performance
Unit
–1V
–2V
–3V, –3E
–4F
MLAB
Single-port RAM/ROM
Simple dual-port RAM
1,000
782
667
600
MHz
MHz
Simple dual-port RAM
with read-during-write
option
630
510
460
330
M20K Block(29)
Single-port RAM/ROM
Simple dual-port RAM
1000 (HS)
850 (LP)
782 (HS)
664 (LP)
667 (HS)
567 (LP)
600 (HS)
510 (LP)
MHz
MHz
MHz
Simple dual-port RAM,
coherent read enabled
1000 (HS)
850 (LP)
782 (HS)
664 (LP)
667 (HS)
567 (LP)
600 (HS)
510 (LP)
Single-port RAM with
the read-during-write
option set to Old Data
800 (HS)
680 (LP)
640 (HS)
540 (LP)
560 (HS)
476 (LP)
480 (HS)
410 (LP)
Simple dual-port RAM
with the read-during-
write option set to Old
Data
Simple dual-port RAM
with ECC enabled, 512
× 32
600 (HS)
500 (LP)
480 (HS)
400 (LP)
420 (HS)
357 (LP)
360 (HS)
300 (LP)
MHz
continued...
(29)
For M20K block, timing/power optimization feature is available. The available options are High Speed (HS) and Low Power (LP). For
details on this timing/power optimization feature, refer to the Agilex Embedded Memory User Guide.
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Memory
Mode
Performance
Unit
–1V
–2V
–3V, –3E
–4F
Simple dual-port RAM
with ECC, optional
pipeline registers
1000 (HS)
850 (LP)
782 (HS)
664 (LP)
667 (HS)
567 (LP)
600 (HS)
510 (LP)
MHz
MHz
enabled, 512 × 32
Dual-port ROM
600 (HS)
500 (HS)
420 (HS)
360 (HS)
True dual-port RAM
Simple quad-port RAM
Simple dual-port
600 (HS)
750
480 (HS)
640
420 (HS)
500
360 (HS)
500
MHz
MHz
eSRAM
Local Temperature Sensor Specifications
Table 26.
Local Temperature Sensor Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Description
Local Temperature Sensor
Temperature Range
Accuracy
Sampling Rate
1 KSPS
Conversion Time
–40 to 125 °C(30)
±5 °C
< 1 ms
Remote Temperature Diode Specifications
Note the following for the remote temperature diode specifications:
•
•
•
The typical value is at 25°C.
Diode accuracy improves with lower injection current.
Absolute accuracy is dependent on third-party external diode ADC and integration specifics.
(30)
Temperature range refers to junction temperature.
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Table 27.
Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD)
For specification status, see the Data Sheet Status table
Description
Min
10
Typ
Max
170
0.75
<3
Unit
μA
V
Ibias, diode source current
Vbias, voltage across diode
Series resistance
—
—
0.43
—
—
Ω
Diode ideality factor
—
1.006(31)
—
—
Table 28.
Remote Temperature Diode Specifications for Intel Agilex Devices (E-Tile TSD)
For specification status, see the Data Sheet Status table
Description
Min
100
0.56
—
Typ
—
Max
170
0.8
< 2
—
Unit
μA
V
Ibias, diode source current
Vbias, voltage across diode
Series resistance
—
—
Ω
Diode ideality factor
—
1.008
—
Table 29.
Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD)
For specification status, see the Data Sheet Status table
Description
Min
10
Typ
Max
170
0.87
<10
—
Unit
μA
V
Ibias, diode source current
Vbias, voltage across diode
Series resistance
—
0.56
—
—
—
Ω
Diode ideality factor
—
1.0108(32)
—
(31)
(32)
When using lower injection current (two-currents) implementation, the ideality factor is 1.009.
When using lower injection current (two-currents) implementation, the ideality factor is 1.03.
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Voltage Sensor Specifications
Table 30.
Voltage Sensor Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Parameter Minimum
Typical
Maximum
Unit
Bit
Resolution
—
—
—
—
—
—
—
7
—
1
Sampling rate
—
—
—
—
—
—
KSPS
LSB
LSB
pF
Differential non-linearity (DNL)
Integral non-linearity (INL)
±1
±1
40
Input capacitance
Voltage sensor accuracy, Vin range: 0 V to 1.249 V
3.5
1.49
%
Unipolar Input Mode
Input signal range for
Vsigp
V
Common mode voltage on
Vsign
—
—
—
—
0.25
1.24
V
V
Input signal range for
Vsigp – Vsign
Periphery Performance Specifications
This section describes the periphery performance, LVDS SERDES, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and
perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable
frequency in your system.
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LVDS SERDES Specifications
Table 31.
LVDS SERDES Specifications for Intel Agilex Devices
LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 3 to 10.
DDR registers support SERDES factor J = 1 to 2.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
For specification status, see the Data Sheet Status table
Paramet Symbol Conditio
–1 Speed Grade
–2 Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
er
n
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Clock
frequen
cy
fHSCLK_in
(input
clock
Clock
boost
factor W
= 1 to
10
—
800
10
—
700
10
—
625
10
—
625
MHz
frequen
cy) True 40(33)
Differen
tial I/O
Standar
ds
fHSCLK_in
(input
clock
frequen
cy)
Clock
boost
factor W
= 1 to
40(33)
10
—
625
10
—
625
10
—
525
10
—
525
MHz
Single-
Ended
I/O
Standar
ds
continued...
(33)
Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
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Paramet Symbol Conditio
er
–1 Speed Grade
Typ
–2 Speed Grade
Typ
–3 Speed Grade
Typ
–4 Speed Grade
Typ
Unit
n
Min
Max
800(34)
Min
Max
700(34)
Min
Max
625(34)
Min
Max
625(34)
fHSCLK_O
—
—
—
—
—
—
—
—
—
MHz
UT
(output
clock
frequen
cy)
Transmit True
ter Differen
SERDES
factor J
= 4 to
150
—
1,600
150
—
1,434
150
—
1,250
150
—
1,000
Mbps
tial I/O
Standar
ds -
10(36)
(37) (38)
fHSDR
SERDES
factor J
150
150
—
—
1,200
150
150
—
—
1,076
150
150
—
—
938
150
150
—
—
600
Mbps
Mbps
(data
rate)(35)
= 3(36)
(37) (38)
(39)
(39)
(39)
SERDES
factor J
= 2,
840(39)
uses
DDR
register
s
continued...
(34)
(35)
(36)
This is achieved by using the PHY clock network.
Requires package skew compensation with PCB trace length.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain
which is design dependent and requires timing analysis.
(37)
(38)
The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you
use. The I/O differential buffer and serializer do not have a minimum toggle rate.
(39)
The maximum ideal data rate is the SERDES factor (J) × the PLL maximum output frequency (fOUT) provided you can close the design
timing and the signal integrity meets the interface requirements.
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Paramet Symbol Conditio
–1 Speed Grade
Typ
–2 Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
er
n
Min
Max
420(39)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
(39)
(39)
(39)
SERDES
factor J
= 1,
150
—
150
—
150
—
150
—
Mbps
uses
DDR
register
s
tx Jitter
True
Differen
tial I/O
Standar
ds
-
Total
jitter for
data
rate,
600
Mbps –
1.6
—
—
160
—
—
200
—
—
250
—
—
350
ps
Gbps
Total
jitter for
data
rate, <
600
Mbps
—
—
0.1
55
—
—
0.12
—
—
0.15
—
—
0.21
UI
%
tDUTY
TX
45
50
45
50
55
45
50
55
45
50
55
(40)
output
clock
duty
cycle for
Differen
tial I/O
Standar
ds
tRISE
&
True
—
—
160
—
—
180
—
—
200
—
—
220
ps
(37)
tFALL
Differen
tial I/O
Standar
ds
(41)
continued...
(40)
(41)
Not applicable for DIVCLK = 1.
This applies to default pre-emphasis and VOD settings only.
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Paramet Symbol Conditio
er
–1 Speed Grade
–2 Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
n
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
(35)
TCCS
True
—
—
330
—
—
330
—
—
330
—
—
330
ps
(40)
Differen
tial I/O
Standar
ds
Receiver True
SERDES
factor J
= 4 to
150
—
1,600
150
—
1,434
150
—
1,250
150
—
1,000
Mbps
Differen
tial I/O
Standar
ds -
10(36)
(37) (38)
fHSDRDPA
(data
rate)
SERDES
factor J
150
—
—
—
1,200
150
—
—
—
1,076
150
—
—
—
938
150
—
—
—
600
Mbps
Mbps
Mbps
= 3(36)
(37) (38)
(38)
(42)
(38)
(42)
(38)
(42)
(38)
(42)
fHSDR
(data
rate)
SERDES
factor J
= 3 to
(without 10
DPA)(35)
(38)
(39)
(38)
(39)
(38)
(39)
(38)
(39)
SERDES
factor J
= 2,
uses
DDR
register
s
(38)
(39)
(38)
(39)
(38)
(39)
(38)
(39)
SERDES
factor J
= 1,
—
—
—
—
Mbps
uses
DDR
register
s
continued...
(42)
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
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Paramet Symbol Conditio
–1 Speed Grade
Typ
–2 Speed Grade
Typ
–3 Speed Grade
Typ
–4 Speed Grade
Typ Max
Unit
UI
er
n
Min
Max
Min
Max
Min
Max
Min
DPA
(FIFO
DPA run
length
—
—
—
—
—
10,000
—
—
—
—
10,000
—
—
—
—
10,000
—
—
—
—
10,000
mode)
DPA
(soft
CDR
DPA run
length
SGMII/
GbE
protocol
—
—
5
—
—
5
—
—
5
—
—
5
UI
mode)
All other
protocol
s
50 data
transitio
n per
50 data
transitio
n per
50 data
transitio
n per
50 data
transitio
n per
—
208 UI
208 UI
208 UI
208 UI
Soft
CDR
mode
Soft-
CDR
ppm
toleranc
e
—
–300
—
—
—
300
–300
—
—
—
300
–300
—
—
—
300
–300
—
—
—
300
ppm
ps
Non
DPA
Samplin
g
—
330
330
330
330
mode
Window
DPA Lock Time Specifications
Table 32.
DPA Lock Time Specifications for Intel Agilex Devices
The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1- to-0 transition.
For specification status, see the Data Sheet Status table
Standard
Training Pattern
Number of Data Transitions in
One Repetition of the Training
Pattern
Number of Repetitions per
256 Data Transitions(43)
Maximum Data Transition
SPI-4
00000000001111111111
00001111
2
2
128
128
768
Parallel Rapid I/O
768
continued...
(43)
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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Standard
Training Pattern
Number of Data Transitions in
One Repetition of the Training
Pattern
Number of Repetitions per
256 Data Transitions(43)
Maximum Data Transition
10010000
10101010
01010101
4
8
8
64
32
32
768
768
768
Miscellaneous
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Figure 2.
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps
25
8.5
0.28
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
(43)
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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Table 33.
LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
For specification status, see the Data Sheet Status table
Parameter
Jitter Frequency (Hz)
10,000
Sinusoidal Jitter (UI)
F1
F2
F3
F4
25
25
17,565
1,493,000
0.28
0.28
50,000,000
Figure 3.
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
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Memory Standards Supported by the Hard Memory Controller
Table 34.
Memory Standards Supported by the Hard Memory Controller for Intel Agilex Devices
This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
For specification status, see the Data Sheet Status table
Memory Standard
Rate Support
Maximum Frequency (MHz)
DDR4 SDRAM
Quarter rate
1,600
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
Memory Standards Supported by the Soft Memory Controller
Table 35.
Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices
This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
For specification status, see the Data Sheet Status table
Memory Standard
Rate Support
Quarter rate
Quarter rate
Maximum Frequency (MHz)
RLDRAM 3(44)
QDR IV SRAM
1,200
1,066
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
(44)
For Intel Agilex RLDRAM 3, Intel only provides the PHY-only option.
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Memory Standards Supported by the HPS Hard Memory Controller
Table 36.
Memory Standards Supported by the HPS Hard Memory Controller for Intel Agilex Devices
This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
For specification status, see the Data Sheet Status table
Memory Standard
Rate Support
Quarter rate
Half rate
Maximum Frequency (MHz)
DDR4 SDRAM
1,600
1,333
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
DLL Range Specifications
Table 37.
DLL Frequency Range Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Parameter Performance (for All Speed Grades)
DLL operating frequency range
Unit
MHz
MHz
600 – 1,600
DLL reference clock input
Minimum 600
Memory Output Clock Jitter Specifications
The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential
signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel
recommends using PHY clock networks for better jitter performance.
The memory clock output jitter is within the JEDEC specifications when the phase jitter (integration bandwidth 10 kHz to 50
MHz) of the input clock is not more than 20 ps peak-to-peak, or 1.42 ps RMS at 1e-12 BER and 1.22 ps at 1e-16 BER.
E-Tile Transceiver Performance Specifications
This section provides E-tile transceiver specifications and timing for Intel Agilex devices.
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E-Tile Transceiver Performance
Table 38.
E-Tile Transmitter and Receiver Data Rate Performance Specifications
For specification status, see the Data Sheet Status table
Symbol/Description Condition
Transceiver Speed Grade
Unit
-1
-2
28.3
56
-3
17.4
32
Supported data rate(45)
NRZ
28.9
Gbps
Gbps
PAM4
57.8(46)
E-Tile Transceiver Reference Clock Specifications
Table 39.
E-Tile Reference Clock LVPECL DC Electrical Characteristics
For specification status, see the Data Sheet Status table
Symbol
Refclk Parameter
Min
Typ
Max
Unit
VTT
VTT
Termination Voltage (2.5 V
compliant)
0.4
0.5
0.6
V
Termination Voltage (3.3 V
compliant)
1.04
1.3
1.56
V
RTT
Termination Resistor
Differential Voltage
40
0.4
50
0.8
—
60
Ω
V
VDIFF
VCM
1.2
Input Common Mode
Voltage (2.5 V compliant,
no internal termination
resistor)
VDIFF/2
VCCCLK_GXE - VDIFF/2
V
continued...
(45)
The supported data rate is for chip-to-chip and backplane links.
Two channels are combined to support up to 57.8 Gbps.
(46)
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Symbol
Refclk Parameter
Min
Typ
Max
Unit
Input Common Mode
Voltage (2.5 V compliant,
internal termination
resistor)
VCCCLK_GXE - 1.6
VCCCLK_GXE - 1.3
VCCCLK_GXE - 1.0
V
Input Common Mode
Voltage (3.3 V compliant,
no internal termination
resistor)
VDIFF/2
—
2
VCCCLK_GXE - VDIFF/2
V
V
Input Common Mode
Voltage (3.3 V compliant,
internal termination
resistor)
1.4
2.6
Table 40.
E-Tile Reference Clock Electrical and Jitter Requirements
For specification status, see the Data Sheet Status table
Parameter
Condition
Min
125
-100
45
40
—
Typ
156.25
—
Max
700
100
55
Unit
MHz
Frequency
—
—
—
Frequency Tolerance
Clock Duty Cycle
Rise/Fall Times
Phase Jitter
ppm
50
%
20% to 80%
12 kHz to 20 MHz
10 kHz
—
300
0.5
ps
0.375
—
ps rms
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise(47)
—
-130
-138
-138
-140
-144
-146
100 kHz
—
—
500 kHz
—
—
3 MHz
—
—
10 MHz
—
—
20 MHz
—
—
(47)
The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of
156.25 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) =
REFCLK phase noise at 156.25 MHz + 20*log10(f/156.25).
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E-Tile Transmitter Specifications
Table 41.
E-Tile Transmitter Specifications
For specification status, see the Data Sheet Status table
Symbol/Description
Transmitter differential
output voltage peak-to-
peak
Condition
Min
Typ
Max
Unit
No precursor/postcursor
de-emphasis
—
0.965
—
V
Transmitter common mode
voltage
—
VCCRT_GXE/2
V
E-Tile Receiver Specifications
Table 42.
E-Tile Receiver Specifications
For specification status, see the Data Sheet Status table
Symbol/Description Condition
Absolute VMAX for a
Min
Typ
Max
Unit
—
—
1.2
V
receiver pin
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before/after
device configuration
1.2
V
VICM (AC coupled)(48)
Receiver run length(49)
DC input impedance
—
—
—
—
VCCRT_GXE
V
—
40
80
—
—
100(50)
60
symbols
Ω
Ω
DC differential input
impedance
100
120
continued...
(48)
(49)
(50)
This value uses internal AC coupling. External coupling capacitors are required beyond the VCCRT_GXE
No additional transition density requirements apply.
.
The incoming data must be statistically DC-balanced.
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Symbol/Description
Condition
Min
Typ
Max
Unit
Powered down DC input
impedance
Receiver pin impedance
when the receiver
termination is powered
down
100k
—
—
Ω
Differential termination
PPM tolerance
From DC to 100 MHz
80
—
100
—
120
750
Ω
Allowed frequency
mismatch between
REFCLK and RX data
ppm
P-Tile Transceiver Performance Specifications
This section provides P-tile transceiver specifications and timing for Intel Agilex devices.
P-Tile Transceiver Performance
Table 43.
P-Tile Transmitter and Receiver Data Rate Performance
For specification status, see the Data Sheet Status table
Symbol/Description
Supported data rate
Condition
PCIe*
Gen 1
Gen 2
Gen 3
Gen 4
Unit
Gbps
2.5
5
8
16
Table 44.
P-Tile PLLA Performance
For specification status, see the Data Sheet Status table
Symbol/Description Condition
Transceiver Speed Grade
Unit
Min
—
Typ
5
Max
—
VCO frequency
—
GHz
MHz
PLL bandwidth (BWTX-
PKG_PLL1)
PCIe 2.5 GT/s
1.5
—
22
PLL peaking (PKGTX-PLL1) PCIe 2.5 GT/s
—
5
—
—
3
dB
PLL bandwidth (BWTX-
PKG_PLL2)
PCIe 5.0 GT/s
16
MHz
PLL peaking (PKGTX-PLL2) PCIe 5.0 GT/s
—
—
1
dB
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Table 45.
P-Tile PLLB Performance
For specification status, see the Data Sheet Status table
Symbol/Description
Condition
Transceiver Speed Grade
Unit
Min
—
2
Typ
8
Max
—
4
VCO frequency
—
GHz
MHz
MHz
dB
PLL bandwidth (BWTX-
PKG_PLL1)
PCIe 8.0 GT/s
PCIe 16.0 GT/s
—
2
—
4
PLL peaking (PKGTX-PLL1) PCIe 8.0 GT/s
PCIe 16.0 GT/s
—
—
—
2
—
2
dB
P-Tile Transceiver Reference Clock Specifications
Table 46.
P-Tile Reference Clock Specifications
For specification status, see the Data Sheet Status table
Symbol/Description
Condition
All Transceiver Speed Grades
Unit
Min
Typ
HCSL
100
Max
Supported I/O Standards
—
—
—
Input Reference Clock
Frequency(51)
99.97
100.03
MHz
Rising Edge Rate(52)
Falling Edge Rate(52)
Duty cycle
—
—
—
—
0.6
0.6
40
—
—
—
—
4
4
V/ns
V/ns
%
60
33
Spread-spectrum
modulating clock
frequency
30
kHz
continued...
(51)
(52)
This number is with spread spectrum clocking (SSC) turned off.
Measured from -150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential
zero crossing.
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Symbol/Description
Condition
All Transceiver Speed Grades
Unit
Min
Typ
Max
Spread-spectrum
downspread
—
—
0 to -0.5
—
%
Absolute VMAX
Absolute VMIN
—
—
—
—
—
1.15
-0.3
—
—
—
V
V
Peak-to-peak differential
input voltage
300
1,500
mV
VICM (DC coupled)
—
—
250
—
—
—
550
150
mV
ps
Cycle to cycle jitter
(TCCJITTER)(53)
TSSC-MAX-PERIOD-SLEW
—
—
—
1,250
ppm/us
P-Tile Transmitter Specifications
Table 47.
P-Tile Transmitter Specifications
For specification status, see the Data Sheet Status table
Symbol/Description Condition
All Transceiver Speed Grades
Unit
Min
Typ
Max
Supported I/O Standards
PCIe
—
High Speed Differential I/O
—
—
Ω
Differential on-chip
termination resistors
80
120
Differential peak-to-peak
voltage for full swing
PCIe 2.5 GT/s
PCIe 5.0 GT/s
PCIe 8.0 GT/s
800
800
800
—
—
—
1,100
1,100
1,100
mV
mV
mV
continued...
(53)
When using PCI Express*, you must meet the reference clock phase jitter requirements as specified in the PCIE Express Card
Electromechanical Specification for 2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications
for 8.0 GT/s in the PCI Express Base Specification Revision 3.0, and Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express
Base Specification Revision 4.0.
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Symbol/Description
Condition
All Transceiver Speed Grades
Unit
Min
800
250
Typ
—
Max
1,100
—
PCIe 16.0 GT/s
mV
mV
Differential peak-to-peak
voltage during EIEOS
PCIe 8.0 GT/s and 16.0
GT/s
—
Lane-to-lane output skew
PCIe 2.5 GT/s
PCIe 5.0 GT/s
PCIe 8.0 GT/s
PCIe 16.0 GT/s
—
—
—
—
—
—
—
—
2.5
2
ns
ns
ns
ns
1.5
1.25
P-Tile Receiver Specifications
Table 48.
P-Tile Receiver Specifications
For specification status, see the Data Sheet Status table
Symbol/Description Condition
All Transceiver Speed Grades
Unit
Min
Typ
Max
Supported I/O Standards
PCIe
High Speed Differential I/O
—
Peak-to-peak differential
input voltage VID (diff p-p)
PCIe 2.5 GT/s(54)
PCIe 5.0 GT/s(54)
PCIe 8.0 GT/s
175(55)
100(55)
25(55)
—
—
—
—
1,200
1,200
mV
mV
mV
(56)
—
(56)
PCIe 16.0 GT/s
25(55)
—
mV
continued...
(54)
(55)
Voltage shown for PCIe 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
For PCIe at 2.5 and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe 8.0 GT/s
and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx
package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
(56)
The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe Express Base
Specification Rev. 4.0 for the generator (TX) launch voltage value.
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Symbol/Description
Condition
All Transceiver Speed Grades
Unit
Min
—
Typ
0
Max
—
VICM (AC coupled)
—
—
V
Differential on-chip
termination resistors
80
—
120
Ω
RESREF(57)
—
167.3
169
170.7
Ω
HPS Performance Specifications
This section provides hard processor system (HPS) specifications and timing for Intel Agilex devices.
HPS Clock Performance
Table 49.
Maximum HPS Clock Frequencies for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Performance
VCCL_HPS (V)
MPU Frequency
(MHz)
L3 Frequency
(MHz)
MPFE Frequency
(MHz)
Rate
DDR Clock (MHz)
DDR (Mb/s per
pin)
(l3_main_free_c
lk)
–1 speed grade
Fixed: 0.9
SmartVID
SmartVID
SmartVID
1,350
1,200
1,000
800
400
400
400
400
400
667
400
667
334
600
300
Quarter
Half
1,600
1,333
1,600
1,333
1,333
1,200
1,200
3,200
2,666
3,200
2,666
2,666
2,400
Quarter
Half
–2 speed grade
–3 speed grade
Quarter
Half
Quarter
2,400
continued...
(57)
Connecting RESREF at 169 Ω calibrates PCIe channel on-chip termination to 85 Ω.
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Performance
VCCL_HPS (V)
MPU Frequency
(MHz)
L3 Frequency
(MHz)
MPFE Frequency
(MHz)
Rate
DDR Clock (MHz)
DDR (Mb/s per
pin)
(l3_main_free_c
lk)
534
267
467
Half
Quarter
Half
1,067
1,067
933
2,133
2,133
1,866
–4 speed grade
Fixed: 0.8
800
400
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the maximum allowed SDRAM operating frequency.
HPS Internal Oscillator Frequency
Table 50.
HPS Internal Oscillator Frequency for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Description
Min
Typ
Max
Unit
Internal Oscillator Frequency
160
370
400
MHz
HPS PLL Specifications
Table 51.
HPS PLL Input Requirements for Intel Agilex Devices
The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the Intel Agilex Device Family Pin Connection Guidelines for information about
assigning this pin.
For specification status, see the Data Sheet Status table
Description
Clock input range
Min
25
—
Typ
—
Max
125
50
Unit
MHz
PPM
%
Clock input accuracy
Clock input duty cycle
—
45
50
55
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Table 52.
HPS PLL Performance for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Description
Main PLL VCO output
Min
—
Max
3,000
3,000
500
Unit
MHz
MHz
MHz
MHz
Peripheral PLL VCO output
h2f_user0_clk(58)
—
—
h2f_user1_clk(58)
—
500
Related Information
Intel Agilex Device Family Pin Connection Guidelines
Provides more information about the HPS_OSC_CLK pin assignment.
HPS SPI Timing Characteristics
Table 53.
SPI Master Timing Requirements for Intel Agilex Devices
You can adjust the input delay timing by programming the rx_sample_dly register.
For specification status, see the Data Sheet Status table
Symbol
Description
Min
Typ
Max
Unit
Tspi_ref_clk
The period of the SPI
internal reference clock,
sourced from
2.5
—
—
ns
l4_main_clk
Tclk
SPIM_CLK clock period
SPIM_CLK duty cycle
SPIM_CLK output jitter
16.67
45
—
50
—
—
55
2
ns
%
%
ns
Tdutycycle
Tck_jitter
Tdio
—
Master-out slave-in
(MOSI) output skew
–3
—
2
continued...
(58)
The HPS PLL provides this clock to the FPGA fabric.
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Symbol
Description
Min
Typ
Max
Unit
(59)
Tdssfrst
SPI_SS_N asserted to first
SPIM_CLK edge
(1.5 × Tclk) – 2
—
—
ns
(59)
Tdsslst
Last SPIM_CLK edge to
SPI_SS_N deasserted
Tclk – 2
—
—
—
—
ns
ns
(60)
Tsu
SPIM_MISO setup time
with respect to SPIM_CLK
capture edge
4.5 – (rx_sample_dly ×
(61)
Tspi_ref_clk
)
(60)
Th
Input hold in respect to
SPIM_CLK capture edge
—
—
ns
1.3 + (rx_sample_dly ×
Tspi_ref_clk
)
(59)
(60)
SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge
depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising
edge.
(61)
Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps)
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Figure 4.
SPI Master Output Timing Diagram
scph* = 0
Tdssfrst
Tdsslst
Tdio (max)
Tdio (min)
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
SPI_MISO
OUT0
OUT1
OUTn
scph* = 1
Tdssfrst
Tdsslst
Tdio (max)
Tdio (min)
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
SPI_MISO
OUT0
OUT1
OUTn
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Figure 5.
SPI Master Input Timing Diagram
scph* = 0
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
SPI_MISO
Tsu
Th
IN0
IN1
INn
scph* = 1
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
SPI_MISO
Tsu
Th
IN0
IN1
INn
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Table 54.
SPI Slave Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Min
Typ
Max
Unit
Tspi_ref_clk
The period of the SPI
internal reference clock,
sourced from
2.5
—
—
ns
l4_main_clk
Tclk
SPIM_CLK clock period
SPIM_CLK duty cycle
30
45
—
50
—
—
55
ns
%
ns
Tdutycycle
Td
Master-in slave-out
(MISO) output skew
(2 × Tspi_ref_clk) + 3
(3 × Tspi_ref_clk) + 11
Tsu
Master-out slave-in
(MOSI) setup time
4
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Th
Master-out slave-in
(MOSI) hold time
9
Tsuss
SPI_SS_N asserted to first
SPIM_CLK edge
Tspi_ref_clk + 4
Thss
Last SPIM_CLK edge to
SPI_SS_N deasserted
Tspi_ref_clk + 4
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Figure 6.
SPI Slave Output Timing Diagram
scph* = 0
Td (max)
Td (min)
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
OUT0
OUT1
OUTn
scph* = 1
Td (max)
Td (min)
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
OUT0
OUT1
OUTn
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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Figure 7.
SPI Slave Input Timing Diagram
scph* = 0
Tsuss
Thss
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
Th
Ts
IN0
IN1
INn
scph* = 1
Tsuss
Thss
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
Ts
Th
IN0
IN1
INn
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
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HPS SD/MMC Timing Characteristics
Table 55.
HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Agilex Devices
These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.
For specification status, see the Data Sheet Status table
Symbol
Tsdmmc_cclk
Description
Min
Typ
Max
Unit
SDMMC_CCLK clock period
(Identification mode)
2,500
—
—
ns
SDMMC_CCLK clock period
(SDR12)
40
20
—
—
—
—
ns
ns
SDMMC_CCLK clock period
(SDR25)
Tdutycycle
Tsdmmc_cclk_jitter
Tsdmmc_clk
SDMMC_CCLK duty cycle
SDMMC_CCLK output jitter
45
—
5
50
—
—
55
2
%
%
ns
Internal reference clock
before division by 4
—
Td
SDMMC_CMD/
—
—
—
3 + (Tsdmmc_clk
×
ns
ns
ns
Tsdmmc_clk × drvsel/2
SDMMC_DATA[7:0] output
drvsel/2)
delay(62)
Tsu
SDMMC_CMD/
6 – (Tsdmmc_clk
×
—
—
SDMMC_DATA[7:0] input
smplsel/2)
setup(63)
Th
SDMMC_CMD/
SDMMC_DATA[7:0] input
hold(63)
0.5 + (Tsdmmc_clk ×
smplsel/2)
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at
1.8 V at power on.
(62)
(63)
When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz
for example, the output delay time is 7.5 to 10.5 ns.
When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200
MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.
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Note:
SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC
interface.
Figure 8.
SD/MMC Timing Diagram
SDMMC_CCLK
Td
SDMMC_CMD and SDMMC_DATA (Out)
SDMMC_CMD and SDMMC_DATA (In)
Command/Data Out
TSU
Th
Command/Data In
HPS USB UPLI Timing Characteristics
Table 56.
HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for
Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Min
—
Typ
16.667
—
Max
—
Unit
ns
Tusb_clk
Td
USB_CLK clock period
Clock to USB_STP/
USB_DATA[7:0] output
delay
2
7
ns
Tsu
Th
Setup time for USB_DIR/
USB_NXT/USB_DATA[7:0]
4
1
—
—
—
—
ns
ns
Hold time for USB_DIR/
USB_NXT/USB_DATA[7:0]
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Figure 9.
USB ULPI Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
TSU Th
USB_DIR and USB_NXT
Note:
The USB interface supports single data rate (SDR) timing only.
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 57.
Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
TX_CLK clock period
TX_CLK clock period
TX_CLK clock period
TX_CLK duty cycle
TX_CLK duty cycle
Min
—
Typ
8
Max
—
Unit
ns
Tclk (1000Base-T)
Tclk (100Base-T)
—
40
400
50
50
—
—
ns
Tclk (10Base-T)
—
—
ns
Tdutycycle (1000Base-T)
Tdutycycle (10/100Base-T)
45
55
60
0.5
%
40
%
(64) (65)
Td
TXD/TX_CTL to TX_CLK
output skew
–0.5
ns
(64)
(65)
Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O
programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.
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Figure 10.
RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
D0
D1
Td
TX_CTL
Table 58.
RGMII RX Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
RX_CLK duty cycle
RX_CLK duty cycle
Min
—
Typ
8
Max
—
Unit
ns
Tclk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tdutycycle (1000Base-T)
Tdutycycle (10/100Base-T)
Tsu
—
40
400
50
50
—
—
ns
—
—
ns
45
40
1
55
60
—
%
%
RX_D/RX_CTL to RX_CLK
setup time
ns
(66)
Th
RX_CLK to RX_D/RX_CTL
hold time
1
—
—
ns
(66)
If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK
by 1.5-2 ns, using the HPS I/O programmable delay.
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Figure 11.
RGMII RX Timing Diagram
RX_CLK
TSU
Th
RX_D[3:0]
RX_CTL
D0
D1
Table 59.
Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Min
Typ
Max
Unit
Tclk
REF_CLK clock period,
sourced by HPS TX_CLK
—
20
—
ns
REF_CLK clock period,
sourced by external clock
source
—
20
—
ns
Tdutycycle_int
Clock duty cycle, REF_CLK
sourced by TX_CLK
35
35
50
50
65
65
%
%
Tdutycycle_ext
Clock duty cycle, REF_CLK
sourced by external clock
source
Table 60.
RMII TX Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Min
Typ
Max
Unit
Td
TX_CLK to TXD/TX_CTL
output data delay
2
—
10
ns
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Figure 12.
RMII TX Timing Diagram
Reference Clock (RX_CLK) (1)
TX_D[1:0]
D0
D1
Td
TX_CTL
Note:
1. For RMII mode, RX_CLK is always used as the reference clock. Refer to the HPS-to-PHY Interface Diagram in the Intel Agilex Hard
Processor System Technical Reference Manual for example system-level topologies.
Table 61.
RMII RX Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Min
2
Typ
—
Max
—
Unit
ns
Tsu
Th
RX_D/RX_CTL setup time
RX_D/RX_CTL hold time
1
—
—
ns
Figure 13.
RMII RX Timing Diagram
Reference Clock (RX_CLK) (1)
TSU
Th
RX_D[1:0]
D0
D1
RX_CTL
Note:
1. For RMII mode, RX_CLK is always used as the reference clock. Refer to the HPS-to-PHY Interface Diagram in the Intel Agilex Hard
Processor System Technical Reference Manual for example system-level topologies.
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Table 62.
Management Data Input/Output (MDIO) Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Min
400
10
Typ
—
Max
—
Unit
ns
Tclk
Td
MDC clock period
MDC to MDIO output data
delay
—
300
ns
Tsu
Th
Setup time for MDIO data
Hold time for MDIO data
10
0
—
—
—
—
ns
ns
Figure 14.
MDIO Timing Diagram
MDC
Td
MDIO_OUT
Dout0
Dout1
TSU
Th
Din0
MDIO_IN
Related Information
HPS-to-PHY Interface Diagrams section, Intel Agilex Hard Processor System Technical Reference Manual
Provides the example system-level topologies.
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HPS I2C Timing Characteristics
Table 63.
HPS I2C Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
Tclk
Serial clock (SCL)
clock period
10
—
2.5
—
μs
Tclk_jitter
I2C clock output jitter
SCL high period
—
4(68)
2
—
2
%
μs
μs
μs
(67)
THIGH
—
—
—
0.6(69)
1.3(72)
0.1
—
—
—
(70)
TLOW
SCL low period
4.7(71)
0.25
TSU;DAT
Setup time for serial
data line (SDA) data
to SCL
(73)
THD;DAT
Hold time for SCL to
SDA data
0
3.15
0
0.6
μs
TVD;DAT and TVD;ACK
SCL to SDA output
data delay
—
3.45(75)
—
0.9(76)
μs
(74)
continued...
(67)
(68)
(69)
(70)
(71)
(72)
(73)
(74)
You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
The recommended minimum setting for ic_ss_scl_hcnt is 440.
The recommended minimum setting for ic_fs_scl_hcnt is 71.
You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
The recommended minimum setting for ic_ss_scl_lcnt is 500.
The recommended minimum setting for ic_fs_scl_lcnt is 141.
THD;DAT is affected by the rise and fall time.
TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
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Symbol
Description
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
TSU;STA
Setup time for a
repeated start
condition
4.7
—
0.6
—
μs
μs
THD;STA
Hold time for a
repeated start
condition
4
—
0.6
—
TSU;STO
Setup time for a stop
condition
4
—
—
0.6
1.3
—
—
μs
μs
TBUF
SDA high pulse
duration between
STOP and START
4.7
(77)
Tscl:r
Tscl:f
Tsda:r
Tsda:f
SCL rise time
SCL fall time
SDA rise time
SDA fall time
—
—
—
—
1,000
300
20
6.54
20
300
300
300
300
ns
ns
ns
ns
(77)
(77)
(77)
1,000
300
6.54
(75)
(76)
(77)
Use maximum SDA_HOLD = 240 to be within the specification.
Use maximum SDA_HOLD = 60 to be within the specification.
Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value,
and total capacitance on the transmission line.
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Figure 15.
I2C Timing Diagram
tSU;DAT
tf
tr
70%
30%
SDA
SCL
tHIGH
tVD;DAT
tHD;DAT
tf
tr
70%
30%
tHD;STA
Tclk
tLOW
tBUF
70%
30%
SDA
SCL
tSU;STA
tHD;STA
tVD;ACK
tSU;STO
70%
30%
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HPS NAND Timing Characteristics
Table 64.
HPS NAND ONFI 1.0 Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Write enable pulse width
Write enable hold time
Read enable pulse width
Read enable hold time
Min
10
7
Max
—
Unit
ns
(78)
TWP
(78)
TWH
—
ns
(78)
TRP
10
7
—
ns
(78)
TREH
—
ns
(78)
TCLS
Command latch enable to write
enable setup time
10
—
ns
(78)
TCLH
Command latch enable to write
enable hold time
5
15
5
—
—
—
—
—
ns
ns
ns
ns
ns
(78)
TCS
Chip enable to write enable
setup time
(78)
TCH
Chip enable to write enable hold
time
(78)
TALS
Address latch enable to write
enable setup time
10
5
(78)
TALH
Address latch enable to write
enable hold time
(78)
TDS
Data to write enable setup time
Data to write enable hold time
Write enable high to R/B low
Chip enable to data access time
7
5
—
—
ns
ns
ns
(78)
TDH
(78)
TWB
—
—
200
100
TCEA
ns
continued...
(78)
This timing is software programmable. Refer to the NAND Flash Controller chapter in the Intel Agilex Hard Processor System Technical
Reference Manual for more information about software-programmable timing in the NAND flash controller.
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Symbol
Description
Min
—
Max
40
Unit
ns
TREA
TRHZ
Read enable to data access time
Read enable to data high
impedance
—
200
ns
TRR
Ready to read enable low
20
—
ns
Figure 16.
NAND Command Latch Timing Diagram
CLE
tCLS
tCLH
tCH
tCS
CE
tWP
WE
tALS
tALH
ALE
tDS
Command
tDH
IO0-7
R/B
tWB
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Figure 17.
NAND Address Latch Timing Diagram
tCLS
CLE
tCS
CE
tWP
WE
tWH
tALS
tDS
tALH
tDH
ALE
IO0-7
Address
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Figure 18.
NAND Data Output Cycle Timing Diagram
tCLH
CLE
CE
tCH
tWP
tWP
tWP
WE
tWH
tALS
ALE
IOx
tDS tDH
DOUT 0
tDS tDH
DOUT 1
tDS tDH
DOUT n
Figure 19.
NAND Data Input Cycle Timing Diagram
tCEA
CE
tRP
tRP
tRP
RE
tREH
tRR
R/B
tREA
tRHZ
DIN 0
tREA
tRHZ
DIN 1
tREA
tRHZ
DIN n
IOx
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Figure 20.
NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
CE
tRP
tREH
RE
tRR
tREA
tREA
R/B
IOx
tRHZ
DIN n
DIN 0
DIN 1
tCEA
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Figure 21.
NAND Read Status Timing Diagram
CLE
tCLS
tCLH
tCH
tCS
tCEA
CE
tWP
WE
tRHZ
RE
tDS
tDH
IO0-7
70h
Status
tREA
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Figure 22.
NAND Read Status Enhanced Timing Diagram
tCLS
tCS
tCLH
CLE
CE
tCH
tCEA
tWP
tWP
tALS
WE
tALH
tALH
tWH
ALE
RE
tREA
tRHZ
tDS tDH
78h
R1
R2
R3
Status
IO0-7
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HPS Trace Timing Characteristics
Table 65.
Trace Timing Requirements for Intel Agilex Devices
To increase the trace bandwidth, Intel recommends routing the trace interface to the FPGA in the HPS Platform Designer component. The FPGA trace interface
offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.
Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed
possible. Refer to your trace module data sheet for termination recommendations.
Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing
relationship with the HPS programmable I/O delay.
For specification status, see the Data Sheet Status table
Symbol
Description
Trace clock period
Min
6.667
—
Typ
—
Max
—
Unit
ns
Tclk
Tclk_jitter
Tdutycycle
Trace clock output jitter
—
2
%
Trace clock maximum duty
cycle
45
50
55
%
Td
Tclk to D0–D15 output data
delay
0
—
1.8
ns
Figure 23.
Trace Timing Diagram
Clock (DDR)
Trace Data (DDR)
Td
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HPS GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock
frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable
GPIO pulse width is 62.5 µs (at 32 kHz).
If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal
is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If
the external signal is more than two clock cycles, the external signal is not filtered.
HPS JTAG Timing Characteristics
Table 66.
HPS JTAG Timing Requirements for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
TCK clock period
Min
41.66
20
20
5
Typ
—
Max
—
Unit
ns
tJCP
tJCH
TCK clock high time
TCK clock low time
—
—
ns
tJCL
—
—
ns
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
—
—
ns
5
—
—
ns
0
—
—
ns
tJPCO
0
—
8
ns
tJPZX
JTAG port high impedance
to valid output
—
—
10
ns
tJPXZ
JTAG port valid output to
high impedance
—
—
10
ns
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HPS Programmable I/O Timing Characteristics
Table 67.
HPS Programmable I/O Delay (Output Path) for Intel Agilex Device
For specification status, see the Data Sheet Status table
Name
output_val_en
output_val
Description
Min
Typ
Max
Unit
ZERO_CHAIN_DEL
AY
0
1
1
1
1
1
1
1
1
1
0
0
1
2
3
4
5
6
7
8
Intrinsic I/O delay.
Bypasses the delay
chain
TBD
0
TBD
ps
CHAIN_DELAY
Intrinsic I/O delay
+ Minimum + 0 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
ps
ps
ONE_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 1 ×
Chain Delay
TWO_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 2 ×
Chain Delay
THREE_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 3 ×
Chain Delay
FOUR_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 4 ×
Chain Delay
FIVE_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 5 ×
Chain Delay
SIX_CHAIN_DELAY
Intrinsic I/O delay
+ Minimum + 6 ×
Chain Delay
SEVEN_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 7 ×
Chain Delay
EIGHT_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 8 ×
Chain Delay
ps
continued...
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Name
output_val_en
output_val
Description
Min
Typ
Max
Unit
NINE_CHAIN_DELA
Y
1
1
1
1
1
1
1
9
Intrinsic I/O delay
+ Minimum + 9 ×
Chain Delay
TBD
TBD
TBD
ps
TEN_CHAIN_DELAY
10
11
12
13
14
15
Intrinsic I/O delay
+ Minimum + 10 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
ELEVEN_CHAIN_DE
LAY
Intrinsic I/O delay
+ Minimum + 11 ×
Chain Delay
TWELVE_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 12 ×
Chain Delay
THIRTEEN_CHAIN_
DELAY
Intrinsic I/O delay
+ Minimum + 13 ×
Chain Delay
FOURTEEN_CHAIN
_DELAY
Intrinsic I/O delay
+ Minimum + 14 ×
Chain Delay
FIFTEEN_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 15 ×
Chain Delay
—
—
—
1
2
3
3
[16:30]
—
INVALID
INVALID
INVALID
—
—
—
—
—
—
—
—
—
ps
[0:15]
16
—
—
—
SIXTEEN_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 16 ×
Chain Delay
TBD
TBD
TBD
SEVENTEEN_CHAIN
_DELAY
3
3
17
18
Intrinsic I/O delay
+ Minimum + 17 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
ps
EIGHTEEN_CHAIN_
DELAY
Intrinsic I/O delay
+ Minimum + 18 ×
Chain Delay
ps
continued...
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Name
output_val_en
output_val
Description
Min
Typ
Max
Unit
NINETEEN_CHAIN_
DELAY
3
3
3
3
3
3
3
3
3
3
3
3
19
20
21
22
23
24
25
26
27
28
29
30
Intrinsic I/O delay
+ Minimum + 19 ×
Chain Delay
TBD
TBD
TBD
ps
TWENTY_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 20 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
TWENTYONE_CHAI
N_DELAY
Intrinsic I/O delay
+ Minimum + 21 ×
Chain Delay
TWENTYTWO_CHAI
N_DELAY
Intrinsic I/O delay
+ Minimum + 22 ×
Chain Delay
TWENTYTHREE_CH
AIN_DELAY
Intrinsic I/O delay
+ Minimum + 23 ×
Chain Delay
TWENTYFOUR_CHA
IN_DELAY
Intrinsic I/O delay
+ Minimum + 24 ×
Chain Delay
TWENTYFIVE_CHAI
N_DELAY
Intrinsic I/O delay
+ Minimum + 25 ×
Chain Delay
TWENTYSIX_CHAIN
_DELAY
Intrinsic I/O delay
+ Minimum + 26 ×
Chain Delay
TWENTYSEVEN_CH
AIN_DELAY
Intrinsic I/O delay
+ Minimum + 27 ×
Chain Delay
TWENTYEIGHT_CH
AIN_DELAY
Intrinsic I/O delay
+ Minimum + 28 ×
Chain Delay
TWENTYNINE_CHA
IN_DELAY
Intrinsic I/O delay
+ Minimum + 29 ×
Chain Delay
THIRTY_CHAIN_DE
LAY
Intrinsic I/O delay
+ Minimum + 30 ×
Chain Delay
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Table 68.
HPS Programmable I/O Delay (Input Path) for Intel Agilex Device
For specification status, see the Data Sheet Status table
Name
input_val_en
input_val
Description
Min
Typ
Max
Unit
ZERO_CHAIN_DEL
AY
0
1
1
1
1
1
1
1
1
1
1
0
0
1
2
3
4
5
6
7
8
9
Intrinsic I/O delay.
Bypasses the delay
chain
TBD
0
TBD
ps
CHAIN_DELAY
Intrinsic I/O delay
+ Minimum + 0 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
ps
ps
ps
ONE_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 1 ×
Chain Delay
TWO_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 2 ×
Chain Delay
THREE_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 3 ×
Chain Delay
FOUR_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 4 ×
Chain Delay
FIVE_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 5 ×
Chain Delay
SIX_CHAIN_DELAY
Intrinsic I/O delay
+ Minimum + 6 ×
Chain Delay
SEVEN_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 7 ×
Chain Delay
EIGHT_CHAIN_DEL
AY
Intrinsic I/O delay
+ Minimum + 8 ×
Chain Delay
NINE_CHAIN_DELA
Y
Intrinsic I/O delay
+ Minimum + 9 ×
Chain Delay
ps
continued...
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Name
input_val_en
input_val
Description
Min
Typ
Max
Unit
TEN_CHAIN_DELAY
1
1
1
1
1
1
10
11
12
13
14
15
Intrinsic I/O delay
+ Minimum + 10 ×
Chain Delay
TBD
TBD
TBD
ps
ELEVEN_CHAIN_DE
LAY
Intrinsic I/O delay
+ Minimum + 11 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
TWELVE_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 12 ×
Chain Delay
THIRTEEN_CHAIN_
DELAY
Intrinsic I/O delay
+ Minimum + 13 ×
Chain Delay
FOURTEEN_CHAIN
_DELAY
Intrinsic I/O delay
+ Minimum + 14 ×
Chain Delay
FIFTEEN_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 15 ×
Chain Delay
—
—
—
1
2
3
3
[16:30]
—
INVALID
INVALID
INVALID
—
—
—
—
—
—
—
—
—
ps
[0:15]
16
—
—
—
SIXTEEN_CHAIN_D
ELAY
Intrinsic I/O delay
+ Minimum + 16 ×
Chain Delay
TBD
TBD
TBD
SEVENTEEN_CHAIN
_DELAY
3
3
3
17
18
19
Intrinsic I/O delay
+ Minimum + 17 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
EIGHTEEN_CHAIN_
DELAY
Intrinsic I/O delay
+ Minimum + 18 ×
Chain Delay
NINETEEN_CHAIN_
DELAY
Intrinsic I/O delay
+ Minimum + 19 ×
Chain Delay
ps
continued...
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Name
input_val_en
input_val
Description
Min
Typ
Max
Unit
TWENTY_CHAIN_D
ELAY
3
3
3
3
3
3
3
3
3
3
3
20
21
22
23
24
25
26
27
28
29
30
Intrinsic I/O delay
+ Minimum + 20 ×
Chain Delay
TBD
TBD
TBD
ps
TWENTYONE_CHAI
N_DELAY
Intrinsic I/O delay
+ Minimum + 21 ×
Chain Delay
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
TWENTYTWO_CHAI
N_DELAY
Intrinsic I/O delay
+ Minimum + 22 ×
Chain Delay
TWENTYTHREE_CH
AIN_DELAY
Intrinsic I/O delay
+ Minimum + 23 ×
Chain Delay
TWENTYFOUR_CHA
IN_DELAY
Intrinsic I/O delay
+ Minimum + 24 ×
Chain Delay
TWENTYFIVE_CHAI
N_DELAY
Intrinsic I/O delay
+ Minimum + 25 ×
Chain Delay
TWENTYSIX_CHAIN
_DELAY
Intrinsic I/O delay
+ Minimum + 26 ×
Chain Delay
TWENTYSEVEN_CH
AIN_DELAY
Intrinsic I/O delay
+ Minimum + 27 ×
Chain Delay
TWENTYEIGHT_CH
AIN_DELAY
Intrinsic I/O delay
+ Minimum + 28 ×
Chain Delay
TWENTYNINE_CHA
IN_DELAY
Intrinsic I/O delay
+ Minimum + 29 ×
Chain Delay
THIRTY_CHAIN_DE
LAY
Intrinsic I/O delay
+ Minimum + 30 ×
Chain Delay
You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0
through 47).
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Configuration Specifications
General Configuration Timing Specifications
Table 69.
General Configuration Timing Specifications for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Requirement
Unit
Min
—
Max
20
(79)
tCF12ST1
tCF02ST0
tST0
ms
ms
ms
nCONFIG high to nSTATUS high
nCONFIG low to nSTATUS low
—
400
10
0.5
nSTATUS low pulse during
configuration error
(80)
tCD2UM
—
5
ms
CONF_DONE high to user mode
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR
circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device
is ready to begin configuration.
Table 70.
POR Delay Specification for Intel Agilex Devices
For specification status, see the Data Sheet Status table
POR Delay
Minimum
Maximum
Unit
AS (Normal mode), AVST ×8, AVST ×16,
AVST ×32, SD/MMC
11
17
ms
AS (Fast mode)
1.1
6.9
ms
(79)
(80)
The maximum time does not exceed 2× of the typical value.
This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.
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External Configuration Clock Source Requirements
Table 71.
External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements
For specification status, see the Data Sheet Status table
Description
External Clock Source
Min
Typ
Max
Unit
MHz
%
Clock input frequency(81)
Clock input jitter tolerance
Clock input duty cycle
Powered by VCCIO_SDM
25/100/125
—
—
2
45
50
55
%
JTAG Configuration Timing
Table 72.
JTAG Timing Parameters and Values for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
Requirement
Unit
Minimum
Maximum
tJCP
30
14
14
2
—
—
—
—
—
—
ns
ns
ns
ns
ns
TCK clock period
tJCH
TCK clock high time
tJCL
TCK clock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
3
5
ns
continued...
(81)
The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency
on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel Quartus Prime software. Other frequencies in the
range are not supported.
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Symbol
Description
Requirement
Unit
Minimum
Maximum
tJPCO
tJPZX
JTAG port clock to output
—
—
7
ns
ns
JTAG port high impedance to
valid output
14
tJPXZ
JTAG port valid output to high
impedance
—
14
ns
Figure 24.
JTAG Timing Diagram
TMS
TDI
tJCP
tJPSU
tJPH
tJCH
tJCL
TCK
tJPZX
tJPCO
tJPXZ
TDO
AS Configuration Timing
Table 73.
AS Timing Parameters for Intel Agilex Devices
Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. The maximum tolerance for skew between
nCSO and AS_CLK is recommended to be less than 200 ps. The tolerance for skew between AS_CLK to AS_DATA must be within 0 ps – 400 ps.
For specification status, see the Data Sheet Status table
Symbol
Description
AS_CLK clock period
AS_CLK duty cycle
Minimum
—
Typical
7.52
50
Maximum
—
Unit
ns
(82)
Tclk
Tdutycycle
Tdcsfrs
45
55
%
4.21(83)
—
7.50(83)
ns
AS_nCSO[3:0] asserted
to first AS_CLK edge
continued...
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Symbol
Description
Minimum
Typical
Maximum
Unit
Tdcslst
5.18(83)
—
8(83)
ns
Last AS_CLK edge to
AS_nCSO[3:0]
deasserted
(84)
Tdo
0
0
—
—
1.5
15
ns
ns
AS_DATA0 output delay
(85)
Text_delay
Total external propagation
delay on AS signals
Tdcsb2b
Minimum delay of slave
select deassertion between
two back-to-back transfers
1
—
—
AS_CLK
(82)
AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash
devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash
setup/hold time specifications and Intel Agilex AS timing specifications in the Intel Agilex Device Datasheet. For AS using multiple
serial flash devices, refer to the Intel Agilex Configuration User Guide for the recommended AS_CLK frequency and maximum board
loading.
(83)
(84)
AS operating at maximum clock frequency = 133 MHz. The delay is larger when operating at AS clock frequency lower than 133 MHz.
Load capacitance for DCLK = 12 pF and AS_DATA = 27 pF. Intel recommends obtaining the Tdo for a given link (including receiver,
transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash
setup time,
•
•
Tsu = AS_CLK/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
Tho = AS_CLK/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
(85)
Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
•
Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
• Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the
minimum and maximum specification values.
•
•
Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
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Figure 25.
AS Configuration Serial Output Timing Diagram
Tdo (min)
Tdcslst
Tdcsfrs
Tdo (max)
nCSO
AS_CLK
AS_DATA
OUT0
OUT1
OUTn
Figure 26.
AS Configuration Serial Input Timing Diagram
nCSO
AS_CLK
AS_DATA
Text_delay
IN0
IN1
INn
Avalon® Streaming (Avalon®-ST) Configuration Timing
Table 74.
Avalon®-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Agilex Devices
For specification status, see the Data Sheet Status table
Symbol
Description
AVST_CLK high time
Minimum
Unit
ns
tACLKH
tACLKL
tACLKP
3.6
3.6
8
ns
AVST_CLK low time
AVST_CLK period
ns
continued...
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Symbol
Description
Minimum
Unit
(86)
tADSU
2.1
ns
AVST_DATA setup time before rising
edge of AVST_CLK
(86)
tADH
0
2.1
0
ns
ns
ns
AVST_DATA hold time after rising edge of
AVST_CLK
tAVSU
AVST_VALID setup time before rising
edge of AVST_CLK
tAVDH
AVST_VALID hold time after rising edge
of AVST_CLK
Figure 27.
Avalon®-ST Configuration Timing Diagram
tACLKP
tACLKH
tACLKL
AVSTx8_CLK
or AVST_CLK
AVST_READY
or AVSTx8_READY
tAVSU
tAVDH
AVSTx8_VALID
or AVST_VALID
must deassert
within 6 cycles
tADSU
tADH
AVSTx8_DATA[7:0]
AVST_DATA[15:0]
AVST_data[31:0]]
data0 data1 data2 data3
(86)
Data sampled by the FPGA (sink) at the next rising clock edge.
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Configuration Bit Stream Sizes
Table 75.
Configuration Bit Stream Sizes for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Variant
Compressed Configuration Bit Stream Size (Mbits)
AGF004, AGF006
AGF008
178.4
238
AGF012, AGF014
446.3
833.4
AGF022, AGF027, AGI022, AGI027
Maximum Configuration Time Estimation
Table 76.
Maximum Configuration Time Estimation for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Variant
Maximum Configuration Time (ms)
AS ×4
554.3
773.1
1,400
2,500
AVST ×8
315.6
AVST ×16
221.9
AVST ×32
122.4
SD/MMC
762.1
AGF004, AGF006
AGF008
414.9
288.1
155.6
1,000
AGF012, AGF014
762.3
519.7
271.3
1,900
AGF022, AGF027, AGI022,
AGI027
1,400
949.6
486.3
3,500
I/O Timing
I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing
analysis. You may generate the I/O timing report manually using the Timing Analyzer.
The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the
design after you complete place-and-route.
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Related Information
AN 775: I/O Timing Information Generation Guidelines
Provides the techniques to generate I/O timing information using the Intel Quartus Prime software.
Programmable IOE Delay
Table 77.
Programmable IOE Delay for Intel Agilex Devices
For specification status, see the Data Sheet Status table
Parameter
Maximum Offset
Minimum offset
Fast Model
Extended
1.748
Slow model
Unit
ns
–E2
–E3
Input Delay Chain
(INPUT_DELAY_CHAIN
)
63
15
0
0
2.659
3.030
Output Delay Chain
(OUTPUT_DELAY_CHA
IN)
0.410
0.626
0.712
ns
Glossary
Table 78.
Glossary
Term
Definition
Differential I/O Standards
Receiver Input Waveforms
continued...
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Term
Definition
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p - n = 0 V
V
ID
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p - n = 0 V
V
OD
fHSCLK
fHSDR
I/O PLL input clock frequency.
LVDS SERDES block—maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
LVDS SERDES block—maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J (SERDES factor)
LVDS SERDES block—deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
JTAG Timing Specifications
continued...
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Term
Definition
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
tJPXZ
tJPZX
tJPCO
TDO
RL
Receiver differential input discrete resistor (external to the Intel Agilex device).
Sampling window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold
times determine the ideal strobe position in the sampling window, as shown:
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
Single-ended voltage referenced I/O standard
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the
voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which
the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to
provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
continued...
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Term
Definition
V CCIO
V OH
V IH(AC)
V IH(DC)
V IL(DC)
V REF
V IL(AC)
V OL
V SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across
channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure
under SW in this table).
tDUTY
LVDS SERDES block—duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
tFALL
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the GPIO driven by a PLL.
tOUTPJ_IO
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20–80%).
tRISE
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
VCM(DC)
VICM
VICM(DC)
VID
DC Common mode input voltage.
Input Common mode voltage—the common mode of the differential signal at the receiver.
VCM(DC) DC Common mode input voltage.
Input differential voltage swing—the difference in voltage between the positive and complementary conductors of a
differential transmission at the receiver.
VDIF(AC)
VDIF(DC)
AC differential input voltage—minimum AC input differential voltage required for switching.
DC differential input voltage—minimum DC input differential voltage required for switching.
continued...
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Term
Definition
VIH
Voltage input high—the minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC)
VIH(DC)
VIL
High-level AC input voltage.
High-level DC input voltage.
Voltage input low—the maximum positive voltage applied to the input which is accepted by the device as a logic low.
Low-level AC input voltage.
VIL(AC)
VIL(DC)
VOCM
VOD
Low-level DC input voltage.
Output Common mode voltage—the common mode of the differential signal at the transmitter.
Output differential voltage swing—the difference in voltage between the positive and complementary conductors of a
differential transmission line at the transmitter.
VSWING
VOX
VIX(AC)
W
Differential input voltage.
Output differential cross point voltage.
VIX Input differential cross point voltage.
LVDS SERDES block—Clock Boost Factor.
Document Revision History for the Intel Agilex Device Data Sheet
Document
Version
Changes
2020.05.14
2020.03.18
Updated VCCFUSEWR_SDM specifications in the Recommended Operating Conditions for Intel Agilex Devices table.
•
•
•
Added the Absolute Maximum Rating for Intel Agilex Devices table.
Added Maximum Allowed Overshoot and Undershoot Voltage section.
Updated the Recommended Operating Conditions for Intel Agilex Devices table.
— Updated the typical values for VCC and VCCP
.
— Added VCCR_CORE specifications.
— Updated description for VCCPT and VCCIO_PIO_SDM
.
— Updated VCCFUSEWR_SDM and VI specifications.
— Updated VCCA_PLL specifications and description.
— Added a note for TJ minimum specifications for Industrial.
— Updated tRAMP minimum specification.
continued...
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Document
Version
Changes
•
Updated the E-Tile Transceiver Power Supply Operating Conditions table.
— Updated VCCCLK_GXE for maximum DC level.
— Updated VCCCLK_GXE for recommended AC transient level.
— Updated wording for all recommended DC values from % of DC level to % of Vnominal
.
•
•
Updated wording for all recommended DC values from % of DC level to % of Vnominal in the P-Tile Transceiver Power Supply Operating Conditions.
Updated the E-Tile Transmitter and Receiver Data Rate Performance Specifications table with the transceiver speed grades for the NRZ and PAM4
supported data rates.
•
•
Updated the transmitter differential output voltage peak-to-peak typical value in the E-Tile Transmitter Specifications table.
Updated the E-tile Receiver Specifications table:
— Added the absolute Vmax for a receiver pin specification
— Added the maxium peak-to-peak differential input voltage VID (diff p-p) before/after device configuration specification
— Added VICM (AC coupled) specification
— Removed the electrical idle detection voltage specification
•
Updated P-Tile Transceiver Performance:
— Added supported data rate for Gen1, Gen 2, Gen 3, and Gen 4 in the P-Tile Transmitter and Receiver Data Rate Performance table.
— Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLA Performance table.
— Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLB Performance table.
Updated P-Tile Transmitter Specifications:
•
•
— Added PCIe condition for Supported I/O Standards.
— Removed VOCM (AC Coupled).
Updated P-Tile Receiver Specifications:
— Added PCIe condition for Supported I/O Standards.
— Added PCIe 8.0 GT/s and 16.0 GT/s specifications for the peak-to-peak differential input voltage VID (diff p-p) and added corresponding notes.
— Updated RESREF specification. Added a note to the RESREF specification.
•
•
•
•
•
Updated VCCL_HPS and VCCPLLDIG_HPS specifications for SmartVID in the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator.
Added a note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices table.
Added a note in the Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel Agilex Devices table.
Updated the Differential I/O Standards Specifications for Intel Agilex Devices table.
— Updated I/O standard name from "1.5 V True Differential Signaling" to "True Differential Signaling (Transmitter & Receiver)".
— Added specifications for True Differential Signaling (Receiver only).
— Updated note to True Differential Signaling.
continued...
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Document
Version
Changes
•
Updated the I/O PLL Specifications for Intel Agilex Devices table.
— Added notes for tFCOMP, tOUTPJ_DC, and tOUTCCJ_DC
.
— Removed tINCCJ specifications.
— Added tREFPJ and tREFPN specifications.
— Updated tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC specifications.
•
•
Added a note for fixed-point 27 × 27 multiplication mode in the DSP Block Performance Specifications for Intel Agilex Devices table.
Updated the Memory Block Performance Specifications for Intel Agilex Devices table.
— Updated the specifications for MLAB memory.
— Updated the specifications for M20K block and added low power (LP) specifications.
Updated the specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD) table.
Added the Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD) table.
Updated the LVDS SERDES Specifications for Intel Agilex Devices table.
•
•
•
— Updated the tx Jitter - True Differential I/O Standards specifications for –4 speed grade.
— Removed global, regional, or local in clock routing resource.
•
Updated the DPA Lock Time Specifications for Intel Agilex Devices table.
— Updated the description of the table.
— Updated the maximum data transition from 960 to 768.
•
•
•
Updated the jitter requirements in the Memory Output Clock Jitter Specifications section.
Updated the specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device
tables.
•
Updated the following diagrams:
— USB ULPI Timing Diagram
— RGMII TX Timing Diagram
— RMII TX Timing Diagram
— RMII RX Timing Diagram
•
•
•
•
Updated tST0 and tCD2UM specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
Added notes to Tclk and Tdo specifications in the AS Timing Parameters for Intel Agilex Devices table.
Updated tADSU and tAVSU specifications in the Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Agilex Devices table.
Added the following tables:
— Configuration Bit Stream Sizes for Intel Agilex Devices
— Maximum Configuration Time Estimation for Intel Agilex Devices
— Programmable IOE Delay for Intel Agilex Devices
2019.12.18
2019.04.02
Updated the I/O PLL Specifications for Intel Agilex Devices table.
•
•
Removed scanclk from fDYCONFIGCLK parameter.
Corrected the maximum specification for fDYCONFIGCLK from 200 MHz to 100 MHz.
Initial release.
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