AT80570KJ0806M/SLB9C [INTEL]
RISC Microprocessor, 32-Bit, 3000MHz, CMOS, PBGA775;型号: | AT80570KJ0806M/SLB9C |
厂家: | INTEL |
描述: | RISC Microprocessor, 32-Bit, 3000MHz, CMOS, PBGA775 |
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中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual-Core Intel® Xeon® Processor
3100 Series
Datasheet
February 2009
Document Number: 319004-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
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MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
®
®
The Dual-Core Intel Xeon Processor 3100 Series may contain design defects or errors known as errata which may cause the
product to deviate from published specifications.
Φ
®
Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled
for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
depending on your hardware and software configurations. See http://developer.intel.com/technology/intel64/ for more information
including details on which processors support Intel 64 or consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
®
Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and
for some uses, certain platform software enabled for it. Functionality, performance or other benefit will vary depending on
hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all
operating systems. Please check with your application vendor.
Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep®
Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more
information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Xeon, Pentium, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other
countries.
* Other names and brands may be claimed as the property of others.
Copyright © 2009, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction .......................................................................................................9
1.1
Terminology .......................................................................................................9
1.1.1 Processor Terminology Definitions ............................................................ 10
References ....................................................................................................... 11
1.2
2
Electrical Specifications............................................................................... 13
2.1
2.2
Power and Ground Lands.................................................................................... 13
Decoupling Guidelines........................................................................................ 13
2.2.1 Vcc Decoupling ...................................................................................... 13
2.2.2 Vtt Decoupling....................................................................................... 13
2.2.3 FSB Decoupling...................................................................................... 14
Voltage Identification......................................................................................... 14
Reserved, Unused, and TESTHI Signals ................................................................ 16
Flexible Motherboard Guidelines (FMB)................................................................. 17
Power Segment Identifier (PSID)......................................................................... 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification........................................................ 18
2.6.3 VCC Overshoot ...................................................................................... 20
2.6.4 Die Voltage Validation............................................................................. 21
Signaling Specifications...................................................................................... 21
2.7.1 FSB Signal Groups.................................................................................. 22
2.7.2 CMOS and Open Drain Signals ................................................................. 23
2.7.3 Processor DC Specifications ..................................................................... 23
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications..... 24
2.7.3.2 GTL+ Front Side Bus Specifications ............................................. 25
Clock Specifications........................................................................................... 26
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................ 26
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 27
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 27
2.8.4 BCLK[1:0] Specifications......................................................................... 28
2.3
2.4
2.5
2.6
2.7
2.8
3
Package Mechanical Specifications.................................................................. 31
3.1
Package Mechanical Specifications....................................................................... 31
3.1.1 Package Mechanical Drawing.................................................................... 31
3.1.2 Processor Component Keep-Out Zones...................................................... 35
3.1.3 Package Loading Specifications ................................................................ 36
3.1.4 Package Handling Guidelines.................................................................... 36
3.1.5 Package Insertion Specifications............................................................... 36
3.1.6 Processor Mass Specification.................................................................... 37
3.1.7 Processor Materials................................................................................. 37
3.1.8 Processor Markings................................................................................. 37
3.1.9 Processor Land Coordinates..................................................................... 37
4
5
Land Listing and Signal Descriptions............................................................... 39
4.1
4.2
Processor Land Assignments............................................................................... 39
Alphabetical Signals Reference............................................................................ 70
Thermal Specifications and Design Considerations....................................... 77
5.1
Processor Thermal Specifications......................................................................... 77
5.1.1 Thermal Specifications ............................................................................ 77
5.1.2 Thermal Metrology ................................................................................. 81
Processor Thermal Features................................................................................ 81
5.2.1 Thermal Monitor..................................................................................... 81
5.2.2 Thermal Monitor 2.................................................................................. 82
5.2
Datasheet
3
5.2.3 On-Demand Mode...................................................................................83
5.2.4 PROCHOT# Signal ..................................................................................84
5.2.5 THERMTRIP# Signal................................................................................84
Platform Environment Control Interface (PECI) ......................................................84
5.3.1 Introduction...........................................................................................84
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems ..................85
5.3.2 PECI Specifications .................................................................................85
5.3.2.1 PECI Device Address..................................................................85
5.3.2.2 PECI Command Support.............................................................85
5.3.2.3 PECI Fault Handling Requirements...............................................86
5.3.2.4 PECI GetTemp0() Error Code Support ..........................................86
5.3
6
Features..............................................................................................................87
6.1
6.2
Power-On Configuration Options ..........................................................................87
Clock Control and Low Power States.....................................................................87
6.2.1 Normal State .........................................................................................88
6.2.2 HALT and Extended HALT Powerdown States ..............................................88
6.2.2.1 HALT Powerdown State ..............................................................88
6.2.2.2 Extended HALT Powerdown State ................................................89
6.2.3 Stop Grant and Extended Stop Grant States...............................................89
6.2.3.1 Stop-Grant State.......................................................................89
6.2.3.2 Extended Stop Grant State.........................................................90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop
State, and Stop Grant Snoop State90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State.......90
6.2.5 Enhanced Intel SpeedStep® Technology ....................................................90
6.2.6 Processor Power Status Indicator (PSI) Signal ............................................91
7
Boxed Processor Specifications........................................................................93
7.1
7.2
Introduction......................................................................................................93
Mechanical Specifications....................................................................................94
7.2.1 Boxed Processor Cooling Solution Dimensions.............................................94
7.2.2 Boxed Processor Fan Heatsink Weight .......................................................95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....96
Electrical Requirements ......................................................................................96
7.3.1 Fan Heatsink Power Supply ......................................................................96
Thermal Specifications........................................................................................97
7.4.1 Boxed Processor Cooling Requirements......................................................97
7.4.2 Variable Speed Fan.................................................................................99
7.3
7.4
8
Debug Tools Specifications..............................................................................103
8.1
Logic Analyzer Interface (LAI) ...........................................................................103
8.1.1 Mechanical Considerations .....................................................................103
8.1.2 Electrical Considerations........................................................................103
Figures
2-1 Processor VCC Static and Transient Tolerance ...............................................................20
2-2 VCC Overshoot Example Waveform..............................................................................21
2-3 Differential Clock Waveform.......................................................................................29
2-4 Measurement Points for Differential Clock Waveforms....................................................29
3-1 Processor Package Assembly Sketch ...........................................................................31
3-2 Processor Package Drawing Sheet 1 of 3......................................................................33
3-3 Processor Package Drawing Sheet 2 of 3......................................................................34
3-4 Processor Package Drawing Sheet 3 of 3......................................................................35
3-5 Processor Top-Side Markings Example.........................................................................37
3-6 Processor Land Coordinates and Quadrants, Top View ...................................................38
4-1 land-out Diagram (Top View – Left Side) .....................................................................40
4-2 land-out Diagram (Top View – Right Side) ...................................................................41
4
Datasheet
5-1 Processor Thermal Profile (65 W) ............................................................................... 80
5-2 Processor Thermal Profile (45 W) ............................................................................... 80
5-3 Case Temperature (TC) Measurement Location ............................................................ 81
5-4 Thermal Monitor 2 Frequency and Voltage Ordering...................................................... 83
5-5 Conceptual Fan Control Diagram on PECI-Based Platforms............................................. 85
6-1 Processor Low Power State Machine ........................................................................... 88
7-1 Mechanical Representation of the Boxed Processor ....................................................... 93
7-2 Side View Space Requirements for the Boxed Processor ................................................ 94
7-3 Top View Space Requirements for the Boxed Processor ................................................. 95
7-4 Overall View Space Requirements for the Boxed Processor............................................. 95
7-5 Boxed Processor Fan Heatsink Power Cable Connector Description.................................. 96
7-6 Baseboard Power Header Placement Relative to Processor Socket................................... 97
7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................... 98
7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) ................... 99
7-9 Boxed Processor Fan Heatsink Set Points................................................................... 100
Datasheet
5
Tables
1-1 References ..............................................................................................................11
2-1 Voltage Identification Definition .................................................................................15
2-2 Absolute Maximum and Minimum Ratings ....................................................................17
2-3 Voltage and Current Specifications..............................................................................18
2-4 Processor VCC Static and Transient Tolerance ...............................................................19
2-5 VCC Overshoot Specifications......................................................................................20
2-6 FSB Signal Groups....................................................................................................22
2-7 Signal Characteristics................................................................................................23
2-8 Signal Reference Voltages .........................................................................................23
2-9 GTL+ Signal Group DC Specifications ..........................................................................23
2-10Open Drain and TAP Output Signal Group DC Specifications ...........................................24
2-11CMOS Signal Group DC Specifications .........................................................................24
2-12PECI DC Electrical Limits ...........................................................................................25
2-13GTL+ Bus Voltage Definitions.....................................................................................25
2-14Core Frequency to FSB Multiplier Configuration.............................................................26
2-15BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................27
2-16Front Side Bus Differential BCLK Specifications.............................................................28
2-17FSB Differential Clock Specifications (1333 MHz FSB) ....................................................28
3-1 Processor Loading Specifications.................................................................................36
3-2 Package Handling Guidelines......................................................................................36
3-3 Processor Materials...................................................................................................37
4-1 Alphabetical Land Assignments...................................................................................42
4-2 Numerical Land Assignment.......................................................................................58
4-3 Signal Description.....................................................................................................70
5-1 Processor Thermal Specifications................................................................................78
5-2 Processor Thermal Profile (65 W)................................................................................79
5-3 Processor Thermal Profile (45W).................................................................................79
5-4 GetTemp0() Error Codes ...........................................................................................86
6-1 Power-On Configuration Option Signals .......................................................................87
7-1 Fan Heatsink Power and Signal Specifications...............................................................97
7-2 Fan Heatsink Power and Signal Specifications.............................................................100
6
Datasheet
Revision History
Document
Number
Version
Number
Revision
Date
Revision
Description
January 2008
319004
1.0
-001
• Initial release
®
®
• Added Dual-Core Intel Xeon Processor L3110
• Added PSI# signal
February
2009
-002
• Updated VID information
Datasheet
7
8
Datasheet
Introduction
1 Introduction
The Dual-Core Intel® Xeon® Processor 3100 Series, like the previous Dual-Core Intel®
Xeon® Processor 3000 Series, are based on the Intel® CoreTM microarchitecture. The
Intel Core microarchitecture combines the performance of previous generation
products with the power efficiencies of a low-power microarchitecture to enable
smaller, quieter systems. The Dual-Core Intel® Xeon® Processor 3100 Series is a 64-
bit processor that maintain compatibility with IA-32 software.
In this document, the Dual-Core Intel® Xeon® Processor 3100 Series may be referred
to simply as “the processor.”
The processors utilize Flip-Chip Land Grid Array (FC-LGA8) package technology, and
plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
The processor is a dual-core processor, based on 45 nm process technology. The
processor features the Intel® Advanced Smart Cache, a shared multi-core optimized
cache that significantly reduces latency to frequently used data. The processor features
a 1333 MHz front side bus (FSB) and 6 MB of L2 cache. The processor supports all the
existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3),
Supplemental Streaming SIMD Extension 3 (SSSE3), and the Streaming SIMD
Extensions 4.1 (SSE4.1). The processor supports several Advanced Technologies:
Execute Disable Bit, Intel® 64 architecture, Enhanced Intel SpeedStep® Technology,
Intel® Virtualization Technology (Intel® VT), and Intel® Trusted Execution Technology
(Intel® TXT).
The processor's front side bus (FSB) utilizes a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
Datasheet
9
Introduction
1.1.1
Processor Terminology Definitions
Commonly used terms are explained here for clarification:
• Dual-Core Intel® Xeon® Processor 3100 Series — Dual core processor in the
FC-LGA8 package with a 6 MB L2 cache.
• Processor — For this document, the term processor is the generic form of the
Dual-Core Intel® Xeon® Processor 3100 Series.
• Intel® CoreTM microarchitecture — A new foundation for Intel® architecture-
based desktop, mobile and mainstream server multi-core processors. For additional
information refer to: http://www.intel.com/technology/architecture/coremicro/
• Keep-out zone — The area on or near the processor that system design can not
utilize.
• Processor core — Processor die with integrated L2 cache.
• LGA775 socket — The Dual-Core Intel® Xeon® Processor 3100 Series mate with
the system board through a surface mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.
• Execute Disable Bit — Execute Disable Bit allows memory to be marked as
executable or non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the Intel® Architecture Software Developer's Manual
for more detailed information.
• Intel® 64 Architecture— An enhancement to Intel's IA-32 architecture, allowing
the processor to execute operating systems and applications written to take
advantage of the Intel 64 architecture. Further details on Intel 64 architecture and
programming model can be found in the Intel Extended Memory 64 Technology
Software Developer Guide at http://developer.intel.com/technology/
64bitextensions/.
10
Datasheet
Introduction
• Enhanced Intel SpeedStep® Technology — Enhanced Intel SpeedStep
Technology allows trade-offs to be made between performance and power
consumptions, based on processor utilization. This may lower average power
consumption (in conjunction with OS support).
• Intel® Virtualization Technology (Intel® VT) — A set of hardware
enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel VT will provide a foundation for widely-deployed virtualization
solutions and enables more robust hardware assisted virtualization solutions. More
information can be found at: http://www.intel.com/technology/virtualization/
• Intel® Trusted Execution Technology (Intel® TXT) — A key element in Intel's
safer computing initiative which defines a set of hardware enhancements that
interoperate with an Intel TXT enabled OS to help protect against software-based
attacks. Intel TXT creates a hardware foundation that builds on Intel's
Virtualization Technology (Intel VT) to help protect the confidentiality and integrity
of data stored/created on the client PC.
• Platform Environment Control Interface (PECI) — A proprietary one-wire bus
interface that provides a communication channel between the processor and
chipset components to external monitoring devices.
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document:
Table 1-1.
References
Document
Location
http://www.intel.com/
products/processor/
xeon3000/
Wolfdale Processors Thermal and Mechanical Design
Guidelines Addendum
documentation.htm#therma
l_models
http://download.intel.com/
design/intarch/specupdt/
319006.pdf
Dual-Core Intel® Xeon® Processor 3100 Series
Specification Update
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket
http://www.intel.com/design/
processor/applnots/313214.htm
LGA775 Socket Mechanical Design Guide
http://intel.com/design/
Pentium4/guides/
302666.htm
IA-32 Intel Architecture Software Developer's Manual
Volume 1: Basic Architecture
http://www.intel.com/
design/products/processor/
manuals/
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide, Part 1
Volume 3B: System Programming Guide, Part 2
§
Datasheet
11
Introduction
12
Datasheet
Electrical Specifications
2 Electrical Specifications
2.1
Power and Ground Lands
The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to VCC, while all VSS lands must be
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
VTT specifications outlined in Table 2-3.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 2-3. Failure to do so can result in timing violations or reduced lifetime of
the component. For further information and guidelines, refer to the appropriate
platform design guidelines.
2.2.1
2.2.2
VCC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket and appropriate platform design guidelines for further
information.
VTT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To ensure compliance with the specifications, various
factors associated with the power delivery solution must be considered including
regulator type, power plane and trace sizing, and component placement. A
conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors. For further information regarding
power delivery, decoupling and layout guidelines, refer to the appropriate platform
design guidelines.
Datasheet
13
Electrical Specifications
2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation. Decoupling
guidelines are described in the appropriate platform design guidelines.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see Chapter 2.6.3 for VCC overshoot
specifications). Refer to Table 2-11 for the DC specifications for these signals. Voltages
for each processor frequency is provided in Table 2-3.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 2-3. Refer to the Processor
Specification Update for further details on specific valid core frequency and VID values
of the processor. Note that this differs from the VID employed by the processor during
a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep®
technology, or Extended HALT State).
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages. Table 2-1 specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not
outputs of the processor but are strapped to VSS on the processor package. VID0 and
VID7 must be connected to the VR controller for compatibility with future processors.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 2-3 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 2-4 and Figure 2-1 as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 2-3
and Table 2-4. Refer to the Voltage Regulator Design Guide for further details.
14
Datasheet
Electrical Specifications
Table 2-1.
Voltage Identification Definition
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
Voltage
Voltage
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFF
1.6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.0375
1.025
1.0125
1
1.5875
1.575
1.5625
1.55
0.9875
0.975
0.9625
0.95
1.5375
1.525
1.5125
1.5
0.9375
0.925
0.9125
0.9
1.4875
1.475
1.4625
1.45
0.8875
0.875
0.8625
0.85
1.4375
1.425
1.4125
1.4
0.8375
0.825
0.8125
0.8
1.3875
1.375
1.3625
1.35
0.7875
0.775
0.7625
0.75
1.3375
1.325
1.3125
1.3
0.7375
0.725
0.7125
0.7
1.2875
1.275
1.2625
1.25
0.6875
0.675
0.6625
0.65
1.2375
1.225
1.2125
1.2
0.6375
0.625
0.6125
0.6
1.1875
1.175
1.1625
1.15
0.5875
0.575
0.5625
0.55
1.1375
1.125
1.1125
1.1
0.5375
0.525
0.5125
0.5
1.0875
1.075
1.0625
1.05
OFF
Datasheet
15
Electrical Specifications
2.4
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
VTT, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 2-6 for details on GTL+ signals that do not include on-die
termination.
Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT). For details see Table 2-13.
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs
must be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing.
All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor
which matches the nominal trace impedance.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
Terminating multiple TESTHI pins together with a single pull-up resistor is not
recommended for designs supporting boundary scan for proper Boundary Scan testing
of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of
the board transmission line traces. For example, if the nominal trace impedance is 50
Ω, then a value between 40 Ω and 60 Ω should be used.
16
Datasheet
Electrical Specifications
2.5
Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have
specifications equal to the FMB value in the foreseeable future. System designers
should meet the FMB values to ensure their systems will be compatible with future
processors. The FMB values are shown in Table 2-3 and Table 5-1.
2.6
Power Segment Identifier (PSID)
Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched
power requirement situations. The PSID mechanism enables BIOS to detect if the
processor in use requires more power than the platform voltage regulator (VR) is
capable of supplying. For example, a 130W TDP processor installed in a board with a
65W or 95W TDP capable VR may draw too much power and cause a potential VR issue.
2.6.1
Absolute Maximum and Minimum Ratings
Table 2-2 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 2-2.
Absolute Maximum and Minimum Ratings
1, 2
Symbol
Parameter
Min
Max
Unit
Notes
V
V
Core voltage with respect to V
FSB termination voltage with
–0.3
–0.3
1.45
1.45
V
V
-
CC
TT
SS
-
respect to V
SS
TCASE
Processor case temperature
Processor storage temperature
See Section 5
–40
See Section 5
85
°C
°C
-
T
3, 4, 5
STORAGE
Notes:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
2.
3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
Datasheet
17
Electrical Specifications
the long-term reliability of the device. For functional operation, refer to the processor case temperature
specifications.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long term reliability of the processor.
4.
5.
2.6.2
DC Voltage and Current Specification
Table 2-3.
Voltage and Current Specifications
2,
Notes
Symbol
VID Range
Parameter
Min
Typ
Max
Unit
11
VID
0.8500
-
1.3625
V
1
Core V
Processor Numbers
(6MB Cache):
V
for
CC
CC
775_VR_CONFIG_06A
Refer to Table 2-4,
Figure 2-1
V
3, 4, 5
E3110
E3120
L3110
3.00 GHz
3.16 GHz
775_VR_CONFIG_06
3.00 GHz
V
V
Default V voltage for initial power up
-
1.10
-
V
CC_BOOT
CCPLL
CC
CC
PLL V
- 5%
-
1.50
-
+ 5%
75
CC
I
2006 FMB
A
V
6
V
FSB termination voltage
(DC + AC specifications)
1.045
1.10
1.155
7, 8
TT
VTT_OUT_LEFT and
VTT_OUT_RIGHT I
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per land
-
-
-
-
580
mA
A
CC
I
I
I
for V supply before V stable
4.5
4.6
9
TT
CC
CC
TT
CC
for V supply after V stable
TT
CC
I
I
I
I
CC for PLL land
130
200
mA
µA
CC_VCCPLL
CC_GTLREF
for GTLREF
-
-
CC
Notes:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Thermal
®
Monitor 2, Enhanced Intel SpeedStep technology, or Extended HALT State).
2.
Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
3.
4.
These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.3 and Table 2-1 for more information.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
5.
Refer to Table 2-4 and Figure 2-1for the minimum, typical, and maximum VCC allowed for a given current.
The processor should not be subjected to any V and I
combination wherein V exceeds V
for a
CC
CC
CC_MAX
CC
given current.
6.
7.
I
specification is based on V
loadline. Refer to Figure 2-1 for details.
CC_MAX
TT
CC_MAX
V
must be provided via a separate voltage source and not be connected to V . This specification is
CC
measured at the land.
8.
9.
Baseboard bandwidth is limited to 20 MHz.
This is the maximum total current drawn from the V plane by only the processor. This specification does
TT
not include the current coming from on-board termination (R ), through the signal line. Refer to the
TT
appropriate platform design guide and the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket to determine the total I drawn by the system. This
TT
parameter is based on design characterization and is not tested.
10. Adherence to the voltage specifications for the processor are required to ensure reliable processor
operation.
18
Datasheet
Electrical Specifications
Table 2-4.
Processor VCC Static and Transient Tolerance
1, 2, 3, 4
Voltage Deviation from VID Setting (V)
I
(A)
CC
Maximum Voltage
Typical Voltage
Minimum Voltage
1.40 mΩ
1.48 mΩ
1.55 mΩ
0
0.000
-0.007
-0.014
-0.021
-0.028
-0.035
-0.042
-0.049
-0.056
-0.063
-0.070
-0.077
-0.084
-0.091
-0.098
-0.105
-0.019
-0.026
-0.034
-0.041
-0.049
-0.056
-0.063
-0.071
-0.078
-0.085
-0.093
-0.100
-0.108
-0.115
-0.122
-0.130
-0.038
-0.046
-0.054
-0.061
-0.069
-0.077
-0.085
-0.092
-0.100
-0.108
-0.116
-0.123
-0.131
-0.139
-0.147
-0.154
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
Notes:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.6.3.
2.
3.
This table is intended to aid in reading discrete points on Figure 2-1.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer
to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket for socket loadline guidelines and VR implementation details.
Adherence to this loadline specification is required to ensure reliable processor operation.
4.
Datasheet
19
Electrical Specifications
Figure 2-1. Processor VCC Static and Transient Tolerance
Icc [A]
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
Vcc Maximum
Vcc Typical
Vcc Minimum
Notes:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.6.3.
2.
3.
This loadline specification shows the deviation from the VID set point.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer
to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket for socket loadline guidelines and VR implementation details.
2.6.3
V
Overshoot
CC
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 2-5.
VCC Overshoot Specifications
Symbol
Parameter
Magnitude of V overshoot above VID
Min
Max
Unit
Figure
Notes
1
1
V
-
-
50
25
mV
µs
2-2
2-2
OS_MAX
CC
T
Time duration of V overshoot above VID
CC
OS_MAX
Notes:
1. Adherence to these specifications is required to ensure reliable processor operation.
20
Datasheet
Electrical Specifications
Figure 2-2.
VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
Notes:
1.
2.
V
is measured overshoot voltage.
is measured time duration above VID.
OS
OS
T
2.6.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 2-5 when
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are <
10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.
2.7
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families. Design guidelines for the processor front
side bus are detailed in the appropriate platform design guides (refer to Section 1.2).
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 2-13 for GTLREF specifications). Refer to the applicable
platform design guidelines for details. Termination resistors (RTT) for GTL+ signals are
Datasheet
21
Electrical Specifications
provided on the processor silicon and are terminated to VTT. Intel chipsets will also
provide on-die termination, thus eliminating the need to terminate the bus on the
motherboard for most GTL+ signals.
2.7.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 2-6 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 2-6.
FSB Signal Groups
1
Signal Group
Type
Signals
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
3
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BR0# , DBSY#, DRDY#, HIT#,
HITM#, LOCK#
GTL+ Source
Synchronous I/O
Synchronous to
assoc. strobe
Signals
Associated Strobe
3
REQ[4:0]#, A[16:3]#
ADSTB0#
3
A[35:17]#
ADSTB1#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
GTL+ Strobes
CMOS
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/
3
NMI, SMI# , STPCLK#, PWRGOOD, SLP#, TCK, TDI, TMS,
TRST#, BSEL[2:0], VID[7:0], PSI#
Open Drain Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO
4
Open Drain Input/
Output
PROCHOT#
2
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]
Power/Other
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0],
COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION,
2
DBR# , VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI,
MSID[1:0]
Notes:
22
Datasheet
Electrical Specifications
1.
2.
Refer to Section 4.2 for signal descriptions.
In processor systems where no debug port is implemented on the system board, these signals are used to
support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
3.
4.
The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 6.1 for details.
PROCHOT# signal type is open drain output and CMOS input.
.
Table 2-7.
Signal Characteristics
Signals with R
Signals with No R
TT
TT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#,
PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY#
A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI,
MSID[1:0], PWRGOOD, RESET#, SMI#, STPCLK#,
TDO, TESTHI[13:0], THERMTRIP#, VID[7:0],
GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL
1
Open Drain Signals
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#,
TDO, FCx
Notes:
1.
Signals that do not have R , nor are actively driven to their high-voltage level.
TT
Table 2-8.
Signal Reference Voltages
GTLREF
V
/2
TT
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#,
1
INIT#, PROCHOT#, PWRGOOD , SMI#,
1
1
1
1
STPCLK#, TCK , TDI , TMS , TRST#
Note:
1.
See Table 2-10 for more information.
2.7.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3 and DC specifications. See Section 6.2 for additional
timing requirements for entering and leaving the low power states.
2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 2-9.
GTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit Notes
V
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
-0.10
GTLREF - 0.10
V
V
V
A
2, 6
3, 4, 6
4, 6
-
IL
V
GTLREF + 0.10
V
+ 0.10
TT
IH
V
V
- 0.10
V
OH
OL
TT
TT
/
TT_MAX
I
N/A
V
[(R
) + (2 * R
)]
ON_MIN
TT_MIN
Datasheet
23
Electrical Specifications
Table 2-9.
GTL+ Signal Group DC Specifications
I
Input Leakage Current
Output Leakage Current
Buffer On Resistance
N/A
N/A
± 100
± 100
9.16
µA
µA
W
7
8
5
LI
I
LO
R
7.49
ON
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
V
V
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
IL
IH
IH
and V
may experience excursions above V ..
OH
TT
Refer to processor I/O Buffer Models for I/V characteristics.
The V referred to in these specifications is the instantaneous V .
Leakage to V with land held at V .
Leakage to V with land held at 300mV.
TT
TT
SS
TT
TT
Table 2-10. Open Drain and TAP Output Signal Group DC Specifications
Uni
t
1
Symbol
Parameter
Min
Max
Notes
V
Output Low Voltage
Output Low Current
0
0.20
50
V
-
OL
I
16
mA
µA
2
3
OL
I
Output Leakage Current
N/A
± 200
LO
Notes:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Measured at V * 0.2V.
For Vin between 0 and V
TT
.
OH
Table 2-11. CMOS Signal Group DC Specifications
Uni
t
1
Symbol
Parameter
Min
Max
Notes
V
Input Low Voltage
-0.10
V
* 0.30
+ 0.10
* 0.10
+ 0.10
V
V
3, 6
IL
TT
V
Input High Voltage
V
* 0.70
V
4, 5, 6
6
IH
TT
TT
V
Output Low Voltage
Output High Voltage
Output Low Current
Output Low Current
Input Leakage Current
Output Leakage Current
-0.10
0.90 * V
V
V
OL
OH
OL
OH
TT
V
V
V
2, 5, 6
6, 7
6, 7
8
TT
TT
I
V
V
* 0.10 / 67
* 0.10 / 67
N/A
V
V
* 0.10 / 27
* 0.10 / 27
± 100
A
TT
TT
TT
TT
I
I
A
I
µA
µA
LI
N/A
± 100
9
LO
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
All outputs are open drain.
V
V
V
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
IL
IH
IH
and V
may experience excursions above V ..
OH
TT
The V referred to in these specifications refers to instantaneous V .
TT
TT
I
is measured at 0.10 * V
I
is measured at 0.90 * V
OL
TT. OH TT.
Leakage to V with land held at V .
Leakage to V with land held at 300 mV.
SS
TT
TT
2.7.3.1
Platform Environment Control Interface (PECI) DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
processor contains Digital Thermal Sensors (DTS) distributed throughout die. These
sensors are implemented as analog-to-digital converters calibrated at the factory for
reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
24
Datasheet
Electrical Specifications
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
Table 2-12. PECI DC Electrical Limits
1
Symbol
Definition and Conditions
Min
Max
Units
Notes
Input Voltage Range
Hysteresis
Vin
-0.15
VTT
-
V
V
2
Vhysteresis
0.1 * VTT
Negative-edge threshold voltage
0.275 *
VTT
0.500 *
VTT
Vn
Vp
V
Positive-edge threshold voltage
0.550 *
VTT
0.725 *
VTT
V
High level output source
Isource
Isink
-6.0
0.5
N/A
1.0
mA
mA
(V
= 0.75 * V
TT)
OH
Low level output sink
(V = 0.25 * V
)
TT
OL
3
High impedance state leakage to V
High impedance leakage to GND
Bus capacitance per node
Ileak+
Ileak-
N/A
N/A
50
10
10
-
µA
µA
TT
3
4
Cbus
N/A
pF
Signal noise immunity above 300 MHz
Vnoise
Notes:
0.1 * VTT
Vp-p
1. V supplies the PECI interface. PECI behavior does not affect V min/max specifications. Please refer to
TT
TT
Table 2-3 for V specifications.
TT
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
.
2.7.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-7 for details on which GTL+ signals do not include on-die
termination. Refer to the appropriate platform design guidelines for specific
implementation details.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits. For more details on platform design, see the
applicable platform design guide.
Table 2-13. GTL+ Bus Voltage Definitions
1
Symbol
Parameter
Min
Typ
Max
Units Notes
GTLREF_PU
GTLREF_PD
GTLREF pull up resistor
GTLREF pull down resistor
Termination Resistance
COMP Resistance
57.6 * 0.99
100 * 0.99
45
57.6
100
57.6 * 1.01
100 * 1.01
55
Ω
Ω
Ω
Ω
Ω
2
2
3
4
4
R
50
TT
COMP[3:0]
COMP8
49.40
49.90
24.90
50.40
COMP Resistance
24.65
25.15
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Datasheet
25
Electrical Specifications
2.
GTLREF is to be generated from V by a voltage divider of 1% resistors. If a Varibale GTLREF circuit is
TT
used on the board (for Quad-Core processors compatibility) the GTLREF lands connected to the Variable
GTLREF circuit may require different resistor values. Each GTLREF land must be connected, refer to the
platform design guide for implementation details.
3.
4.
R
is the on-die termination resistance measured at V /3 of the GTL+ output driver. Refer to the
T
T
T
T
appropriate platform design guide for the board impedance. Refer to processor I/O buffer models for I/V
characteristics.
COMP resistance must be provided on the system board with 1% resistors. See the applicable platform
design guide for implementation details. COMP[3:0] and COMP8 resistors are to V
.
SS
2.8
Clock Specifications
2.8.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to Table 2-14 for the processor supported ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
Table 2-14. Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
Core Frequency
(333 MHz BCLK/1333 MHz
FSB)
1, 2
Notes
1/6
1/7
2 GHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3 GHz
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/10.5
1/11
1/11.5
1/12
1/12.5
1/13
1/13.5
1/14
1/15
3.16 GHz
3.33 GHz
3.50 GHz
3.66 GHz
3.83 GHz
4 GHz
4.16 GHz
4.33 GHz
4.50 GHz
4.66 GHz
5 GHz
Notes:
1.
2.
Individual processors operate only at or below the rated frequency.
Listed frequencies are not necessarily committed production frequencies.
26
Datasheet
Electrical Specifications
2.8.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The processor will operate at a 1333 MHz FSB frequency (selected by a 333 MHz
BCLK[1:0] frequency). Individual processors will only operate at their specified FSB
frequency.
For more information about these signals, refer to Section 4.2 and the appropriate
platform design guidelines.
Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
L
L
H
H
L
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
333 MHz
L
H
H
H
H
L
L
H
H
H
H
L
H
H
L
L
2.8.3
2.8.4
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 2-3 for DC specifications. Refer to the appropriate
platform design guidelines for decoupling and routing guidelines.
BCLK[1:0] Specifications
Table 2-16. Front Side Bus Differential BCLK Specifications
Notes
1
Symbol
Parameter
Min
Typ
Max
Unit Figure
V
Input Low Voltage
Input High Voltage
-0.30
N/A
N/A
N/A
N/A
N/A
1.15
V
V
V
2-3
2-3
2-3
3
3
2
L
V
H
V
Absolute Crossing
Point
0.300
0.550
CROSS(abs)
∆V
CROSS
Range of Crossing
Points
N/A
N/A
0.140
V
2-3
-
V
Overshoot
N/A
N/A
N/A
N/A
1.4
N/A
N/A
V
V
V
2-3
2-3
2-4
4
4
5
OS
US
V
Undershoot
-0.300
0.300
V
DifferentialOutput
Swing
SWING
Notes:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
Datasheet
27
Electrical Specifications
3.
4.
“Steady state” voltage, not including overshoot or undershoot.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute
value of the minimum voltage.
5.
Measurement taken from differential waveform.
Table 2-17. FSB Differential Clock Specifications (1333 MHz FSB)
1
T# Parameter
BCLK[1:0] Frequency
Min
Nom
Max
Unit
Figure
Notes
331.633
2.99970
-
-
-
333.367
3.01538
150
MHz
ns
-
7
T1: BCLK[1:0] Period
2-3
2-3
2-4
2
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew Rate
Slew Rate Matching
-
ps
3
4
2.5
-
8
V/ns
%
5
N/A
N/A
20
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a
333 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this specification as
governed by the period stability specification (T2). Min period specification is based on -300 PPM deviation
from a 3 ns period. Max period specification is based on the summation of +300 PPM deviation from a 3 ns
period and a +0.5% maximum variance due to spread spectrum clocking.
In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
Slew rate is measured through the VSWING voltage range centered about differential zero. Measurement
taken from differential waveform.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a
±75mV window centered on the average cross point where Clock rising meets Clock# falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations.
3.
4.
5.
6.
Duty Cycle (High time/Period) must be between 40 and 60%
Figure 2-3. Differential Clock Waveform
Tph
Overshoot
VH
BCLK1
Rising Edge
Ringback
Ringback
Margin
VCROSS (ABS
)
VCROSS (ABS)
Threshold
Region
Falling Edge
Ringback
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
28
Datasheet
Electrical Specifications
Figure 2-4. Measurement Points for Differential Clock Waveforms
Slew_rise
Slew _fall
+150 mV
+150mV
0.0V
0.0V
V_swing
-150 mV
-150mV
Diff
T5 = BCLK[1:0] rise and fall time through the swing region
§ §
Datasheet
29
Electrical Specifications
30
Datasheet
Package Mechanical Specifications
3 Package Mechanical
Specifications
3.1
Package Mechanical Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch
of the processor package components and how they are assembled together. Refer to
the LGA775 Socket Mechanical Design Guide for complete details on the LGA775
socket.
The package components shown in Figure 3-1 include the following:
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM)
3. Processor core (die)
4. Package substrate
5. Capacitors
Figure 3-1. Processor Package Assembly Sketch
TIM
Core (die)
IHS
Substrate
Capacitors
LGA775 Socket
System Board
Note:
1.
Socket and motherboard are included for reference and are not part of processor package.
3.1.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions include:
1. Package reference with tolerances (total height, length, width, etc.)
2. IHS parallelism and tilt
3. Land dimensions
4. Top-side and back-side component keep-out dimensions
Datasheet
31
Package Mechanical Specifications
5. Reference datums
6. All drawing dimensions are in mm [in].
7. Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal/Mechanical
Design Guidelines.
32
Datasheet
Package Mechanical Specifications
Figure 3-2. Processor Package Drawing Sheet 1 of 3
Datasheet
33
Package Mechanical Specifications
Figure 3-3. Processor Package Drawing Sheet 2 of 3
34
Datasheet
Package Mechanical Specifications
Figure 3-4. Processor Package Drawing Sheet 3 of 3
3.1.2
Processor Component Keep-Out Zones
Datasheet
35
Package Mechanical Specifications
The processor may contain components on the substrate that define component keep-
out zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-
out zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
3.1.3
Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
maintained by any thermal and mechanical solutions.
.
Table 3-1.
Processor Loading Specifications
Parameter
Minimum
Maximum
Notes
Static
80 N [17 lbf]
-
311 N [70 lbf]
756 N [170 lbf]
1, 2, 3
1, 3, 4
Dynamic
Notes:
1.
2.
These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the
minimum specified load on the processor package.
3.
4.
These specifications are based on limited testing for design characterization. Loading limits are for the
package only and do not include the limits of the processor socket.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
3.1.4
Package Handling Guidelines
Table 3-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.
Package Handling Guidelines
Parameter
Maximum Recommended
Notes
Shear
Tensile
Torque
311 N [70 lbf]
111 N [25 lbf]
1, 4
2, 4
3, 4
3.95 N-m [35 lbf-in]
Notes:
1.
2.
3.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.
4.
These guidelines are based on limited testing for design characterization.
3.1.5
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
36
Datasheet
Package Mechanical Specifications
3.1.6
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.
3.1.7
Processor Materials
Table 3-3 lists some of the package components and associated materials.
Table 3-3.
Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel Plated Copper
Fiber Reinforced Resin
Gold Plated Copper
Substrate Lands
3.1.8
Processor Markings
Figure 3-5 shows the topside markings on the processor. This diagram is to aid in the
identification of the processor.
Figure 3-5. Processor Top-Side Markings Example
M
INTEL ©'06 3110
INTEL® XEON®
SLxxx [COO]
3.00GHZ/6M/1333/06
e4
[FPO]
ATPO
S/N
3.1.9
Processor Land Coordinates
Figure 3-6 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
Datasheet
37
Package Mechanical Specifications
.
Figure 3-6. Processor Land Coordinates and Quadrants, Top View
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
W
V
Address/
Common Clock/
Async
Socket 775
Quadrants
Top View
U
U
T
T
R
R
P
P
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
VTT / Clocks
Data
§
38
Datasheet
Land Listing and Signal Descriptions
4 Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
4.1
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 4-1 is a listing of all processor lands ordered alphabetically by land
(signal) name. Table 4-2 is also a listing of all processor lands; the ordering is by land
number.
Datasheet
39
Land Listing and Signal Descriptions
Figure 4-1. land-out Diagram (Top View – Left Side)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AN
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AM
AL
AK
AJ
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AH
AG
AF
AE
AD
AC
AB
AA
Y
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W
V
U
T
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
R
P
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
N
M
L
K
J
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
FC34
VSS
FC31
FC33
VCC
H
BSEL1
BSEL2
FC15
VSS
VSS
VSS
VSS
VSS
VSS
FC32
G
F
BSEL0 BCLK1
TESTHI4
VTT_SEL
TESTH
I5
TESTH
I3
TESTH
I6
RESET D47# D44#
#
DSTBN2 DSTBP
#
D35#
D38#
D36#
D37#
D32#
VSS
D31#
D30#
2#
RSVD
BCLK0
TESTH
I0
TESTH
I2
TESTH
I7
RSVD
VSS
D43#
D41#
VSS
E
FC26
VTT
VSS
VTT
VSS
VTT
VSS
VTT
VSS
VTT
FC10
VSS
RSVD
D45# D42#
VSS
D40#
D39#
VSS
VSS
D34#
RSVD
D33#
VSS
D
VTT
VTT
VCCPL D46# VSS
L
D48#
DBI2#
D49#
C
VTT
VTT
VTT
VTT
VTT
VSS
VCCIO VSS
PLL
D58#
DBI3#
VSS
D54#
DSTBP
3#
VSS
D51#
B
A
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSSA
VCCA
D63# D59#
D62# VSS
VSS
D60#
D61#
D57#
VSS
VSS
D55#
D53#
FC23
RSVD
D56#
DSTBN VSS
3#
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
40
Datasheet
Land Listing and Signal Descriptions
Figure 4-2. land-out Diagram (Top View – Right Side)
14
13
VSS
12
VCC
11
10
9
8
7
6
5
4
3
2
1
VSS_MB_
REGULATION
VCC_MB_
REGULATION
VCC
VCC
VSS
VCC
VCC
VID_S
ELECT
VSS_
SENSE
VCC_
SENSE
VSS
VSS
AN
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VID7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC40
VID3
FC8
VID6
VSS
VID2
VID0
VSS
AM
AL
AK
AJ
VID1
VID5
VID4
VSS
VRDSEL
ITP_CLK0
ITP_CLK1
VSS
PROCHOT#
VSS
FC25
FC24
VSS
A35#
VSS
A34#
A33#
A31#
A27#
VSS
BPM0#
RSVD
BPM1#
VSS
A32#
A30#
A28#
RSVD
VSS
AH
AG
AF
AE
AD
AC
AB
AA
A29#
VSS
BPM5#
VSS
BPM3#
BPM4#
VSS
TRST#
TDO
SKTOCC#
VCC
RSVD
A22#
VSS
FC18
TCK
ADSTB1#
A25#
A24#
A23#
FC36
BPM2#
DBR#
IERR#
FC39
TDI
VCC
RSVD
A26#
A21#
VSS
TMS
VCC
A17#
VSS
FC37
VSS
VCC
VSS
VTT_OUT_
RIGHT
FC0/
BOOTSELECT
VCC
VCC
VSS
VSS
A19#
A18#
VSS
A20#
VSS
PSI#
VSS
Y
A16#
TESTHI1
TESTHI12/
FC44
MSID0
W
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
A14#
A12#
A9#
A15#
A13#
A11#
A8#
VSS
FC30
VSS
RSVD
FC29
FC4
MSID1
FC28
V
U
T
A10#
VSS
COMP1
COMP3
ADSTB0
#
VSS
FERR#/
PBE#
VSS
R
VCC
VCC
VCC
VSS
VSS
VSS
A4#
RSVD
RSVD
A5#
VSS
INIT#
VSS
SMI#
TESTHI11
PWRGOOD
VSS
P
VSS
RSVD
A7#
IGNNE#
N
M
REQ2#
STPCLK#
THERMTRIP
#
VCC
VCC
VCC
VSS
VSS
VSS
VSS
A3#
A6#
VSS
TESTHI13
VSS
LINT1
LINT0
L
K
J
REQ3#
REQ4#
VSS
REQ0#
VSS
A20M#
FC22
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
REQ1#
FC3
VTT_OUT_
LEFT
VSS
VSS
VSS
TESTHI10
FC35
VSS
GTLREF1
GTLREF0
FC27
H
D29# D27#
D28# VSS
DSTBN1# DBI1
#
FC38
VSS
D16#
D18#
BPRI#
D17#
DEFER
#
RSVD
FC21
PECI
TESTHI
9/FC43
TESTHI8/
FC42
COMP2
FC5
G
F
D24#
D23#
VSS
RS1#
VSS
BR0#
VSS
D26#
D25#
DSTBP1#
VSS
VSS
D21#
D22#
D19#
VSS
VSS
RSVD
D20#
RSVD
VSS
FC20
VSS
HITM#
HIT#
TRDY#
VSS
VSS
E
RSVD
D15#
D12#
ADS#
RSVD
D
D52# VSS
D14#
D11#
VSS
FC41
DSTBN0#
VSS
D3#
D1#
VSS
LOCK#
BNR#
DRDY#
C
VSS
COMP8 D13#
VSS
D9#
D10#
D8#
DSTBP0# VSS
D6#
D7#
D5#
VSS
VSS
D4#
D0#
D2#
RS0#
RS2#
DBSY#
VSS
VSS
1
B
A
D50# COMP0 VSS
VSS
DBI0#
14
13
12
11
10
9
8
7
6
5
4
3
2
Datasheet
41
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Land Name
Land #
Direction
Signal
Buffer
Type
Land Name
Land #
Direction
A32#
A33#
A34#
A35#
A4#
AH4
AH5
AJ5
AJ6
P6
Source
Synch
Input/
Output
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A3#
U6
T4
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
U5
Source
Synch
Input/
Output
Source
Synch
Input/
Output
U4
Source
Synch
Input/
Output
Source
Synch
Input/
Output
V5
Source
Synch
Input/
Output
A5#
M5
L4
Source
Synch
Input/
Output
V4
Source
Synch
Input/
Output
A6#
Source
Synch
Input/
Output
W5
AB6
W6
Y6
Source
Synch
Input/
Output
A7#
M4
R4
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A8#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A9#
T5
Source
Synch
Input/
Output
Source
Synch
Input/
Output
ADS#
ADSTB0#
ADSTB1#
D2
Common
Clock
Input/
Output
Y4
Source
Synch
Input/
Output
R6
Source
Synch
Input/
Output
K3
Asynch
CMOS
Input
AD5
Source
Synch
Input/
Output
AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
L5
Source
Synch
Input/
Output
BCLK0
BCLK1
BNR#
F28
G28
C2
Clock
Clock
Input
Input
Source
Synch
Input/
Output
Common
Clock
Input/
Output
Source
Synch
Input/
Output
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
AJ2
AJ1
AD2
AG2
AF2
AG3
G8
Common
Clock
Input/
Output
Source
Synch
Input/
Output
Common
Clock
Input/
Output
Source
Synch
Input/
Output
Common
Clock
Input/
Output
Source
Synch
Input/
Output
Common
Clock
Input/
Output
Source
Synch
Input/
Output
Common
Clock
Input/
Output
Source
Synch
Input/
Output
Common
Clock
Input/
Output
Source
Synch
Input/
Output
Common
Clock
Input
Source
Synch
Input/
Output
F3
Common
Clock
Input/
Output
A30#
A31#
AG4
AG5
Source
Synch
Input/
Output
BSEL0
G29
Asynch
CMOS
Output
Source
Synch
Input/
Output
42
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
COMP8
D0#
H30
G30
A13
T1
Asynch
CMOS
Output
Output
Input
Input
Input
Input
Input
D24#
D25#
D26#
D27#
D28#
D29#
D3#
F12
D13
E13
G13
F14
G14
C6
Source
Synch
Input/
Output
Asynch
CMOS
Source
Synch
Input/
Output
Power/
Other
Source
Synch
Input/
Output
Power/
Other
Source
Synch
Input/
Output
G2
Power/
Other
Source
Synch
Input/
Output
R1
Power/
Other
Source
Synch
Input/
Output
B13
B4
Power/
Other
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D4#
F15
G15
G16
E15
E16
G18
G17
F17
F18
E18
A5
Source
Synch
Input/
Output
D1#
C5
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D2#
B10
C11
D8
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
B12
C12
D11
G9
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
F8
Source
Synch
Input/
Output
Source
Synch
Input/
Output
F9
Source
Synch
Input/
Output
Source
Synch
Input/
Output
E9
Source
Synch
Input/
Output
D40#
D41#
D42#
D43#
D44#
D45#
E19
F20
E21
F21
G21
E22
Source
Synch
Input/
Output
A4
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D20#
D21#
D22#
D23#
D7
Source
Synch
Input/
Output
Source
Synch
Input/
Output
E10
D10
F11
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Datasheet
43
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
D46#
D47#
D48#
D49#
D5#
D22
G22
D20
D17
B6
Source
Synch
Input/
Output
DBI1#
DBI2#
G11
D19
C20
AC2
B2
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
DBI3#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
DBR#
Power/
Other
Output
Source
Synch
Input/
Output
DBSY#
Common
Clock
Input/
Output
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D6#
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B7
Source
Synch
Input/
Output
DEFER#
DRDY#
G7
Common
Clock
Input
Source
Synch
Input/
Output
C1
Common
Clock
Input/
Output
Source
Synch
Input/
Output
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
C8
Source
Synch
Input/
Output
Source
Synch
Input/
Output
G12
G20
A16
B9
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
E12
G19
C17
Y1
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
FC0/
BOOTSELECT
Power/
Other
D60#
D61#
D62#
D63#
D7#
B19
A19
A22
B22
A7
Source
Synch
Input/
Output
FC10
FC15
FC17
FC18
FC20
FC21
FC22
FC23
E24
H29
Y3
Power/
Other
Source
Synch
Input/
Output
Power/
Other
Source
Synch
Input/
Output
Power/
Other
Source
Synch
Input/
Output
AE3
E5
Power/
Other
Source
Synch
Input/
Output
Power/
Other
D8#
A10
A11
A8
Source
Synch
Input/
Output
F6
Power/
Other
D9#
Source
Synch
Input/
Output
J3
Power/
Other
DBI0#
Source
Synch
Input/
Output
A24
Power/
Other
44
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
FC24
FC25
FC26
FC27
FC28
FC29
FC3
AK1
AL1
E29
G1
Power/
Other
GTLREF1
HIT#
H2
D4
E4
Power/
Other
Input
Power/
Other
Common
Clock
Input/
Output
Power/
Other
HITM#
IERR#
IGNNE#
INIT#
Common
Clock
Input/
Output
Power/
Other
AB2
N2
P3
Asynch
CMOS
Output
Input
Input
U1
Power/
Other
Asynch
CMOS
U2
Power/
Other
Asynch
CMOS
J2
Power/
Other
ITP_CLK0
ITP_CLK1
LINT0
AK3
AJ3
K1
TAP
TAP
Input
Input
Input
FC30
FC31
FC32
FC33
FC34
FC35
FC36
FC37
FC38
FC39
FC4
U3
Power/
Other
Asynch
CMOS
J16
H15
H16
J17
H4
Power/
Other
LINT1
LOCK#
MSID0
L1
C3
W1
V1
G5
AL2
N1
K4
J5
Asynch
CMOS
Input
Power/
Other
Common
Clock
Input/
Output
Power/
Other
Power/
Other
Output
Power/
Other
MSID1
Power/
Other
Output
Power/
Other
PECI
Power/
Other
Input/
Output
AD3
AB3
G10
AA2
T2
Power/
Other
PROCHOT#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
Asynch
CMOS
Input/
Output
Power/
Other
Power/
Other
Input
Power/
Other
Source
Synch
Input/
Output
Power/
Other
Source
Synch
Input/
Output
Power/
Other
M6
K6
J6
Source
Synch
Input/
Output
FC40
FC41
FC5
AM6
C9
Power/
Other
Source
Synch
Input/
Output
Power/
Other
Source
Synch
Input/
Output
F2
Power/
Other
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
V2
A20
AC4
AE4
AE6
AH2
D1
FC8
AK6
R3
Power/
Other
FERR#/PBE#
GTLREF0
Asynch
CMOS
Output
Input
H1
Power/
Other
Datasheet
45
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
D14
D16
E23
E6
TESTHI5
TESTHI6
G26
G24
F24
G3
Power/
Other
Input
Input
Input
Input
Input
Output
Power/
Other
TESTHI7
Power/
Other
E7
TESTHI8/FC42
TESTHI9/FC43
THERMTRIP#
Power/
Other
F23
F29
G6
G4
Power/
Other
M2
Asynch
CMOS
N4
N5
TMS
AC1
E3
TAP
Input
Input
P5
TRDY#
Common
Clock
G23
Common
Clock
Input
Input
Input
Input
Output
Input
Input
TRST#
VCC
AG1
AA8
TAP
Input
RS0#
RS1#
B3
F5
Common
Clock
Power/
Other
Common
Clock
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB8
Power/
Other
RS2#
A3
Common
Clock
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC8
Power/
Other
SKTOCC#
SMI#
AE8
P2
Power/
Other
Power/
Other
Asynch
CMOS
Power/
Other
STPCLK#
M3
Asynch
CMOS
Power/
Other
TCK
TDI
AE1
AD1
AF1
F26
TAP
TAP
TAP
Input
Input
Power/
Other
TDO
Output
Input
Power/
Other
TESTHI0
Power/
Other
Power/
Other
TESTHI1
TESTHI10
TESTHI11
TESTHI12/FC44
TESTHI13
TESTHI2
W3
H5
Power/
Other
Input
Input
Input
Input
Input
Input
Input
Input
Power/
Other
Power/
Other
Power/
Other
P1
Power/
Other
AD23
AD24
AD25
AD26
AD27
Power/
Other
W2
L2
Power/
Other
Power/
Other
Power/
Other
Power/
Other
F25
G25
G27
Power/
Other
Power/
Other
TESTHI3
Power/
Other
Power/
Other
TESTHI4
Power/
Other
46
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD28
AD29
AD30
AD8
Power/
Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30
AG8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AE9
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22
AF8
Power/
Other
Power/
Other
Power/
Other
AG9
Power/
Other
Power/
Other
AH11
AH12
AH14
AH15
AH18
AH19
AH21
AH22
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AF9
Power/
Other
Power/
Other
Datasheet
47
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AH25
AH26
AH27
AH28
AH29
AH30
AH8
Power/
Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AK18
AK19
AK21
AK22
AK25
AK26
AK8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AH9
Power/
Other
AK9
Power/
Other
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
Power/
Other
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AJ9
Power/
Other
Power/
Other
AK11
AK12
AK14
AK15
Power/
Other
Power/
Other
Power/
Other
AL9
Power/
Other
Power/
Other
AM11
AM12
Power/
Other
Power/
Other
Power/
Other
48
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
Power/
Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AN8
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AM9
Power/
Other
Power/
Other
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
AN25
AN26
AN29
AN30
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
J9
Power/
Other
Power/
Other
K23
Power/
Other
Datasheet
49
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
K24
K25
K26
K27
K28
K29
K30
K8
Power/
Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N29
N30
N8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
P8
Power/
Other
Power/
Other
R8
Power/
Other
Power/
Other
T23
T24
T25
T26
T27
T28
T29
T30
T8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
L8
Power/
Other
Power/
Other
M23
M24
M25
M26
M27
M28
M29
M30
M8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
U23
U24
U25
U26
U27
U28
U29
U30
U8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
N23
N24
N25
N26
N27
N28
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
V8
Power/
Other
50
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W23
W24
W25
W26
W27
W28
W29
W30
W8
Power/
Other
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VRDSEL
VSS
AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
AL3
B1
Asynch
CMOS
Output
Output
Output
Output
Output
Output
Output
Output
Power/
Other
Asynch
CMOS
Power/
Other
Asynch
CMOS
Power/
Other
Asynch
CMOS
Power/
Other
Asynch
CMOS
Power/
Other
Asynch
CMOS
Power/
Other
Asynch
CMOS
Power/
Other
Asynch
CMOS
Power/
Other
Power/
Other
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
Power/
Other
Power/
Other
Power/
Other
VSS
B11
B14
B17
B20
B24
B5
Power/
Other
Power/
Other
VSS
Power/
Other
Power/
Other
VSS
Power/
Other
Power/
Other
VSS
Power/
Other
Power/
Other
VSS
Power/
Other
Power/
Other
VSS
Power/
Other
Power/
Other
VSS
B8
Power/
Other
Power/
Other
VSS
A12
A15
A18
A2
Power/
Other
VCC_MB_
REGULATION
AN5
AN3
A23
C23
D23
AN7
Power/
Other
Output
Output
VSS
Power/
Other
VCC_SENSE
Power/
Other
VSS
Power/
Other
VCCA
Power/
Other
VSS
Power/
Other
VCCIOPLL
VCCPLL
Power/
Other
VSS
A21
A6
Power/
Other
Power/
Other
VSS
Power/
Other
VID_SELECT
Power/
Other
Output
VSS
A9
Power/
Other
Datasheet
51
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD4
AD7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AE10
AE13
AE16
AE17
AE2
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE5
Power/
Other
AA30
AA6
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AA7
Power/
Other
Power/
Other
AB1
Power/
Other
Power/
Other
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AE7
Power/
Other
Power/
Other
AF10
AF13
AF16
AF17
AF20
AF23
AF24
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AC3
Power/
Other
Power/
Other
AC6
Power/
Other
Power/
Other
AC7
Power/
Other
Power/
Other
52
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF25
AF26
AF27
AF28
AF29
AF3
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH24
AH3
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AH6
Power/
Other
Power/
Other
AH7
Power/
Other
Power/
Other
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
Power/
Other
Power/
Other
Power/
Other
AF30
AF6
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AF7
Power/
Other
Power/
Other
AG10
AG13
AG16
AG17
AG20
AG23
AG24
AG7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AJ7
Power/
Other
AH1
Power/
Other
AK10
AK13
AK16
AK17
AK2
Power/
Other
AH10
AH13
AH16
AH17
AH20
AH23
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AK20
AK23
Power/
Other
Power/
Other
Power/
Other
Datasheet
53
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK24
AK27
AK28
AK29
AK30
AK5
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM24
AM27
AM28
AM4
AN1
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AN10
AN13
AN16
AN17
AN2
Power/
Other
AK7
Power/
Other
Power/
Other
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AN20
AN23
AN24
AN27
AN28
C10
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
C13
Power/
Other
AM1
Power/
Other
C16
Power/
Other
AM10
AM13
AM16
AM17
AM20
AM23
Power/
Other
C19
Power/
Other
Power/
Other
C22
Power/
Other
Power/
Other
C24
Power/
Other
Power/
Other
C4
Power/
Other
Power/
Other
C7
Power/
Other
Power/
Other
D12
Power/
Other
54
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D15
D18
D21
D24
D3
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F7
Power/
Other
Power/
Other
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
D5
Power/
Other
Power/
Other
D6
Power/
Other
Power/
Other
D9
Power/
Other
Power/
Other
E11
E14
E17
E2
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
E20
E25
E26
E27
E28
E8
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
F10
F13
F16
F19
F22
F4
Power/
Other
Power/
Other
Power/
Other
H6
Power/
Other
Power/
Other
H7
Power/
Other
Power/
Other
H8
Power/
Other
Power/
Other
H9
Power/
Other
Power/
Other
J4
Power/
Other
Datasheet
55
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J7
K2
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P27
P28
P29
P30
P4
Power/
Other
Power/
Other
Power/
Other
K5
Power/
Other
Power/
Other
K7
Power/
Other
Power/
Other
L23
L24
L25
L26
L27
L28
L29
L3
Power/
Other
Power/
Other
Power/
Other
P7
Power/
Other
Power/
Other
R2
Power/
Other
Power/
Other
R23
R24
R25
R26
R27
R28
R29
R30
R5
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
L30
L6
Power/
Other
Power/
Other
Power/
Other
Power/
Other
L7
Power/
Other
Power/
Other
M1
M7
N3
Power/
Other
Power/
Other
Power/
Other
R7
Power/
Other
Power/
Other
T3
Power/
Other
N6
Power/
Other
T6
Power/
Other
N7
Power/
Other
T7
Power/
Other
P23
P24
P25
P26
Power/
Other
U7
Power/
Other
Power/
Other
V23
V24
V25
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
56
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal
Buffer
Type
Signal
Buffer
Type
Land Name
Land #
Direction
Land Name
Land #
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V26
V27
V28
V29
V3
Power/
Other
VTT
A27
A28
A29
A30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
J1
Power/
Other
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
V30
V6
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
V7
Power/
Other
VTT
Power/
Other
W4
W7
Y2
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
Y5
Power/
Other
VTT
VTT
Power/
Other
Y7
Power/
Other
Power/
Other
VSS_MB_
REGULATION
AN6
AN4
B23
B25
B26
B27
B28
B29
B30
A25
A26
Power/
Other
Output
Output
VTT
Power/
Other
VSS_SENSE
VSSA
VTT
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
Power/
Other
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_SEL
Power/
Other
Output
Output
Output
VTT
Power/
Other
AA1
F27
Power/
Other
VTT
Power/
Other
Power/
Other
VTT
Power/
Other
VTT
Power/
Other
VTT
Power/
Other
VTT
Power/
Other
VTT
Power/
Other
Datasheet
57
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land #
Direction
Land
Signal
Land #
Direction
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A21#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Name
Buffer Type
A10
D08#
Source
Synch
Input/
Output
A11
D09#
Source
Synch
Input/
Output
A12
VSS
Power/Other
Power/Other
A13
A14
COMP0
D50#
Input
Source
Synch
Input/
Output
AA30
AA4
A15
A16
VSS
Power/Other
Source
Synch
Input/
Output
DSTBN3#
Source
Synch
Input/
Output
AA5
A23#
Source
Synch
Input/
Output
A17
D56#
Source
Synch
Input/
Output
AA6
AA7
AA8
AB1
AB2
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
A18
A19
VSS
Power/Other
D61#
Source
Synch
Input/
Output
VCC
A2
VSS
RESERVED
VSS
Power/Other
VSS
A20
A21
A22
IERR#
Asynch
CMOS
Output
Power/Other
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC37
VSS
A26#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D62#
Source
Synch
Input/
Output
A23
A24
A25
A26
A27
A28
A29
A3
VCCA
FC23
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
VTT
AB30
AB4
RS2#
Common
Clock
Input
Source
Synch
Input/
Output
A30
A4
VTT
Power/Other
AB5
AB6
A24#
A17#
Source
Synch
Input/
Output
D02#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A5
D04#
Source
Synch
Input/
Output
AB7
AB8
VSS
VCC
TMS
DBR#
VCC
VCC
VCC
VCC
Power/Other
Power/Other
TAP
A6
A7
VSS
Power/Other
D07#
Source
Synch
Input/
Output
AC1
Input
AC2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
A8
DBI0#
VSS
Source
Synch
Input/
Output
AC23
AC24
AC25
AC26
A9
Power/Other
Power/Other
AA1
VTT_OUT_
RIGHT
Output
AA2
FC39
Power/Other
58
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
AC27
AC28
AC29
AC3
VCC
VCC
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE2
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
FC18
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE3
AC30
AC4
AC5
RESERVED
A25#
Source
Synch
Input/
Output
AC6
AC7
AC8
AD1
AD2
VSS
VSS
Power/Other
Power/Other
Power/Other
TAP
VCC
TDI
Input
BPM2#
Common
Clock
Input/
Output
AE30
AE4
AE5
RESERVED
VSS
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD3
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE6
RESERVED
VSS
VCC
AE7
Power/Other
Power/Other
Power/Other
TAP
VCC
AE8
SKTOCC#
VCC
Output
Output
VCC
AE9
VCC
AF1
TDO
VCC
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF2
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FC36
VCC
VCC
AD30
AD4
VCC
VSS
VSS
AD5
ADSTB1#
Source
Synch
Input/
Output
VCC
AD6
A22#
Source
Synch
Input/
Output
VCC
VSS
AD7
AD8
VSS
VCC
TCK
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
TAP
VSS
VCC
AE1
Input
VCC
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
BPM4#
Common
Clock
Input/
Output
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Datasheet
59
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
AF28
AF29
AF3
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
AG6
A29#
Source
Synch
Input/
Output
AG7
AG8
VSS
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
AF30
AF4
VSS
AG9
A28#
Source
Synch
Input/
Output
AH1
AF5
A27#
Source
Synch
Input/
Output
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH2
VSS
VCC
VCC
VSS
AF6
AF7
VSS
VSS
VCC
VCC
TRST#
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
TAP
AF8
VCC
VCC
VSS
AF9
AG1
Input
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCC
VCC
RESERVED
VSS
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VSS
AG2
BPM3#
Common
Clock
Input/
Output
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG3
VSS
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AH30
AH4
VCC
A32#
VSS
Source
Synch
Input/
Output
VCC
VCC
VCC
VCC
VCC
BPM5#
AH5
A33#
Source
Synch
Input/
Output
AH6
AH7
AH8
AH9
AJ1
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Common
Clock
Input/
Output
VCC
VCC
AG30
AG4
VCC
Power/Other
BPM1#
Common
Clock
Input/
Output
A30#
Source
Synch
Input/
Output
AJ10
AJ11
VSS
VCC
Power/Other
Power/Other
AG5
A31#
Source
Synch
Input/
Output
60
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AK19
AK2
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AJ2
BPM0#
Common
Clock
Input/
Output
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ3
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
VCC
AK3
AK30
AK4
ITP_CLK0
VSS
Input
VSS
Power/Other
VSS
VID4
Asynch
CMOS
Output
VCC
VCC
AK5
AK6
VSS
FC8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
AK7
VSS
VSS
AK8
VCC
ITP_CLK1
VSS
Input
AK9
VCC
AJ30
AJ4
Power/Other
Power/Other
AL1
FC25
VSS
VSS
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL2
AJ5
A34#
Source
Synch
Input/
Output
VCC
VCC
AJ6
A35#
Source
Synch
Input/
Output
VSS
VCC
AJ7
AJ8
VSS
VCC
VCC
FC24
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VSS
AJ9
VSS
AK1
VCC
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
VCC
PROCHOT#
Asynch
CMOS
Input/
Output
AL20
AL21
AL22
AL23
AL24
AL25
VSS
VCC
VCC
VSS
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Datasheet
61
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
AL26
AL27
AL28
AL29
VCC
VSS
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM4
AM5
VSS
Power/Other
VID6
Asynch
CMOS
Output
AM6
AM7
FC40
VID7
Power/Other
Asynch
CMOS
Output
AL3
AL30
AL4
VRDSEL
VCC
AM8
AM9
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VID5
Asynch
CMOS
Output
Output
Output
AN1
AL5
AL6
VID1
VID3
Asynch
CMOS
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN2
Asynch
CMOS
AL7
AL8
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VID0
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL9
AM1
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM2
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN3
Asynch
CMOS
Output
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM3
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VID2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC_SENS Power/Other
E
Output
AN30
AN4
VCC
Power/Other
VSS_SENS Power/Other
E
Output
Output
AN5
AN6
AN7
VCC_MB_
REGULATI
ON
Power/Other
VSS_MB_
REGULATI
ON
Power/Other
Output
Output
Asynch
CMOS
Output
VID_SELEC Power/Other
T
AM30
VCC
Power/Other
62
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
AN8
AN9
B1
VCC
VCC
Power/Other
Power/Other
Power/Other
B9
C1
DSTBP0#
DRDY#
Source
Synch
Input/
Output
Common
Clock
Input/
Output
VSS
B10
D10#
Source
Synch
Input/
Output
C10
C11
VSS
Power/Other
D11#
Source
Synch
Input/
Output
B11
B12
VSS
Power/Other
D13#
Source
Synch
Input/
Output
C12
D14#
Source
Synch
Input/
Output
B13
COMP8
Power/
Other
Input
C13
C14
VSS
Power/Other
D52#
Source
Synch
Input/
Output
B14
B15
VSS
Power/Other
D53#
Source
Synch
Input/
Output
C15
D51#
Source
Synch
Input/
Output
B16
D55#
Source
Synch
Input/
Output
C16
C17
VSS
Power/Other
DSTBP3#
Source
Synch
Input/
Output
B17
B18
VSS
Power/Other
D57#
Source
Synch
Input/
Output
C18
D54#
Source
Synch
Input/
Output
B19
B2
D60#
Source
Synch
Input/
Output
C19
C2
VSS
Power/Other
BNR#
Common
Clock
Input/
Output
DBSY#
Common
Clock
Input/
Output
C20
C21
DBI3#
D58#
Source
Synch
Input/
Output
B20
B21
VSS
Power/Other
D59#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
B22
D63#
Source
Synch
Input/
Output
C22
C23
C24
C25
C26
C27
C28
C29
C3
VSS
VCCIOPLL
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B23
B24
B25
B26
B27
B28
B29
B3
VSSA
VSS
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
LOCK#
Common
Clock
Input/
Output
RS0#
Common
Clock
Input
C30
C4
VTT
VSS
Power/Other
Power/Other
B30
B4
VTT
Power/Other
D00#
Source
Synch
Input/
Output
C5
D01#
Source
Synch
Input/
Output
B5
B6
VSS
Power/Other
C6
D03#
Source
Synch
Input/
Output
D05#
Source
Synch
Input/
Output
C7
C8
VSS
Power/Other
B7
B8
D06#
VSS
Source
Synch
Input/
Output
DSTBN0#
Source
Synch
Input/
Output
Power/Other
Datasheet
63
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
C9
FC41
Power/
Other
E11
E12
VSS
Power/Other
DSTBP1#
Source
Synch
Input/
Output
D1
RESERVED
D22#
D10
Source
Synch
Input/
Output
E13
D26#
Source
Synch
Input/
Output
D11
D15#
Source
Synch
Input/
Output
E14
E15
VSS
Power/Other
D33#
Source
Synch
Input/
Output
D12
D13
VSS
Power/Other
D25#
Source
Synch
Input/
Output
E16
D34#
Source
Synch
Input/
Output
D14
D15
D16
D17
RESERVED
VSS
E17
E18
VSS
Power/Other
Power/Other
D39#
Source
Synch
Input/
Output
RESERVED
D49#
E19
D40#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
E2
VSS
VSS
Power/Other
Power/Other
D18
D19
VSS
Power/Other
E20
E21
DBI2#
Source
Synch
Input/
Output
D42#
Source
Synch
Input/
Output
D2
ADS#
D48#
Common
Clock
Input/
Output
E22
D45#
Source
Synch
Input/
Output
D20
Source
Synch
Input/
Output
E23
E24
RESERVED
FC10
D21
D22
VSS
Power/Other
Power/
Other
D46#
Source
Synch
Input/
Output
E25
E26
E27
E28
E29
E3
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D23
D24
D25
D26
D27
D28
D29
D3
VCCPLL
VSS
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VTT
FC26
TRDY#
VTT
Common
Clock
Input
VTT
E4
HITM#
Common
Clock
Input/
Output
VTT
VSS
VTT
E5
E6
E7
E8
E9
FC20
RESERVED
RESERVED
VSS
Power/Other
D30
D4
HIT#
Common
Clock
Input/
Output
Power/Other
D5
D6
D7
VSS
VSS
Power/Other
Power/Other
D19#
Source
Synch
Input/
Output
D20#
Source
Synch
Input/
Output
F10
F11
VSS
Power/Other
D23#
Source
Synch
Input/
Output
D8
D12#
Source
Synch
Input/
Output
F12
F13
D24#
VSS
Source
Synch
Input/
Output
D9
VSS
Power/Other
E10
D21#
Source
Synch
Input/
Output
Power/Other
64
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
F14
D28#
Source
Synch
Input/
Output
G15
D31#
Source
Synch
Input/
Output
F15
D30#
Source
Synch
Input/
Output
G16
G17
G18
D32#
D36#
D35#
Source
Synch
Input/
Output
F16
F17
VSS
Power/Other
Source
Synch
Input/
Output
D37#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
F18
D38#
Source
Synch
Input/
Output
G19
DSTBP2#
Source
Synch
Input/
Output
F19
F2
VSS
FC5
Power/Other
Power/Other
G2
COMP2
Power/Other
Input
G20
DSTBN2#
Source
Synch
Input/
Output
F20
D41#
Source
Synch
Input/
Output
G21
G22
G23
D44#
D47#
Source
Synch
Input/
Output
F21
F22
D43#
VSS
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Power/Other
F23
F24
F25
F26
F27
F28
F29
F3
RESERVED
TESTHI7
TESTHI2
TESTHI0
VTT_SEL
BCLK0
RESET#
Common
Clock
Input
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Output
Input
G24
G25
G26
G27
G28
G29
TESTHI6
TESTHI3
TESTHI5
TESTHI4
BCLK1
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Input
Input
Output
RESERVED
BR0#
BSEL0
Asynch
CMOS
Common
Clock
Input/
Output
G3
G30
G4
TESTHI8/
FC42
Power/Other
Input
Output
Input
F4
F5
VSS
Power/Other
RS1#
Common
Clock
Input
BSEL2
Asynch
CMOS
F6
F7
F8
FC21
VSS
Power/Other
Power/Other
TESTHI9/
FC43
Power/Other
G5
PECI
Power/Other
Input/
Output
D17#
Source
Synch
Input/
Output
G6
G7
RESERVED
DEFER#
F9
D18#
Source
Synch
Input/
Output
Common
Clock
Input
Input
G1
FC27
FC38
Power/Other
G8
G9
BPRI#
D16#
Common
Clock
G10
Power/
Other
Source
Synch
Input/
Output
G11
G12
G13
G14
DBI1#
DSTBN1#
D27#
Source
Synch
Input/
Output
H1
GTLREF0
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
Source
Synch
Input/
Output
H10
H11
H12
H13
Source
Synch
Input/
Output
VSS
VSS
D29#
Source
Synch
Input/
Output
VSS
Datasheet
65
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
H14
H15
H16
H17
H18
H19
VSS
FC32
FC33
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J21
J22
J23
J24
J25
J26
J27
J28
J29
J3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC22
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
H2
GTLREF1
VSS
Input
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H3
VSS
VSS
VSS
J30
J4
VSS
VSS
J5
REQ1#
Source
Synch
Input/
Output
VSS
J6
REQ4#
Source
Synch
Input/
Output
VSS
VSS
J7
J8
J9
K1
VSS
VCC
Power/Other
Power/Other
Power/Other
FC15
VSS
VCC
H30
BSEL1
Asynch
CMOS
Output
Input
LINT0
Asynch
CMOS
Input
H4
H5
H6
H7
H8
H9
J1
FC35
TESTHI10
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
K2
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
K23
K24
K25
K26
K27
K28
K29
K3
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VTT_OUT_
LEFT
Output
VCC
VCC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J2
VCC
VCC
VCC
VCC
VCC
VCC
FC31
FC34
VCC
VCC
FC3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A20M#
Asynch
CMOS
Input
K30
K4
VCC
Power/Other
REQ0#
Source
Synch
Input/
Output
K5
K6
VSS
Power/Other
REQ3#
Source
Synch
Input/
Output
K7
K8
L1
VSS
VCC
Power/Other
Power/Other
LINT1
Asynch
CMOS
Input
Input
L2
TESTHI13
Power/Other
J20
VCC
66
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
L23
L24
L25
L26
L27
L28
L29
L3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A06#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
N26
N27
N28
N29
N3
VCC
VCC
VCC
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
N30
N4
N5
N6
N7
N8
P1
P2
RESERVED
RESERVED
VSS
L30
L4
Power/Other
Power/Other
Power/Other
Power/Other
Source
Synch
Input/
Output
VSS
VCC
L5
A03#
Source
Synch
Input/
Output
TESTHI11
SMI#
Input
Input
Asynch
CMOS
L6
L7
L8
M1
VSS
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
P23
P24
P25
P26
P27
P28
P29
P3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
INIT#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
M2
THERMTRI
P#
Asynch
CMOS
Output
M23
M24
M25
M26
M27
M28
M29
M3
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
Asynch
CMOS
Input
VCC
VCC
P30
P4
VSS
VSS
Power/Other
Power/Other
VCC
VCC
P5
RESERVED
A04#
STPCLK#
Asynch
CMOS
Input
P6
Source
Synch
Input/
Output
M30
M4
VCC
Power/Other
P7
P8
VSS
VCC
COMP3
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A07#
Source
Synch
Input/
Output
R1
Input
M5
M6
A05#
Source
Synch
Input/
Output
R2
REQ2#
Source
Synch
Input/
Output
R23
R24
R25
R26
R27
R28
R29
R3
VSS
VSS
M7
M8
N1
N2
VSS
VCC
Power/Other
Power/Other
VSS
VSS
PWRGOOD Power/Other
Input
Input
VSS
IGNNE#
Asynch
CMOS
VSS
N23
N24
N25
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
VSS
FERR#/
PBE#
Asynch
CMOS
Output
Datasheet
67
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
R30
R4
VSS
Power/Other
U6
A10#
Source
Synch
Input/
Output
A08#
Source
Synch
Input/
Output
U7
U8
VSS
VCC
Power/Other
Power/Other
Power/Other
R5
VSS
Power/Other
R6
ADSTB0#
Source
Synch
Input/
Output
V1
MSID1
RESERVED
VSS
Output
V2
R7
R8
T1
T2
VSS
VCC
Power/Other
Power/Other
Power/Other
V23
V24
V25
V26
V27
V28
V29
V3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
COMP1
FC4
Input
VSS
Power/
Other
VSS
VSS
T23
T24
T25
T26
T27
T28
T29
T3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
A11#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
V30
V4
VSS
A15#
Source
Synch
Input/
Output
V5
A14#
Source
Synch
Input/
Output
T30
T4
V6
V7
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Source
Synch
Input/
Output
V8
VCC
T5
A09#
Source
Synch
Input/
Output
W1
W2
MSID0
Output
Input
TESTHI12/ Power/Other
FC44
T6
T7
VSS
VSS
VCC
FC28
FC29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC30
VCC
A13#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
W23
W24
W25
W26
W27
W28
W29
W3
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
T8
U1
VCC
U2
VCC
U23
U24
U25
U26
U27
U28
U29
U3
VCC
VCC
VCC
TESTHI1
VCC
Input
W30
W4
VSS
W5
A16#
Source
Synch
Input/
Output
U30
U4
W6
A18#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
W7
W8
VSS
VCC
Power/Other
Power/Other
U5
A12#
Source
Synch
Input/
Output
68
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
Name
Signal
Buffer Type
Land
Name
Signal
Buffer Type
Land #
Direction
Land #
Direction
Y1
FC0/
BOOTSELE
CT
Power/Other
Y30
Y4
VCC
Power/Other
A20#
Source
Synch
Input/
Output
Y2
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC17
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Y5
Y6
VSS
Power/Other
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y3
A19#
Source
Synch
Input/
Output
Y7
Y8
VSS
VCC
Power/Other
Power/Other
Datasheet
69
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 4-3.
Signal Description (Sheet 1 of 8)
Name
A[35:3]#
Type
Description
36
Input/ A[35:3]# (Address) define a 2 -byte physical memory address space. In
Output sub-phase 1 of the address phase, these signals transmit the address of a
transaction. In sub-phase 2, these signals transmit transaction type
information. These signals must connect the appropriate pins/lands of all
agents on the processor FSB. A[35:3]# are source synchronous signals and
are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a
subset of the A[35:3]# signals to determine power-on configuration. See
Section 6.1 for more details.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1-MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this
signal following an Input/Output write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus
transaction.
ADS#
Input/ ADS# (Address Strobe) is asserted to indicate the validity of the transaction
Output address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the
ADS# activation to begin protocol checking, address decode, internal snoop,
or deferred reply ID match operations associated with the new transaction.
ADSTB[1:0]#
Input/ Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising
Output and falling edges. Strobes are associated with signals as shown below.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All
processor FSB agents must receive these signals to drive their outputs and
latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing V
.
CROSS
BNR#
Input/ BNR# (Block Next Request) is used to assert a bus stall by any bus agent
Output unable to accept new bus transactions. During a bus stall, the current bus
owner cannot issue any new transactions.
BPM[5:0]#
Input/ BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
Output signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins/lands of all
processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY#
is a processor output used by debug tools to determine processor debug
readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the processor.
Refer to the appropriate platform design guide for more detailed information.
These signals do not have on-die termination. Refer to Section 2.7.2, and
appropriate platform design guide for termination requirements.
70
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 2 of 8)
Name
Type
Description
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor FSB. It must connect the appropriate pins/lands of all processor
FSB agents. Observing BPRI# active (as asserted by the priority agent)
causes all other agents to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed, then releases the bus by de-
asserting BPRI#.
BR0#
Input/ BR0# drives the BREQ0# signal in the system and is used by the processor
Output to request the bus. During power-on configuration this signal is sampled to
determine the agent ID = 0.
This signal does not have on-die termination and must be terminated.
BSEL[2:0]
Output The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the
processor input clock frequency. Table 2-15 defines the possible
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset
and clock synthesizer. All agents must operate at the same frequency. For
more information about these signals, including termination
recommendations refer to Section 2.9.2 and the appropriate platform design
guidelines.
COMP[3:0], COMP8
D[63:0]#
Analog COMP[3:0] and COMP8 must be terminated to V on the system board using
SS
precision resistors. Refer to the appropriate platform design guide for details
on implementation.
Input/ D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
Output path between the processor FSB agents, and must connect the appropriate
pins/lands on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond
to a pair of one DSTBP# and one DSTBN#. The following table shows the
grouping of data signals to data strobes and DBI#.
Quad-Pumped Signal Groups
DSTBN#/
DSTBP#
Data Group
DBI#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# signals determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DBI# signal. When the
DBI# signal is active, the corresponding data group is inverted and therefore
sampled active high.
DBI[3:0]#
Input/ DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the
Output polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when
the data on the data bus is inverted. If more than half the data bits, within a
16-bit group, would have been asserted electrically low, the bus agent may
invert the data bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI3#
DBI2#
DBI1#
DBI0#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
Datasheet
71
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 3 of 8)
Name
Type
Description
DBR#
Output DBR# (Debug Reset) is used only in processor systems where no debug port
is implemented on the system board. DBR# is used by a debug port
interposer so that an in-target probe can drive system reset. If a debug port
is implemented in the system, DBR# is a no connect in the system. DBR# is
not a processor signal.
DBSY#
Input/ DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data
Output on the processor FSB to indicate that the data bus is in use. The data bus is
released after DBSY# is de-asserted. This signal must connect the
appropriate pins/lands on all processor FSB agents.
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
ensured in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or input/output agent. This signal
must connect the appropriate pins/lands of all processor FSB agents.
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use
of the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms. Refer to
the appropriate platform design guide for implementation details.
DPRSTP#
Input
NOTE: Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms. Refer to the
appropriate platform design guide for implementation details.
DPSLP#
Input
NOTE: Some processors may not have the Deep Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
DRDY#
Input/ DRDY# (Data Ready) is asserted by the data driver on each data transfer,
Output indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be de-asserted to insert idle clocks. This signal must connect the
appropriate pins/lands of all processor FSB agents.
DSTBN[3:0]#
Input/ DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Output
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
72
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 4 of 8)
Name
Type
Description
DSTBP[3:0]#
Input/ DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Output
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FC0/BOOTSELECT
Other
Other
FC0/BOOTSELECT is not used by the processor. When this land is tied to Vss
previous processors based on the Intel NetBurst® microarchitecture should
be disabled and prevented from booting. Refer to appropriate platform
design guide for termination guidance.
FCx
FC signals are signals that are available for compatibility with other
processors. Refer to the appropriate platform design guide for more
information on how these are connected on the motherboard.
FERR#/PBE#
Output FERR#/PBE# (floating point error/pending break event) is a multiplexed
signal and its meaning is qualified by STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating-point error and will be asserted
when the processor detects an unmasked floating-point error. When
STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on
the Intel 387 coprocessor, and is included for compatibility with systems
using MS-DOS*-type floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state. For
additional information on the pending break event functionality, including the
identification of support of the feature and enable/disable information, refer
to volume 3 of the Intel Architecture Software Developer's Manual and the
Intel Processor Identification and the CPUID Instruction application note.
GTLREF[1:0]
Input
GTLREF[1:0] determine the signal reference level for GTL+ input signals.
GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or
logical 1. Refer to the applicable platform design guide for more information.
HIT#
Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
Output operation results. Any FSB agent may assert both HIT# and HITM# together
to indicate that it requires a snoop stall, which can be continued by
HITM#
reasserting HIT# and HITM# together.
Input/
Output
IERR#
Output IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor FSB. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The
processor will keep IERR# asserted until the assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.7.2 for
termination requirements.
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions.
If IGNNE# is de-asserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction
caused an error. IGNNE# has no effect when the NE bit in control register 0
(CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an Input/Output write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus
transaction.
Datasheet
73
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 5 of 8)
Name
Type
Description
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-point registers. The
processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins/lands of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#,
then the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0]
LINT[1:0]
Input
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
used as BCLK[1:0] references for a debug port implemented on an
interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are
no connects in the system. These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of
all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes
INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium processor. Both signals are
asynchronous.
Both of these signals must be software configured via BIOS programming of
the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after Reset, operation of these signals as
LINT[1:0] is the default configuration.
LOCK#
Input/ LOCK# indicates to the system that a transaction must occur atomically. This
Output signal must connect the appropriate pins/lands of all processor FSB agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning
of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# de-asserted. This enables
symmetric agents to retain ownership of the processor FSB throughout the
bus locked operation and ensure the atomicity of lock.
MSID[1:0]
Output On a processor these signals are connected on the package to Vss. As an
alternative to MSID, Intel has implemented the Power Segment Identifier
(PSID) to report the maximum Thermal Design Power of the processor. Refer
to the Platform Design Guide for additional information regarding PSID.
PECI
Input/ PECI is a proprietary one-wire bus interface. See Chapter 5.3 for details.
Output
PROCHOT#
Input/ As an output, PROCHOT# (Processor Hot) will go active when the processor
Output temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#. See
Section 5.2.4 for more details.
PSI#
Output Processor Power Status Indicator Signal. This signal may be asserted when
the processor is in the Deeper Sleep State. PSI# can be used to improve load
efficiency of the voltage regulator, resulting in platfrom power savings. Refer
to the Voltage Regulator-Down (VRD) 11.1 Processor Power Delivery Design
Guidelines for details on the PSI# signal.
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable
and within their specifications. ‘Clean’ implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
74
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 6 of 8)
Name
REQ[4:0]#
Type
Description
Input/ REQ[4:0]# (Request Command) must connect the appropriate pins/lands of
Output all processor FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB0#.
RESET#
Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For
a power-on Reset, RESET# must stay active for at least one millisecond after
V
and BCLK have reached their proper specifications. On observing active
CC
RESET#, all FSB agents will de-assert their outputs within two clocks.
RESET# must not be kept asserted for more than 10 ms while PWRGOOD is
asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are
described in the Section 6.1.
This signal does not have on-die termination and must be terminated on the
system board.
RESERVED
RS[2:0]#
SKTOCC#
SMI#
All RESERVED lands must remain unconnected. Connection of these lands to
V
, V , V , or to any other signal (including each other) can result in
CC
SS TT
component malfunction or incompatibility with future processors.
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins/lands of all processor FSB agents.
Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor.
System board designers may use this signal to determine if the processor is
present.
Input
Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-
state its outputs.
STPCLK#
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core
units except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK#
is de-asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
Input
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI provides
the serial input needed for JTAG specification support.
TDO
Output TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI[13:0]
Input
TESTHI[13:0] must be connected to the processor’s appropriate power
source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description)
through a resistor for proper processor operation. See Section 2.4 for more
details.
Datasheet
75
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 7 of 8)
Name
Type
Description
THERMTRIP#
Output In the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached a temperature approximately 20 °C
above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates
the processor junction temperature has reached a level beyond where
permanent silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect the
processor, its core voltage (V ) must be removed following the assertion of
CC
THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 µs of
the assertion of PWRGOOD (provided V and V are asserted) and is
TT
CC
disabled on de-assertion of PWRGOOD (if V or V are not valid,
TT
CC
THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains
latched until PWRGOOD, V or V is de-asserted. While the de-assertion of
TT
CC
the PWRGOOD, V or V signal will de-assert THERMTRIP#, if the
TT
CC
processor’s junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted within 10 µs of the assertion of
PWRGOOD (provided V and V are valid).
TT
CC
TMS
Input
Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY#
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins/lands of all FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. Refer to the eXtended Debug Port: Debug
Port Design Guide for UP and DP Platforms for complete implementation
details.
VCC
Input
Input
VCC are the power pins for the processor. The voltage supplied to these pins
is determined by the VID[7:0] pins.
VCCA
VCCA provides isolated power for internal PLLs on previous generation
processors. It may be left as a No-Connect on boards supporting the Wolfdale
processor.
VCCIOPLL
Input
Input
VCCIOPLL provides isolated power for internal processor FSB PLLs on
previous generation processors. It may be left as a No-Connect on boards
supporting the Wolfdale processor.
VCCPLL
VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE
Output VCC_SENSE is an isolated low impedance connection to processor core power
(V ). It can be used to sense or measure voltage near the silicon with little
CC
noise.
VCC_MB_
REGULATION
Output This land is provided as a voltage regulator feedback sense point for V . It is
CC
connected internally in the processor package to the sense point land U27 as
described in the Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines For Desktop LGA775 Socket.
VID[7:0]
Output The VID (Voltage ID) signals are used to support automatic selection of
power supply voltages (V ). Refer to the appropriate platform design guide
CC
or the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information. The voltage
supply for these signals must be valid before the VR can supply V to the
CC
processor. Conversely, the VR output must be disabled until the voltage
supply for the VID signals becomes valid. The VID signals are needed to
support the processor voltage specification variations. See Table 2-1 for
definitions of these signals. The VR must supply the voltage that is requested
by the signals, or disable itself.
VID_SELECT
Output This land is tied high on the processor package and is used by the VR to
choose the proper VID table. Refer to the appropriate platform design guide
or the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information.
VRDSEL
VSS
Input
This input should be left as a no connect in order for the processor to boot.
The processor will not boot on legacy platforms where this land is connected
to V
.
SS
Input
VSS are the ground pins for the processor and should be connected to the
system ground plane.
76
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 8 of 8)
Name
Type
Description
VSSA
Input
VSSA provides isolated ground for internal PLLs on previous generation
processors. It may be left as a No-Connect on boards supporting the
processor.
VSS_SENSE
Output VSS_SENSE is an isolated low impedance connection to processor core V
.
SS
It can be used to sense or measure ground near the silicon with little noise.
VSS_MB_
REGULATION
Output This land is provided as a voltage regulator feedback sense point for V . It is
SS
connected internally in the processor package to the sense point land V27 as
described in the Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines For Desktop LGA775 Socket.
VTT
Miscellaneous voltage supply.
VTT_OUT_LEFT
Output The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a
voltage supply for some signals that require termination to V on the
TT
motherboard. Refer to the appropriate platform design guide for details on
implementation.
VTT_OUT_RIGHT
VTT_SEL
Output The VTT_SEL signal is used to select the correct V voltage level for the
TT
processor. This land is connected internally in the package to V
.
SS
§ §§
Datasheet
77
Land Listing and Signal Descriptions
78
Datasheet
Thermal Specifications and Design Considerations
5 Thermal Specifications and
Design Considerations
5.1
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
appropiate Thermal and Mechanical Design Guidelines (see Section 1.2).
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (TC)
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table 5-1. Thermal solutions not designed to provide this level of
thermal capability may affect the long-term reliability of the processor and system.
The processor uses a methodology for managing processor temperatures which is
intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 5.3. If the value reported via PECI is less than TCONTROL, then the case
temperature is permitted to exceed the Thermal Profile. If the value reported via PECI
is greater than or equal to TCONTROL, then the processor case temperature must remain
at or below the temperature as specified by the thermal profile. The temperature
reported over PECI is always a negative value and represents a delta below the onset of
thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2).
Systems that implement fan speed control must be designed to take these conditions in
to account. Systems that do not alter the fan speed only need to ensure the case
temperature meets the thermal profile specifications.
In order to determine a processor's case temperature specification based on the
thermal profile, it is necessary to accurately measure processor power dissipation. Intel
has developed a methodology for accurate power measurement that correlates to Intel
test temperature and voltage conditions. Refer to the Wolfdale Processors Thermal and
Mechanical Design Guidelines Addendum and the Live Die System Thermal Testing
Basics for the details of this methodology.
Datasheet
77
Thermal Specifications and Design Considerations
The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 5-1 instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. To ensure maximum flexibility for future
requirements, systems should be designed to the Flexible Motherboard (FMB)
guidelines, even if a processor with a lower thermal dissipation is currently planned. In
all cases the Thermal Monitor or Thermal Monitor 2 feature must be enabled
for the processor to remain within specification.
Table 5-1.
Processor Thermal Specifications
Thermal
Design
Power
Extended
HALT
Core
Frequency
(GHz)
Minimu
Processor
Number
Maximum T
(°C)
4
C
FMB Guidance
m T
Notes
C
Power
(°C)
2,3
1
(W)
(W)
See Table 5-2
and
Figure 5-1
E3110
E3120
L3110
3.00
3.16
3.00
65.0
65.0
45.0
8
8
6
775_VR_CONFIG_06A
(65 W)
775_VR_CONFIG_06
5
(45 W)
Notes:
1.
2.
3.
Specification is at 36°C Tc and minimum voltage loadline. Specification is guaranteed by design
characterization and not 100% tested.
Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not
the maximum power that the processor can dissipate.
This table shows the maximum TDP for a given frequency range. Individual processors may have a lower
TDP. Therefore, the maximum T will vary depending on the TDP of the individual processor. Refer to
C
thermal profile figure and associated table for the allowed combinations of power and T .
C
4.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting future thermal requirements.
78
Datasheet
Thermal Specifications and Design Considerations
Table 5-2.
Processor Thermal Profile (65 W)
Maximum Tc
Maximum Tc
(°C)
Power (W)
Power
(°C)
0
45.1
45.9
46.8
47.6
48.5
49.3
50.1
51.0
51.8
52.7
53.5
54.3
55.2
56.0
56.9
57.7
58.5
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
65
59.4
60.2
61.1
61.9
62.7
63.6
64.4
65.3
66.1
66.9
67.8
68.6
69.5
70.3
71.1
72.0
72.4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Table 5-3.
Processor Thermal Profile (45W)
Maximum Tc
Power (W)
(°C)
0
45.8
47.26
48.72
50.18
51.64
53.1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
54.56
56.02
57.48
58.94
60.4
61.86
63.32
64.78
66.24
67.7
69.16
70.62
72.08
Datasheet
79
Thermal Specifications and Design Considerations
38
40
42
44
45
73.54
75
76.46
77.92
78.65
Figure 5-1. Processor Thermal Profile (65 W)
72.0
68.0
64.0
60.0
56.0
52.0
48.0
44.0
y = 0.42x + 45.1
0
10
20
30
Power (W)
40
50
60
Figure 5-2. Processor Thermal Profile (45 W)
Thermal Profile
90
80
70
60
50
40
30
20
10
0
y = 0 .7 3 x + 4 5 .8
0
10
20
30
Power (W)
40
50
80
Datasheet
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (TC) for the processor is specified in
Table 5-1. This temperature specification is meant to help ensure proper operation of
the processor. Figure 5-3 illustrates where Intel recommends TC thermal
measurements should be made. For detailed guidelines on temperature measurement
methodology, refer to the appropiate Thermal and Mechanical Design Guidelines (see
Section 1.2).
Figure 5-3. Case Temperature (TC) Measurement Location
Measure TC at this point
(geometric center of the package)
37.5 mm
5.2
Processor Thermal Features
5.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30-50%). Clocks often will not
be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
Datasheet
81
Thermal Specifications and Design Considerations
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
and in some cases may result in a TC that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the Wolfdale Processors Thermal and
Mechanical Design Guidelines Addendum for information on designing a thermal
solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor
power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-FSB multiple utilized by the processor is that contained in the
CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2-3. These parameters
represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new
frequency. This transition occurs very rapidly (on the order of 5 µs). During the
frequency transition, the processor is unable to service any bus requests, and
consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and
kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes
to reach the target operating voltage. Each step will likely be one VID table entry (see
Table 2-3). The processor continues to execute instructions during the voltage
transition. Operation at the lower voltage reduces the power consumption of the
processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
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voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to ensure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 5-4 for an illustration of this ordering.
Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
fMAX
fTM2
Frequency
VID
VIDTM2
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on
demand mode. The Thermal Monitor TCC, however, can be activated through the use of
the on demand mode.
5.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor
IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5%
on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand
mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.
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Thermal Specifications and Design Considerations
5.2.4
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#.
PROCHOT# is a bi-directional signal. As an output, PROCHOT# (Processor Hot) will go
active when the processor temperature monitoring sensor detects that one or both
cores has reached its maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores.
The TCC will remain active until the system de-asserts PROCHOT#.
PROCHOT# allows for some protection of various components from over-temperature
situations. The PROCHOT# signal is bi-directional in that it can either signal when the
processor (either core) has reached its maximum operating temperature or be driven
from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained
current instead of maximum current. Systems should still provide proper cooling for the
VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling
failure. The system thermal design should allow the power delivery circuitry to operate
within its temperature specification even while the processor is operating at its Thermal
Design Power. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
of time when running the most power intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss. Refer to
the Voltage Regulator Design Guide for details on implementing the bi-directional
PROCHOT# feature.
5.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 4-3). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 4-3. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage
(VCC) must be removed within the timeframe defined in Table 2-9.
5.3
Platform Environment Control Interface (PECI)
5.3.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. PECI uses
CRC checking on the host side to ensure reliable transfers between the host and client
devices. Also, data transfer speeds across the PECI interface are negotiable within a
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wide range (2Kbps to 2Mbps). The PECI interface on the processor is disabled by
default and must be enabled through BIOS. More information can be found in the
Platform Environment Control Interface (PECI) Specification.
5.3.1.1
T
and TCC activation on PECI-Based Systems
CONTROL
Fan speed control solutions based on PECI utilize a TCONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the TCONTROL value as negative. Thermal management algorithms
should utilize the relative temperature value delivered over PECI in conjunction with the
TCONTROL MSR value to control or optimize fan speeds. Figure 5-5 shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
Figure 5-5. Conceptual Fan Control Diagram on PECI-Based Platforms
5.3.2
PECI Specifications
5.3.2.1
PECI Device Address
The PECI register resides at address 0x30.
5.3.2.2
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Please refer to this document for details on supported PECI
command function and codes.
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Thermal Specifications and Design Considerations
5.3.2.3
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not assured to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damage. It is recommended that the PECI host controller take appropriate
action to protect the client processor device if valid temperature readings have not
been obtained in response to three consecutive GetTemp()s or for a one second time
interval. The host controller may also implement an alert to software in the event of a
critical or continuous fault condition.
5.3.2.4
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
Table 5-4:
Table 5-4.
GetTemp0() Error Codes
Error Code
Description
0x8000
0x8002
General sensor error
Sensor is operational, but has detected a temperature below its operational range
(underflow)
§ §
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6 Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 6-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for configuration purposes, the processor does not distinguish between
a "warm" reset and a "power-on" reset.
Table 6-1.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Signal1,2
SMI#
Execute BIST
A3#
A25#
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
BR0#
A[24:4]#, A[35:26]#
Note:
1.
2.
3.
Asserting this signal during RESET# will select the corresponding option.
Address signals not identified in this table as configuration options should not be asserted during RESET#.
Disabling of any of the cores within the processors must be handled by configuring the EXT_CONFIG Model
Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 6-1 for a visual representation of the processor low
power states.
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Features
Figure 6-1. Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Extended HALT or HALT
State
- BCLK running
- Snoops and interrupts
allowed
Normal State
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
- Normal Execution
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service Snoops to caches
Extended Stop Grant
State or Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Extended Stop Grant
Snoop or Stop Grant
Snoop State
- BCLK running
- Service Snoops to caches
Snoop Event Occurs
Snoop Event Serviced
6.2.1
6.2.2
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT powerdown state must be configured and enabled via the BIOS for the processor
to remain within specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default powerdown state entered will be HALT.
Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The halted core will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT powerdown state. See the Intel Architecture Software
Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more
information.
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The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT powerdown state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT powerdown state must be enabled via the BIOS for the processor to remain
within its specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.3
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the BIOS Writer's Guide for Extended Stop Grant configuration information. Refer to
the sections below for details about the Stop Grant and Extended Stop Grant states.
6.2.3.1
Stop-Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
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Features
6.2.3.2
Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted
and Extended Stop Grant has been enabled via the BIOS.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended Stop Grant state. When entering the low power
state, the processor will first switch to the lower bus ratio and then transition to the
lower VID.
The processor exits the Extended Stop Grant state when a break event occurs. When
the processor exits the Extended Stop Grant state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.4
Extended HALT Snoop State, HALT Snoop State, Extended
Stop Grant Snoop State, and Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the Extended HALT state. If
Extended HALT state is not enabled in the BIOS, the default Snoop State entered will
be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State,
Stop Grant Snoop State, Extended HALT Snoop State, Extended Stop Grant Snoop
State.
6.2.4.1
6.2.4.2
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT powerdown state. During a snoop transaction, the processor enters the HALT
Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT powerdown state, as appropriate.
Extended HALT Snoop State, Extended Stop Grant Snoop State
The processor will remain in the lower bus ratio and VID operating point of the
Extended HALT state or Extended Stop Grant state.
While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops
are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After
the snoop is serviced the processor will return to the Extended HALT state or Extended
Stop Grant state.
®
6.2.5
Enhanced Intel SpeedStep Technology
The processor supports Enhanced Intel SpeedStep Technology. This technology enables
the processor to switch between frequency and voltage points, which may result in
platform power savings. In order to support this technology, the system must support
dynamic VID transitions. Switching between voltage/frequency states is software
controlled.
Enhanced Intel SpeedStep Technology is a technology that creates processor
performance states (P states). P states are power consumption and capability states
within the Normal state as shown in Figure 6-1. Enhanced Intel SpeedStep Technology
enables real-time dynamic switching between frequency and voltage points. It alters
the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to
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best serve the performance and power requirements of the processor and system. Note
that the front side bus is not altered; only the internal core frequency is changed. In
order to run at reduced power consumption, the voltage is altered in step with the bus
ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
• Voltage/Frequency selection is software controlled by writing to processor MSR's
(Model Specific Registers), thus eliminating chipset dependency.
- If the target frequency is higher than the current frequency, Vcc is incremented in
steps (+12.5 mV) by placing a new value on the VID signals after which the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
- If the target frequency is lower than the current frequency, the processor shifts to
the new frequency and Vcc is then decremented in steps (-12.5 mV) by changing
the target VID through the VID signals.
6.2.6
Processor Power Status Indicator (PSI) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve efficiency of the
voltage regulator, resulting in platform power savings. For details, refer to the
compatible chipset Platform Design Guide and Voltage Regulator-Down (VRD) 11.1
Processor Power Delivery Design Guidelines.
PSI# may be asserted only when the processor is in the Deeper Sleep state.
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Boxed Processor Specifications
7 Boxed Processor Specifications
7.1
Introduction
The processor will also be offered as an Intel boxed processor. Intel boxed processors
are intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators.
Note:
Note:
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed
processor.
Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the Wolfdale Processors Thermal and Mechanical Design
Guidelines Addendum for further guidance. Contact your local Intel Sales
Representative for this document.
Figure 7-1. Mechanical Representation of the Boxed Processor
Note: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
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Boxed Processor Specifications
7.2
Mechanical Specifications
7.2.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 7-2 (Side View), and Figure 7-3 (Top
View). The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 7-7 and Figure 7-8. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 7-2. Side View Space Requirements for the Boxed Processor
95.0
[3.74]
81.3
[3.2]
10.0
[0.39]
25.0
[0.98]
Boxed_Proc_SideView
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Figure 7-3. Top View Space Requirements for the Boxed Processor
95.0
[3.74]
95.0
[3.74]
Boxed_Proc_TopView
Notes:
1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical
representation.
Figure 7-4. Overall View Space Requirements for the Boxed Processor
7.2.2
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5
and the Wolfdale Processors Thermal and Mechanical Design Guidelines Addendum for
details on the processor weight and heatsink requirements.
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Boxed Processor Specifications
7.2.3
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
7.3
Electrical Requirements
7.3.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 7-5. Baseboards
must provide a matched power header to support the boxed processor. Table 7-1
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses
at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the
connector labeled as CONTROL.
The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 7-6 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned within 110 mm [4.33 inches] from the center of the
processor socket.
Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description
Signal
Pin
Straight square pin, 4-pin terminal housing with
polarizing ribs and friction locking ramp.
1
2
3
4
GND
+12 V
0.100" pitch, 0.025" square pin width.
SENSE
CONTROL
Match with straight pin, friction lock header on
mainboard.
3 4
1 2
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Table 7-1.
Fan Heatsink Power and Signal Specifications
Description
Min
Typ
Max
Unit
Notes
+12V: 12 volt fan power supply
11.4
12
12.6
V
-
IC:
- Maximum fan steady-state current draw
- Average fan steady-state current draw
- Maximum fan start-up current draw
—
—
—
—
1.2
0.5
2.2
1.0
—
—
—
—
A
A
A
-
- Fan start-up current draw maximum
duration
Second
pulses per
fan
1
SENSE: SENSE frequency
—
2
—
revolution
2, 3
CONTROL
21
25
28
kHz
Notes:
1. Baseboard should pull this pin up to 5V with a resistor.
2. Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
Boxed_Proc_PwrHeaderPlacement
7.4
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by
the boxed processor.
7.4.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
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Boxed Processor Specifications
temperature specification is found in Chapter 5 of this document. The boxed processor
fan heatsink is able to keep the processor temperature within the specifications (see
Table 5-1) in chassis that provide good thermal management. For the boxed processor
fan heatsink to operate properly, it is critical that the airflow provided to the fan
heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the
sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow
through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink
reduces the cooling efficiency and decreases fan life. Figure 7-7 and Figure 7-8
illustrate an acceptable airspace clearance for the fan heatsink. The air temperature
entering the fan should be kept below 38 ºC. Again, meeting the processor's
temperature specification is the responsibility of the system integrator.
Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
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Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)
7.4.2
Variable Speed Fan
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin
motherboard header it will operate as follows:
The boxed processor fan will operate at different speeds over a short range of internal
chassis temperatures. This allows the processor fan to operate at a lower speed and
noise level, while internal chassis temperatures are low. If internal chassis temperature
increases beyond a lower set point, the fan speed will rise linearly with the internal
temperature until the higher set point is reached. At that point, the fan speed is at its
maximum. As fan speed increases, so does fan noise levels. Systems should be
designed to provide adequate air around the boxed processor fan heatsink that remains
cooler then lower set point. These set points, represented in Figure 7-9 and Table 7-2,
can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis
temperature should be kept below 38 ºC. Meeting the processor's temperature
specification (see Chapter 5) is the responsibility of the system integrator.
The motherboard must supply a constant +12V to the processor's power header to
ensure proper operation of the variable speed fan for the boxed processor. Refer to
Table 7-1 for the specific requirements.
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Boxed Processor Specifications
Figure 7-9. Boxed Processor Fan Heatsink Set Points
Table 7-2.
Fan Heatsink Power and Signal Specifications
Boxed Processor Fan
Heatsink Set Point (ºC)
Boxed Processor Fan Speed
Notes
1
When the internal chassis temperature is below or equal to this set
point, the fan operates at its lowest speed. Recommended maximum
internal chassis temperature for nominal operating environment.
X ≤ 30
When the internal chassis temperature is at this point, the fan operates
between its lowest and highest speeds. Recommended maximum
internal chassis temperature for worst-case operating environment.
-
-
Y = 35
Z ≥ 38
When the internal chassis temperature is above or equal to this set
point, the fan operates at its highest speed.
Notes:
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin
motherboard header and the motherboard is designed with a fan speed controller with
PWM output (CONTROL see Table 7-1) and remote thermal diode measurement
capability the boxed processor will operate as follows:
As processor power has increased the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.
The 4th wire PWM solution provides better control over chassis acoustics. This is
achieved by more accurate measurement of processor die temperature through the
processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the
use of an ASIC located on the motherboard that sends out a PWM control signal to the
4th pin of the connector labeled as CONTROL. The fan speed is based on actual
processor temperature instead of internal ambient chassis temperatures.
100
Datasheet
Boxed Processor Specifications
If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard
CPU fan header it will default back to a thermistor controlled mode, allowing
compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode,
the fan RPM is automatically varied based on the Tinlet temperature measured by a
thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed
control see the Wolfdale Processors Thermal and Mechanical Design Guidelines
Addendum.
§
Datasheet
101
Boxed Processor Specifications
102
Datasheet
Debug Tools Specifications
8 Debug Tools Specifications
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging the processor systems. Tektronix and Agilent should be
contacted to get specific information about their logic analyzer interfaces. The following
information is general in nature. Specific information must be obtained from the logic
analyzer vendor.
Due to the complexity of Dual-Core Intel® Xeon® Processor 3100 Series systems, the
LAI is critical in providing the ability to probe and capture FSB signals. There are two
sets of considerations to keep in mind when designing a Dual-Core Intel® Xeon®
Processor 3100 Series system that can make use of an LAI: mechanical and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processors. The LAI lands
plug into the processor socket, while the processors lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection
between the processors and a logic analyzer. The maximum volume occupied by the
LAI, known as the keepout volume, as well as the cable egress restrictions, should be
obtained from the logic analyzer vendor. System designers must make sure that the
keepout volume remains unobstructed inside the system. Note that it is possible that
the keepout volume reserved for the LAI may differ from the space normally occupied
by the processor heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic
analyzer vendor for electrical specifications and load models for the LAI solution it
provides.
Datasheet
103
Debug Tools Specifications
104
Datasheet
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