AW80581GH0416M_技术文档

Intel® Core™2 Extreme Quad-Core

Mobile Processor and Intel® Core™2

Quad Mobile Processor on 45-nm

Process

Datasheet

For platforms based on Mobile Intel® 4 Series Express Chipset

Family

January 2009

Document Number: 320390-002

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conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with

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The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications

enabled for IntelÆ 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for

more information.

Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http://

processorfinder.intel.com or contact your Intel representative for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check

with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Φ

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some

uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations

and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Intel, Pentium, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction..............................................................................................................7

1.1

1.2

Terminology .......................................................................................................7

References .........................................................................................................9

2

Low Power Features................................................................................................ 11

2.1

Clock Control and Low Power States .................................................................... 11

2.1.1 Core Low Power State Descriptions........................................................... 13

2.1.1.1 Core C0 State........................................................................... 13

2.1.1.2 Core C1/AutoHALT Powerdown State........................................... 13

2.1.1.3 Core C1/MWAIT Powerdown State............................................... 14

2.1.1.4 Core C2 State........................................................................... 14

2.1.1.5 Core C3 State........................................................................... 14

2.1.1.6 Core C4 State........................................................................... 14

2.1.2 Package Low Power State Descriptions...................................................... 14

2.1.2.1 Normal State............................................................................ 14

2.1.2.2 Stop-Grant State ...................................................................... 15

2.1.2.3 Stop-Grant Snoop State............................................................. 15

2.1.2.4 Sleep State.............................................................................. 15

2.1.2.5 Deep Sleep State...................................................................... 16

2.1.2.6 Deeper Sleep State................................................................... 16

Enhanced Intel SpeedStep® Technology .............................................................. 17

Extended Low Power States................................................................................ 17

FSB Low Power Enhancements............................................................................ 18

2.4.1 Dual Intel Dynamic Acceleration............................................................... 19

Processor Power Status Indicator (PSI-2) Signal.................................................... 19

2.2

2.3

2.4

2.5

3

Electrical Specifications........................................................................................... 21

3.1

3.2

Power and Ground Pins ...................................................................................... 21

Decoupling Guidelines........................................................................................ 21

3.2.1 VCC Decoupling...................................................................................... 21

3.2.2 FSB AGTL+ Decoupling ........................................................................... 21

3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 21

Voltage Identification and Power Sequencing ........................................................ 22

Catastrophic Thermal Protection.......................................................................... 26

Reserved and Unused Pins.................................................................................. 26

FSB Frequency Select Signals (BSEL[2:0])............................................................ 27

FSB Signal Groups............................................................................................. 27

CMOS Signals ................................................................................................... 29

Maximum Ratings.............................................................................................. 29

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10 Processor DC Specifications ................................................................................ 30

4

5

Package Mechanical Specifications and Pin Information.......................................... 37

4.1

4.2

Package Mechanical Specifications....................................................................... 37

Processor Pinout and Pin List .............................................................................. 40

Thermal Specifications and Design Considerations .................................................. 67

5.1

Monitoring Die Temperature ............................................................................... 68

5.1.1 Thermal Diode ....................................................................................... 68

5.1.2 Intel® Thermal Monitor........................................................................... 69

5.1.3 Digital Thermal Sensor............................................................................ 71

PROCHOT# Signal Pin........................................................................................ 72

5.2

Datasheet

3

Figures

1

2

3

4

5

6

7

8

9

Core Low Power States..............................................................................................12

Package Low Power States.........................................................................................13

PSI-2 Functionality Logic Diagram ..............................................................................19

Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor.............................33

Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor...................34

Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2) ................................38

Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2) ................................39

Quad-Core Processor Pinout (Top Package View, Left Side) ............................................40

Quad-Core Processor Pinout (Top Package View, Right Side) ..........................................41

Tables

1

2

3

4

5

6

7

8

9

References ............................................................................................................... 9

Coordination of Core Low Power States at the Package Level..........................................13

Voltage Identification Definition..................................................................................23

BSEL[2:0] Encoding for BCLK Frequency......................................................................27

FSB Pin Groups ........................................................................................................28

Processor Absolute Maximum Ratings..........................................................................29

Voltage and Current Specifications for the Quad-Core Extreme Mobile Processors..............30

Voltage and Current Specifications for the Quad-Core Mobile Processors ..........................31

AGTL+ Signal Group DC Specifications ........................................................................34

10 CMOS Signal Group DC Specifications..........................................................................36

11 Open Drain Signal Group DC Specifications ..................................................................36

12 Pin Listing by Pin Name.............................................................................................42

13 Pin Listing by Pin Number..........................................................................................49

14 Signal Description.....................................................................................................57

15 New Pins for the Quad-Core Mobile Processor...............................................................66

16 Processor Power Specifications...................................................................................67

17 Thermal Diode Interface............................................................................................69

18 Thermal Diode Parameters Using Transistor Model ........................................................69

4

Datasheet

Revision History

Document

Number

Revision

Number

Description

Date

August 2008

January 2009

320390

Initial Release

-001

-002

•

Updated Table 8: Added Q9000 information

Updated Table 16: Added Q9000 information

§

Datasheet

5

6

Datasheet

Introduction

1 Introduction

The Intel® Core^TM2 Extreme quad-core processor and Intel® Core^TM2 quad processor

on 45-nanometer process technology for platforms based on Mobile Intel® 4 Series

Express Chipset Family is the first low-power, mobile quad-core processor based on the

Intel® Core™ microarchitecture.

In this document, the Intel Core 2 Extreme quad-core processor and Intel Core 2 quad

processor are referred to as the processor or quad-core processor and the Mobile Intel

4 Series Express Chipset is referred to as the (G)MCH.

Key features of the processor include:

• Quad-core mobile processor for mobile with enhanced performance

• Supports Intel® architecture with Intel® Wide Dynamic Execution

• Supports L1 cache-to-cache (C2C) transfer

• On-die, primary 32-kB instruction cache and 32-kB write-back data cache in each

core

• 12-MB second-level shared cache with Advanced Transfer Cache architecture

• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3),

supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets

• Processors are offered at 1066-MHz source-synchronous front side bus (FSB)

• Advanced power management features including Enhanced Intel SpeedStep®

Technology

• Digital thermal sensor (DTS)

• Intel® 64 architecture

• Supports Enhanced Intel® Virtualization Technology

• Supports PSI2 functionality

• Execute Disable Bit support for enhanced security

• Half ratio support (N/2) for core to bus ratio

1.1

Terminology

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

#

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

AGTL+

Datasheet

7

Introduction

Term

Definition

Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor landings should not

be connected to any supply voltages, have any I/Os biased or receive any

clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device

removed from packaging material) the processor must be handled in

accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Storage

Conditions

Enhanced Intel

SpeedStep®

Technology

Technology that provides power management capabilities to laptops.

Processor core die with integrated L1 and L2 cache. All AC timing and signal

integrity specifications are at the pads of the processor core.

Processor Core

The Execute Disable bit allows memory to be marked as executable or non-

executable, when combined with a supporting operating system. If code

attempts to run in non-executable memory the processor raises an error to

the operating system. This feature can prevent some classes of viruses or

worms that exploit buffer overrun vulnerabilities and can thus help improve

the overall security of the system. See the Intel® 64 and IA-32

Execute Disable

Bit

Architectures Software Developer's Manuals for more detailed information.

Intel® 64

Technology

64-bit memory extensions to the IA-32 architecture.

Intel®

Virtualization

Technology

Processor virtualization which when used in conjunction with Virtual

Machine Monitor software enables multiple, robust independent software

environments inside a single platform.

Quad-core processor supports the N/2 feature which allows having

fractional core to bus ratios. This feature provides the flexibility of having

more frequency options and be able to have products with smaller

frequency steps.

Half ratio support

(N/2) for Core to

Bus ratio

TDP

V_CC

V_SS

Thermal Design Power

The processor core power supply

The processor ground

8

Datasheet

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document.

Table 1.

References

Document

Number¹

Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2

Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor, Intel®

Core™2 Duo Mobile Processor, and Intel® Core™2 Solo Mobile

320121

Processors on 45-nm Process Specification Update

Mobile Intel® 4 Series Express Chipset Family Datasheet

320122

320123

Mobile Intel® 4 Series Express Chipset Family Specification Update

Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)

Datasheet

316972

316973

Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)

Specification Update

See http://

www.intel.com/

products/processor/

manuals/index.htm

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

NOTES:Contact your Intel representative for the latest revision and document number of this

document.

§

Datasheet

9

Introduction

10

Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low Power States

The processor supports low power states both at the individual core level and the

package level for optimal power management.

A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low

power states. When all cores coincide in a common core low power state, the central

power management logic ensures the entire processor enters the respective package

low power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4) I/O read to the

(G)MCH.

The processor implements two software interfaces for requesting low power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK

register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are

converted to equivalent MWAIT C-state requests inside the processor and do not

directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does

not need to be set up before using the P_LVLx I/O read interface. The sub-state hints

used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model

specific register (MSR).

If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the

PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system

logic that individual cores should return to the C0 state and the processor should return

to the Normal state.

Figure 1 shows the core low power states and Figure 2 shows the package low power

states for the processor. Table 2 maps the core low power states to package low power

states.

Datasheet

11

Low Power Features

Figure 1.

Core Low Power States

Stop

Grant

STPCLK#

asserted

deasserted

STPCLK#

asserted

STPCLK#

deasserted

STTPPCCLKL#K#

deeaasssesreterdte

C1/Auto

Halt

STPCLK#

asserted

Core State

Break

C1/MWAIT

HLT instruction

Halt break

MWAIT(C1)

C0

P_LVL2 or

MWAIT(C2)

Core State

Break

Core State

Break

P_LVL4 or

MWAIT(C4)

Core State

Break

+

C2

+

P_LVL3 or

MWAIT(C3)

C4

+

C3

Halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

+ __ STPCLK# assertion and de-assertion have no effect if a core is in C2, C3 or C4.

12

Datasheet

Low Power Features

Figure 2.

Package Low Power States

STPCLK# asserted

SLP# asserted

DPSLP# asserted

DPRSTP# asserted

DPRSTP# desserted

Stop

Grant

Deep

Sleep

Deeper

Sleep

Normal

SLP# desserted

STPCLK# desserted

DPSLP# deasserted

Snoop

serviced

Snoop

occurs

Stop Grant

Snoop

Table 2.

Coordination of Core Low Power States at the Package Level

Package State

Core0 State

Core1 State

C2

C0

C1¹

C3

C4

C0

C1¹

C2

Normal

Stop-Grant

Deep Sleep

Stop-Grant

Deep Sleep

Deeper Sleep

C3

C4

NOTE:

1.

AutoHALT or MWAIT/C1.

2.1.1

Core Low Power State Descriptions

2.1.1.1

Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2

Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when a core executes the HALT instruction.

The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,

LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to

immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more

information.

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

Datasheet

13

Low Power Features

While in AutoHALT Powerdown state, the due core processor will process bus snoops

and snoops from the other core. The processor core will enter a snoopable sub-state

(not shown in Figure 1) to process the snoop and then return to the AutoHALT

Powerdown state.

2.1.1.3

2.1.1.4

Core C1/MWAIT Powerdown State

C1/MWAIT is a low power state entered when the processor core executes the

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the

AutoHALT state except that Monitor events can cause the processor core to return to

the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,

N-Z, for more information.

Core C2 State

Individual cores of the quad-core processor can enter the C2 state by initiating a

P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not

issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also

asserted.

While in the C2 state, the quad-core processor will process bus snoops and snoops

from the other core. The processor core will enter a snoopable sub-state (not shown in

Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5

Core C3 State

Individual cores of the quad-core processor can enter the C3 state by initiating a

P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the

processor core flushes the contents of its L1 caches into the processor’s L2 cache.

Except for the caches, the processor core maintains all its architectural states in the C3

state. The Monitor remains armed if it is configured. All of the clocks in the processor

core are stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB or when the other core of the dual-core

die of quad-core processor accesses cacheable memory. The processor core will

transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0]

(NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to

immediately initialize itself.

2.1.1.6

Core C4 State

Individual cores of the quad-core processor can enter the C4 state by initiating a

P_LVL4 or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor

core behavior in the C4 state is nearly identical to the behavior in the C3 state. The

only difference is that if all processor cores are in C4, the central power management

logic will request that the entire processor enter the Deeper Sleep package low power

state (see Section 2.1.2.6).

2.1.2

Package Low Power State Descriptions

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor remains in the

Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT

state.

14

Datasheet

Low Power Features

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, each core of the quad-core processor enters the

Stop-Grant state within 20 bus clocks after the response phase of the processor-issued

Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,

C3, or C4 state remain in their current low power state. When the STPCLK# pin is

deasserted, each core returns to its previous core low power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor will stay

in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,

DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC

Specification T45. When re-entering the Stop-Grant state from the Sleep state,

STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification

T75.

While in Stop-Grant state, the processor will service snoops and latch interrupts

delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts

and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be

asserted if there is any pending interrupt or Monitor event latched within the processor.

Pending interrupts that are blocked by the EFLAGS. IF bit being clear will still cause

assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor

should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop

on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)

occurs with the assertion of the SLP# signal.

2.1.2.3

2.1.2.4

Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this

state until the snoop on the FSB has been serviced (whether by the processor or

another agent on the FSB) or the interrupt has been latched. The processor returns to

the Stop-Grant state once the snoop has been serviced or the interrupt has been

latched.

Sleep State

The Sleep state is a low power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#

pin should only be asserted when the processor is in the Stop-Grant state. SLP#

assertions while the processor is not in the Stop-Grant state is out of specification and

may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before

the processor has returned to the Stop-Grant state will result in unpredictable behavior.

Datasheet

15

Low Power Features

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor will reset itself, ignoring

the transition through the Stop-Grant state. If RESET# is driven active while the

processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted

immediately after RESET# is asserted to ensure the processor correctly executes the

Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While

the processor is in the Sleep state, the SLP# pin must be deasserted if another

asynchronous FSB event needs to occur.

2.1.2.5

Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep

state. BCLK may be stopped during the Deep Sleep state for additional platform-level

power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs

of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to

allow for PLL stabilization) must occur before the processor can be considered to be in

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep

state, it will not respond to interrupts or snoop transactions. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable

behavior.

2.1.2.6

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core

voltage levels. One of the potential lower core voltage levels is achieved by entering the

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state.

In response to entering Deeper Sleep, the processor drives the VID code corresponding

to the Deeper Sleep core voltage on the VID[6:0] pins.

Exit from Deeper Sleep state is initiated by DPRSTP# deassertion when either core

requests a core state other than C4 or either core requests a processor performance

state other than the lowest operating point.

16

Datasheet

Low Power Features

2.2

Enhanced Intel SpeedStep® Technology

The processor features Enhanced Intel SpeedStep Technology. Following are the key

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the

lowest power.

• Voltage and frequency selection is software-controlled by writing to processor

MSRs:

— If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins, and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch-free

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 ms during the

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high

the processor can automatically perform a transition to a lower frequency and

voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up-transition to the previous frequency and voltage point

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions

enabling better system-level thermal management.

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection.

— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in

case of unsuccessful TM2 transition.

— Quad core thermal management synchronization.

Each core in the quad-core processor implements an independent MSR for controlling

Enhanced Intel SpeedStep Technology, but all cores must operate at the same voltage.

The processor has performance state coordination logic to resolve frequency and

voltage requests from the four cores into a single voltage request for the package as a

whole. If all cores request the same frequency and voltage, then the processor will

transition to the requested common frequency and voltage.

2.3

Extended Low Power States

Extended low power states (CXE) optimize for power by forcibly reducing the

performance state of the processor when it enters a package low power state. Instead

of directly transitioning into the package low power low power state, the enhanced

package low power state first reduces the performance state of the processor by

performing an Enhanced Intel SpeedStep Technology transition down to the lowest

Datasheet

17

Low Power Features

operating point. Upon receiving a break event from the package low power state,

control will be returned to software while an Enhanced Intel SpeedStep Technology

transition up to the initial operating point occurs. The advantage of this feature is that it

significantly reduces leakage while in the Stop-Grant and Deeper Sleep states.

Note:

Long-term reliability cannot be assured unless all the Extended Low Power States are

enabled.

The processor implements two software interfaces for requesting enhanced package

low power states: MWAIT instruction extensions with sub-state hints and via BIOS by

configuring IA32_MISC_ENABLES MSR bits to automatically promote package low

power states to enhanced package low power states.

Caution:

Extended Stop-Grant must be enabled via the BIOS for the processor to

remain within specification. As processor technology changes, enabling the

extended low power states becomes increasingly crucial when building computer

systems. Maintaining the proper BIOS configuration is key to reliable, long-term

system operation. Not complying to this guideline may affect the long-term reliability of

the processor.

Enhanced Intel SpeedStep Technology transitions are multistep processes

that require clocked control. These transitions cannot occur when the processor is in

the Sleep or Deep Sleep package low power states since processor clocks are not active

in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E

configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep

state configuration will lower core voltage to the Deeper Sleep level while in Deeper

Sleep and, upon exit, will automatically transition to the lowest operating voltage and

frequency to reduce snoop service latency. The transition to the lowest operating point

or back to the original software-requested point may not be instantaneous.

Furthermore, upon very frequent transitions between active and idle states, the

transitions may lag behind the idle state entry resulting in the processor either

executing for a longer time at the lowest operating point or running idle at a high

operating point. Observations and analyses show this behavior should not significantly

impact total power savings or performance score while providing power benefits in

most other cases.

2.4

FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On-Die Termination disabling

• Low V_CCP(I/O termination voltage)

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control input

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows

a reciprocal power reduction in GMCH address and control input buffers when the

processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers

is disabled when the signals are driven low, resulting in additional power savings. The

low I/O termination voltage is on a dedicated voltage plane independent of the core

voltage, enabling low I/O switching power at all times.

18

Datasheet

Low Power Features

2.4.1

Dual Intel Dynamic Acceleration

The processor supports Dual Intel Dynamic Acceleration. For any two cores in the

quad-core processor, the Dual Intel Dynamic Acceleration feature allows one core to

operate at a higher frequency point while the other core is inactive and the operating

system requests increased performance. Thus, quad-core processor could enter Dual

Intel Dynamic Acceleration when two cores are idle and the other two are active. This

higher frequency is called the opportunistic frequency and the maximum rated

operating frequency is the ensured frequency.

Dual Intel Dynamic Acceleration enabling requires exposure, via BIOS, of the

opportunistic frequency as the highest ACPI P state

2.5

Processor Power Status Indicator (PSI-2) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a

reduced power consumption state. PSI# can be used to improve intermediate and light

load efficiency of the voltage regulator, resulting in platform power savings and

extended battery life. The algorithm that the processor uses for determining when to

assert PSI# is different from the algorithm used in previous mobile processors.

PSI-2 functionality improves overall voltage regulator efficiency over a wide power

range based on the C-state and P-state of the four cores. The combined C-state of all

cores are used to dynamically predict processor power. The PSI-2 functionality logic

diagram is shown in Figure 3.

Figure 3.

PSI-2 Functionality Logic Diagram

§

Datasheet

19

Low Power Features

20

Datasheet

Electrical Specifications

3 Electrical Specifications

3.1

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of V_CC

(power) and V_SS(ground) inputs. All power pins must be connected to V_CCpower

planes while all V_SSpins must be connected to system ground planes. Use of multiple

power and ground planes is recommended to reduce I*R drop. Refer to the platform

design guides for more details. The processor V_CCpins must be supplied the voltage

determined by the VID (Voltage ID) pins.

3.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large average current swings between low and full power states.

This may cause voltages on power planes to sag below their minimum values if bulk

decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply

current during longer lasting changes in current demand by the component, such as

coming out of an idle condition. Similarly, they act as a storage well for current when

entering an idle condition from a running condition. Care must be taken in the board

design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 3. Failure to do so may result in timing violations or

reduced lifetime of the component.

3.2.1

V Decoupling

CC

V_CCregulator solutions need to provide bulk capacitance with a low Effective Series

Resistance (ESR) and keep a low interconnect resistance from the regulator to the

socket. Bulk decoupling for the large current swings when the part is powering on, or

entering/exiting low-power states, should be provided by the voltage regulator solution

depending on the specific system design.

3.2.2

3.2.3

FSB AGTL+ Decoupling

The processors integrate signal termination on the die as well as incorporate high

frequency decoupling capacitance on the processor package. Decoupling must also be

provided by the system motherboard for proper AGTL+ bus operation.

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous-generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio at manufacturing.The processor uses a differential clocking

implementation.

Datasheet

21

Electrical Specifications

3.3

Voltage Identification and Power Sequencing

The processor uses seven voltage identification pins,VID[6:0], to support automatic

selection of power supply voltages. The VID pins for the processor are CMOS outputs

driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding

to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to

a low-voltage level.

22

Datasheet

Electrical Specifications

Table 3.

Voltage Identification Definition (Sheet 1 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

Datasheet

23

Electrical Specifications

Table 3.

Voltage Identification Definition (Sheet 2 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

24

Datasheet

Electrical Specifications

Table 3.

Voltage Identification Definition (Sheet 3 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

Datasheet

25

Electrical Specifications

Table 3.

Voltage Identification Definition (Sheet 4 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

0.0000

3.4

3.5

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An

external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, which halts

all processor internal clocks and activity, leakage current can be high enough that the

processor cannot be protected in all conditions without the removal of power to the

processor. If the external thermal sensor detects a catastrophic processor temperature

of 125°C (maximum), or if the THERMTRIP# signal is asserted, the V_CCsupply to the

processor must be turned off within 500 ms to prevent permanent silicon damage due

to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the

PWRGOOD signal is not asserted.

Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC

,

V_SS, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4.2 for a pin listing of the

processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no-connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected. The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for

test purposes internally and can be left as “No Connects”.

26

Datasheet

Electrical Specifications

3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 4.

Table 4.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1] BSEL[0]

BCLK Frequency

L

H

L

266 MHz

RESERVED

L

H

L

H

L

H

L

3.7

FSB Signal Groups

The FSB signals have been combined into groups by buffer type in the following

sections. AGTL+ input signals have differential input buffers that use GTLREF as a

reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input

group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers

to the AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source-synchronous data bus, two sets of timing

parameters need to be specified. One set is for common clock signals, which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second

set is for the source-synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 5 identifies which signals are common clock, source synchronous,

and asynchronous.

Datasheet

27

Electrical Specifications

Table 5.

FSB Pin Groups

Signal Group

Type

Signals¹

AGTL+ Common Clock

Input

Synchronous

to BCLK[1:0]

BPRI#, DEFER#, PREQ#⁵, RESET#, RS[2:0]#,

TRDY#

ADS#, BNR#, BPM[3:0]#³, BPM_2[3:0]#³, BR0#,

BR1#, DBSY#, DRDY#, HIT#, HITM#, LOCK#,

PRDY#³, DPWR#

Synchronous

to BCLK[1:0]

AGTL+ Common Clock I/O

Signals

Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[35:17]#

ADSTB[1]#

Synchronous

to assoc.

strobe

AGTL+ Source

Synchronous I/O

D[15:0]#, DINV0#

D[31:16]#, DINV1#

D[47:32]#, DINV2#

D[63:48]#, DINV3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous

to BCLK[1:0]

AGTL+ Strobes

CMOS Input

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#,

Asynchronous LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#,

STPCLK#

Open Drain Output

Open Drain I/O

CMOS Output

Asynchronous FERR#, IERR#, THERMTRIP#

Asynchronous PROCHOT#⁴

Asynchronous PSI#, VID[6:0], BSEL[2:0]

Synchronous

CMOS Input

TCK, TDI, TDI_M, TMS, TRST#

to TCK

Synchronous

TDO, TDO_M

to TCK

Open Drain Output

FSB Clock

Clock

BCLK[1:0]

COMP[3:0], DBR#2, GTLREF, GTLREF_2, RSVD,

TEST2, TEST1, THERMDA, THERMDA_2,

THERMDC, THERMDC_2, VCC, VCCA, VCCP,

Power/Other

V

_{CC_SENSE}, V_SS, V_{SS_SENSE}

NOTES:

1.

2.

Refer to Chapter 4 for signal descriptions and termination requirements.

In processor systems where there is no debug port implemented on the system board,

these signals are used to support a debug port interposer. In systems with the debug port

implemented on the system board, these signals are no connects.

BPM[2:1]#,BPM_2[1]# and PRDY# are AGTL+ output-only signals.

PROCHOT# signal type is open drain output and CMOS input.

3.

4.

5.

On-die termination differs from other AGTL+ signals.

28

Datasheet

Electrical Specifications

3.8

3.9

CMOS Signals

CMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for more than four BCLKs for the

processor to recognize them. See Section 3.10 for DC specifications for the CMOS

signal groups.

Maximum Ratings

Table 6 specifies absolute maximum and minimum ratings only and these lie outside

the functional limits of the processor. Only within functional operation limits,

functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded.

At conditions exceeding the absolute maximum and minimum ratings, neither

functionality nor long-term reliability can be expected. Moreover, if a device is

subjected to these conditions for any length of time then, when returned to conditions

within the functional operating condition limits, it will either not function or its reliability

will be severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 6.

Processor Absolute Maximum Ratings

Symbol

T_STORAGE

Parameter

Min

Max

Unit Notes^1,5

Processor Storage Temperature

-40

85

°C

V

2,3,4

Any Processor Supply Voltage with Respect

to V_SS

V_CC

-0.3

-0.1

1.45

AGTL+ Buffer DC Input Voltage with

Respect to V_SS

V_inAGTL+

V_{inAsynch_CMOS}

NOTES:

V

CMOS Buffer DC Input Voltage with Respect

to V_SS

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal

specifications must be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias.

Storage within these limits will not affect the long-term reliability of the device. For

functional operation, please refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long-term reliability of the processor.

3.

4.

Datasheet

29

Electrical Specifications

3.10

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise. See Table 5 for the pin signal definitions and

signal pin assignments.

The table below lists the DC specifications for the processor and are valid only while

meeting specifications for junction temperature, clock frequency, and input voltages.

The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the

highest and lowest core operating frequencies supported on the processor. Active mode

load line specifications apply in all states except in the Deep Sleep and Deeper Sleep

states. V_CC,BOOTis the default voltage driven by the voltage regulator at power up in

order to set the VID values. Unless specified otherwise, all specifications for the

processor are at T_J= 100°C. Read all notes associated with each parameter.

Table 7.

Voltage and Current Specifications for the Quad-Core Extreme Mobile

Processors (Sheet 1 of 2)

Symbol

V_CCDAM

Parameter

Min

Typ

Max

Unit

Notes

V_CCin Intel Dynamic Acceleration

Technology Mode

0.90

—

1.30

V

1, 2

V_CCHFM

V_CCLFM

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

0.90

0.85

—

1.25

1.10

V

1, 2

Default V_CCVoltage for Initial Power

Up

V_CC,BOOT

—

1.20

V

2, 5, 6

V_CCP

AGTL+ Termination Voltage

PLL Supply Voltage

1.00

1.425

0.65

1.05

1.5

—

1.10

1.575

0.85

V

V_CCA

V_CCDPRSLP

V_CCat Deeper Sleep

1, 2

I_CCfor Processors Recommended

Design Target

I_CCDES

—

64

—

A

5, 10

I_CCfor Processors

Processor

Core Frequency/Voltage

Number

I_CC

QX9300

2.53 GHz & V_CCHFM

1.60 GHz & V_CCLFM

64

47

—

A

3, 4

I_CCAuto-Halt & Stop-Grant

HFM

LFM

I_AH,

I_SGNT

32.4

30.0

I_CCSleep

HFM

LFM

I_SLP

—

31.8

29.7

A

3, 4

I_CCDeep Sleep

I_DSLP

HFM

LFM

—

30.1

28.8

A

3, 4

I_DPRSLP

I_CCDeeper Sleep

20.5

30

Datasheet

Electrical Specifications

Table 7.

Voltage and Current Specifications for the Quad-Core Extreme Mobile

Processors (Sheet 2 of 2)

Symbol

dI_CC/DT

I_CCA

I_CCP

Parameter

Min

Typ

Max

Unit

Notes

V_CCPower Supply Current Slew Rate

at Processor Package Pin

—

600

130

A/µs

mA

5, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

8, 9

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID),

which is set at manufacturing and cannot be altered. Individual maximum VID values are

calibrated during manufacturing such that two processors at the same frequency may have

different settings within the VID range. Note that this differs from the VID employed by

the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel

SpeedStep Technology, or Enhanced Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}

pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe

capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the

probe should be less than 5 mm. Ensure external noise from the system is not coupled in

the scope probe.

3.

4.

5.

6.

7.

Specified at 100°C T_J.

Specified at the nominal V_CC

Measured at the bulk capacitors on the motherboard.

_CC,BOOTtolerance shown in Figure 4 and Figure 5.

.

V

Based on simulations and averaged over the duration of any change in current. Specified

by design/characterization at nominal V_CC. Not 100% tested.

8.

This is a power-up peak current specification, which is applicable when V_CCPis high and

V

_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand

_{CC_CORE}are high.

9.

V

10.

Instantaneous current I_{CC_CORE_INST}of 85 A has to be sustained for short time (t_INST) of

35µs. Average current will be less than maximum specified I_CCDES. VR OCP threshold

should be high enough to support current levels described herein.

Table 8.

Voltage and Current Specifications for the Quad-Core Mobile Processors

(Sheet 1 of 2)

Symbol

V_CCDAM

Parameter

Min

Typ

Max

Unit

Notes

V_CCin Intel Dynamic Acceleration

Technology Mode

0.90

—

1.30

V

1, 2

V_CCHFM

V_CCLFM

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

0.90

0.85

—

1.25

1.10

V

1, 2

Default V_CCVoltage for Initial Power

Up

V_CC,BOOT

—

1.20

V

2, 5, 6

V_CCP

AGTL+ Termination Voltage

PLL Supply Voltage

1.00

1.425

0.65

1.05

1.5

—

1.10

1.575

0.85

V

V_CCA

V_CCDPRSLP

V_CCat Deeper Sleep

1, 2

I_CCfor Processors Recommended

Design Target

I_CCDES

—

64

A

5, 10

Datasheet

31

Electrical Specifications

Table 8.

Voltage and Current Specifications for the Quad-Core Mobile Processors

(Sheet 2 of 2)

Symbol

Parameter

I_CCfor Processors

Min

Typ

Max

Unit

Notes

—

Processor

Number

Core Frequency/Voltage

—

I_CC

Q9100

2.26 GHz & V_CCHFM

1.60 GHz & V_CCLFM

64

47

A

3, 4

Q9000

2.0 GHz & V_CCHFM

1.60 GHz & V_CCLFM

64

47

I_CCAuto-Halt & Stop-Grant

HFM

LFM

I_AH,

I_SGNT

—

32.4

30.0

A

3, 4

I_CCSleep

HFM

LFM

I_SLP

31.8

29.7

I_CCDeep Sleep

HFM

LFM

I_DSLP

30.1

28.8

I_DPRSLP

dI_CC/DT

I_CCA

I_CCDeeper Sleep

—

20.5

600

130

A

3, 4

5, 7

V_CCPower Supply Current Slew Rate

at Processor Package Pin

A/µs

mA

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

4.5

2.5

A

I_CCP

8,9

I

_CCfor V_CCPSupply after V_CCStable

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID),

which is set at manufacturing and cannot be altered. Individual maximum VID values are

calibrated during manufacturing such that two processors at the same frequency may have

different settings within the VID range. Note that this differs from the VID employed by

the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel

SpeedStep Technology, or Enhanced Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}

pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe

capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the

probe should be less than 5 mm. Ensure external noise from the system is not coupled in

the scope probe.

3.

4.

5.

6.

7.

Specified at 100°C T_J.

Specified at the nominal V_CC

Measured at the bulk capacitors on the motherboard.

_CC,BOOTtolerance shown in Figure 4 and Figure 5.

.

V

Based on simulations and averaged over the duration of any change in current. Specified

by design/characterization at nominal V_CC. Not 100% tested.

8.

This is a power-up peak current specification, which is applicable when V_CCPis high and

V

_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand

_{CC_CORE}are high.

9.

V

10.

Instantaneous current I_{CC_CORE_INST}of 85 A has to be sustained for short time (t_INST) of

35µs. Average current will be less than maximum specified I_CCDES. VR OCP threshold

should be high enough to support current levels described herein.

32

Datasheet

Electrical Specifications

Figure 4.

Active V_CCand I_CCLoadline for Quad-Core Extreme Mobile Processor

V_CC-CORE[V]

Slope = -2.1 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V_CC-COREmax {HFM|LFM}

V_{CC-CORE, DC}max {HFM|LFM}

10mV= RIPPLE

V_CC-COREnom {HFM|LFM}

V_{CC-CORE, DC}min {HFM|LFM}

V_CC-COREmin {HFM|LFM}

+/-V_CC-CORETolerance

= VR St. Pt. Error 1/

I_CC-CORE

[A]

0

I_CC-COREmax

{HFM|LFM}

Note 1/ V_CC-CORESet Point Error Tolerance is per below :

Tolerance V_CC-COREVID Voltage Range

--------------- --------------------------------------------------------

+/-1.5% V_CC-CORE> 0.7500V

+/-11.5mV 0.5000V </= Vcc_core </= 0.75000V

Datasheet

33

Electrical Specifications

Figure 5.

Deeper Sleep V_CCand I_CCLoadline for Quad-Core Extreme Mobile Processor

V_CC-CORE[V]

Slope = -2.1 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V_CC-COREmax {HFM|LFM}

V_{CC-CORE, DC}max {HFM|LFM}

13mV= RIPPLE

V_CC-COREnom {HFM|LFM}

V_{CC-CORE, DC}min {HFM|LFM}

V_CC-COREmin {HFM|LFM}

+/-V_CC-CORETolerance

= VR St. Pt. Error 1/

I_CC-CORE

[A]

0

I_CC-COREmax

{HFM|LFM}

Note 1/ V_CC-CORESet Point Error Tolerance is per below:

Tolerance

V_CC-COREVID Voltage Range

--------------- --------------------------------------------------------

+/-[(VID*1.5%)-3mV]

+/-(11.5mV-3mV)

V_CC-CORE> 0.7500V

0.5000V </= V_CC-CORE</= 0.7500V

0.3000V </= V_CC-CORE< 0.5000V

NOTE: Deeper Sleep mode tolerance depends on VID value.

Table 9.

AGTL+ Signal Group DC Specifications (Sheet 1 of 2)

Symbol

Parameter

I/O Voltage

Reference Voltage

Min

Typ

Max

Unit

Notes¹

V_CCP

1.00

0.65

1.05

0.70

0.67

25

1.10

0.72

0.7

V

Ω

GTLREF

6

GTLREF_2 Reference Voltage_2

0.653

24.75

R_COMP

R_ODT/A

Compensation Resistor

25.25

10

Termination Resistor

Address

45

50

55

Ω

11, 12

11, 13

11, 14

Termination Resistor

Data

R_ODT/D

Termination Resistor

Control

R_ODT/Cntrl

V_IH

V_IL

Input High Voltage

Input Low Voltage

Output High Voltage

0.82

-0.10

0.90

1.05

0

1.20

0.55

1.10

V

3,6

2,4

6

V_OH

V_CCP

34

Datasheet

Electrical Specifications

Table 9.

AGTL+ Signal Group DC Specifications (Sheet 2 of 2)

Termination Resistance

Address

R_TT/A

R_TT/D

R_TT/Cntrl

R_ON/A

45

50

55

Ω

7, 12

7, 13

7, 14

5, 12

5, 13

5, 14

Termination Resistance

Data

Termination Resistance

Control

45

50

55

Buffer On Resistance

Address

8.25

8.33

12.25

Buffer On Resistance

Data

R_ON/D

Buffer On Resistance

Control

R_ON/Cntrl

I_LI

Input Leakage Current

Pad Capacitance

—

± 100

2.75

µA

pF

8

9

Cpad

1.80

2.30

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

_ILis defined as the maximum voltage level at a receiving agent that will be interpreted as

a logical low value.

_IHis defined as the minimum voltage level at a receiving agent that will be interpreted as

a logical high value.

_IHand V_OHmay experience excursions above V_CCP. However, input signal drivers must

comply with the signal quality specifications.

This is the pulldown driver resistance. Refer to processor I/O Buffer Models for I/V

characteristics. Measured at 0.31*V_CCP. R_ON(min) = 0.418*R_TT, R_ON(typ) = 0.455*R_TT,

V

3.

4.

5.

V

R_ON(max) = 0.527*R_TT. R_TTtypical value of 55 Ω is used for R_ONtyp/min/max

calculations.

6.

7.

GTLREF/GTLREF_2 should be generated from V_CCPwith a 1% tolerance resistor divider.

The V_CCPreferred to in these specifications is the instantaneous V_CCP

.

R_TTis the on-die termination resistance measured at V_OLof the AGTL+ output driver.

Measured at 0.31*V_CCP. R_TTis connected to V_CCPon die. Refer to processor I/O buffer

models for I/V characteristics.

8.

Specified with on-die R_TTand R_ONturned off. Vin between 0 and V_CCP.

9.

Cpad includes die capacitance only. No package parasitics are included.

This is the external resistor on the comp pins.

10.

11.

12.

13.

14.

On-die termination resistance, measured at 0.33*V_CCP

.

Applies to Signals A[35:3].

Applies to Signals D[63:0].

Applies to Signals BPRI#, DEFER#, PREQ#, PREST#, RS[2:0]#, TRDY#, ADS#, BNR#,

BPM[3:0], BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, DSTB[1:0]#,

DSTBP[3:0] and DSTBN[3:0]#.

Datasheet

35

Electrical Specifications

Table 10.

CMOS Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min

Typ

Max

Unit Notes¹

V_CCP

V_IL

1.00

-0.10

0.7*V_CCP

-0.10

0.9*V_CCP

1.5

1.05

0.00

V_CCP

0

1.10

0.3*V_CCP

V_CCP+0.1

0.1*V_CCP

V_CCP+0.1

4.1

V

Input Low Voltage CMOS

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Current

Output High Current

Input Leakage Current

Pad Capacitance

V

2, 3

2

V_IH

V_OL

V_OH

I_OL

V

2

V_CCP

—

V

2

mA

µA

pF

4

I_OH

1.5

—

4.1

5

I_LI

—

±100

6

Cpad1

1.80

2.30

2.75

7

Pad Capacitance for CMOS

Input

Cpad2

0.95

1.2

1.45

pF

8

NOTES:

1.

2.

3.

4.

5.

6.

7.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V_CCPreferred to in these specifications refers to instantaneous V_CCP

Refer to the processor I/O Buffer Models for I/V characteristics.

Measured at 0.1 *V_CCP

Measured at 0.9 *V_CCP

For Vin between 0 V and V_CCP. Measured when the driver is tristated.

Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package

parasitics are included.

.

8.

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are

included.

Table 11.

Open Drain Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes¹

V_OH

V_OL

I_OL

Output High Voltage

Output Low Voltage

Output Low Current

Output Leakage Current

Pad Capacitance

V_CCP–5%

V_CCP

—

V_CCP+5%

0.20

V

3

0

16

—

50

mA

µA

pF

2

4

5

I_LO

—

±200

2.75

Cpad

1.80

2.30

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2 V.

V

_OHis determined by value of the external pull-up resistor to V_CCP. Refer to the appropriate

platform design guide for details.

For Vin between 0 V and V_OH

4.

5.

.

Cpad includes die capacitance only. No package parasitics are included.

§

36

Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin

Information

4.1

Package Mechanical Specifications

The processor is available in a 478-pin Micro-FCPGA package. The package mechanical

dimensions are shown in Figure 6 and Figure 7.

The mechanical package pressure specifications are in a direction normal to the surface

of the processor. This requirement protects the processor die from fracture risk due to

uneven die pressure distribution under tilt, stack-up tolerances and other similar

conditions. These specifications assume that a mechanical attach is designed

specifically to load one type of processor.

The processor package substrate should not be used as a mechanical reference or load-

bearing surface for the thermal or mechanical solution.

Datasheet

37

Package Mechanical Specifications and Pin Information

Figure 6.

Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2)

38

Datasheet

Package Mechanical Specifications and Pin Information

Figure 7.

Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2)

Datasheet

39

Package Mechanical Specifications and Pin Information

4.2

Processor Pinout and Pin List

Figure 8 and Figure 9 shows the processor pinout as viewed from the top of the

package. Table 12 provides the pin list, arranged numerically by pin name. Table 13

provides the pin list, arranged numerically by pin number. Table 14 is the signal

description for processor. Table 15 lists new quad-core processor pins compared to the

Intel Core 2 Duo processor.

Figure 8.

Quad-Core Processor Pinout (Top Package View, Left Side)

1

2

3

4

5

6

7

8

9

10

11

12

13

A

VSS

SMI#

VSS

FERR#

A20M#

VCC

VSS

VCC

VSS

VCC

A

B

BPM_2[

2]#

B

INIT#

TEST7

TDO_M

VSS

LINT1

DPSLP#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

IGNNE

#

THERM

TRIP#

C

D

E

RESET#

VSS

LINT0

C

D

E

STPCLK

#

PWRGO

OD

RSVD

BNR#

VSS

SLP#

VCC

RSVD

VSS

DPRSTP

#

DBSY#

HITM#

VSS

GTLREF

_CONT

ROL

F

BR0#

VSS

RS[0]#

RS[1]#

VSS

TDI_M

VCC

VSS

VCC

VSS

F

G

H

VSS

TRDY#

RS[2]#

VSS

BPRI#

HIT#

VSS

G

H

REQ[1]

#

ADS#

LOCK#

DEFER#

REQ[3]

#

J

A[9]#

VSS

A[3]#

VSS

VCCP

J

REQ[2]

#

REQ[0]

#

K

L

VSS

A[6]#

A[4]#

VSS

VCCP

VSS

K

L

REQ[4]#

A[13]#

VSS

A[5]#

ADSTB[0]

#

BPM_2[

1]#

M

A[7]#

VCCP

M

BPM_2[0

]#

N

VSS

A[8]#

A[10]#

VSS

VCCP

N

P

R

A[15]#

A[16]#

A[12]#

VSS

A[14]#

A[24]#

A[11]#

VSS

P

R

A[19]#

VCCP

THRMD

A_2

T

U

V

VSS

A[26]#

VSS

A[25]#

A[18]#

VSS

VCCP

VSS

T

U

V

A[23]#

A[30]#

VSS

A[21]#

A[31]#

ADSTB[1]

#

THRMD

C_2

VCCP

W

Y

VSS

A[27]#

A[17]#

A[32]#

VSS

A[28]#

A[22]#

A[20]#

VSS

W

Y

COMP[3]

A[29]#

A

AA

AB

AC

AD

AE

AF

COMP[2]

VSS

A[34]#

PRDY#

VSS

A[35]#

TDO

A[33]#

VSS

TMS

TDI

TRST#

VSS

BR1#

VCC

RSVD

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

A

B

BPM[3]

#

A

C

PREQ#

BPM[2]#

VSS

TCK

RSVD

VSS

BPM[1]

#

BPM[0]

#

A

D

VSS

VID[0]

PSI#

VSS

SENSE

BPM_2[

3]#

A

E

VID[6]

VID[4]

VSS

VID[2]

VCC

SENSE

A

F

TEST5

VSS

VID[5]

VID[3]

VID[1]

VSS

VCC

VSS

VCC

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

40

Datasheet

Package Mechanical Specifications and Pin Information

Figure 9.

Quad-Core Processor Pinout (Top Package View, Right Side)

14

15

16

17

18

19

20

21

22

23

24

THRMDA

VSS

25

VSS

26

A

B

C

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BCLK[1]

VSS

BCLK[0]

BSEL[0]

VSS

TEST6

VCCA

A

B

C

VCC

BSEL[1]

TEST1

THRMDC

VSS

DBR#

BSEL[2]

TEST3

PROCHOT

#

D

VCC

VSS

VCC

VSS

IERR#

GTLREF_2

VSS

DPWR#

TEST2

VSS

D

E

F

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DRDY#

VCCP

D[0]#

VSS

D[7]#

D[4]#

VSS

D[6]#

VSS

D[2]#

D[13]#

VSS

E

F

D[1]#

D[9]#

G

D[3]#

D[5]#

G

DSTBP[

0]#

H

VSS

D[12]#

D[15]#

VSS

DINV[0]#

H

DSTBN[

0]#

J

K

L

VCCP

VSS

D[11]#

VSS

D[10]#

D[8]#

VSS

J

K

L

D[14]#

D[22]#

D[17]#

D[29]#

VSS

DSTBN[

1]#

D[20]#

DSTBP[

1]#

M

VCCP

VSS

D[23]#

D[21]#

VSS

M

N

P

VCCP

VSS

D[16]#

D[26]#

VSS

DINV[1]#

VSS

D[31]#

D[24]#

VSS

N

P

D[25]#

D[18]#

COMP[0

]

R

T

VCCP

VSS

D[19]#

VSS

D[28]#

D[27]#

VSS

R

T

D[37]#

DINV[2]#

D[30]#

D[38]#

VSS

COMP[1

]

U

D[39]#

U

V

VCCP

VSS

D[36]#

VSS

D[34]#

D[43]#

VSS

D[35]#

VSS

V

W

D[41]#

D[44]#

W

DSTBN[

2]#

Y

VSS

D[32]#

VSS

D[42]#

D[45]#

VSS

D[40]#

VSS

Y

DSTBP[

2]#

A

AA

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

D[50]#

D[46]#

A

B

AB

AC

D[52]#

VSS

D[51]#

D[60]#

VSS

D[63]#

D[61]#

VSS

D[33]#

VSS

D[47]#

D[57]#

VSS

D[53]#

GTLREF

VSS

DINV[3

]#

A

C

A

D

A

D

D[54]#

VCC

D[59]#

D[58]#

D[49]#

D[48]#

DSTBN[3]

#

A

E

AE

AF

D[55]#

DSTBP[3]

#

A

F

VCC

VSS

VCC

VSS

VCC

VSS

D[62]#

D[56]#

VSS

TEST4

14

15

16

17

18

19

20

21

22

23

24

25

26

Datasheet

41

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

A20M#

A[10]#

A6

CMOS

Input

Input/

Output

A[35]#

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

ADS#

AA3

Source Synch

Common Clock

Source Synch

Input/

Output

N3

P5

Source Synch

Input/

Output

J4

Input/

Output

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

A[33]#

A[34]#

Source Synch

Input/

Output

L5

L4

K5

M3

N2

J1

Input/

Output

P2

Input/

Output

Input/

Output

L2

Input/

Output

Input/

Output

P4

Input/

Output

Input/

Output

P1

Input/

Output

Input/

Output

R1

Y2

Input/

Output

Input/

Output

Input/

Output

H1

Input/

Output

U5

R3

W6

U4

Y5

Input/

Output

ADSTB[0]# M1

ADSTB[1]# V1

Input/

Output

Input/

Output

Input/

Output

BCLK[0]

BCLK[1]

A22

A21

Bus Clock

Input

Input/

Output

Input/

Output

BNR#

E2

Common Clock

Input/

Output

Input/

Output

BPM[0]#

AD4

Input/

Output

U1

R4

T5

BPM[1]#

BPM[2]#

AD3

AD1

Common Clock Output

Input/

Output

Input/

Common Clock

Output

Input/

Output

BPM[3]#

AC4

Input/

Common Clock

Output

Input/

Output

BPM_2[0]# N5

BPM_2[1]# M4

BPM_2[2]# B2

T3

Common Clock Output

Input/

Output

W2

W5

Y4

Input/

Common Clock

Output

Input/

Output

Input/

Common Clock

Output

BPM_2[3]# AE8

Input/

Output

BPRI#

BR0#

G5

F1

Common Clock Input

Input/

Output

U2

V4

W3

AA4

AB2

Input/

Common Clock

Output

Input/

Output

Input/

Common Clock

Output

BR1#

AA7

Input/

Output

BSEL[0]

BSEL[1]

BSEL[2]

B22

B23

C21

CMOS

Output

Input/

Output

Input/

Output

42

Datasheet

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

Input/

Output

Input/

Output

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

R26

Power/Other

Source Synch

D[29]#

D[2]#

L25

Source Synch

Input/

Output

Input/

Output

U26

AA1

Y1

E26

Input/

Output

Input/

Output

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[3]#

T25

Input/

Output

Input/

Output

N25

Y22

Input/

Output

Input/

Output

E22

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

F24

L23

M24

L22

M23

P25

P23

P22

T24

R24

Input/

Output

Input/

Output

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[1]#

AB24

V24

Input/

Output

Input/

Output

Input/

Output

Input/

Output

V26

Input/

Output

Input/

Output

V23

Input/

Output

Input/

Output

T22

Input/

Output

Input/

Output

U25

U23

G22

Y25

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[4]#

Input/

Output

Input/

Output

W22

Y23

Input/

Output

Input/

Output

Input/

Output

Input/

Output

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

W24

W25

AA23

AA24

AB25

AE24

AD24

F23

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

D[50]#

AA21

Datasheet

43

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

Input/

Output

Input/

Output

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[5]#

AB22

Source Synch

DPWR#

DRDY#

D24

Common Clock

Source Synch

Input/

Output

Input/

Output

AB21

AC26

F21

Input/

Output

Input/

Output

DSTBN[0]# J26

DSTBN[1]# L26

DSTBN[2]# Y26

DSTBN[3]# AE25

DSTBP[0]# H26

DSTBP[1]# M26

DSTBP[2]# AA26

DSTBP[3]# AF24

Input/

Output

Input/

Output

AD20 Source Synch

Input/

Output

Input/

Output

AE22

AF23

AC25

AE21

Source Synch

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

AD21 Source Synch

Input/

Output

Input/

Output

G25

Source Synch

Input/

Output

FERR#

A5

Open Drain

Power/Other

Output

Input

D[60]#

D[61]#

D[62]#

D[63]#

D[6]#

AC22

GTLREF

GTLREF_2

AD26

D22

Input/

Output

AD23 Source Synch

GTLREF_C

ONTROL

Input/

Output

Input/

Output

F8

G6

E4

CMOS

AF22

AC23

E25

Source Synch

Input/

Output

Input/

Output

HIT#

Common Clock

Input/

Output

Input/

Output

HITM#

IERR#

IGNNE#

INIT#

LINT0

D20

C4

Open Drain

CMOS

Output

Input

Input/

Output

D[7]#

E23

Input/

Output

D[8]#

K24

B3

CMOS

C6

CMOS

Input/

Output

D[9]#

G24

C20

E1

Source Synch

CMOS

LINT1

B4

CMOS

DBR#

Output

Input/

Output

LOCK#

H4

Common Clock

Input/

Output

DBSY#

DEFER#

DINV[0]#

Common Clock

PRDY#

PREQ#

AC2

AC1

Common Clock Output

Common Clock Input

H5

Common Clock Input

Input/

Source Synch

Output

Input/

Open Drain

H25

PROCHOT# D21

Output

Input/

Source Synch

Output

PSI#

AE6

D6

CMOS

Output

Input

DINV[1]#

DINV[2]#

DINV[3]#

N24

PWRGOOD

Input/

Source Synch

Output

U22

Input/

Output

REQ[0]#

REQ[1]#

REQ[2]#

K3

H2

K2

Source Synch

Input/

Source Synch

Output

AC20

Input/

Output

DPRSTP#

DPSLP#

E5

B5

CMOS

Input

Input/

Output

44

Datasheet

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

Input/

Output

VCC

A15

Power/Other

REQ[3]#

REQ[4]#

J3

Source Synch

A17

Input/

Output

L1

A18

A20

RESET#

RS[0]#

RS[1]#

RS[2]#

RSVD

C1

Common Clock Input

Reserved

AA9

F3

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB7

F4

G3

D2

RSVD

AA8

AC8

D8

Reserved

RSVD

Reserved

RSVD

Reserved

SLP#

D7

CMOS

Open Drain

Test

Input

Output

SMI#

A3

AB9

STPCLK#

TCK

D5

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AC7

AC5

AA6

F6

TDI

TDI_M

TDO

AB3

D3

C23

D25

C24

AF26

AF1

A26

C3

TDO_M

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

TEST7

Test

AC9

Test

AC10

AC12

AC13

AC15

AC17

AC18

AD7

Test

THERMTRIP

#

C7

Open Drain

Output

THRMDA

A24

Power/Other

CMOS

THRMDA_2 T2

THRMDC

B25

AD9

THRMDC_2 V3

AD10

AD12

AD14

AD15

AD17

AD18

AE9

TMS

AB5

Input

TRDY#

TRST#

VCC

G2

Common Clock Input

AB6

A7

CMOS

Input

Power/Other

VCC

A9

VCC

A10

A12

A13

VCC

AE10

AE12

VCC

Datasheet

45

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

VCC

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

B7

Power/Other

VCC

E13

E15

E17

E18

E20

F7

Power/Other

CMOS

VCC

F9

VCC

F10

F12

F14

F15

F17

F18

F20

B26

C26

G21

J6

VCC

B9

VCCA

VCCP

VCCSENSE

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

B10

B12

B14

B15

B17

B18

B20

C9

J21

K6

K21

M6

M21

N6

C10

C12

C13

C15

C17

C18

D9

N21

R6

R21

T6

T21

V6

D10

D12

D14

D15

D17

D18

E7

V21

W21

AF7

AD6

AF5

AE5

AF4

AE3

AF3

AE2

Output

CMOS

E9

CMOS

E10

E12

CMOS

46

Datasheet

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

VSS

A2

Power/Other

VSS

AD19

AD22

AD25

AE1

AE4

AE11

AE14

AE16

AE19

AE23

AE26

AF2

Power/Other

A4

A8

A11

A14

A16

A19

A23

A25

AA2

AA5

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AF6

AF8

AF11

AF13

AF16

AF19

AF21

AF25

B6

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

B8

B11

B13

B16

B19

B21

B24

C2

AC6

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

C5

C8

C11

C14

C16

C19

C22

C25

D1

AD11 Power/Other

AD13 Power/Other

AD16 Power/Other

D4

D11

Datasheet

47

Package Mechanical Specifications and Pin Information

Table 12.

Pin Listing by Pin Name

Table 12.

Pin Listing by Pin Name

Name

#

Signal

Buffer Type

Name

#

Signal

Buffer Type

Direction

VSS

D13

D16

D19

D23

D26

E3

Power/Other

VSS

VSSSENSE

L21

L24

M2

Power/Other

M5

M22

M25

N1

E6

E8

N4

E11

E14

E16

E19

E21

E24

F2

N23

N26

P3

P6

P21

P24

R2

F5

R5

F11

F13

F16

F19

F22

F25

G1

R22

R25

T1

T4

T23

T26

U3

G4

U6

G23

G26

H3

U21

U24

V2

H6

V5

H21

H24

J2

V22

V25

W1

W4

W23

W26

Y3

J5

J22

J25

K1

K4

Y6

K23

K26

L3

Y21

Y24

AE7

Output

L6

48

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

A2

VSS

Power/Other

CMOS

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

A3

SMI#

VSS

Input

A4

Power/Other

Open Drain

CMOS

A5

FERR#

A20M#

VCC

Output

Input

A6

A7

Power/Other

Bus Clock

A8

VSS

A9

VCC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

VCC

VSS

Input/

Output

AA21

AA22

AA23

D[50]#

VSS

Source Synch

Power/Other

Source Synch

VCC

Input/

Output

D[45]#

VSS

VCC

Input/

Output

AA24

AA25

AA26

AB1

D[46]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

VSS

VCC

Input/

Output

VCC

DSTBP[2]#

VSS

VCC

Input/

Output

AB2

A[34]#

BCLK[1]

BCLK[0]

VSS

Input

AB3

AB4

AB5

AB6

AB7

AB8

AB9

TDO

VSS

Open Drain

Power/Other

CMOS

Output

Bus Clock

Power/Other

Test

TMS

TRST#

VCC

VSS

Input

THRMDA

VSS

CMOS

Power/Other

TEST6

Input/

Output

AA1

AA2

AA3

COMP[2]

VSS

Power/Other

Source Synch

VCC

AB10 VCC

AB11 VSS

AB12 VCC

AB13 VSS

AB14 VCC

AB15 VCC

AB16 VSS

AB17 VCC

AB18 VCC

AB19 VSS

AB20 VCC

Input/

Output

A[35]#

Input/

Output

AA4

A[33]#

Source Synch

AA5

AA6

VSS

TDI

Power/Other

CMOS

Input

Common

Clock

Input/

Output

AA7

BR1#

AA8

RSVD

VCC

VSS

Reserved

AA9

Power/Other

AA10

AA11

Datasheet

49

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

Input/

Output

Common

AB21 D[52]#

Source Synch

AD1

AD2

AD3

BPM[2]#

Output

Clock

Input/

Output

VSS

Power/Other

AB22 D[51]#

AB23 VSS

Source Synch

Power/Other

Source Synch

Common

Clock

BPM[1]#

Output

Input/

Output

Common

Clock

Input/

Output

AB24 D[33]#

AD4

BPM[0]#

Input/

Output

AD5

AD6

AD7

AD8

AD9

VSS

Power/Other

CMOS

AB25 D[47]#

AB26 VSS

Source Synch

Power/Other

VID[0]

VCC

Output

Power/Other

Common

Clock

AC1

PREQ#

Input

VSS

VCC

Common

Clock

AC2

AC3

AC4

PRDY#

VSS

Output

AD10 VCC

AD11 VSS

AD12 VCC

AD13 VSS

AD14 VCC

AD15 VCC

AD16 VSS

AD17 VCC

AD18 VCC

AD19 VSS

Power/Other

Common

Clock

Input/

Output

BPM[3]#

AC5

AC6

AC7

AC8

AC9

TCK

CMOS

Input

VSS

VCC

RSVD

VCC

Power/Other

Reserved

Power/Other

AC10 VCC

AC11 VSS

AC12 VCC

AC13 VCC

AC14 VSS

AC15 VCC

AC16 VSS

AC17 VCC

AC18 VCC

AC19 VSS

Input/

Output

AD20 D[54]#

Source Synch

Input/

Output

AD21 D[59]#

AD22 VSS

Source Synch

Power/Other

Source Synch

Input/

Output

AD23 D[61]#

Input/

Output

AD24 D[49]#

Source Synch

AD25 VSS

Power/Other

CMOS

Input/

Output

AD26 GTLREF

Input

AC20 DINV[3]#

AC21 VSS

Source Synch

Power/Other

Source Synch

AE1

AE2

AE3

AE4

AE5

AE6

AE7

VSS

VID[6]

VID[4]

VSS

Output

Input/

Output

AC22 D[60]#

CMOS

Power/Other

CMOS

Input/

Output

AC23 D[63]#

AC24 VSS

Source Synch

Power/Other

Source Synch

VID[2]

PSI#

Output

CMOS

Input/

Output

AC25 D[57]#

VSSSENSE

Power/Other

Common

Clock

Input/

Output

Input/

Output

AE8

BPM_2[3]#

AC26 D[53]#

Source Synch

50

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

AE9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

AF19

AF20

AF21

VSS

VCC

VSS

Power/Other

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

Input/

Output

AF22

AF23

AF24

D[62]#

Source Synch

Input/

Output

D[56]#

Input/

Output

DSTBP[3]#

AF25

AF26

VSS

Power/Other

Test

TEST4

Common

Clock

Input/

Output

B2

BPM_2[2]#

B3

INIT#

LINT1

DPSLP#

VSS

CMOS

Input

Input/

Output

AE21

D[58]#

Source Synch

B4

CMOS

B5

CMOS

Input/

Output

AE22

AE23

AE24

D[55]#

VSS

Source Synch

Power/Other

Source Synch

B6

Power/Other

CMOS

B7

VCC

Input/

Output

B8

VSS

D[48]#

B9

VCC

Input/

Output

AE25

DSTBN[3]#

Source Synch

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

VCC

AE26

AF1

VSS

Power/Other

Test

VSS

TEST5

VSS

VCC

AF2

Power/Other

CMOS

VSS

AF3

VID[5]

VID[3]

VID[1]

VSS

Output

VCC

AF4

CMOS

VCC

AF5

CMOS

VSS

AF6

Power/Other

VCC

AF7

VCCSENSE

VSS

VCC

AF8

VSS

AF9

VCC

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

VCC

VSS

BSEL[0]

BSEL[1]

VSS

Output

VCC

CMOS

VSS

Power/Other

VCC

THRMDC

VCCA

VCC

VSS

Common

Clock

C1

C2

RESET#

VSS

Input

VCC

Power/Other

VCC

Datasheet

51

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

C3

C4

C5

C6

TEST7

Test

D15

D16

D17

D18

D19

D20

VCC

VSS

Power/Other

Open Drain

IGNNE#

VSS

CMOS

Input

Power/Other

CMOS

VCC

VSS

LINT0

Input

THERMTRIP

#

C7

Open Drain

Output

IERR#

Output

C8

VSS

Power/Other

CMOS

Input/

Output

D21

PROCHOT#

Open Drain

C9

VCC

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

VCC

D22

D23

GTLREF_2

VSS

Power/Other

Input

VSS

VCC

Common

Clock

Input/

Output

D24

DPWR#

VCC

D25

D26

TEST2

VSS

Test

VSS

Power/Other

VCC

Common

Clock

Input/

Output

E1

DBSY#

VSS

VCC

Common

Clock

Input/

Output

E2

E3

E4

BNR#

VSS

VCC

Power/Other

VSS

Common

Clock

Input/

Output

DBR#

BSEL[2]

VSS

Output

HITM#

CMOS

E5

DPRSTP#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

CMOS

Input

Power/Other

Test

E6

Power/Other

TEST1

TEST3

VSS

E7

Test

E8

Power/Other

Reserved

E9

VCCA

VSS

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

D2

RSVD

TDO_M

VSS

D3

Open Drain

Power/Other

CMOS

Output

D4

D5

STPCLK#

PWRGOOD

SLP#

RSVD

VCC

Input

D6

CMOS

D7

CMOS

D8

Reserved

D9

Power/Other

D10

D11

D12

D13

D14

VCC

VSS

VCC

Input/

Output

E22

D[0]#

Source Synch

VSS

VCC

52

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

Input/

Output

Common

E23

E24

E25

D[7]#

Source Synch

Power/Other

Source Synch

G2

TRDY#

Input

Clock

VSS

Common

Clock

G3

G4

G5

RS[2]#

VSS

Input/

Output

D[6]#

Power/Other

Input/

Output

Common

Clock

E26

D[2]#

Source Synch

BPRI#

Input

Common

Clock

Input/

Output

Common

Clock

Input/

Output

F1

F2

F3

BR0#

VSS

G6

HIT#

VCCP

D[3]#

VSS

Power/Other

G21

G22

G23

G24

Power/Other

Source Synch

Power/Other

Source Synch

Common

Clock

Input/

Output

RS[0]#

Input

Common

Clock

F4

RS[1]#

Input/

Output

D[9]#

F5

F6

F7

VSS

Power/Other

CMOS

TDI_M

VCC

Input

Input/

Output

G25

G26

H1

D[5]#

VSS

Source Synch

Power/Other

GTLREF_CO

NTROL

Input/

Output

F8

CMOS

Common

Clock

Input/

Output

ADS#

F9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

Input/

Output

H2

H3

H4

REQ[1]#

VSS

Source Synch

Power/Other

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

Common

Clock

Input/

Output

LOCK#

Common

Clock

H5

DEFER#

Input

H6

VSS

Power/Other

H21

Input/

Output

H22

D[12]#

Source Synch

Input/

Output

H23

H24

H25

D[15]#

VSS

Source Synch

Power/Other

Source Synch

Common

Clock

Input/

Output

F21

F22

F23

DRDY#

VSS

Input/

Output

DINV[0]#

Power/Other

Source Synch

Input/

Output

H26

DSTBP[0]#

Source Synch

Input/

Output

D[4]#

Input/

Output

J1

J2

J3

A[9]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

F24

F25

F26

G1

D[1]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Input/

Output

REQ[3]#

Input/

Output

D[13]#

VSS

Input/

Output

J4

J5

A[3]#

VSS

Source Synch

Power/Other

Datasheet

53

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

J6

VCCP

Power/Other

Input/

Output

L25

L26

D[29]#

Source Synch

J21

J22

VCCP

VSS

Input/

Output

DSTBN[1]#

Input/

Output

Input/

Output

J23

D[11]#

Source Synch

M1

M2

M3

ADSTB[0]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

J24

J25

J26

K1

D[10]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Input/

Output

A[7]#

Input/

Output

Common

Clock

DSTBN[0]#

VSS

M4

BPM_2[1]#

Output

M5

VSS

Power/Other

Input/

Output

M6

VCCP

VSS

K2

REQ[2]#

M21

M22

Input/

Output

K3

K4

K5

REQ[0]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

M23

D[23]#

Source Synch

Input/

Output

A[6]#

Input/

Output

M24

M25

M26

N1

D[21]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

K6

VCCP

Power/Other

K21

Input/

Output

DSTBP[1]#

VSS

Input/

Output

K22

K23

K24

D[14]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

N2

A[8]#

Input/

Output

D[8]#

Input/

Output

N3

N4

N5

A[10]#

VSS

Source Synch

Power/Other

Input/

Output

K25

K26

L1

D[17]#

VSS

Source Synch

Power/Other

Source Synch

Common

Clock

Input/

Output

BPM_2[0]#

Input/

Output

REQ[4]#

N6

VCCP

Power/Other

Input/

Output

L2

L3

L4

A[13]#

VSS

Source Synch

Power/Other

Source Synch

N21

Input/

Output

N22

N23

N24

D[16]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

A[5]#

Input/

Output

Input/

Output

L5

A[4]#

Source Synch

DINV[1]#

L6

VSS

Power/Other

Input/

Output

N25

N26

P1

D[31]#

VSS

Source Synch

Power/Other

Source Synch

L21

Input/

Output

L22

D[22]#

Source Synch

Input/

Output

A[15]#

Input/

Output

L23

L24

D[20]#

VSS

Source Synch

Power/Other

Input/

Output

P2

P3

A[12]#

VSS

Source Synch

Power/Other

54

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

Signal

Buffer

Type

#

Pin Name

Direction

Pin Name

Direction

Input/

Output

Input/

Output

P4

P5

A[14]#

Source Synch

T24

D[27]#

Source Synch

Input/

Output

Input/

Output

A[11]#

T25

T26

U1

D[30]#

VSS

Source Synch

Power/Other

Source Synch

P6

VSS

Power/Other

P21

Input/

Output

A[23]#

Input/

Output

P22

D[26]#

Source Synch

Input/

Output

U2

U3

U4

A[30]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

P23

P24

P25

D[25]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

A[21]#

Input/

Output

D[24]#

Input/

Output

U5

A[18]#

Source Synch

Input/

Output

P26

D[18]#

Source Synch

U6

VSS

Power/Other

Input/

Output

U21

R1

R2

R3

A[16]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

U22

DINV[2]#

Source Synch

Input/

Output

Input/

Output

A[19]#

U23

U24

U25

D[39]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

R4

A[24]#

Source Synch

Input/

Output

D[38]#

R5

VSS

Power/Other

R6

VCCP

VSS

Input/

Output

U26

V1

COMP[1]

Power/Other

Source Synch

R21

R22

Input/

Output

ADSTB[1]#

Input/

Output

V2

V3

VSS

Power/Other

R23

D[19]#

Source Synch

THRMDC_2

Input/

Output

R24

R25

R26

D[28]#

VSS

Source Synch

Power/Other

Input/

Output

V4

A[31]#

Source Synch

V5

VSS

Power/Other

Input/

Output

COMP[0]

V6

VCCP

VSS

T1

T2

VSS

Power/Other

V21

V22

THRMDA_2

Input/

Output

Input/

Output

T3

T4

T5

A[26]#

VSS

Source Synch

Power/Other

Source Synch

V23

D[36]#

Source Synch

Input/

Output

V24

V25

V26

W1

D[34]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Input/

Output

A[25]#

T6

VCCP

Power/Other

Input/

Output

D[35]#

VSS

T21

Input/

Output

T22

T23

D[37]#

VSS

Source Synch

Power/Other

Input/

Output

W2

A[27]#

Datasheet

55

Package Mechanical Specifications and Pin Information

Table 13.

Pin Listing by Pin

Number

Signal

Buffer

Type

#

Pin Name

Direction

Input/

Output

W3

W4

W5

A[32]#

Source Synch

Power/Other

Source Synch

VSS

Input/

Output

A[28]#

Input/

Output

W6

A[20]#

VCCP

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

W21

W22

W23

W24

Input/

Output

D[41]#

VSS

Input/

Output

D[43]#

Input/

Output

W25

W26

Y1

D[44]#

VSS

Source Synch

Power/Other

Input/

Output

COMP[3]

Input/

Output

Y2

Y3

Y4

A[17]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

A[29]#

Input/

Output

Y5

A[22]#

Source Synch

Y6

VSS

Power/Other

Y21

Input/

Output

Y22

D[32]#

Source Synch

Input/

Output

Y23

Y24

Y25

D[42]#

VSS

Source Synch

Power/Other

Source Synch

Input/

Output

D[40]#

Input/

Output

Y26

DSTBN[2]#

Source Synch

56

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 1 of 9)

Name

Type

Description

If A20M# (Address-20 Mask) is asserted, the processor masks

physical address bit 20 (A20#) before looking up a line in any

internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address

wrap-around at the 1-MB boundary. Assertion of A20M# is only

supported in real mode.

A20M#

Input

A20M# is an asynchronous signal. However, to ensure recognition

of this signal following an input/output write instruction, it must be

valid along with the TRDY# assertion of the corresponding input/

output Write bus transaction.

A[35:3]# (Address) define a 2³⁶-byte physical memory address

space. In sub-phase 1 of the address phase, these pins transmit

the address of a transaction. In sub-phase 2, these pins transmit

transaction type information. These signals must connect the

appropriate pins of both agents on the processor FSB. A[35:3]#

are source-synchronous signals and are latched into the receiving

buffers by ADSTB[1:0]#. Address signals are used as straps, which

are sampled before RESET# is deasserted.

Input/

Output

A[35:3]#

ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[35:3]# and REQ[4:0]# pins. All bus

agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal snoop, or deferred

reply ID match operations associated with the new transaction.

Input/

Output

ADS#

Address strobes are used to latch A[35:3]# and REQ[4:0]# on

their rising and falling edges. Strobes are associated with signals

as shown below.

Input/

Output

ADSTB[1:0]#

Signals

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[35:17]# ADSTB[1]#

Associated Strobe

The differential pair BCLK (Bus Clock) determines the FSB

frequency. All FSB agents must receive these signals to drive their

outputs and latch their inputs.

BCLK[1:0]

BNR#

Input

All external timing parameters are specified with respect to the

rising edge of BCLK0 crossing V_CROSS

.

BNR# (Block Next Request) is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus

stall, the current bus owner cannot issue any new transactions.

Input/

Output

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor that indicate

the status of breakpoints and programmable counters used for

monitoring processor performance. BPM[3:0]# should connect the

appropriate pins of all processor FSB agents.This includes debug or

performance monitoring tools.

Output

BPM[2:1]#

BPM[3,0]#

Input/

Output

Datasheet

57

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 2 of 9)

Name

Type

Description

BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and

performance monitor signals of the second die. They are outputs

from the processor that indicate the status of breakpoints and

programmable counters used for monitoring processor

performance. BPM_2[3:0]# should connect the appropriate pins of

all processor FSB agents.This includes debug or performance

monitoring tools.

BPM_2[1]#

Output

BPM_2[0;3:2]

#

Input/

Output

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the FSB. It must connect the appropriate pins of both FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes

the other agent to stop issuing new requests, unless such requests

are part of an ongoing locked operation. The priority agent keeps

BPRI# asserted until all of its requests are completed, then

releases the bus by deasserting BPRI#.

BPRI#

Input

BR0# is used by the processor to request the bus. The arbitration

is done between the processor (Symmetric Agent) and GMCH (High

Priority Agent).

Input/

Output

BR0#

BR1#

Arbitration Request signal for the second die.

BR1# is connected to the first die within the package, allowing two

dies within quad-core parts to artitrite for the bus. This pin is

fundamentally provided for debug capabilities and should be left as

NC.

Input/

Output

BSEL[2:0] (Bus Select) are used to select the processor input clock

frequency. Table 4 defines the possible combinations of the signals

and the frequency associated with each combination. The required

frequency is determined by the processor, chipset and clock

synthesizer. All agents must operate at the same frequency.

BSEL[2:0]

COMP[3:0]

Output

Analog

COMP[3:0] must be terminated on the system board using

precision (1% tolerance) resistors.

58

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 3 of 9)

Name

Type

Description

D[63:0]# (Data) are the data signals. These signals provide a

64-bit data path between the FSB agents, and must connect the

appropriate pins on both agents. The data driver asserts DRDY# to

indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four

times in a common clock period. D[63:0]# are latched off the

falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group

of 16 data signals correspond to a pair of one DSTBP# and one

DSTBN#. The following table shows the grouping of data signals to

data strobes and DINV#.

Quad-Pumped Signal Groups

DSTBN#/

Input/

Output

D[63:0]#

Data Group

DINV#

DSTBP#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DINV# pins determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DINV#

signal. When the DINV# signal is active, the corresponding data

group is inverted and therefore sampled active high.

DBR# (Data Bus Reset) is used only in processor systems where

no debug port is implemented on the system board. DBR# is used

by a debug port interposer so that an in-target probe can drive

system reset. If a debug port is implemented in the system, DBR#

is a no connect in the system. DBR# is not a processor signal.

DBR#

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the FSB to indicate that the data bus is in use. The

data bus is released after DBSY# is deasserted. This signal must

connect the appropriate pins on both FSB agents.

Input/

Output

DBSY#

DEFER#

DEFER# is asserted by an agent to indicate that a transaction

cannot be ensured in-order completion. Assertion of DEFER# is

normally the responsibility of the addressed memory or input/

output agent. This signal must connect the appropriate pins of both

FSB agents.

Input

Datasheet

59

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 4 of 9)

Name

Type

Description

DINV[3:0]# (Data Bus Inversion) are source synchronous and

indicate the polarity of the D[63:0]# signals. The DINV[3:0]#

signals are activated when the data on the data bus is inverted.

The bus agent will invert the data bus signals if more than half the

bits, within the covered group, would change level in the next

cycle.

DINV[3:0]# Assignment To Data Bus

Input/

Output

DINV[3:0]#

Bus Signal

Data Bus Signals

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DPRSTP#, when asserted on the platform, causes the processor to

transition from the Deep Sleep State to the Deeper Sleep state or

C6 state. To return to the Deep Sleep State, DPRSTP# must be

deasserted. DPRSTP# is driven by the ICH9M chipset.

DPRSTP#

Input

DPSLP# when asserted on the platform causes the processor to

transition from the Sleep State to the Deep Sleep state. To return

to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven

by the ICH9M chipset.

DPSLP#

DPWR#

DRDY#

DPWR# is a control signal used by the chipset to reduce power on

the processor data bus input buffers. The processor drives this pin

during dynamic FSB frequency switching.

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be deasserted to insert idle clocks.

This signal must connect the appropriate pins of both FSB agents.

Input/

Output

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DINV[0]#

DSTBN[0]#

Input/

Output

DSTBN[3:0]#

D[31:16]#, DINV[1]# DSTBN[1]#

D[47:32]#, DINV[2]# DSTBN[2]#

D[63:48]#, DINV[3]# DSTBN[3]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

DSTBP[0]#

D[15:0]#, DINV[0]#

Input/

Output

DSTBP[3:0]#

D[31:16]#, DINV[1]# DSTBP[1]#

D[47:32]#, DINV[2]# DSTBP[2]#

D[63:48]#, DINV[3]# DSTBP[3]#

60

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 5 of 9)

Name

Type

Description

FERR# (Floating-point Error)/PBE# (Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#.

When STPCLK# is not asserted, FERR#/PBE# indicates a floating

point when the processor detects an unmasked floating-point error.

FERR# is similar to the ERROR# signal on the Intel® 387

coprocessor, and is included for compatibility with systems using

Microsoft MS-DOS*-type floating-point error reporting. When

STPCLK# is asserted, an assertion of FERR#/PBE# indicates that

the processor has a pending break event waiting for service. The

assertion of FERR#/PBE# indicates that the processor should be

returned to the Normal state. When FERR#/PBE# is asserted,

indicating a break event, it will remain asserted until STPCLK# is

deasserted. Assertion of PREQ# when STPCLK# is active will also

cause an FERR# break event.

FERR#/PBE#

Output

For additional information on the pending break event functionality,

including identification of support of the feature and enable/disable

information, refer to Volumes 3A and 3B of the Intel® 64 and IA-

32 Architectures Software Developer's Manuals and the Intel®

Processor Identification and CPUID Instruction application note.

GTLREF determines the signal reference level for AGTL+ input pins.

GTLREF should be set at 2/3 V_CCP. GTLREF is used by the AGTL+

receivers to determine if a signal is a logical 0 or logical 1.

GTLREF

Input

Refer to the appropriate platform design guide for details on

GTLREF implementation.

GTL reference level for AGTL+ input pins of the second die.

GTLREF_2

Refer to the appropriate platform design guide for details on

GTLREF implementation.

This pin can be used as GTLREF_2 disconnect circuit control signal.

GTLREF_2 maps out to a reserved pin on Intel® Core^TM2 Duo

Processor, for Dual Core and quad-core interchangeable

motherboard, GTLREF_CONTROL can be used as a control signal

for a circuit that will automaticlly switch between Dual Core and

quad-core modes.

GTLREF_CONT

ROL

Input/

Output

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT#

and HITM# together to indicate that it requires a snoop stall that

can be continued by reasserting HIT# and HITM# together.

HIT#

Input/

Output

HITM#

IERR# (Internal Error) is asserted by the processor as the result of

an internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may

optionally be converted to an external error signal (e.g., NMI) by

system core logic. The processor will keep IERR# asserted until the

assertion of RESET#, BINIT#, or INIT#.

IERR#

Output

Datasheet

61

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 6 of 9)

Name

Type

Description

IGNNE# (Ignore Numeric Error) is asserted to force the processor

to ignore a numeric error and continue to execute non-control

floating-point instructions. If IGNNE# is deasserted, the processor

generates an exception on a non-control floating-point instruction

if a previous floating-point instruction caused an error. IGNNE# has

no effect when the NE bit in control register 0 (CR0) is set.

IGNNE#

Input

IGNNE# is an asynchronous signal. However, to ensure recognition

of this signal following an input/output write instruction, it must be

valid along with the TRDY# assertion of the corresponding input/

output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers

inside the processor without affecting its internal caches or

floating-point registers. The processor then begins execution at the

power-on Reset vector configured during power-on configuration.

The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure

recognition of this signal following an input/output write

instruction, it must be valid along with the TRDY# assertion of the

corresponding input/output write bus transaction. INIT# must

connect the appropriate pins of both FSB agents.

INIT#

Input

If INIT# is sampled active on the active-to-inactive transition of

RESET#, then the processor executes its Built-in Self-Test (BIST).

LINT[1:0] (Local APIC Interrupt) must connect the appropriate

pins of all APIC Bus agents. When the APIC is disabled, the LINT0

signal becomes INTR, a maskable interrupt request signal, and

LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are

backward-compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS

programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of both

FSB agents. For a locked sequence of transactions, LOCK# is

asserted from the beginning of the first transaction to the end of

the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of

the FSB, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the FSB

throughout the bus locked operation and ensure the atomicity of

lock.

Probe Ready signal used by debug tools to determine processor

debug readiness.

PRDY#

PREQ#

Output

Input

Probe Request signal used by debug tools to request debug

operation of the processor.

62

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 7 of 9)

Name

Type

Description

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the

processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC) has

been activated, if enabled. As an input, assertion of PROCHOT# by

the system will activate the TCC, if enabled. The TCC will remain

active until the system deasserts PROCHOT#.

Input/

Output

PROCHOT#

By default PROCHOT# is configured as an output. The processor

must be enabled via the BIOS for PROCHOT# to be configured as

bidirectional.

Refer to the appropriate platform design guide for termination

requirements.

This signal may require voltage translation on the motherboard.

Processor Power Status Indicator signal. This signal is asserted

when the processor is both in the normal state (HFM to LFM) and in

lower power states (Deep Sleep and Deeper Sleep).

PSI#

Output

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and

power supplies are stable and within their specifications. ‘Clean’

implies that the signal remains low (capable of sinking leakage

current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal must

then transition monotonically to a high state. Rise time and

monotonicity requirements are shown in Table 29. Figure 21

illustrates the relationship of PWRGOOD to the RESET# signal.

PWRGOOD can be driven inactive at any time, but clocks and

power must again be stable before a subsequent rising edge of

PWRGOOD. It must also meet the minimum pulse width

specification in Table 29, and be followed by a 2 ms (minimum)

RESET# pulse.

PWRGOOD

Input

The PWRGOOD signal must be supplied to the processor; it is used

to protect internal circuits against voltage sequencing issues. It

should be driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins

of both FSB agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are

source synchronous to ADSTB[0]#.

Input/

Output

REQ[4:0]#

Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at

least two milliseconds after V_CCand BCLK have reached their

proper specifications. On observing active RESET#, both FSB

agents will deassert their outputs within two clocks. All processor

straps must be valid within the specified setup time before RESET#

is deasserted.

RESET#

Input

Refer to the appropriate platform design guide for termination

requirements and implementation details. There is a 55 Ω

(nominal) on die pull-up resistor on this signal.

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and

must connect the appropriate pins of both FSB agents.

RS[2:0]#

Datasheet

63

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 8 of 9)

Name

Type

Description

Reserved/ These pins are RESERVED and must be left unconnected on the

RSVD

No

Connect

board. However, it is recommended that routing channels to these

pins on the board be kept open for possible future use.

SLP# (Sleep), when asserted in Stop-Grant state, causes the

processor to enter the Sleep state. During Sleep state, the

processor stops providing internal clock signals to all units, leaving

only the Phase-Locked Loop (PLL) still operating. Processors in this

state will not recognize snoops or interrupts. The processor will

recognize only assertion of the RESET# signal, deassertion of

SLP#, and removal of the BCLK input while in Sleep state. If SLP#

is deasserted, the processor exits Sleep state and returns to Stop-

Grant state, restarting its internal clock signals to the bus and

processor core units. If DPSLP# is asserted while in the Sleep

state, the processor will exit the Sleep state and transition to the

Deep Sleep state.

SLP#

Input

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt,

the processor saves the current state and enters System

Management Mode (SMM). An SMI Acknowledge transaction is

issued and the processor begins program execution from the SMM

handler.

SMI#

Input

If an SMI# is asserted during the deassertion of RESET#, then the

processor will tristate its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to

enter a low power Stop-Grant state. The processor issues a Stop-

Grant Acknowledge transaction, and stops providing internal clock

signals to all processor core units except the FSB and APIC units.

The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is deasserted,

the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus

clock; STPCLK# is an asynchronous input.

STPCLK#

Input

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TCK

TDI

Input

TDI (Test Data In) transfers serial test data into the first die. TDI

provides the serial input needed for JTAG specification support.

TDI_M (Test Data In) transfers serial test data into the second die.

TDI_M provides the serial input needed for JTAG specification

support. Connect to TDO_M on the platform.

TDI_M

TDO

Input

Output

TDO (Test Data Out) transfers serial test data out of the second

die. TDO provides the serial output needed for JTAG specification

support.

TDO_M (Test Data Out) transfers serial test data out of the first

die. TDO_M provides the serial output needed for JTAG

specification support. Connect to TDI_M on the platform.

TDO_M

64

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 9 of 9)

Name

Type

Description

TEST1,

TEST2,

TEST3,

TEST4,

TEST5,

TEST6

TEST7

Refer to the appropriate platform design guide for further TEST1,

TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination

requirements and implementation details.

Input

The processor protects itself from catastrophic overheating by use

of an internal thermal sensor. This sensor is set well above the

normal operating temperature to ensure that there are no false

trips. The processor will stop all execution when the junction

temperature exceeds approximately 125 °C. This is signalled to the

system by the THERMTRIP# (Thermal Trip) pin.

THERMTRIP#

Output

THRMDA

Other

Thermal Diode Anode.

THRMDA_2

THRMDC

Thermal Diode Anode of the second die.

Thermal Diode Cathode.

THRMDC_2

Thermal Diode Cathode of the second die.

TMS (Test Mode Select) is a JTAG specification support signal used

by debug tools.

TMS

Input

TRDY# (Target Ready) is asserted by the target to indicate that it

is ready to receive a write or implicit writeback data transfer.

TRDY# must connect the appropriate pins of both FSB agents.

TRDY#

TRST#

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

VCC

Input

Processor core power supply.

VCCA

VCCP

VCCA provides isolated power for the internal processor core PLLs_.

Processor I/O Power Supply.

VCCSENSE together with VSSSENSE are voltage feedback signals

that control the 2.1 mΩ loadline at the processor die. It should be

used to sense voltage near the silicon with little noise.

VCCSENSE

VID[6:0]

Output

VID[6:0] (Voltage ID) pins are used to support automatic selection

of power supply voltages (V_CC). Unlike some previous generations

of processors, these are CMOS signals that are driven by the

processor. The voltage supply for these pins must be valid before

the VR can supply V_CCto the processor. Conversely, the VR output

must be disabled until the voltage supply for the VID pins becomes

valid. The VID pins are needed to support the processor voltage

specification variations. See Table 3 for definitions of these pins.

The VR must supply the voltage that is requested by the pins, or

disable itself.

Output

VSS

Input

Processor core ground node.

VSSSENSE together with VCCSENSE are voltage feedback signals

that control the 2.1-mΩ loadline at the processor die. It should be

used to sense ground near the silicon with little noise.

VSSSENSE

Output

Datasheet

65

Package Mechanical Specifications and Pin Information

Table 15.

New Pins for the Quad-Core Mobile Processor

Pin Name

BPM_2[0]#

Pin#

Description

N5 BPM_2[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals of the second die. They are outputs from the

processor that indicate the status of breakpoints and programmable

B2 counters used for monitoring processor performance. BPM_2[3:0]#

should connect the appropriate pins of all processor FSB agents.This

BPM_2[1]#

BPM_2[2]#

M4

BPM_2[3]#

AE8

includes debug or performance monitoring tools.

Arbitration Request signal for the second die.

BR1# is connected to the first die within the package, allowing two

dies within quad-core parts to artitrite for the bus. This pin is

BR1#

AA7

fundamentally provided for debug capabilities and should be left as a

NC.

GTLREF_2

D22 GTL reference level for AGTL+ input pins of the second die.

This pin can be used as GTLREF_2 disconnect circuit control signal.

GTLREF_2 maps out to a reserved pin on Intel Core 2 Duo mobile

processor, for dual-core and quad-core interchangeable

GTLREF_CONTROL

F8

motherboard,GTLREF_CONTROL can be used as a control signal for a

circuit that will automaticlly switch between Dual Core and quad-

core modes.

RSVD

AC8

These pins are RESERVED and must be left unconnected on the

AA8 board. However, it is recommended that routing channels to these

pins on the board be kept open for possible future use.

D8

TDI_M (Test Data In) transfers serial test data into the second die.

TDI_M

F6

TDI_M provides the serial input needed for JTAG specification

support. Connect to TDO_M on the platform.

TDO_M (Test Data Out) transfers serial test data out of the first die.

TDO_M

D3 TDO_M provides the serial output needed for JTAG specification

support. Connect to TDI_M on the platform.

THRMDA_2

THRMDC_2

T2

V3

Thermal Diode Anode of the second die.

Thermal Diode Cathode of the second die.

§

66

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

The processor requires a thermal solution to maintain temperatures within operating

limits.

Caution:

Operating the processor outside these operating limits may result in permanent

damage to the processor and potentially other components in the system.

Maintaining the proper thermal environment is key to reliable, long-term system

operation. A complete thermal solution includes both component and system-level

thermal management features. To allow for the optimal operation and long-term

reliability of Intel processor-based systems, the system/processor thermal solution

should be designed so the processor remains within the minimum and maximum

junction temperature (T_J) specifications at the corresponding thermal design power

(TDP) value listed in Table 16. Analysis indicates that real applications are unlikely to

cause the processor to consume the theoretical maximum power dissipation for

sustained time periods.

Table 16.

Processor Power Specifications

Processor

Number

Thermal Design

Power

Symbol

Core Frequency & Voltage

Unit Notes

QX9300

45

35

2.53 GHz & V_CCHFM

2.26 GHz & V_CCHFM

2.0 GHz & V_CCHFM

1.60 GHz & V_CCLFM

Q9100

Q9000

1, 4,

5, 6

TDP

W

Symbol

Parameter

Min Typ Max

Unit Notes

Auto Halt, Stop Grant Power

at HFM V_CC

P_AH,

—

19.4

14.5

W

2, 5, 7

2, 5, 8

P_SGNT

at LFM V_CC

Sleep Power

at HFM V_CC

at LFM V_CC

P_SLP

18.6

14.1

Deep Sleep Power

at HFM V_CC

P_DSLP

7.9

7.1

at LFM V_CC

P_DPRSLPDeeper Sleep Power

—

0

—

4.0

W

2, 8

3, 4

T_J

Junction Temperature

100

°C

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specifications.

Datasheet

67

Thermal Specifications and Design Considerations

5.

Processor TDP requirements in Intel Dynamic Acceleration mode are lesser than TDP in

HFM.

6.

7.

8.

At Tj of 100^oC

At Tj of 50^oC

At Tj of 35^oC

5.1

Monitoring Die Temperature

The processor incorporates three methods of monitoring die temperature:

• Thermal Diode

• Intel® Thermal Monitor

• Digital Thermal Sensor

Note:

The Intel Thermal Monitor (detailed in Section 5.1.2) must be used to determine when

the maximum specified processor junction temperature has been reached.

5.1.1

Thermal Diode

Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current

characteristics of a substrate PNP transistor. Since these characteristics are a function

of temperature, in principle one can use these parameters to calculate silicon

temperature values. For older silicon process technologies (i.e., Intel® Core™2 Duo

mobile processors on 65nm process), it is possible to simplify the voltage/current and

temperature relationships by treating the substrate transistor as though it were a

simple diffusion diode. In this case, the assumption is that the beta of the transistor

does not impact the calculated temperature values. The resultant “diode” model

essentially predicts a quasi linear relationship between the base/emitter voltage

differential of the PNP transistor and the applied temperature (one of the

proportionality constants in this relationship is processor specific, and is known as the

diode ideality factor). Realization of this relationship is accomplished with the SMBus

thermal sensor that is connected to the transistor.

The quad-core processor, however, is built on Intel’s advanced 45-nm processor

technology. Due to this new highly advanced processor technology, it is no longer

possible to model the substrate transistor as a simple diode. To accurately calculate

silicon temperature one must use a full bi-polar junction transistor-type model. In this

model, the voltage/current and temperature characteristics include an additional

process dependant parameter which is known as the transistor “beta”. System

designers should be aware that the current thermal sensors on Santa Rosa platforms

may not be configured to account for “beta” and should work with their SMB thermal

sensor vendors to ensure they have a part capable of reading the thermal diode in BJT

model.

Offset between the thermal diode-based temperature reading and the Intel Thermal

Monitor reading may be characterized using the Intel Thermal Monitor’s automatic

mode activation of the thermal control circuit. This temperature offset must be taken

into account when using the processor thermal diode to implement power management

events. This offset is different than the diode Toffset value programmed into the

processor Model-Specific Register (MSR).

Table 17 to Table 18 provide the diode interface and transistor model specifications.

68

Datasheet

Thermal Specifications and Design Considerations

Table 17.

Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

A24

B25

T2

Thermal diode anode

Thermal diode cathode

THERMDA_2

THERMDC_2

Thermal diode anode of the second die

Thermal diode cathode of the second die

V3

Table 18.

Thermal Diode Parameters Using Transistor Model

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I_FW

I_E

Forward Bias Current

Emitter Current

5

—

200

μA

1

n_Q

Transistor Ideality

0.997

0.1

3.0

1.001

0.4

1.008

0.5

2, 3, 4

2, 3

2

Beta

R_T

Series Resistance

4.5

7.0

Ω

NOTES:

1.

2.

3.

4.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Characterized across a temperature range of 50-100°C.

Not 100% tested. Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

/n

I

_C= I_S* (e ^qVBE ^kT–1)

Q

where I_S= saturation current, q = electronic charge, V_BE= voltage across the transistor

base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute

temperature (Kelvin).

5.1.2

Intel® Thermal Monitor

The Intel® Thermal Monitor helps control the processor temperature by activating the

TCC (Thermal Control Circuit) when the processor silicon reaches its maximum

operating temperature. The temperature at which the Intel Thermal Monitor activates

the TCC is not user configurable. Bus traffic is snooped in the normal manner and

interrupt requests are latched (and serviced during the time that the clocks are on)

while the TCC is active.

With a properly designed and characterized thermal solution, it is anticipated that the

TCC would only be activated for very short periods of time when running the most

power-intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be minor and hence not detectable. An under-

designed thermal solution that is not able to prevent excessive activation of the TCC in

the anticipated ambient environment may cause a noticeable performance loss and

may affect the long-term reliability of the processor. In addition, a thermal solution that

is significantly under designed may not be capable of cooling the processor even when

the TCC is active continuously.

The Intel Thermal Monitor controls the processor temperature by modulating (starting

and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep

Technology transition when the processor silicon reaches its maximum operating

Datasheet

69

Thermal Specifications and Design Considerations

temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic

mode and on-demand mode. If both modes are activated, automatic mode takes

precedence.

There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal

Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the

processor. After automatic mode is enabled, the TCC will activate only when the

internal die temperature reaches the maximum allowed value for operation.

When TM1 is enabled and a high temperature situation exists, the clocks will be

modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times

are processor speed-dependent and will decrease linearly as processor core frequencies

increase. Once the temperature has returned to a non-critical level, modulation ceases

and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid

active/inactive transitions of the TCC when the processor temperature is near the trip

point. The duty cycle is factory configured and cannot be modified. Also, automatic

mode does not require any additional hardware, software drivers, or interrupt handling

routines. Processor performance will be decreased by the same amount as the duty

cycle when the TCC is active.

When TM2 is enabled and a high temperature situation exists, the processor will

perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the

processor temperature drops below the critical level, the processor will make an

Enhanced Intel SpeedStep Technology transition to the last requested operating point.

Intel recommends TM1 and TM2 be enabled on the processors.

TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in

the auto-throttle MSR, TM2 takes precedence over TM1. However, if Force TM1 over

TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below

the maximum operating temperature, then TM1 will also activate to help cool down the

processor.

If a processor load-based Enhanced Intel SpeedStep Technology transition (through

MSR write) is initiated when a TM2 period is active, there are two possible results:

1. If the processor load-based Enhanced Intel SpeedStep Technology transition target

frequency is higher than the TM2 transition-based target frequency, the processor

load-based transition will be deferred until the TM2 event has been completed.

2. If the processor load-based Enhanced Intel SpeedStep Technology transition target

frequency is lower than the TM2 transition-based target frequency, the processor

will transition to the processor load-based Enhanced Intel SpeedStep Technology

target frequency point.

The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal

Monitor control register is written to a 1, the TCC will be activated immediately

independent of the processor temperature. When using on-demand mode to activate

the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the

same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is

fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be

programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.

On-demand mode may be used at the same time automatic mode is enabled, however,

if the system tries to enable the TCC via on-demand mode at the same time automatic

mode is enabled and a high temperature condition exists, automatic mode will take

precedence.

An external signal, PROCHOT# (processor hot) is asserted when the processor detects

that its temperature is above the thermal trip point. Bus snooping and interrupt

latching are also active while the TCC is active.

70

Datasheet

Thermal Specifications and Design Considerations

Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also

includes one ACPI register, one performance counter register, three MSR, and one I/O

pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal

Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt

upon the assertion or deassertion of PROCHOT#.

PROCHOT# will not be asserted when the processor is in the Stop Grant,

Sleep, and Deep Sleep low power states, hence the thermal diode reading

must be used as a safeguard to maintain the processor junction temperature

within maximum specification. If the platform thermal solution is not able to

maintain the processor junction temperature within the maximum specification, the

system must initiate an orderly shutdown to prevent damage. If the processor enters

one of the above low power states with PROCHOT# already asserted, PROCHOT# will

remain asserted until the processor exits the low power state and the processor

junction temperature drops below the thermal trip point.

If Thermal Monitor automatic mode is disabled, the processor will be operating out of

specification. Regardless of enabling the automatic or on-demand modes, in the event

of a catastrophic cooling failure, the processor will automatically shut down when the

silicon has reached a temperature of approximately 125 °C. At this point the

THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor

activity and does not generate any bus cycles. When THERMTRIP# is asserted, the

processor core voltage must be shut down within the time specified in Chapter 3.

In all cases the Intel Thermal Monitor feature must be enabled for the processor to

remain within specification.

5.1.3

Digital Thermal Sensor

The processor also contains an on-die Digital Thermal Sensor (DTS) that can be read

via an MSR (no I/O interface). Each core of the processor will have a unique digital

thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the

preferred method of reading the processor die temperature since it can be located

much closer to the hottest portions of the die and can thus more accurately track the

die temperature and potential activation of processor core clock modulation via the

Thermal Monitor. The DTS is only valid while the processor is in the normal operating

state (the Normal package level low power state).

Unlike traditional thermal devices, the DTS outputs a temperature relative to the

maximum supported operating temperature of the processor (T_J,max). It is the

responsibility of software to convert the relative temperature to an absolute

temperature. The temperature returned by the DTS will always be at or below T_J,max

.

Catastrophic temperature conditions are detectable via an Out Of Specification status

bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating

out of specification and immediate shutdown of the system should occur. The processor

operation and code execution is not ensured once the activation of the Out of

Specification status bit is set.

The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1/TM2)

trigger point. When the DTS indicates maximum processor core temperature has been

reached, the TM1 or TM2 hardware thermal control mechanism will activate. The DTS

and TM1/TM2 temperature may not correspond to the thermal diode reading since the

thermal diode is located in a separate portion of the die and there is a thermal gradient

between the individual core DTS. Additionally, the thermal gradient from DTS to

thermal diode can vary substantially due to changes in processor power, mechanical

and thermal attach, and software application. The system designer is required to use

the DTS to ensure proper operation of the processor within its temperature operating

specifications.

Datasheet

71

Thermal Specifications and Design Considerations

Changes to the temperature can be detected via two programmable thresholds located

in the processor MSRs. These thresholds have the capability of generating interrupts

via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software

Developer's Manuals for specific register and programming details.

5.2

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die

temperature has reached its maximum operating temperature. If TM1 or TM2 is

enabled, then the TCC will be active when PROCHOT# is asserted. The processor can

be configured to generate an interrupt upon the assertion or deassertion of

PROCHOT#. Refer to the an interrupt upon the assertion or deassertion of PROCHOT#.

Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for

specific register and programming details.

The processor implements a bi-directional PROCHOT# capability to allow system

designs to protect various components from overheating situations. The PROCHOT#

signal is bi-directional in that it can either signal when the processor has reached its

maximum operating temperature or be driven from an external source to activate the

TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal

protection of system components.

Only a single PROCHOT# pin exists at a package level of the processor. When any

core's thermal sensor trips, PROCHOT# signal will be driven by the processor package.

If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above its

TCC temperature trip point, and all cores will have their core clocks modulated. If TM2

is enabled then, regardless of which core(s) are above the TCC temperature trip point,

all cores will enter the lowest programmed TM2 performance state. It is important to

note that Intel recommends both TM1 and TM2 to be enabled.

When PROCHOT# is driven by an external agent, if only TM1 is enabled on all cores,

then all processor cores will have their core clocks modulated. If TM2 is enabled on all

cores, then all processor cores will enter the lowest programmed TM2 performance

state. It should be noted that Force TM1 on TM2, enabled via BIOS, does not have any

effect on external PROCHOT#. If PROCHOT# is driven by an external agent when TM1,

TM2, and Force TM1 on TM2 are all enabled, then the processor will still apply only

TM2.

PROCHOT# may be used for thermal protection of voltage regulators (VR). System

designers can create a circuit to monitor the VR temperature and activate the TCC

when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)

and activating the TCC, the VR will cool down as a result of reduced processor power

consumption. Bi-directional PROCHOT# can allow VR thermal designs to target

maximum sustained current instead of maximum current. Systems should still provide

proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case

of system cooling failure. The system thermal design should allow the power delivery

circuitry to operate within its temperature specification even while the processor is

operating at its TDP. With a properly designed and characterized thermal solution, it is

anticipated that bi-directional PROCHOT# would only be asserted for very short periods

of time when running the most power-intensive applications. An under-designed

thermal solution that is not able to prevent excessive assertion of PROCHOT# in the

anticipated ambient environment may cause a noticeable performance loss.

§

72

Datasheet


型号：	AW80581GH0416M
厂家：	INTEL
描述：	RISC Microprocessor, 64-Bit, 2000MHz, PPGA478 外围集成电路
文件：	总72页 (文件大小：1242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AW80581GH0416M [INTEL]

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