BN7C31BH [INTEL]
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER; CHMOS单片8位微控制器
| 型号： | BN7C31BH |
| 厂家： | 
INTEL |
| 描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80C31BH/80C51BH/87C51
MCS 51
É
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Automotive
Y
Y
Extended Automotive Temperature
Programmable Serial Port
b
a
Range ( 40 C to 125 C Ambient)
§
§
Y
TTL- and CMOS-Compatible Logic
Levels
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
High Performance CHMOS Process
Power Control Modes
Y
Y
Y
Y
Y
64K External Program Memory Space
64K External Data Memory Space
IDLE and POWER DOWN Modes
4 Kbyte On-Chip ROM/EPROM
128 x 8-bit RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
5 Interrupt Sources
ONCE Mode Facilitates System Testing
Available in 12 MHz and 16 MHz
Versions
Y
Available in PLCC and DIP Packages
Ý
(See Packaging Specification, Order 231369)
Quick-Pulse EPROM Programming
2-Level Program Memory Lock EPROM
Boolean Processor
The MCS 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are
É
functionally compatible with the standard MCS 51 HMOS microcontroller products. This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS. This combina-
tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set.
Like the MCS 51 HMOS microcontroller versions, the MCS 51 CHMOS microcontroller products have the
following features: 4 Kbytes of EPROM/ROM (87C51/80C51BH respectively); 128 bytes of RAM; 32 I/O lines;
two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial port; and on-chip
oscillator and clock circuitry. In addition, the MCS 51 CHMOS microcontroller products exhibit low operating
power, along with two software selectable modes of reduced activity for further power reductionÐIdle and
Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
The 87C51 is the EPROM version of the 80C51BH. It contains 4 Kbytes of on-chip program memory that can
be electrically programmed, and can be erased by exposure to ultraviolet light. The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm, by which the entire 4 Kbyte array can be programmed in about
12 seconds.
NOTICE:
This datasheet contains information on products in full production. Specifications within this datasheet
are subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
January 1995
Order Number: 270419-007
AUTOMOTIVE 80C31BH/80C51BH/87C51
270419–1
Figure 1. MCS 51 Microcontroller Architectural Block Diagram
É
2
AUTOMOTIVE 80C31BH/80C51BH/87C51
automotive temperature range option, operational
characteristics are guaranteed over the temperature
80C31BH/80C51BH/87C51
PRODUCT OPTIONS
b
a
range of 40 C to 125 C ambient.
§
§
Intel’s extended and automotive temperature range
products are designed to meet the needs of those
applications whose operating requirements exceed
commercial standards.
The automotive and extended temperature versions
of the MCS 51 microcontroller product families are
available with or without burn-in options as listed in
Table 1.
With the extended temperature range option, opera-
tional characteristics are guaranteed over the tem-
As shown in Figure 2, temperature, burn-in, and
package options are identified by a one- or two-letter
prefix to the part number.
b
a
perature range of 40 C to 85 C ambient. For the
§
§
270419–2
*Example:
AN80C51 indicates an automotive temperature range version of the 80C51 in a PLCC package with 4 Kbyte ROM
program memory.
Figure 2. MCS 51 Microcontroller Product Family Nomenclature
É
Table 1. Temperature Options
Operating
Temperature
Classification
Temperature
Designation
Burn-In
Options
Temperature
C Ambient
§
b
b
a
Extended
T
L
40 to 85
Standard
Extended
a
40 to 85
b
b
a
Automotive
A
B
40 to 125
Standard
Extended
a
40 to 125
3
AUTOMOTIVE 80C31BH/80C51BH/87C51
Diagrams are for pin reference only. Package sizes are not to scale.
270419–3
Pin (PDIP)
*EPROM only
**Do not connect reserved pins
270419–4
Pad (PLCC)
Figure 3. Pin Connections
current (I , on the datasheet) because of the inter-
IL
nal pullups.
PIN DESCRIPTION
V
: Supply voltage during normal, Idle, and Power
CC
Down operations.
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
V
SS
: Circuit ground.
V
:
V
Ð(EPROM PLCC only) secondary
SS1
SS1
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
ground. Provided to reduce ground bounce and im-
prove power supply bypassing.
NOTE:
This pin is not a substitute for the V pin (pin 22).
SS
current (I , on the data sheet) because of the inter-
IL
nal pullups.
For ROM and ROMless, pin 1 is reservedÐdo not
connect.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
@
address (MOVX DPTR). In this application it uses
strong internal pullups when emitting 1s.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emit-
ting 1s.
During accesses to external Data Memory that use
@
8-bit addresses (MOVX Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (I , on the datasheet) because of the pull-
IL
ups.
4
AUTOMOTIVE 80C31BH/80C51BH/87C51
Port 3 also serves the functions of various special
features of the MCS 51 microcontroller family, as
listed below:
Pin Name
Alternate Function
P3.0 RXD Serial Input Line
P3.1 TXD Serial Output Line
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
270419–5
Figure 4. Using the On-Chip Oscillator
P3.4
P3.5
P3.6
P3.7
T0
T1
Timer 0 External Input
Timer 1 External Input
WR External Data Memory Write Strobe
RD External Data Memory Read Strobe
Port 3 also receives some control signals for
EPROM programming and program verification.
RESET: Reset input. A logic high on this pin for two
machine cycles while the oscillator is running resets
the device. An internal pulldown resistor permits a
power-on reset to be generated using only an exter-
270419–6
Figure 5. External Clock Drive
nal capacitor to V
.
XTAL1: Input to the inverting oscillator amplifier and
input to the internal clock generating circuits.
CC
ALE/PROG (EPROM Only): Address Latch Enable
output signal for latching the low byte of the address
during accesses to external memory. This pin is also
the program pulse input (PROG) during EPROM pro-
gramming.
XTAL2: Output from the inverting oscillator amplifi-
er.
OSCILLATOR CHARACTERISTICS
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 4.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 5. There are no require-
ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data-
sheet must be observed.
PSEN: Program Store Enable is the Read strobe
to External Program Memory. When the
87C51/80C51BH is executing from Internal Program
Memory, PSEN is inactive (high). When the device is
executing code from External Program Memory,
PSEN is activated twice each machine cycle, except
that two PSEN activations are skipped during each
access to External Data Memory.
EA/V
:
strapped to in order to enable the
External Access enable. EA must be
V
IDLE MODE
PP
SS
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hard-
ware reset.
87C51/80C51BH to fetch code from External Pro-
gram Memory locations starting at 0000H up to
[
0FFFFH. Note, however, that if either of the Lock
Bits is programmed, the logic level at EA is internally
]
latched during reset. (EPROM only.)
EA must be strapped to V
execution.
for internal program
CC
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes pro-
gram execution, from where it left off, up to two ma-
chine cycles before the internal reset algorithm
takes control. On-chip hardware inhibits access to
V
PP
(EPROM Only): This pin also receives the
12.75V programming supply voltage (V ) during
PP
EPROM programming.
5
AUTOMOTIVE 80C31BH/80C51BH/87C51
Table 2. Status of the External Pins During Idle and Power Down
Program
Memory
Mode
Idle
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Idle
Power Down
Power Down
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook, and Applica-
tion Note AP-252, ‘‘Designing with the 80C51BH.’’
internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminat-
ed by reset, the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory.
DESIGN CONSIDERATIONS
At power on, the voltage on V and RST must
CC
come up at the same time for a proper start-up.
#
#
#
Before entering the Power Down mode the con-
tents of the Carry Bit and B.7 must be equal.
When the Idle mode is terminated by a hardware
reset, the device normally resumes program exe-
cution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to inter-
nal RAM in this event, but access to the port pins
in not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.
The only exit from Power Down is a hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated be-
fore V is restored to its normal operating level and
CC
must be held active long enough to allow the oscilla-
tor to restart and stabilize.
An external oscillator may encounter as much as
a 100 pF load at XTAL1 when it starts up. This is
due to interaction between the amplifier and its
feedback capacitance. Once the external signal
#
#
meets the V and V specifications the capaci-
IL
IH
tance will not exceed 20 pF.
For EPROM versions exposure to light when the
device is in operation may cause logic errors. For
this reason, it is suggested that an opaque label
be placed over the window when the die is ex-
posed to ambient light.
6
AUTOMOTIVE 80C31BH/80C51BH/87C51
When Lock Bit 1 is programmed, the logic level at
the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch
initializes to a random value, and holds that value
until reset is activated. It is necessary that the
latched value of EA be in agreement with the current
logic level at that pin in order for the device to func-
tion properly.
PROGRAM MEMORY LOCK
(EPROM Only)
The 87C51 contains two program memory lock
schemes: Encrypted Verify and Lock Bits.
Encrypted Verify: The 87C51 implements a 32-
byte EPROM array that can be programmed by the
customer, and which can then be used to encrypt
the program code bytes during EPROM verification.
The EPROM verification procedure is performed as
usual, except that each code byte comes out logical-
ly X-NORed with one of the 32 key bytes. The key
bytes are gone through in sequence. Therefore, to
read the ROM code, one has to know the 32 key
bytes in their proper sequence.
ONCE MODE
The ONCE (‘‘on-circuit emulation’’) mode facilitates
testing and debugging of systems using the 87C51
without the 87C51 having to be removed from the
circuit. The ONCE mode is invoked by:
1. Pull ALE low while the device is in reset and
PSEN is high;
Lock Bits: Also on the chip are two Lock Bits which
can be left unprogrammed (U) or can be pro-
grammed (P) to obtain the following additional fea-
tures:
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator cir-
cuit remains active. While the 87C51 is in this mode,
an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal
reset is applied.
Bit 1
U
Bit 2
U
Additional Features
none
P
U
Externally fetched code can not
#
access internal Program Memory.
Further programming disabled.
#
(Reserved for Future definition.)
U
P
P
P
Externally fetched code can not
#
access internal Program Memory.
Further programming disabled.
Program verification is disabled.
#
#
7
AUTOMOTIVE 80C31BH/80C51BH/87C51
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
b
a
Ambient Temperature Under Bias 40 C to 125 C
§
§
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
Voltage on EA/V Pin to V ÀÀÀÀÀÀÀ0V to 13.0V
a
PP
SS
b a
ÀÀ 0.5V to 6.5V
Voltage on Any Other Pin to V
SS
I
per I/O pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
OL
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(Based on package heat transfer limitations, not de-
vice power consumption).
a
Typical Junction Temperature (T ) ÀÀÀÀÀÀÀÀ 135 C
§
J
a
(Based upon ambient temperature at 125 C)
§
Typical Thermal Resistance Junction-to-Ambient
(i ):
JA
PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75 C/W
§
PLCCÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46 C/W
§
DC CHARACTERISTICS:
e b
a
40 C to 125 C; V
e
e
g
g
(T
A
5V 10% (5V 20% EPROM Only); V
0V)
§
§
CC
SS
Max
(87C51/80C51BH)
Test
Conditions
Symbol
Parameter
Min
Typ(1)
Unit
b
b
b
V
V
V
V
V
V
V
Input Low Voltage (Except EA)
0.5
0.2 V
0.2 V
0.25
0.45
V
V
IL
CC
Input Low Voltage to EA
0
IL1
IH
CC
a
a
0.5
Input High Voltage (Except XTAL1, RST) 0.2V
1.0
V
V
V
CC
CC
a
a
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1, 2, 3)
Output Low Voltage (Port 0, ALE, PSEN)
0.7 V
0.1
0.5
V
IH1
OL
OL1
OH
CC
CC
(7)
(2)
e
e
0.45
0.45
V
I
I
I
I
I
I
1.6 mA
OL
OL
OH
OH
OH
OH
(7)
(2)
3.2 mA
V
e b
e b
e b
e b
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
2.4
V
60 mA
0.9 V
CC
V
10 mA
V
OH1
Output High Voltage (Port 0 in
External Bus Mode)
2.4
0.9 V
V
800 mA
(3)
80 mA
V
CC
b
e
I
I
Logical 0 Input Current (Ports 1, 2, 3)
75
mA
mA
V
0.45 V
(4)
IL
IN
b
Logical 1-to-0 transition current
(Ports 1, 2, 3)
750
TL
e
g
I
I
Input Leakage Current (Port 0)
Power Supply Current:
10
mA
V
V
or V
IL IH
LI
IN
CC
(5)
@
Active Mode 12 MHz
11.5
1.3
3
25/20
6/5
100/75
mA
mA
mA
(5)
(6)
@
Idle Mode 12 MHz
Power Down Mode
e
2.2V to 5.5V
V
CC
RRST
CIO
Internal Reset Pulldown Resistor
Pin Capacitance
50
300
KX
10
pF
NOTES:
1. ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V s of ALE and Ports
OL
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
l
to-0 transitions during bus operations. In the worst cases (capacitive loading
100pF), the noise pulse on the ALE pin may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
3. Capacitive loading on Ports 0 and 2 may cause the V
specification when the address bits are stabilizing.
on ALE and PSEN to momentarily fall below the 0.9 V
CC
OH
8
AUTOMOTIVE 80C31BH/80C51BH/87C51
NOTES: (Continued)
4. Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V is approximately 2V.
IN
5. ICCMAX at other frequencies is given by:
e
e
c
c
a
a
a
Active Mode: 87C51
ICCMAX
0.94
1.47
FREQ
FREQ
3.81
13.71
2.36
80Cx1BH ICCMAX
c
e
Idle Mode:
ICCMAX
0.14
FREQ
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 6.
6. See Figures 7 through 10 for I test conditions. Minimum V for Power Down is 2.0V.
7. Under steady state (non-transient) conditions, I must be externally limited as follows:
CC
CC
OL
Maximum I per port pin:
OL
Maximum I per 8-bit port
10 mA
OL
Port 0:
Ports 1, 2, and 3:
Maximum total I for all output pins:
26 mA
15 mA
71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater
OL OL
than the listed test conditions.
270419–10
Figure 8. I Test Condition, Idle Mode.
CC
All other pins are disconnected.
270419–7
Figure 6. I vs. FREQ. Valid only
CC
within frequency specifications of the
device under test.
270419–11
Figure 9. I Test Condition, Power Down
CC
Mode. All other pins are disconnected.
270419–8
Figure 7. I Test Condition, Active Mode.
CC
All other pins are disconnected.
270419–9
Figure 10. Clock Signal Waveform for I tests in Active and Idle Modes.
CC
e
e
5 ns.
T
T
CHCL
CLCH
9
AUTOMOTIVE 80C31BH/80C51BH/87C51
EXPLANATION OF THE AC SYMBOLS
L:Logic level LOW, or ALE.
P:PSEN.
Q:Output data.
R:RD signal.
T:Time.
Each timing symbol has 5 characters. The first char-
acter is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
V:Valid.
W:WR signal.
X:No longer a valid logic level.
Z:Float.
A:Address.
C:Clock.
For example,
D:Input data.
H:Logic level HIGH.
I:Instruction (program memory contents).
e
e
T
AVLL
T
LLPL
Time from Address Valid to ALE Low.
Time from ALE Low to PSEN Low.
e b
0V; Load Capacitance for Port 0, ALE, and PSEN
a
e
CC
g
g
AC CHARACTERISTICS: (T
e
Outputs
40 C to 125 C; V
5V 10% (5V 20% EPROM Only);
e
100 pF; Load Capacitance for All Other
§
§
A
V
SS
e
80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
12 MHz Osc
Variable Oscillator
Symbol
Parameter
Units
Min
Max
Min
Max
1/T
Oscillator Frequency
87C51/80C51BH/80C31BH
MHz
CLCL
3.5
12–16
b
CLCL
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ALE Pulse Width
127
28
2T
40
55
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
b
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr In
ALE Low to PSEN Low
PSEN Pulse Width
T
T
AVLL
LLAX
LLIV
CLCL
CLCL
b
48
b
b
224
135
4T
3T
110
115
CLCL
b
43
T
40
LLPL
CLCL
b
CLCL
205
3T
45
PLPH
PLIV
PSEN Low to Valid Instr In
Input Instr Hold After PSEN
Input Instr Float After PSEN
Address Valid to Valid Instr In
PSEN Low to Address Float
RD Pulse Width
CLCL
0
0
PXIX
b
b
59
312
10
T
CLCL
25
PXIZ
5T
CLCL
105
AVIV
10
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
b
b
400
400
6T
6T
100
100
CLCL
CLCL
WR Pulse Width
b
RD Low to Valid Data In
Data Hold After RD High
Data Float After RD High
ALE Low to Valid Data In
Address Valid to Valid Data In
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
RD or WR High to ALE High
252
5T
CLCL
165
0
0
b
97
2T
70
CLCL
b
517
585
300
8T
150
165
CLCL
CLCL
b
9T
b
a
50
200
203
23
3T
50
130
60
3T
CLCL
CLCL
b
b
b
4T
T
CLCL
CLCL
CLCL
33
T
50
0
0
b
a
40
43
123
T
40
T
CLCL
CLCL
10
AUTOMOTIVE 80C31BH/80C51BH/87C51
EXTERNAL PROGRAM MEMORY READ CYCLE
270419–12
EXTERNAL DATA MEMORY READ CYCLE
270419–13
EXTERNAL DATA MEMORY WRITE CYCLE
270419–14
11
AUTOMOTIVE 80C31BH/80C51BH/87C51
EXTERNAL CLOCK DRIVE
EXTERNAL CLOCK DRIVE WAVEFORM
Symbol
1/T
Parameter
Min Max Units
Oscillator Frequency 3.5 12 MHz
3.5 16
CLCL
T
T
T
T
High Time
Low Time
Rise Time
Fall Time
20
20
ns
ns
ns
ns
CHCX
270419–17
CLCX
CLCH
CHCL
20
20
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
12 MHz
Oscillator
Variable
Oscillator
Symbol
Parameter
Units
Min
1.0
700
50
Max
Min
12T
Max
T
T
T
T
T
Serial Port Clock Cycle Time
ms
ns
ns
ns
ns
XLXL
CLCL
b
133
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
10T
QVXH
XHQX
XHDX
XHDV
CLCL
b
2T
117
CLCL
0
0
b
133
700
10T
CLCL
SHIFT REGISTER MODE TIMING WAVEFORMS
270419–15
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270419–16
270419–18
For timing purposes a port pin is no longer floating when a 100
mV change from load voltage occurs, and begins to float when a
100 mV change from the loaded V /V level occurs. I /I
b
AC inputs during testing are driven at V
CC
0.5 for a Logic ‘‘1’’
and 0.45V for a Logic ‘‘0.’’ Timing measurements are made at V
IH
OH OL OL OH
t
g
min for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.
IL
20 mA.
12
AUTOMOTIVE 80C31BH/80C51BH/87C51
to identify the device. The signature bytes identify
the device as an 87C51 manufactured by Intel.
EPROM CHARACTERISTICS
(EPROM Only)
Table 3 shows the logic levels for reading the signa-
ture byte, and for programming the Program Memo-
ry, the Encryption Table, and the Lock Bits. The cir-
cuit configuration and waveforms for Quick-Pulse
Programming are shown in Figures 11 and 12. Fig-
ure 13 shows the circuit configuration for normal
Program Memory verification.
The 87C51 is programmed by a modified Quick-
Pulse Programming algorithm. It differs from older
methods in the value used for V
(Programming
PP
Supply Voltage) and in the width and number of the
ALE/PROG pulses.
The 87C51 contains two signature bytes that can be
read and used by an EPROM programming system
Table 3. EPROM Programming Modes
ALE/
EA/
MODE
RST
PSEN
P2.7
P2.6
P3.7
P3.6
PROG
V
PP
Read Signature
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program Code Data
Verify Code Data
Pgm Encryption Table
Pgm Lock Bit 1
0*
1
V
PP
1
0*
0*
0*
V
PP
PP
PP
V
V
Pgm Lock Bit 2
NOTES:
e
e
e
e
‘‘1’’
‘‘0’’
Valid high for that pin
Valid low for that pin
g
5V 20% during programming and verification
V
V
12.75V
g
0.25V
PP
CC
*ALE/PROG receives 25 programming pulses while V
is held at 12.75V. Each programming pulse is low for 100 ms
PP
g
(
10 ms) and high for a minimum of 10 ms.
270419–19
Figure 11. Programming Configuration
13
AUTOMOTIVE 80C31BH/80C51BH/87C51
270419–20
Figure 12. PROG Waveforms
through 1FH, using the ‘‘Pgm Encryption Table’’ lev-
els. Don’t forget that after the Encryption Table is
programmed, verify cycles will produce only encrypt-
ed data.
Quick-Pulse Programming
(EPROM Only)
The setup for Microcontroller Quick-Pulse Program-
ming is shown in Figure 11. Note that the 87C51 is
running with a 4 to 6 MHz oscillator. The reason the
oscillator needs to be running is that the device is
executing internal address and program data trans-
fers.
To program the Lock Bits, repeat the 25-pulse pro-
gramming sequence using the ‘‘Pgm Lock Bit’’ lev-
els. After one Lock Bit is programmed, further pro-
gramming of the Code Memory and Encryption Ta-
ble is disabled. However, the other Lock Bit can still
be programmed.
The address of the EPROM location to be pro-
grammed is applied to Ports 1 and 2, as shown in
Figure 11. The code byte to be programmed into
that location is applied to Port 0. RST, PSEN, and
pins of Ports 2 and 3 specified in Table 3 are held at
the ‘‘Program Code Data’’ levels indicated in Table
2. Then ALE/PROG is pulsed low 25 times as
shown in Figure 12.
Note that the EA/V pin must not be allowed to go
level for any
PP
above the maximum specified V
PP
amount of time. Even a narrow glitch above that volt-
age level can cause permanent damage to the de-
vice. The V source should be well regulated and
PP
free of glitches and overshoot.
To program the Encryption Table, repeat the 25-
0
pulse programming sequence for addresses
270419–21
Figure 13. Program Verification
14
AUTOMOTIVE 80C31BH/80C51BH/87C51
Program Verification
(EPROM Only)
Program/Verify Algorithms
(EPROM Only)
If Lock Bit 2 has not been programmed, the on-chip
Program Memory can be read out for program verifi-
cation. The address of the Program Memory location
to be read is applied to Ports 1 and 2 as shown in
Figure 13. The other pins are held at the ‘‘Verify
Code Data’’ levels indicated in Table 3. The con-
tents of the addressed location will be emitted on
Port 0. External pullups are required on Port 0 for
this operation. Detailed timing specifications are
shown in later sections of this datasheet.
Any algorithm in agreement with the conditions list-
ed in Table 3, and which satisfies the timing specifi-
cations, is suitable.
Erasure Characteristics
(EPROM Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an ex-
tended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadver-
tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
If the Encryption Table has been programmed, the
data presented at Port 0 will be the Exclusive NOR
of the program byte with one of the encryption bytes.
The user will have to know the Encryption Table
contents in order to correctly decode the verification
data. The Encryption Table itself can not be read
out.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
2
ed dose of at least 15 W-sec/cm . Exposing the
Reading the Signature Bytes
(EPROM Only)
2
EPROM to an ultraviolet lamp of 12,000 mW/cm
The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1s state.
e
e
(030H)
(031H)
89H indicates manufactured by Intel
57H indicates 87C51
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
e
e
e
0V)
SS
g
5V 20%, V
(T
A
21 C to 27 C, V
§
Symbol
§
CC
Parameter
Min
Max
13.0
50
Units
V
V
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
12.5
PP
I
mA
PP
1/T
4
6
MHz
CLCL
T
T
T
T
T
T
T
T
T
T
T
T
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
48T
AVGL
CLCL
CLCL
CLCL
CLCL
CLCL
48T
48T
48T
48T
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQV
EHQZ
GHGL
P2.7 (ENABLE) High to V
PP
V
PP
V
PP
Setup to PROG Low
Hold After PROG
10
ms
ms
ms
10
90
PROG Width
110
Address to Data Valid
48T
CLCL
CLCL
CLCL
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to PROG Low
48T
48T
0
10
ms
15
AUTOMOTIVE 80C31BH/80C51BH/87C51
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
270419–22
*FOR PROGRAMMING CONDITIONS SEE FIGURE 11.
FOR VERIFICATION CONDITIONS SEE FIGURE 13.
DATASHEET REVISION SUMMARY
The following are the key differences between this datasheet and the -006 version:
1. The ‘‘preliminary’’ status was removed and replaced with production status (no label).
2. Trademark was updated.
The following are the key differences between the -005 and the -006 version of the datasheet:
1. Preliminary notice added to Title page.
2. Figure 3 Pin Connections the NC** pins are now Reserved** pins.
3. Figure 3 Pin Connections RST pin is now RESET pin.
4. RST pin description is now RESET pin description.
5. Figure 4 the capacitor values have been removed.
6. CERDIP part reference in the D.C. Characteristics section has been removed.
7. I
Max characteristics have been corrected to reflect test program conditions.
CC
8. T
and T
formulas changed to correlate 12 MHz timings.
RLDV
AVIV
The following are the key differences between the -004 and the -005 version of this datasheet:
1. Removed references to burn-in options in Table 1 and added explanation of burn-in offered. Removed
references to commercial temperatures.
b
2. Deleted reference to ‘‘ 1’’ designation 16 MHz.
3. Differentiated V for ROM/ROMless and EPROM.
CC
The following are the key differences between the -002 and the -003 version of this datasheet:
1. Changed the title to 80C31BH/80C51BH/87C51 CHMOS Single-Chip 8-Bit Microcontroller.
2. Added the pin count for each package version in Figure 2.
3. Removed references to burn-in options in Table 1.
4. Added external oscillator start-up design considerations.
The following are the key differences between the -002 and the -001 version of the 80C51BH datasheet:
1. Maximum I per I/O pin added.
OL
2. Note 7 on Maximum Current Specifications added to DC Characterstics.
3. Datasheet Revision Summary added.
16
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