BV80605002505AG/SLBPS [INTEL]
RISC Microprocessor, 64-Bit, 3060MHz, CMOS, PBGA1156;
| 型号： | BV80605002505AG/SLBPS |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 64-Bit, 3060MHz, CMOS, PBGA1156 |
| 文件： | 总94页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Intel Core™ i7-800 and i5-700
Desktop Processor Series
Datasheet – Volume 1
This is volume 1 of 2
July 2010
Document Number: 322164-004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE
FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.
®
Intel Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware and software, as well
as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with
the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of
implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host
OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/
technology/platform-technology/intel-amt/
Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology (Intel® Virtualization Technology
(Intel® VT-x) and Intel® Virtualization Technology for Directed I/O (Intel® VT-d)), a Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an
application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some
uses. For more information, see http://www.intel.com/technology/security
®
®
Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM) and, for some uses,
certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software
configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your
application vendor.
Warning: Altering clock frequency and/or voltage may (i) reduce system stability and useful life of the system and processor; (ii) cause the processor
and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system
data integrity. Intel has not tested, and does not warranty, the operation of the processor beyond its specifications.
* Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance
varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo
Boost Technology. For more information, see http://www.intel.com/technology/turboboost
Hyper-threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-enabled chipset, BIOS, and
operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which
processors support HT Technology, see http://www.intel.com/info/hyperthreading.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications
®
enabled for Intel 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for
more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
®
Enhanced Intel SpeedStep Technology for specified units of this processor available Q2/06. See the Processor Spec Finder at http://
processorfinder.intel.com or contact your Intel representative for more information.
Intel, Intel Core, Core Inside, Intel Speedstep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009-2010, Intel Corporation. All rights reserved.
2
Datasheet, Volume 1
Contents
1
Introduction..............................................................................................................9
1.1
Processor Feature Details ................................................................................... 11
1.1.1 Supported Technologies .......................................................................... 11
Interfaces ........................................................................................................ 11
1.2.1 System Memory Support......................................................................... 11
1.2.2 PCI Express* ......................................................................................... 12
1.2.3 Direct Media Interface (DMI).................................................................... 13
1.2.4 Platform Environment Control Interface (PECI)........................................... 13
Power Management Support ............................................................................... 14
1.3.1 Processor Core....................................................................................... 14
1.3.2 System................................................................................................. 14
1.3.3 Memory Controller.................................................................................. 14
1.3.4 PCI Express* ......................................................................................... 14
Thermal Management Support ............................................................................ 14
Package........................................................................................................... 14
Terminology ..................................................................................................... 15
Related Documents ........................................................................................... 17
1.2
1.3
1.4
1.5
1.6
1.7
2
Interfaces................................................................................................................ 19
2.1
System Memory Interface .................................................................................. 19
2.1.1 System Memory Technology Supported..................................................... 19
2.1.2 System Memory Timing Support............................................................... 20
2.1.3 System Memory Organization Modes......................................................... 20
2.1.3.1 Single-Channel Mode................................................................. 20
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode............ 21
2.1.4 Rules for Populating Memory Slots............................................................ 22
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA).......... 23
2.1.5.1 Just-in-Time Command Scheduling.............................................. 23
2.1.5.2 Command Overlap .................................................................... 23
2.1.5.3 Out-of-Order Scheduling............................................................ 23
2.1.6 System Memory Pre-Charge Power Down Support Details............................ 23
PCI Express* Interface....................................................................................... 24
2.2.1 PCI Express* Architecture ....................................................................... 24
2.2.1.1 Transaction Layer ..................................................................... 25
2.2.1.2 Data Link Layer ........................................................................ 25
2.2.1.3 Physical Layer .......................................................................... 25
2.2.2 PCI Express* Configuration Mechanism ..................................................... 26
2.2.3 PCI Express* Ports and Bifurcation ........................................................... 27
2.2.3.1 PCI Express* Bifurcated Mode .................................................... 27
Direct Media Interface (DMI)............................................................................... 27
2.3.1 DMI Error Flow....................................................................................... 27
2.3.2 Processor/PCH Compatibility Assumptions.................................................. 27
2.3.3 DMI Link Down ...................................................................................... 27
Platform Environment Control Interface (PECI)...................................................... 28
Interface Clocking ............................................................................................. 28
2.5.1 Internal Clocking Requirements................................................................ 28
2.2
2.3
2.4
2.5
3
Technologies ........................................................................................................... 29
3.1
Intel® Virtualization Technology.......................................................................... 29
3.1.1 Intel® VT-x Objectives............................................................................ 29
3.1.2 Intel® VT-x Features .............................................................................. 29
Datasheet, Volume 1
3
3.1.3 Intel® VT-d Objectives ............................................................................30
3.1.4 Intel® VT-d Features...............................................................................30
3.1.5 Intel® VT-d Features Not Supported..........................................................31
Intel® Trusted Execution Technology (Intel® TXT) .................................................31
Intel® Hyper-Threading Technology .....................................................................32
Intel® Turbo Boost Technology............................................................................32
3.2
3.3
3.4
4
Power Management .................................................................................................33
4.1
ACPI States Supported .......................................................................................33
4.1.1 System States........................................................................................33
4.1.2 Processor Core/Package Idle States...........................................................33
4.1.3 Integrated Memory Controller States.........................................................33
4.1.4 PCI Express* Link States .........................................................................34
4.1.5 Interface State Combinations ...................................................................34
Processor Core Power Management......................................................................34
4.2.1 Enhanced Intel® SpeedStep® Technology ..................................................34
4.2.2 Low-Power Idle States.............................................................................35
4.2.3 Requesting Low-Power Idle States ............................................................36
4.2.4 Core C-states.........................................................................................37
4.2.4.1 Core C0 State...........................................................................37
4.2.4.2 Core C1/C1E State ....................................................................37
4.2.4.3 Core C3 State...........................................................................38
4.2.4.4 Core C6 State...........................................................................38
4.2.4.5 C-State Auto-Demotion..............................................................38
4.2.5 Package C-States ...................................................................................38
4.2.5.1 Package C0 ..............................................................................40
4.2.5.2 Package C1/C1E........................................................................40
4.2.5.3 Package C3 State......................................................................40
4.2.5.4 Package C6 State......................................................................40
Integrated Memory Controller (IMC) Power Management.........................................41
4.3.1 Disabling Unused System Memory Outputs.................................................41
4.3.2 DRAM Power Management and Initialization ...............................................41
4.3.2.1 Initialization Role of CKE ............................................................41
4.3.2.2 Conditional Self-Refresh.............................................................41
4.3.2.3 Dynamic Power Down Operation..................................................42
4.3.2.4 DRAM I/O Power Management ....................................................42
PCI Express* Power Management ........................................................................42
4.2
4.3
4.4
5
6
Thermal Management ..............................................................................................43
Signal Description....................................................................................................45
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
System Memory Interface...................................................................................46
Memory Reference and Compensation ..................................................................48
Reset and Miscellaneous Signals ..........................................................................48
PCI Express* Based Interface Signals...................................................................49
DMI—Processor to PCH Serial Interface.................................................................49
PLL Signals .......................................................................................................50
Intel® Flexible Display Interface Signals ...............................................................50
JTAG/ITP Signals ...............................................................................................51
Error and Thermal Protection...............................................................................52
6.10 Power Sequencing .............................................................................................53
6.11 Processor Core Power Signals..............................................................................53
6.12 Graphics and Memory Core Power Signals.............................................................55
6.13 Ground and NCTF ..............................................................................................56
6.14 Processor Internal Pull Up/Pull Down ....................................................................56
4
Datasheet, Volume 1
7
Electrical Specifications........................................................................................... 57
7.1
7.2
Power and Ground Lands.................................................................................... 57
Decoupling Guidelines........................................................................................ 57
7.2.1 Voltage Rail Decoupling........................................................................... 57
Processor Clocking (BCLK[0], BCLK#[0]).............................................................. 58
7.3.1 PLL Power Supply................................................................................... 58
VCC Voltage Identification (VID) .......................................................................... 58
Reserved or Unused Signals................................................................................ 62
Signal Groups................................................................................................... 62
Test Access Port (TAP) Connection....................................................................... 65
Absolute Maximum and Minimum Ratings ............................................................. 65
DC Specifications .............................................................................................. 66
7.9.1 Voltage and Current Specifications............................................................ 66
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 73
7.10.1 DC Characteristics.................................................................................. 73
7.10.2 Input Device Hysteresis .......................................................................... 74
8
Processor Land and Signal Information ................................................................... 75
8.1
Processor Land Assignments............................................................................... 75
Datasheet, Volume 1
5
Figures
1-1 Intel® Core™ i7-800 and i5-700 Desktop Processor Series Platform Diagram....................10
2-1 Intel® Flex Memory Technology Operation ...................................................................21
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes...................22
2-3 PCI Express* Layering Diagram..................................................................................24
2-4 Packet Flow through the Layers..................................................................................25
2-5 PCI Express* Related Register Structures in Processor...................................................26
4-1 Idle Power Management Breakdown of the Processor Cores............................................35
4-2 Thread and Core C-State Entry and Exit ......................................................................36
4-3 Package C-State Entry and Exit ..................................................................................39
7-1 VCC Static and Transient Tolerance Loadlines................................................................69
7-2 Input Device Hysteresis.............................................................................................74
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) ..........................................................76
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................77
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) ..........................................................78
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................79
Tables
1-1 Intel® Core™ i7-800 and i5-700 Desktop Processor Series SKU
Supported Memory Summary....................................................................................11
1-2 Related Documents .................................................................................................17
2-1 Supported DIMM Module Configurations .....................................................................19
2-2 DDR3 System Memory Timing Support.......................................................................20
2-3 System Memory Pre-Charge Power Down Support .......................................................23
2-4 Processor Reference Clock Requirements....................................................................28
4-1 Processor Core/Package State Support.......................................................................33
4-2 G, S, and C State Combinations ................................................................................34
4-3 Coordination of Thread Power States at the Core Level.................................................36
4-4 P_LVLx to MWAIT Conversion....................................................................................37
4-5 Coordination of Core Power States at the Package Level...............................................39
4-6 Targeted Memory State Conditions ............................................................................42
6-1 Signal Description Buffer Types.................................................................................45
6-2 Memory Channel A ..................................................................................................46
6-3 Memory Channel B ..................................................................................................47
6-4 Memory Reference and Compensation........................................................................48
6-5 Reset and Miscellaneous Signals................................................................................48
6-6 PCI Express* Based Interface Signals ........................................................................49
6-7 DMI—Processor to PCH Serial Interface......................................................................49
6-8 PLL Signals.............................................................................................................50
6-9 Intel® Flexible Display Interface................................................................................50
6-10 JTAG/ITP................................................................................................................51
6-11 Error and Thermal Protection ....................................................................................52
6-12 Power Sequencing...................................................................................................53
6-13 Processor Core Power Signals ...................................................................................53
6-14 Graphics and Memory Power Signals..........................................................................55
6-15 Ground and NCTF....................................................................................................56
6-16 Processor Internal Pull Up/Pull Down..........................................................................56
7-1 VRD 11.1/11.0 Voltage Identification Definition...........................................................59
7-2 Market Segment Selection Truth Table for MSID[2:0]...................................................61
7-3 Signal Groups 1 ......................................................................................................63
7-4 Processor Absolute Minimum and Maximum Ratings.....................................................65
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications....................66
7-6 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications .....................67
7-7 VCC Static and Transient Tolerance ...........................................................................68
7-8 DDR3 Signal Group DC Specifications.........................................................................70
6
Datasheet, Volume 1
7-9 Control Sideband and TAP Signal Group DC Specifications ............................................ 71
7-10 PCI Express* DC Specifications................................................................................. 72
7-11 PECI DC Electrical Limits.......................................................................................... 73
8-1 Signals Not Used by the Intel® Core™ i7-800 and i5-700 Desktop Processor Series ......... 75
8-2 Processor Pin List by Pin Name ................................................................................. 80
Datasheet, Volume 1
7
Revision History
Revision
Number
Description
Date
September
2009
001
002
•
•
Initial release
®
January
2010
Added Intel Core™ i7-860S and i5-750S processors
®
003
004
•
•
Added Intel Core™ i7-875K and i7-880 processors
June 2010
July 2010
®
Added Intel Core™ i5-760 and i7-870S processors
§ §
8
Datasheet, Volume 1
Introduction
1 Introduction
The Intel® Core™ i7-800 and i5-700 desktop processor series are the next generation
of 64-bit, multi-core processors built on 45-nanometer process technology. Based on
the low-power/high-performance Intel microarchitecture, the processor is designed for
a two-chip platform, instead of the traditional three-chip platforms (processor, (G)MCH,
and ICH). The two-chip platform consists of a processor and Platform Controller Hub
(PCH) and enables higher performance, easier validation, and improved x-y footprint.
The Intel® 5 Series Chipset components for desktop are the PCH. The Intel® Core™ i7-
800 and i5-700 desktop processor series are designed for desktop platforms.
This document provides DC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, interface functional descriptions,
and additional feature information pertinent to the implementation and operation of the
processor on its respective platform.
Note:
Note:
Note:
Note:
Note:
Throughout this document, the Intel® Core™ i7-800 and i5-700 desktop processor
series may be referred to as “processor”.
Throughout this document, the Intel® Core™ i7-800 desktop processor series refers to
the Intel® Core™ i7-880, i7-875K, i7-870, i7-870S, i7-860, and i7-860S processors.
Throughout this document, the Intel® Core™ i5-700 desktop processor series refers to
the Intel® Core™ i5-760, i5-750, and i5-750S processor.
Throughout this document, the Intel® 5 series Chipset Platform Controller Hub may
also be referred to as “PCH”.
Some processor features are not available on all platforms. Refer to the processor
specification update for details.
Included in this family of processors is an integrated memory controller (IMC) and
integrated I/O (IIO) (such as PCI Express* and DMI) on a single silicon die. This single
die solution is known as a monolithic processor. For specific features supported for
individual Intel Core™ i7-800 and i5-700 desktop processor series SKUs, refer to the
Intel® Core™ i7-800 and i5-700 Desktop Processor Series Specification Update.
Figure 1-1 shows an example desktop platform block diagram.
Datasheet, Volume 1
9
Introduction
Figure 1-1. Intel® Core™ i7-800 and i5-700 Desktop Processor Series Platform Diagram
Quad Core CPU with
Integrated Memory Controller
DDR3 DIMMs
PCI Express* 1x16
OR
Discrete Graphics
(PEG)
2 Channels
Processor
(2 UDIMM/Channel)
PCI Express* 2x 8
DDR3 DIMMs
DMI
PECI
6
Ports
3 Gb/s
Serial ATA
Intel®
Management
Engine
14
Ports
USB 2.0
Intel® 5 Series Chipset
Intel® HD Audio
SMBUS 2.0
SPI Flash
SPI
8 x1 PCI Express*
2.0 Ports
PCI Express*
PCI
(2.5 GT/s)
PCI
FWH
Gigabit
Network Connection
TPM 1.2
LPC
Super I/O
Some technologies may not be enabled on all processor SKUs. Refer
to the Processor Specification Update for details.
GPIO
10
Datasheet, Volume 1
Introduction
1.1
Processor Feature Details
• Four cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data second-level cache (L2) for each core
• 8-MB shared instruction/data last-level cache (L3), shared among all cores
1.1.1
Supported Technologies
• Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
• Intel® Virtualization Technology (Intel® VT-x)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology
• Intel® 64 Architecture
• Execute Disable Bit
• Intel® Turbo Boost Technology
Note:
Some technologies may not be enabled on all processor SKUs. Refer to the processor
specification update for details.
1.2
Interfaces
1.2.1
System Memory Support
Table 1-1.
Intel® Core™ i7-800 and i5-700 Desktop Processor Series SKU
Supported Memory Summary
Transfer
# of
Channels
DIMMs/Ch
annel
Platform
Memory Type
Rate
Notes
(MT/s)
DDR3:
Desktop Intel 5 Series Chipset
Platform
Non-ECC
1 or 2
1 or 2
1066, 1333
1
Unbuffered
Notes:
1.
ECC DIMMs and mixing of non-ECC and ECC DIMMs are not supported.
System memory features include:
• Data burst length of eight for all memory organization modes
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Maximum memory bandwidth of 10.6 GB/s in single-channel mode or 21 GB/s in
dual-channel mode assuming DDR3 1333 MT/s
• 1-Gb and 2-Gb DDR3 DRAM technologies are supported.
• Using 2-Gb device technologies, the largest memory capacity possible is 16 GB for
UDIMMs (assuming Dual Channel Mode with a four dual rank unbuffered DIMM
memory configuration)
Datasheet, Volume 1
11
Introduction
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Command launch modes of 1n/2n
• Intel® Fast Memory Access (Intel® FMA)
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
1.2.2
PCI Express*
• The processor PCI Express* port(s) are fully-compliant with the PCI Express Base
Specification, Revision 2.0.
• Intel® Core™ i7-800 and i5-700 desktop processor series with Intel 5 Series
Chipset SKUs support:
— One 16-lane PCI Express port configurable to two 8-lane PCI Express ports
intended for Graphics Attach.
• PCI Express port 0 is mapped to PCI Device 3.
• PCI Express port 1 is mapped to PCI Device 5.
• The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x1 widths for a single PCI Express mode.
• 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported.
• Either port can be configured independently as 2.5 GT/s or 5.0 GT/s.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s for x16.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— PCI Express Port 0 -> PCI Express Port 1
— PCI Express Port 1 -> PCI Express Port 0
— DMI -> PCI Express Port 0
— DMI -> PCI Express Port 1
— PCI Express Port 1 -> DMI
— PCI Express Port 0 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
12
Datasheet, Volume 1
Introduction
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
• PCI Express reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Dynamic frequency change capability (2.5 GT/s - 5.0 GT/s)
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
1.2.3
Direct Media Interface (DMI)
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH
— DMI -> PCI Express Port 0 write traffic
— DMI -> PCI Express Port 1 write traffic
— DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI, and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage” and Full Swing “high-power/high-
voltage” modes
1.2.4
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between
processor and a PECI master, usually the PCH.
Datasheet, Volume 1
13
Introduction
1.3
Power Management Support
1.3.1
Processor Core
• Full support of ACPI C-states as implemented by the following processor C-states:
— C0, C1, C1E, C3, C6
• Enhanced Intel SpeedStep® Technology
1.3.2
1.3.3
System
• S0, S1, S3, S4, S5
Memory Controller
• Conditional self-refresh
• Dynamic power-down
1.3.4
PCI Express*
• L0s and L1 ASPM power management capability.
1.4
Thermal Management Support
• Digital Thermal Sensor
• Intel® Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Memory Thermal Throttling
• External Thermal Sensor
• Fan Speed Control with DTS
1.5
Package
• The processor socket type is noted as LGA 1156. The package is a 37.5 x 37.5 mm
Flip Chip Land Grid Array (FCLGA 1156).
14
Datasheet, Volume 1
Introduction
1.6
Terminology
Term
Description
DDR3
Third generation Double Data Rate SDRAM memory technology
Display Port*
DP
DMA
Direct Memory Access
DMI
Direct Media Interface
DTS
Digital Thermal Sensor
ECC
Error Correction Code
Enhanced Intel
Technology that provides power management capabilities.
®
SpeedStep Technology
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code attempts
to run in non-executable memory, the processor raises an error to the operating
system. This feature can prevent some classes of viruses or worms that exploit
buffer overrun vulnerabilities and can, thus, help improve the overall security of the
Execute Disable Bit
®
system. See the Intel 64 and IA-32 Architectures Software Developer's Manuals
for more detailed information.
Flip Chip Land Grid Array
FCLGA
Legacy component – Graphics Memory Controller Hub. Platforms using LGA 1156
processors do not use a (G)MCH component.
(G)MCH
The legacy I/O Controller Hub component that contains the main PCI interface, LPC
interface, USB2, Serial ATA, and other I/O functions. It communicates with the
legacy (G)MCH over a proprietary interconnect called DMI. Platforms using LGA
1156 processors do not use an ICH component.
ICH
IMC
Integrated Memory Controller
®
Intel 64 Technology
64-bit memory extensions to the IA-32 architecture.
®
®
®
Intel Hyper-Threading The processor supports Intel Hyper-Threading Technology (Intel HT Technology)
Technology
that allows an execution core to function as two logical processors.
®
Intel Turbo Boost Technology is a feature that allows the processor core to
®
Intel Turbo Boost
opportunistically and automatically run faster than its rated operating frequency if it
is operating below power, temperature, and current limits.
Technology
®
®
Intel TXT
Intel Trusted Execution Technology
®
®
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS) control,
for enabling I/O device virtualization. VT-d also brings robust security by providing
protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d.
®
Intel VT-d
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
®
Intel Virtualization
Technology
ITPM
IOV
Integrated Trusted Platform Module
I/O Virtualization
LCD
Liquid Crystal Display
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
LVDS
NCTF
Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity, audio
features, power management, manageability, security and storage features.
PCH
PECI
PEG
Platform Environment Control Interface
PCI Express* Graphics. External Graphics using PCI Express Architecture. A high-
speed serial interface whose configuration is software compatible with the existing
PCI specifications.
Datasheet, Volume 1
15
Introduction
Term
Processor
Description
The 64-bit multi-core component (package)
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Processor Core
A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DIMM.
Rank
SCI
System Control Interrupt. Used in ACPI protocol.
A non-operational state. The processor may be installed in a platform, in a tray, or
loose. Processors may be sealed in packaging or exposed to free air. Under these
conditions, processor landings should not be connected to any supply voltages,
have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is,
unsealed packaging or a device removed from packaging material), the processor
must be handled in accordance with moisture sensitivity labeling (MSL) as indicated
on the packaging material.
Storage Conditions
TAC
TDP
TLP
Thermal Averaging Constant
Thermal Design Power
Transaction Layer Packet
TOM
TTM
Top of Memory
Time-To-Market
V
V
V
V
Processor core power rail
CC
Processor ground
SS
L3 shared cache, memory controller, and processor I/O power rail
DDR3 power rail
TT
DDQ
VLD
x1
Variable Length Decoding
Refers to a Link or Port with one Physical Lane
Refers to a Link or Port with four Physical Lanes
Refers to a Link or Port with eight Physical Lanes
Refers to a Link or Port with sixteen Physical Lanes
x4
x8
x16
16
Datasheet, Volume 1
Introduction
1.7
Related Documents
Refer to the following documents for additional information.
Table 1-2.
Related Documents
Document
Document Number/ Location
®
Intel Core™ i7-800 and i5-700 Desktop Processor Series Datasheet,
http://download.intel.com/design
/processor/datashts/322165.pdf
Volume 2
®
Intel Core™ i7-800 i5-700 Desktop Processor Series Specification
www.intel.com/Assets/PDF/specu
pdate/322166.pdf
Update
®
Intel Core™ i7-800 and i5-700 Desktop Processor Series and LGA1156
http://download.intel.com/design
/processor/designex/322167.pdf
Socket Thermal and Mechanical Specifications and Design Guidelines
®
®
Intel 5 Series Chipset and Intel 3400 Series Chipset Datasheet
www.intel.com/Assets/PDF/datas
heet/322169
®
®
Intel 5 Series Chipset and Intel 3400 Series Chipset Thermal and
Mechanical Specifications and Design Guidelines
www.intel.com/Assets/PDF/desig
nguide/322171.pdf
Voltage Regulator-Down (VRD) 11.1 Design Guidelines
http://download.intel.com/design
/processor/designex/322172.pdf
Advanced Configuration and Power Interface Specification 3.0
PCI Local Bus Specification 3.0
http://www.acpi.info/
http://www.pcisig.com/specificati
ons
PCI Express Base Specification, Revision 2.0
DDR3 SDRAM Specification
http://www.pcisig.com
http://www.jedec.org
http://www.vesa.org
Display Port Specification
®
Intel 64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
http://www.intel.com/products/pr
ocessor/manuals/
§ §
Datasheet, Volume 1
17
Introduction
18
Datasheet, Volume 1
Interfaces
2 Interfaces
This chapter describes the interfaces supported by the processor.
2.1
System Memory Interface
2.1.1
System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two
independent, 64-bit wide channels. Refer to Section 1.2.1 for details on the type of
memory supported.
• Supported DIMM Types
— Unbuffered DIMMs—1066 MT/s (PC3-8500), and 1333 MT/s (PC3-10600)
• Desktop Intel 5 Series Chipset platform DDR3 DIMM Modules
— Raw Card A—Single Sided x8 unbuffered non-ECC
— Raw Card B—Double Sided x8 unbuffered non-ECC
— Raw Card C—Single Sided x16 unbuffered non-ECC
• DDR3 DRAM Device Technology
— Unbuffered—1-Gb and 2-Gb DDR3 DRAM Device technologies and addressing
are supported (as detailed in Table 2-1).
Table 2-1.
Supported DIMM Module Configurations
# of
Physical
Device
Ranks
# of
Row/Col
Address
Bits
# of
Raw
Card
Version
DRAM
Device
Technology
# of
DRAM
Devices
DIMM
Capacity
DRAM
Organization
Banks
Inside
DRAM
Page
Size
Desktop Intel 5 Series Chipset Platforms:
Unbuffered/Non-ECC Supported DIMM Module Configurations
A
B
C
1 GB
2 GB
1 Gb
1 Gb
2 Gb
1 Gb
128 M X 8
128 M X 8
256 M X 8
64 M X 16
8
16
16
4
1
2
2
1
14/10
14/10
15/10
13/10
8
8
8
8
8 K
8 K
8 K
8 K
4 GB
512 MB
Note: DIMM module support is based on availability and is subject to change.
Datasheet, Volume 1
19
Interfaces
2.1.2
System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1N indicates a new command may be issued every clock
and 2N indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Table 2-2.
DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
Unbuffered
DIMM CMD
Mode
Registered
DIMM CMD
Mode
t
(t
t
t
(t
CWL
CK
CL
CK
RCD
CK
RP
CK
Notes
)
(t
)
)
(t
)
7
8
8
9
7
8
8
9
7
8
8
9
1066
1333
6
See Note 1, 2, 3
See Note 1, 2, 3
1N Only
1N Only
4
4
4
4
7
10
10
10
Note:
1.
2.
3.
Two Un-buffered DIMM Memory Configurations = 2N Command Mode at 1066/1333 MHz
One Un-buffered DIMM Memory Configurations = 1N Command Mode at 1066/1333 MHz
Both Channel A and B will run at same Command Mode based on the slowest mode enabled relative to the
memory configurations populated in both channels. For example, if Channel A has both DIMM connectors
populated (2N CMD Mode) and Channel B has only one DIMM connector populated (1N CMD Mode) then 2N
CMD mode would be enabled for both channels.
4.
System Memory timing support is based on availability and is subject to change.
2.1.3
System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated, but not
both.
20
Datasheet, Volume 1
Interfaces
®
2.1.3.2
Dual-Channel Mode—Intel Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology mode. This mode combines the
advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel
Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The
symmetric zone starts at the lowest address in each channel and is contiguous until the
asymmetric zone begins or until the top address of the channel with the smaller
capacity is reached. In this mode, the system runs with one zone of dual-channel mode
and one zone of single-channel mode, simultaneously, across the whole memory array.
Figure 2-1. Intel® Flex Memory Technology Operation
C
T op of M em ory
N o n in terleaved
access
B
B
C
B
C H A
C H B
C
D u al ch an nel
in terleaved access
B
B
B
C H A
C H B
B – T he largest physical m em ory am ount of the sm aller size m em ory m odule
C – T he rem aining physical m em ory am ount of the larger size m em ory m odule
2.1.3.2.1
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note:
The DRAM device technology and width may vary from one channel to the other.
Datasheet, Volume 1
21
Interfaces
2.1.3.2.2
Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start at the bottom of Channel A and stay there until the end of the highest
rank in Channel A, and then addresses continue from the bottom of Channel B to the
top. Real-world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization; thus, in most
cases, bandwidth is limited to a single channel.
This mode is used when Intel Flex Memory Technology is disabled and both Channel A
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
Figure 2-2. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
Dual Channel Interleaved
(memory sizes must match)
Dual Channel Asymmetric
(memory sizes can differ)
CL
CL
Top of
Memory
Top of
Memory
CH. B
CH. A
CH. B
CH.A-top
DRB
CH. A
CH. B
CH. A
CH. B
CH. A
0
0
2.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel for unbuffered DIMMs For dual-channel modes, both channels
must have at least one DIMM connector populated and for single-channel mode only a
single-channel may have one or more DIMM connectors populated.
Note:
DIMM0 must always be populated within any memory configuration. DIMM0 is the
furthest DIMM within a channel and is identified by the CS#[1:0], ODT[1:0], and
CKE[1:0] signals.
22
Datasheet, Volume 1
Interfaces
®
2.1.5
Technology Enhancements of Intel Fast Memory Access
®
(Intel FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2
2.1.5.3
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6
System Memory Pre-Charge Power Down Support Details
The IMC supports and enables the following DDR3 DRAM Device pre-charge power
down DLL controls during a pre-charge power down.
• Slow Exit is where the DRAM device DLL is disabled after entering pre-charge
power down
• Fast Exit is where the DRAM device DLLs are maintained after entering pre-charge
power down
Table 2-3.
System Memory Pre-Charge Power Down Support
DIMM per Channel
Configuration
Precharge Power Down
Slow/Fast Exit
DIMM Type
One
Two
Unbuffered DIMM
Unbuffered DIMM
Slow Exit
Fast Exit
Datasheet, Volume 1
23
Interfaces
2.2
PCI Express* Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The number of PCI Express controllers available is dependent on the platform:
• Intel Core™ i7-800 and i5-700 desktop processor series with the desktop Intel 5
Series Chipset: 1 x16 PCI Express Graphics or 2x8 PCI Express Graphics are
supported.
2.2.1
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-
and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250-MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The PCI Express ports support 5.0 GT/s speed as well. Operating at
5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s
operation. When operating with more than one PCI Express controller, each controller
can be operating at either 2.5 GT/s or 5.0 GT/s.
The PCI Express architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-3 for the PCI Express Layering Diagram.
Figure 2-3. PCI Express* Layering Diagram
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
24
Datasheet, Volume 1
Interfaces
Figure 2-4. Packet Flow through the Layers
2.2.1.1
2.2.1.2
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of the Data Link Layer include link management, error detection, and
error correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to the Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets that are used for Link management functions.
2.2.1.3
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
Datasheet, Volume 1
25
Interfaces
2.2.2
PCI Express* Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
.
Figure 2-5. PCI Express* Related Register Structures in Processor
PCI Express
PCI
Express*
Device
Port 0
PCI-PCI
Bridge
representing
root PCI
Express port
(Device 5)
PCI-PCI
Bridge
representing
root PCI
Express port
(Device 3)
PCI
Compatible
Host Bridge
Device
PCI Express
Port 1
(Device 0)
PCI
Express*
Device
DMI
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (consisting of the first 256 B
of a logical device's configuration space) and an extended PCI Express region
(consisting of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using 32-
bit operations (32-bit aligned) only.
See the PCI Express Base Specification for details of both the PCI-compatible and PCI
Express Enhanced configuration mechanisms and transaction rules.
26
Datasheet, Volume 1
Interfaces
2.2.3
PCI Express* Ports and Bifurcation
The PCI Express interface on the processor is a single 16 lane (x16) port that can also
be configured at narrower widths. It may be bifurcated (refer to Table 6-5) and each
port may train to narrower widths. The PCI Express port is designed to be compliant
with the PCI Express Base Specification rev 2.0
2.2.3.1
PCI Express* Bifurcated Mode
When bifurcated, the signals that had previously been assigned to lanes 15:8 of the
single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary port. This
assignment applies whether the lane numbering is reversed or not. The controls for the
Secondary port and the associated virtual PCI-to-PCI bridge can be found in PCI Device
5. Refer to Table 6-5 for port bifurcation configuration settings and supported
configurations.
When the port is not bifurcated, Device 5 is hidden from the discovery mechanism used
in PCI enumeration, such that configuration of the device is neither possible nor
necessary.
2.3
Direct Media Interface (DMI)
DMI connects the processor and the PCH chip-to-chip. The DMI is similar to a four-lane
PCI Express supporting up to 1 GB/s of bandwidth in each direction.
Note:
Only DMI x4 configuration is supported.
2.3.1
DMI Error Flow
DMI can only generate SERR in response to errors—never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.3.2
2.3.3
Processor/PCH Compatibility Assumptions
The processor is compatible with the PCH and is not compatible with any previous
(G)MCH or ICH products.
DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
Datasheet, Volume 1
27
Interfaces
2.4
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between
processor and a PECI master, usually the PCH. The processor implements a PECI
interface to:
• Allow communication of processor thermal and other information to the PECI
master.
• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.
2.5
Interface Clocking
2.5.1
Internal Clocking Requirements
Table 2-4.
Processor Reference Clock Requirements
Reference Input Clocks
BCLK[0]/BCLK#[0]
PEG_CLK/PEG_CLK#
Input Frequency
Associated PLL
Processor/Memory
PCI Express/DMI
133 MHz
100 MHz
§ §
28
Datasheet, Volume 1
Technologies
3 Technologies
3.1
Intel® Virtualization Technology
Intel Virtualization Technology (Intel VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets. Intel Virtualization Technology (Intel VT-x) added hardware support in the
processor to improve the virtualization performance and robustness. Intel Virtualization
Technology for Directed I/O (Intel VT-d) adds chipset hardware implementation to
support and improve I/O virtualization performance and robustness.
Intel VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:
http://www.intel.com/products/processor/manuals/index.htm.
The Intel VT-d spec and other VT documents can be referenced at:
http://www.intel.com/technology/virtualization/index.htm.
®
3.1.1
Intel VT-x Objectives
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable
virtualized platforms. By using Intel VT-x, a VMM is:
• Robust—VMMs no longer need to use paravirtualization or binary translation. This
means that they will be able to run off-the-shelf OSs and applications without any
special steps.
• Enhanced—Intel VT enables VMMs to run 64-bit guest operating systems on IA
x86 processors.
• More reliable—Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
• More secure—The use of hardware transitions in the VMM strengthens the
isolation of VMs and further prevents corruption of one VM from affecting others on
the same system.
®
3.1.2
Intel VT-x Features
The processor core supports the following Intel VT-x features:
• Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization
— It eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as
TLBs)
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
Datasheet, Volume 1
29
Technologies
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS after an amount
of time specified by the VMM. The VMM sets a timer value before entering a
guest
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
®
3.1.3
3.1.4
Intel VT-d Objectives
The key Intel VT-d objectives are domain-based isolation and hardware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same operating system, or there can be multiple operating system
instances running on the same system—offering benefits such as system consolidation,
legacy migration, activity partitioning, or security.
®
Intel VT-d Features
The processor supports the following Intel VT-d features:
• 48-bit maximum guest address width and 36-bit maximum host address width for
non-isoch traffic, in UP profiles
• 39-bit maximum guest address width and 36-bit maximum host address width for
isoch (Intel High Definition Audio isoch) traffic
• Support for 4K page sizes only
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
— Support for fault collapsing based on Requester ID
• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
• Support for page-selective IOTLB invalidation
• Support for queue-based invalidation interface
• Support for Intel VT-d read prefetching/snarfing (such as, translations within a
cacheline are stored in an internal buffer for reuse for subsequent transactions)
• Support for ARI (Alternate Requester ID—a PCI SIG ECR for increasing the function
number count in a PCI Express device) to support IOV devices
30
Datasheet, Volume 1
Technologies
®
3.1.5
Intel VT-d Features Not Supported
The following features are not supported by the processor with Intel VT-d:
• No support for PCISIG endpoint caching (ATS)
• No support for interrupt remapping
• No support for advance fault reporting
• No support for super pages
• No support for 1 or 2 level page walks for isoch remap engine and 1, 2, or 3 level
walks for non-isoch remap engine
• No support for Intel VT-d translation bypass address range (such usage models
need to be resolved with VMM help in setting up the page tables correctly)
3.2
Intel® Trusted Execution Technology (Intel® TXT)
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel TXT platform helps to provide the authenticity of the controlling environment
such that those wishing to rely on the platform can make an appropriate trust decision.
The Intel TXT platform determines the identity of the controlling environment by
accurately measuring and verifying the controlling software.
Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:
• The launching of the Measured Launched Environment (MLE).
• The protection of the MLE from potential corruption.
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX).
The SMX interface includes the following functions:
• Measured/Verified launch of the MLE.
• Mechanisms to ensure the above measurement is protected and stored in a secure
location.
• Protection mechanisms that allow the MLE to control attempts to modify itself.
Datasheet, Volume 1
31
Technologies
3.3
Intel® Hyper-Threading Technology
The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology)
that allows an execution core to function as two logical processors. While some
execution resources such as caches, execution units, and buses are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled using the BIOS and
requires operating system support.
Intel recommends enabling Hyper-Threading Technology with Microsoft Windows
Vista*, Microsoft Windows* XP Professional/Windows* XP Home, and disabling Hyper-
Threading Technology using the BIOS for all previous versions of Windows operating
systems. For more information on Hyper-Threading Technology, see:
http://www.intel.com/products/ht/hyperthreading_more.htm.
3.4
Intel® Turbo Boost Technology
Intel® Turbo Boost Technology is a feature that allows the processor core to
opportunistically and automatically run faster than its rated operating frequency if it is
operating below power, temperature, and current limits. Maximum frequency is
dependent on the SKU and number of active cores. No special hardware support is
necessary for Intel Turbo Boost Technology. BIOS and the operating system can enable
or disable Intel Turbo Boost Technology.
Note:
Intel Turbo Boost Technology may not be available on all SKUs. Refer to the processor
specification update for details.
§ §
32
Datasheet, Volume 1
Power Management
4 Power Management
This chapter provides information on the following power management topics:
• ACPI States
• Processor Core
• IMC
• PCI Express*
4.1
ACPI States Supported
The ACPI states supported by the processor are described in this section.
4.1.1
System States
State
Description
G0/S0
Full On
Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported
by the processor).
G1/S3-Cold
G1/S4
G2/S5
G3
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
Soft off. All power lost (except wakeup on PCH). Total reboot.
Mechanical off. All power removed from system.
4.1.2
Processor Core/Package Idle States
Table 4-1.
Processor Core/Package State Support
State
Description
C0
Active mode, processor executing code.
AutoHALT state.
C1
C1E
AutoHALT state with lowest frequency and voltage operating point.
Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2
cache to the L3 shared cache. Clocks are shut off to the core.
C3
C6
Execution cores in this state save their architectural state before removing
core voltage.
4.1.3
Integrated Memory Controller States
State
Description
Power up
CKE asserted. Active mode.
Pre-charge Power down
Active Power down
Self-Refresh
CKE de-asserted (not self-refresh) with all banks closed.
CKE de-asserted (not self-refresh) with minimum one bank active.
CKE de-asserted using device self-refresh.
Datasheet, Volume 1
33
Power Management
4.1.4
PCI Express* Link States
State
Description
L0
Full on – Active transfer state.
L0s
L1
First Active Power Management low power state – Low exit latency.
Lowest Active Power Management - Longer exit latency.
Lowest power state (power-off) – Longest exit latency.
L3
4.1.5
Interface State Combinations
Table 4-2.
G, S, and C State Combinations
Processor
Global (G)
State
Sleep (S)
State
Processor
State
Core
System Clocks
Description
(C) State
G0
G0
G0
S0
S0
S0
C0
C1/C1E
C3
Full On
Auto-Halt
Deep Sleep
On
On
On
Full On
Auto-Halt
Deep Sleep
Deep Power
Down
G0
S0
C6
On
Deep Power Down
G1
G1
G2
G3
S3
S4
S5
NA
Power off
Power off
Power off
Power off
Power off
Power off
Power off
Power off
Off, except RTC
Off, except RTC
Off, except RTC
Power off
Suspend to RAM
Suspend to Disk
Soft Off
Hard off
4.2
Processor Core Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-
states have longer entry and exit latencies.
®
®
4.2.1
Enhanced Intel SpeedStep Technology
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps to an optimized voltage. This voltage is signaled by the VID[7:0] pins
to the voltage regulator. Once the voltage is established, the PLL locks on to the
target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the VID[7:0] pins.
34
Datasheet, Volume 1
Power Management
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per second are possible.
4.2.2
Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread level C-states are
available if Intel Hyper-Threading Technology is enabled.
Figure 4-1. Idle Power Management Breakdown of the Processor Cores
Thread 0 Thread 1
Thread 0 Thread 1
Core 0 State
Core 1 State
Processor Package State
Datasheet, Volume 1
35
Power Management
Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.
Figure 4-2. Thread and Core C-State Entry and Exit
MWAIT(C6),
P_LVL3 I/O Read
C0
MWAIT(C1), HLT
MWAIT(C1), HLT
(C1EEnabled)
MWAIT(C3),
P_LVL2 I/ O Read
C1
C1 E
C3
C6
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Table 4-3.
Coordination of Thread Power States at the Core Level
Thread 1
Processor Core
C-State
C0
C0
C0
C0
C0
C1
C3
C6
C0
C1
C3
C6
C0
C0
C0
1
1
1
C1
C1
C1
C1
C3
C3
C1
C3
C6
Thread 0
1
1
Note:
1. If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or higher.
4.2.3
Requesting Low-Power Idle States
The primary software interfaces for requesting low-power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
36
Datasheet, Volume 1
Power Management
Note:
The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows:
Table 4-4.
P_LVLx to MWAIT Conversion
P_LVLx
MWAIT(Cx)
Notes
P_LVL2
P_LVL3
MWAIT(C3)
MWAIT(C6)
C6. No sub-states allowed
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note:
When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF' feature that triggers a wakeup on
an interrupt, even if interrupts are masked by EFLAGS.IF.
4.2.4
Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (such that,
Thread 0 requests C1E while thread1 requests C3, resulting in a core C1E state).
See Table 4-3.
• A core transitions to C0 state when:
— an interrupt occurs.
— there is an access to the monitored address if the state was entered using an
MWAIT instruction.
• For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes
only that thread. However, since both threads are no longer at the same core C-
state, the core resolves to C0.
• For core C6, an interrupt coming into either thread wakes both threads into C0
state.
• Any interrupt coming into the processor package may wake any core.
4.2.4.1
4.2.4.2
Core C0 State
The normal operating state of a core where code is being executed.
Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 4.2.5.2.
Datasheet, Volume 1
37
Power Management
4.2.4.3
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
4.2.4.4
4.2.4.5
Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
C-State Auto-Demotion
In general, deeper C-states, such as C6, have long latencies and have higher energy
entry/exit costs. The resulting performance and energy penalties become significant
when the entry/exit frequency of a deeper C-state is high.
Therefore, incorrect or inefficient usage of deeper C-states may have a negative impact
on power consumption. To increase residency and improve power consumption in
deeper C-states, the processor supports C-state auto-demotion.
There are two C-State auto-demotion options:
• C6 to C3
• C6/C3 To C1
The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s
residency history. Requests to deeper C-states are demoted to shallower C-states when
the original request doesn't make sense from a performance or energy perspective.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
4.2.5
Package C-States
The processor supports C0, C1/C1E, C3, and C6 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor. The processor will put the DRAM into self-refresh in the package C3
and C6 states.
• For package C-states, the processor is not required to enter C0 before entering any
other C-state.
38
Datasheet, Volume 1
Power Management
The processor exits a package C-state when a break event is detected. If DRAM was
allowed to go into self-refresh in package C3 or C6 state, it will be taken out of self-
refresh. Depending on the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
Table 4-5 shows an example package C-state resolution for a dual-core processor.
Figure 4-3 summarizes package C-state transitions.
Table 4-5.
Coordination of Core Power States at the Package Level
Core 1
Package C-State
1
C0
C1
C3
C6
C0
C0
C0
C0
C0
C0
C0
C0
1
1
1
1
C1
C3
C6
C1
C1
C1
C1
C3
C3
C1
C3
C6
Core 0
1
1
Note:
1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.
Figure 4-3. Package C-State Entry and Exit
C0
C3
C1
C6
Datasheet, Volume 1
39
Power Management
4.2.5.1
4.2.5.2
Package C0
The normal operating state for the processor. The processor remains in the normal
state when at least one of its cores is in the C0 or C1 state or when the platform has
not granted permission to the processor to go into a low power state. Individual cores
may be in lower power idle states while the package is in C0.
Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low power state when:
• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.
The package enters the C1E state when:
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES.
No notification to the system occurs upon entry to C1/C1E.
4.2.5.3
Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform.
• The processor has requested the C6 state, but the platform only allowed C3.
In package C3-state, the L3 shared cache is snoopable.
4.2.5.4
Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 state, and the processor has been granted permission
by the platform.
In package C6 state, all cores save their architectural state and have their core
voltages reduced. The L3 shared cache is still powered and snoopable in this state.
40
Datasheet, Volume 1
Power Management
4.3
Integrated Memory Controller (IMC) Power
Management
The main memory is power managed during normal operation and in low power ACPI
Cx states.
4.3.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as, DIMM connector is
unpopulated, or is single-sided) is tristated. The benefits of disabling unused SM signals
are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and SCKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with a DIMM present,
the DIMM is not ensured to maintain data integrity.
4.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
4.3.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2
Conditional Self-Refresh
The processor conditionally places memory into self-refresh in the C3 and C6 low power
states.
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service. The target usage is shown in Table 4-6.
Datasheet, Volume 1
41
Power Management
Table 4-6.
Targeted Memory State Conditions
Mode
Memory State with External Graphics
C0, C1, C1E
C3, C6
Dynamic memory rank power down based on idle conditions.
Dynamic memory rank power down based on idle conditions
If there are no memory requests, then enter self-refresh. Otherwise, use dynamic memory
rank power down based on idle conditions.
S3
S4
Self Refresh Mode
Memory power down (contents lost)
4.3.2.3
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.
The processor core controller can be configured to put the devices in active power down
(CKE de-assertion with open pages) or precharge power down (CKE de-assertion with
all pages closed). Precharge power down provides greater power savings but has a
bigger performance impact, since all pages will first be closed before putting the
devices in power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
4.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM
control signals, such as CS#, CKE, and ODT for unpopulated DIMM slots.
The I/O buffer for an unused signal should be tristated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4
PCI Express* Power Management
• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L3 Ready state.
42
Datasheet, Volume 1
Thermal Management
5 Thermal Management
For thermal specifications and design guidelines, refer to the appropriate Thermal and
Mechanical Specifications and Design Guidelines (see Section 1.7).
§ §
Datasheet, Volume 1
43
Thermal Management
44
Datasheet, Volume 1
Signal Description
6 Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type.
Notations
Signal Type
I
Input Pin
Output Pin
O
I/O
Bi-directional Input/Output Pin
The signal description also includes the type of buffer used for the particular signal.
Table 6-1.
Signal Description Buffer Types
Signal
Description
PCI Express* interface signals. These signals are compatible with the PCI Express 2.0
Signaling Environment AC Specifications and are AC Coupled. The buffers are not
3.3 V tolerant. Refer to the PCI Express Specification.
PCI Express*
Intel Flexible Display Interface signals. These signals are compatible with PCI Express
2.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3 V tolerant.
FDI
Direct Media Interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3 V tolerant.
DMI
CMOS
DDR3
GTL
CMOS buffers. 1.1 V tolerant
DDR3 buffers: 1.5 V tolerant
Gunning Transceiver Logic signaling technology
Test Access Port signal
TAP
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
Analog
Ref
Voltage reference signal
Asynch
This signal is asynchronous and has no timing relationship with any reference clock.
Datasheet, Volume 1
45
Signal Description
6.1
System Memory Interface
Table 6-2.
Memory Channel A
Signal Name
SA_BS[2:0]
Description
Direction
Type
Bank Select: These signals define which banks are
selected within each SDRAM rank.
O
DDR3
CAS Control Signal: This signal is used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SDRAM
Commands.
SA_CAS#
O
DDR3
SDRAM Inverted Differential Clock: Channel A SDRAM
Differential clock signal-pair complement.
SA_CK#[1:0]
SA_CK#[3:2]
O
O
DDR3
DDR3
SDRAM Inverted Differential Clock: Channel A SDRAM
Differential clock signal-pair complement.
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair.
SA_CK[1:0]
SA_CK[3:2]
O
O
DDR3
DDR3
The crossing of the positive edge of SA_CKx and the
negative edge of its complement SA_CKx# are used to
sample the command and control signals on the SDRAM.
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair.
The crossing of the positive edge of SA_CKx and the
negative edge of its complement SA_CKx# are used to
sample the command and control signals on the SDRAM.
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up
Power-down SDRAM ranks
Place all SDRAM ranks into and out of self-refresh
during STR
SA_CKE[3:0]
O
DDR3
Chip Select: (1 per rank) These signals are used to select
particular SDRAM components during the active state.
There is one Chip Select for each SDRAM rank.
SA_CS#[3:0]
SA_CS#[7:4]
O
O
DDR3
DDR3
These signals are only used for processors and platforms
that have Registered DIMM support. These signals are
used to select particular SDRAM components during the
active state and SA_CS#[7:6] are used as the on die
termination for the first DIMM.
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes.
When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SA_DM[7:0] for every data byte lane.
SA_DM[7:0]
SA_DQ[63:0]
Note: These signals are not used by the Intel Core™ i7-
800 and i5-700 desktop processor series. They are
connected to V on the package.
SS
Data Bus: Channel A data signal interface to the SDRAM
data bus.
I/O
I/O
DDR3
DDR3
Data Strobes: SA_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SA_DQS[8:0] and its
SA_DQS#[8:0] during read and write transactions.
SA_DQS[8:0]
SA_DQS#[8:0]
SA_ECC_CB[7:0]
SA_MA[15:0]
SA_ODT[3:0]
Data Lines for ECC Check Byte.
I/O
O
DDR3
DDR3
DDR3
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
On Die Termination: Active Termination Control
O
RAS Control Signal: This signal is used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
SA_RAS#
SA_WE#
O
O
DDR3
DDR3
Write Enable Control Signal: This signal is used with
SA_RAS# and SA_CAS# (along with SA_CS#) to define
the SDRAM Commands.
46
Datasheet, Volume 1
Signal Description
Table 6-3.
Memory Channel B
Signal Name
Description
Direction
Type
Bank Select: These signals define which banks are
selected within each SDRAM rank.
SB_BS[2:0]
O
DDR3
CAS Control Signal: This signal is used with SB_RAS#
and SB_WE# (along with SB_CS#) to define the SDRAM
Commands.
SB_CAS#
O
DDR3
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement.
SB_CK#[1:0]
SB_CK#[3:2]
O
O
DDR3
DDR3
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement.
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
SB_CK[1:0]
SB_CK[3:2]
O
O
DDR3
DDR3
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up
Power-down SDRAM ranks
Place all SDRAM ranks into and out of self-refresh
during STR
SB_CKE[3:0]
O
DDR3
Chip Select: (1 per rank) These signals are used to select
particular SDRAM components during the active state.
There is one Chip Select for each SDRAM rank.
SB_CS#[3:0]
SB_CS#[7:4]
O
O
DDR3
DDR3
These signals are only used for processors and platforms
that have Registered DIMM support. These signals are
used to select particular SDRAM components during the
active state and SB_CS#[7:6] are used as the on die
termination for the first DIMM.
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes. When activated during writes, the
corresponding data groups in the SDRAM are masked.
There is one SB_DM[7:0] for every data byte lane.
SB_DM[7:0]
SB_DQ[63:0]
Note: These signals are not used by the Intel Core™ i7-
800 and i5-700 desktop processor series. They are
connected to V on the package.
SS
Data Bus: Channel B data signal interface to the SDRAM
data bus.
I/O
I/O
DDR3
DDR3
Data Strobes: SB_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SB_DQS[8:0] and its
SB_DQS#[8:0] during read and write transactions.
SB_DQS[8:0]
SB_DQS#[8:0]
SB_ECC_CB[7:0]
SB_MA[15:0]
SB_ODT[3:0]
Data Lines for ECC Check Byte.
I/O
O
DDR3
DDR3
DDR3
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
On-Die Termination: Active Termination Control.
O
RAS Control Signal: This signal is used with SB_CAS#
and SB_WE# (along with SB_CS#) to define the SDRAM
Commands.
SB_RAS#
SB_WE#
O
O
DDR3
DDR3
Write Enable Control Signal: This signal is used with
SB_RAS# and SB_CAS# (along with SB_CS#) to define
the SDRAM Commands.
Datasheet, Volume 1
47
Signal Description
6.2
Memory Reference and Compensation
Table 6-4.
Memory Reference and Compensation
Signal Name
Description
Direction
Type
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Channel A and B Output DDR3 DIMM DQ Reference Voltage.
O
I
Analog
Analog
SM_RCOMP[2:0]
System Memory Impedance Compensation.
6.3
Reset and Miscellaneous Signals
Table 6-5.
Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name
Description
Direction
Type
Configuration signals:
The CFG signals have a default value of 1 if not
terminated on the board.
•
CFG[1:0]: PCI Express Bifurcation
Intel Core™ i7-800 and i5-700 desktop
processor series:
11 = 1 x16 PCI Express
10 = 2 x8 PCI Express
01 = Reserved
00 = Reserved
CFG[17:0]
I
CMOS
•
CFG[2]: Reserved configuration land. A test point
may be placed on the board for this land.
•
•
CFG[3]: Reserved configuration land.
CFG[6:4]: Reserved configuration lands. A test
point may be placed on the board for this land.
•
CFG[17:7]: Reserved configuration lands. Intel
does not recommend a test point on the board for
this land.
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
COMP0
COMP1
COMP2
COMP3
FC_x
I
I
I
I
Analog
Analog
Analog
Analog
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
Table 7-9 for the termination requirement.
Future Compatibility (FC) signals are signals that are
available for compatibility with other processors. A test
point may be placed on the board for these lands.
External Thermal Sensor Input: If the system
temperature reaches a dangerously high value, this
signal can be used to trigger the start of system
memory throttling.
PM_EXT_TS#[1:0]
I
CMOS
CMOS
Power Management Sync: A sideband signal to
communicate power management status from the
platform to the processor.
PM_SYNC
I
This signal is an indication of the processor being reset.
Asynch
CMOS
RESET_OBS#
O
48
Datasheet, Volume 1
Signal Description
Table 6-5.
Reset and Miscellaneous Signals (Sheet 2 of 2)
Signal Name
Description
Direction
Type
Reset In: When asserted, this signal will asynchronously
reset the processor logic. This signal is connected to the
PLTRST# output of the PCH.
RSTIN#
I
CMOS
RESERVED. Must be left unconnected on the board.
Intel does not recommend a test point on the board for
this land.
RSVD
RESERVED/Non-Critical to Function: Pin for package
mechanical reliability. A test point may be placed on the
board for this land.
RSVD_NCTF
RESERVED-Test Point. A test point may be placed on the
board for this land.
RSVD_TP
DDR3 DRAM Reset: Reset signal from processor to
DRAM devices. One common to all channels.
SM_DRAMRST#
O
DDR3
6.4
PCI Express* Based Interface Signals
Table 6-6.
PCI Express* Based Interface Signals
Signal Name
PEG_ICOMPI
Description
Direction
Type
PCI Express Current Compensation.
PCI Express Current Compensation.
PCI Express Resistor Bias Control.
PCI Express Resistance Compensation.
PCI Express Receive Differential Pair.
I
I
I
I
Analog
Analog
Analog
Analog
PEG_ICOMPO
PEG_RBIAS
PEG_RCOMPO
PEG_RX[15:0]
PEG_RX#[15:0]
I
PCI Express
PCI Express
PEG_TX[15:0]
PEG_TX#[15:0]
PCI Express Transmit Differential Pair.
O
6.5
DMI—Processor to PCH Serial Interface
Table 6-7.
DMI—Processor to PCH Serial Interface
Signal Name
Description
Direction
Type
DMI_RX[3:0]
DMI_RX#[3:0]
DMI input from PCH: Direct Media Interface receive
differential pair.
I
DMI
DMI_TX[3:0]
DMI_TX#[3:0]
DMI output to PCH: Direct Media Interface transmit
differential pair.
O
DMI
Datasheet, Volume 1
49
Signal Description
6.6
PLL Signals
Table 6-8.
PLL Signals
Signal Name
Description
Direction
Type
BCLK[0]
Differential bus clock input to the processor.
I
I
Diff Clk
BCLK#[0]
BCLK[1]
BCLK#[1]
Differential bus clock input to the processor. Reserved
for possible future use.
Diff Clk
Diff Clk
BCLK_ITP
BCLK_ITP#
Buffered differential bus clock pair to ITP..
O
Differential PCI Express / DMI Clock In:
These pins receive a 100-MHz Serial Reference clock.
This clock is used to generate the clocks necessary for
the support of PCI Express. This also is the reference
PEG_CLK
PEG_CLK#
I
Diff Clk
®
clock for Intel Flexible Display Interface.
6.7
Intel® Flexible Display Interface Signals
Note:
The signals noted below as not being used are included for reference to define all LGA
1156 land locations. These signals will be used by future processors that are
compatible with LGA 1156 platforms.
Table 6-9.
Intel® Flexible Display Interface
Signal Name
Description
Direction
Type
®
Intel Flexible Display Interface Frame Sync—Pipe A.
FDI_FSYNC[0]
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
®
Intel Flexible Display Interface Frame Sync—Pipe B.
FDI_FSYNC[1]
FDI_INT
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
®
Intel Flexible Display Interface Hot Plug Interrupt.
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
®
Intel Flexible Display Interface Line Sync—Pipe A.
FDI_LSYNC[0]
FDI_LSYNC[1]
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
®
Intel Flexible Display Interface Line Sync—Pipe B.
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
®
Intel Flexible Display Interface Transmit Differential
Pair—Pipe A..
Note: These signals are not used by the processor.
They are connected to V on the package.
FDI_TX[3:0]
FDI_TX#[3:0]
SS
®
Intel Flexible Display Interface Transmit Differential
Pair—Pipe B.
FDI_TX[7:4]
FDI_TX#[7:4]
Note: These signals are not used by the processor.
They are connected to V on the package.
SS
50
Datasheet, Volume 1
Signal Description
6.8
JTAG/ITP Signals
Table 6-10. JTAG/ITP
Signal Name
Description
Direction
Type
Breakpoint and Performance Monitor Signals: Outputs
from the processor that indicate the status of
breakpoints and programmable counters used for
monitoring processor performance.
BPM#[7:0]
DBR#
I/O
GTL
DBR# is used only in systems where no debug port is
implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can
drive system reset.
O
PRDY# is a processor output used by debug tools to
determine processor debug readiness.
PRDY#
PREQ#
TCK
O
I
Asynch GTL
Asynch GTL
TAP
PREQ# is used by debug tools to request debug
operation of the processor.
TCK (Test Clock) provides the clock input for the
processor Test Bus (also known as the Test Access Port).
I
TDI (Test Data In) transfers serial test data into the
processor. TDI provides the serial input needed for JTAG
specification support.
TDI
I
I
TAP
TAP
TAP
TAP
TDI_M (Test Data In) transfers serial test data into the
processor. TDI_M provides the serial input needed for
JTAG specification support.
TDI_M
TDO
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for
JTAG specification support.
O
O
TDO_M (Test Data Out) transfers serial test data out of
the processor. TDO_M provides the serial output needed
for JTAG specification support.
TDO_M
TMS (Test Mode Select) is a JTAG specification support
signal used by debug tools.
TMS
I
I
TAP
TAP
TRST# (Test Reset) resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
TRST#
Datasheet, Volume 1
51
Signal Description
6.9
Error and Thermal Protection
Table 6-11. Error and Thermal Protection
Signal Name
Description
Direction
Type
Catastrophic Error: This signal indicates that the system
has experienced a catastrophic error and cannot continue
to operate. The processor will set this for non-recoverable
machine check errors or other unrecoverable internal
errors. Since this is an I/O pin, external agents are allowed
to assert this pin that will cause the processor to take a
machine check exception.
CATERR#
I/O
GTL
CATERR# is used for signaling the following types of errors:
•
•
Legacy MCERR: CATERR# is asserted for 16 BCLKs.
Legacy IERR: CATERR# remains asserted until warm or
cold reset.
PECI (Platform Environment Control Interface) is the serial
sideband interface to the processor and is used primarily
for thermal, power, and error management.
PECI
I/O
I/O
Asynch
PROCHOT# goes active when the processor temperature
monitoring sensor(s) detects that the processor has
reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit has
been activated, if enabled. This signal can also be driven to
the processor to activate the Thermal Control Circuit. This
signal does not have on-die termination and must be
terminated on the system board.
PROCHOT#
Asynch GTL
Processor Power Status Indicator: This signal is asserted
when maximum possible processor core current
consumption is less than 15 A. Assertion of this signal is an
indication that the VR controller does not currently need to
Asynch
CMOS
PSI#
be able to provide I above 15 A, and the VR controller
O
O
CC
can use this information to move to more efficient
operating point. This signal will de-assert at least 3.3 s
before the current consumption will exceed 15 A. The
minimum PSI# assertion and de-assertion time is 1 BCLK.
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal operating
temperature to ensure that there are no false trips. The
processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is
signaled to the system by the THERMTRIP# pin.
THERMTRIP#
Asynch GTL
52
Datasheet, Volume 1
Signal Description
6.10
Power Sequencing
Table 6-12. Power Sequencing
Signal Name
Description
Direction
Type
SKTOCC# (Socket Occupied): This signal will be pulled to
ground on the processor package. There is no connection
to the processor silicon for this signal. System board
designers may use this signal to determine if the
processor is present.
SKTOCC#
O
SM_DRAMPWROK processor input: This signal connects to
PCH DRAMPWROK.
Asynch
CMOS
SM_DRAMPWROK
TAPPWRGOOD
I
Power good for ITP. Indicates to the ITP when the TAP can
be accessed.
Asynch
CMOS
O
VCCPWRGOOD_0 and VCCPWRGOOD_1 (Power Good)
Processor Input: The processor requires these signals to
1
be a clean indication that V , V
, V , V
supplies
CC
CCPLL
TT
AXG
are stable and within their specifications and that BCLK is
stable and has been running for a minimum number of
cycles. These signals must then transition monotonically
to a high state. These signals can be driven inactive at
any time, but BCLK and power must again be stable
before a subsequent rising edge of VCCPWRGOOD_0 and
VCCPWRGOOD_1. These signals should be tied together
and connected to the CPUPWRGD output signal of the
PCH.
VCCPWRGOOD_0
VCCPWRGOOD_1
Asynch
CMOS
I
Note 1: These signals are not used by the processor.
They are no connect on the package.
The processor requires this input signal to be a clean
indication that the V power supply is stable and within
TT
specifications. 'Clean' implies that the signal will remain
low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until
they come within specification. The signal must then
transition monotonically to a high state. Note that it is not
valid for VTTPWRGOOD to be de-asserted while
Asynch
CMOS
VTTPWRGOOD
I
VCCPWRGOOD_0 and VCCPWRGOOD_1 are asserted.
6.11
Processor Core Power Signals
Table 6-13. Processor Core Power Signals (Sheet 1 of 2)
Signal Name
ISENSE
Description
Direction
Type
Current sense from VRD11.1 Compliant Regulator to the
processor core.
I
Analog
Processor core power supply. The voltage supplied to
these pins is determined by the VID pins.
VCC
PWR
PWR
VCC/Non-Critical to Function: Pin for package
mechanical reliability.
VCC_NCTF
VCC_SENSE and VSS_SENSE provide an isolated, low
impedance connection to the processor core voltage
and ground. They can be used to sense or measure
voltage near the silicon.
VCC_SENSE
Analog
Datasheet, Volume 1
53
Signal Description
Table 6-13. Processor Core Power Signals (Sheet 2 of 2)
Signal Name
Description
Direction
Type
VID[7:0] (Voltage ID) are used to support automatic
selection of power supply voltages (V ). Refer to the
CC
Voltage Regulator-Down (VRD) 11.1 Design Guidelines
for more information. The voltage supply for these
signals must be valid before the VR can supply V to
CC
the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID signals
become valid. The VR must supply the voltage that is
requested by the signals, or disable itself.
VID7 and VID6 should be tied separately to V using a
SS
1 k resistor (This value is latched on the rising edge of
VTTPWRGOOD).
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
I/O
CMOS
CSC[2:0]—Current Sense Configuration bits, for ISENSE
gain setting. See Voltage Regulator-Down (VRD) 11.1
Design Guidelines for gain setting information. This
value is latched on the rising edge of VTTPWRGOOD.
MSID[2:0] (Market Segment Identification) are used to
indicate the maximum platform capability to the
processor. A processor will only boot if the MSID[2:0]
pins are strapped to the appropriate setting (or higher)
on the platform (see Table 7-3 for MSID encodings).
MSID is used to help protect the platform by preventing
a higher power processor from booting in a platform
designed for lower power processors. MSID[2:0] are
latched on the rising edge of VTTPWRGOOD.
VCC_SENSE and VSS_SENSE provide an isolated, low
impedance connection to the processor core voltage
and ground. They can be used to sense or measure
voltage near the silicon.
VSS_SENSE
Analog
Analog
VTT_SENSE and VSS_SENSE_VTT provide an isolated,
low impedance connection to the processor V voltage
TT
VSS_SENSE_VTT
and ground. They can be used to sense or measure
voltage near the silicon.
Processor power for the memory controller, shared cache
and I/O (1.1 V).
VTT
PWR
The VTT_SELECT signal is used to select the correct V
voltage level for the processor. The processor will be
TT
VTT_SELECT
O
CMOS
configured to drive a low voltage level for VTT_SELECT.
VTT_SENSE and VSS_SENSE_VTT provide an isolated,
low impedance connection to the processor V voltage
TT
and ground. They can be used to sense or measure
voltage near the silicon.
VTT_SENSE
Analog
54
Datasheet, Volume 1
Signal Description
6.12
Graphics and Memory Core Power Signals
Note:
The signals noted below as not being used are included for reference to define all LGA
1156 land locations. These signals will be used by future processors that are
compatible with LGA 1156 platforms.
Table 6-14. Graphics and Memory Power Signals
Signal Name
Description
Direction
Type
Integrated graphics output signal to a VRD11.1 compliant
VR. When asserted this signal indicates that the
integrated graphics is in render suspend mode. This
signal is also used to control render suspend state exit
slew rate.
GFX_DPRSLPVR
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
Current Sense from an VRD11.1 compliant VR to the
integrated graphics.
GFX_IMON
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
GFX_VID[6:0] (Voltage ID) pins are used to support
automatic selection of nominal voltages (V
). These are
AXG
CMOS signals that are driven by the processor. The VID
code output by VID[6:0] and associated voltages are
given in Chapter 7.
GFX_VID[6:0]
Note: These signals are not used by the processor. They
are connected to V on the package.
TT
Integrated graphics output signal to integrated graphics
VR. This signal is used as an on/off control to
enable/disable the integrated graphics VR.
GFX_VR_EN
VAXG
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
Graphics core power supply.
Note: These signals are not used by the processor. They
are no connect on the package.
VAXG_SENSE and VSSAXG_SENSE provide an isolated,
low impedance connection to the VAXG voltage and
ground. They can be used to sense or measure voltage
near the silicon.
VAXG_SENSE
Note: This signal is not used by the processor. It is a no
connect on the package.
VCCPLL provides isolated power for internal processor
PLLs.
VCCPLL
VDDQ
PWR
PWR
Processor I/O supply voltage for DDR3.
VAXG_SENSE and VSSAXG_SENSE provide an isolated,
low impedance connection to the VAXG voltage and
ground. They can be used to sense or measure voltage
near the silicon.
VSSAXG_SENSE
Note: This signal is not used by the processor. It is
connected to V on the package.
SS
Datasheet, Volume 1
55
Signal Description
6.13
Ground and NCTF
Table 6-15. Ground and NCTF
Signal Name
Description
Direction
Type
VSS are the ground pins for the processor and should be
connected to the system ground plane.
VSS
GND
Corner Ground Connection: This land may be used to test
for connection to ground. A test point may be placed on
the board for this land. This land is considered Non-
Critical to Function.
CGC_TP_NCTF
6.14
Processor Internal Pull Up/Pull Down
Table 6-16. Processor Internal Pull Up/Pull Down
Pull Up/Pull
Signal Name
Down
Rail
Value
SM_DRAMPWROK
Pull Down
Pull Down
VSS
VSS
10–20 k
10–20 k
VCCPWRGOOD_0
VCCPWRGOOD_1
VTTPWRGOOD
BPM#[7:0]
TCK
Pull Down
Pull Up
Pull Up
Pull Up
Pull Up
Pull Up
Pull Up
Pull Up
Pull Up
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
10–20 k
44–55
44–55
44–55
44–55
1–5 k
TDI
TMS
TRST#
TDI_M
44–55
44–55
5–14 k
PREQ#
CFG[17:0]
§ §
56
Datasheet, Volume 1
Electrical Specifications
7 Electrical Specifications
7.1
Power and Ground Lands
The processor has VCC, VTT, VDDQ, VCCPLL, VAXG1, and VSS (ground) inputs for on-
chip power distribution. All power lands must be connected to their respective
processor power planes, while all VSS lands must be connected to the system ground
plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
The VCC lands must be supplied with the voltage determined by the processor Voltage
IDentification (VID) signals. Table 7-1 specifies the voltage level for the various VIDs.
7.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low- and full-power states. This
may cause voltages on power planes to sag below their minimum values, if bulk
decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors,
supply current during longer lasting changes in current demand (for example, coming
out of an idle condition). Similarly, capacitors act as a storage well for current when
entering an idle condition from a running condition. To keep voltages within
specification, output decoupling must be properly designed.
Caution:
Design the board to ensure that the voltage provided to the processor remains within
the specifications listed in Table 7-5. Failure to do so can result in timing violations or
reduced lifetime of the processor. For further information and design guidelines, refer
to the Voltage Regulator Down (VRD) 11.1 Design Guidelines.
7.2.1
Voltage Rail Decoupling
The voltage regulator solution needs to provide:
• bulk capacitance with low effective series resistance (ESR).
• a low interconnect resistance from the regulator to the socket.
• bulk decoupling to compensate for large current swings generated during power-
on, or low-power idle state entry/exit.
The power delivery solution must ensure that the voltage and current specifications are
met, as defined in Table 7-5.
1. These signals are not used by the processor. They are no connect on the package.
Datasheet, Volume 1
57
Electrical Specifications
7.3
Processor Clocking (BCLK[0], BCLK#[0])
The processor uses a differential clock to generate the processor core(s) operating
frequency, memory controller frequency, and other internal clocks. The processor core
frequency is determined by multiplying the processor core ratio by 133 MHz. Clock
multiplying within the processor is provided by an internal phase locked loop (PLL) that
requires a constant frequency input, with exceptions for Spread Spectrum Clocking
(SSC).
The processor maximum core frequency is configured during power-on reset by using
its manufacturing default value. This value is the highest core multiplier at which the
processor can operate. If lower maximum speeds are desired, the appropriate ratio can
be configured using the FLEX_RATIO MSR.
7.3.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 7-6 for DC
specifications.
7.4
VCC Voltage Identification (VID)
The VID specification for the processor is defined by the Voltage Regulator Down (VRD)
11.1 Design Guidelines. The processor uses eight voltage identification signals,
VID[7:0], to support automatic selection of voltages. Table 7-1 specifies the voltage
level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage
level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0]
= 11111111), or the voltage regulation circuit cannot supply the voltage that is
requested, the voltage regulator must disable itself. See the Voltage Regulator Down
(VRD) 11.1 Design Guidelines for further details. VID signals are CMOS push/pull
drivers. Refer to Table 7-9 for the DC specifications for these signals. The VID codes will
change due to temperature and/or current load changes to minimize the power of the
part. A voltage range is provided in Table 7-5. The specifications are set so that one
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in Table 7-5. The processor provides the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (VCC). This
will represent a DC shift in the loadline.
Note:
A low-to-high or high-to-low voltage state change will result in as many VID transitions
as necessary to reach the target core voltage. Transitions above the maximum
specified VID are not permitted. One VID transition occurs in 1.25 us. Table 7-1
includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be
maintained.
The VR used must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
Table 7-5 and Table 7-7. See the Voltage Regulator Down (VRD) 11.1 Design Guidelines
for further details.
Several of the VID signals (VID[5:3]/CSC[2:0] and VID[2:0]/MSID[2:0]) serve a dual
purpose and are sampled during reset. Refer to the signal description table in
Chapter 6 and Table 7-3 for further information.
58
Datasheet, Volume 1
Electrical Specifications
Table 7-1.
VRD 11.1/11.0 Voltage Identification Definition (Sheet 1 of 3)
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
V
V
CC_MAX
CC_MAX
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFF
OFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95626
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84374
0.83750
0.83125
0.82500
0.81875
0.81250
0.80625
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
Datasheet, Volume 1
59
Electrical Specifications
Table 7-1.
VRD 11.1/11.0 Voltage Identification Definition (Sheet 2 of 3)
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
V
V
CC_MAX
CC_MAX
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
60
Datasheet, Volume 1
Electrical Specifications
Table 7-1.
VRD 11.1/11.0 Voltage Identification Definition (Sheet 3 of 3)
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
V
V
CC_MAX
CC_MAX
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
OFF
Table 7-2.
Market Segment Selection Truth Table for MSID[2:0]
1
MSID2
MSID1
MSID0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
2009A processors supported
2009B processors supported
Reserved
Notes:
1.
2.
The MSID[2:0] signals are provided to indicate the maximum platform capability to the processor.
®
2009A processors have thermal requirements that are equivalent to those of the Intel Core™2 Duo E8000
processor series. Refer to the appropriate processor Thermal and Mechanical Specifications and Design
Guidelines for additional information (see Section 1.7).
®
3.
2009B processors have thermal requirements that are equivalent to those of the Intel Core™2 Quad
Q9000 processor series. Refer to the appropriate processor Thermal and Mechanical Specifications and
Design Guidelines for additional information (see Section 1.7).
Datasheet, Volume 1
61
Electrical Specifications
7.5
Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – these signals should not be connected
• RSVD_TP – these signals should be routed to a test point
• RSVD_NCTF – these signals are non-critical to function and may be left un-
connected
Arbitrary connection of these signals to VCC, VTT, VDDQ, VCCPLL, VSS, or to any other
signal (including each other) may result in component malfunction or incompatibility
with future processors. See Chapter 8 for a land listing of the processor and the
location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs may be left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For details, see Table 7-9.
7.6
Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals, have On-
Die Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
62
Datasheet, Volume 1
Electrical Specifications
Table 7-3.
Signal Groups (Sheet 1 of 2)1
Alpha
Group
Signal Group
Type
Signals
System Reference Clock
BCLK[0], BCLK#[0],
BCLK[1], BCLK#[1],
PEG_CLK, PEG_CLK#
Differential
(a)
(b)
CMOS Input
Differential
CMOS Output
BCLK_ITP, BCLK_ITP#
2
DDR3 Reference Clocks
Differential
SA_CK[3:0], SA_CK#[3:0]
SB_CK[3:0], SB_CK#[3:0]
(c)
DDR3 Output
2
DDR3 Command Signals
SA_RAS#, SB_RAS#,
SA_CAS#, SB_CAS#
SA_WE#, SB_WE#
SA_MA[15:0], SB_MA[15:0]
SA_BS[2:0], SB_BS[2:0]
4
4
SA_DM[7:0] , SB_DM[7:0]
Single Ended
(d)
DDR3 Output
SM_DRAMRST#
SA_CS#[3:0], SB_CS#[3:0]
SA_CS#[7:4], SB_CS#[7:4]
SA_ODT[3:0], SB_ODT[3:0]
SA_CKE[3:0], SB_CKE[3:0]
2
DDR3 Data Signals
Single ended
(e)
(f)
DDR3 Bi-directional
DDR3 Bi-directional
SA_DQ[63:0], SB_DQ[63:0]
SA_DQS[8:0], SA_DQS#[8:0]
3
SA_ECC_CB[7:0]
Differential
SB_DQS[8:0], SB_DQS#[8:0]
3
SB_ECC_CB[7:0]
TAP (ITP/XDP)
Single Ended
(g)
(h)
CMOS Input
TCK, TDI, TMS, TRST#, TDI_M
TDO, TDO_M
CMOS Open-Drain
Output
Single Ended
Asynchronous CMOS
Output
TAPPWRGOOD
Single Ended
Control Sideband
Single Ended
(i)
VCCPWRGOOD_0,
VCCPWRGOOD_1, VTTPWRGOOD
Asynchronous CMOS
Input
(ja)
Asynchronous CMOS
Input
SM_DRAMPWROK
Single Ended
Single Ended
Single Ended
(jb)
(k)
(l)
Asynchronous Output
RESET_OBS#
Asynchronous GTL
Output
PRDY#, THERMTRIP#
Single Ended
Single Ended
(m)
(n)
Asynchronous GTL Input PREQ#
GTL Bi-directional
CATERR#, BPM#[7:0]
Asynchronous Bi-
directional
PECI
Single Ended
Single Ended
Single Ended
(o)
(p)
Asynchronous GTL Bi-
directional
PROCHOT#
CFG[17:0], PM_SYNC,
PM_EXT_TS#[1:0]
(qa)
CMOS Input
Datasheet, Volume 1
63
Electrical Specifications
Table 7-3.
Signal Groups (Sheet 2 of 2)1
Alpha
Group
Signal Group
Type
Signals
Single Ended
Single Ended
(qb)
(r)
CMOS Input
RSTIN#
CMOS Output
VTT_SELECT
VID[7:6]
Single Ended
Single Ended
(s)
CMOS Bi-directional
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
COMP0, COMP1, COMP2, COMP3,
SM_RCOMP[2:0], ISENSE
(t)
Analog Input
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Single Ended
(ta)
Analog Output
Power/Ground/Other
VCC, VCC_NCTF, VTT, VCCPLL,
(u)
(v)
(w)
Power
Ground
5
VDDQ, VAXG
VSS, CGC_TP_NCTF
RSVD, RSVD_NCTF, RSVD_TP,
FC_x
No Connect
Asynchronous CMOS
Output
PSI#
Single Ended
(x)
VCC_SENSE, VSS_SENSE,
(y)
(z)
Sense Points
VTT_SENSE, VSS_SENSE_VTT,
5
5
VAXG_SENSE , VSSAXG_SENSE
Other
SKTOCC#, DBR#
PCI Express*
Differential
(ac)
(ad)
PCI Express Input
PCI Express Output
PEG_RX[15:0], PEG_RX#[15:0]
PEG_TX[15:0], PEG_TX#[15:0]
Differential
PEG_ICOMP0, PEG_ICOMPI,
PEG_RCOMP0, PEG_RBIAS
Single Ended
(ae)
Analog Input
DMI
Differential
Differential
(af)
DMI Input
DMI_RX[3:0], DMI_RX#[3:0]
DMI_TX[3:0], DMI_TX#[3:0]
(ag)
DMI Output
®
Intel FDI
4
4
FDI_FSYNC[1:0] ,
Single Ended
Differential
(ah)
(ai)
FDI Input
4
FDI_LSYNC[1:0] , FDI_INT
4
4
FDI Output
FDI_TX[7:0] , FDI_TX#[7:0]
Notes:
1.
2.
3.
4.
5.
Refer to Chapter 6 for signal description details.
SA and SB refer to DDR3 Channel A and DDR3 Channel B.
These signals are only used on processors and platforms that support ECC DIMMs.
These signals will not be actively used on the Intel Core™ i7-800 and i5-700 desktop processor series.
These signals are not used by the processor. They are no connect on the package.
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least eight BCLKs for the processor to recognize the proper signal state. See
Section 7.9 for the DC specifications.
64
Datasheet, Volume 1
Electrical Specifications
7.7
7.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
Absolute Maximum and Minimum Ratings
Table 7-4 specifies absolute maximum and minimum ratings. At conditions outside
functional operation condition limits, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to
conditions outside these limits (but within the absolute maximum and minimum
ratings) the device may be functional, but with its lifetime degraded depending on
exposure to conditions exceeding the functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time, it will either not function or its reliability will be
severely degraded when returned to conditions within the functional operating
condition limits.
Although the processor contains protective circuitry to resist damage from Electro-
Static Discharge (ESD), precautions should always be taken to avoid high static
voltages or electric fields.
Table 7-4.
Processor Absolute Minimum and Maximum Ratings
1, 2
Symbol
Parameter
Min
Max
Unit
Notes
Processor Core voltage with respect
V
-0.3
1.40
V
6
CC
to V
SS
Voltage for the memory controller
and Shared Cache with respect to V
V
-0.3
-0.3
1.40
1.80
V
V
TT
SS
Processor I/O supply voltage for
V
DDQ
DDR3 with respect to V
SS
Processor PLL voltage with respect to
SS
V
-0.3
-40
1.98
85
V
CCPLL
V
T
Storage temperature
C
3, 4, 5
STORAGE
Notes:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
2.
3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, refer to the processor case temperature
specifications.
4.
5.
6.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long-term reliability of the processor.
CC
V
is a VID based rail.
Datasheet, Volume 1
65
Electrical Specifications
7.9
DC Specifications
The processor DC specifications in this section are defined at the processor
pads, unless noted otherwise. See Chapter 8 for the processor land listings and
Chapter 6 for signal definitions. Voltage and current specifications are detailed in
Table 7-5 and Table 7-6. For platform planning, refer to Table 7-7 that provides VCC
static and transient tolerances. This same information is presented graphically in
Figure 7-1.
The DC specifications for the DDR3 signals are listed in Table 7-8 Control Sideband and
Test Access Port (TAP) are listed in Table 7-9.
Table 7-5 through Table 7-6 list the DC specifications for the processor and are valid
only while meeting the thermal specifications (as specified in the processor Thermal
and Mechanical Specifications and Guidelines), clock frequency, and input voltages.
Care should be taken to read all notes associated with each parameter.
7.9.1
Voltage and Current Specifications
Table 7-5.
Processor Core Active and Idle Mode DC Voltage and Current Specifications
Symbol
VID
Parameter
Min
Typ
Max
Unit
Note
VID Range
for processor core
0.6500
—
1.4000
V
V
V
V
V
See Table 7-7 and Figure 7-1
1, 2, 3
CC
CC,BOOT
CC
V
Default V voltage for initial power up
—
—
1.10
—
—
CC
Processor
Number
2009B I ; for Intel Core™ i7-
CC
800 and i5-700 processor
series with 95 W TDP
i7-880
i7-875K
i7-870
i7-860
i5-760
i5-750
3.06 GHz
2.93 GHz
2.93 GHz
2.80 GHz
2.80 GHz
2.66 GHz
110
110
110
110
110
110
I
I
A
A
4
4
CC
Processor
Number
2009A I ; for Intel Core™ i7-
CC
800 and i5-700 processor
series with 82 W TDP
—
—
CC
i7-870S
i7-860S
i5-750S
2.66 GHz
2.53 GHz
2.40 GHz
75
75
75
2009B Sustained I ; recommended design
CC
target for Intel Core™ i7-800 and i5-700
processor series with 95 W TDP
I
I
—
—
—
—
90
60
A
A
CC_TDC
CC_TDC
2009A Sustained I ; recommended design
CC
target for Intel Core™ i7-800 and i5-700
processor series with 82 W TDP
Notes:
1.
Each processor is programmed with a maximum valid voltage identification value (VID) that is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
2.
3.
4.
Refer to Table 7-7 and Figure 7-1 for the minimum, typical, and maximum V allowed for a given current.
The processor should not be subjected to any V and I combination wherein V exceeds V for a
CC_MAX
CC
CC
CC
CC
given current.
specification is based on the V
I
loadline. Refer to Figure 7-1 for details.
CC_MAX
CC_MAX
66
Datasheet, Volume 1
Electrical Specifications
Table 7-6.
Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
Voltage for the memory controller
and shared cache defined at the
socket motherboard VTT pinfield
via.
1.045
1.10
1.155
V
1
V
TT
Voltage for the memory controller
and shared cache defined across
VTT_SENSE and VSS_SENSE_VTT.
1.023
1.10
1.117
V
2
Processor I/O supply voltage for
DDR3
V
1.425
1.71
1.5
1.8
1.575
1.89
V
V
DDQ
PLL supply voltage (DC + AC
specification)
V
CCPLL
2009B (Intel Core™ i7-800 and i5-
700 series processor with 95 W
TDP): Current for the memory
controller and Shared Cache
I
I
—
—
—
—
35
35
A
A
TT
TT
2009A (Intel Core™ i7-800 and i5-
700 series processor with 82 W
TDP): Current for the memory
controller and Shared Cache
2009B (Intel Core™ i7-800 and i5-
700 series processor with 95 W
TDP): Sustained current for the
memory controller and Shared
Cache
I
I
—
—
—
—
30
30
A
A
TT_TDC
TT_TDC
2009A (Intel Core™ i7-800 and i5-
700 series processor with 82 W
TDP): Sustained current for the
memory controller and Shared
Cache
Processor I/O supply current for
DDR3
I
—
—
—
—
—
—
6
6
A
A
A
DDQ
Processor I/O supply sustained
current for DDR3
I
DDQ_TDC
Processor I/O supply standby
current for DDR3
I
0.650
DDQ_STANDBY
I
PLL supply current
—
—
—
—
1.1
0.7
A
A
CC_VCCPLL
I
PLL sustained supply current
CC_VCCPLL_TDC
Notes:
1.
V
must be provided using a separate voltage source and not be connected to V . The voltage
T
T
C
C
specification requirements are defined in the middle of the VTT pinfield at the processor socket vias on the
bottom side of the baseboard. The voltage specifications are measured with a 20-MHz bandwidth
oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled
into the oscilloscope probe.
2.
V
must be provided using a separate voltage source and not be connected to V . The voltage
TT
CC
specification requirements are defined across VTT_SENSE and VSS_SENSE_VTT lands at the processor
socket vias on the bottom side of the baseboard. The requirements across the SENSE signals account for
voltage drops and impedances across the baseboard vias, socket, and processor package up to the
processor Si. The voltage specifications are measured with a 20-MHz bandwidth oscilloscope, 1.5 pF
maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope
probe.
Datasheet, Volume 1
67
Electrical Specifications
Table 7-7.
VCC Static and Transient Tolerance
1, 2, 3
Voltage Deviation from VID Setting
I
(A)
CC
V
(V)
V
(V)
V
(V)
CC_Min
1.40 m
CC_Max
CC_Typ
1.40 m
1.40 m
0
0.000
-0.007
-0.014
-0.021
-0.028
-0.035
-0.042
-0.049
-0.056
-0.063
-0.070
-0.077
-0.084
-0.091
-0.098
-0.105
-0.112
-0.119
-0.126
-0.133
-0.140
-0.147
-0.019
-0.026
-0.033
-0.040
-0.047
-0.054
-0.061
-0.068
-0.075
-0.082
-0.089
-0.096
-0.103
-0.110
-0.117
-0.124
-0.131
-0.138
-0.145
-0.152
-0.159
-0.166
-0.038
-0.045
-0.052
-0.059
-0.066
-0.073
-0.080
-0.087
-0.094
-0.101
-0.108
-0.115
-0.122
-0.129
-0.136
-0.143
-0.150
-0.157
-0.164
-0.171
-0.178
-0.185
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
110
Notes:
1.
2.
3.
The V
and V
loadlines represent static and transient limits.
CC_MAX
CC_MIN
This table is intended to aid in reading discrete points on Figure 7-1.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for socket load line
guidelines and VR implementation.
68
Datasheet, Volume 1
Electrical Specifications
Figure 7-1. VCC Static and Transient Tolerance Loadlines
Icc [A]
0
10
20
30
40
50
60
70
80
90
100
110
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
VID - 0.188
Vcc Maximum
Vcc Minimum
Vcc Typical
Datasheet, Volume 1
69
Electrical Specifications
Table 7-8.
DDR3 Signal Group DC Specifications
Alpha
Group
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
Input Low Voltage
Input High Voltage
Output Low Voltage
(e,f)
(e,f)
—
—
0.43*V
—
V
V
2,4
3
IL
DDQ
V
0.57*V
—
IH
DDQ
(V
/ 2)* (R
))
VTT_TERM
/
ON
DDQ
ON
V
(c,d,e,f)
—
—
—
6
4,6
5
OL
(R +R
Output High Voltage
V
– ((V
/ 2)*
DDQ
DDQ
V
R
(c,d,e,f)
—
V
OH
ON
(R /(R +R ))
VTT_TERM
ON
ON
DDR3 Clock Buffer On
Resistance
—
—
21
20
20
21
—
—
—
—
36
31
31
36
R
R
R
DDR3 Command Buffer On
Resistance
ON
ON
ON
5
DDR3 Control Buffer On
Resistance
—
5
DDR3 Data Buffer On
Resistance
—
5
On-Die Termination for
Data Signals
Data ODT
(d)
93.5
—
—
126.5
I
Input Leakage Current
COMP Resistance
COMP Resistance
COMP Resistance
—
(t)
(t)
(t)
—
99
± 1
101
mA
LI
100
24.9
130
7
7
7
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
24.7
128.7
25.1
131.3
Notes:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
V
V
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
IL
IH
IH
and V
may experience excursions above V
. However, input signal drivers must comply with the signal quality
OH
DDQ
specifications.
This is the pull down driver resistance.
5.
6.
7.
R
is the termination on the DIMM and is not controlled by the processor.
VTT_TERM
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V
.
SS
70
Datasheet, Volume 1
Electrical Specifications
Table 7-9.
Control Sideband and TAP Signal Group DC Specifications
1
Symbol
Alpha Group
Parameter
Min
Typ
Max
Units
Notes
V
(m),(n),(p),(qa),(qb),(s)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
—
—
—
—
—
—
—
—
—
0.64
V
V
V
V
V
V
V
V
V
2
2,4
2
IL
*
TT
TT
TT
V
(m),(n),(p),(qa),(qb),(s)
0.76
V
—
IH
*
TT
TT
TT
V
(g)
—
0.40
V
V
IL
*
V
(g)
0.75
V
V
—
2,4
2
IH
*
V
(ja)
(ja)
(jb)
(jb)
—
0.25
IL
*
V
0.75
—
2,4
2
IH
*
V
—
0.29
—
IL
IH
OL
V
0.87
2,4
V
(k),(l),(n),(p),(r),
(s),(h),(i)
V
* R
/
ON
+
TT
—
—
(R
V
2,6
2,4
ON
R
)
SYS_TERM
V
R
(k),(l),(n),(p),
(r),(s),(i)
Output High Voltage
OH
V
—
—
—
—
V
TT
(ab)
Buffer on Resistance
20
—
45
ON
I
(ja),(jb),(m),(n),
(p),(qa),(s),(t),(g)
Input Leakage Current
LI
LI
±200
A
3
I
(qb)
(t)
Input Leakage Current
COMP Resistance
COMP Resistance
COMP Resistance
COMP Resistance
—
—
49.9
49.9
20
±100
50.4
50.4
20.2
20.2
A
3
5
5
5
5
COMP0
COMP1
COMP2
COMP3
49.4
49.4
19.8
19.8
(t)
(t)
(t)
20
Notes:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
The V referred to in these specifications refers to instantaneous V
.
TT
TT
IN
and V
For V between 0 V and V . Measured when the driver is tristated.
TT
V
may experience excursions above V . However, input signal drivers must comply with the signal quality
IH
O
H
T
T
specifications.
5.
6.
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V
SYS_TERM
.
SS
R
is the system termination on the signal.
Datasheet, Volume 1
71
Electrical Specifications
Table 7-10. PCI Express* DC Specifications
Alpha
Group
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
(ad)
Differential peak to peak Tx
voltage swing
V
0.8
—
—
—
1.2
20
V
3
TX-DIFF-p-p
(ad)
(ad)
Tx AC Peak Common Mode
Output Voltage (Gen1 only)
V
mV
1,2,6
TX_CM-AC-p
Tx AC Peak-to-Peak Common
Mode Output Voltage (Gen2
only)
V
—
—
100
mV
1,2
TX_CM-AC-p-p
(ad)
(ad)
(ac)
(ac)
(ac)
(ac)
(ac)
DC Differential Tx Impedance
(Gen1 only)
Z
Z
80
—
—
—
—
—
—
—
—
120
120
60
1,10
1,10
1,8,9
1
TX-DIFF-DC
TX-DIFF-DC
DC Differential Tx Impedance
(Gen2 only)
DC Common Mode Rx
Impedance
Z
40
RX-DC
DC Differential Rx Impedance
(Gen1 only)
Z
80
120
1.2
1.2
150
RX-DIFF-DC
Differential Rx input Peak to
Peak Voltage (Gen1 only)
V
V
0.175
0.120
—
V
1
RX-DIFFp-p
RX-DIFFp-p
Differential Rx Input Peak to
Peak Voltage (Gen2 only)
V
1,1
1,7
Rx AC peak Common Mode
Input Voltage
V
mV
RX_CM-AC-p
PEG_ICOMPO
PEG_ICOMPI
(ae)
(ae)
Comp Resistance
Comp Resistance
Comp Resistance
Comp Resistance
49.5
49.5
50
50
50.5
50.5
4,5
4,5
4,5
4,5
PEG_RCOMPO (ae)
PEG_RBIAS (ae)
49.5
50
50.5
742.5
750
757.5
Notes:
1.
2.
Refer to the PCI Express Base Specification for more details.
and V are defined in the PCI Express Base Specification. Measurement is made over
at least 10^ UI.
As measured with compliance test load. Defined as 2*|V
V
TX-AC-CM-PP
TX-AC-CM-P
6
3.
4.
5.
6.
7.
– V
|.
TXD-
TXD+
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V
PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor
RMS value.
.
SS
Measured at Rx pins into a pair of 50-terminations into ground. Common mode peak voltage is defined by
the expression: max{|(Vd+ - Vd-) – V-CMDC|}.
8.
9.
DC impedance limits are needed to guarantee Receiver detect.
The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 ±20%) must be within the
specified range by the time Detect is entered.
10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
72
Datasheet, Volume 1
Electrical Specifications
7.10
Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. For the
PECI command set supported by the processor, refer to the appropriate processor
Thermal and Mechanical Specifications and Design Guidelines for additional information
(see Section 1.7).
7.10.1
DC Characteristics
The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical
specifications shown in Table 7-11 is used with devices normally operating from a VTT
interface supply. VTT nominal levels will vary between processor families. All PECI
devices will operate at the VTT level determined by the processor installed in the
system. For specific nominal VTT levels, refer to Table 7-6.
Table 7-11. PECI DC Electrical Limits
1
Symbol
Definition and Conditions
Min
Max
Units
Notes
V
Input Voltage Range
-0.150
V
V
V
V
V
in
TT
V
Hysteresis
0.1 * V
N/A
hysteresis
TT
V
V
Negative-Edge Threshold Voltage
Positive-Edge Threshold Voltage
High-Level Output Source
0.275 * V
0.550 * V
0.500 * V
0.725 * V
n
TT
TT
p
TT
TT
I
-6.0
N/A
mA
source
(V
= 0.75 * V )
TT
OH
Low-Level Output Sink
(V = 0.25 * V
I
0.5
1.0
mA
µA
sink
)
TT
OL
High Impedance State Leakage to
(V = V
I
N/A
100
2
2
leak+
V
)
OL
TT
leak
High Impedance Leakage to GND
(V = V
I
N/A
N/A
100
10
µA
pF
leak-
)
OH
leak
C
Bus Capacitance per Node
bus
Signal Noise Immunity above
300 MHz
V
0.1 * V
N/A
V
p-p
noise
TT
Notes:
1.
2.
V
supplies the PECI interface. PECI behavior does not affect V min/max specifications.
TT TT
The leakage specification applies to powered devices on the PECI bus.
Datasheet, Volume 1
73
Electrical Specifications
7.10.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design.
Figure 7-2. Input Device Hysteresis
VTTD
Maximum VP
PECI High Range
Minimum VP
Maximum VN
Minimum
Hysteresis Signal Range
Valid Input
Minimum VN
PECI Ground
PECI Low Range
.
§ §
74
Datasheet, Volume 1
Processor Land and Signal Information
8 Processor Land and Signal
Information
8.1
Processor Land Assignments
The processor land-map quadrants are shown in Figure 8-1 through Figure 8-4.
Table 8-2 provides a listing of all processor lands ordered alphabetically by pin name.
Not all signals listed in this chapter are used by the processor. Table 8-1 lists the signals
that are not used by the Intel Core™ i7-800 and i5-700 desktop processor series. The
signals are included for reference to define all LGA 1156 land locations. These signals
will be used by future processors that are compatible with LGA 1156 platforms.
Table 8-1.
Signals Not Used by the Intel® Core™ i7-800 and i5-700 Desktop Processor
Series
Interface
Signals Not Used
FDI_FSYNC[1:0]
FDI_LSYNC[1:0]
FDI_INT
Intel Flexible Display Interface
FDI_TX[7:0]
FDI_TX#[7:0]
GFX_DPRSLPVR
GFX_IMON
GFX_VID[6:0]
GFX_VR_EN
Integrated Graphics Core Power
VAXG
SA_DM[7:0]
Memory
SB_DM[7:0]
SA_ECC_CB[7:0]
SB_ECC_CB[7:0]
SA_DQS[8]/SA_DQS#[8]
SB_DQS[8]/SB_DQS#[8]
SA_CS#[7:4]
SB_CS#[7:4]
Memory Interface:, ECC Related
Memory Interface: RDIMM Related
Datasheet, Volume 1
75
Processor Land and Signal Information
Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
RSVD_NCTF
SA_DQ[49] SA_DQ[52]
SB_CS#[0]
SB_MA[10] SA_ODT[3]
VDDQ
VDDQ
VSS
VSS
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
RSVD_NCTF
SA_DQS#[5]
SA_DQ[55] SA_DQS[6] SA_DQ[48] SA_DQ[53] SA_DQ[47]
SA_DM[5] SA_DQ[45] SB_CS#[1] SB_MA[13]
SA_CS#[1] SA_ODT[2]
SA_ODT[1] SA_ODT[0]
SA_MA[13] SA_CS#[3]
SB_CAS# SB_RAS# SB_BS[1]
RSVD_NCTF
SA_DQS#[6]
SA_DQ[50] SA_DQ[54]
SA_DQ[42] SA_DQS[5]
SA_DQ[44] SB_CS#[3]
VDDQ
SB_ODT[2] SB_CS#[2]
SA_CS#[0]
SA_CS#[2]
VDDQ
VDDQ
VSS
VSS
VSS
RSVD_NCTF
SA_DQ[40]
SA_DQ[61] SA_DQ[60] SA_DQ[51]
SA_DM[6] SA_DQ[43] SA_DQ[46]
SA_DQ[41]
SB_ODT[1] SB_ODT[3] SB_ODT[0]
SB_WE# SB_BS[0]
SB_DQ[39] SB_DQS[4]
SA_CAS#
VSS
VSS
SB_DQ[47]
SA_DQS#[4]
SA_DQ[38]
SA_DQ[57] SA_DQ[56]
SB_DQ[49] SB_DQ[53]
SB_DQ[40] SB_DQ[44]
SA_DQ[33]
SB_DQ[36]
SA_DM[7]
SA_DQS#[7]
SA_WE#
VDDQ
VSS
VSS
VSS
VSS
VSS
SB_DQS#[6]
SB_DQ[46]
SB_DQS#[5]
SB_DQ[45]
SB_DQS#[4]
SA_DQS[7]
SB_DQS[6] SB_DQ[48]
SB_DQ[42]
SA_DQS[4] SA_DQ[37] SB_DQ[35] SB_DQ[34]
SA_CK[0] SA_CK#[0]
VSS
VSS
VSS
SA_DQ[63] SA_DQ[62]
SB_DQ[55] SB_DQ[51]
SB_DQ[52]
SB_DQS[5] SB_DQ[41] SA_DQ[35]
SA_DQ[34]
SB_DQ[38]
SB_DQ[33] SB_DQ[37] SA_CK#[2]
VSS
VSS
VSS
VSS
VSS VSS
VSS
SB_DQ[60]
SA_DQ[59] SA_DQ[58]
SB_DQ[54] SB_DQ[50] SB_DM[5]
SA_DQ[39] SA_DM[4]
SA_DQ[32] SA_DQ[36]
SB_DM[4] SB_DQ[32]
SA_CK[2]
RSVD
VTT
VTT
VTT
TMS
VSS
VSS
VSS
VSS
VSS
TCK
TDI
SB_DQS#[7]
SB_DQ[57] SB_DQ[61]
SB_DQ[43]
SB_CS#[5] SB_CS#[4] SA_CS#[5]
SB_DM[6]
BPM#[4]
TRST#
RSVD RSVD RSVD RSVD RSVD RSVD
VSS
DBR#
BCLK_ITP#
TDO
RESET_OBS#
SB_DQS[7] SB_DQ[63] SB_DQ[56]
SB_CS#[6] SA_CS#[6]
BPM#[0] BPM#[1]
BPM#[5]
RSVD
RSVD RSVD
VSS
VSS
VSS
VSS
VSS
VSS
TAPPWRGOOD
SKTOCC#
SB_DM[7]
SB_CS#[7] SA_CS#[7] SA_CS#[4]
BCLK_ITP
BPM#[2] BPM#[3] BPM#[7] BPM#[6]
PREQ#
RSVD RSVD RSVD RSVD RSVD
VSS
AK
AJ
SB_DQ[59] SB_DQ[58] SB_DQ[62]
PRDY#
RSVD
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT VTT
VTT
VTT
VTT
SM_DRAMPWROK
VTTPWRGOOD
VCCPWRGOOD_1
VCCPWRGOOD_0
PROCHOT#
PM_SYNC
RSVD
VSS
VSS
AH
AG
AF
AE
AD
AC
AB
AA
FC_AG40 CATERR#
PSI#
PECI
VSS
VSS
VTT
VTT
VTT_SELECT
THERMTRIP#
RSTIN#
TDO_M TDI_M COMP0
VSS
VSS_SENSE_VTT
VTT_SENSE
FC_AE38
VSS
VTT VTT
VTT VTT
VTT VTT VTT VTT VTT VTT VTT VTT
VTT VTT VTT VTT VTT VTT VTT VTT
VSS VSS VSS VSS VSS VSS VSS VSS
VTT VTT VTT VTT VTT VTT
76
Datasheet, Volume 1
Processor Land and Signal Information
Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant)
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
RSVD_NCTF
SB_MA[4]
SB_MA[9] SA_MA[1]
SA_MA[5] SB_MA[14]
SA_CKE[3] SB_CKE[1] SA_DQ[27]
SA_DQS[3] SA_DQ[25]
VDDQ
VDDQ
VDDQ
VSS
VSS
AY
AW
AV
AU
AT
AR
AP
AN
AM
AL
SA_DQS#[3]
RSVD_NCTF
SA_DQ[22]
SA_MA[0] SB_MA[6] SB_MA[11] SB_MA[12] SA_MA[4] SA_MA[7] SA_MA[9] SA_MA[12] SA_CKE[1]
SB_CKE[0] SA_DQ[31]
SA_DQ[24] SA_DQ[19] SA_DQ[18]
VDDQ
SM_DRAMRST#
RSVD_NCTF
SB_MA[15] SA_CKE[2] SB_CKE[3]
SA_DQ[30] SA_DM[3] SA_DQ[29] SA_DQ[23]
SA_BS[0]
SB_MA[2] SB_MA[5]
SA_MA[2] SA_MA[6]
SB_BS[2]
VDDQ
VDDQ
VDDQ
VSS
SA_DQS#[2]
SB_MA[0] SA_BS[1] SB_MA[1] SB_MA[3] SB_MA[7] SA_MA[3] SA_MA[8] SA_MA[11] SA_BS[2]
SA_CKE[0] SB_CKE[2] SA_DQ[26]
SA_DQ[28] SA_DQS[2]
SA_DQ[17] SA_DM[2]
VDDQ
VSS VSS
SB_ECC_CB[1]
SA_MA[10]
SB_MA[8]
SB_CK[1]
SA_MA[14]
SB_DQ[31]
SB_DM[3] SB_DQ[24]
SA_DQ[16] SA_DQ[20]
SA_DQ[21]
SA_RAS#
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
SB_ECC_CB[0]
SA_ECC_CB[2]
SA_ECC_CB[3]
SB_DQS#[8]
SB_ECC_CB[7]
SB_CK[3] SB_CK#[3] SB_CK[0] SB_CK#[0] SB_CK#[1] SB_DQS[8]
SA_MA[15] SB_DQ[26] SB_DQS[3] SB_DQ[25] SB_DQ[29] SB_DQ[19] SA_DQ[15] SA_DQ[10] SA_DQ[11]
VSS
VSS
VSS
VSS
SB_ECC_CB[3]
SA_ECC_CB[0]
SA_ECC_CB[1]
SA_DQS#[8]
SA_DQS[8]
SB_DQS#[3]
SA_DQS#[1]
SA_CK[3] SA_CK[1]
SB_DQ[18] SB_DQ[23]
SA_DQS[1] SA_DQ[14]
VSS VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
SB_ECC_CB[2]
SB_ECC_CB[6]
SB_ECC_CB[5]
SA_CK#[3] SA_CK#[1] SB_CK[2] SB_CK#[2]
SB_DQ[28] SB_DQ[22] SB_DQS[2] SB_DQ[17]
SA_DQ[8] SA_DQ[9] SA_DM[1]
RSVD_TP
SA_ECC_CB[7]
VSS
SB_ECC_CB[4]
SB_DQS#[2]
SB_DQ[27] SB_DM[2]
SB_DQ[21] SA_DQ[12] SA_DQ[13]
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
VSS
VSS
VSS
SA_ECC_CB[5]
SB_DQ[30]
SB_DQ[16] SB_DQ[20] SB_DQ[11]
SA_DQ[2] SA_DQ[3]
RSVD RSVD
RSVD RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT VTT
VSS
SA_ECC_CB[6]
SA_ECC_CB[4]
SB_DQ[15] SB_DQ[10]
SA_DQS[0] SA_DQ[7] SA_DQ[6]
RSVD
RSVD RSVD RSVD RSVD RSVD
VSS
VSS
VSS
VSS VSS
AK
AJ
SB_DQS#[1]
SA_DQ[1]
SA_DQS#[0]
SA_DM[0]
SB_DQ[3] SB_DQ[14]
VDDQ
VDDQ
VDDQ
VSS
VSS
VTT
VSS
VSS
VSS
VSS
VSS
VTT
SB_DQ[2] SB_DQ[9] SB_DQS[1]
SB_DM[1]
SA_DQ[5] SA_DQ[0]
VSS
VSS
AH
AG
AF
AE
AD
AC
AB
AA
SB_DIMM_VREFDQ
SM_RCOMP[0]
SA_DQ[4]
SB_DQ[12] SB_DQ[8] SB_DQ[13]
VCCPLL
VSS
SA_DIMM_VREFDQ
COMP1
VSS
SB_DQ[6] SB_DQS[0]
VCCPLL VCCPLL
VSS
SB_DQS#[0]
SM_RCOMP[2]
RSVD
SB_DQ[7]
SB_DM[0]
FDI_LSYNC[0]
FDI_FSYNC[0]
PM_EXT_TS#[1]
VSS
VSS
VTT
VSS
VTT
VSS
FDI_LSYNC[1]
SM_RCOMP[1]
SB_DQ[0] SB_DQ[1]
SB_DQ[4] SB_DQ[5]
RSVD
VSS
FDI_FSYNC[1]
FDI_INT
VSS
VTT
PM_EXT_TS#[0]
VSS
VSS
VTT
BCLK#[0]
PEG_CLK#
BCLK[1] BCLK[0]
PEG_CLK
VSS
Datasheet, Volume 1
77
Processor Land and Signal Information
Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant)
VTT VTT VTT VTT VTT VTT
VSS VSS VSS VSS VSS VSS
Y
W
V
U
T
VTT VTT VTT VTT VTT VTT VTT VTT
VID[0]/MSID[0]
VID[1]/MSID[1]
VID[2]/MSID[2]
VID[3]/CSC[0]
VID[4]/CSC[1]
VID[5]/CSC[2]
VID[6] VID[7]
VCC_SENSE
VSS_SENSE
ISENSE
VSS VSS VSS VSS
VSS
VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC
VSS VCC VCC VSS VCC VCC VSS VCC
VCC VCC VSS VCC VCC VSS VCC VCC VSS
R
P
N
M
L
VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC
VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC
VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC
VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC
VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC
VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
K
J
H
G
F
E
VAXG
VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS
D
C
B
A
VCC_NCTF
VAXG
VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VCC VSS
CGC_TP_NCTF
VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC
VCC_NCTF
VSS VCC VCC VSS VCC
VSS VCC VCC VSS VCC VCC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
78
Datasheet, Volume 1
Processor Land and Signal Information
Figure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant)
FDI_TX#[7]
FDI_TX[4]
FDI_TX#[6]
BCLK#[1]
FDI_TX[3]
FDI_TX[7]
FDI_TX[6]
FDI_TX#[4]
FDI_TX[1]
VSS
Y
W
V
U
T
FDI_TX#[3]
DMI_RX#[3]
DMI_RX[3]
FDI_TX#[1]
VTT
VTT
DMI_RX#[2]
VSS
VTT VTT VTT
VTT
FDI_TX#[2]
FDI_TX[0]
FDI_TX#[0]
DMI_RX#[1]
FDI_TX[2]
DMI_RX[1]
PEG_RX[15]
DMI_TX#[3]
PEG_RX[14]
DMI_RX[2]
DMI_RX#[0]
VSS
PEG_RX#[15]
VSS
VTT VTT VTT
VTT
FDI_TX[5]
FDI_TX#[5]
PEG_TX#[15] PEG_TX[15]
DMI_TX[3] DMI_RX[0]
VSS
R
P
N
M
L
PEG_RX#[14]
DMI_TX#[2]
VSS
VSS
VTT VTT VTT
PEG_TX#[14]
PEG_TX[13] PEG_TX#[13]
DMI_TX#[1]
DMI_TX[1]
DMI_TX[2]
DMI_TX#[0]
VSS
VTT
PEG_TX[14]
PEG_TX[11] PEG_TX#[11]
VAXG VAXG VAXG
VAXG VAXG VAXG
VAXG VAXG VAXG
VAXG VAXG VAXG
RSVD
VSS VCC VSS VCC
VCC VCC VSS VCC
VCC VSS VCC VCC
VSS VCC VCC VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS
VSS
VTT VTT VTT
PEG_TX#[12] PEG_TX[10] PEG_TX#[10]
PEG_RX#[13]
PEG_RX[13]
DMI_TX[0]
PEG_RX#[12]
PEG_RX[12]
PEG_RX#[10]
PEG_RX[10]
PEG_RX#[8]
CFG[17]
CFG[13]
RSVD
VSS
VSS
VTT
PEG_TX[12]
PEG_TX#[8]
PEG_TX[8]
PEG_RX[11]
PEG_TX#[5]
CFG[15]
CFG[10] CFG[14] CFG[11]
VSS
VSS VSS
VSS
K
J
GFX_DPRSLPVR
PEG_TX#[9]
GFX_VID[6]
PEG_TX#[7]
PEG_RX#[11]
PEG_TX[7]
CFG[12]
CFG[9]
VSS
VSS
VSS
PEG_TX[9]
PEG_TX[5]
CFG[16]
CFG[4] CFG[5]
VAXG
VAXG VAXG
VCC VCC VSS
VSS
VSS
VSS VSS
VSS
H
G
F
GFX_VID[5]
GFX_VID[0]
CFG[1]
VSS
PEG_TX#[6]
PEG_TX#[4]
PEG_TX#[2]
PEG_TX[2]
PEG_RX#[9]
PEG_TX[4]
PEG_RX[9]
PEG_TX[3]
CFG[8]
VAXG VAXG
VAXG VAXG
VCC VSS
VSS
VSS
GFX_VR_EN
PEG_TX#[3]
PEG_TX[6] GFX_IMON
CFG[3] CFG[7]
VAXG VAXG VAXG
VAXG VAXG
VSS
VSS
VSS
VSS
VSS
GFX_VID[2]
GFX_VID[3]
PEG_TX#[1]
PEG_RX#[7]
PEG_TX[1]
PEG_TX#[0]
PEG_RX[8]
RSVD_NCTF
CFG[2] CFG[6] CFG[0]
VAXG
VAXG
VAXG
VAXG VAXG
VAXG VAXG
VAXG VAXG
VAXG VAXG
VAXG VAXG
VSS
VSS
VSS
VSS
VSS VSS
E
PEG_ICOMPI
PEG_RX#[0]
PEG_RX#[6]
PEG_RX[7]
RSVD_NCTF
VAXG VAXG
VSS
VSS VSS
VSS
VSS
VSS VSS VSS
D
C
B
A
GFX_VID[4]
PEG_ICOMPO
PEG_RX#[1]
PEG_RX#[3]
PEG_RX#[5]
PEG_RX[5]
PEG_RX[0]
PEG_TX[0]
PEG_RX[6]
RSVD_NCTF
COMP3
VAXG VAXG
VSS
VSS
VSS
VSSAXG_SENSE
GFX_VID[1]
PEG_RCOMPO
PEG_RX#[4]
PEG_RX[1]
PEG_RX[3]
COMP2
VAXG VAXG
VSS
VSS
VSS
PEG_RX[2]
7
VAXG_SENSE
PEG_RX#[2]
RSVD_NCTF
PEG_RBIAS
PEG_RX[4]
VAXG
VAXG
VAXG
VAXG
RSVD
VSS
20 19 18 17 16 15 14 13 12 11 10
9
8
6
5
4
3
2
1
Datasheet, Volume 1
79
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
DMI_RX[3]
Pin # Buffer Type
Dir.
BCLK_ITP
BCLK_ITP#
BCLK[0]
BCLK[1]
BCLK#[0]
BCLK#[1]
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
CATERR#
CFG[0]
AK39
AK40
AA7
AA8
AA6
Y8
CMOS
CMOS
CMOS
Diff Clk
CMOS
Diff Clk
GTL
O
W3
T1
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
I
I
O
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
FC_AE38
I
U2
I
I
V1
I
I
W2
L1
I
I
O
O
O
O
O
O
O
O
AL33
AL32
AK33
AK32
AM31
AL30
AK30
AK31
AG39
E8
I/O
N3
GTL
I/O
N1
GTL
I/O
R2
GTL
I/O
M1
N2
GTL
I/O
GTL
I/O
P1
GTL
I/O
R3
GTL
I/O
AE38
AG40
AC4
AC3
AC2
AD4
AD3
U6
GTL
I/O
I
FC_AG40
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
CMOS
CMOS
CMOS
CMOS
CMOS
FDI
I
CFG[1]
G8
I
I
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[2]
K10
K8
I
I
I
FDI_LSYNC[0]
FDI_LSYNC[1]
FDI_TX[0]
I
J12
I
I
L8
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
K9
I
FDI_TX[1]
V4
FDI
K12
H7
I
FDI_TX[2]
U8
FDI
I
FDI_TX[3]
W8
W5
R8
FDI
L11
E10
F10
H10
H9
I
FDI_TX[4]
FDI
I
FDI_TX[5]
FDI
CFG[3]
I
FDI_TX[6]
Y4
FDI
CFG[4]
I
FDI_TX[7]
Y6
FDI
CFG[5]
I
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
GFX_DPRSLPVR
GFX_IMON
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
U5
FDI
CFG[6]
E9
I
V3
FDI
CFG[7]
F9
I
U7
FDI
CFG[8]
G12
H12
B39
AF36
AF2
B11
C11
AL40
AF3
AG3
R1
I
W7
W4
R7
FDI
CFG[9]
I
FDI
CGC_TP_NCTF
COMP0
FDI
Analog
Analog
Analog
Analog
I
I
Y3
FDI
COMP1
Y5
FDI
COMP2
I
J10
F6
CMOS
Analog
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
COMP3
I
DBR#
O
O
O
I
G10
B12
E12
E11
C12
G11
O
O
O
O
O
O
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
Analog
Analog
DMI
U3
DMI
I
U1
DMI
I
80
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
GFX_VID[6]
GFX_VR_EN
ISENSE
J11
F12
T40
AG35
AA3
AA4
D11
C10
A11
B10
C9
B8
CMOS
O
O
I
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
PM_SYNC
L6
M4
K7
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
CMOS
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
CMOS
Analog
PECI
Asynch
I/O
I
N6
M8
R5
PEG_CLK
Diff Clk
PEG_CLK#
Diff Clk
I
PEG_ICOMPI
PEG_ICOMPO
PEG_RBIAS
PEG_RCOMPO
PEG_RX[0]
PEG_RX[1]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_TX[0]
PEG_TX[1]
Analog
I
E5
Analog
I
F3
Analog
I
G6
H4
F7
Analog
I
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
I
I
J6
G1
J3
I
K3
I
H8
D7
E6
J1
I
L2
I
P3
I
L5
T3
I
M3
L7
A7
I
B6
I
N5
N8
R6
A5
I
B4
I
C3
D2
E1
I
F5
I
F4
I
G5
H3
G7
J5
G3
D9
C8
H1
J2
I
I
I
I
K4
I
J8
K1
I
AB5
AB4
AH39
AJ38
AK37
AH34
L3
I
CMOS
I
P4
I
CMOS
I
T4
I
PRDY#
Asynch GTL
Asynch GTL
Asynch GTL
O
I
A6
I
PREQ#
C6
B5
I
PROCHOT#
PSI#
I/O
O
O
I
I
AG38 Asynch CMOS
AL39 Asynch CMOS
C4
D3
E2
I
RESET_OBS#
RSTIN#
I
AF34
A12
CMOS
I
RSVD
F1
I
RSVD
AD2
AE2
G2
C7
E7
I
RSVD
O
O
RSVD
AH40
AJ39
RSVD
Datasheet, Volume 1
81
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
RSVD_NCTF
Pin # Buffer Type
Dir.
RSVD
AK12
AK13
AK14
AK15
AK16
AK18
AK25
AK26
AK27
AK28
AK29
AL12
AL14
AL15
AL17
AL18
AL26
AL27
AL29
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM25
AM26
AM27
AM28
AM29
AM30
L12
B3
C2
RSVD
RSVD_NCTF
RSVD_NCTF
RSVD_TP
RSVD
D1
RSVD
AN11
RSVD
SA_BS[0]
AV20
AU19
AU12
AU22
AR22
AP18
AN21
AP19
AR21
AN18
AP21
AN19
AU10
AW10
AV10
AY10
AV21
AW24
AU21
AU23
AK22
AM22
AL23
AK23
AJ2
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
RSVD
SA_BS[1]
RSVD
SA_BS[2]
O
RSVD
SA_CAS#
O
RSVD
SA_CK[0]
SA_CK[1]
O
RSVD
O
RSVD
SA_CK[2]
SA_CK[3]
O
RSVD
O
RSVD
SA_CK#[0]
SA_CK#[1]
SA_CK#[2]
SA_CK#[3]
SA_CKE[0]
SA_CKE[1]
SA_CKE[2]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_CS#[4]
SA_CS#[5]
SA_CS#[6]
SA_CS#[7]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQ[0]
SA_DQ[1]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
O
RSVD
AN1
O
RSVD
AU1
O
RSVD
AV6
I/O
O
RSVD
AN29
AW31
AU35
AT38
AH1
RSVD
O
RSVD
O
RSVD
M12
O
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
A4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AU40
AV1
AJ4
AR3
AV39
AW2
AR2
AM3
AW38
AY3
AM2
AP1
AY37
AR4
82
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[2]
AT4
AU2
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[6]
AT39
AT40
AN38
AN39
AK1
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AW3
AW4
AL2
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[3]
AT3
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_DQ[7]
AU38
AU39
AP39
AP40
AK2
AT1
AV2
AV4
AW5
AY5
SA_DQ[8]
AN3
AU8
SA_DQ[9]
AN2
AY8
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_DQS[8]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS#[8]
SA_ECC_CB[0]
SA_ECC_CB[1]
SA_ECC_CB[2]
SA_ECC_CB[3]
SA_ECC_CB[4]
SA_ECC_CB[5]
SA_ECC_CB[6]
SA_ECC_CB[7]
SA_MA[0]
AK3
AU5
AP2
AV5
AU4
AL1
AY6
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[4]
AV7
AR28
AV32
AW36
AR39
AL10
AJ3
AW7
AN27
AT28
AP28
AP30
AN26
AR27
AR29
AN30
AG2
AP3
AU3
AW6
AT29
AW32
AV35
AR38
AM10
AP10
AN10
AR11
AP11
AK9
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[5]
AU30
AU31
AV33
AU34
AV30
AW30
AU33
AW33
AW35
AY35
AH2
AL9
AK11
AM11
AW18
AY15
AT19
AU13
AW11
AU24
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
AV37
AU37
AY34
AW34
AV36
AW37
SA_MA[1]
O
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
O
O
O
O
Datasheet, Volume 1
83
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
SB_DM[4]
Pin # Buffer Type
Dir.
SA_MA[14]
SA_MA[15]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_RAS#
SA_WE#
AT11
AR10
AV15
AU15
AW14
AY13
AV14
AW13
AU14
AW12
AV23
AV24
AW23
AY24
AT20
AT22
AU25
AW25
AV12
AW27
AR17
AT15
AN17
AR19
AR16
AR15
AN16
AR18
AW8
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AN24
AN32
AM33
AK35
AD7
AD6
AK6
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQ[0]
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SB_DQ[1]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[2]
AL4
AG6
AG4
AJ7
AK7
AL6
AN5
AP6
AR5
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_CK[0]
SB_CK[1]
SB_CK[2]
SB_CK[3]
SB_CK#[0]
SB_CK#[1]
SB_CK#[2]
SB_CK#[3]
SB_CKE[0]
SB_CKE[1]
SB_CKE[2]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_CS#[4]
SB_CS#[5]
SB_CS#[6]
SB_CS#[7]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
AH8
AL5
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[3]
AM4
AN7
AP5
AT6
AR7
AR9
AM8
AN8
AR6
AJ8
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[4]
AL8
AY9
AT9
AU9
AN23
AP23
AR25
AR26
AT23
AP22
AP25
AT26
AC7
AV9
AY27
AW29
AV26
AV29
AM23
AM24
AL24
AK24
AE4
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
AT32
AP31
AR33
AM32
AT31
AH4
AM7
AT7
84
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[5]
AR31
AR34
AT33
AR35
AT36
AC6
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SB_ECC_CB[2]
SB_ECC_CB[3]
SB_ECC_CB[4]
SB_ECC_CB[5]
SB_ECC_CB[6]
SB_ECC_CB[7]
SB_MA[0]
SB_MA[1]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_RAS#
AN15
AP14
AM12
AN12
AN14
AP13
AU20
AU18
AY25
AW16
AW15
AW28
AY12
AV11
AV18
AU17
AY18
AV17
AW17
AU16
AT17
AY16
AU27
AU29
AV27
AU28
AW26
AU26
AK38
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[6]
AN33
AP36
AP34
AT35
AN34
AP37
AL35
AM35
AJ36
AJ37
AF5
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_DQ[7]
AN35
AM34
AJ35
AL36
AE6
SB_DQ[8]
AG5
SB_DQ[9]
AH7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_DQS[8]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS#[8]
SB_ECC_CB[0]
SB_ECC_CB[1]
AF4
AH6
AN6
AR8
SB_WE#
AT25
AP32
AR36
AL37
AR14
AE5
SKTOCC#
SM_DRAMPWROK
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
TAPPWRGOOD
TCK
AH37 Asynch CMOS
AV8
AG1
AD1
AE1
DDR3
Analog
Analog
Analog
O
I
I
I
AJ5
AK34 Asynch CMOS
O
I
AM6
AN37
AM37
AF37
AM38
AF38
AF35
AN40
AM39
A14
TAP
TAP
AP8
TDI
I
AR24
AR32
AR37
AM36
AR13
AR12
AT13
TDI_M
TAP
I
TDO
TAP
O
O
O
I
TDO_M
TAP
THERMTRIP#
TMS
Asynch GTL
TAP
TRST#
TAP
I
VAXG
PWR
Datasheet, Volume 1
85
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
VAXG
Pin # Buffer Type
Dir.
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
A15
A17
A18
B14
B15
B17
B18
C14
C15
C17
C18
C20
C21
D14
D15
D17
D18
D20
D21
E14
E15
E17
E18
E20
F14
F15
F17
F18
F19
G14
G15
G17
G18
H14
H15
H17
J14
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
L16
M14
M15
M16
A13
A23
A24
A26
A27
A33
A35
A36
B23
B25
B26
B28
B29
B31
B32
B34
B35
B37
B38
C23
C24
C25
C27
C28
C30
C31
C33
C34
C36
C37
C39
D23
D24
D26
D27
D29
D30
D32
D33
D35
PWR
PWR
PWR
PWR
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VAXG
VAXG
VAXG
VAXG_SENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J15
J16
K14
K15
K16
L14
L15
86
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D36
D38
D39
E22
E23
E25
E26
E28
E29
E31
E32
E34
E35
E37
E38
E40
F21
F22
F24
F25
F27
F28
F30
F31
F33
F34
F36
F37
F39
F40
G20
G21
G23
G24
G26
G27
G29
G30
G32
G33
G35
G36
G38
G39
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H19
H20
H22
H23
H25
H26
H28
H29
H31
H32
H34
H35
H37
H38
H40
J18
J19
J21
J22
J24
J25
J27
J28
J30
J31
J33
J34
J36
J37
J39
J40
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Datasheet, Volume 1
87
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
K36
K38
K39
L17
L19
L20
L22
L23
L25
L26
L28
L29
L31
L32
L34
L35
L37
L38
L40
M17
M19
M21
M22
M24
M25
M27
M28
M30
M33
M34
M36
M37
M39
M40
N33
N35
N36
N38
N39
P33
P34
P35
P36
P37
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
P38
P39
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
PWR
PWR
PWR
Asynch
Asynch
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
P40
R33
R34
R35
R36
R37
R38
R39
R40
VCC_NCTF
VCC_NCTF
VCC_SENSE
VCCPLL
A38
C40
T35
AF7
VCCPLL
AF8
VCCPLL
AG8
AH35
AH36
AJ11
AJ13
AJ15
AT10
AT18
AT21
AU11
AV13
AV16
AV19
AV22
AV25
AV28
AW9
AY11
AY14
AY17
AY23
AY26
U40
VCCPWRGOOD_0
VCCPWRGOOD_1
VDDQ
I
I
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VID[0]/MSID[0]
VID[1]/MSID[1]
VID[2]/MSID[2]
VID[3]/CSC[0]
VID[4]/CSC[1]
VID[5]/CSC[2]
I/O
I/O
I/O
I/O
I/O
I/O
U39
U38
U37
U36
U35
88
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
VID[6]
VID[7]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U34
U33
CMOS
CMOS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ28
AJ30
AJ33
AJ34
AJ40
AJ6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
A25
A28
A34
A37
AJ9
AA5
AK10
AK17
AK36
AK4
AB3
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AB6
AK5
AK8
AL11
AL13
AL16
AL19
AL22
AL25
AL28
AL3
AB8
AC1
AD5
AD8
AE3
AL31
AL34
AL38
AL7
AE37
AE7
AF1
AM1
AF40
AF6
AM40
AM5
AG34
AG36
AG7
AH3
AM9
AN13
AN20
AN22
AN25
AN28
AN31
AN36
AN4
AH33
AH38
AH5
AJ1
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AN9
AP12
AP15
AP16
AP17
AP20
AP24
Datasheet, Volume 1
89
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP26
AP27
AP29
AP33
AP35
AP38
AP4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B9
C13
C16
C19
C22
C26
C29
C32
C35
C38
C5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AP7
AP9
AR1
AR20
AR23
AR30
AR40
AT12
AT14
AT16
AT2
D10
D12
D13
D16
D19
D22
D25
D28
D31
D34
D37
D4
AT24
AT27
AT30
AT34
AT37
AT5
D40
D5
AT8
AU32
AU36
AU6
D6
D8
E13
E16
E19
E21
E24
E27
E3
AU7
AV3
AV31
AV34
AV38
AY33
AY36
AY4
E30
E33
E36
E39
E4
AY7
B16
B24
B27
F11
F13
F16
F2
B30
B33
B36
B7
F20
90
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F23
F26
F29
F32
F35
F38
F8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K11
K13
K19
K2
K22
K25
K28
K31
K34
K37
K40
K5
G13
G16
G19
G22
G25
G28
G31
G34
G37
G4
K6
L13
L18
L21
L24
L27
L30
L33
L36
L39
L4
G40
G9
H11
H13
H16
H18
H2
H21
H24
H27
H30
H33
H36
H39
H5
L9
M13
M18
M2
M20
M23
M26
M29
M32
M35
M38
M5
H6
J13
J17
J20
J23
J26
J29
J32
J35
J38
J4
M6
M7
N34
N37
N4
N40
P2
J7
P5
Datasheet, Volume 1
91
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
Pin Name
Pin # Buffer Type
Dir.
VSS
R4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Analog
Analog
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
AE33
AE34
AE39
AE40
AE8
AF33
AG33
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ32
AK19
AK20
AK21
AL20
AL21
L10
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VSS
T33
VSS
T36
VSS
T37
VSS
T38
VSS
T39
VSS
T5
VSS
U4
VSS
V5
VSS
W33
W34
W35
W36
W37
W38
Y7
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS_SENSE_VTT
VSSAXG_SENSE
VTT
T34
AE36
B13
AA33
AA34
AA35
AA36
AA37
AA38
AB7
VTT
VTT
VTT
M10
M11
M9
VTT
VTT
VTT
N7
VTT
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
AC5
P6
VTT
P7
VTT
P8
VTT
T2
VTT
T6
VTT
T7
VTT
T8
VTT
V2
VTT
V33
V34
V35
V36
V37
V38
V39
V40
V6
VTT
AC8
VTT
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
VTT
VTT
VTT
VTT
VTT
VTT
VTT
V7
92
Datasheet, Volume 1
Processor Land and Signal Information
Table 8-2.
Processor Pin List by Pin
Name
Pin Name
Pin # Buffer Type
Dir.
VTT
V8
W1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
CMOS
Analog
VTT
VTT
W6
VTT
Y33
Y34
Y35
Y36
Y37
Y38
AF39
AE35
VTT
VTT
VTT
VTT
VTT
VTT_SELECT
VTT_SENSE
VTTPWRGOOD
O
I
AG37 Asynch CMOS
§ §
Datasheet, Volume 1
93
Processor Land and Signal Information
94
Datasheet, Volume 1
相关型号：
©2020 ICPDF网 联系我们和版权申明