BX80526C1000256/SL4MF

Intel^®Pentium^®III Processor Based on 0.13

Micron Process Up to 1.33 GHz

Datasheet

■ Available at 1.0, 1.13, 1.20, 1.33 GHz.

■ Power Management capabilities

—System Management mode

—Multiple low-power states

System bus frequency at 133 MHz

■ 256 KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache with Error

Correcting Code (ECC))

■ Dual Independent Bus (DIB) architecture:

Separate dedicated external System Bus and

dedicated internal high-speed cache bus

■ Optimized for 32-bit applications running on

advanced 32-bit operating systems

■ Flip Chip Pin Grid Array (FC-PGA2) packaging

technology; FC-PGA2 processors deliver high

performance with improved handling protection

and socketability

■ Internet Streaming SIMD Extensions for

enhanced video, sound and 3D performance

■ Integrated high performance 16 KB instruction

■ Binary compatible with applications running

on previous members of the Intel

microprocessor line

■ Dynamic execution micro architecture

■ Data Prefetch Logic

and 16 KB data, nonblocking, level one cache

■ 256 KB Integrated Full Speed level two cache

allows for low latency on read/store operations

■ Quad Quadword Wide (256 bit) cache data bus

provides extremely high throughput on read/

store operations.

■ 8-way cache associativity provides improved

cache hit rate on reads/store operations.

■ Error-correcting code for System Bus data

The Intel^®Pentium^®III processor based on 0.13 micron process is designed for high-performance

desktops and for workstations and servers. It is binary compatible with previous Intel Architecture

processors. The Pentium^®III processor on 0.13 micron process provides great performance for

applications running on advanced operating systems such as Windows* 98, Windows NT*, Windows*

2000, Windows Me*, Windows XP*, and Linux. This is achieved by integrating the best attributes of

Intel processors—the dynamic execution, Dual Independent Bus architecture plus Intel MMX™

technology and Internet Streaming SIMD Extensions—bringing a new level of performance for systems

buyers. The Pentium^®III processor based on 0.13 micron process extends the power of the Pentium^®III

processor with performance headroom for business media, communication and internet capabilities.

Systems based on Pentium^®III processors based on 0.13 micron process also include the latest features

to simplify system management and lower the cost of ownership for large and small business

environments. The Pentium^®III processor based on 0.13 micron process offers great performance for

today’s and tomorrow’s applications.

December 2001

Document Number: 249765-002

Information in this document is provided in connection with Intel^®products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel^®Pentium^®III processor may contain design defects or errors known as errata which may cause the product to deviate from published spec-

ifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling

1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

Intel, Celeron, Pentium, and MMX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun-

tries.

*Other names and brands may be claimed as the property of others.

Datasheet

Intel^®Pentium^®III Processor Based on 0.13 Micron Process Up to 1.33 GHz

Contents

1.0

Introduction.........................................................................................................................9

1.1

Terminology.........................................................................................................10

1.1.1 Package and Processor Terminology ....................................................10

1.1.2 Processor Naming Convention...............................................................11

Related Documents.............................................................................................11

1.2

2.0

Electrical Specifications....................................................................................................12

2.1

2.2

Processor System Bus and VREF........................................................................12

Clock Control and Low Power States..................................................................13

2.2.1 Normal State—State 1 ...........................................................................14

2.2.2 AutoHALT Powerdown State—State 2...................................................14

2.2.3 Stop-Grant State—State 3 .....................................................................14

2.2.4 HALT/Grant Snoop State—State 4 ........................................................15

2.2.5 Sleep State—State 5..............................................................................15

2.2.6 Deep Sleep State—State 6 ....................................................................15

2.2.7 Clock Control..........................................................................................16

Power and Ground Pins ......................................................................................16

2.3.1 Phase Lock Loop (PLL) Power...............................................................17

Decoupling Guidelines ........................................................................................17

2.4.1 Processor VCC_COREDecoupling............................................................17

Processor System Bus Clock and Processor Clocking.......................................18

Voltage Identification...........................................................................................19

Processor System Bus Unused Pins...................................................................22

Processor System Bus Signal Groups ................................................................22

2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................23

2.8.2 System Bus Frequency Select Signals ..................................................24

Test Access Port (TAP) Connection....................................................................25

Maximum Ratings................................................................................................25

Processor Voltage Level Specifications ..............................................................25

AGTL System Bus Specifications........................................................................30

System Bus Timing Specifications ......................................................................31

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

3.0

Signal Quality Specifications............................................................................................42

3.1

BCLK/BCLK# & PICCLK Signal Quality Specifications and

Measurement Guidelines ....................................................................................42

AGTL Signal Quality Specifications and Measurement Guidelines.....................43

3.2.1 Overshoot/Undershoot Guidelines .........................................................44

3.2.1.1 Overshoot/Undershoot Magnitude ............................................44

3.2.1.2 Overshoot/Undershoot Pulse Duration......................................45

3.2.1.3 Activity Factor............................................................................45

3.2.1.4 Reading Overshoot/Undershoot Specification Tables...............46

3.2.1.5 Determining if a System Meets the Overshoot/Undershoot

3.2

Specifications ............................................................................47

3.3

Non-AGTL Signal Quality Specifications and Measurement Guidelines.............48

3.3.1 Overshoot/Undershoot Guidelines .........................................................49

3.3.2 Ringback Specification ...........................................................................50

3.3.3 Settling Limit Guideline...........................................................................50

Datasheet

3

Intel^®Pentium^®III Processor Based on 0.13 Micron Process Up to 1.33 GHz

4.0

5.0

6.0

Thermal Specifications and Design Considerations.........................................................51

4.1

Thermal Specifications........................................................................................51

4.1.1 THERMTRIP# Requirement...................................................................51

4.1.2 Thermal Diode........................................................................................52

Thermal Metrology ..............................................................................................52

4.2

Mechanical Specifications................................................................................................53

5.1

5.2

5.3

5.4

FC-PGA2 Mechanical Specifications ..................................................................53

Recommended Mechanical Keep-Out Zones .....................................................55

Processor Markings ............................................................................................56

Processor Signal Listing......................................................................................57

Boxed Processor Specifications.......................................................................................68

6.1

6.2

6.3

Mechanical Specifications...................................................................................69

6.1.1 Mechanical Specifications for the FC-PGA2 Package ...........................69

6.1.2 Boxed Processor Heatsink Weight.........................................................70

Thermal Specifications........................................................................................71

6.2.1 Boxed Processor Cooling Requirements ...............................................71

6.2.2 Boxed Processor Thermal Cooling Solution Clip ...................................71

Electrical Requirements for the Boxed Intel^®Pentium^®III Processor

Based on 0.13 micron Process ...........................................................................72

6.3.1 Electrical Requirements .........................................................................72

7.0

Processor Signal Description...........................................................................................74

7.1

7.2

Alphabetical Signals Reference ..........................................................................74

Signal Summaries...............................................................................................81

4

Datasheet

Intel^®Pentium^®III Processor Based on 0.13 Micron Process Up to 1.33 GHz

Figures

1

2

3

4

5

6

7

8

Integrated Heat Spreader (IHS) ............................................................................9

AGTL Bus Topology in a Uniprocessor Configuration.........................................13

Stop Clock State Machine...................................................................................13

PLL Filter Specification........................................................................................17

Differential/Single-Ended Clocking Example.......................................................18

VTT Power Good and Bus Select Interconnect Diagram.....................................21

BSEL[1:0] Example for a System Design............................................................24

Vcc Static and Transient Tolerance ....................................................................28

Clock Waveform..................................................................................................36

BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform ..............................37

System Bus Valid Delay Timings ........................................................................37

System Bus Setup and Hold Timings..................................................................38

System Bus Reset and Configuration Timings....................................................38

Platform Power-On Sequence and Timings........................................................39

Power-On Reset and Configuration Timings.......................................................40

Test Timings (TAP Connection) ..........................................................................40

Test Reset Timings .............................................................................................41

BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins ...........43

Low to High AGTL Receiver Ringback Tolerance...............................................44

Maximum Acceptable AGTL Overshoot/Undershoot Waveform.........................48

Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback ......................48

Package Dimensions...........................................................................................53

Volumetric Keep-Out...........................................................................................55

Component Keep-Out .........................................................................................55

Top Side Processor Markings .............................................................................56

Intel^®Pentium^®III Processor Based on 0.13 micron Process Pinout .................57

Conceptual Boxed Intel^®Pentium^®III Processor Based on 0.13 micron

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Process for the PGA370 Socket..........................................................................68

Comparison between FC-PGA and FC-PGA2 package......................................69

Side View of Space Requirements for the Boxed Processor ..............................70

Dimensions of Mechanical Step Feature in Heatsink Base.................................70

Thermal Airspace Requirement for all Boxed Intel^®Pentium^®III Processor

Based on 0.13 micron Process Fan Heatsinks in the PGA370 Socket...............71

Boxed Processor Fan Heatsink Power Cable Connector Description.................72

Motherboard Power Header Placement Relative to the Boxed

28

29

30

31

32

33

Intel^®Pentium^®III Processor Based on 0.13 micron Process ............................73

Datasheet

5

Intel^®Pentium^®III Processor Based on 0.13 Micron Process Up to 1.33 GHz

Tables

1

Processor Identification.......................................................................................11

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

System Bus Clock in Deep Sleep Mode (Differential Mode only) .......................16

Voltage Identification Definition ..........................................................................20

System Bus Signal Groups ................................................................................23

Frequency Select Truth Table for BSEL[1:0] ......................................................24

Absolute Maximum Ratings ................................................................................25

Voltage and Current Specifications ....................................................................26

Power Supply Current Slew Rate (dIcccore/dt)...................................................27

Vcc Static and Transient Tolerance ....................................................................28

AGTL Signal Group Levels Specifications .........................................................29

Non-AGTL Signal Group Levels Specifications .................................................29

3.3 Volt CMOS Output Signal Group DC Specifications .....................................30

Processor AGTL Bus Specifications ..................................................................30

System Bus Timing Specifications (Single-Ended Clock)...................................31

System Bus Timing Specifications (Differential Clock) .......................................32

Valid System Bus to Core Frequency Ratios .....................................................33

System Bus Timing Specifications (AGTL Signal Group) ...................................33

System Bus Timing Specifications (CMOS Signal Group)..................................33

System Bus Timing Specifications (Reset Conditions) ......................................34

System Bus Timing Specifications (APIC Clock and APIC I/O) ..........................34

System Bus Timing Specifications (TAP Connection) ........................................35

Platform Power-On Timings................................................................................36

BCLK (Single-Ended Clock Mode) Signal Quality Specifications for

Simulation at the Processor Pins ........................................................................42

BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality

Specifications for Simulation at the Processor Pins ...........................................42

AGTL Signal Groups Ringback Tolerance Specifications at the

24

25

Processor Pins ...................................................................................................43

Example Platform Information.............................................................................46

133 MHz AGTL Signal Group Overshoot/Undershoot Tolerance ......................47

33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance........................49

Signal Ringback Specifications for Non-AGTL Signal Simulation at

26

27

28

29

the Processor Pins .............................................................................................50

30

Intel^®Pentium^®III Processor Based on 0.13 micron Process

Thermal Design Power .......................................................................................51

THERMTRIP# Time Requirement.......................................................................51

Thermal Diode Parameters .................................................................................52

Thermal Diode Interface......................................................................................52

Intel^®Pentium^®III Processor Based on 0.13 micron Process

31

32

33

34

Package Dimensions ..........................................................................................54

Processor Case Loading Parameters .................................................................54

Signal Listing in Order by Signal Name ..............................................................58

Signal Listing in Order by Pin Number ................................................................63

Boxed Processor Fan Heatsink Spatial Dimensions...........................................70

Fan Heatsink Power and Signal Specifications...................................................72

Signal Description ...............................................................................................74

Output Signals.....................................................................................................81

Input Signals .......................................................................................................81

Input/Output Signals (Single Driver)....................................................................83

Input/Output Signals (Multiple Driver) .................................................................83

35

36

37

38

39

40

41

42

43

44

6

Datasheet

Intel^®Pentium^®III Processor Based on 0.13 Micron Process Up to 1.33 GHz

Revision History

Revision

Date

Description

-001

-002

•

Initial Release

December 2001

Added 1.33 GHz processor

Datasheet

7

Intel^®Pentium^®III Processor Based on 0.13 Micron Process Up to 1.33 GHz

This page is intentionally left blank.

8

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

1.0

Introduction

The Intel^®Pentium^®III processor based on 0.13 micron process for the PGA370 socket is the next

member of the P6 family, in the Intel IA-32 processor line and hereafter will be referred to as

simply “the processor”. The Pentium^®III processor based on 0.13 micron process continues in the

package technology called “flip-chip pin grid array” but contains an Integrated Heat Spreader

(IHS) (see Figure 1). The flip-chip with IHS package will be labeled as FC-PGA2 and utilizes the

same 370-pin zero insertion force socket (PGA370). Thermal solutions contact the IHS directly for

the FC-PGA2 package and not to the bare-die as with the FC-PGA attachment.

The Pentium^®III processor based on 0.13 micron process, like its predecessors in the P6 family of

processors, implements a Dynamic Execution microarchitecture—a unique combination of

multiple branch prediction, data flow analysis, and speculative execution. This enables these

processors to deliver higher performance than the Intel Pentium processor, while maintaining

binary compatibility with all previous Intel Architecture processors. The processor also executes

Intel^®MMX^TMtechnology instructions for enhanced media and communication performance just

as it’s predecessor, the Intel Pentium III processor. Additionally, the Pentium III processor based on

0.13 micron process executes Streaming SIMD (single-instruction, multiple data) Extensions for

enhanced floating point and 3-D application performance. Data Prefetch Logic adds functionality

that anticipates the data needed by the application and pre-loads it into the Advanced Transfer

Cache, further increasing processor and application performance. The processor utilizes multiple

low-power states such as Sleep, and Deep Sleep to conserve power during idle times.

The processor includes an integrated on-die, 256 KB 8-way set associative level-two (L2) cache.

The L2 cache implements the Advanced Transfer Cache Architecture with a 256-bit wide bus.

The processor also includes a 16 KB level one (L1) instruction cache and 16 KB L1 data cache.

These cache arrays run at the full speed of the processor core. The Pentium III processor based on

0.13 micron process for the PGA370 socket has a dedicated L2 cache bus, thus maintaining the

dual independent bus architecture to deliver high bus bandwidth and performance. Memory is

cacheable for 64 GB of addressable memory space, allowing significant headroom for desktop

systems. Refer to the Specification Update document for this processor to determine the

cacheability and cache configuration options for a specific processor. Contact your nearest Intel

Sales Representative for the latest Processor Specification Update.

Figure 1. Integrated Heat Spreader (IHS)

FC-PGA2 w/IHS

FC-PGA

The Pentium III processor based on 0.13 micron process supports a lower voltage differential and

single-ended clocking for the system bus. The previous generation Intel^®Pentium^®III or Intel^®

Celeron^®processors for the PGA370 socket will function in a Pentium III processor based on 0.13

micron process-supported platform, if that platform has been designed to be backward compatible.

In addition, the Pentium III processor based on 0.13 micron process will not function in a previous

generation platform due to incompatible system bus signal levels and clock type. Care must be

taken to ensure the correct processors are installed in the correct PGA370 socket platforms.

Datasheet

9

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

1.1

Terminology

In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a

signal is in the active state (based on the name of the signal) when driven to a low level. For

example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable

interrupt has occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal

is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to

a hex ‘A’ (H= High logic level, L= Low logic level).

The term “system bus” refers to the interface between the processor, system core logic (i.e., the

chipset components), and other bus agents.

1.1.1

Package and Processor Terminology

The following terms are used often in this document and are explained here for clarification:

• Intel^®Pentium^®III Processor based on 0.13 micron process—The entire product including

all internal components. Contains 256 KB of L2 cache and is uni-processor capable only.

• PGA370 socket—370-pin Zero Insertion Force (ZIF) socket which a FC-PGA packaged

processor plugs into.

• FC-PGA—Flip Chip Pin Grid Array. The package technology used on Intel Pentium III

processors based on 0.18 micron technology (CPUID=068xh) for the PGA370 socket. The

FC-PGA package has the processor die exposed.

• FC-PGA2—Flip Chip Pin Grid Array 2. The package technology used on the Pentium III

processor based on 0.13 micron process for the PGA370 socket. The FC-PGA2 package

contains an Integrated Heat Spreader that covers the processor die.

• Advanced Transfer Cache (ATC)—L2 cache architecture used on the Pentium III processors

based on 0.13 micron process. ATC consists of microarchitectural improvements that provide

a higher data bandwidth interface into the processor core that is completely scaleable with the

processor core frequency.

• Keep-out zone—The area on or near a FC-PGA packaged processor that system designs can

not utilize.

• Keep-in zone—The area of a FC-PGA packaged processor that thermal solutions may utilize.

• Processor—For this document, the term processor is the generic form of the Pentium III

processor based on 0.13 micron process for the PGA370 socket in the FC-PGA2 package.

• Processor core—The processor’s execution engine.

• Integrated Heat Spreader (IHS)—The Integrated Heat Spreader (IHS) is a metal cover on

the die and it is an integral part of the processor. The IHS promotes heat spreading away from

the die backside to ease thermal constraints.

The cache and L2 cache are industry designated names.

10

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

1.1.2

Processor Naming Convention

Table 1. Processor Identification

System Bus

Frequency

(MHz)

Core Frequency

(GHz)

L2 Cache Size

(KBs)

L2 Cache

Type

1

Processor

CPUID

2

1A

1.13A

1.20

1.33

1.00

1.13

1.20

1.33

133

256

ATC

06Bxh

NOTES:

®

1. Refer to the Intel Pentium^®III Processor Specification Update for the exact CPUID for each processor.

2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor core.

With ATC, the interface between the processor core and L2 Cache is 256-bits wide, runs at the same

frequency as the processor core and has enhanced buffering.

1.2

Related Documents

The reader of this specification should also be familiar with material and concepts presented in the

following documents ^1,2

:

1

Document

Order Number/Location

®

AP-485, Intel Processor Identification and the CPUID Instruction

AP-589, Design for EMI

241618

243334

243193

243190

243191

243192

244001

243565

244410

245025

298349

®

Intel Architecture Software Developer's Manual

Volume I: Basic Architecture

Volume II: Instruction Set Reference

Volume III: System Programming Guide

P6 Family of Processors Hardware Developer’s Manual

IA-32 Processors and Related Products 1999 Databook

370-Pin Socket (PGA370) Design Guidelines

PGA370 Heat Sink Cooling in MicroATX Chassis

®

3

Intel 815 Chipset Platform For use with the Universal Socket 370 Design Guide

®

Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller

Hub 2 Mobile (ICH2-M) Datasheet

290687

http:/developer.intel.com/

design/PentiumIII/

designgd

®

Intel Pentium III Processor in the FC-PGA2 Package Thermal design

Guidelines

3

CK-815 Clock Synthesizer/Driver Specification

3

CK-408 Clock Synthesizer/Driver Specification

3

VRM 8.5 DC-DC Converter Design Guidelines

®

3

Extensions to the Pentium Pro Processor BIOS Writer’s Guide Revision

NOTES:

1. Unless otherwise noted, this reference material can be found on the Intel Developer’s Website located at

http://developer.intel.com.

®

2. For a complete listing of Intel Pentium III processor reference material, refer to the Intel Developer’s

Website at http://developer.intel.com/design/PentiumIII/.

3. Contact your local sales representative for this document.

Datasheet

11

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.0

Electrical Specifications

2.1

Processor System Bus and VREF

The Pentium III processor based on 0.13 micron process uses the original low voltage signaling of

the Gunning Transceiver Logic (GTL) technology for the system bus. The GTL system bus

operates at 1.25V signal levels versus GTL+ which operates at 1.5 V signal levels. The GTL+

signal technology is used by the Intel Pentium Pro, Intel Pentium II, and Intel Pentium III

processors.

Current P6 family processors vary from the Intel Pentium Pro processor in their output buffer

implementation. The buffers that drive the system bus signals on the Pentium III processor based on

0.13 micron process are actively driven to VTT for one clock cycle after the low to high transition

to improve rise times. These signals are open-drain and require termination to a supply. Because

this specification is different from the standard GTL specification, it is referred to as AGTL, or

Assisted GTL in this and other documentation related to the Pentium III processor based on 0.13

micron process.

AGTL logic and AGTL+ logic are not compatible with each other due to differences with the signal

switching levels. Pentium III processor based on 0.13 micron process cannot be installed into

platforms where the chipset only supports the AGTL+ signal levels. For more information on

AGTL or AGTL+ routing, refer to the appropriate platform design guide.

AGTL inputs use differential receivers that requires a reference voltage (VREF). VREF is used by the

differential receivers to determine if the input signal is a logical 0 or a logical 1. The VREF signal is

typically implemented as a voltage divider on the platform. Noise decoupling is critical for the

VREF signal. Refer to the platform design guide for the recommended decoupling requirements.

Another important item for the AGTL system bus is termination.

System bus termination is used to pull each signal to a high voltage level and to control reflections

on the transmission line. The processor contains on-die termination resistors that provide

termination for one end of the system bus. The other end of the system bus should also be

terminated near the chipset by resistors placed on the platform or on-die termination within the

chipset. It is recommended that the system bus is implemented using Dual-End Termination (DET)

to meet the timings and signal integrity specified by the Pentium III processor based on 0.13 micron

process. Figure 2 is a schematic representation of the AGTL bus topology for the Pentium III

processor based on 0.13 micron process, when the chipset has does not have on-die termination.

Note: The RESET# signal requires a discrete external termination resistor on the system board.

The AGTL bus depends on incident wave switching. Therefore, timing calculations for AGTL

signals are based on flight time as opposed to capacitive deratings. Analog signal simulations of the

system bus, including trace lengths, is highly recommended especially when not following the

recommended layout guidelines.

12

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 2. AGTL Bus Topology in a Uniprocessor Configuration

Processor

Chipset

I/O

Note: RESET# requires external termination.

Note: Refer to appropriate design guide for platform specific termination.

2.2

Clock Control and Low Power States

Processors allow the use of Sleep, and Deep Sleep states to reduce power consumption by stopping

the clock to internal sections of the processor, depending on each particular state. See Figure 3 for a

visual representation of the processor low power states.

Figure 3. Stop Clock State Machine

HALT Instruction and

HALT Bus Cycle Generated

1. Normal State

2. Auto HALT Power Down State

BCLK running.

INIT#, BINIT#, INTR,

SMI#, RESET#

Normal execution.

Snoops and interrupts allowed.

STPCLK# Asserted

STPCLK# De-asserted

STPCLK#

Asserted

STPCLK#

De-asserted

Snoop

Event

Occurs

Snoop

Event

Serviced

and Stop-Grant State

entered from

AutoHALT

Snoop Event Occurs

Snoop Event Serviced

3. Stop Grant State

4. HALT/Grant Snoop State

BCLK running.

Snoops and interrupts allowed.

Service snoops to caches.

SLP#

Asserted

De-asserted

5. Sleep State

BCLK running.

No snoops or interrupts allowed.

BCLK

Input

Stopped

Restarted

6. Deep Sleep State

BCLK stopped.

No snoops or interrupts allowed.

PCB757a

Datasheet

13

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep

Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (Hex), bit 26

must be set to a 1 (this is the power on default setting) for the processor to stop all internal clocks

during these modes. For more information, see the Intel Architecture Software Developer’s

Manual, Volume 3: System Programming Guide.

2.2.1

2.2.2

Normal State—State 1

This is the normal operating state for the processor.

AutoHALT Powerdown State—State 2

AutoHALT is a power state entered when the processor executes the HALT instruction. The

processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI,

INTR). RESET# causes the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,

Volume III: System Programmer's Guide for more information.

FLUSH# is serviced during the AutoHALT state, and the processor will return to the AutoHALT

state.

The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.

When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT

state.

2.2.3

Stop-Grant State—State 3

The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.

Since the AGTL signal pins receive power from the system bus, these pins should not be driven

(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the system bus should be driven to the inactive state.

BINIT# and FLUSH# are not serviced during the Stop-Grant state.

RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant

state. A transition back to the Normal state occurs with the deassertion of the STPCLK# signal.

A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the

system bus (see Section 2.2.4). A transition to the Sleep state (see Section 2.2.5) occurs with the

assertion of the SLP# signal.

While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] are latched by the processor, and only

serviced when the processor returns to the Normal state. Only one occurrence of each event is

recognized and serviced upon return to the Normal state.

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Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.2.4

2.2.5

HALT/Grant Snoop State—State 4

The processor responds to snoop transactions on the system bus while in Stop-Grant state or in

AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant

Snoop state. The processor stays in this state until the snoop on the system bus has been serviced

(whether by the processor or another agent on the system bus). After the snoop is serviced, the

processor returns to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

Sleep State—State 5

The Sleep state is a very low power state in which the processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be

entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,

causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or

AutoHALT states.

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state cause

unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)

are allowed on the system bus while the processor is in Sleep state. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through

Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#

and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the

processor correctly executes the reset sequence.

While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep

state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep state, the SLP# pin can be

deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum

assertion of one BCLK period.

2.2.6

Deep Sleep State—State 6

The Deep Sleep state is the lowest power state the processor can enter while maintaining context.

The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from

the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is

stopped. BCLK and BCLK# have to be separated by at least 0.2 V during the Deep Sleep State.

Stopping of the BCLK input lowers the overall current consumption to leakage levels.

To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL

stabilization) must occur before the processor can be considered to be in the Sleep state. Once in

the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals are allowed on the system bus

while the processor is in Deep Sleep state. Any transition on an input signal before the processor

has returned to Stop-Grant state will result in unpredictable behavior.

Datasheet

15

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 2. System Bus Clock in Deep Sleep Mode (Differential Mode only)¹

Symbol

Parameter

Min

0.4

0

Max

Units

Notes

V

BCLK Voltage Level when not active

BCLK# Voltage Level when not active

1.45

V

2

BCLK

V

–V

V

BCLK – 0.2

BCLK

BCLK#

NOTES:

1. The values in this table are based on differential probe measurement of the BCLK.

2. The DC voltage level specified must be maintained when the system bus clock is not active (e.g., Deep Sleep

Mode). V has to be 200 mV less than V

BCLK#

BCLK.

2.2.7

Clock Control

BCLK provides the clock signal for the processor and on-die L2 cache. During AutoHALT Power

Down and Stop-Grant states, the processor will process a system bus snoop. The processor does not

stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into

the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.

When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop

transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the

Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is

restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor

has re-entered Sleep state).

PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.

PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep

Sleep state to the Sleep state, PICCLK must be restarted with BCLK.

2.3

Power and Ground Pins

The operating voltage for the Pentium III processor based on 0.13 micron process is the same for

the core and the L2 cache. VCC_COREis defined as the power pins that supply voltage to the

processor’s core and cache. The Voltage Regulator Module (VRM) or Voltage Regulator are

controlled by the five voltage identification (VID) signals driven by the processor. The VID signals

specify the voltage required by the processor core. Refer to Section 2.6 for further details on the

VID voltage settings.

The Pentium III processor based on 0.13 micron process has 74 VCC_CORE, 7 VREF, 20 VTT,

VCC_CMOS1.5, VCC_CMOS1.8,VCC_CMOS2.0and 74 VSS inputs. The VREF inputs are used as the AGTL

reference voltage for the processor. The VTT inputs (1.25V) are used to provide an AGTL

termination voltage to the processor. VCC_CMOS1.5and VCC_CMOS1.8and VCC_CMOS2.0are not

voltage input pins to the processor but rather voltage sources for the pullup resistors which are

connected to CMOS (non-AGTL) input/output signals driven to/from the processor. The VSS

inputs are ground pins for the processor core and L2 cache.

On the platform, all VCC_COREpins must be connected to a voltage island (an island is a portion of

a power plane that has been divided, or an entire plane) to minimize any voltage drop that may

occur due to trace impedance. It is also highly recommended for the platform to provide either a

voltage island or a wide trace for the VTT pins. Similarly, all Vss pins must be connected to a

system ground plane. These recommendations can be found in the platform design guide layout

section.

16

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Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.3.1

Phase Lock Loop (PLL) Power

It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.

A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,

decoupled power source for the internal PLL. Refer to the Phase Lock Loop Power section in the

appropriate platform design guide for the recommended filter implementation.

Figure 4. PLL Filter Specification

0.2 dB

0 dB

-0.5 dB

Forbidden

Zone

Forbidden

Zone

-28 dB

-40 dB

DC

fpeak

1 MHz

66 MHz

force

2.4

Decoupling Guidelines

Due to the large number of transistors and high internal clock speeds, the processor is capable of

generating large average current swings between low and full power states. The fluctuations can

cause voltages on power planes to sag below their nominal values if bulk decoupling is not

adequate. Care must be taken in the board design to ensure that the voltage provided to the

processor remains within the specifications listed in Table 7. Failure to do so can result in timing

violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a

voltage overshoot).

2.4.1

Processor VCC_COREDecoupling

The regulator for the VCC_COREinput must be capable of delivering the dICC_CORE/dt (defined in

Table 7) while maintaining the required tolerances (also defined in Table 7). Failure to meet these

specifications can result in timing violations (during VCC_COREsag) or a reduced lifetime of the

component (during VCC_COREovershoot).

Datasheet

17

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

The processor requires both high frequency and bulk decoupling on the system motherboard for

proper AGTL bus operation. The minimum recommendation for the processor decoupling

requirement is listed below. All capacitors should be placed next to and within the PGA370 socket

cavity and mounted on the primary side of the motherboard. The capacitors are arranged to

minimize the overall inductance between the VCC_COREand Vss power pins.

Decoupling Recommendations

• VCC_COREdecoupling: A minimum of sixteen 4.7 uF capacitors in a 1206 package.

• VTT decoupling: Twenty 0.1 uF capacitors in 0603 packages.

• VREF decoupling: 0.1 uF and 0.001 uF capacitors in 0603 package placed near the VREF pins.

For additional decoupling requirements, refer to the appropriate platform design guide for

recommended capacitor component value/quantity and placement.

2.5

Processor System Bus Clock and Processor Clocking

The Intel Pentium III processor based on 0.13 micron process will implement an auto-detect

mechanism that will allow the processor to use either single-ended or differential signaling for the

system bus and processor clocking. The processor checks to see if the signal on pin Y33 is

toggling. If this signal is toggling, the processor operates in differential mode. Refer to Figure 5 for

an example on differential clocking. Resistor values and clock topology are listed in the

appropriate platform design guide for a differential implementation.

Note: References to BCLK throughout this document also imply to it’s complement signal, BCLK# in

differential implementations, and when noted otherwise.

Since legacy PGA370 socket platforms use a different single-ended clocking specification than the

Pentium III processor based on 0.13 micron process, the Pentium III processor based on 0.13

micron process will not function when placed into these platforms. The BCLK input directly

controls the operating speed of the system bus interface. All AGTL system bus timing parameters

are specified with respect to the crossing point of the rising edge of the BCLK and the falling edge

of BCLK# inputs in a differential implementation. See the P6 Family of Processors Hardware

Developer's Manual for further details. The reference voltage of the BCLK in the P6 Family of

Processors Hardware Developer Manual is re-defined as the crossing point of the BCLK and

BCLK# in a differential implementation.

Figure 5. Differential/Single-Ended Clocking Example

BCLK

+

Processor

or Chipset

Clock

Driver

–

BCLK#

BCLK

Processor

or Chipset

Clock

Driver

18

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.6

Voltage Identification

There are five voltage identification (VID) pins on the PGA370 socket. These pins can be used to

support automatic selection of VCC_COREvoltages. The VID pins for the Pentium III processor

based on 0.13 micron process are open drain signals versus opens or shorts found on the previous

Intel Pentium III FC-PGA processor. Refer to Table 11 for level specifications for the VID signals.

This pull-up resistor may be either external logic on the motherboard or internal to the Voltage

Regulator.

The VID signals rely on a 3.3 V pull-up resistor to set the signal to a logic high level. The VID pins

are needed to fully support voltage specification variations on current and future processors. The

voltage selection range for the processor is defined in Table 3. The VID25mV signal is a new

signal that allows the voltage regulator or voltage regulator module (VRM) to output voltage levels

in 25 mV increment necessary for the Pentium III processor based on 0.13 micron process only.

The current Pentium III processor in the FC-PGA package will not have this VID25mV signal. The

VID25mV pin location is actually a Vss pin on the model 68xh Pentium III processor. By

connecting the VID25mV signal to the Vss pin, it will disable the 25mV stepping granularity

output and the regulator will resort to 50 mV stepping increment. The voltage regulator or VRM

must supply the voltage that is requested or disable itself.

In addition to the new signal “VID25mV”, the Pentium III processor based on 0.13 micron process

will introduce a second new signal labeled as “VTT_PWRGD”. The VTT_PWRGD signal informs

the platform that the VID and BSEL signals are stable and should be sampled. During Power-up,

the VID signals will be in an indeterminate state for a small period of time. The voltage regulator or

the VRM should not latch the VID signals until the VTT_PWRGD signal is asserted by the VRM

and sampled active. The assertion of the VTT_PWRGD signal indicates the VID signals are stable

and are driven to the final state by the processor. Refer to Figure 14 for power-up timing sequence

for the VTT_PWRGD and the VID signals.

Datasheet

19

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 3. Voltage Identification Definition ¹

VID25mV

VID3

VID2

VID1

VID0

Vcc

CORE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.05

1.075

1.10

1.125

1.15

1.175

1.20

1.225

1.25

1.275

1.30

1.325

1.35

1.375

1.40

1.425

1.45

1.475

1.50

1.525

1.55

1.575

1.60

1.625

1.65

1.675

1.70

1.725

1.75

1.775

1.80

1.825

NOTES:

1. 0 = Processor pin connected to VSS.

1 = Open on processor; may be pulled up to TTL VIH (3.3V max) on baseboard.

The VID pins should be pulled up to a 3.3 V level. This may be accomplished with pull-ups

internal to the voltage regulator, which ensures valid VID pull-up voltage during Power-up and

Power-down sequences. If external resistors are used for the VID[3:0, 25mV] signal, the power

source must be guaranteed to be stable when the supply to the voltage regulator is stable. This

prevents the possibility of the processor supply going above the specified VCC_COREin the event of

a failure in the supply for the VID lines. In the case of a DC-to-DC converter, this can be

accomplished by using the input voltage to the converter for the VID line pull-ups. A resistor equal

to 1 KΩ may be used to connect the VID signals to the voltage regulator input.

Note: Intel requires that designs utilize VRM 8.5 and not VRM 8.4 specifications to meet the Pentium III

processor based on 0.13 micron process requirements.

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Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

To re-emphasize, VRM 8.5 introduces two new signals [VID25mV and VTT_PWRGD] that is

utilized by the Pentium III processor based on 0.13 micron process and platform. Ignoring and not

connecting these two new pins, as documented in the Platform Design Guidelines, will prevent the

Pentium III processor based on 0.13 micron process from operating at the specified voltage levels

and core frequency. Figure 6 provides a high-level interconnection schematic. Refer to the VRM

8.5 DC-DC Converter Design Guideline and the appropriate Platform Design Guidelines for

further detailed information on the voltage identification and bus select implementation. Refer to

Figure 14 for VID power-up sequence and timing requirements.

Figure 6. VTT Power Good and Bus Select Interconnect Diagram

VID[3:0, 25mV]

VTT

VRM 8.5

Voltage Regulator

VTT

Processor

1 kΩ

VCC

CORE

VTT_PW RGD

(output)

VTT_PW RGD

(input)

BSEL[1:0]

Clock

Driver

Datasheet

21

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.7

Processor System Bus Unused Pins

All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins

to VCC_CORE, VREF, VSS, VTT or to any other signal (including each other) can result in component

malfunction or incompatibility with future processors. See Section 5.4 for a pin listing of the

processor and the location of each RESERVED pin.

PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to

VCC_CMOS1.5even when the APIC will not be used. A separate pull-up resistor must be provided for

each PICD signal.

For reliable operation, always connect unused inputs or bidirectional signals to their deasserted

signal level. The pull-up or pull-down resistor values are system dependent and should be chosen

such that the logic high (V_IH) and logic low (V_IL) requirements are met. See Table 11 for level

specifications of non-AGTL signals.

For unused AGTL inputs, the on-die termination will be sufficient. No external R_TTis necessary on

the motherboard.

For unused CMOS inputs, active low signals should be connected through a pull-up resistor to

VCC_CMOS1.5and meet V_IHrequirements. Unused active high CMOS inputs should be connected

through a pull-down resistor to ground (VSS) and meet V_ILrequirements. Unused CMOS outputs

can be left unconnected. A resistor must be used when tying bidirectional signals to power or

ground. When tying any signal to power or ground, a resistor will also allow for system testability.

2.8

Processor System Bus Signal Groups

To simplify the following discussion, the processor system bus signals have been combined into

groups by buffer type. All P6 family processor system bus outputs are open drain and require a

high-level source provided termination resistors. However, the Pentium III processor based on 0.13

micron process includes on-die termination for AGTL signals and termination resistors placed on

the platform are not necessary except for the RESET# signal which still requires external

termination.

AGTL input signals have differential input buffers which use VREF as a reference signal. AGTL

output signals require termination to 1.25 V. In this document, the term “AGTL Input” refers to the

AGTL input group as well as the AGTL I/O group when receiving. Similarly, “AGTL Output”

refers to the AGTL output group as well as the AGTL I/O group when driving.

The PWRGOOD signal input is a 1.8 V signal level and must be pulled up to VCC_CMOS1.8. The

VTT_PWRGD is not 1.8 V tolerant and must be connected to VTT (1.25 V)_.Other CMOS inputs

(A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and STPCLK#) are

only 1.5 V tolerant and must be pulled up to VCC_CMOS1.5. The CMOS, APIC, and TAP outputs are

open drain and must be pulled to the appropriate level to meet the input specifications of the

interfacing device.

The groups and the signals contained within each group are shown in Table 4. Refer to Section 7.0

for a description of these signals.

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Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 4. System Bus Signal Groups ¹

Group Name

Signals

AGTL Input

BPRI#, DEFER#, RESET#, RSP#

PRDY#

AGTL Output

A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,

2

AGTL I/O

BR0# , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,

RS[2:0]#, TRDY#

CMOS Input

(1.25 V)

VTT_PWRGD

3

CMOS Input

(1.5 V)

A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,

STPCLK#

4

CMOS Input

(1.8 V)

PWRGOOD

5

CMOS Output

FERR#, IERR#, THERMTRIP#

4

(1.5 V)

8

CMOS Output

VID[3:0,25mV], BSEL[1:0]

BCLK0, BCLK0#

(3.3 V)

System Bus

10

Clock

(1.25 V / 2.5 V)

9

APIC Clock

PICCLK

4

APIC I/O

PICD[1:0]

4

TAP Input

TCK, TDI, TMS, TRST#

TDO

4

TAP Output

7

CPUPRES#, DYN_OE, NCHTRL, PLL[2:1], SLEWCTRL, RTTCTRL ,THERMDN,

6

Power/Other

THERMDP, VCC

, VREF, VSS, VTT, Reserved,

CORE

NOTES:

1. See Section 7.0 for information on the these signals.

2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information.

3. This signal is 1.25 V.

4. These signals are 1.5 V.

5. This signal is 1.8 V.

6. VCC

is the power supply for the processor core and is described in Section 2.6.

CORE

VID[3:0,25mV] is described in Section 2.6.

VTT is used to terminate the system bus and generate VREF on the motherboard.

VSS is system ground.

BSEL[1:0] is described in Section 2.8.2 and Section 7.0.

All other signals are described in Section 7.0.

7. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform

design guide for the recommended pulldown resistor value.

8. These signals are 3.3 V.

9. These signals are 2.0 V.

10. 1.25 V signal for differential clock application and 2.5V for Single-ended clock application.

2.8.1

Asynchronous vs. Synchronous for System Bus Signals

All AGTL signals are synchronous to BCLK (BCLK/BCLK#). All of the CMOS, Clock, APIC,

and TAP signals can be applied asynchronously to BCLK (BCLK/BCLK#). All APIC signals are

synchronous to PICCLK. All TAP signals are synchronous to TCK.

Datasheet

23

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.8.2

System Bus Frequency Select Signals

The System Bus Frequency Select Signals (BSEL [1:0]) are used to select the system bus

frequency for the Pentium III processor based on 0.13 micron process. The BSEL signals are also

used by the chipset and system bus clock generator. The BSEL pins for the Pentium III processor

based on 0.13 micron process are open drain signals versus opens or shorts found on the previous

Intel

Pentium III FC-PGA processor. Refer to Table 11 for level specifications for the BSEL signals.

The BSEL signals rely on a 3.3 V pull-up resistor to set the signal to a logic high level. Similar to

the VID signals described in Section 2.6, the VTT_PWRGD signal also informs the platform that

the BSEL signals are stable and should be sampled. During Power-up, the BSEL signals will be in

a indeterminate state for a small period of time. The chipset or system bus clock generator should

not sample and/or latch the BSEL signals until the VTT_PWRGD signal is asserted. The assertion

of the VTT_PWRGD signal indicates the BSEL signals are stable and are driven to the final state

by the processor. Refer to Figure 14 for power-up timing sequence for the VTT_PWRGD and the

BSEL signals.

Table 5 defines the possible combinations of the BSEL signals and the frequency associated with

each combination. The frequency selection is determined by the processor(s) and driven out to the

chipset and system bus clock generator. All system bus agents must operate at the same frequency

determined by the processor. The Pentium III processor based on 0.13 micron process operates at

133 MHz system bus frequency based on the system bus specified rating marked on the package.

Over or under-clocking the system bus frequency outside the specified rating marked on the

package is not recommended.

Figure 7. BSEL[1:0] Example for a System Design

3.3V

Processor

BSEL0 BSEL1

1 kΩ

Clock Driver

Chipset

Table 5. Frequency Select Truth Table for BSEL[1:0]

BSEL1

BSEL0

Frequency

0

1

0

1

0

1

Reserved

133 MHz

24

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the processor be first in the TAP chain and followed by any other components

within the system. A translation buffer should be used to connect to the rest of the chain unless one

of the other components is capable of accepting an input of the appropriate voltage. Similar

considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be

required with each driving a different voltage level.

2.10

Maximum Ratings

Table 6 contains processor stress ratings only. Functional operation at the absolute maximum and

minimum is not implied nor guaranteed. The processor should not receive a clock while subjected

to these conditions. Functional operating conditions are given in the timing and level tables in

Section 2.11 through Section 2.13. Extended exposure to the maximum ratings may affect device

reliability. Furthermore, although the processor contains protective circuitry to resist damage from

static electric discharge, one should always take precautions to avoid high static voltages or electric

fields.

Table 6. Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

TSTORAGE

Processor storage temperature

-40

85

°C

VCC

and

Processor core voltage and termination

supply voltage with respect to VSS

CORE

0.5

1.75

V

VTT

Vin

AGTL buffer input voltage

-0.3

1.78

2.08

3.6

V

1, 3

AGTL

CMOS buffer DC input voltage with respect

to VSS

1.5

2, 3, 4

CMOS

VVID & VBSEL

Max VID and BSEL pin current

NOTES:

1. Input voltage can never exceed VSS +1.78 volts.

2. Input voltage can never exceed VSS + 2.08 volts.

3. Input voltage can never go below -0.3 V

4. Parameter applies to CMOS, APIC, and TAP bus signal groups only.

2.11

Processor Voltage Level Specifications

The processor voltage level specifications in this section are defined at the PGA370 socket pins

(bottom side of the motherboard). See Section 7.0 for the processor signal descriptions and

Section 5.4 for the signal listings.

Most of the signals on the processor system bus are in the AGTL signal group. These signals are

specified to be terminated to 1.25 V. The voltage level specifications for these signals are listed in

Table 10 on page 29.

To allow connection with other devices, the clock, CMOS, APIC, and TAP signals are designed to

interface at non-AGTL levels. The voltage level specifications for these pins are listed in Table 11

on page 29.

Datasheet

25

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 7 through Table 13 list the voltage level specifications for the Pentium III processor based on

0.13 micron process. Specifications are valid only while meeting specifications for junction

temperature, clock frequency, and input voltages. Care should be taken to read all notes associated

with each parameter.

Table 7. Voltage and Current Specifications ^{1, 2}

Symbol

Parameter

Core Freq

Min

Typ

Max Unit

Notes

1.00 GHz

1.13 GHz

1.20 GHz

1.33 GHz

1.475

1.5

VCC

VCC for processor core

V

3

CORE

Static AGTL bus

termination voltage

, 4

VTT

1.25

V

1.25 ±3%

1.25 ±9%

Transient AGTL bus

termination voltage

, 4

, 12

V

1.5

1.8

V

1.5 ± 10%

1.8 ± 10%

cc_cmos1.5

cc_cmos1.8

Baseboard

Processor core voltage

static tolerance level at the

PGA370 socket pins

VCC

CORE

V

5

Tolerance,

Static

Refer to Figure 8 and

Table 9 for Tolerance

values

Baseboard

Processor core voltage

transient tolerance level at

the PGA370 socket pins

VCC

CORE

V

A

Tolerance,

Transient

1.00 GHz

1.13 GHz

1.20 GHz

1.33 GHz

19.0

20.1

20.6

23.1

ICC

ICC for processor core

6

CORE

ICC

ICC for Vcc

250

1

mA

CMOS1.5

CMOS1.8

CMOS3.3

CMOS1.5

CMOS1.8

CMOS3.3

35

Termination voltage supply

current

IVTT

2.3

A

1.00 GHz

1.13 GHz

1.20 GHz

1.33 GHz

12.9

13.7

14.0

15.7

ICC Stop-Grant for

processor core

ISGnt

A

7, 8

11.0

12.0

A

13

14

IDSLP

ICC Deep Sleep

Power supply current slew

rate

Refer to Table 8 for Slew

Rate

A/

µs

dICC_CORE/dt

8, 9, 10, 11

Termination current slew

rate

Table

13

A/

8, 9, 10, See

dI _TT/dt

v

µs Table 13

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

®

2. All specifications in this table apply only to the Intel Pentium III processor based on 0.13 micron process.

3. Vcc and Icc supply the processor core and the on-die L2 cache.

CORE

4. VTT must be held to 1.25 V ±9% while the AGTL bus is active. It is required that VTT be held to 1.25 V ±3%

while the processor system bus is static (idle condition). The ±3% range is the required design target; ±9%

26

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

will come from the transient noise added. This is measured at the PGA370 socket pins on the bottom side of

the baseboard.

5. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the

processor socket pin on the soldered-side of the motherboard. VCC

must return to within the static

CORE

voltage specification within 100 µs after a transient event; see the VRM 8.5 DC-DC Converter Design

Guidelines for further details.

6. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.

7. The current specified is also for AutoHALT state.

8. Maximum values are specified by design/characterization at nominal Vcc

.

CORE

9. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum

inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.

10.dIcc/dt specifications are measured and specified at the PGA370 socket pins.

11.Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output

load ranges specified in the tables above. See VRM 8.5 Specification.

12.Pull ups only.

13.For processors with VCC

14.For processors with VCC

of 1.475 V.

of 1.5 V.

CORE

Table 8. Power Supply Current Slew Rate (dIcc_core/dt)

Slew Rate: 26 A Load Step

Slew Rate (26 A): ICC at Socket

30

25

20

15

10

5

PWL SLew Rate Data

Time (us) ICC at Socket (A)

0.1

0.15

0.5

1

1.5

2

2.5

4

3.5

4

26.23

23.18

20.03

21.10

21.88

22.29

22.30

22.07

21.78

21.58

21.51

4.5

0

1

2

3

4

5

6

Table 8 contains typical slew rate data for the Pentium III processor based on 0.13 micron process.

Actual slew rate values and wave-shapes may vary slightly depending on the type and size of

decoupling capacitors used in a particular implementation.

Datasheet

27

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 9. Vcc Static and Transient Tolerance

Voltage Deviation from VID Setting (mV)

Static Tolerance

Transient Tolerance

Min

Max

Min

Max

Icc (A)

0

15

5

65

55

5

85

74

2

-5

4

-5

45

-15

-25

-35

-45

-55

-65

-76

-87

-98

-110

-121

-132

-144

-155

62

6

-15

-25

-35

-45

-55

-65

-75

-85

-95

-105

-115

-125

-135

35

51

8

25

40

10

12

14

16

18

20

22

24

26

28

30

15

28

5

17

-5

6

-15

-25

-35

-45

-55

-65

-75

-85

-5

-15

-25

-35

-45

-55

-65

-75

Figure 8. Vcc Static and Transient Tolerance

80

60

Transient M axim um Load Line

Static M axim um Load Line

40

20

0

-20

-40

-60

-80

-100

-120

Static M inim um Load Line

Transient M inim um Load Line

-140

0

5

10

15

20

25

30

Icc Load (A)

28

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 10. AGTL Signal Group Levels Specifications ¹

Symbol

Parameter

Min

Max

Unit

Notes

VIL

Input Low Voltage

Input High Voltage

Buffer On Resistance

VREF – 0.200

V

Ω

6

VIH

VREF + 0.200

2, 3, 6

5

Ron

16.67

±100

Leakage Current for inputs,

outputs, and I/O

IL

µA

4, 7

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. All inputs, outputs, and I/O pins must comply with the signal quality specifications in Section 3.0.

3. Minimum and maximum VTT are given in Table 13 on page 30.

4. (0 ≤ VIN ≤ 1.25 V +3%) and (0 ≤ VOUT ≤ 1.25 V+3%).

5. Refer to the processor I/O Buffer Models for I/V characteristics.

6. Steady state input voltage must not be above VSS + 1.65 V or below VTT – 1.65 V.

7. Does not apply to Vcc leakage current due to the presence of on-die RTT.

Table 11. Non-AGTL Signal Group Levels Specifications ¹

Symbol

Parameter

Min

Max

Unit

Notes

VIL

Input Low Voltage

Input High Voltage

0.4

Vcmos_ref – 0.300

0.36

V

11

10

8

1.2

1.5

1.8

2.0

VIL

-0.150

-0.36

-0.40

1.03

0.40

9

VIH

11

1.2

1.5

Vcmos_ref

+ 0.250

VIH

Input High Voltage

V

+ 10%

V

6, 10, 12

12, 13

CC_CMOS1.5

Vcmos_ref

+ 0.200

VIH

Input High Voltage PICD[1:0]

2.0

1.5PICD

VIH

Input High Voltage

1.44

1.60

2.16

V

Ω

8

9

2

1.8

2.0

R

30

on

7, 9, All

VOL

Output Low Voltage

0.30

V

outputs are

open-drain

IOL

ILI

Output Low Current

10

mA

µA

Input Leakage Current

Output Leakage Current

±100

3, 6

ILO

3, 4, 6, 7

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. Parameter measured at 9 mA (for use with TTL inputs).

3. (0 ≤ VIN ≤ 1.8 V +10%).

4. (0 ≤ VOUT ≤ 1.8 V +10%).

5. For BCLK specifications, refer to Table 24 on page 42.

6. (0 ≤ VIN ≤ 1.5 V +10%).

7. (0 ≤ VOUT ≤ 1.5 V +10%).

8. Applies to non-AGTL signal PWRGOOD.

9. Applies to non-AGTL signal PICCLK.

10.Applies to non-AGTL signals except BCLK, PICCLK, and PWRGOOD.

11.Applies to non-AGTL signal VTT_PWRGD.

12.Vcmos_ref = 2/3 Vcc_cmos1.5, refer to Table 7 on page 26.

13.Applies to PICD[1:0] only

Datasheet

29

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 12. 3.3 Volt CMOS Output Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

V

Nominal Voltage

3.45

0.9

V

3.3 + 5%

VOH

ILO

Output High Voltage

Output Leakage Current

100

µA

2.12

AGTL System Bus Specifications

It is recommended that the AGTL bus be routed in a daisy-chain fashion with termination resistors

to VTT. These termination resistors are placed electrically between the ends of the signal traces and

the VTT voltage supply. The valid high and low levels are determined by the input buffers using a

reference voltage called VREF. Refer to the appropriate platform design guide for more

information.

Table 13 lists the nominal specification for the AGTL termination voltage (VTT). The AGTL

reference voltage (VREF) is generated on the system motherboard and should be set to 2/3 VTT for

the processor and other AGTL logic. It is important that the baseboard impedance be specified and

held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL signal group traces

is known and well-controlled. For more details on the AGTL buffer specification, see the

Intel^®Pentium^®II Processor Developer's Manual and AP-585, Intel^®Pentium^®II Processor

AGTL Guidelines.

Table 13. Processor AGTL Bus Specifications ^{1, 2}

Symbol

VTT

Parameter

Min

Typ

Max

Units

Notes

Bus Termination Voltage

1.1375

1.25

56

V

3

4

5

On-die R

VREF

Termination Resistor

50

115

Ω

TT

68

Bus Reference Voltage

2/3VTT

V

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. Pentium III processors based on 0.13 micron process for the PGA370 socket contain AGTL termination

resistors on the processor die, except for the RESET# input.

3. VTT must be held to 1.25 V ±9%. It is required that VTT be held to 1.25 V ±3% while the processor system bus

is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard.

4. Uni-processor platforms require a 56 Ω resistor and dual-processor platforms require a 68 Ω resistor.

Tolerance for on-die RTT is ±10% (56, 68 Ω resistors). RTT is ±15% (100 Ω resistors).

5. VREF is generated on the motherboard and should be 2/3 VTT ±5% nominally. Insure that there is adequate

VREF decoupling on the motherboard.

30

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

2.13

System Bus Timing Specifications

The processor system bus timings specified in this section are defined at the socket pins on the

bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins

during manufacturing. Timings at the processor pins are specified by design characterization. See

Section 7.0 for the processor signal definitions.

Table 14 through Table 21 list the timing specifications associated with the processor system bus.

These specifications are broken into the following categories: Table 14 contains the system bus

clock specifications for Single-ended clock mode operation and Table 15 contains the system bus

clock specifications for Differential clock mode operation. Table 17 contains the AGTL

specifications, Table 18 contains the CMOS signal group specifications, Table 19 contains timings

for the reset conditions, Table 20 covers APIC bus timing, and Table 21 covers TAP timing.

All processor system bus timing specifications for the AGTL signal group are relative to the rising

edge of the BCLK input. All AGTL timings are referenced to VREF for both 0 and 1 logic levels

unless otherwise specified.

The timings specified in this section should be used in conjunction with the I/O buffer models

provided by Intel. These I/O buffer models, which include package information, are available for

the Pentium III processor based on 0.13 micron process in the FC-PGA2 package in IBIS* 3.1

model format (Electronic Format).

AGTL layout guidelines are also available in the appropriate platform design guide.

Care should be taken to read all notes associated with a particular timing parameter.

7

Table 14. System Bus Timing Specifications (Single-Ended Clock)^1,4

133 MHz

100 MHz

T# Parameter

Min

Max

Min

Max

Unit

Figure

Notes

T1: BCLK Period - average

7.5

7.65

10.0

9.75

10.15

ns

9

2

T1 : BCLK Period - Instantaneous

abs

7.25

ns

minimum

T2: BCLK Period Stability

T5: BCLK Rise Time

T6: BCLK Fall Time

T3: BCLK High Time

T4: BCLK Low Time

T7: BCLK Input High

T8: BCLK Input Low

250

1.6

250

1.6

ps

ns

V

2

3

5

6

0.4

1.4

2.2

0.4

2.5

2.4

2.2

10

0.3

V

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. Period, jitter, offset and skew measured at 1.25 V.

3. Measured from 0.5 to 2.0 V.

4. CLKREF (BCLK#) = 1.25 V with ± 5% DC tolerance. CLKREF must be generated from a stable source. AC

tolerances must be less than -40 dB @ 1 MHz.

5. BCLK High Time is measured above 2.0 V.

6. BCLK Low Time is measured below 0.5 V.

Datasheet

31

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 15. System Bus Timing Specifications (Differential Clock)^{1, 2, 6}

133 MHz

100 MHz

T# Parameter

Min

Max

Min

Max

Unit

Figure

Notes

T1: BCLK Period - average

7.5

7.7

10.0

9.8

10.2

ns

9

3, 4

5

T1 : BCLK Period - Instantaneous

abs

7.30

ns

minimum

T2: BCLK Period Stability

Vcross: Crossing point at 1 V Swing

T5: BCLK Rise Time

T6: BCLK Fall Time

200

0.76

550

325

200

0.76

550

325

ps

V

0.51

175

0.51

175

9

ps

10

7, 8

Rise/Fall Time Matching

BCLK Duty Cycle

45% 55% 45% 55%

4

Input High Voltage

0.92

-0.2

0.35

1.45

0.35

0.92

-0.2

0.35

1.45

0.35

V

Input Low Voltage

Rising Edge Ring Back

Falling Edge Ring Back

-0.35

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. All timings for the AGTL signals are referenced at the rising edge of BCLK and the falling edge of BCLK# at

the processor pin. All AGTL signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the

processor pins.

3. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to

core clock ratio is determined during initialization. Individual processors will only operate at their specified

system bus frequency, 133 MHz. Table 16 shows the supported ratios for each processor.

4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be

used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be

measured at adjacent crossing points of BCLK and BCLK# which is defined as the rising edge of BCLK and

the falling edge of BCLK# at the processor pin. The jitter present must be accounted for as a component of

BCLK timing skew between devices.

5. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the

jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should

be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a

spectrum analyzer. See the appropriate clock synthesizer/driver specification for details.

6. Measurement taken from differential waveform, defined as BCLK – BCLK#.

7. Rise time is measured from -0.35 to +0.35 V and fall time is measured from 0.35 V to -0.35 V.

8. Measured at the socket pin.

32

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 16. Valid System Bus to Core Frequency Ratios ^{1, 2, 3}

Core Frequency

BCLK Frequency

Frequency

Multiplier

Processor

(GHz)

(MHz)

1A

1.13A

1.20

1.33

1.00

1.13

1.20

1.33

133

7.5

8.5

9

10

NOTES:

1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency

multipliers.

2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the

®

Intel Pentium III processor based on 0.13 micron process.

3. Individual processors will only operate at their specified system bus frequency; 133 MHz.

Table 17. System Bus Timing Specifications (AGTL Signal Group)^{1, 2, 3}

T# Parameter

Min

Max

Unit

Figure

Notes

T7: AGTL Output Valid Delay

T8: AGTL Input Setup Time

T9: AGTL Input Hold Time

T10: RESET# Pulse Width

0.40

0.95

1.00

3.25

ns

ms

11

12

13

4

5, 6, 7, 10

8

6, 9

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. These specifications are tested during manufacturing.

3. All timings for the AGTL signals are referenced to the rising edge of BCLK and the falling edge of BCLK# at

the processor pin. All AGTL signal timings (compatibility signals, etc.) are referenced at 0.80 V at the

processor pins.

4. Valid delay timings for these signals are specified into 50 Ω to 1.25 V, VREF at 0.8 V ±2% and with 56 Ω or

68 Ω on-die R

.

TT

5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.

6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.

7. Specification is for a minimum 0.40 V swing from VREF – 200 mV to VREF + 200 mV. This assumes an edge

rate of 0.3 V/ns.

8. Specification is for a maximum 0.8 V swing from VTT – 0.8 V to VTT. This assumes an edge rate of 3 V/ns.

9. This should be measured after VCC

, VTT, Vcc

, and BCLK (and BCLK#) are stable.

CORE

CMOS

10.BREQ signals observe a 1.2 ns minimum setup time.

Table 18. System Bus Timing Specifications (CMOS Signal Group) ^{1, 2, 3, 4}

T# Parameter

Min

Max

Unit

Figure

Notes

Active and

T14: CMOS Input Pulse Width, except

PWRGOOD

2

BCLKs

11

15

Inactive states

T15: PWRGOOD Inactive Pulse Width

10

5

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies

2. These specifications are tested during manufacturing.

3. These signals may be driven asynchronously.

4. All CMOS outputs shall be asserted for at least 2 system bus clocks.

5. When driven inactive or after VCC

, VTT, VCC , and BCLK and BCLK# are stable.

CORE CMOS

Datasheet

33

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 19. System Bus Timing Specifications (Reset Conditions) ¹

T# Parameter

Min

Max

Unit

Figure

Notes

T16: Reset Configuration Signals (A[14:5]#,

BR0#, INIT#) Setup Time

Before deassertion

of RESET#

4

BCLKs

13

T17: Reset Configuration Signals (A[14:5]#,

BR0#, INIT#) Hold Time

After clock that

deasserts RESET#

2

20

BCLKs

13

NOTE:

®

1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processors based on

0.13 micron process frequencies.

Table 20. System Bus Timing Specifications (APIC Clock and APIC I/O)^{1, 2, 3}

T# Parameter

T21: PICCLK Frequency

Min

Max

Unit

Figure

Notes

2.0

30.0

10.5

0.25

8.0

33.3

MHz

ns

T22: PICCLK Period

500.0

10

12

11

10

T23: PICCLK High Time

@ > 1.60 V

@ < 0.40 V

(0.40V – 1.60V )

(1.60 – 0.40 V)

4

T24: PICCLK Low Time

T25: PICCLK Rise Time

3.0

T26: PICCLK Fall Time

T27: PICD[1:0] Setup Time

T28: PICD[1:0] Hold Time

T29a: PICD[1:0] Valid Delay (Rising Edge)

T29b: PICD[1:0] Valid Delay (Falling Edge)

2.5

4

1.5

8.7

4, 5, 6

1.5

12.0

4, 5, 6

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors based on 0.13

micron process at all frequencies.

2. These specifications are tested during manufacturing.

3. All timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.9 V at the processor pins.

All APIC I/O signal timings are referenced at 1.0 V at the processor pins.

4. Referenced to PICCLK rising edge.

5. For open drain signals, valid delay is synonymous with float delay.

6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.

34

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 21. System Bus Timing Specifications (TAP Connection)^{1, 2, 3}

T# Parameter

T30: TCK Frequency

Min

Max

16.667

Unit

MHz

Figure

Notes

T31: TCK Period

60.0

25.0

ns

10

T32: TCK High Time

T33: TCK Low Time

Vcmos_ref + 0.200 V, 10

Vcmos_ref – 0.200 V, 10

(Vcmos_ref – 0.200 V) –

(Vcmos_ref + 0.200 V),

T34: TCK Rise Time

T35: TCK Fall Time

5.0

ns

10

4, 10

(Vcmos_ref + 0.200 V) –

(Vcmos_ref – 0.200 V),

4, 10

T36: TRST# Pulse Width

T37: TDI, TMS Setup Time

T38: TDI, TMS Hold Time

T39: TDO Valid Delay

40.0

5.0

ns

17

16

Asynchronous, 10

5

14.0

1.0

5

10.0

25.0

6, 7

T40: TDO Float Delay

6, 7, 10

T41: All Non-Test Outputs Valid

Delay

2.0

25.0

ns

16

6, 8, 9

T42: All Non-Test Inputs Setup Time

T43: All Non-Test Inputs Setup Time

T44: All Non-Test Inputs Hold Time

ns

16

6, 8, 9, 10

5, 8, 9

5.0

13.0

5, 8, 9

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processors based on

0.13 micron process frequencies.

2. All timings for the TAP signals are referenced to the TCK rising edge at 1.0 V at the processor pins. All TAP

signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.

3. These specifications are tested during manufacturing, unless otherwise noted.

4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.

5. Referenced to TCK rising edge.

6. Referenced to TCK falling edge.

7. Valid delay timing for this signal is specified to 1.5 V.

8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to TAP operations.

9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.

10.Not 100% tested. Specified by design characterization.

Datasheet

35

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 22. Platform Power-On Timings²

T# Parameter

Min

Max

Unit

Figure

Notes

T45: Valid Time Before VTT_PWRGD

T46: Valid Time Before PWRGOOD

T47: RESET# Inactive to Valid Outputs

T48: RESET# Inactive to Drive Signals

1.0

2.0

1

ms

14

1

BCLK

4

NOTES:

1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform

during processor power-up sequence.

2. Configuration Input signals include: A[14:5], BR0#, INIT#. For timing of these signals, refer to Table 18 and

Figure 13.

Notes: For Figure 9 through Figure 19, the following apply:

1. Figure 9 through Figure 19 are to be used in conjunction with Table 14 through Table 21.

2. All timings for the AGTL signals at the processor pins are referenced to the rising edge of

BCLK and the falling edge of BCLK# at the crossing point for differential clock mode and to

the rising edge of BCLK at BCLK_VREF(1.25 V) for single-ended clock mode. All AGTL

signal timings (address bus, data bus, etc.) are referenced at 2/3VTT at the processor pins.

3. All timings for the APIC I/O signals at the processor pins are referenced to the PICCLK rising

edge at 0.9 V. All APIC I/O signal timings are referenced at 1.0 V at the processor pins.

4. All timings for the TAP signals at the processor pins are referenced to the TCK rising edge at

1.0 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.

Figure 9. Clock Waveform

V ih

B C L K

V cro ss

B C L K #

V il

T p

T p = T 1 (B C L K P e rio d )

N O T E : S in g le -E n d e d c lo c k u s e s B C L K o n ly,

D iffe re n tia l c lo c k u se s B L C K a n d B C L K #

36

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 10. BCLK/BCLK#, PICCLK, and TCK Generic Clock Waveform

T_p

T_h

Vih diff

Vringback

(rise)

V2

V3

V1

0V

Vringback

(fall)

Vil diff

T_r

T_f

T_h

T_l

=

T5, T25, T34, (Rise Time)

T6, T26, T35, (Fall Time)

T3, T23, T32, (High Time)

T4, T24, T33, (Low Time)

T_f

T_l

T_r

T_p

T1, T22, T31 (BCLK, TCK, PICCLK Period)

V1 = BCLK is referenced to 0.30V (Differential Mode), 0.50V (Single-Ended Mode)

TCK is referenced to Vref - 200 mV, PICCLK is referenced to 0.4V.

V2 = BCLK is refernced to 0.9V (Differental Mode), 2.0V (Single-Ended Mode)

TCK is referenced to Vref + 200 mV, PICCLK is refernced to 1.6V

V3 = BCLK and BLCK# crossing point of the rising edge of BLCK and the falling edge of BCLK# (Differential Mode),

BCLK i refereced to 1.25V (Single-Ended Mode), PICCLK is reference to 1.0V, TCK is referenced to Vcmosref

Figure 11. System Bus Valid Delay Timings

BCLK#

BCLK

Tx

Valid

V

Signal

Tpw

Tx = T7, T29a, T29b (Valid Delay)

Tpw = T14, T15 (Pulse Width)

NOTE: Single-Ended clock uses BCLK only,

Differential clock uses BCLK and BCLK#

V = Vref for AGTL signal group; Vcmosref for CMOS, APIC and TAP signal groups

Datasheet

37

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 12. System Bus Setup and Hold Timings

BCLK#

V_Cross

BCLK

Th

Ts

V

Valid

V_Cross

= Crossing point of BLCK and BCLK#

Ts = T8, T27 (Setup Time)

Th = T9, T28 (Hold Time)

NOTE: Single-Ended clock uses BCLK only,

Differential clock uses BCLK and BCLK#

V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups

Figure 13. System Bus Reset and Configuration Timings

BCLK#

BCLK

T8

T9

RESET#

T10

T17

Configuration

(A[14:5]#, BR0#,

BR1#, FLUSH#,

INT#)

T16

Valid

T9 = (AGTL+ Input Hold Time)

T8 = (AGTL+ Input Setup Time)

T10 = (RESET# Pulse Width)

NOTE: Single-Ended clock uses BCLK only,

Differential clock uses BCLK and BCLK#

T16 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup Time)

T17 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)

38

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 14. Platform Power-On Sequence and Timings

Vtt, Vref

Vcmosref

VID

Valid

BSEL[1:0]

VTT_PWRGD

VCC_Core

T45

BCLK#

BCLK

PICCLK

T46

VCC_PWRGD

Configuration Inputs

RESET#

Inactive

Valid Config

T47

Active

Valid

THERMTRIP#

PICD[1:0]

AGTL Outputs

All other CMOS

Outputs

Inactive

Active

T48

All other Inputs

Datasheet

39

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 15. Power-On Reset and Configuration Timings

BCLK

Vcc_CORE, V_TT

,

V_REF

V_{IH, min}

T_b

PWRGOOD

V_{IL, max}

T_a

RESET#

T_C

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Valid Ratio

T_a= T15 (PWRGOOD Inactive Pulse)

T_b= T10 (RESET# Pulse Width)

T_c= T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)

Figure 16. Test Timings (TAP Connection)

TCK

T_v

T_r

T_w

T_s

TDI, TMS

Input

Signal

T_x

T_y

T_u

T_z

TDO

Output

Signal

T_r= T43 (All Non-Test Inputs Setup Time)

T_s= T44 (All Non-Test Inputs Hold Time)

T_u= T40 (TDO Float Delay)

T_v= T37 (TDI, TMS Setup Time)

T_w= T38 (TDI, TMS Hold TIme)

T_x= T39 (TDO Valid Delay)

T_y= T41 (All Non-Test Outputs Valid Delay)

T_z= T42 (All Non-Test Outputs Float Time)

40

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 17. Test Reset Timings

TRST#

1.00V

T36

T36 = TRST# Pulse Width

Datasheet

41

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

3.0

Signal Quality Specifications

Signals driven on the processor system bus should meet signal quality specifications to ensure that

the components read data properly and to ensure that incoming signals do not affect the long term

reliability of the component. Specifications are provided for simulation at the processor pins.

Meeting the specifications at the processor pins in Table 23, Table 24, and Table 27 ensures that

signal quality effects will not adversely affect processor operation.

3.1

BCLK/BCLK# & PICCLK Signal Quality Specifications and

Measurement Guidelines

Table 24 describes the signal quality specifications at the processor pins for the processor system

bus clock (BCLK/BCLK#) and APIC clock (PICCLK) signals. References made to BCLK signal

quality specifications also applies to BCLK#. Figure 18 describes the signal quality waveform for

the system bus clock at the processor pins.

Table 23. BCLK (Single-Ended Clock Mode) Signal Quality Specifications for Simulation at

the Processor Pins¹

T# Parameter

Min

Nom

Max

Unit

Figure

Notes

V1: BCLK VIL

V2: BCLK VIH

0.3

V

18

2.2

-0.5

2.0

V3: BCLK Absolute Voltage Range

V4: BCLK Rising Edge Ringback

V5: BCLK Falling Edge Ringback

3.1

0.5

2

Table 24. BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality Specifications

for Simulation at the Processor Pins ¹

T# Parameter

Min

Nom

Max

Unit

Figure

Notes

V1: BCLK VIL

-0.2

0.35

0.40

1.45

V

18

V1: PICCLK VIL

V2: BCLK VIH

0.92

1.60

-0.2

-0.4

0.35

1.60

V2 PICCLK VIH

V3: BCLK Absolute Voltage Range

V3: PICCLK Absolute Voltage Range

V4: BCLK Rising Edge Ringback

V4: PICCLK Rising Edge Ringback

V5: BCLK Falling Edge Ringback

V5: PICCLK Falling Edge Ringback

1.45

2.4

2

-0.35

0.40

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processors based on

0.13 micron process frequencies.

2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the BCLK/BCLK# and PICCLK signals can dip back to after passing the VIH (rising) or VIL (falling)

voltage limits. This specification is an absolute value.

42

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 18. BCLK/BCLK#, PICCLK Generic Clock Waveform at the Processor Pins

V3

V4

V2

V1

V5

V3

3.2

AGTL Signal Quality Specifications and Measurement

Guidelines

Many scenarios have been simulated to generate a set of AGTL layout guidelines that are available

in the appropriate platform design guide. Refer to the Intel^®Pentium^®II Processor Developer's

Manual (Order Number 243502) for the AGTL buffer specification.

Table 25 provides the AGTL signal quality specifications for the processor for use in simulating

signal quality at the processor pins.

The Pentium III processor based on 0.13 micron process maximum allowable overshoot and

undershoot specifications for a given duration of time are detailed in Table 24 through Table 26.

Figure 19 shows the AGTL ringback tolerance and Figure 20 shows the overshoot/undershoot

waveform.

Table 25. AGTL Signal Groups Ringback Tolerance Specifications at the Processor Pins ^{1, 2, 3}

T# Parameter

Min

Unit

Figure

Notes

4, 8

α: Overshoot

100

0.50

±200

200

mV

ns

19

τ: Minimum Time at High

ρ: Amplitude of Ringback

φ: Final Settling Voltage

mV

ns

5, 6, 7, 8

8

δ: Duration of Squarewave Ringback

N/A

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processors based on

0.13 micron process frequencies.

2. Specifications are for the edge rate of 0.3 – 3 V/ns. See Figure 19 for the generic waveform.

3. All values specified by design characterization.

4. See Table 24 for maximum allowable overshoot.

5. Ringback between VREF + 100 mV and VREF + 200 mV or VREF – 300 mV and VREF – 100 mVs requires the

flight time measurements to be adjusted as described in the Intel AGTL Specifications. Ringback below

VREF + 100 mV or above VREF – 100 mV is not supported.

6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other

sources of system noise.

7. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = -100 mV specifies the

signal cannot ringback below VREF + 100 mV).

8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200 mV.

Datasheet

43

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 19. Low to High AGTL Receiver Ringback Tolerance

τ

α

V_REF+ 0.2

φ

V_REF

ρ

V_REF- 0.2

δ

0.7V Clk Ref

V_start

Clock

Time

Note: High to low case is analogous

3.2.1

Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high

voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast

signal edge rates. The processor can be damaged by repeated overshoot events on 1.25 V or 2.5 V

tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining

the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse

direction and the activity factor (AF). Permanent damage to the processor is the likely result of

excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make

satisfying the ringback specification difficult.

When performing simulations to determine impact of overshoot and undershoot, ESD diodes must

be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide

overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not

clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models

are being used to characterize the Pentium III processor based on 0.13 micron process performance,

care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O Buffer

models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an

I/O Buffer model will impact results and may yield excessive overshoot/undershoot.

3.2.1.1

Overshoot/Undershoot Magnitude

Magnitude describes the maximum potential difference between a signal and its voltage reference

level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS

using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to

VTT. This could be accomplished by simultaneously measuring the VTT plane while measuring the

signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform. The

true undershoot waveform can also be obtained with the following oscilloscope data file analysis:

Converted Undershoot Waveform = VTT – Signal_measured

44

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Note: The converted undershoot waveform appears as a positive (overshoot) signal.

Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact

must be determined independently.

After the true waveform conversion, the undershoot/overshoot specifications shown in Table 26

through Table 29 can be applied to the converted undershoot waveform using the same magnitude

and pulse duration specifications used with an overshoot waveform.

Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed

in Table 26 through Table 29. These specifications must not be violated at any time regardless of

bus activity or system state. Within these specifications are threshold levels that define different

allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the

Absolute Maximum Specifications (1.78 V AGTL, 2.08 V CMOS), the pulse magnitude, duration

and activity factor must all be used to determine if the overshoot/undershoot pulse is within

specifications.

3.2.1.2

Overshoot/Undershoot Pulse Duration

Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/

undershoot reference voltage (Vos_ref = 1.32 V AGTL, 1.80 V CMOS). The total time could

encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses

within a single overshoot/undershoot event may need to be measured to determine the total pulse

duration.

Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot

pulse duration.

Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered

together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the

individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that

total event.

3.2.1.3

Activity Factor

Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a

clock. Since the highest frequency of assertion of an AGTL or a CMOS signal is every other clock,

an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER

clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform

occurs one time in every 200 clock cycles.

The specifications provided in Table 26 through Table 29 show the Maximum Pulse Duration

allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table

entry is independent of all others, meaning that the Pulse Duration reflects the existence of

overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot

that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can

be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the

event occurs at all times and no other events can occur).

Note: Activity factor for AGTL signals is referenced to system bus clock frequency.

Note: Activity factor for CMOS signals is referenced to PICCLK frequency.

Datasheet

45

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

3.2.1.4

Reading Overshoot/Undershoot Specification Tables

The overshoot/undershoot specification for the Pentium III processor based on 0.13 micron process

is not a simple single value. Instead, many factors are needed to determine what the over/

undershoot specification is. In addition to the magnitude of the overshoot, the following parameters

must also be known: the junction temperature the processor will be operating at, the width of the

overshoot (as measured above TBD V) and the Activity Factor (AF). To determine the allowed

overshoot for a particular overshoot event, the following must be done:

1. Determine the signal group of the particular signal. If the signal is an AGTL signal operating

with a 133 MHz system bus, use Table 27 (133 MHz AGTL signal group). If the signal is a

CMOS signal, use Table 29 (33 MHz CMOS signal group).

2. Determine the maximum case temperature (Tcase) for the range of processors that the system

will support (65^oC).

3. Determine the magnitude of the overshoot (relative to VSS)

4. Determine the Activity Factor (how often does this overshoot occur?)

5. From the appropriate specification table, read off the maximum pulse duration (in ns) allowed.

6. Compare the specified maximum pulse duration to the signal being measured. If the pulse

duration measured is less than the pulse duration shown in the table, the signal meets the

specifications.

The above procedure is similar for undershoots after the undershoot waveform has been converted

to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events

as they are mutually exclusive.

The following is an example showing how the maximum pulse duration is determined for a given

waveform.

Table 26. Example Platform Information

Required Information

Maximum Platform Support

Notes

FSB Signal Group

Max Tcase

133 MHz AGTL

72 °C

Overshoot Magnitude

1.78 V

Measured Value

Measured overshoot occurs on

average every 20 clocks

Activity Factor (AF)

0.1

Given the above parameters and using Table 27 (65^oC/AF = 0.1 column), the maximum allowed

pulse duration is 7.5 ns. Since the measure pulse duration is 7.5 ns, this particular overshoot event

passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/

undershoot events meet the specifications.

46

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

3.2.1.5

Determining if a System Meets the Overshoot/Undershoot Specifications

The overshoot/undershoot specifications listed in the following tables specify the allowable

overshoot/undershoot for a single overshoot/undershoot event. However, most systems will have

multiple overshoot and/or undershoot events that each have their own set of parameters (duration,

AF and magnitude). While each overshoot on its own may meet the overshoot specification, when

you add the total impact of all overshoot events, the system may fail. A guideline to ensure a

system passes the overshoot and undershoot specifications is shown below. It is important to meet

these guidelines; otherwise, contact your Intel field representative.

1. Insure no AGTL signal ever exceeds 1.78 V and no CMOS signal ever exceeds 2.08 V.

OR

2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot

specifications in the following tables

OR

3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse

duration for each magnitude and compare the results against the AF = 1 specifications. If all of

these worst case overshoot or undershoot events meet the specifications

(measured time < specifications) in the table (where AF=1), then the system passes.

The following notes apply to Table 26 through Table 29.

NOTES:

1. Overshoot/Undershoot Magnitude = 1.78 V (AGTL), 2.08 V (CMOS) is an absolute value and

should never be exceeded

2. Overshoot is measured relative to VSS.

3. Undershoot is measured relative to VTT

4. Overshoot/Undershoot Pulse Duration is measured relative to 1.32 V for AGTL and 1.80 V for

CMOS.

5. Rinbacks below VTT can not be subtracted from Overshoots/Undershoots

6. Lesser Undershoot does not allocate longer or larger Overshoot

7. OEMs are encouraged to follow Intel provided layout guidelines. Consult the layout guidelines

provided in the specific platform design guide.

8. All values specified by design characterization

Table 27. 133 MHz AGTL Signal Group Overshoot/Undershoot Tolerance ^{1, 2, 3}

Maximum Pulse

Duration at

Tcase = 60 °C (ns)

Maximum Pulse

Duration at

Tcase = 69 °C (ns)

Maximum Pulse

Duration at

Tcase = 71 °C (ns)

Maximum Pulse

Duration at

Tcase = 72 °C (ns)

Overshoot/

Undershoot

Magnitude

(V)

AF =

0.01

AF =

0.1

AF =

0.01

AF =

0.1

AF =

1

AF =

0.01

AF =

0.1

AF =

1

AF =

0.01

AF =

0.1

AF =

1

AF = 1

1.78

1.73

1.68

1.63

1.58

1.53

1.48

15

1.5

3.1

6.8

14

0.153

0.31

0.68

1.42

2.95

6.2

8.7

15

0.87

2.0

4.6

10

0.087

0.20

0.46

1.0

6

0.6

1.3

2.8

6

0.06

0.13

0.28

0.6

6

0.6

1.2

2.7

5

0.06

0.12

0.27

0.57

1.20

2.46

5.10

13

20

12

20

15

2.3

12

20

1.27

2.65

5.45

12

20

15

5.0

15

13.2

15

NOTES:

1. Measurements taken at the processor socket pins on the solder-side of the motherboard.

2. Overshoot/Undershoot Magnitude = 1.78 V is an absolute value and should never be exceeded.

3. BCLK Period = 7.5 ns.

Datasheet

47

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 20. Maximum Acceptable AGTL Overshoot/Undershoot Waveform

Time dependent Overshoot

0.1 ns

0.3 ns

1.78 V Max

1 ns

1.62 V

Vos_ref

1.47 V

1.32 V

c

a

b

a

b

c

Vss

-0.15 V

-0.30 V

-0.46 V Min

0.1 ns

0.3 ns

1 ns

Time dependent Undershoot

3.3

Non-AGTL Signal Quality Specifications and Measurement

Guidelines

There are three signal quality parameters defined for non-AGTL signals: overshoot/undershoot,

ringback, and settling limit. All three signal quality parameters are shown in Figure 21 for the non-

AGTL signal group.

Figure 21. Non-AGTL Overshoot/Undershoot, Settling Limit, and Ringback ¹

Settling Limit

Overshoot

V

HI

Rising-Edge

Ringback

Falling-Edge

Ringback

Settling Limit

V

LO

V

SS

Time

Undershoot

NOTE:

1. V = 1.80 V for all non-AGTL signals except for BCLK, PICCLK, and PWRGOOD. V =2.0 V for PICCLK,

HI

and V =1.8 V for PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1.

HI

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Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

3.3.1

Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high

voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast

signal edge rates (see Figure 21 for non-AGTL signals). The processor can be damaged by repeated

overshoot events on 1.25 V or 1.8 V tolerant buffers if the charge is large enough (i.e., if the

overshoot is great enough). Permanent damage to the processor is the likely result of excessive

overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the

ringback specification difficult. The overshoot/undershoot guideline is 0.3 V and assumes the

absence of diodes on the input. These guidelines should be verified in simulations without the on-

chip ESD protection diodes present because the diodes will begin clamping the 1.25 V and 2.5 V

tolerant signals beginning at approximately 0.7 V above the appropriate supply and 0.7 V below

VSS. If signals are not reaching the clamping voltage, this will not be an issue. A system should not

rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the

components and make meeting the ringback specification very difficult.

Table 28. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance

Maximum Pulse Duration

at Tcase = 69 °C (ns)

Maximum Pulse Duration

at Tcase = 71 °C (ns)

Maximum Pulse Duration

at Tcase = 72 °C (ns)

Overshoot/

Undershoot

Magnitude (V)

AF =

0.01

AF =

0.1

AF =

1

AF =

0.01

AF =

0.1

AF =

1

AF =

0.01

AF =

0.1

AF =

1

2.38

2.33

2.28

2.23

2.18

2.13

2.08

35

60

3.5

8.0

18

41

60

0.35

0.8

1.8

4.1

9.0

21

19

40

60

1.9

4

0.19

0.40

0.80

1.80

3.75

8

17

36

60

1.7

3.6

7

0.17

0.36

0.77

1.60

3.42

7

8

18

37

60

16

34

60

16

14

NOTES:The undershoot guideline limits transitions exactly as described for the ATGL signals. See

Figure 20.

Datasheet

49

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

3.3.2

Ringback Specification

Ringback refers to the amount of reflection seen after a signal has switched. The ringback

specification is the voltage that the signal rings back to after achieving its maximum absolute

value. See Figure 21 for an illustration of ringback. Excessive ringback can cause false signal

detection or extend the propagation delay. The ringback specification applies to the input pin of

each receiving agent. Violations of the signal ringback specification are not allowed under any

circumstances for non-AGTL signals.

Ringback can be simulated with or without the input protection diodes that can be added to the

input buffer model. However, signals that reach the clamping voltage should be evaluated further.

See Table 29 for the signal ringback specifications for non-AGTL signals for simulations at the

processor pins.

Table 29. Signal Ringback Specifications for Non-AGTL Signal Simulation at the Processor

Pins ¹

Maximum Ringback

Input Signal Group

Transition

(with Input Diodes Present)

Unit

Figure

2

Non-AGTL Signals

0 → 1

1 → 0

0 → 1

Vcmos_ref + 0.200

Vcmos_ref – 0.300

1.44

V

21

2

Non-AGTL Signals

PWRGOOD

NOTES:

®

1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processor based on

0.13 micron process frequencies.

2. Non-AGTL signals except PWRGOOD.

3.3.3

Settling Limit Guideline

Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach

before its next transition. The amount allowed is 10% of the total signal swing (V_HI_–V) above

LO

and below its final value. A signal should be within the settling limits of its final value, when either

in its high state or low state, before it transitions again.

Signals that are not within their settling limit before transitioning are at risk of unwanted

oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be

done either with or without the input protection diodes present. Violation of the settling limit

guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of

the ringing increasing in the subsequent transitions.

50

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

4.0

Thermal Specifications and Design Considerations

This chapter provides needed data for designing a thermal solution. However, for the correct

thermal measuring processes, refer to the Intel^®Pentium^®III Processor in the FC-PGA2 Package

Thermal Design Guidelines document. The Pentium III processor based on 0.13 micron process

uses flip chip pin grid array packaging technology with a Integrated Heat Spreader and has a case

temperature (T_case) specified.

4.1

Thermal Specifications

Table 30 provides the thermal design power dissipation and maximum temperatures for the

Pentium III processor based on 0.13 micron process. Systems should design for the highest possible

processor power, even if a processor with a lower thermal dissipation is planned. A thermal

solution should be designed to ensure the case temperature never exceeds these specifications.

®

1

Table 30. Intel Pentium III Processor Based on 0.13 micron Process Thermal Design Power

Processor

L2 Cache

Size

(KBs)

Processor

Power

Core

Frequency

(GHz)

Maximum

2

Processor

T

(°C)

CASE

(W)

1A

1.13A

1.20

1.33

1.00

1.13

1.20

1.33

256

27.6

29.1

29.9

33.9

69

71

NOTES:

1. These values are specified at nominal VCC

for the processor pins.

CORE

2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL bus

termination. The maximum power for each of these components does not occur simultaneously.

3. Processor core power includes only the power dissipated by the core die.

4.1.1

THERMTRIP# Requirement

In the event the processor drives the THERMTRIP# signal active during valid operation, both the

VCC and VTT supplies to the processor must be turned off to prevent thermal runaway of the

processor. Valid operation refers to the operating conditions where the THERMTRIP# signal is

guaranteed valid. The time required from THERMTRIP# asserted to VCC rail at 1/2 nominal is

5 sec and THERMTRIP# asserted to VTT rail at 1/2 nominal is 5 sec.

Table 31. THERMTRIP# Time Requirement

Power Rail

Power Target

Time Required For Power Drop

VCC

VTT

1/2 Nominal VCC

1/2 Nominal VTT

5 seconds

NOTE: Once Vcc and VTT supplies are turned off the THERMTRIP# signal will be deactivated. System logic

should ensure no “unsafe” power cycling occurs due to this deassertion.

Datasheet

51

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

4.1.2

Thermal Diode

The Pentium III processor based on 0.13 micron process incorporates an on-die diode that may be

used to monitor the die temperature (junction temperature). A thermal sensor located on the

motherboard, or a stand-alone measurement kit, may monitor the die temperature of the processor

for thermal management or instrumentation purposes. Table 32 and Table 33 provide the diode

parameter and interface specifications.

The Pentium III processor based on 0.13 micron process uses an Integrated Heat Spreader (IHS)

and has a case temperature requirement. See the Intel^®Pentium^®III Processor in the FC-PGA2

Package Thermal Design Guidelines document for details on measuring the case temperature. The

thermal diode should be used for system thermal management and not determining specification

compliance.

Table 32. Thermal Diode Parameters¹

Symbol

Parameter

Forward Bias Current

Min

Typ

Max

Unit

Notes

I

5

N/A

150

µA

1

fw

n

Diode Ideality Factor

Forward Bias Current

Diode Ideality Factor

1.001452

5

1.007152

N/A

1.012852

300

2, 4, 5

1

I

µA

fw

n

1.000807

1.009528

1.018249

3, 4, 5

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized at 75° C with a forward bias current of 5 – 150 µA.

3. Characterized at 75° C with a forward bias current of 5 – 300 µA.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

equation:

I

=Is(e^ ((Vd*q)/(nkT)) - 1), where Is = saturation current, q = electronic charge, Vd = voltage across the

fw

diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).

5. Not 100% tested. Specified by design characterization.

Table 33. Thermal Diode Interface

Pin Name

PGA370 Socket pin #

Pin Description

THERMDP

THERMDN

AL31

AL29

diode anode (p_junction)

diode cathode (n_junction)

4.2

Thermal Metrology

The thermal metrology for the Pentium III processor based on 0.13 micron process in the FC-PGA2

package should be followed to evaluate the thermal performance of proposed cooling solutions.

The thermal metrology is contained in the Intel^®Pentium^®III Processor in the FC-PGA2 Package

Thermal Design Guidelines document.

52

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

5.0

Mechanical Specifications

The Pentium III processor based on 0.13 micron process uses a FC-PGA2 package technology.

Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a

complete terminology listing.

The processor utilizes a PGA370 socket for installation into the motherboard. Details on the socket

are available in the 370-Pin Socket (PGA370) Design Guidelines.

Note: For Figure 22, the following apply:

1. Unless otherwise specified, the following drawings are dimensioned in inches.

2. All dimensions provided with tolerances are guaranteed to be met for all normal production

product.

3. Figures and drawings labeled as “Reference Dimensions” are provided for informational

purposes only. Reference dimensions are extracted from the mechanical design database and

are nominal dimensions with no tolerance information applied. Reference dimensions are

NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in

parentheses without tolerances are reference dimensions.

4. Drawings are not to scale.

5.1

FC-PGA2 Mechanical Specifications

Figure 22 is provided to aid in the design of heatsink and clip solutions as well as demonstrate

where pin-side capacitors will be located on the processor. Table 34 includes the measurements for

these dimensions in both inches and millimeters.

Figure 22. Package Dimensions

Datasheet

53

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 34. Intel^®Pentium^®III Processor Based on 0.13 micron Process Package Dimensions

Millimeters

Maximum

Inches

Symbol

Minimum

Notes

Minimum

Maximum

Notes

A1

A2

B1

B2

C1

C2

D

2.266

0.980

2.690

1.180

0.089

0.038

1.212

0.106

0.047

1.229

30.800

31.200

33.000 max

49.428

1.299 max

49.632

45.974

17.780

0.889

1.946

1.790

0.000

1.954

1.810

0.700

0.035

D1

G1

G2

G3

H

45.466

0.000

2.540

Nominal

0.100

Nominal

L

3.048

0.431

3.302

0.483

0.120

0.017

0.130

0.019

ΦP

Pin TP

0.508 Diametric True Position (Pin-to-Pin)

0.020 Diametric True Position (Pin-to-Pin)

NOTE: Capacitors will be placed on the pin-side of the FC-PGA2 package in the area defined by G1, G2, and

G3. This area is a keepout zone for motherboard designers.

For Table 35, the following apply:

1. It is not recommended to use any portion of the processor substrate as a mechanical reference

or load bearing surface for thermal solutions.

2. Parameters assume uniformly applied loads.

Table 35. Processor Case Loading Parameters

1

2,3

Parameter

IHS Surface

Dynamic (max)

Static (max)

Unit

200

125

75

100

N/A

lbf

ibf

IHS Edge

IHS Corner

NOTES:

1. This specification applies to a uniform and a non-uniform load.

2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and

processor interface.

3. See socket manufacturer’s force loading specification also to ensure compliance. Maximum static loading

listed here does not account for the maximum reaction forces on the socket tabs or pins.

54

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

5.2

Recommended Mechanical Keep-Out Zones

Figure 23. Volumetric Keep-Out

Figure 24. Component Keep-Out

Datasheet

55

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

5.3

Processor Markings

Figure 25 shows the processor top-side markings; the markings are provided to aid in the

identification of a Pentium III processor based on 0.13 micron process. Table 34 lists the

measurements for the package dimensions.

Figure 25. Top Side Processor Markings

GRP1LN1: Intel '01 (m)(c)__-__(Country Of Origin)

GRP1LN2: (FPO)–(S/N)

GRP1LN1

GRP1LN2

GRP2LN1

GRP2LN2

GRP2LN1: (Core Frequency)/(Cache Size)/(FSB)/(VID)

GRP2LN2: (S-Spec)

56

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

5.4

Processor Signal Listing

Table 36 and Table 37 provide the processor pin definitions. The signal locations on the PGA370

socket are to be used for signal routing, simulation, and component placement on the baseboard.

Figure 26 provides a pin-side view of the Pentium III processor based on 0.13 micron process

pinout.

Figure 26. Intel^®Pentium^®III Processor Based on 0.13 micron Process Pinout

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

AN

AM

AL

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Z

AN

AM

AL

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Z

DYN_OE

A12

A15

A16

A6

VTT

AP0

AP1

VTT

VCC

VTT

BPRI

DEFER

VSS VCC

REQ3

LOCK

VSS

REQ2

VTT

RP

TRDY

HIT

DRDY

BR0

ADS

TRST

TDI

TDO

VID2

KEY

VCC

VSS

VCC

A3

VSS

A11

VCC

VSS

A14

VCC

VSS

VCC

THRMDP

VSS

VID1

VCC

VTT

VSS

A13

A9

A7

REQ4

HITM

DBSY

PWRGD

VCC VSS

THRMDN

RS2

TCK

TMS

BSEL0

VSS

VID0

RSV

A21

VCC

VttPWRGD A28

VREF6

VSS

REQ0

VCC

CMOSREF AERR

VCC VSS

VCC

VID25m

V

RSV

BSEL1

RESET2#

RESET

A19

VCC

VSS

VCC

VSS

VCC

SMI

VID3

VSS

VCC

VSS

A10

A25

A5

A8

A4

BNR

REQ1

VTT

RS1

VCC

RS0

SLP

VCC

THERM

TRIP

VSS

VCC

INIT

STPCLK

IGNNE

VTT

A17

DETECT

VSS

VCC

VSS

VCC

VSS

A35

A31

A24

A22

A20

A20M

IERR

FLUSH

VCC

VREF5

VTT

A33

VSS

VTT

VCC

FERR

RSP

VCC

VSS

BR1

A23

A18

A32

VTT

VCC

A27

RSV

D0

A30

A26

A34

D15

VCC

VSS

VCC

RSV

VSS

VCC

VSS

A29

Y

BCLK#/

CLKREF

VCC

VSS

X

VSS

VSS VTT

W

V

W

V

PLL1

VCC

PLL2

VSS

RSV

VTT

BCLK

VSS

VCC

RSV

VCC

VSS

BERR

VREF4

Pin Side View

U

VTT

D4

VSS

T

D1

D6

VCC

VSS

VCC

VSS

S

RTT

CTRL

VCC

D8

D5

VCC

VSS

VTT

RSV

R

D17

D18

D11

VREF3

VCC

VSS

VCC

Q

D12

RSV

D10

RSV

P

D9

VSS

N

D2

D14

D20

D30

VCC

NCHCTRL

LINT1

RSV

M

D3

LINT0

L

D13

VSS

PICD1

VCC

PICD0

K

VCC

VREF2

VCC

D24

D19

VCC

VSS

J

D7

PICCLK

VCC

PREQ

VTT

H

VSS

D16

VSS

VCC

G

D21

D26

D33

D23

D25

VCC

VSS

VCC

D31

BP2

VTT

F

VCC

VSS

VCC

VSS

D32

D22

D38

D27

D42

VCC

D41

D63

VSS

RSV

VCC

VSS

VCC

VSS

SLEW

VCC

VSS

VCC

VSS

VREF1

VSS

RSV

E

VSS

D34

VCC

D36

VSS

D45

VCC

D49

VSS

D40

VCC

VTT

D62

D50

DEP6

DEP5

DEP4 VREF0

VCC

BPM1

VCC

BP3

CTRL

D

VCC

D39

D52

VSS

VCC

VSS

VCC

VSS

C

D59

D55

D54

D58

D56

DEP1

DEP0

BPM0

VCC BINIT

CPUPRES

B

VCC

D35

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

A

D37

D29

D28

D43

D44

D51

D47

D48

D57

D46

D60

D61

DEP7

DEP3

DEP2

PRDY

D53

VSS

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

Datasheet

57

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 36. Signal Listing in Order by

Signal Name

Table 36. Signal Listing in Order by

Signal Name (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

No.

A3#

AK8

AGTL I/O

BERR#

V4

AGTL I/O

AGTL Input

AGTL I/O

3.3V Output

Power/Other

AGTL I/O

A4#

AH12

AH8

AN9

AL15

AH10

AL9

AH6

AK10

AN5

AL7

AK14

AL5

AN7

AE1

Z6

AGTL I/O

CMOS Input

AGTL I/O

System Bus Clock

BINIT#

BNR#

BP2#

BP3#

BPM0#

BPM1#

BPRI#

BR0#

BR1#

BSEL0

BSEL1

CPUPRES#

D0#

B36

AH14

G33

E37

C35

E35

AN17

AN29

X2

A5#

A6#

A7#

A8#

A9#

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

A33#

A34#

A35#

A20M#

ADS#

AERR#

AP0#

AP1#

BCLK

BCLK#/CLKREF

AJ33

AJ31

C37

W1

T4

D1#

D2#

N1

AG3

AC3

AJ1

D3#

M6

U1

D4#

D5#

S3

AE3

AB6

AB4

AF6

Y3

D6#

T6

D7#

J1

D8#

S1

D9#

P6

D10#

D11#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

Q3

AA1

AK6

Z4

M4

Q1

L1

AA3

AD4

X6

N3

U3

H4

AC1

W3

R4

P4

AF4

AE33

AN31

AK24

AL11

AN13

W37

Y33

H6

L3

G1

F8

G3

K6

E3

E1

58

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 36. Signal Listing in Order by

Signal Name (Continued)

No.

Pin Name

Signal Group

No.

Pin Name

Signal Group

D27#

F12

A5

AGTL I/O

AGTL Input

AGTL I/O

DEP1#

C31

AGTL I/O

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBSY#

DEFER#

DEP0#

DEP2#

A33

AGTL I/O

A3

DEP3#

A31

AGTL I/O

J3

DEP4#

E31

AGTL I/O

C5

DEP5#

C29

AGTL I/O

F6

DEP6#

E29

AGTL I/O

C1

DEP7#

A29

AGTL I/O

C7

DETECT

DRDY#

DYN_OE

FERR#

FLUSH#

HIT#

AF36

AN27

AN3

AC35

AE37

AL25

AL23

AE35

AG37

AG33

AM2

M36

L37

Power/Other

AGTL I/O

B2

C9

Power/Other

CMOS Output

CMOS Input

AGTL I/O

A9

D8

D10

C15

D14

D12

A7

HITM#

AGTL I/O

IERR#

CMOS Output

CMOS Input

Power/Other

CMOS Input

AGTL I/O

IGNNE#

INIT#

A11

C11

A21

A15

A17

C13

C25

A13

D16

A23

C21

C19

C27

A19

C23

C17

A25

A27

E25

F16

AL27

AN19

C33

KEY

LINT0/INTR

LINT1/NMI

LOCK#

NCHCTRL

PICCLK

PICD0

AK20

N37

Power/Other

APIC Clock Input

APIC I/O

J33

J35

PICD1

L35

APIC I/O

PLL1

W33

U33

Power/Other

AGTL Output

CMOS Input

AGTL I/O

PLL2

PRDY#

PREQ#

PWRGOOD

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

Reserved

A35

J37

AK26

AK18

AH16

AH18

AL19

AL17

AK30

AL1

AGTL I/O

Reserved for future use

F10

E21

L33

Datasheet

59

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 36. Signal Listing in Order by

Signal Name (Continued)

Table 36. Signal Listing in Order by

Signal Name (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

No.

Reserved

RESET#

RESET2#

RP#

N33

Reserved for future use

AGTL Input

VCC

AH36

AJ13

AJ17

AJ21

AJ25

AJ29

AJ5

Power/Other

CORE

N35

VCC

Q33

Q35

Q37

R2

W35

Y1

AJ9

Z36

AK2

AK34

AM12

AM16

AM20

AM24

AM28

AM32

AM4

AM8

B10

B14

B18

B22

B26

B30

B34

B6

AH4

AJ3

AGTL Input

AN23

AH26

AH22

AK28

AC37

S35

AGTL I/O

RS0#

AGTL + Input

AGTL Input

RS1#

RS2#

AGTL Input

RSP#

AGTL Input

RTTCTRL

SLEWCTRL

SLP#

Power/Other

E27

Power/Other

AH30

AJ35

AG35

AL33

AN35

AN37

AL29

AL31

CMOS Input

SMI#

CMOS Input

STPCLK#

TCK

CMOS Input

TAP Input

TDI

TAP Input

TDO

TAP Output

THERMDN

THERMDP

Power/Other

THERMTRIP# AH28

CMOS Output

TAP Input

C3

TMS

AK32

AN25

AN33

AA37

AA5

D20

D24

D28

D32

D36

D6

TRDY#

TRST#

AGTL Input

TAP Input

VCC

Power/Other

CORE

Power/Other

AB2

Power/Other

AB34

AD32

AE5

Power/Other

E13

E17

E5

Power/Other

AF2

Power/Other

E9

AF34

AH24

AH32

Power/Other

F14

Power/Other

F2

Power/Other

F22

60

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 36. Signal Listing in Order by

Signal Name (Continued)

No.

Pin Name

Signal Group

No.

Pin Name

Signal Group

VCC

F26

F30

F34

F4

Power/Other

3.3V Output

Power/Other

Vss

AC5

Power/Other

CORE

CMOS_REF

VCC

Vss

AD2

AD34

AF32

AG5

AH2

AH34

AJ11

AJ15

AJ19

AJ23

AJ27

AJ7

Power/Other

H32

H36

J5

K2

K32

K34

M32

N5

P2

P34

R32

R36

S5

AL3

AM10

AM14

AM18

AM22

AM26

AM30

AM34

AM6

B12

T2

T34

V32

V36

W5

Y35

Z32

AK22

AK36

AL35

AM36

AL37

AJ37

E33

F18

K4

B16

V

B20

VID 25mV

VID0

B24

B28

VID1

B32

VID2

B4

VID3

B8

VREF0

VREF1

VREF2

VREF3

VREF4

VREF5

VREF6

Vss

D18

D2

D22

R6

D26

V6

D30

AD6

AK12

A37

AB32

AC33

D34

D4

E11

Vss

E15

Vss

E19

Datasheet

61

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 36. Signal Listing in Order by

Signal Name (Continued)

Table 36. Signal Listing in Order by

Signal Name (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

No.

Vss

E7

Power/Other

Vss

Y37

Power/Other

Vss

F20

F24

F28

F32

F36

G5

Power/Other

Vss

VTT

Y5

Z2

Z34

AB36

AH20

AK16

AL13

AL21

AN11

AN15

E23

H2

H34

K36

L5

M2

M34

P32

P36

Q5

G35

G37

S33

AD36

AG1

X34

R34

T32

T36

U5

AA33

AA35

AN21

S37

V2

V34

X32

X36

X4

U35

U37

VTT_PWRGD AK4

62

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 37. Signal Listing in Order by Pin

Number (Continued)

Number

No.

Pin Name

Signal Group

AGTL I/O

Pin Name

Signal Group

A3

D29#

AD34

AD36

AE1

Vss

Power/Other

A5

D28#

D43#

D37#

D44#

D51#

D47#

D48#

D57#

D46#

D53#

D60#

D61#

DEP7#

DEP3#

DEP2#

PRDY#

Vss

AGTL I/O

VTT

Power/Other

AGTL I/O

A7

AGTL I/O

A17#

A22#

A9

AGTL I/O

AE3

AGTL I/O

A11

AGTL I/O

AE5

VCC

CORE

Power/Other

CMOS Input

CMOS Output

CMOS Input

Power/Other

AGTL I/O

A13

A15

A17

A19

A21

A23

A25

A27

A29

A31

A33

A35

A37

AA1

AA3

AA5

AA33

AA35

AA37

AB2

AB4

AB6

AB32

AB34

AB36

AC1

AC3

AC5

AC33

AC35

AC37

AD2

AD4

AD6

AD32

AGTL I/O

AE33

AE35

AE37

AF2

A20M#

IERR#

AGTL I/O

FLUSH#

AGTL I/O

VCC

CORE

AGTL I/O

AF4

A35#

A25#

Vss

AGTL I/O

AF6

AGTL I/O

AF32

AF34

AF36

AG1

Power/Other

AGTL I/O

VCC

CORE

AGTL I/O

DETECT

VTT

AGTL I/O

AG3

A19#

AGTL Output

Power/Other

AGTL I/O

AG5

Vss

Power/Other

CMOS Input

Power/Other

AGTL Input

AGTL I/O

AG33

AG35

AG37

AH2

INIT#

STPCLK#

IGNNE#

Vss

A27#

A30#

AGTL I/O

VCC

VTT

VCC

Power/Other

AGTL I/O

CORE

AH4

RESET#

A10#

AH6

AH8

A5#

AGTL I/O

CORE

AH10

AH12

AH14

AH16

AH18

AH20

AH22

AH24

AH26

AH28

AH30

AH32

AH34

AH36

AJ1

A8#

AGTL I/O

A24#

A23#

Vss

A4#

AGTL I/O

BNR#

REQ1#

REQ2#

VTT

AGTL I/O

Power/Other

AGTL I/O

VCC

AGTL I/O

CORE

VTT

Power/Other

AGTL Input

Power/Other

AGTL + Input

A33#

A20#

Vss

RS1#

AGTL I/O

VCC

CORE

Power/Other

CMOS Output

AGTL Input

Power/Other

AGTL I/O

RS0#

Vss

THERMTRIP# CMOS Output

FERR#

RSP#

Vss

SLP#

CMOS Input

Power/Other

AGTL I/O

VCC

Vss

VCC

CORE

A31#

VREF5

CORE

Power/Other

A21#

VCC

CORE

AJ3

RESET2#

AGTL Input

Datasheet

63

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 37. Signal Listing in Order by Pin

Number (Continued)

Table 37. Signal Listing in Order by Pin

Number (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

AJ5

VCC

Power/Other

AL11

AL13

AL15

AL17

AL19

AL21

AL23

AL25

AL27

AL29

AL31

AL33

AL35

AL37

AM2

AP0#

AGTL I/O

CORE

AJ7

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Power/Other

3.3V Output

CMOS Input

3.3V Output

Power/Other

VTT

Power/Other

AGTL I/O

AJ9

A7#

AJ11

AJ13

AJ15

AJ17

AJ19

AJ21

AJ23

AJ25

AJ27

AJ29

AJ31

AJ33

AJ35

AJ37

AK2

REQ4#

REQ3#

VTT

AGTL I/O

Power/Other

AGTL I/O

HITM#

HIT#

AGTL I/O

DBSY#

THERMDN

THERMDP

TCK

AGTL I/O

Power/Other

TAP Input

VID0

3.3V Output

Power/Other

3.3V Output

Power/Other

AGTL I/O

BSEL1

BSEL0

SMI#

VID2

KEY

AM4

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

CORE

VID3

AM6

VCC

AM8

CORE

AK4

VTT_PWRGD Power/Other

AM10

AM12

AM14

AM16

AM18

AM20

AM22

AM24

AM26

AM28

AM30

AM32

AM34

AM36

AN3

AK6

A28#

A3#

AGTL I/O

AK8

AGTL I/O

AK10

AK12

AK14

AK16

AK18

AK20

AK22

AK24

AK26

AK28

AK30

AK32

AK34

AK36

AL1

A11#

VREF6

A14#

VTT

AGTL I/O

Power/Other

AGTL I/O

Power/Other

AGTL I/O

REQ0#

LOCK#

AGTL I/O

V

Power/Other

AGTL I/O

CMOS_REF

AERR#

PWRGOOD

RS2#

CMOS Input

AGTL Input

Reserved for future use

TAP Input

Reserved

TMS

VID1

DYN_OE

A12#

A16#

A6#

VCC

Power/Other

3.3V Output

Reserved for future use

Power/Other

AGTL I/O

AN5

CORE

VID 25mV

Reserved

Vss

AN7

AGTL I/O

AN9

AGTL I/O

AL3

AN11

AN13

AN15

AN17

VTT

Power/Other

AGTL I/O

AL5

A15#

AP1#

VTT

AL7

A13#

AGTL I/O

Power/Other

AGTL Input

AL9

A9#

AGTL I/O

BPRI#

64

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 37. Signal Listing in Order by Pin

Number (Continued)

Table 37. Signal Listing in Order by Pin

Number (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

AN19

AN21

AN23

AN25

AN27

AN29

AN31

AN33

AN35

AN37

B2

DEFER#

VTT

AGTL Input

Power/Other

AGTL I/O

C25

D50#

AGTL I/O

C27

C29

C31

C33

C35

C37

D2

D56#

AGTL I/O

RP#

DEP5#

DEP1#

DEP0#

BPM0#

CPUPRES#

VSS

AGTL I/O

TRDY#

DRDY#

BR0#

ADS#

TRST#

TDI

AGTL Input

AGTL I/O

Power/Other

AGTL I/O

TAP Input

D4

Vss

TDO

TAP Output

AGTL I/O

D6

VCC

CORE

D35#

Vss

D8

D38#

D39#

D42#

D41#

D52#

Vss

B4

Power/Other

AGTL I/O

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D32

D34

D36

E1

AGTL I/O

B6

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

AGTL I/O

CORE

B8

AGTL I/O

B10

B12

B14

B16

B18

B20

B22

B24

B26

B28

B30

B32

B34

B36

C1

AGTL I/O

Power/Other

AGTL I/O

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

VCC

CORE

D26#

D25#

E3

AGTL I/O

BINIT#

D33#

E5

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

Power/Other

Reserved for future use

Power/Other

AGTL I/O

CORE

AGTL I/O

E7

C3

VCC

CORE

Power/Other

AGTL I/O

E9

C5

D31#

D34#

D36#

D45#

D49#

D40#

D59#

D55#

D54#

D58#

E11

E13

E15

E17

E19

E21

E23

E25

E27

E29

C7

AGTL I/O

C9

AGTL I/O

C11

C13

C15

C17

C19

C21

C23

AGTL I/O

Reserved

4

AGTL I/O

VTT

AGTL I/O

D62#

AGTL I/O

SLEWCTRL

DEP6#

Power/Other

AGTL I/O

Datasheet

65

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 37. Signal Listing in Order by Pin

Number (Continued)

Table 37. Signal Listing in Order by Pin

Number (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

E31

DEP4#

AGTL I/O

K2

VCC

CORE

Power/Other

AGTL I/O

E33

E35

E37

F2

VREF0

BPM1#

BP3#

Power/Other

AGTL I/O

K4

VREF2

D24#

K6

AGTL I/O

K32

K34

K36

L1

VCC

Vss

Power/Other

AGTL I/O

CORE

VCC

Power/Other

AGTL I/O

CORE

F4

F6

D32#

D13#

F8

D22#

AGTL I/O

L3

D20#

AGTL I/O

F10

F12

F14

F16

F18

F20

F22

F24

F26

F28

F30

F32

F34

F36

G1

Reserved

D27#

Reserved for future use

AGTL I/O

L5

Vss

Power/Other

Reserved for future use

APIC I/O

L33

L35

L37

M2

M4

M6

M32

M34

M36

N1

Reserved

PICD1

LINT1/NMI

Vss

VCC

Power/Other

AGTL I/O

CORE

D63#

VREF1

Vss

CMOS Input

Power/Other

AGTL I/O

Power/Other

AGTL I/O

D11#

VCC

Vss

VCC

Vss

VCC

Vss

VCC

Vss

D3#

AGTL I/O

CORE

VCC

Power/Other

CMOS Input

AGTL I/O

CORE

Vss

LINT0/INTR

D2#

N3

D14#

AGTL I/O

N5

VCC

CORE

Power/Other

Reserved for future use

Power/Other

AGTL I/O

N33

N35

Q33

P2

Reserved

D21#

D23#

Vss

G3

AGTL I/O

G5

Power/Other

AGTL I/O

VCC

CORE

G33

G35

G37

H2

BP2#

VTT

P4

D18#

D9#

Vss

Power/Other

AGTL I/O

P6

AGTL I/O

VTT

P32

P34

P36

Q1

Power/Other

AGTL I/O

Vss

VCC

CORE

H4

D16#

D19#

Vss

H6

AGTL I/O

D12#

H32

H34

H36

J1

VCC

Vss

VCC

D7#

Power/Other

AGTL I/O

Q3

D10#

AGTL I/O

CORE

Q5

Vss

Power/Other

Reserved for future use

AGTL I/O

N37

Q35

Q37

R2

NCHCTRL

Reserved

D17#

CORE

J3

D30#

AGTL I/O

J5

VCC

Power/Other

APIC Clock Input

APIC I/O

CORE

J33

J35

J37

PICCLK

PICD0

R4

R6

VREF3

Power/Other

PREQ#

CMOS Input

R32

VCC

CORE

66

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 37. Signal Listing in Order by Pin

Number (Continued)

Table 37. Signal Listing in Order by Pin

Number (Continued)

No.

Pin Name

Signal Group

Pin Name

Signal Group

R34

Vss

Power/Other

AGTL I/O

V36

VCC

CORE

Power/Other

R36

S1

VCC

CORE

W1

W3

W5

W33

W35

W37

X2

D0#

A34#

AGTL I/O

D8#

D5#

AGTL I/O

S3

AGTL I/O

VCC

CORE

Power/Other

Reserved for future use

System Bus Clock

AGTL I/O

S5

VCC

Power/Other

AGTL I/O

PLL1

Reserved

BCLK

BR1#

Vss

CORE

S33

S35

S37

T2

VTT

RTTCTRL

VTT

VCC

CORE

X4

Power/Other

AGTL I/O

T4

D1#

D6#

Vss

X6

A32#

Vss

T6

AGTL I/O

X32

X34

X36

Y1

Power/Other

Reserved for future use

AGTL I/O

T32

T34

T36

U1

Power/Other

AGTL I/O

VTT

VCC

Vss

CORE

Vss

Reserved

A26#

Vss

D4#

Y3

U3

D15#

Vss

AGTL I/O

Y5

Power/Other

U5

Power/Other

AGTL I/O

Y33

Y35

Y37

Z2

BCLK#/CLKREF System Bus Clock

U33

U35

U37

V2

PLL2

VTT

VCC

Vss

Power/Other

AGTL I/O

CORE

VTT

Vss

Z4

A29#

A18#

V4

BERR#

VREF4

Z6

AGTL I/O

V6

Power/Other

Z32

Z34

Z36

VCC

Power/Other

Reserved for future use

CORE

V32

V34

VCC

Vss

CORE

Vss

Reserved

Datasheet

67

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

6.0

Boxed Processor Specifications

The Pentium III processor based on 0.13 micron process for the PGA370 socket may also be

offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who

build systems from motherboards and standard components. The boxed Pentium III processor

based on 0.13 micron process will be supplied with an unattached fan heatsink.

This section documents motherboard and system requirements for the fan heatsink that will be

supplied with the boxed Pentium III processor based on 0.13 micron process. This section is

particularly important for OEMs that manufacture motherboards for system integrators. Unless

otherwise noted, all figures in this section are dimensioned in inches. Figure 27 shows a

mechanical representation of the boxed Intel Pentium III processor based on 0.13 micron process in

the Flip Chip Pin Grid Array 2 (FC-PGA2) package.

Note: Drawings in this section reflect only the specifications on the Intel Boxed processor product. These

dimensions should not be used as a generic keep-out zone for all heatsinks. It is the system

designer’s responsibility to consider their proprietary solution when designing to the required keep-

out zone on their system platform and chassis. Refer to the Intel^®Pentium^®III processor Thermal/

Mechanical Functional Specification for further guidance. Contact your local Intel Sales

Representative for this document.

Figure 27. Conceptual Boxed Intel^®Pentium^®III Processor Based on 0.13 micron Process for

the PGA370 Socket

68

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

6.1

Mechanical Specifications

6.1.1

Mechanical Specifications for the FC-PGA2 Package

This section documents the mechanical specifications of the boxed Pentium III processor based on

0.13 micron process fan heatsink in the FC-PGA2 Package. The boxed processor in the FC-PGA2

Package ships with an un-attached fan heatsink. Figure 27 shows a mechanical representation of

the boxed Pentium III processor based on 0.13 micron process for the PGA370 socket in the Flip

Chip Pin Grid Array 2 (FC-PGA2) package.

The boxed processor fan heatsink is also asymmetrical in that the mechanical step feature,

Figure 30, must sit over the socket’s cam. The step allows the heatsink to securely interface with

the processor in order to meet the processor’s thermal requirements.

The dimensions for the boxed processor with the integrated fan heatsink are shown in Figure 29.

All dimensions are in inches.

The Pentium III processor based on 0.13 micron process uses a new technology termed FC-PGA2.

The FC-PGA2 package leverages the previous FC-PGA package technology used on Intel Pentium

III processors based on 0.18 micron technology (CPUID=068xh). The FC-PGA2 package adds an

Integrated Heat Spreader (IHS) to improve heat conduction from the processor die. This new

solution prevent the need for exotic thermal solutions in the higher power density processors. See

Section 5.0 of this document for the mechanical specifications of the PGA370 socket.

Section 5.2 of this document also shows the recommended mechanical keepout zones for the boxed

processor fan heatsink assembly. Figure 23 and Figure 24 show the REQUIRED keepout

dimensions for the boxed processor thermal solution. The cooling fin orientation on the heatsink

relative to the PGA370 socket is subject to change. Contact your local Intel Sales Representative

for documentation specific to the boxed fan heatsink orientation relative to the PGA370 socket.

Figure 28 shows the changes to the package mechanicals between the FC-PGA and FC-PGA2

designs. Note that the boxed fan heatsinks and associated clips are not compatible with earlier

boxed Intel Pentium III processors based on 0.18 micron technology (CPUID=068xh) fan

heatsinks.

Figure 28. Comparison between FC-PGA and FC-PGA2 package

(FC-PGA2)

(FC-PGA)

1.9 mm

3.5 mm

49.5 mm square

3.2 mm

Datasheet

69

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Figure 29. Side View of Space Requirements for the Boxed Processor

Table 38. Boxed Processor Fan Heatsink Spatial Dimensions

Dimensions (Inches)

Fan Heatsink Length

Min

Typ

Max

Units

3.14

1.81

2.6

Inches

Fan Heatsink Height

Fan Heatsink Width

Fan Heatsink height above motherboard

Air Keepout Zones from end of Fan Heatsink

0.29

0.20

0.30

0.33

Figure 30. Dimensions of Mechanical Step Feature in Heatsink Base

0.043

0.472

Units = inches

6.1.2

Boxed Processor Heatsink Weight

The boxed processor thermal cooling solution will not weigh more than 180 grams.

70

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

6.2

Thermal Specifications

This section describes the cooling requirements of the thermal cooling solution utilized by the

boxed processor.

6.2.1

Boxed Processor Cooling Requirements

The boxed processor is directly cooled with a fan heatsink. However, meeting the processor’s

temperature specification is also a function of the thermal design of the entire system and

ultimately the responsibility of the system integrator. The processor temperature specification is

found in Section 4.1 of this document. The boxed processor fan heatsink is able to keep the

processor temperature within the specifications (see Table 30 in Section 4.1) in chassis that provide

good thermal management.

For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to

the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of

the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan

heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and

decreases fan life. Figure 31 illustrate an acceptable airspace clearance for the fan heatsink. It is

also recommended that the air temperature entering the fan be kept below 45 °C. Again, meeting

the processor’s temperature specification is the responsibility of the system integrator. The

processor temperature specification is found in Section 4.1 of this document.

B

Figure 31. Thermal Airspace Requirement for all Boxed Intel^®Pentium^®III Processor Based

on 0.13 micron Process Fan Heatsinks in the PGA370 Socket

6.2.2

Boxed Processor Thermal Cooling Solution Clip

The boxed processor thermal solution requires installation by a system integrator to secure the

thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket.

Motherboards designed for use by system integrators should take care to consider the implications

of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket

attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach

tabs in a way that interferes with the installation of the boxed processor thermal cooling solution

Figure 23 and Figure 24 show the REQUIRED keepout dimensions for the boxed processor

thermal solution.

Datasheet

71

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

®

6.3

Electrical Requirements for the Boxed Intel Pentium III

Processor Based on 0.13 micron Process

6.3.1

Electrical Requirements

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is attached

to the fan and will draw power from a power header on the motherboard. The power cable

connector and pinout are shown in Figure 32. Motherboards must provide a matched power header

to support the boxed processor. Table 38 contains specifications for the input and output signals at

the fan heatsink connector. The fan heatsink outputs a SENSE signal (an open-collector output)

that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides V_OH

to match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the

SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to

GND.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the motherboard

documentation or on the motherboard. Figure 33 shows the recommended location of the fan

power connector relative to the PGA370 socket. The motherboard power header should be

positioned within 4.00 inches (lateral) of the fan power connector for the FC-PGA2 package.

Figure 32. Boxed Processor Fan Heatsink Power Cable Connector Description

1

Signal

GND

Straight square pin, 3-pin terminal housing with

polarizing ribs and friction locking ramp.

2

3

+12V

0.100" pin pitch, 0.025" square pin width.

SENSE

Waldom/Molex P/N 22-01-3037 or equivalent.

Match with straight pin, friction lock header on motherboard

Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3,

or equivalent.

1

2

3

Table 39. Fan Heatsink Power and Signal Specifications

Description

Min

Typ

Max

+12 V: 12 volt fan power supply

IC: Fan current draw

10.8 V

12 V

13.2 V

100 mA

SENSE: SENSE frequency (motherboard should pull this

pin up to appropriate VCC with resistor)

2 pulses per

fan revolution

72

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

®

Figure 33. Motherboard Power Header Placement Relative to the Boxed Intel^®Pentium III

Processor Based on 0.13 micron Process

0.10"

R = 4.00”

PGA370

Socket 7

0.10"

Datasheet

73

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

7.0

Processor Signal Description

This section provides an alphabetical listing of all the Pentium III processor based on 0.13 micron

process signals. The tables at the end of this section summarize the signals by direction: output,

input, and I/O.

7.1

Alphabetical Signals Reference

Table 40. Signal Description (Sheet 1 of 8)

Name

Type

Description

If the A20M# (Address-20 Mask) input signal is asserted, the processor masks

physical address bit 20 (A20#) before looking up a line in any internal cache and

before driving a read/write transaction on the bus. Asserting A20M# emulates the

8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#

is only supported in real mode.

A20M#

I

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O Write bus transaction.

The A[35:3]# (Address) signals define a 2³⁶-byte physical memory address space.

When ADS# is active, these pins transmit the address of a transaction; when ADS#

is inactive, these pins transmit transaction type information. These signals must

connect the appropriate pins of all agents on the processor system bus. The

A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#

signals are parity-protected by the AP0# parity signal.

A[35:3]#

I/O

On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#

®

pins to determine their power-on configuration. See the Intel Pentium II

Processor Developer’s Manual for details.

The ADS# (Address Strobe) signal is asserted to indicate the validity of the

transaction address on the A[35:3]# pins. All bus agents observe the ADS#

activation to begin parity checking, protocol checking, address decode, internal

snoop, or deferred reply ID match operations associated with the new transaction.

This signal must connect the appropriate pins on all processor system bus agents.

ADS#

I/O

The AERR# (Address Parity Error) signal is observed and driven by all processor

system bus agents, and if used, must connect the appropriate pins on all processor

system bus agents. AERR# observation is optionally enabled during power-on

configuration; if enabled, a valid assertion of AERR# aborts the current transaction.

AERR#

If AERR# observation is disabled during power-on configuration, a central agent

may handle an assertion of AERR# as appropriate to the error handling architecture

of the system.

The AP[1:0]# (Address Parity) signals are driven by the request initiator along with

ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers

A[23:3]#. A correct parity signal is high if an even number of covered signals are

low and low if an odd number of covered signals are low. This allows parity to be

high when all the covered signals are high. AP[1:0]# should connect the appropriate

pins of all processor system bus agents.

AP[1:0]#

I/O

The BCLK (Bus Clock) and BCLK# (for differential clock) signals determines the

bus frequency. All processor system bus agents must receive this signal to drive

their outputs and latch their inputs on the rising edge of BCLK. For differential

clocking, all processor system bus agents must receive this signal to drive their

outputs and latch their inputs on the BCLK and BCLK# crossing point.

BCLK/BCLK#

I

All external timing parameters are specified with respect to the BCLK signal.

74

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 2 of 8)

Name

Type

Description

The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error

without a bus protocol violation. It may be driven by all processor system bus

agents, and must connect the appropriate pins of all such agents, if used. However,

Pentium III processors based on 0.13 micron process do not observe assertions of

the BERR# signal.

BERR# assertion conditions are configurable at a system level. Assertion options

are defined by the following options:

BERR#

I/O

•

Enabled or disabled.

Asserted optionally for internal errors along with IERR#.

Asserted optionally by the request initiator of a bus transaction after it observes

an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

The BINIT# (Bus Initialization) signal may be observed and driven by all processor

system bus agents, and if used must connect the appropriate pins of all such

agents. If the BINIT# driver is enabled during power on configuration, BINIT# is

asserted to signal any bus condition that prevents reliable future information.

If BINIT# observation is enabled during power-on configuration, and BINIT# is

sampled asserted, all bus state machines are reset and any data which was in

transit is lost. All agents reset their rotating ID for bus arbitration to the state after

Reset, and internal count information is lost. The L1 and L2 caches are not

affected.

BINIT#

I/O

If BINIT# observation is disabled during power-on configuration, a central agent

may handle an assertion of BINIT# as appropriate to the error handling architecture

of the system.

The BNR# (Block Next Request) signal is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus stall, the current

bus owner cannot issue any new transactions.

Since multiple agents might need to request a bus stall at the same time, BNR# is a

wire-OR signal which must connect the appropriate pins of all processor system

bus agents. In order to avoid wire-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, BNR# is activated on specific clock edges and

sampled on specific clock edges.

BNR#

I/O

The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the

status of breakpoints.

BP[3:2]#

I/O

The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance

monitor signals. They are outputs from the processor which indicate the status of

breakpoints and programmable counters used for monitoring processor

performance.

BPM[1:0]#

The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the

processor system bus. It must connect the appropriate pins of all processor system

bus agents. Observing BPRI# active (as asserted by the priority agent) causes all

other agents to stop issuing new requests, unless such requests are part of an

ongoing locked operation. The priority agent keeps BPRI# asserted until all of its

requests are completed, then releases the bus by deasserting BPRI#.

BPRI#

BR0#

I

The BR0# (Bus Request) pins drive the BREQ[0]# signal in the system. During

power-up configuration, the central agent asserts the BR0# bus signal in the

system to assign the symmetric agent ID to the processor. The processor samples

its BR0# pin on the active-to-inactive transition of the RESET# to obtain its

symmetric agent ID. The processor asserts the BR0# pin to request the system

bus. BR0# must be connected to a 10–56 Ω resistor to VSS. Refer to the platform

design guide for implementation detail and resistor tolerance.

I/O

Datasheet

75

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 3 of 8)

Name

Type

Description

The BSEL signals are CMOS signals which are used to select the system bus

frequency. A BSEL[1:0] = ‘11’ selects a 133 MHz system bus frequency. The

frequency is determined by the processor(s), chipset, and frequency synthesizer

capabilities. All system bus agents must operate at the same frequency. The

Pentium III processor based on 0.13 micron process operates at 133 MHz system

bus frequency.

BSEL[1:0]

O

These signals must be pulled up to 3.3 V power rail with 330–1 kΩ resistors and

provided as a frequency selection signal to the clock driver/synthesizer and chipset.

Refer to the platform design guide for implementation detail and resistor tolerance.

In Single-ended clock mode the CLKREF input is a filtered 1.25 V supply voltage for

the processor PLL. A voltage divider and decoupling solution is provided by the

motherboard. See the design guide for implementation details.

CLKREF

I

When the processor operates in differential clock mode, this signal becomes

BCLK#.

The CPUPRES# signal is defined to allow a system design to detect the presence

of a processor in a PGA370 socket. Combined with the VID combination of

VID[25mV,3:0]= 11111 (see Section 2.6), a system can determine whether a

processor core is present. See the table below for states and values for determining

the presence of a processor core.

PGA370 Socket Occupation Truth Table

CPUPRES#

O

Signal

Value

Status

0

CPUPRES#

VID[25mV,3:0]

Processor core installed in the PGA370

socket.

Anything other

than ‘11111’

CPUPRES#

VID[25mV,3:0] Any value

1

PGA370 socket not occupied.

The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit

data path between the processor system bus agents, and must connect the

appropriate pins on all such agents. The data driver asserts DRDY# to indicate a

valid data transfer.

D[63:0]#

DBSY#

I/O

I

The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving

data on the processor system bus to indicate that the data bus is in use. The data

bus is released after DBSY# is deasserted. This signal must connect the

appropriate pins on all processor system bus agents.

The DEFER# signal is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility

of the addressed memory or I/O agent. This signal must connect the appropriate

pins of all processor system bus agents.

DEFER#

The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection

for the data bus. They are driven by the agent responsible for driving D[63:0]#, and

must connect the appropriate pins of all processor system bus agents that use

them. The DEP[7:0]# signals are enabled or disabled for ECC protection during

power on configuration.

DEP[7:0]#

I/O

A tri-state (high-impedance) output. Can be used for platforms that need to

differentiate Pentium III processors based on 0.13 micron process that support

VTT =1.25 V only, from Pentium III processors (AF36=VSS) that support

VTT =1.50 V only. The output on this signal is stable when VTT is stable. Refer to the

appropriate platform design guide for implementation details.

DETECT

DRDY#

O

The DRDY# (Data Ready) signal is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#

may be deasserted to insert idle clocks. This signal must connect the appropriate

pins of all processor system bus agents.

I/O

76

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 4 of 8)

Name

Type

Description

The DYN_OE allows the BSEL and VID signals to be driven out from the processor.

When this signal is low (a condition that will occur if the Pentium III processor based

on 0.13 micron process is installed in a non-supported platform), the VID and BSEL

signals will be tri-stated and the platform pull-up resistors will set the VID and BSEL

to all 1s which is a safe setting. This signal must be connected to a 1 kΩ resistor to

VTT. Refer to the platform design guide for implementation detail and resistor

tolerance.

DYN_OE

I

The FERR# (Floating-point Error) signal is asserted when the processor detects an

unmasked floating-point error. FERR# is similar to the ERROR# signal on the

Intel 387 coprocessor, and is included for compatibility with systems using

MS-DOS*-type floating-point error reporting.

FERR#

O

When the FLUSH# input signal is asserted, processors write back all data in the

Modified state from their internal caches and invalidate all internal cache lines. At

the completion of this operation, the processor issues a Flush Acknowledge

transaction. The processor does not cache any new data while the FLUSH# signal

remains asserted.

FLUSH# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O Write bus transaction.

FLUSH#

I

On the active-to-inactive transition of RESET#, each processor samples FLUSH#

to determine its power-on configuration. See the P6 Family of Processors

Hardware Developer’s Manual for details.

This signal must be connected to a 150 Ω resistor to VCC

. Refer to the

CMOS1.5

platform design guide for implementation detail and resistor tolerance.

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop

operation results, and must connect the appropriate pins of all processor system

bus agents. Any such agent may assert both HIT# and HITM# together to indicate

that it requires a snoop stall, which can be continued by reasserting HIT# and

HITM# together.

HIT#

I/O

HITM#

The IERR# (Internal Error) signal is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN

transaction on the processor system bus. This transaction may optionally be

converted to an external error signal (e.g., NMI) by system core logic. The

processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or

INIT#.

IERR#

O

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to

ignore a numeric error and continue to execute noncontrol floating-point

instructions. If IGNNE# is deasserted, the processor generates an exception on a

noncontrol floating-point instruction if a previous floating-point instruction caused an

error. IGNNE# has no effect when the NE bit in control register 0 is set.

IGNNE#

I

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O Write bus transaction.

The INIT# (Initialization) signal, when asserted, resets integer registers inside all

processors without affecting their internal (L1 or L2) caches or floating-point

registers. Each processor then begins execution at the power-on Reset vector

configured during power-on configuration. The processor continues to handle

snoop requests during INIT# assertion. INIT# is an asynchronous signal and must

connect the appropriate pins of all processor system bus agents.

INIT#

KEY

I

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST).

Can be used to prevent legacy processors from booting in incompatible platforms.

Legacy processors use this pin as a RESET and should be tied to ground for a

Pentium III processor based on 0.13 micron process only platform but for flexible

platform implementations this pin should be a No Connect. Refer to the appropriate

platform design guide for implementation details.

Datasheet

77

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 5 of 8)

Name

Type

Description

The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of

all APIC Bus agents, including all processors and the core logic or I/O APIC

component. When the APIC is disabled, the LINT0 signal becomes INTR, a

maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those names

on the Intel Pentium processor. Both signals are asynchronous.

LINT[1:0]

I

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC

is enabled by default after Reset, operation of these pins as LINT[1:0] is the default

configuration.

The LOCK# signal indicates to the system that a transaction must occur atomically.

This signal must connect the appropriate pins of all processor system bus agents.

For a locked sequence of transactions, LOCK# is asserted from the beginning of

the first transaction end of the last transaction.

LOCK#

I/O

When the priority agent asserts BPRI# to arbitrate for ownership of the processor

system bus, it will wait until it observes LOCK# deasserted. This enables symmetric

agents to retain ownership of the processor system bus throughout the bus locked

operation and ensure the atomicity of lock.

The NCHCTRL input signal provides AGTL pull-down strength control. The Pentium

III processor based on 0.13 micron process samples this input to determine the N-

channel device strength for pull-down when it is the driving agent. This signal must

be connected to a 14 Ω resistor to VTT. Refer to the platform design guide for

implementation detail and resistor tolerance.

NCHCTRL

I

The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or

I/O APIC which is required for operation of all processors, core logic, and I/O APIC

components on the APIC bus.

PICCLK

I

The PICD[1:0] (APIC Data) signals are used for bidirectional serial message

passing on the APIC bus, and must connect the appropriate pins of all processors

and core logic or I/O APIC components on the APIC bus.

PICD[1:0]

I/O

All Pentium III processors based on 0.13 micron process have an internal analog

PLL clock generator that requires a quiet power supply. PLL1 and PLL2 are inputs

PLL1, PLL2

I

to this PLL and must be connected to VCC

through a low pass filter that

CORE

minimizes jitter. See the platform design guide for implementation details.

The PRDY (Probe Ready) signal is a processor output used by debug tools to

determine processor debug readiness.

PRDY#

PREQ#

O

I

The PREQ# (Probe Request) signal is used by debug tools to request debug

operation of the processors.

The PWRGOOD (Power Good) signal is processor input. The processor requires

this signal to be a clean indication that the clocks and power supplies

(VCC

, etc.) are stable and within their specifications. Clean implies that the

CORE

signal will remain low (capable of sinking leakage current), without glitches, from

the time that the power supplies are turned on until they come within specification.

The signal must then transition monotonically to a high state. PWRGOOD can be

driven inactive at any time, but clocks and power must again be stable before a

subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width

specification in Table 18, and be followed by a 1 ms RESET# pulse.

PWRGOOD

I

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

The REQ[4:0]# (Request Command) signals must connect the appropriate pins of

all processor system bus agents. They are asserted by the current bus owner over

two clock cycles to define the currently active transaction type.

REQ[4:0]#

I/O

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Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 6 of 8)

Name

Type

Description

Asserting the RESET# signal resets all processors to known states and invalidates

their L1 and L2 caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least one millisecond after VCC

and

CORE

CLK have reached their proper specifications. On observing active RESET#, all

processor system bus agents will deassert their outputs within two clocks.

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the

P6 Family of Processors Hardware Developer’s Manual for details.

RESET#

I

The processor may have its outputs tristated via power-on configuration. Otherwise,

if INIT# is sampled active during the active-to-inactive transition of RESET#, the

processor will execute its Built-in Self-Test (BIST). Whether or not BIST is

executed, the processor will begin program execution at the power on Reset vector

(default 0_FFFF_FFF0h). RESET# must connect the appropriate pins of all

processor system bus agents.

RESET# is the only AGTL signal which does not have on-die termination.

Therefore, it is necessary to place a discrete 56 Ω resistor to VTT. Refer to the

platform design guide for implementation detail and resistor tolerance.

RESET2# pin is provided to differentiate the Pentium III processor based on 0.13

micron process from legacy Pentium III processors. The Pentium III processor

based on 0.13 micron process does not use the RESET2# pin. Refer to the platform

design guide for the proper connections of this signal.

RESET2#

I

The RP# (Request Parity) signal is driven by the request initiator, and provides

parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of

all processor system bus agents.

RP#

I/O

A correct parity signal is high if an even number of covered signals are low and low

if an odd number of covered signals are low. This definition allows parity to be high

when all covered signals are high.

The RS[2:0]# (Response Status) signals are driven by the response agent (the

agent responsible for completion of the current transaction), and must connect the

appropriate pins of all processor system bus agents.

RS[2:0]#

The RSP# (Response Parity) signal is driven by the response agent (the agent

responsible for completion of the current transaction) during assertion of RS[2:0]#,

the signals for which RSP# provides parity protection. It must connect the

appropriate pins of all processor system bus agents.

RSP#

I

A correct parity signal is high if an even number of covered signals are low and low

if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also

high, since this indicates it is not being driven by any agent guaranteeing correct

parity.

The RTTCTRL input signal provides AGTL termination control. The Pentium III

processor based on 0.13 micron process samples this input to set the termination

resistance value for the on-die AGTL termination. This signal must be connected to

a 56 Ω resistor to Vss on a uni-processor platform or a 68 Ω resistor to Vss on a

dual-processor platform. Refer to the platform design guide for implementation

detail and resistor tolerance.

RTTCTRL

I

The SLEWCTRL input signal provides AGTL slew rate control. The Pentium III

processor based on 0.13 micron process samples this input to determine the slew

rate for AGTL signals when it is the driving agent. This signal must be connected to

a 110 Ω resistor to Vss. Refer to the platform design guide for implementation detail

and resistor tolerance.

SLEWCTRL

The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to

enter the Sleep state. During Sleep state, the processor stops providing internal

clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state will not recognize snoops or interrupts. The processor will

recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in

Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to

Stop-Grant state, restarting its internal clock signals to the bus and APIC processor

core units.

SLP#

I

Datasheet

79

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 7 of 8)

Name

Type

Description

The SMI# (System Management Interrupt) signal is asserted asynchronously by

system logic. On accepting a System Management Interrupt, processors save the

current state and enter System Management Mode (SMM). An SMI Acknowledge

transaction is issued, and the processor begins program execution from the SMM

handler.

SMI#

I

The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a

low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the bus and APIC units. The processor continues to snoop bus transactions

and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the

processor restarts its internal clock to all units, services pending interrupts while in

the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no

effect on the bus clock; STPCLK# is an asynchronous input.

STPCLK#

I

The TCK (Test Clock) signal provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TCK

I

The TDI (Test Data In) signal transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

TDI

The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TDO

O

I

Thermal Diode Cathode. Used to calculate core (junction) temperature.

See Section 4.1.

THERMDN

THERMDP

Thermal Diode Anode. Used to calculate core (junction) temperature.

See Section 4.1.

The processor protects itself from catastrophic overheating by use of an internal

thermal sensor. This sensor is set well above the normal operating temperature to

ensure that there are no false trips. The processor will stop all execution when the

junction temperature exceeds approximately 135 °C. This is signaled to the system

by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains

latched, and the processor stopped, until RESET# goes active or core power is

removed. There is no hysteresis built into the thermal sensor itself; as long as the

die temperature drops below the trip level, a RESET# pulse will reset the processor

and execution will continue. If the temperature has not dropped below the trip level,

the processor will continue to drive THERMTRIP# and remain stopped.

THERMTRIP#

O

In the event the processor drives the THERMTRIP# signal active during valid

operation, both the VCC and VTT supplies to the processor must be turned off to

prevent thermal runaway of the processor. Valid operation refers to the operating

conditions where the THERMTRIP# signal is guaranteed valid. The time required

from THERMTRIP# asserted to VCC rail at 1/2 nominal is 5 seconds and

THERMTRIP# asserted to VTT rail at 1/2 nominal is 5 seconds. Once VCC and VTT

supplies are turned off, the THERMTRIP# signal will be deactivated. System logic

should ensure no “unsafe” power cycling occurs due to this deassertion.

The TMS (Test Mode Select) signal is a JTAG specification support signal used by

debug tools.

TMS

I

The TRDY# (Target Ready) signal is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of all processor system bus agents.

TRDY#

TRST#

I/O

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

I

The V

3 of V

input pin supplies non-AGTL reference voltage, which is typically 2/

CMOS_REF

V

. V

is used by the non-AGTL receivers to determine if a signal

CMOS_REF

CMOS

CMOS_REF

is a logical 0 or a logical 1.

80

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 40. Signal Description (Sheet 8 of 8)

Name

Type

Description

The VID[3:0, 25 mV] (Voltage ID) pins can be used to support automatic selection

of power supply voltages. These pins are CMOS signals that must be pulled up to

3.3 V power rail with 1 kΩ resistors. The VID pins are needed to cleanly support

voltage specification variations on processors. See Table 3 for definitions of these

pins. The power supply must supply the voltage that is requested by these pins, or

disable itself.

VID [3:0,25mV]

O

The VREF input pins supply the AGTL reference voltage, which is typically 2/3 of

VTT. VREF is used by the AGTL receivers to determine if a signal is a logical 0 or a

logical 1.

VREF

I

The VTT_PWRGD signal informs the system that the VID/BSEL signals are in their

correct logic state. During Power-up, the VID signals will be in a indeterminate state

for a small period of time. The voltage regulator or the VRM should not sample and/

or latch the VID signals until the VTT_PWRGD signal is asserted. The assertion of

the VTT_PWRGD signal indicates the VID signals are stable and are driven to the

final state by the processor. Refer to Figure 6 for power-up timing sequence for the

VTT_PWRGD and the VID signals.

VTT_PWRGD

7.2

Signal Summaries

Table 41 through Table 44 list attributes of the processor output, input, and I/O signals.

Table 41. Output Signals

Name

Active Level

Clock

Signal Group

BSEL[1:0]

CPUPRES#

DETECT

High

Low

High

Low

High

Low

N/A

Asynch

BCLK

Power/Other

CMOS Output

AGTL Output

TAP Output

FERR#

IERR#

PRDY#

TDO

TCK

THERMTRIP#

VID[3:0, 25mV]

Asynch

CMOS Output

Power/Other

Table 42. Input Signals (Sheet 1 of 2)

Name

Active Level

Clock

Signal Group

Qualified

A20M#

BCLK

Low

High

Low

High

Asynch

—

CMOS Input

System Bus Clock

AGTL Input

Always¹

Always

BPRI#

DEFER#

FLUSH#

IGNNE#

INIT#

BCLK

Asynch

Always

AGTL Input

Always

CMOS Input

Always¹

INTR

APIC disabled mode

Datasheet

81

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 42. Input Signals (Sheet 2 of 2)

Name

Active Level

Clock

Signal Group

Qualified

KEY

LINT[1:0]

NMI

N/A

High

N/A

Asynch

—

Power/Other

CMOS Input

Power/Other

APIC Clock

CMOS Input

AGTL Input

Power/Other

CMOS Input

TAP Input

APIC enabled mode

APIC disabled mode

NCHCTRL

PICCLK

PREQ#

PWRGOOD

RESET#

RESET2#

RSP#

High

Low

High

Low

N/A

Always

Asynch

BCLK

Asynch

—

Always

RTTCTRL

SLEWCTRL

SLP#

N/A

Low

High

Low

High

During Stop-Grant state

SMI#

STPCLK#

TCK

TDI

TCK

TAP Input

TMS

TCK

TAP Input

TRST#

Asynch

TAP Input

VTT_PWRGD

Power/Other

NOTE: Synchronous assertion with active TDRY# ensures synchronization.

82

Datasheet

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

Table 43. Input/Output Signals (Single Driver)

Name

Active Level

Clock

Signal Group

Qualified

A[35:3]#

ADS#

Low

BCLK

AGTL I/O

AGTL Input

ADS#, ADS#+1

Always

AP[1:0]#

BP[3:2]#

BPM[1:0]#

BR0#

ADS#, ADS#+1

Always

D[63:0]#

DBSY#

DEP[7:0]#

DRDY#

LOCK#

REQ[4:0]#

RP#

DRDY#

Always

DRDY#

Always

ADS#, ADS#+1

Always

RS[2:0]#

TRDY#

Table 44. Input/Output Signals (Multiple Driver)

Name

Active Level

Clock

Signal Group

Qualified

AERR#

BERR#

BINIT#

BNR#

Low

High

BCLK

PICCLK

AGTL I/O

APIC I/O

ADS#+3

Always

HIT#

HITM#

PICD[1:0]

Datasheet

83

Intel^®Pentium^®Processor Based on 0.13 Micron Process up to 1.33 GHz

84

Datasheet


型号：	BX80526C1000256/SL4MF
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 1000MHz, CMOS, PPGA370
文件：	总84页 (文件大小：1513K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BX80526C1000256/SL4MF [INTEL]

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