BX80569QX9650A/SLAN3 [INTEL]
RISC Microprocessor, 64-Bit, 3000MHz, CMOS, PBGA775;型号: | BX80569QX9650A/SLAN3 |
厂家: | INTEL |
描述: | RISC Microprocessor, 64-Bit, 3000MHz, CMOS, PBGA775 |
文件: | 总104页 (文件大小:2811K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
Intel Core™2 Extreme Processor
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®
QX9000 Series, Intel Core™2 Quad
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Δ
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Processor Q9000 , Q9000S , Q8000 ,
and Q8000S Series
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Datasheet
— on 45 nm process in the 775 land package
August 2009
Document Number: 318726-010
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH
MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights
that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any
license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property
rights.
®
®
The Intel Core™2 Extreme processor QX9000 series and Intel Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S
series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
®
Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled
for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including
details on which processors support Intel 64, or consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
±
®
®
Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires
a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,
an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing
Group and specific software for some uses. For more information, see http://www.intel.com/technology/security/
®
‡ Not all specified units of this processor support Enhanced Intel SpeedStep Technology. See the Processor Spec Finder at http:/
/processorfinder.intel.com or contact your Intel representative for more information.
Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep®
Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more
information.
Intel, Pentium, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007–2009, Intel Corporation. All Rights Reserved.
2
Datasheet
Contents
1
Introduction............................................................................................................ 11
1.1
Terminology ..................................................................................................... 12
1.1.1 Processor Terminology Definitions ............................................................ 12
References ....................................................................................................... 14
1.2
2
Electrical Specifications........................................................................................... 15
2.1
2.2
Power and Ground Lands.................................................................................... 15
Decoupling Guidelines........................................................................................ 15
2.2.1 VCC Decoupling ..................................................................................... 15
2.2.2 Vtt Decoupling....................................................................................... 15
2.2.3 FSB Decoupling...................................................................................... 16
Voltage Identification......................................................................................... 16
Reserved, Unused, and TESTHI Signals ................................................................ 18
Power Segment Identifier (PSID)......................................................................... 18
Voltage and Current Specification........................................................................ 19
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 19
2.6.2 DC Voltage and Current Specification........................................................ 20
2.6.3 VCC Overshoot ...................................................................................... 25
2.6.4 Die Voltage Validation............................................................................. 25
Signaling Specifications...................................................................................... 26
2.7.1 FSB Signal Groups.................................................................................. 26
2.7.2 CMOS and Open Drain Signals ................................................................. 28
2.7.3 Processor DC Specifications ..................................................................... 28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications..... 29
2.7.3.2 GTL+ Front Side Bus Specifications ............................................. 30
Clock Specifications........................................................................................... 31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................ 31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 32
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 32
2.8.4 BCLK[1:0] Specifications......................................................................... 32
2.3
2.4
2.5
2.6
2.7
2.8
3
Package Mechanical Specifications .......................................................................... 35
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Package Mechanical Drawing............................................................................... 35
Processor Component Keep-Out Zones................................................................. 39
Package Loading Specifications ........................................................................... 39
Package Handling Guidelines............................................................................... 39
Package Insertion Specifications.......................................................................... 40
Processor Mass Specification............................................................................... 40
Processor Materials............................................................................................ 40
Processor Markings............................................................................................ 40
4
5
Land Listing and Signal Descriptions ....................................................................... 43
4.1
4.2
Processor Land Assignments............................................................................... 43
Alphabetical Signals Reference............................................................................ 64
Thermal Specifications and Design Considerations .................................................. 75
5.1
Processor Thermal Specifications......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 82
Processor Thermal Features................................................................................ 82
5.2.1 Thermal Monitor..................................................................................... 82
5.2.2 Thermal Monitor 2.................................................................................. 83
5.2
Datasheet
3
5.2.3 On-Demand Mode...................................................................................84
5.2.4 PROCHOT# Signal ..................................................................................85
5.2.5 THERMTRIP# Signal................................................................................85
Platform Environment Control Interface (PECI) ......................................................86
5.3.1 Introduction...........................................................................................86
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems ..................86
5.3.2 PECI Specifications .................................................................................87
5.3.2.1 PECI Device Address..................................................................87
5.3.2.2 PECI Command Support.............................................................87
5.3.2.3 PECI Fault Handling Requirements...............................................87
5.3.2.4 PECI GetTemp0() Error Code Support ..........................................87
5.3
6
Features ..................................................................................................................89
6.1
6.2
Power-On Configuration Options ..........................................................................89
Clock Control and Low Power States.....................................................................89
6.2.1 Normal State .........................................................................................90
6.2.2 HALT and Extended HALT Powerdown States ..............................................90
6.2.2.1 HALT Powerdown State ..............................................................90
6.2.2.2 Extended HALT Powerdown State ................................................91
6.2.3 Stop Grant and Extended Stop Grant States...............................................91
6.2.3.1 Stop-Grant State.......................................................................91
6.2.3.2 Extended Stop Grant State.........................................................92
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended
Stop Grant Snoop State, and Stop Grant Snoop State..................................92
6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................92
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State.......92
6.2.5 Sleep State............................................................................................92
6.2.6 Deep Sleep State....................................................................................93
6.2.7 Deeper Sleep State.................................................................................93
6.2.8 Enhanced Intel SpeedStep® Technology ....................................................94
Processor Power Status Indicator (PSI) Signal .......................................................94
6.3
7
Boxed Processor Specifications................................................................................95
7.1
7.2
Introduction......................................................................................................95
Mechanical Specifications....................................................................................96
7.2.1 Boxed Processor Cooling Solution Dimensions.............................................96
7.2.2 Boxed Processor Fan Heatsink Weight .......................................................97
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....97
Electrical Requirements ......................................................................................97
7.3.1 Fan Heatsink Power Supply ......................................................................97
Thermal Specifications........................................................................................99
7.4.1 Boxed Processor Cooling Requirements......................................................99
7.4.2 Variable Speed Fan...............................................................................100
Boxed Intel® Core™2 Extreme Processor QX9650 Specifications ............................101
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight........102
7.3
7.4
7.5
8
Debug Tools Specifications ....................................................................................105
8.1
Logic Analyzer Interface (LAI) ...........................................................................105
8.1.1 Mechanical Considerations .....................................................................105
8.1.2 Electrical Considerations........................................................................105
4
Datasheet
Figures
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4-1
4-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
VCC Static and Transient Tolerance......................................................................... 24
VCC Overshoot Example Waveform......................................................................... 25
Differential Clock Waveform .................................................................................. 34
Measurement Points for Differential Clock Waveforms............................................... 34
Processor Package Assembly Sketch....................................................................... 35
Processor Package Drawing (Sheet 1 of 3) .............................................................. 36
Processor Package Drawing (Sheet 2 of 3) .............................................................. 37
Processor Package Drawing (Sheet 3 of 3) .............................................................. 38
Processor Top-Side Markings Example (Intel® Core™2 Extreme Processor QX9650)...... 40
Processor Top-Side Markings Example (Intel® Core™2 Quad Processor Q9000 Series) .. 41
Processor Land Coordinates and Quadrants, Top View............................................... 42
land-out Diagram (Top View – Left Side)................................................................. 44
land-out Diagram (Top View – Right Side)............................................................... 45
Intel® Core™2 Extreme Processor QX9770 Thermal Profile........................................ 78
Intel® Core™2 Extreme Processor QX9650 Thermal Profile........................................ 79
Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile .................... 80
Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile................. 81
Case Temperature (TC) Measurement Location ........................................................ 82
Thermal Monitor 2 Frequency and Voltage Ordering.................................................. 84
Conceptual Fan Control Diagram on PECI-Based Platforms ........................................ 86
Processor Low Power State Machine ....................................................................... 90
Mechanical Representation of the Boxed Processor ................................................... 95
Space Requirements for the Boxed Processor (side view) .......................................... 96
Space Requirements for the Boxed Processor (top view) ........................................... 96
Space Requirements for the Boxed Processor (overall view) ...................................... 97
Boxed Processor Fan Heatsink Power Cable Connector Description.............................. 98
Baseboard Power Header Placement Relative to Processor Socket............................... 98
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ............... 99
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) ............... 99
Boxed Processor Fan Heatsink Set Points .............................................................. 100
Space Requirements for the Boxed Processor (side view) ........................................ 102
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ............. 102
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) ............. 103
Datasheet
5
Tables
1-1
References..........................................................................................................14
Voltage Identification Definition..............................................................................17
Absolute Maximum and Minimum Ratings................................................................19
Voltage and Current Specifications .........................................................................20
VCC Static and Transient Tolerance .........................................................................23
VCC Overshoot Specifications .................................................................................25
FSB Signal Groups................................................................................................26
Signal Characteristics ...........................................................................................27
Signal Reference Voltages .....................................................................................27
GTL+ Signal Group DC Specifications......................................................................28
Open Drain and TAP Output Signal Group DC Specifications .......................................28
CMOS Signal Group DC Specifications .....................................................................29
PECI DC Electrical Limits .......................................................................................30
GTL+ Bus Resistance Definitions ............................................................................30
Core Frequency to FSB Multiplier Configuration ........................................................31
BSEL[2:0] Frequency Table for BCLK[1:0]...............................................................32
Front Side Bus Differential BCLK Specifications.........................................................32
FSB Differential Clock Specifications (1600 MHz FSB)................................................33
FSB Differential Clock Specifications (1333 MHz FSB)................................................33
Processor Loading Specifications ............................................................................39
Package Handling Guidelines..................................................................................39
Processor Materials...............................................................................................40
Alphabetical Land Assignments ..............................................................................46
Numerical Land Assignment...................................................................................55
Signal Description ................................................................................................64
Processor Thermal Specifications............................................................................76
Intel® Core™2 Extreme Processor QX9770 Thermal Profile ........................................78
Intel® Core™2 Extreme Processor QX9650 Thermal Profile ........................................79
Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile.....................80
Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile.................81
GetTemp0() Error Codes .......................................................................................87
Power-On Configuration Option Signals ...................................................................89
Fan Heatsink Power and Signal Specifications...........................................................98
Fan Heatsink Power and Signal Specifications.........................................................100
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
3-1
3-2
3-3
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
6-1
7-1
7-2
6
Datasheet
Revision History
Revision
Number
Description
Revision Date
-001
-002
• Initial release
November 2007
January 2008
• Added Intel® Core™2 Quad processors Q9550, Q9450, and Q9300
• Added 1600 MHz FSB
• Added Intel® Core™2 Extreme processor QX9770
-003
March 2008
• Added Intel® Core™2 Quad processors Q9650 and Q9400
• Added PSI# signal
-004
August 2008
• Updated Sections 6.2.3, 6.2.4, 6.2.5, 6.2.6, 6.2.7, and 6.3
• Updated FSB termination voltage in Table 2-3
-005
-006
• Added Intel® Core™2 Quad processor Q8200
• Added Intel® Core™2 Quad processor Q8300
August 2008
December 2008
• Added Intel® Core™2 Quad processor Q9000S and Q8000S series – Q9550S,
Q9400S, and Q8200S.
• Added Intel® Core™2 Quad processors Q8400 and Q8400S
• Corrected list of Intel® VT supported processors: Intel® Core™2 Quad
processors Q8400 and Q8400S
• Added Intel® Core™2 Quad processors Q9505 and Q9505S
-007
-008
-009
-010
January 2009
April 2009
May 2009
August 2009
§
Datasheet
7
8
Datasheet
Intel® Core™2 Extreme Processor QX9000 Series and
Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000,
Q8000S Series Features
• Available at 3.20 GHz and 3.00 GHz (Intel®
Core™2 Extreme processor QX9000 series)
• Available at 3.0 GHz, 2.83 GHz, 2.66 GHz,
and 2.50 GHz (Intel® Core™2 Quad
processor Q9650, Q9550, Q9505, Q9450,
Q9400, and Q9300)
• Available at 2,66 GHz, 2.50 GHz and
2.33 GHz (Intel® Core™2 Quad processor
Q8400, Q8300, and Q8200)
• Available at 2.83 GHz and 2.66 GHz (Intel®
Core™2 Quad processor Q9550S, Q9505S,
and Q9400S)
• Available at 2.66 GHz and 2.33 GHz (Intel®
Core™2 Quad processor Q8400S and
Q8200S)
• FSB frequency at 1333 MHz (Intel® Core™2
Extreme processor QX9650, Intel® Core™2
Quad Q9000, Q9000S, Q8000, and Q8000S
series only)
• Binary compatible with applications running
on previous members of the Intel
microprocessor line
• Supports Execute Disable Bit capability
• Intel® Wide Dynamic Execution
• Intel® Advanced Smart Cache
• Intel® Smart Memory Access
• Intel® Intelligent Power Capability
• Intel® Advanced Digital Media Boost
• Optimized for 32-bit applications running on
advanced 32-bit operating systems
• Two 6 MB Level 2 caches (Intel® Core™2
Extreme processor QX9000 series, Intel®
Core™2 Quad processor Q9650, Q9550,
Q9550S, and Q9450)
• Two 4 MB Level 2 caches (Intel® Core™2
Quad processor Q9505, Q9505S, Q8400,
and Q8400S)
• Two 3 MB Level 2 caches (Intel® Core™2
Quad processor Q9400, Q9400S, and
Q9300)
• Two 2 MB Level 2 caches (Intel® Core™2
Quad processor Q8200, Q8200S, and
Q8300)
• Intel® HD Boost utilizing new SSE4
instructions for improved multimedia
performance, especially for video encoding
and photo processing
• FSB frequency at 1600 MHz (Intel® Core™2
Extreme processor QX9770 only)
• Enhanced Intel SpeedStep® Technology
• Supports Intel® 64Φ architecture
• Supports Intel® Virtualization Technology
(Intel® Core™2 Extreme processor QX9650,
Intel® Core™2 Quad processor Q9000 and
Q9000S series, Intel® Core™2 Quad
processors Q8400 and Q8400S only)
• Supports Intel® Trusted Execution
Technology (Intel® Core™2 Quad processor
Q9000 and Q9000S series only)
• System Management mode
• 12-way cache associativity provides
improved cache hit rate on load/store
operations
• Low power processor (Intel® Core™2 Quad
processor Q9000S and Q8000S series only)
• 775-land Package
The Intel Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000,
Q9000S, Q8000, and Q8000S series deliver Intel's advanced, powerful processors for desktop PCs.
The processor is designed to deliver performance across applications and usages where end-users can
truly appreciate and experience the performance. These applications include Internet audio and
streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and
multitasking user environments.
Intel® 64Φ architecture enables the processor to execute operating systems and applications written
to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep®
technology, allows tradeoffs to be made between performance and power consumption.
The Intel Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000, Q9000S,
Q8000, and Q8000S series also includes the Execute Disable Bit capability. This feature, combined
with a supported operating system, allows memory to be marked as executable or non-executable.
Datasheet
9
The Intel Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and
Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization
Technology. Virtualization Technology provides silicon-based functionality that works together with
compatible Virtual Machine Monitor (VMM) software to improve on software-only solutions.
The Intel® Core™2 Quad processor Q9000 and Q9000S series support Intel® Trusted Execution
Technology (Intel® TXT). Intel® TXT is a key element in Intel's safer computing initiative that defines
a set of hardware enhancements that operate with an Intel TXT enabled operating system to help
protect against software-based attacks. It creates a hardware foundation that builds on Intel's
Virtualization Technology to help protect the confidentiality and integrity of data stored/created on the
client PC.
§ §
10
Datasheet
Introduction
1 Introduction
The Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad
processor Q9000, Q9000S, Q8000, and Q8000S series are based on the Enhanced
Intel® Core™ microarchitecture. The Enhanced Intel Core microarchitecture combines
the performance of previous generation Desktop products with the power efficiencies of
a low-power microarchitecture to enable smaller, quieter systems. The Intel® Core™2
Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000, Q9000S,
Q8000, and Q8000S series are 64-bit processors that maintains compatibility with IA-
32 software.
The processors use a Flip-Chip Land Grid Array (FC-LGA6) package technology, and
plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
Note:
Note:
In this document, the Intel® Core™2 Extreme processor QX9000 series and the Intel®
Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series may be referred
to simply as "the processor."
The following products are covered in this document:
• The Intel® Core™2 Extreme processor QX9000 series refers to the QX9770 and
QX9650.
• The Intel® Core™2 Quad processor Q9000 series refers to the Q9650, Q9550,
Q9505, Q9450, Q9400, and Q9300.
• The Intel® Core™2 Quad processor Q9000S series refers to the Q9550S, Q9505S,
and Q9400S.
• The Intel® Core™2 Quad processor Q8000 series refers to the Q8200, Q8300,
Q8400.
• The Intel® Core™2 Quad processor Q8000S series refers to the Q8200S and
Q8400S.
The processor is based on 45 nm process technology. The processor features the Intel®
Advanced Smart Cache, a shared multi-core optimized cache that significantly reduces
latency to frequently used data. The processors feature 1600 MHz and 1333 MHz front
side bus (FSB) frequencies.The processors also feature two independent but shared
12 MB of L2 cache (2x6M), two independent but shared 8 MB of L2 cache (2x4M), two
independent but shared 6 MB of L2 cache (2x3M) or two independent but shared 4 MB
of L2 caches (2x2M).
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2),
Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming SIMD Extension 3
(SSSE3), and the Streaming SIMD Extensions 4.1 (SSE4.1). The processor supports
several Advanced Technologies: Execute Disable Bit, Intel® 64 architecture (Intel® 64),
and Enhanced Intel SpeedStep® Technology. In addition, the Intel® Core™2 Extreme
processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series,
and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization
Technology (Intel® VT). Further, the Intel® Core™2 Quad processor Q9000 and
Q9000S series support Intel® Trusted Execution Technology (Intel® TXT).
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 12.4 GB/s.
Datasheet
11
Introduction
The processor uses some of the infrastructure already enabled by 775_VR_CONFIG_05
platforms including heatsink, heatsink retention mechanism, and socket.
Manufacturability is a high priority; hence, mechanical assembly may be completed
from the top of the baseboard and should not require any special tooling.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
1.1.1
Processor Terminology Definitions
Commonly used terms are explained here for clarification:
• Intel® Core™2 Extreme processor QX9000 series — Quad core Extreme
Edition processor in the FC-LGA6 package with two 6 MB L2 cache.
• Intel® Core™2 Quad processor Q9000 series — Quad core processor in the FC-
LGA8 package with two 6 MB L2 caches or two 3 MB L2 caches.
• Intel® Core™2 Quad processor Q8000 Series — Quad core processor in the
FC-LGA8 package with two 4 MB L2 caches or two 2 MB L2 caches..
• Intel® Core™2 Quad processor Q9000S series — Low power Quad core
processor in the FC-LGA8 package with two 6 MB L2 caches or two 3 MB L2 caches.
• Intel® Core™2 Quad Processor Q8000S Series — Low power Quad core
processor in the FC-LGA8 package with two 4 MB L2 caches or two 2 MB L2 caches
caches.
• Processor — For this document, the term processor is the generic form of the
Intel® Core™2 Extreme processor QX9000 series, the Intel® Core™2 Quad
processor Q9000, Q9000S, Q8000, and Q8000S series.
• Enhanced Intel® CoreTM microarchitecture — A new foundation for Intel®
architecture-based desktop, mobile and mainstream server multi-core processors.
For additional information refer to: http://www.intel.com/technology/architecture/
coremicro/
• Keep-out zone — The area on or near the processor that system design can not
utilize.
• Processor core — Processor die with integrated L2 cache.
• LGA775 socket — The processor mates with the system board through a surface
mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
12
Datasheet
Introduction
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.
• Execute Disable Bit — Allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code attempts
to run in non-executable memory the processor raises an error to the operating
system. This feature can prevent some classes of viruses or worms that exploit
buffer over run vulnerabilities and can thus help improve the overall security of the
system. See the Intel® Architecture Software Developer's Manual for more detailed
information.
• Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing
the processor to execute operating systems and applications written to take
advantage of Intel 64 architecture. Further details on Intel 64 architecture and
programming model can be found in the Software Developer Guide at http://
developer.intel.com/technology/64bitextensions/.
• Enhanced Intel SpeedStep® Technology — Enhanced Intel SpeedStep
Technology allows trade-offs to be made between performance and power
consumptions, based on processor utilization. This may lower average power
consumption (in conjunction with OS support).
• Intel® Virtualization Technology (Intel® VT) — A set of hardware
enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel VT will provide a foundation for widely-deployed virtualization
solutions and enables more robust hardware assisted virtualization solutions. More
information can be found at: http://www.intel.com/technology/virtualization/
• Intel® Trusted Execution Technology (Intel® TXT)— Intel® Trusted Execution
Technology (Intel® TXT) is a security technology by Intel and requires for operation
a computer system with Intel® Virtualization Technology, a Intel Trusted Execution
Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules,
and an Intel or other Intel Trusted Execution Technology compatible measured
virtual machine monitor. In addition, Intel Trusted Execution Technology requires
the system to contain a TPMv1.2 as defined by the Trusted Computing Group and
specific software for some uses.
• Platform Environment Control Interface (PECI) — A proprietary one-wire bus
interface that provides a communication channel between the processor and
chipset components to external monitoring devices.
Datasheet
13
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1-1.
References
Document
Location
Intel® Core™2 Extreme Processor QX9000 Series, Intel® Core™2 http://www.intel.com/
Quad Processor Q9000, Q9000S, Q8000, and Q8000S Series
Specification Update
design/processor/specupdt/
318727.htm
http://www.intel.com/
design/processor/designex/
315594.htm
Intel® Core™2 Extreme Processor and Intel® Core™2 Quad
Processor Thermal and Mechanical Design Guidelines
Intel® Core™2 Extreme Processor QX6800 and Intel® Core™2
Extreme Processor QX9770 Thermal and Mechanical Design
Guidelines
http://www.intel.com/
design/processor/designex/
316854.htm
http://www.intel.com/
design/processor/applnots/
313214.htm
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket
Balanced Technology Extended (BTX) System Design Guide
LGA775 Socket Mechanical Design Guide
www.formfactors.org
http://intel.com/design/
Pentium4/guides/
302666.htm
Intel® 64 and IA-32 Intel Architecture Software Developer's
Manuals
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
http://www.intel.com/
products/processor/
manuals/
§
14
Datasheet
Electrical Specifications
2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and
signals. DC electrical characteristics are provided.
2.1
Power and Ground Lands
The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to VCC, while all VSS lands must be
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands that meets the VTT
specifications outlined in Table 2-3.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 2-3. Failure to do so can result in timing violations or reduced lifetime of
the component.
2.2.1
2.2.2
V
Decoupling
CC
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket.
VTT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To ensure compliance with the specifications, various
factors associated with the power delivery solution must be considered including
regulator type, power plane and trace sizing, and component placement. A
conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors.
Datasheet
15
Electrical Specifications
2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see Chapter 2.6.3 for VCC overshoot
specifications). Refer to Table 2-11 for the DC specifications for these signals. Voltages
for each processor frequency is provided in Table 2-3.
Note:
To support the Deeper Sleep State the platform must use a VRD 11.1 compliant
solution. The Deeper Sleep State also requires additional platform support. For further
information on Voltage Regulator-Down solutions, contact your Intel field
representative.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 2-3. Refer to the Intel® Core™2
Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S,
Q8000, and Q8000S Series Specification Update for further details on specific valid core
frequency and VID values of the processor. Note that this differs from the VID
employed by the processor during a power management event (Thermal Monitor 2,
Enhanced Intel SpeedStep® technology, or Extended HALT State).
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages. Table 2-1 specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. The processor provides the ability to operate while transitioning to an adjacent
VID and its associated processor core voltage (VCC). This will represent a DC shift in
the load line. It should be noted that a low-to-high or high-to-low voltage state change
may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 2-3 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 2-4 and Figure 2-1as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in Table 2-3
and Table 2-4. Refer to the Voltage Regulator Design Guide for further details.
16
Datasheet
Electrical Specifications
Table 2-1.
Voltage Identification Definition
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
Voltage
Voltage
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFF
1.6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.0375
1.025
1.0125
1
1.5875
1.575
1.5625
1.55
0.9875
0.975
0.9625
0.95
1.5375
1.525
1.5125
1.5
0.9375
0.925
0.9125
0.9
1.4875
1.475
1.4625
1.45
0.8875
0.875
0.8625
0.85
1.4375
1.425
1.4125
1.4
0.8375
0.825
0.8125
0.8
1.3875
1.375
1.3625
1.35
0.7875
0.775
0.7625
0.75
1.3375
1.325
1.3125
1.3
0.7375
0.725
0.7125
0.7
1.2875
1.275
1.2625
1.25
0.6875
0.675
0.6625
0.65
1.2375
1.225
1.2125
1.2
0.6375
0.625
0.6125
0.6
1.1875
1.175
1.1625
1.15
0.5875
0.575
0.5625
0.55
1.1375
1.125
1.1125
1.1
0.5375
0.525
0.5125
0.5
1.0875
1.075
1.0625
1.05
OFF
Datasheet
17
Electrical Specifications
2.4
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
VTT, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 2-6 for details on GTL+ signals that do not include on-die
termination.
Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT). For details, see Table 2-13.
TAP and CMOS signals do not include on-die termination. Inputs and used outputs must
be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing.
All TESTHI[10:7:0] lands should be individually connected to VTT via a pull-up resistor
which matches the nominal trace impedance.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI10 – cannot be grouped with other TESTHI signals
Terminating multiple TESTHI pins together with a single pull-up resistor is not
recommended for designs supporting boundary scan for proper Boundary Scan testing
of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[10,7:0] lands should have a resistance value within ± 20% of the impedance
of the board transmission line traces. For example, if the nominal trace impedance is
50 Ω, then a value between 40 Ω and 60 Ω should be used.
2.5
Power Segment Identifier (PSID)
Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched
power requirement situations. The PSID mechanism enables BIOS to detect if the
processor in use requires more power than the platform voltage regulator (VR) is
capable of supplying. For example, a 130 W TDP processor installed in a board with a
65 W or 95 W TDP capable VR may draw too much power and cause a potential VR
issue.
18
Datasheet
Electrical Specifications
2.6
Voltage and Current Specification
2.6.1
Absolute Maximum and Minimum Ratings
Table 2-2 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 2-2.
Absolute Maximum and Minimum Ratings
Symbol
VCC
Parameter
Min
Max
Unit Notes1, 2
Core voltage with respect to
VSS
–0.3
1.45
V
V
-
FSB termination voltage with
respect to VSS
VTT
–0.3
See Section 5
–40
1.45
-
-
See
Section 5
TCASE
Processor case temperature
°C
°C
Processor storage
temperature
TSTORAGE
85
3, 4, 5
NOTES:
1.
2.
3.
For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to
the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits will not affect the long-term reliability of the device. For
functional operation, refer to the processor case temperature specifications.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long term reliability of the processor.
4.
5.
Datasheet
19
Electrical Specifications
2.6.2
DC Voltage and Current Specification
Table 2-3.
Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
1.3625
Unit Notes2, 10
VID Range
VID
0.8500
—
V
1
Processor Number
V
QX9770
3.20 GHz (12 MB Cache)
VCC for
Processor Number
775_VR_CONFIG_05B:
V
QX9650
3.00 GHz (12 MB Cache)
Processor Number
VCC for
775_VR_CONFIG_05A:
Q9650
Q9550
Q9550S
Q9505
Q9505S
Q9450
Q9400
Q9400S
Q9300
Q8400
Q8300
Q8200
Q8400S
Q8200S
3.0 GHz (12 MB Cache)
2.83 GHz (12 MB Cache)
2.83 GHz (12 MB Cache)
2.83 GHz (8 MB Cache)
2.83 GHz (8 MB Cache)
2.66 GHz (12 MB Cache)
2.66 GHz (6 MB Cache)
2.66 GHz (6 MB Cache)
2.50 GHz (6 MB Cache)
2.66 GHz (8 MB Cache)
2.50 GHz (4 MB Cache)
2.33 GHz (4 MB Cache)
2.66 GHz (8 MB Cache)
2.33 GHz (4 MB Cache)
Refer to Table 2-4 and
Figure 2-1
VCC Core
3, 4, 5
V
VCC_BOOT
VCCPLL
Default VCC voltage for initial power up
PLL VCC
—
1.10
1.50
—
V
- 5%
+ 5%
20
Datasheet
Electrical Specifications
Table 2-3.
Symbol
Voltage and Current Specifications
Parameter
Processor Number
Min
Typ
Max
Unit Notes2, 10
—
—
A
3.20 GHz (12 MB Cache)
Processor Number ICC for
775_VR_CONFIG_05B:
3.00 GHz (12 MB Cache)
Processor Number ICC for
775_VR_CONFIG_05A:
140
125
QX9770
—
—
A
QX9650
Q9650
Q9550
Q9550S
Q9505
Q9505S
Q9450
Q9400
Q9400S
Q9300
Q8400
Q8300
Q8200
Q8400S
Q8200S
3.0 GHz (12 MB Cache)
2.83 GHz (12 MB Cache)
2.83 GHz (12 MB Cache)
2.83 GHz (8 MB Cache)
2.83 GHz (8 MB Cache)
2.66 GHz (12 MB Cache)
2.66 GHz (6 MB Cache)
2.66 GHz (6 MB Cache)
2.50 GHz (6 MB Cache)
2.66 GHz (8 MB Cache)
2.50 GHz (4 MB Cache)
2.33 GHz (4 MB Cache)
2.66 GHz (8 MB Cache)
2.33 GHz (4 MB Cache)
100
100
100
100
100
100
100
100
100
100
100
100
100
100
ICC
6
—
—
A
on Intel® 3 series
Chipset family boards
on Intel® 4 series
Chipset family boards
FSB termination
voltage
1.045
1.14
1.1
1.2
1.155
1.26
VTT
V
8, 9
(DC + AC
specifications)
VTT_OUT_LEFT
and
DC Current that may be drawn from
—
—
580
mA
A
VTT_OUT_RIGHT VTT_OUT_LEFT and VTT_OUT_RIGHT per land
ICC
ICC for VTT supply before VCC stable
8.0
7.0
ITT
—
—
9
ICC for VTT supply after VCC stable
ICC_VCCPLL
ICC_GTLREF
I
CC for PLL land
—
—
—
—
260
200
mA
µA
ICC for GTLREF
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep® Technology, or Extended HALT State).
2.
3.
4.
Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See Section 2.3 and Table 2-1 for more
information.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
Datasheet
21
Electrical Specifications
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
5.
Refer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum VCC allowed for
a given current. The processor should not be subjected to any VCC and ICC combination
wherein VCC exceeds VCC_MAX for a given current.
6.
7.
I
V
CC_MAX specification is based on VCC_MAX loadline. Refer to Figure 2-1 for details.
TT must be provided via a separate voltage source and not be connected to VCC. This
specification is measured at the land.
8.
9.
Baseboard bandwidth is limited to 20 MHz.
This is the maximum total current drawn from the VTT plane by only the processor. This
specification does not include the current coming from on-board termination (RTT),
through the signal line. Refer to the Voltage Regulator Design Guide to determine the total
I
TT drawn by the system. This parameter is based on design characterization and is not
tested.
10.
Adherence to the voltage specifications for the processor are required to ensure reliable
processor operation.
22
Datasheet
Electrical Specifications
Table 2-4.
VCC Static and Transient Tolerance
Voltage Deviation from VID Setting (V)1, 2, 3, 4
ICC (A)
Maximum Voltage
Typical Voltage
Minimum Voltage
1.30 mΩ
1.38 mΩ
1.45 mΩ
0
5
0.000
-0.007
-0.013
-0.020
-0.026
-0.033
-0.039
-0.046
-0.052
-0.059
-0.065
-0.072
-0.078
-0.085
-0.091
-0.098
-0.101
-0.111
-0.117
-0.124
-0.130
-0.137
-0.143
-0.150
-0.156
-0.163
-0.019
-0.026
-0.033
-0.040
-0.047
-0.053
-0.060
-0.067
-0.074
-0.081
-0.088
-0.095
-0.102
-0.108
-0.115
-0.122
-0.126
-0.136
-0.143
-0.150
-0.157
-0.163
-0.170
-0.177
-0.184
-0.191
-0.038
-0.045
-0.053
-0.060
-0.067
-0.074
-0.082
-0.089
-0.096
-0.103
-0.111
-0.118
-0.125
-0.132
-0.140
-0.147
-0.151
-0.161
-0.169
-0.176
-0.183
-0.190
-0.198
-0.205
-0.212
-0.219
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
3.
This table is intended to aid in reading discrete points on Figure 2-1.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket
loadline guidelines and VR implementation details.
4.
Adherence to this loadline specification is required to ensure reliable processor operation.
Datasheet
23
Electrical Specifications
Figure 2-1. VCC Static and Transient Tolerance
Icc [A]
0
10
20
30
40
50
60
70
80
90
100
110
120
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
VID - 0.188
VID - 0.200
VID - 0.213
VID - 0.225
Vcc Maximum
Vcc Typical
Vcc Minimum
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
3.
This loadline specification shows the deviation from the VID set point.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket
loadline guidelines and VR implementation details.
24
Datasheet
Electrical Specifications
2.6.3
V
Overshoot
CC
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 2-5.
VCC Overshoot Specifications
Symbol
Parameter
Min
Max
Unit
Figure Notes
Magnitude of VCC overshoot above
VID
1
VOS_MAX
—
50
mV
2-2
Time duration of VCC overshoot above
VID
1
TOS_MAX
—
25
µs
2-2
NOTES:
1.
Adherence to these specifications is required to ensure reliable processor operation.
Figure 2-2. VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
NOTES:
1.
2.
V
OS is measured overshoot voltage.
TOS is measured time duration above VID.
2.6.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 2-5 when
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are
< 10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.
Datasheet
25
Electrical Specifications
2.7
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 2-13 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination; thus, eliminating the need to terminate
the bus on the motherboard for most GTL+ signals.
2.7.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[3:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 2-6 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 2-6.
FSB Signal Groups (Sheet 1 of 2)
Signal Group
Type
Signals1
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#3, DBSY#,
DRDY#, HIT#, HITM#, LOCK#
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#3
A[35:17]#3
ADSTB0#
ADSTB1#
GTL+ Source
Synchronous I/O
Synchronous to
assoc. strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
26
Datasheet
Electrical Specifications
Table 2-6.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
Type
Signals1
Synchronous to
BCLK[1:0]
GTL+ Strobes
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#3, STPCLK#, PWRGOOD, SLP#,
TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0],
PSI#
CMOS
Open Drain
Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M
Open Drain
Input/Output
PROCHOT#4
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]2
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[3:0], COMP[8,3:0], RESERVED, TESTHI[10,7:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Power/Other
NOTES:
1.
2.
Refer to Section 4.2 for signal descriptions.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
3.
4.
PROCHOT# signal type is open drain output and CMOS input.
.
Table 2-7.
Signal Characteristics
Signals with RTT
Signals with No RTT
A20M#, BCLK[1:0], BSEL[2:0],
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/
NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,
STPCLK#, TDO, TDO_M, TESTHI[10,7:0],
THERMTRIP#, VID[7:0], GTLREF[3:0], TCK,
TDI, TDI_M, TMS, TRST#, VTT_SEL
Open Drain Signals1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BPMb[3:0]#, BR0#, TDO, TDO_M, FCx
NOTES:
1.
Signals that do not have RTT, nor are actively driven to their high-voltage level.
Table 2-8.
Signal Reference Voltages
GTLREF
VTT/2
BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#,
HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,
REQ[4:0]#, RS[2:0]#, TRDY#
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#,
INIT#, PROCHOT#, PWRGOOD1, SMI#,
STPCLK#, TCK1, TDI1, TDI_M1, TMS1,
TRST#1
NOTE:
1.
See Table 2-10 for more information.
Datasheet
27
Electrical Specifications
2.7.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional
timing requirements for entering and leaving the low power states.
2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 2-9.
GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes1
VIL
VIH
VOH
Input Low Voltage
Input High Voltage
Output High Voltage
-0.10
GTLREF – 0.10
VTT + 0.10
VTT
V
V
V
2, 5
3, 4, 5
4, 5
GTLREF + 0.10
VTT – 0.10
VTT_MAX
[(RTT_MIN) + (2 * RON_MIN)]
/
IOL
ILI
ILO
RON
Output Low Current
N/A
N/A
A
-
Input Leakage
Current
± 100
µA
6
7
Output Leakage
Current
N/A
7.5
± 100
11
µA
Buffer On Resistance
Ω
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
IL is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
IH is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
IH and VOH may experience excursions above VTT.
The VTT referred to in these specifications is the instantaneous VTT.
Leakage to VSS with land held at VTT.
Leakage to VTT with land held at 300 mV.
V
3.
V
4.
5.
6.
7.
V
Table 2-10. Open Drain and TAP Output Signal Group DC Specifications
Symbol
Parameter
Output Low Voltage
Min
Max
Unit Notes1
VOL
IOL
ILO
0
0.20
50
V
-
Output Low Current
16
mA
µA
2
3
Output Leakage Current
N/A
± 200
NOTES:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Measured at VTT * 0.2V.
For Vin between 0 and VOH
.
28
Datasheet
Electrical Specifications
Table 2-11. CMOS Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
Max
Unit
Notes1
VIL
VIH
VOL
VOH
IOL
IOH
ILI
-0.10
VTT * 0.70
-0.10
VTT * 0.30
VTT + 0.10
VTT * 0.10
VTT + 0.10
VTT * 0.10 / 27
VTT * 0.10 / 27
± 100
V
V
3, 6
4, 5, 6
6
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output Low Current
Input Leakage Current
Output Leakage Current
V
0.90 * VTT
VTT * 0.10 / 67
VTT * 0.10 / 67
N/A
V
2, 5, 6
6, 7
6, 7
8
A
A
µA
µA
ILO
N/A
± 100
9
NOTES:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
All outputs are open drain.
V
IL is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
IH is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
IH and VOH may experience excursions above VTT.
The VTT referred to in these specifications refers to instantaneous VTT.
OL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.
4.
V
5.
6.
7.
8.
9.
V
I
Leakage to VSS with land held at VTT.
Leakage to VTT with land held at 300 mV.
2.7.3.1
Platform Environment Control Interface (PECI) DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
processor contains Digital Thermal Sensors (DTS) distributed throughout die. These
sensors are implemented as analog-to-digital converters calibrated at the factory for
reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
Datasheet
29
Electrical Specifications
Table 2-12. PECI DC Electrical Limits
Symbol
Definition and Conditions
Input Voltage Range
Min
Max
Units
Notes1
Vin
-0.15
VTT
—
V
V
V
V
2
Vhysteresis Hysteresis
0.1 * VTT
Vn
Vp
Negative-edge threshold voltage
0.275 * VTT 0.500 * VTT
0.550 * VTT 0.725 * VTT
Positive-edge threshold voltage
High level output source
(VOH = 0.75 * VTT)
Isource
-6.0
0.5
N/A
1.0
mA
mA
Low level output sink
(VOL = 0.25 * VTT)
Isink
3
Ileak+
Ileak-
High impedance state leakage to VTT
High impedance leakage to GND
Bus capacitance per node
N/A
N/A
50
10
10
—
µA
µA
2
4
Cbus
—
pF
Vnoise
Signal noise immunity above 300 MHz
0.1 * VTT
Vp-p
NOTES:
1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer
to Table 2-3 for VTT specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
.
2.7.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-7 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
Table 2-13. GTL+ Bus Resistance Definitions
Symbol
Parameter
Min
Typ
Max
Units Notes1
GTLREF_PU GTLREF pull up resistor
GTLREF_PD GTLREF pull down resistor
57.6 * 0.99
100 * 0.99
45
57.6
100
57.6 * 1.01
100 * 1.01
55
Ω
Ω
Ω
Ω
Ω
2
2
3
4
4
RTT
Termination Resistance
50
COMP[3:0] COMP Resistance
49.40
49.90
24.90
50.40
COMP8
COMP Resistance
24.65
25.15
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Variable
GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF
circuit may require different resistor values. Each GTLREF land must be connected.
3.
4.
R
TT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to VSS
.
30
Datasheet
Electrical Specifications
2.8
Clock Specifications
2.8.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5 (see Table 2-14 for the processor supported ratios).
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
Table 2-14. Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
Core Frequency
(333 MHz BCLK/
1333 MHz FSB)
Core Frequency
(400 MHz BCLK/
1600 MHz FSB)
Notes1, 2
2 GHz
1/6
1/7
2.6 GHz
2.8 GHz
3.0 GHz
3.2 GHz
3.4 GHz
3.6 GHz
3.8 GHz
4.0 GHz
4.2 GHz
4.4 GHz
4.6 GHz
4.8 GHz
5.0 GHz
5.2 GHz
5.4 GHz
5.6 GHz
5.8 GHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3 GHz
1/7.5
1/8
1/8.5
1/9
3.16 GHz
3.33 GHz
3.50 GHz
3.66 GHz
3.83 GHz
4 GHz
1/9.5
1/10
1/10.5
1/11
1/11.5
1/12
1/12.5
1/13
1/13.5
1/14
1/15
4.16 GHz
4.33 GHz
4.50 GHz
4.66 GHz
5 GHz
NOTES:
1.
2.
Individual processors operate only at or below the rated frequency.
Listed frequencies are not necessarily committed production frequencies.
Datasheet
31
Electrical Specifications
2.8.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Intel® Core™2 Extreme processor QX9650, Intel® Core™2 Quad processor Q9000,
Q9000S, Q8000, and Q8000S series operate at a 1333 MHz FSB frequency (selected by
a 333 MHz BCLK[1:0] frequency). The Intel® Core™2 Extreme processor QX9770
operates at a 1600 MHz FSB frequency (selected by a 400 MHz BCLK[1:0] frequency)
Individual processors will only operate at their specified FSB frequency.
For more information about these signals, refer to Section 4.2.
Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
L
L
H
H
L
RESERVED
RESERVED
RESERVED
RESERVED
400 MHz
L
H
H
H
H
L
L
H
H
H
H
L
H
H
L
RESERVED
RESERVED
333 MHz
L
2.8.3
2.8.4
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 2-3 for DC specifications.
BCLK[1:0] Specifications
Table 2-16. Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Input Low Voltage
Input High Voltage
Min
Typ
Max
Unit
Figure Notes1
VL
-0.30
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.15
0.550
0.140
1.4
V
V
V
V
V
V
V
2-3
2-3
2-3
2-3
2-3
2-3
2-4
3
3
2
-
VH
VCROSS(abs) Absolute Crossing Point
0.300
N/A
ΔVCROSS Range of Crossing Points
VOS
VUS
Overshoot
N/A
4
4
5
Undershoot
-0.300
0.300
N/A
VSWING
Differential Output Swing
N/A
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
3.
4.
“Steady state” voltage, not including overshoot or undershoot.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
5.
Measurement taken from differential waveform.
32
Datasheet
Electrical Specifications
Table 2-17. FSB Differential Clock Specifications (1600 MHz FSB)
T# Parameter
BCLK[1:0] Frequency
Min
Nom
Max
Unit
Figure Notes1
397.962
2.499766
-
-
-
-
400.037
2.512800
150
MHz
ns
-
T1: BCLK[1:0] Period
2-3
2-3
2
T2: BCLK[1:0] Period Stability
ps
3, 4, 7
T5: BCLK[1:0] Rise and Fall Slew
Rate
2.5
-
8
V/ns
%
2-4
-
5
6
Slew Rate Matching
N/A
N/A
20
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 400 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -100 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +100 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
4.
For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
5.
6.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
7.
Duty Cycle (High time/Period) must be between 40 and 60%
Table 2-18. FSB Differential Clock Specifications (1333 MHz FSB)
T# Parameter
BCLK[1:0] Frequency
Min
Nom
Max
Unit
Figure Notes1
331.633
2.99970
—
—
—
333.367
3.01538
150
MHz
ns
-
6
2
3
4
5
T1: BCLK[1:0] Period
2-3
2-3
2-4
-
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew Rate
Slew Rate Matching
—
ps
2.5
—
8
V/ns
%
N/A
N/A
20
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4.
5.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6.
Duty Cycle (High time/Period) must be between 40% and 60%.
Datasheet
33
Electrical Specifications
.
Figure 2-3. Differential Clock Waveform
Tph
Overshoot
VH
BCLK1
Rising Edge
Ringback
Ringback
Margin
VCROSS (ABS
)
VCROSS (ABS)
Threshold
Region
Falling Edge
Ringback
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
Figure 2-4. Measurement Points for Differential Clock Waveforms
Slew_rise
Slew _fall
+150 mV
+150mV
0.0V
0.0V
V_swing
-150 mV
-150mV
Diff
T5 = BCLK[1:0] rise and fall time through the swing region
§
34
Datasheet
Package Mechanical Specifications
3 Package Mechanical
Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch
of the processor package components and how they are assembled together. Refer to
the LGA775 Socket Mechanical Design Guide for complete details on the LGA775
socket.
The package components shown in Figure 3-1 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors
Figure 3-1. Processor Package Assembly Sketch
Core (die)
TIM
IHS
Substrate
Capacitors
LGA775 Socket
System Board
NOTE:
1.
Socket and motherboard are included for reference and are not part of processor package.
3.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal and
Mechanical Design Guidelines.
Datasheet
35
Package Mechanical Specifications
Figure 3-2. Processor Package Drawing (Sheet 1 of 3)
36
Datasheet
Package Mechanical Specifications
Figure 3-3. Processor Package Drawing (Sheet 2 of 3)
Datasheet
37
Package Mechanical Specifications
Figure 3-4. Processor Package Drawing (Sheet 3 of 3)
38
Datasheet
Package Mechanical Specifications
3.2
3.3
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keep-
out zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-
out zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
maintained by any thermal and mechanical solutions.
.
Table 3-1.
Processor Loading Specifications
Parameter
Minimum
Maximum
Notes
Static
80 N [17 lbf]
—
311 N [70 lbf]
756 N [170 lbf]
1, 2, 3
1, 3, 4
Dynamic
NOTES:
1.
2.
3.
4.
These specifications apply to uniform compressive loading in a direction normal to the
processor IHS.
This is the maximum force that can be applied by a heatsink retention clip. The clip must
also provide the minimum specified load on the processor package.
These specifications are based on limited testing for design characterization. Loading limits
are for the package only and do not include the limits of the processor socket.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static
load requirement.
3.4
Package Handling Guidelines
Table 3-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.
Package Handling Guidelines
Parameter
Maximum Recommended
Notes
Shear
Tensile
Torque
311 N [70 lbf]
111 N [25 lbf]
1, 4
2, 4
3, 4
3.95 N-m [35 lbf-in]
NOTES:
1.
2.
3.
4.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top
surface.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the
IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal
to the IHS top surface.
These guidelines are based on limited testing for design characterization.
Datasheet
39
Package Mechanical Specifications
3.5
3.6
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.
3.7
Processor Materials
Table 3-3 lists some of the package components and associated materials.
Table 3-3.
Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel Plated Copper
Fiber Reinforced Resin
Gold Plated Copper
Substrate Lands
3.8
Processor Markings
Figure 3-5 and Figure 3-6 show the topside markings on the processor. This diagram is
to aid in the identification of the processor.
Figure 3-5. Processor Top-Side Markings Example (Intel® Core™2 Extreme Processor
QX9650)
M
INTEL ©'06 QX9650
INTEL® CORE™2 EXTREME
SLAN3 XXXX
3.00GHZ/2M/1333/05B
e4
[FPO](e4)
ATPO
S/N
40
Datasheet
Package Mechanical Specifications
Figure 3-6. Processor Top-Side Markings Example (Intel® Core™2 Quad Processor Q9000
Series)
M
INTEL ©'06 Q9550
INTEL® CORE™2 Quad
SLAN3 XXXX
2.83GHZ/2M/1333/05A
e4
[FPO](e4)
ATPO
S/N
Datasheet
41
Package Mechanical Specifications
Figure 3-7 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
.
Figure 3-7. Processor Land Coordinates and Quadrants, Top View
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
W
V
Address/
Common Clock/
Async
Socket 775
Quadrants
Top View
U
U
T
T
R
R
P
P
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
VTT / Clocks
Data
§
42
Datasheet
Land Listing and Signal Descriptions
4 Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
4.1
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 4-1 is a listing of all processor lands ordered alphabetically by land
(signal) name. Table 4-2 is also a listing of all processor lands; the ordering is by land
number.
Datasheet
43
Land Listing and Signal Descriptions
Figure 4-1.land-out Diagram (Top View – Left Side)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AN
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AM
AL
AK
AJ
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AH
AG
AF
AE
AD
AC
AB
AA
Y
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
W
V
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
U
T
R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P
N
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
M
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L
K
J
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
FC34
VSS
FC31
FC33
VCC
H
BSEL1
FC15
FC32
G
F
BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47#
D44# DSTBN2# DSTBP2# D35#
D36#
D37#
VSS
D32#
VSS
D31#
D30#
D33#
VSS
RSVD
FC26
VTT
BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD
VSS
D43#
D42#
VSS
D41#
VSS
VSS
D40#
DBI2#
D38#
D39#
VSS
E
D
VSS
VTT
VSS
VTT
VSS
VTT
VSS
VTT
FC10
VSS
RSVD
D45#
D34#
RSVD
VTT
VTT
VCCPLL D46#
D48#
D49#
VCCIO
VSS
C
VTT
VTT
VTT
VTT
VTT
VSS
D58#
DBI3#
VSS
D54# DSTBP3#
VSS
D51#
D53#
PLL
B
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSSA
VCCA
D63#
D62#
D59#
VSS
VSS
D60#
D61#
D57#
VSS
VSS
D55#
A
FC23
RSVD
D56#
DSTBN3# VSS
16 15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
44
Datasheet
Land Listing and Signal Descriptions
Figure 4-2.land-out Diagram (Top View – Right Side)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VID_SEL
ECT
VSS_MB_
REGULATION REGULATION SENSE
VCC_MB_
VSS_
VCC_
SENSE
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VID0
VSS
AN
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VID7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC40
VID3
FC8
VID6
VID1
VSS
VID5
VID4
VSS
VID2
VSS
FC25
FC24
BPM1#
VSS
AM
AL
AK
AJ
VRDSEL PROCHOT#
VCC
VSS
ITP_CLK0
ITP_CLK1
VSS
VSS
VCC
A35#
VSS
A34#
A33#
A31#
A27#
VSS
BPM0#
RSVD
BPM3#
BPM4#
VSS
VCC
A32#
A30#
A28#
RSVD
VSS
AH
AG
AF
AE
AD
AC
AB
VCC
A29#
VSS
BPM5#
VSS
TRST#
TDO
VCC
SKTOCC#
VCC
RSVD
A22#
VSS
FC18
TCK
ADSTB1#
A25#
A24#
FC36
BPM2#
DBR#
IERR#
TDI
VCC
RSVD
A26#
VSS
TMS
VCC
A17#
FC37
VSS
VTT_OUT_
RIGHT
VCC
VCC
VSS
VSS
VSS
A23#
VSS
A21#
A20#
VSS
PSI#
FC39
VSS
AA
Y
FC0/BOOT-
SELECT
A19#
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
A18#
VSS
A10#
VSS
A16#
A14#
A12#
A9#
VSS
A15#
A13#
A11#
TESTHI1
VSS
TDI_M
RSVD
MSID0
MSID1
TDO_M
COMP1
W
V
FC30
VSS
FC29
U
T
DPRSTP#
FERR#/
PBE#
VCC
VSS
ADSTB0#
VSS
A8#
VSS
COMP3
R
VCC
VCC
VSS
VSS
A4#
RSVD
RSVD
VSS
INIT#
VSS
SMI#
P
N
DPSLP#
VSS
RSVD
IGNNE# PWRGOOD
THER-
VSS
VCC
VSS
REQ2#
A5#
A7#
STPCLK#
M
MTRIP#
VCC
VCC
VSS
VSS
VSS
A3#
A6#
VSS
LINT1
LINT0
L
SLP#
REQ3#
VSS
REQ0#
A20M#
VSS
K
VTT_OUT_
LEFT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VSS
REQ4#
VSS
REQ1#
VSS
FC22
VSS
FC3
J
H
TESTHI10
FC35
GTLREF1
GTLREF0
BPMb0#
D29#
D28#
VSS
D27#
VSS
DSTBN1# DBI1# GTLREF3
D16#
D18#
D19#
VSS
BPRI#
D17#
VSS
DEFER#
VSS
RSVD
FC21
RSVD
VSS
PECI
RS1#
FC20
VSS
BPMb2#
VSS
BPMb3#
BR0#
COMP2
GTLREF2
VSS
G
F
D24#
DSTBP1#
VSS
D23#
VSS
VSS
D21#
D22#
D26#
D25#
RSVD
D20#
HITM#
HIT#
TRDY#
VSS
E
D
C
RSVD
D15#
D12#
ADS#
RSVD
DRDY#
VSS
D52#
VSS
D14#
D11#
VSS
BPMb1# DSTBN0#
VSS
D3#
D1#
VSS
LOCK#
BNR#
VSS
D50#
14
COMP8
COMP0
13
D13#
VSS
12
VSS
D9#
11
D10#
D8#
10
DSTBP0#
VSS
DBI0#
8
D6#
D7#
7
D5#
VSS
6
VSS
D4#
5
D0#
D2#
4
RS0#
RS2#
3
DBSY#
VSS
2
B
A
VSS
9
1
Datasheet
45
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
A3#
A4#
L5
P6
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
BPMb0#
BPMb1#
BPMb2#
BPMb3#
BPRI#
BR0#
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
COMP8
D0#
G1
C9
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
A5#
M5
G4
A6#
L4
G3
A7#
M4
G8
Common Clock
Input
A8#
R4
F3
Common Clock Input/Output
A9#
T5
G29
H30
G30
A13
T1
Asynch CMOS
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Input
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
A20M#
ADS#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
BNR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
U6
T4
U5
U4
Input
V5
G2
Input
V4
R1
Input
W5
AB6
W6
Y6
B13
B4
Input
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
D1#
C5
D2#
A4
Y4
D3#
C6
AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
AH5
AJ5
AJ6
K3
D4#
A5
D5#
B6
D6#
B7
D7#
A7
D8#
A10
A11
B10
C11
D8
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
B12
C12
D11
G9
F8
F9
Asynch CMOS
Input
E9
D2
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
D7
R6
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
AD5
F28
G28
C2
Clock
Clock
Input
Input
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
AJ2
AJ1
AD2 Common Clock Input/Output
AG2 Common Clock Input/Output
AF2
Common Clock Input/Output
AG3 Common Clock Input/Output
46
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
D32#
D33#
G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
A8
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
B9
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
E12
G19
C17
D34#
D35#
D36#
FC0/
BOOTSELECT
Y1
Power/Other
D37#
FC3
FC8
J2
AK6
E24
H29
AE3
E5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D38#
D39#
FC10
D40#
FC15
D41#
FC18
D42#
FC20
D43#
FC21
F6
D44#
FC22
J3
D45#
FC23
A24
AK1
AL1
E29
U2
D46#
FC24
D47#
FC25
D48#
FC26
D49#
FC29
D50#
FC30
U3
D51#
FC31
J16
H15
H16
J17
H4
D52#
FC32
D53#
FC33
D54#
FC34
D55#
FC35
D56#
FC36
AD3
AB3
AA2
AM6
R3
D57#
FC37
D58#
FC39
D59#
FC40
D60#
FERR#/PBE#
GTLREF0
GTLREF1
GTLREF2
GTLREF3
HIT#
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Output
Input
Input
Input
Input
D61#
H1
D62#
H2
D63#
F2
DBI0#
DBI1#
DBI2#
DBI3#
DBR#
DBSY#
DEFER#
DPRSTP#
DPSLP#
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
G10
D4
G11
D19
C20
AC2
B2
Common Clock Input/Output
Common Clock Input/Output
HITM#
IERR#
IGNNE#
INIT#
ITP_CLK0
ITP_CLK1
LINT0
LINT1
LOCK#
MSID0
MSID1
E4
AB2
N2
Asynch CMOS
Asynch CMOS
Asynch CMOS
TAP
Output
Input
Input
Input
Input
Input
Input
Power/Other
Output
Common Clock Input/Output
P3
G7
Common Clock
Asynch CMOS
Asynch CMOS
Input
Input
Input
AK3
AJ3
K1
T2
TAP
P1
Asynch CMOS
Asynch CMOS
C1
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
L1
C8
C3
Common Clock Input/Output
G12
G20
A16
W1
V1
Power/Other
Power/Other
Output
Output
Datasheet
47
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
PECI
PROCHOT#
PWRGOOD
PSI#
G5
AL2
N1
Power/Other Input/Output
Asynch CMOS Input/Output
TESTHI5
TESTHI6
TESTHI7
THERMTRIP#
TMS
G26
G24
Power/Other
Power/Other
Power/Other
Asynch CMOS
TAP
Input
Input
Input
Output
Input
Input
Input
Power/Other
Asynch CMOS
Input
F24
Y3
Output
M2
REQ0#
K4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
AC1
REQ1#
J5
TRDY#
TRST#
VCC
E3
Common Clock
TAP
REQ2#
M6
K6
AG1
REQ3#
AA8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
REQ4#
J6
VCC
AB8
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
RS0#
V2
VCC
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC8
A20
AC4
AE4
AE6
AH2
D1
VCC
VCC
VCC
VCC
VCC
VCC
D14
D16
E23
E6
VCC
VCC
VCC
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD8
VCC
E7
VCC
F23
F29
G6
VCC
VCC
VCC
N4
VCC
N5
VCC
P5
VCC
G23
B3
Common Clock
Common Clock
Common Clock
Common Clock
Power/Other
Asynch CMOS
Asynch CMOS
Asynch CMOS
TAP
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
VCC
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AE9
VCC
RS1#
F5
VCC
RS2#
A3
VCC
SKTOCC#
SLP#
AE8
L2
VCC
VCC
SMI#
P2
VCC
STPCLK#
TCK
M3
AE1
AD1
W2
AF1
U1
VCC
VCC
TDI
TAP
VCC
TDI_M
Power/Other
TAP
VCC
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22
AF8
TDO
VCC
TDO_M
TAP
VCC
TESTHI0
TESTHI1
TESTHI10
TESTHI2
TESTHI3
TESTHI4
F26
W3
H5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
F25
G25
G27
VCC
VCC
VCC
48
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30
AG8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AG9
AH11
AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30
AH8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AJ9
AK11
Datasheet
49
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AN22
AN25
AN26
AN29
AN30
AN8
AN9
J10
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J11
J12
J13
P8
J14
R8
J15
T23
T24
T25
T26
T27
T28
T29
T30
T8
J18
J19
J20
J21
J22
J23
J24
J25
J26
U23
U24
U25
U26
U27
U28
U29
U30
U8
J27
J28
J29
J30
J8
J9
K23
K24
K25
K26
K27
K28
K29
K30
K8
V8
W23
W24
W25
W26
W27
W28
W29
W30
W8
L8
M23
M24
M25
M26
M27
M28
M29
M30
Y23
Y24
Y25
Y26
Y27
Y28
50
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
VCC
VCC
VCC
Y29
Y30
Y8
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC_MB_
REGULATION
AN5
Power/Other
Output
Output
VCC_SENSE
VCCA
VCCIOPLL
VCCPLL
VID_SELECT
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VRDSEL
VSS
AN3
A23
C23
D23
AN7
AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
AL3
B1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Output
Output
Output
Output
Output
Output
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE5
VSS
B11
B14
B17
B20
B24
B5
VSS
VSS
VSS
VSS
VSS
VSS
B8
VSS
A12
A15
A18
A2
VSS
AE7
VSS
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF3
VSS
VSS
A21
A6
VSS
VSS
A9
VSS
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF30
AF6
VSS
VSS
AF7
VSS
AG10
Datasheet
51
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG13
AG16
AG17
AG20
AG23
AG24
AG7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AN1
AH6
AH7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AN10
AN13
AN16
AN17
AN2
AN20
AN23
AN24
AN27
AN28
C10
AJ7
AK10
AK13
AK16
AK17
AK2
C13
C16
C19
C22
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
C24
C4
C7
D12
D15
D18
D21
D24
AK7
D3
AL10
D5
52
Datasheet
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D6
D9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L23
L24
L25
L26
L27
L28
L29
L3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
E11
E14
E17
E2
E20
E25
E26
E27
E28
E8
L30
L6
L7
M1
F10
F13
F16
F19
F22
F4
M7
N3
N6
N7
P23
P24
P25
P26
P27
P28
P29
P30
P4
F7
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3
P7
R2
R23
R24
R25
R26
R27
R28
R29
R30
R5
R7
H6
T3
H7
T6
H8
T7
H9
U7
J4
V23
V24
V25
V26
V27
J7
K2
K5
K7
Datasheet
53
Land Listing and Signal Descriptions
Table 4-1.
Alphabetical Land
Assignments
Table 4-1.
Alphabetical Land
Assignments
Signal Buffer
Signal Buffer
Land Name Land #
Direction
Land Name Land #
Direction
Type
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V28
V29
V3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
A26
A27
A28
A29
A30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V30
V6
V7
W4
W7
Y2
Y5
Y7
VSS_MB_
REGULATION
AN6
Power/Other
Output
Output
VSS_SENSE
VSSA
VTT
AN4
B23
B25
B26
B27
B28
B29
B30
A25
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT_OUT_LE
FT
J1
Power/Other
Output
VTT
VTT
VTT_OUT_RI
GHT
AA1
F27
Power/Other
Power/Other
Output
Output
VTT
VTT_SEL
VTT
54
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
VTT_OUT_RI
AC28
AC29
AC30
AD1
VCC
VCC
Power/Other
Power/Other
Power/Other
TAP
AA1
Power/Other
Output
GHT
FC39
VSS
AA2
AA3
Power/Other
Power/Other
VCC
TDI
Input
AA4
A21#
A23#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
AD2
BPM2#
FC36
VSS
Common Clock Input/Output
Power/Other
AA5
AD3
AA6
AD4
Power/Other
AA7
VSS
Power/Other
AD5
ADSTB1#
A22#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
AA8
VCC
Power/Other
AD6
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
VSS
Power/Other
AD7
VSS
Power/Other
AD8
VCC
Power/Other
VSS
Power/Other
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AE1
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
AB2
IERR#
FC37
A26#
A24#
A17#
VSS
Asynch CMOS
Power/Other
Output
VCC
Power/Other
AB3
TCK
TAP
Input
AB4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
AE2
VSS
Power/Other
Power/Other
AB5
AE3
FC18
RESERVED
VSS
AB6
AE4
AB7
AE5
Power/Other
AB8
VCC
Power/Other
AE6
RESERVED
VSS
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
VSS
Power/Other
AE7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
Power/Other
AE8
SKTOCC#
VCC
Output
VSS
Power/Other
AE9
VSS
Power/Other
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
VSS
VSS
Power/Other
VCC
VSS
Power/Other
VCC
VSS
Power/Other
VSS
VSS
Power/Other
VCC
TMS
DBR#
VSS
TAP
Input
VCC
AC2
Power/Other
Power/Other
Output
VSS
AC3
VSS
AC4
RESERVED
A25#
VSS
VCC
AC5
Source Synch Input/Output
Power/Other
VCC
AC6
VSS
AC7
VSS
Power/Other
VCC
AC8
VCC
Power/Other
VCC
AC23
AC24
AC25
AC26
AC27
VCC
Power/Other
VCC
VCC
Power/Other
VSS
VCC
Power/Other
VSS
VCC
Power/Other
VSS
VCC
Power/Other
VSS
Datasheet
55
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
AE28
AE29
AE30
AF1
VSS
VSS
Power/Other
Power/Other
Power/Other
TAP
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
RESERVED
VSS
A32#
A33#
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
TDO
BPM4#
VSS
Output
AF2
Common Clock Input/Output
Power/Other
AF3
AF4
A28#
A27#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
AF5
AF6
AF7
VSS
Power/Other
AF8
VCC
VCC
VSS
Power/Other
AF9
Power/Other
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG1
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
AH2
VSS
Power/Other
AH3
Power/Other
VCC
VCC
VSS
Power/Other
AH4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
AH5
Power/Other
AH6
VCC
VCC
VSS
Power/Other
AH7
Power/Other
Power/Other
AH8
Power/Other
Power/Other
AH9
Power/Other
VSS
Power/Other
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
TRST#
BPM3#
BPM5#
A30#
A31#
A29#
VSS
TAP
Input
Power/Other
AG2
Common Clock Input/Output
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
AG3
Power/Other
AG4
Power/Other
AG5
Power/Other
AG6
Power/Other
AG7
Power/Other
AG8
VCC
VCC
VSS
Power/Other
Power/Other
AG9
Power/Other
Power/Other
AG10
AG11
AG12
AG13
Power/Other
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
56
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
AH30
AJ1
VCC
BPM1#
BPM0#
ITP_CLK1
VSS
Power/Other
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AL1
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
FC25
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input/Output
AJ2
AJ3
TAP
Input
AJ4
Power/Other
AJ5
A34#
A35#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AJ6
AJ7
AJ8
VCC
AJ9
VCC
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK1
VSS
VCC
VCC
VSS
VCC
VCC
VSS
AL2
PROCHOT# Asynch CMOS Input/Output
VSS
AL3
VRDSEL
VID5
VID1
VID3
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
Power/Other
Asynch CMOS
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
AL4
Output
Output
Output
VCC
AL5
VSS
AL6
VCC
AL7
VCC
AL8
VSS
AL9
VSS
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AM1
VCC
VCC
VSS
VSS
VSS
VSS
FC24
VSS
AK2
AK3
ITP_CLK0
VID4
VSS
TAP
Input
AK4
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
AK5
AK6
FC8
AK7
VSS
AK8
VCC
AK9
VCC
AK10
AK11
AK12
AK13
AK14
AK15
VSS
VCC
VCC
VSS
VCC
VCC
Datasheet
57
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
AM2
AM3
VID0
VID2
VSS
VID6
FC40
VID7
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
Asynch CMOS
Asynch CMOS
Power/Other
Asynch CMOS
Power/Other
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
A2
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock
AM4
VCC
AM5
Output
Output
VSS
AM6
VCC
AM7
VCC
AM8
VSS
AM9
VSS
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AN1
VCC
VCC
VSS
VSS
VCC
VCC
VSS
A3
RS2#
D02#
D04#
VSS
Input
A4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A5
A6
A7
D07#
DBI0#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
B1
D08#
D09#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
COMP0
D50#
VSS
Power/Other
Input
Source Synch Input/Output
Power/Other
DSTBN3#
D56#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
AN2
AN3 VCC_SENSE
Power/Other
Power/Other
Output
Output
D61#
RESERVED
VSS
Source Synch Input/Output
AN4
VSS_SENSE
VCC_MB_
REGULATION
Power/Other
AN5
Power/Other
Power/Other
Output
D62#
VCCA
FC23
VTT
Source Synch Input/Output
Power/Other
VSS_MB_
REGULATION
AN6
Output
Output
Power/Other
AN7 VID_SELECT Power/Other
Power/Other
AN8
AN9
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
Power/Other
VTT
Power/Other
AN10
AN11
AN12
AN13
AN14
AN15
AN16
VTT
Power/Other
VTT
Power/Other
VTT
Power/Other
VSS
Power/Other
B10
B11
D10#
VSS
Source Synch Input/Output
Power/Other
58
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
B12
B13
B14
B15
B16
B17
B18
B19
B2
D13#
COMP8
VSS
Source Synch Input/Output
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
DBI3#
D58#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Input
D53#
D55#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCCIOPLL
VSS
Power/Other
Power/Other
VTT
Power/Other
D57#
D60#
DBSY#
RS0#
D00#
VSS
Source Synch Input/Output
Source Synch Input/Output
Common Clock Input/Output
VTT
Power/Other
VTT
Power/Other
VTT
Power/Other
B3
Common Clock
Input
VTT
Power/Other
B4
Source Synch Input/Output
Power/Other
VTT
Power/Other
B5
RESERVED
ADS#
VSS
B6
D05#
D06#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D2
Common Clock Input/Output
Power/Other
B7
D3
B8
D4
HIT#
VSS
Common Clock Input/Output
Power/Other
B9
DSTBP0#
VSS
Source Synch Input/Output
Power/Other
D5
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
D6
VSS
Power/Other
D59#
D63#
VSSA
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D7
D20#
D12#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D8
D9
Power/Other
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
E2
D22#
D15#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
VTT
Power/Other
VTT
Power/Other
D25#
RESERVED
VSS
Source Synch Input/Output
VTT
Power/Other
VTT
Power/Other
Power/Other
VTT
Power/Other
RESERVED
D49#
VSS
DRDY#
BNR#
LOCK#
VSS
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Power/Other
Source Synch Input/Output
Power/Other
C2
C3
DBI2#
D48#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
C4
C5
D01#
D03#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
C6
D46#
VCCPLL
VSS
Source Synch Input/Output
Power/Other
C7
C8
DSTBN0#
BPMb1#
VSS
Source Synch Input/Output
Common Clock Input/Output
Power/Other
Power/Other
C9
VTT
Power/Other
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
VTT
Power/Other
D11#
D14#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
VTT
Power/Other
VTT
Power/Other
D52#
D51#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
VSS
Power/Other
E3
TRDY#
HITM#
FC20
RESERVED
Common Clock
Input
DSTBP3#
D54#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
E4
Common Clock Input/Output
Power/Other
E5
E6
Datasheet
59
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
E7
E8
RESERVED
F25
F26
F27
F28
F29
G1
TESTHI2
TESTHI0
VTT_SEL
BCLK0
RESERVED
BPMb0#
COMP2
BPMb3#
BPMb2#
PECI
Power/Other
Power/Other
Power/Other
Clock
Input
Input
VSS
D19#
D21#
VSS
Power/Other
E9
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Output
Input
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
F2
DSTBP1#
D26#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Common Clock Input/Output
Power/Other Input
G2
G3
Common Clock Input/Output
Common Clock Input/Output
D33#
D34#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
G4
G5
Power/Other
Input/Output
G6
RESERVED
DEFER#
BPRI#
D39#
D40#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
G7
Common Clock
Common Clock
Input
Input
G8
G9
D16#
Source Synch Input/Output
Power/Other Input
D42#
D45#
RESERVED
FC10
Source Synch Input/Output
Source Synch Input/Output
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
H1
GTLREF3
DBI1#
DSTBN1#
D27#
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
D29#
VSS
D31#
VSS
D32#
VSS
D36#
FC26
D35#
GTLREF2
BR0#
VSS
Power/Other
Input
DSTBP2#
DSTBN2#
D44#
F3
Common Clock Input/Output
Power/Other
F4
F5
RS1#
FC21
Common Clock
Power/Other
Power/Other
Input
D47#
F6
RESET#
TESTHI6
TESTHI3
TESTHI5
TESTHI4
BCLK1
BSEL0
Common Clock
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
F7
VSS
F8
D17#
D18#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
D23#
D24#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
BSEL2
D28#
D30#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
GTLREF0
GTLREF1
VSS
H2
H3
D37#
D38#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
H4
FC35
H5
TESTHI10
VSS
Input
H6
D41#
D43#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
H7
VSS
H8
VSS
H9
VSS
RESERVED
TESTHI7
H10
H11
VSS
Power/Other
Input
VSS
60
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
VSS
VSS
VSS
FC32
FC33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC15
BSEL1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
J27
J28
J29
J30
K1
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
Asynch CMOS
VCC
VCC
LINT0
VSS
Input
Input
K2
K3
A20M#
REQ0#
VSS
K4
Source Synch Input/Output
Power/Other
K5
K6
REQ3#
VSS
Source Synch Input/Output
Power/Other
K7
K8
VCC
Power/Other
K23
K24
K25
K26
K27
K28
K29
K30
L1
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
Output
Output
VCC
Power/Other
VTT_OUT_LE
FT
VCC
Power/Other
J1
Power/Other
LINT1
SLP#
VSS
Asynch CMOS
Asynch CMOS
Power/Other
Input
Input
J2
J3
FC3
FC22
VSS
Power/Other
Power/Other
Power/Other
L2
L3
J4
L4
A06#
A03#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
J5
REQ1#
REQ4#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
L5
J6
L6
J7
L7
VSS
Power/Other
J8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC31
FC34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
L8
VCC
Power/Other
J9
Power/Other
L23
L24
L25
L26
L27
L28
L29
L30
M1
VSS
Power/Other
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
M2 THERMTRIP# Asynch CMOS
Output
Input
Power/Other
M3
M4
STPCLK#
A07#
A05#
REQ2#
VSS
Asynch CMOS
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
M5
Power/Other
M6
Power/Other
M7
Power/Other
M8
VCC
Power/Other
Power/Other
M23
M24
VCC
Power/Other
Power/Other
VCC
Power/Other
Datasheet
61
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
M25
M26
M27
M28
M29
M30
N1
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
R23
R24
R25
R26
R27
R28
R29
R30
T1
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
VSS
VSS
VSS
VSS
PWRGOOD
IGNNE#
VSS
Power/Other
Asynch CMOS
Power/Other
Input
Input
VSS
N2
VSS
N3
COMP1
DPRSTP#
VSS
Input
Input
N4
RESERVED
RESERVED
VSS
T2
N5
T3
N6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Asynch CMOS
Power/Other
T4
A11#
A09#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
N7
VSS
T5
N8
VCC
T6
N23
N24
N25
N26
N27
N28
N29
N30
P1
VCC
T7
VSS
Power/Other
VCC
T8
VCC
Power/Other
VCC
T23
T24
T25
T26
T27
T28
T29
T30
U1
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
DPSLP#
SMI#
INIT#
VSS
Input
Input
Input
VCC
Power/Other
P2
VCC
Power/Other
P3
TDO_M
FC29
FC30
A13#
A12#
A10#
VSS
TAP
Output
P4
U2
Power/Other
Power/Other
P5
RESERVED
A04#
VSS
U3
P6
Source Synch Input/Output
Power/Other
U4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
P7
U5
P8
VCC
Power/Other
U6
P23
P24
P25
P26
P27
P28
P29
P30
R1
VSS
Power/Other
U7
VSS
Power/Other
U8
VCC
Power/Other
VSS
Power/Other
U23
U24
U25
U26
U27
U28
U29
U30
V1
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
COMP3
VSS
Power/Other
Power/Other
Input
VCC
Power/Other
R2
VCC
Power/Other
R3
FERR#/PBE# Asynch CMOS
Output
MSID1
RESERVED
VSS
Power/Other
Output
R4
A08#
VSS
Source Synch Input/Output
Power/Other
V2
R5
V3
Power/Other
R6
ADSTB0#
VSS
Source Synch Input/Output
Power/Other
V4
A15#
A14#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
R7
V5
R8
VCC
Power/Other
V6
62
Datasheet
Land Listing and Signal Descriptions
Table 4-2.
Numerical Land
Assignment
Table 4-2.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
V7
V8
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
W26
W27
W28
W29
W30
VCC
VCC
VCC
VCC
VCC
FC0/
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V23
V24
V25
V26
V27
V28
V29
V30
W1
VSS
VSS
VSS
VSS
Y1
Power/Other
BOOTSELECT
VSS
Y2
Y3
VSS
Power/Other
VSS
PSI#
A20#
VSS
Asynch CMOS
Output
VSS
Y4
Source Synch Input/Output
Power/Other
VSS
Y5
MSID0
TDI_M
Output
Input
Input
Y6
A19#
VSS
Source Synch Input/Output
Power/Other
W2
Y7
W3
TESTHI1
VSS
Power/Other
Power/Other
Y8
VCC
Power/Other
W4
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
VCC
Power/Other
W5
A16#
A18#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
W6
VCC
Power/Other
W7
VCC
Power/Other
W8
VCC
Power/Other
VCC
Power/Other
W23
W24
W25
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
Datasheet
63
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 4-3.
Signal Description (Sheet 1 of 10)
Name
Type
Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these signals
transmit the address of a transaction. In sub-phase 2, these
signals transmit transaction type information. These signals must
connect the appropriate pins/lands of all agents on the processor
FSB. A[35:3]# are source synchronous signals and are latched
into the receiving buffers by ADSTB[1:0]#.
Input/
Output
A[35:3]#
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M#
Input
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must
be valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All
bus agents observe the ADS# activation to begin protocol
checking, address decode, internal snoop, or deferred reply ID
match operations associated with the new transaction.
Input/
Output
ADS#
Address strobes are used to latch A[35:3]# and REQ[4:0]# on
their rising and falling edges. Strobes are associated with signals
as shown below.
Input/
Output
ADSTB[1:0]#
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All processor FSB agents must receive these signals to
drive their outputs and latch their inputs.
BCLK[1:0]
BNR#
Input
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS
.
BNR# (Block Next Request) is used to assert a bus stall by any
bus agent unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
Input/
Output
64
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 2 of 10)
Name
Type
Description
BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint
and performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPM[5:0]# and BPMb[3:0]# should connect the
appropriate pins/lands of all processor FSB agents. BPM[3:0]# are
associated with core 0. BPMb[3:0]# are associated with core 1.
BPM[5:0]#
Input/
Output
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
port. PRDY# is a processor output used by debug tools to
determine processor debug readiness.
BPMb[3:0]#
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination. Refer to
Section 2.6.2 for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of
all processor FSB agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by de-asserting
BPRI#.
BPRI#
Input
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
Input/
Output
BR0#
This signal does not have on-die termination and must be
terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency. Table 2-15 defines the
possible combinations of the signals and the frequency associated
with each combination. The required frequency is determined by
the processor, chipset and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations refer to
Section 2.8.2.
BSEL[2:0]
Output
Analog
COMP[3:0],
COMP8
COMP[3:0] and COMP8 must be terminated to VSS on the system
board using precision resistors.
Datasheet
65
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 3 of 10)
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must
connect the appropriate pins/lands on all such agents. The data
driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group
of 16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals
to data strobes and DBI#.
Quad-Pumped Signal Groups
DSTBN#/
Input/
Output
D[63:0]#
Data Group
DBI#
DSTBP#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]#
signals are activated when the data on the data bus is inverted. If
more than half the data bits, within a 16-bit group, would have
been asserted electrically low, the bus agent may invert the data
bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Input/
Output
DBI[3:0]#
Data Bus
Bus Signal
Signals
DBI3#
DBI2#
DBI1#
D[63:48]#
D[47:32]#
D[31:16]#
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by
DBR#
Output a debug port interposer so that an in-target probe can drive
system reset. If a debug port is implemented in the system, DBR#
is a no connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is
Input/
DBSY#
in use. The data bus is released after DBSY# is de-asserted. This
Output
signal must connect the appropriate pins/lands on all processor
FSB agents.
66
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 4 of 10)
Name
Type
Description
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DEFER#
Input
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted.
Use of the DPRSTP# pin, and corresponding low power state,
requires chipset support and may not be available on all
platforms.
DPRSTP#
Input
NOTE:Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
DPSLP#
DRDY#
Input
NOTE: Some processors may not have the Deep Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle
clocks. This signal must connect the appropriate pins/lands of all
processor FSB agents.
Input/
Output
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Input/
Output
DSTBN[3:0]#
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Input/
Output
DSTBP[3:0]#
FC0/BOOTSELECT is not used by the processor. When this land is
tied to VSS, previous processors based on the Intel NetBurst®
microarchitecture should be disabled and prevented from booting.
FC0/
BOOTSELECT
Other
Other
FC signals are signals that are available for compatibility with
other processors.
FCx
Datasheet
67
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 5 of 10)
Name
Type
Description
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an
unmasked floating-point error. When STPCLK# is not asserted,
FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting. When STPCLK# is
FERR#/PBE#
Output asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The
assertion of FERR#/PBE# indicates that the processor should be
returned to the Normal state. For additional information on the
pending break event functionality, including the identification of
support of the feature and enable/disable information, refer to
volume 3 of the Intel Architecture Software Developer's Manual
and the Intel Processor Identification and the CPUID Instruction
application note.
GTLREF[3:0] determine the signal reference level for GTL+ input
GTLREF[3:0]
Input
signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which
can be continued by reasserting HIT# and HITM# together.
HIT#
HITM#
Input/
Output
IERR# (Internal Error) is asserted by a processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction
may optionally be converted to an external error signal (e.g., NMI)
by system core logic. The processor will keep IERR# asserted until
the assertion of RESET#.
IERR#
Output
This signal does not have on-die termination. Refer to
Section 2.6.2 for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol
floating-point instructions. If IGNNE# is de-asserted, the
processor generates an exception on a noncontrol floating-point
instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0)
is set.
IGNNE#
Input
IGNNE# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output write
instruction, it must be valid along with the TRDY# assertion of the
corresponding Input/Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers
inside the processor without affecting its internal caches or
floating-point registers. The processor then begins execution at
the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins/lands of all processor FSB agents.
INIT#
Input
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
68
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 6 of 10)
Name
Type
Description
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system
board. ITP_CLK[1:0] are used as BCLK[1:0] references for a
debug port implemented on an interposer. If a debug port is
implemented in the system, ITP_CLK[1:0] are no connects in the
system. These are not processor signals.
ITP_CLK[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
LINT[1:0]
Input
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of
all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to
the end of the last transaction.
Input/
Output
LOCK#
When the priority agent asserts BPRI# to arbitrate for ownership
of the processor FSB, it will wait until it observes LOCK# de-
asserted. This enables symmetric agents to retain ownership of
the processor FSB throughout the bus locked operation and
ensure the atomicity of lock.
On the processor these signals are not connected on the package
(they are floating). As an alternative to MSID, Intel has
MSID[1:0]
PECI
Output implemented the Power Segment Identifier (PSID) to report the
maximum Thermal Design Power of the processor. Refer to
Section 2.5 for additional information regarding PSID.
Input/
PECI is a proprietary one-wire bus interface. See Chapter 5.3 for
Output details.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit (TCC)
Input/
PROCHOT#
Output has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#.
See Section 5.2.4 for more details.
Processor Power Status Indicator Signal. This signal may be asserted when
PSI#
Output
the processor is in the Deeper Sleep State. PSI# can be used to improve
load efficiency of the voltage regulator, resulting in platform power savings.
Datasheet
69
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 7 of 10)
Name
Type
Description
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must
then transition monotonically to a high state. PWRGOOD can be
driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD.
PWRGOOD
Input
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate
pins/lands of all processor FSB agents. They are asserted by the
Output current bus owner to define the currently active transaction type.
These signals are source synchronous to ADSTB0#.
Input/
REQ[4:0]#
Asserting the RESET# signal resets the processor to a known
state and invalidates its internal caches without writing back any
of their contents. For a power-on Reset, RESET# must stay active
for at least one millisecond after VCC and BCLK have reached their
proper specifications. On observing active RESET#, all FSB agents
will de-assert their outputs within two clocks. RESET# must not be
RESET#
Input
kept asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
All RESERVED lands must remain unconnected. Connection of
these lands to VCC, VSS, VTT, or to any other signal (including each
other) can result in component malfunction or incompatibility with
future processors.
RESERVED
RS[2:0]# (Response Status) are driven by the response agent
(the agent responsible for completion of the current transaction),
and must connect the appropriate pins/lands of all processor FSB
agents.
RS[2:0]#
SKTOCC#
Input
SKTOCC# (Socket Occupied) will be pulled to ground by the
Output processor. System board designers may use this signal to
determine if the processor is present.
70
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 8 of 10)
Name
Type
Description
SLP# (Sleep), when asserted in Extended Stop Grant or Stop
Grant state, causes the processor to enter the Sleep state. In the
Sleep state, the processor stops providing internal clock signals to
all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts.
The processor will recognize only assertion of the RESET# signal,
deassertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is deasserted, the processor exits Sleep state and
returns to Extended Stop Grant or Stop Grant state, restarting its
internal clock signals to the bus and processor core units. If
DPSLP# is asserted while in the Sleep state, the processor will exit
the Sleep state and transition to the Deep Sleep state. Use of the
SLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
SLP#
Input
NOTE: Some processors may not have the Sleep State enabled,
refer to the Specification Update for specific sku and
stepping guidance.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt,
the processor saves the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the
SMM handler.
SMI#
Input
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-
asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the
bus clock; STPCLK# is an asynchronous input.
STPCLK#
Input
TCK (Test Clock) provides the clock input for the processor Test
Bus (also known as the Test Access Port).
TCK
Input
Input
TDI and TDI_M (Test Data In) transfers serial test data into the
processor. TDI and TDI_M provide the serial input needed for JTAG
specification support. TDI connects to core 0. TDI_M connects to
core 1.
TDI, TDI_M
TDO and TDO_M (Test Data Out) transfers serial test data out of
the processor. TDO and TDO_M provide the serial output needed
for JTAG specification support. TDO connects to core 1. TDO_M
connects to core 0.
TDO, TDO_M
Output
Input
TESTHI[10,7:0] must be connected to the processor’s appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT
signal description) through a resistor for proper processor
operation. See Section 2.4 for more details.
TESTHI[10,7:0]
Datasheet
71
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 9 of 10)
Name
Type
Description
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum TC.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a level beyond where
permanent silicon damage may occur. Upon assertion of
THERMTRIP#, the processor will shut off its internal clocks (thus,
halting program execution) in an attempt to reduce the processor
junction temperature. To protect the processor, its core voltage
(VCC) must be removed following the assertion of THERMTRIP#.
Driving of the THERMTRIP# signal is enabled within 10 μs of the
assertion of PWRGOOD (provided VTT and VCC are asserted) and is
disabled on de-assertion of PWRGOOD (if VTT or VCC are not valid,
THERMTRIP# may also be disabled). Once activated,
THERMTRIP#
Output
THERMTRIP# remains latched until PWRGOOD, VTT or VCC is de-
asserted. While the de-assertion of the PWRGOOD, VTT or VCC
signal will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10 μs of the assertion of PWRGOOD
(provided VTT and VCC are valid).
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TMS
Input
Input
TRDY# (Target Ready) is asserted by the target to indicate that it
is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins/lands of all FSB agents.
TRDY#
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
TRST#
VCC
Input
Input
VCC are the power pins for the processor. The voltage supplied to
these pins is determined by the VID[7:0] pins.
VCCA provides isolated power for internal PLLs on previous
generation processors. It may be left as a No-Connect on boards
supporting the processor.
VCCA
Input
VCCIOPLL provides isolated power for internal processor FSB PLLs
on previous generation processors. It may be left as a No-Connect
on boards supporting the processor.
VCCIOPLL
VCCPLL
Input
Input
VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
VCC_SENSE
Output core power (VCC). It can be used to sense or measure voltage
near the silicon with little noise.
This land is provided as a voltage regulator feedback sense point
for VCC. It is connected internally in the processor package to the
Output sense point land U27 as described in the Voltage Regulator-Down
(VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket.
VCC_MB_
REGULATION
72
Datasheet
Land Listing and Signal Descriptions
Table 4-3.
Signal Description (Sheet 10 of 10)
Name
Type
Description
The VID (Voltage ID) signals are used to support automatic
selection of power supply voltages (VCC). Refer to the Voltage
Regulator Design Guide for more information. The voltage supply
for these signals must be valid before the VR can supply VCC to
the processor. Conversely, the VR output must be disabled until
the voltage supply for the VID signals becomes valid. The VID
signals are needed to support the processor voltage specification
variations. See Table 2-1 for definitions of these signals. The VR
must supply the voltage that is requested by the signals, or
disable itself.
VID[7:0]
Output
This land is tied high on the processor package and is used by the
VID_SELECT
Output VR to choose the proper VID table. Refer to the Voltage Regulator
Design Guide for more information.
This input should be left as a no connect in order for the processor
VRDSEL
VSS
Input
Input
Input
to boot. The processor will not boot on legacy platforms where
this land is connected to VSS
.
VSS are the ground pins for the processor and should be
connected to the system ground plane.
VSSA provides isolated ground for internal PLLs on previous
generation processors. It may be left as a No-Connect on boards
supporting the processor.
VSSA
VSS_SENSE is an isolated low impedance connection to processor
VSS_SENSE
Output core VSS. It can be used to sense or measure ground near the
silicon with little noise.
This land is provided as a voltage regulator feedback sense point
VSS_MB_
REGULATION
for VSS. It is connected internally in the processor package to the
sense point land V27 as described in the Voltage Regulator Design
Output
Guide.
VTT
Miscellaneous voltage supply.
VTT_OUT_LEFT
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
Output provide a voltage supply for some signals that require termination
to VTT on the motherboard.
VTT_OUT_RIGHT
VTT_SEL
The VTT_SEL signal is used to select the correct VTT voltage level
Output for the processor. This land is connected internally in the package
to VSS
.
§
Datasheet
73
Land Listing and Signal Descriptions
74
Datasheet
Thermal Specifications and Design Considerations
5 Thermal Specifications and
Design Considerations
5.1
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
appropriate Thermal and Mechanical Design Guidelines (See Section 1.2).
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (TC)
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table 5-1. Thermal solutions not designed to provide this level of
thermal capability may affect the long-term reliability of the processor and system. For
more details on thermal solution design, refer to the appropriate Thermal and
Mechanical Design Guidelines (See Section 1.2).
The processor uses a methodology for managing processor temperatures which is
intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 5.3. If the value reported via PECI is less than TCONTROL, then the case
temperature is permitted to exceed the Thermal Profile. If the value reported via PECI
is greater than or equal to TCONTROL, then the processor case temperature must remain
at or below the temperature as specified by the thermal profile. The temperature
reported over PECI is always a negative value and represents a delta below the onset of
thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2).
Systems that implement fan speed control must be designed to take these conditions in
to account. Systems that do not alter the fan speed only need to ensure the case
temperature meets the thermal profile specifications.
In order to determine a processor's case temperature specification based on the
thermal profile, it is necessary to accurately measure processor power dissipation. Intel
has developed a methodology for accurate power measurement that correlates to Intel
test temperature and voltage conditions. Refer to the appropriate Thermal and
Mechanical Design Guidelines (See Section 1.2) for the details of this methodology.
Datasheet
75
Thermal Specifications and Design Considerations
The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 5-1 instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor or
Thermal Monitor 2 feature must be enabled for the processor to remain within
specification.
Table 5-1.
Processor Thermal Specifications
Thermal
Design
Power
Extended
HALT
Deeper
Sleep
Core
Freq.
(GHz)
Processor
Number
775_VR_CO Minimum MaximumTC
Notes
Power
Power
NFIG5
T
C (°C)
(°C)
(W) 3, 4
(W)1
(W)
2
See Table 5-2
and
Figure 5-1
QX9770
QX9650
3.20
3.00
136
130
16
16
—
—
—
5
5
8
See Table 5-3
and
Figure 5-2
775_VR_CO
NFIG_05B
7, 8
Q9650
Q9550
Q9550
Q9505
Q9450
Q9400
Q9300
Q8400
Q8300
Q8200
3.0
95
95
95
95
95
95
95
95
95
95
12
12
12
12
12
12
12
12
12
12
8
8
5
5
5
5
5
5
5
5
5
5
6
6
7
7
7
6
7
6
6
7
2.83
2.83
2.83
2.66
2.66
2.50
2.66
2.50
2.33
—
—
—
8
See Table 5-4
and
Figure 5-3
775_VR_CO
NFIG_05A
—
8
8
—
Q9550S
Q9505S
Q9400S
Q8400S
Q8200S
2.83
2.83
2.66
2.66
2.33
65
65
65
65
65
12
12
12
12
12
8
8
8
8
8
5
5
5
5
5
6
6
6
6
6
See Table 5-5
and
Figure 5-4
775_VR_CO
NFIG_06
NOTES:
1.
2.
3.
4.
Specification is at 37° C Tc and minimum voltage loadline. Specification is ensured by
design characterization and not 100% tested.
Specification is at 34° C Tc and minimum voltage loadline. Specification is ensured by design
characterization and not 100% tested.
Thermal Design Power (TDP) should be used for processor thermal solution design targets.
The TDP is not the maximum power that the processor can dissipate.
This table shows the maximum TDP for a given frequency range. Individual processors
may have a lower TDP. Therefore, the maximum TC will vary depending on the TDP of the
individual processor. Refer to thermal profile figure and associated table for the allowed
combinations of power and TC.
5.
775_VR_CONFIG_05 guidelines provide a design target for meeting future thermal
requirements.
6.
7.
8.
These processors have CPUID = 1067Ah.
These processors have CPUID = 10677h.
These processors have CPUID = 10676h.
76
Datasheet
Thermal Specifications and Design Considerations
Table 5-2.
Intel® Core™2 Extreme Processor QX9770 Thermal Profile
Power Maximum
Power Maximum
Power Maximum
Power Maximum
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
0
37.8
38.1
38.3
38.6
38.8
39.1
39.4
39.6
39.9
40.1
40.4
40.7
40.9
41.2
41.4
41.7
42.0
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
42.2
42.5
42.7
43.0
43.3
43.5
43.8
44.0
44.3
44.6
44.8
45.1
45.3
45.6
45.9
46.1
46.4
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
46.6
46.9
47.2
47.4
47.7
47.9
48.2
48.5
48.7
49.0
49.2
49.5
49.8
50.0
50.3
50.5
50.8
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
51.1
51.3
51.6
51.8
52.1
52.4
52.6
52.9
53.1
53.4
53.7
53.9
54.2
54.4
54.7
55.0
55.2
55.5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Figure 5-1. Intel® Core™2 Extreme Processor QX9770 Thermal Profile
55
53
51
49
y = 0.13x + 37.8
47
45
43
41
39
37
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Power (W)
Datasheet
77
Thermal Specifications and Design Considerations
Table 5-3.
Intel® Core™2 Extreme Processor QX9650 Thermal Profile
Power Maximum
Power Maximum
Power Maximum
Power Maximum
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
0
42.4
42.7
43.1
43.4
43.8
44.1
44.4
44.8
45.1
45.5
45.8
46.1
46.5
46.8
47.2
47.5
47.8
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
48.2
48.5
48.9
49.2
49.5
49.9
50.2
50.6
50.9
51.2
51.6
51.9
52.3
52.6
52.9
53.3
53.6
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
54.0
54.3
54.6
55.0
55.3
55.7
56.0
56.3
56.7
57.0
57.4
57.7
58.0
58.4
58.7
59.1
59.4
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
59.7
60.1
60.4
60.8
61.1
61.4
61.8
62.1
62.5
62.8
63.1
63.5
63.8
64.2
64.5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Figure 5-2. Intel® Core™2 Extreme Processor QX9650 Thermal Profile
65.0
63.0
61.0
59.0
57.0
55.0
y = 0.17x + 42.4
53.0
51.0
49.0
47.0
45.0
43.0
41.0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Power (W)
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Datasheet
Thermal Specifications and Design Considerations
Table 5-4.
Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile
Power Maximum
Power Maximum
Power Maximum
Power Maximum
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
0
2
44.8
45.4
45.9
46.5
47.0
47.6
48.2
48.7
49.3
49.8
50.4
51.0
51.5
26
28
30
32
34
36
38
40
42
44
46
48
50
52.1
52.6
53.2
53.8
54.3
54.9
55.4
56.0
56.6
57.1
57.7
58.2
58.8
52
54
56
58
60
62
64
66
68
70
72
74
76
59.4
59.9
60.5
61.0
61.6
62.2
62.7
63.3
63.8
64.4
65.0
65.5
66.1
78
80
82
84
86
88
90
92
94
95
66.6
67.2
67.8
68.3
68.9
69.4
70.0
70.6
71.1
71.4
4
6
8
10
12
14
16
18
20
22
24
Figure 5-3. Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile
72.0
68.0
64.0
y = 0.28x + 44.8
60.0
56.0
52.0
48.0
44.0
0
10
20
30
40
50
60
70
80
90
Power (W)
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79
Thermal Specifications and Design Considerations
Table 5-5.
Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile
Power Maximum
Power Maximum
Power Maximum
Power Maximum
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
(W)
Tc (°C)
0
2
49.6
50.4
51.2
52.1
52.9
53.7
54.5
55.3
56.2
18
20
22
24
26
28
30
32
34
57.0
57.8
58.6
59.4
60.3
61.1
61.9
62.7
63.5
36
38
40
42
44
46
48
50
52
64.4
65.2
66.0
66.8
67.6
68.5
69.3
70.1
70.9
54
56
58
60
62
64
65
71.7
72.6
73.4
74.2
75.0
75.8
76.3
4
6
8
10
12
14
16
Figure 5-4. Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile
80
75
70
65
y = 0.41x + 49.6
60
55
50
45
0
10
20
30
40
50
60
Power (W)
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Datasheet
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (TC) for the processor is specified in
Table 5-1. This temperature specification is meant to help ensure proper operation of
the processor. Figure 5-5 illustrates where Intel recommends TC thermal
measurements should be made. For detailed guidelines on temperature measurement
methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (See
Section 1.2).
Figure 5-5. Case Temperature (TC) Measurement Location
Measure TC atthis point
(geometric center of the package)
37.5 mm
5.2
Processor Thermal Features
5.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30-50%). Clocks often will not
be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
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81
Thermal Specifications and Design Considerations
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
and in some cases may result in a TC that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical
Design Guidelines (See Section 1.2) for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor
power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-FSB multiple utilized by the processor is that contained in the
CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2-3. These parameters
represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new
frequency. This transition occurs very rapidly (on the order of 5 μs). During the
frequency transition, the processor is unable to service any bus requests, and
consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and
kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes
to reach the target operating voltage. Each step will likely be one VID table entry (see
Table 2-3). The processor continues to execute instructions during the voltage
transition. Operation at the lower voltage reduces the power consumption of the
processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to ensure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 5-6 for an illustration of this ordering.
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Thermal Specifications and Design Considerations
Figure 5-6. Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
fMAX
fTM2
Frequency
VID
VIDTM2
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on
demand mode. The Thermal Monitor TCC, however, can be activated through the use of
the on demand mode.
5.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor
IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5%
on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand
mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.
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83
Thermal Specifications and Design Considerations
5.2.4
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#.
PROCHOT# is a bi-directional signal. As an output, PROCHOT# (Processor Hot) will go
active when the processor temperature monitoring sensor detects that one or both
cores has reached its maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores.
The TCC will remain active until the system de-asserts PROCHOT#.
Note:
PROCHOT# will not be asserted (as an output) or observed (as an input) when the
processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low-power states,
hence the thermal solution must be designed to ensure the processor remains within
specification. If the processor enters one of the above low-power states with
PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits
the low-power state and the processor DTS temperature drops below the thermal trip
point.
PROCHOT# allows for some protection of various components from over-temperature
situations. The PROCHOT# signal is bi-directional in that it can either signal when the
processor (either core) has reached its maximum operating temperature or be driven
from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained
current instead of maximum current. Systems should still provide proper cooling for the
VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling
failure. The system thermal design should allow the power delivery circuitry to operate
within its temperature specification even while the processor is operating at its Thermal
Design Power. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
of time when running the most power intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss. Refer to
the Voltage Regulator Design Guide for details on implementing the bi-directional
PROCHOT# feature.
5.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 4-3). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 4-3. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.
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Thermal Specifications and Design Considerations
5.3
Platform Environment Control Interface (PECI)
5.3.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. PECI uses
CRC checking on the host side to ensure reliable transfers between the host and client
devices. Also, data transfer speeds across the PECI interface are negotiable within a
wide range (2Kbps to 2Mbps). The PECI interface on the processor is disabled by
default and must be enabled through BIOS. More information can be found in the
Platform Environment Control Interface (PECI) Specification.
5.3.1.1
T
and TCC activation on PECI-Based Systems
CONTROL
Fan speed control solutions based on PECI utilize a TCONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the TCONTROL value as negative. Thermal management algorithms
should utilize the relative temperature value delivered over PECI in conjunction with the
T
CONTROL MSR value to control or optimize fan speeds. Figure 5-7 shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
Figure 5-7. Conceptual Fan Control Diagram on PECI-Based Platforms
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85
Thermal Specifications and Design Considerations
5.3.2
PECI Specifications
5.3.2.1
PECI Device Address
The PECI register resides at address 30h.
5.3.2.2
5.3.2.3
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command
function and codes.
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not assured to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damage. It is recommended that the PECI host controller take appropriate
action to protect the client processor device if valid temperature readings have not
been obtained in response to three consecutive GetTemp()s or for a one second time
interval. The host controller may also implement an alert to software in the event of a
critical or continuous fault condition.
5.3.2.4
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
Table 5-6.
Table 5-6.
GetTemp0() Error Codes
Error Code
8000h
Description
General sensor error
Sensor is operational, but has detected a temperature below its operational
range (underflow)
8002h
§
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Features
6 Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 6-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for configuration purposes, the processor does not distinguish between
a "warm" reset and a "power-on" reset.
Table 6-1.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Signal1,2
SMI#
Execute BIST
A3#
A25#
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
BR0#
A[24:4]#, A[35:26]#
NOTE:
1.
2.
Asserting this signal during RESET# will select the corresponding option.
Address signals not identified in this table as configuration options should not be asserted
during RESET#.
3.
Disabling of any of the cores within a processor must be handled by configuring the
EXT_CONFIG Model Specific Register (MSR). This MSR allows for the disabling of a single
core per die within the processor package.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 6-1 for a visual representation of the processor low
power states.
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89
Features
Figure 6-1. Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Extended HALT or HALT
State
- BCLK running
- Snoops and interrupts
allowed
Normal State
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
- Normal Execution
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service Snoops to caches
Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Snoop Event Occurs
Snoop Event Serviced
Stop Grant Snoop State
- BCLK running
- Service Snoops to caches
6.2.1
6.2.2
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown state must be configured and enabled via the BIOS for the processor
to remain within specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The halted core will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more
information.
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Datasheet
Features
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown must be enabled using the BIOS for the processor to remain within its
specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will first transition the VID to the original
value and then change the bus ratio back to the original value.
6.2.3
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled using BIOS. Refer to
the sections below for details about the Stop Grant and Extended Stop Grant states.
6.2.3.1
Stop-Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
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91
Features
6.2.3.2
Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted
and Extended Stop Grant has been enabled using BIOS.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended Stop Grant state. When entering the low power
state, the processor will first switch to the lower bus ratio and then transition to the
lower VID.
The processor exits the Extended Stop Grant state when a break event occurs. When
the processor exits the Extended Stop Grant state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.4
Extended HALT Snoop State, HALT Snoop State, Extended
Stop Grant Snoop State, and Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the Extended HALT state. If
Extended HALT state is not enabled in the BIOS, the default Snoop State entered will
be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State,
Stop Grant Snoop State, Extended HALT Snoop State, Extended Stop Grant Snoop
State.
6.2.4.1
6.2.4.2
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT powerdown state. During a snoop transaction, the processor enters the HALT
Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT powerdown state, as appropriate.
Extended HALT Snoop State, Extended Stop Grant Snoop State
The processor will remain in the lower bus ratio and VID operating point of the
Extended HALT state or Extended Stop Grant state.
While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops
are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After
the snoop is serviced the processor will return to the Extended HALT state or Extended
Stop Grant state.
6.2.5
Sleep State
The Sleep state is a low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Extended Stop Grant or Stop
Grant state. The SLP# pin should only be asserted when the processor is in the
Extended Stop Grant or Stop Grant state. SLP# assertions while the processor is not in
these states is out of specification and may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
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state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through the Stop-Grant state.
If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure
the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 6.2.6). While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur. PECI is not available and will not respond
while in the Sleep State.
6.2.6
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset-based platforms with
the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs
of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# de-assertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted
after DPSLP# de-assertion as described above. A period of 15 microseconds (to allow
for PLL stabilization) must occur before the processor can be considered to be in the
Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the
Stop-Grant state.
While in the Deep Sleep state the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in the Deep Sleep state. When the processor is in the Deep
Sleep state it will not respond to interrupts or snoop transactions. Any transition on an
input signal before the processor has returned to the Stop-Grant state will result in
unpredictable behavior. PECI is not available and will not respond while in the Deep
Sleep State.
6.2.7
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is
reduced to a lower level. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. Exit from Deeper Sleep is initiated by
DPRSTP# de-assertion. PECI is not available and will not respond while in the Deeper
Sleep State.
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In response to entering Deeper Sleep, the processor drives the VID code corresponding
to the Deeper Sleep core voltage on the VID pins. Unlike typical Dynamic VID changes
(where the steps are single VID steps) the processor will perform a VID jump on the
order of 100 mV. To support the Deeper Sleep State the platform must use a VRD 11.1
compliant solution.
®
6.2.8
Enhanced Intel SpeedStep Technology
The processor supports Enhanced Intel SpeedStep Technology. This technology enables
the processor to switch between frequency and voltage points, which may result in
platform power savings. In order to support this technology, the system must support
dynamic VID transitions. Switching between voltage/frequency states is software
controlled.
Enhanced Intel SpeedStep Technology is a technology that creates processor
performance states (P states). P states are power consumption and capability states
within the Normal state as shown in Figure 6-1. Enhanced Intel SpeedStep Technology
enables real-time dynamic switching between frequency and voltage points. It alters
the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to
best serve the performance and power requirements of the processor and system. Note
that the front side bus is not altered; only the internal core frequency is changed. In
order to run at reduced power consumption, the voltage is altered in step with the bus
ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
• Voltage/Frequency selection is software controlled by writing to processor MSR's
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, Vcc is incremented
in steps (+12.5 mV) by placing a new value on the VID signals after which the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and Vcc is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
6.3
Processor Power Status Indicator (PSI) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve efficiency of the
voltage regulator, resulting in platform power savings.
PSI# may be asserted only when the processor is in the Deeper Sleep state.
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Boxed Processor Specifications
7 Boxed Processor Specifications
7.1
Introduction
The Intel Core™2 Extreme processor QX9650, Intel Core™2 quad-core processor
Q9000, Q9000S, Q8000, and Q8000S series will also be offered as an Intel boxed
processor. Intel boxed processors are intended for system integrators who build
systems from baseboards and standard components. The boxed processor will be
supplied with a cooling solution. This chapter documents baseboard and system
requirements for the cooling solution that will be supplied with the boxed processor.
This chapter is particularly important for OEMs that manufacture baseboards for
system integrators.
Note:
Note:
Note:
The Intel Core™2 Extreme processor QX9770 requires a special liquid cooling thermal
solution. It will not be offered with the processor. Refer to the appropriate Thermal and
Mechanical Design Guidelines (see Section 1.2) for further guidance.
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed
processor.
Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the appropriate Thermal and Mechanical Design
Guidelines (See Section 1.2) for further guidance. Contact your local Intel Sales
Representative for this document.
Figure 7-1. Mechanical Representation of the Boxed Processor
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
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7.2
Mechanical Specifications
7.2.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 7-2 (Side View), and Figure 7-3 (Top
View). The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 7-7 and Figure 7-8. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 7-2. Space Requirements for the Boxed Processor (side view)
95.0
[3.74]
81.3
[3.2]
10.0
[0.39]
25.0
[0.98]
Figure 7-3. Space Requirements for the Boxed Processor (top view)
95.0
[3.74]
95.0
[3.74]
NOTES:
1.
Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
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Figure 7-4. Space Requirements for the Boxed Processor (overall view)
7.2.2
7.2.3
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5
and the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2) for
details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
7.3
Electrical Requirements
7.3.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 7-5. Baseboards
must provide a matched power header to support the boxed processor. Table 7-1
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses
at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the
connector labeled as CONTROL.
The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.
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The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 7-6 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned within 110 mm [4.33 inches] from the center of the
processor socket.
Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description
Signal
Pin
Straight square pin, 4-pin terminal housing with
polarizing ribs and friction locking ramp.
1
2
3
4
GND
+12 V
0.100" pitch, 0.025" square pin width.
SENSE
CONTROL
Match with straight pin, friction lock header on
mainboard.
3
2
4
1
Table 7-1.
Fan Heatsink Power and Signal Specifications
Description
Min
Typ
Max
Unit
Notes
+12 V: 12 volt fan power supply
11.4
12
12.6
-
V
IC:
- Maximum fan steady-state current draw
- Average fan steady-state current draw
- Maximum fan start-up current draw
—
—
—
—
1.2
0.5
2.2
1.0
—
—
—
—
A
A
A
-
- Fan start-up current draw maximum
duration
Second
pulses per
fan
1
SENSE: SENSE frequency
—
2
—
revolution
2, 3
CONTROL
21
25
28
kHz
NOTES:
1. Baseboard should pull this pin up to 5 V with a resistor.
2. Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
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7.4
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the
boxed processor.
7.4.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is in Chapter 5. The boxed processor fan heatsink is able to
keep the processor temperature within the specifications (see Table 5-1) in chassis that
provide good thermal management. For the boxed processor fan heatsink to operate
properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow
of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace
is required around the fan to ensure that the airflow through the fan heatsink is not
blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and
decreases fan life. Figure 7-7 and Figure 7-8 illustrate an acceptable airspace clearance
for the fan heatsink. The air temperature entering the fan should be kept below 38 ºC.
Again, meeting the processor's temperature specification is the responsibility of the
system integrator.
Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)
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7.4.2
Variable Speed Fan
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin
motherboard header it will operate as follows:
The boxed processor fan will operate at different speeds over a short range of internal
chassis temperatures. This allows the processor fan to operate at a lower speed and
noise level, while internal chassis temperatures are low. If internal chassis
temperature increases beyond a lower set point, the fan speed will rise linearly with
the internal temperature until the higher set point is reached. At that point, the fan
speed is at its maximum. As fan speed increases, so does fan noise levels. Systems
should be designed to provide adequate air around the boxed processor fan heatsink
that remains cooler then lower set point. These set points, represented in Figure 7-9
and Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The
internal chassis temperature should be kept below 38 ºC. Meeting the processor's
temperature specification (see Chapter 5) is the responsibility of the system
integrator.
The motherboard must supply a constant +12 V to the processor's power header to
ensure proper operation of the variable speed fan for the boxed processor. Refer to
Table 7-1 for the specific requirements.
Figure 7-9. Boxed Processor Fan Heatsink Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
Table 7-2.
Fan Heatsink Power and Signal Specifications
Boxed Processor
Fan Heatsink Set
Point (°C)
Boxed Processor Fan Speed
Notes
When the internal chassis temperature is below or equal to this
set point, the fan operates at its lowest speed. Recommended
maximum internal chassis temperature for nominal operating
environment.
1
X ≤ 30
When the internal chassis temperature is at this point, the fan
operates between its lowest and highest speeds. Recommended
maximum internal chassis temperature for worst-case operating
environment.
Y = 35
-
-
When the internal chassis temperature is above or equal to this
set point, the fan operates at its highest speed.
Z ≥ 39
NOTES:
1. Set point variance is approximately ±1 °C from fan heatsink to fan heatsink.
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If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin
motherboard header and the motherboard is designed with a fan speed controller with
PWM output (CONTROL see Table 7-1) and remote thermal diode measurement
capability the boxed processor will operate as follows:
As processor power has increased the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.
The 4th wire PWM solution provides better control over chassis acoustics. This is
achieved by more accurate measurement of processor die temperature through the
processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the
use of an ASIC located on the motherboard that sends out a PWM control signal to the
4th pin of the connector labeled as CONTROL. The fan speed is based on actual
processor temperature instead of internal ambient chassis temperatures.
If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard
processor fan header it will default back to a thermistor controlled mode, allowing
compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode,
the fan RPM is automatically varied based on the Tinlet temperature measured by a
thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed
control see the appropriate Thermal and Mechanical Design Guidelines (See
Section 1.2).
7.5
Boxed Intel® Core™2 Extreme Processor QX9650
Specifications
This section documents the mechanical specifications of the Boxed Intel® Core™2
Extreme processor QX9650. The boxed processor will be shipped with an unattached
fan heatsink. Figure 7-10 shows a mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 7-3 (top view), and Figure 7-4 (side view).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 7-11 and Figure 7-12. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Note:
The Boxed Intel® Core™2 Extreme processor QX9650 cooling solution violates the
boxed processor keep out zones. This is done intentionally, and with the understanding
that Extreme Edition systems will be integrated into larger capacity chassis.
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Figure 7-10. Space Requirements for the Boxed Processor (side view)
7.5.1
Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink
Weight
The Boxed Intel® Core™2 Extreme processor QX9650 fan heatsink weight will complies
with the socket specifications. See Chapter 5 and the appropriate Thermal and
Mechanical Design Guidelines (See Section 1.2) for details on the processor weight and
heatsink requirements.
Figure 7-11. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
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Figure 7-12. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)
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Debug Tools Specifications
8 Debug Tools Specifications
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Intel® Core™2 Extreme processor QX9000 series, Intel®
Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series systems.
Tektronix and Agilent should be contacted to get specific information about their logic
analyzer interfaces. The following information is general in nature. Specific information
must be obtained from the logic analyzer vendor.
Due to the complexity of processor systems, the LAI is critical in providing the ability to
probe and capture FSB signals. There are two sets of considerations to keep in mind
when designing a processor system that can make use of an LAI: mechanical and
electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug
into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection
between the processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be
obtained from the logic analyzer vendor. System designers must make sure that the
keepout volume remains unobstructed inside the system. Note that it is possible that
the keepout volume reserved for the LAI may differ from the space normally occupied
by the processors heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic
analyzer vendor for electrical specifications and load models for the LAI solution it
provides.
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