BX80574E5410P [INTEL]
Microprocessor, CMOS, PBGA771, 37.5 X 37.5 MM, LGA-771;
| 型号： | BX80574E5410P |
| 厂家： | 
INTEL |
| 描述： | Microprocessor, CMOS, PBGA771, 37.5 X 37.5 MM, LGA-771 |
| 文件： | 总124页 (文件大小：3230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Core Intel® Xeon® Processor
5400 Series
Datasheet
August 2008
318589-005
®
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Quad-Core Intel® Xeon® Processor 5400 Series may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
®
drivers and applications enabled for Intel 64 architecture. Processors will not operate (including 32-bit operation) without an
®
Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult
with your system vendor for more information.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Xeon, Intel SpeedStep Technology, Intel Core, and the Intel logo are trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007-2008, Intel Corporation.
2
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
Contents
1
Introduction..............................................................................................................9
1.1
1.2
1.3
Terminology ..................................................................................................... 10
State of Data.................................................................................................... 13
References ....................................................................................................... 13
2
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications................ 15
2.1
2.2
2.3
Front Side Bus and GTLREF ................................................................................ 15
Power and Ground Lands.................................................................................... 16
Decoupling Guidelines........................................................................................ 16
2.3.1 VCC Decoupling...................................................................................... 16
2.3.2 VTT Decoupling...................................................................................... 16
2.3.3 Front Side Bus AGTL+ Decoupling ............................................................ 16
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking....................................... 17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]).................................. 17
2.4.2 PLL Power Supply................................................................................... 18
Voltage Identification (VID) ................................................................................ 18
Reserved, Unused, and Test Signals..................................................................... 21
Front Side Bus Signal Groups.............................................................................. 22
CMOS Asynchronous and Open Drain Asynchronous Signals.................................... 24
Test Access Port (TAP) Connection....................................................................... 24
2.4
2.5
2.6
2.7
2.8
2.9
2.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 24
2.10.1 DC Characteristics.................................................................................. 24
2.10.2 Input Device Hysteresis .......................................................................... 25
2.11 Mixing Processors.............................................................................................. 26
2.12 Absolute Maximum and Minimum Ratings ............................................................. 26
2.13 Processor DC Specifications ................................................................................ 27
2.13.1 Flexible Motherboard Guidelines (FMB)...................................................... 27
2.13.2 VCC Overshoot Specification.................................................................... 38
2.13.3 Die Voltage Validation............................................................................. 39
2.14 AGTL+ FSB Specifications................................................................................... 39
3
Mechanical Specifications........................................................................................ 43
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Package Mechanical Drawings ............................................................................. 43
Processor Component Keepout Zones................................................................... 47
Package Loading Specifications ........................................................................... 47
Package Handling Guidelines............................................................................... 48
Package Insertion Specifications.......................................................................... 48
Processor Mass Specifications ............................................................................. 48
Processor Materials............................................................................................ 48
Processor Markings............................................................................................ 48
Processor Land Coordinates................................................................................ 49
4
Land Listing............................................................................................................. 51
4.1
Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments ........................... 51
4.1.1 Land Listing by Land Name...................................................................... 51
4.1.2 Land Listing by Land Number................................................................... 61
5
6
Signal Definitions .................................................................................................... 71
5.1 Signal Definitions .............................................................................................. 71
Thermal Specifications ............................................................................................ 79
6.1
Package Thermal Specifications........................................................................... 79
6.1.1 Thermal Specifications ............................................................................ 79
6.1.2 Thermal Metrology ................................................................................. 90
Processor Thermal Features................................................................................ 90
6.2
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
3
6.2.1 Intel® Thermal Monitor Features...............................................................90
6.2.2 On-Demand Mode...................................................................................92
6.2.3 PROCHOT# Signal ..................................................................................93
6.2.4 FORCEPR# Signal ...................................................................................93
6.2.5 THERMTRIP# Signal................................................................................94
Platform Environment Control Interface (PECI) ......................................................94
6.3.1 Introduction...........................................................................................94
6.3.2 PECI Specifications .................................................................................96
6.3
7
Features ..................................................................................................................97
7.1
7.2
Power-On Configuration Options ..........................................................................97
Clock Control and Low Power States.....................................................................97
7.2.1 Normal State .........................................................................................98
7.2.2 HALT or Extended HALT State...................................................................98
7.2.3 Stop-Grant State ..................................................................................100
7.2.4 Extended HALT Snoop or HALT Snoop State,
Stop Grant Snoop State.........................................................................101
Enhanced Intel SpeedStep® Technology.............................................................101
7.3
8
Boxed Processor Specifications..............................................................................103
8.1
8.2
Introduction....................................................................................................103
Mechanical Specifications..................................................................................105
8.2.1 Boxed Processor Heat Sink Dimensions (CEK)...........................................105
8.2.2 Boxed Processor Heat Sink Weight..........................................................113
8.2.3 Boxed Processor Retention Mechanism and Heat Sink
Support (CEK)......................................................................................113
Electrical Requirements ....................................................................................113
8.3.1 Fan Power Supply (Active CEK)...............................................................113
8.3.2 Boxed Processor Cooling Requirements....................................................114
Boxed Processor Contents.................................................................................115
8.3
8.4
9
Debug Tools Specifications ....................................................................................117
9.1
9.2
Debug Port System Requirements......................................................................117
Target System Implementation..........................................................................117
9.2.1 System Implementation.........................................................................117
Logic Analyzer Interface (LAI) ...........................................................................117
9.3.1 Mechanical Considerations .....................................................................118
9.3.2 Electrical Considerations........................................................................118
9.3
4
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
Figures
2-1
2-2
2-3
2-4
2-5
2-6
2-7
Input Device Hysteresis ..................................................................................... 25
Quad-Core Intel® Xeon® Processor X5482 Load Current versus Time...................... 30
Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time ............ 31
Quad-Core Intel® Xeon® Processor E5400 Series Load Current versus Time............. 31
Quad-Core Intel® Xeon® Processor L5400 Series Load Current versus Time............. 32
VCC Static and Transient Tolerance Load Lines...................................................... 34
Quad-Core Intel® Xeon® Processor X5482 VCC Static and
Transient Tolerance Load Lines ........................................................................... 35
2-8
2-9
Quad-Core Intel® Xeon® Processor X5400 Series VCC Static and
Transient Tolerance Load Lines ........................................................................... 36
Quad-Core Intel® Xeon® Processor E5400 Series VCC Static and
Transient Tolerance Load Lines ........................................................................... 36
2-10 Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient
Tolerance Load Lines ......................................................................................... 37
2-11 VCC Overshoot Example Waveform...................................................................... 39
2-12 Electrical Test Circuit ......................................................................................... 41
2-13 Differential Clock Waveform................................................................................ 41
2-14 Differential Clock Crosspoint Specification............................................................. 42
2-15 Differential Rising and Falling Edge Rates ............................................................. 42
3-1
3-2
3-3
3-4
3-5
3-6
3-7
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
7-1
8-1
Processor Package Assembly Sketch .................................................................... 43
Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 of 3)...... 44
Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 2 of 3)...... 45
Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 3 of 3)...... 46
Processor Top-side Markings (Example)................................................................ 49
Processor Land Coordinates, Top View.................................................................. 49
Processor Land Coordinates, Bottom View............................................................. 50
Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile ......... 81
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profiles A and B.............. 83
Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile ........................... 86
Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile............................ 87
Quad-Core Intel® Xeon® Processor L5408 Thermal Profile ..................................... 89
Case Temperature (TCASE) Measurement Location ................................................ 90
Intel® Thermal Monitor 2 Frequency and Voltage Ordering ..................................... 92
Quad-Core Intel® Xeon® Processor 5400 Series PECI Topology .............................. 94
Conceptual Fan Control Diagram of PECI-based Platforms....................................... 95
Stop Clock State Machine ................................................................................. 100
Boxed Quad-Core Intel® Xeon® Processor 5400 Series
1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) .................... 104
Boxed Quad-Core Intel® Xeon® Processor 5400 Series 2U Passive Heat Sink ......... 104
2U Passive Quad-Core Intel® Xeon® Processor 5400 Series
8-2
8-3
Thermal Solution (Exploded View) ..................................................................... 105
Top Side Board Keepout Zones (Part 1).............................................................. 106
Top Side Board Keepout Zones (Part 2).............................................................. 107
Bottom Side Board Keepout Zones..................................................................... 108
Board Mounting-Hole Keepout Zones ................................................................. 109
Volumetric Height Keep-Ins .............................................................................. 110
4-Pin Fan Cable Connector (For Active CEK Heat Sink) ......................................... 111
8-4
8-5
8-6
8-7
8-8
8-9
8-10 4-Pin Base Board Fan Header (For Active CEK Heat Sink)...................................... 112
8-11 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution ....................... 114
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
5
Tables
1-1
Quad-Core Intel® Xeon® Processor 5400 Series ...................................................10
Core Frequency to FSB Multiplier Configuration......................................................17
BSEL[2:0] Frequency Table.................................................................................18
Voltage Identification Definition ...........................................................................20
Loadline Selection Truth Table for LL_ID[1:0]........................................................21
Market Segment Selection Truth Table for MS_ID[1:0] ...........................................21
FSB Signal Groups .............................................................................................22
AGTL+ Signal Description Table...........................................................................23
Non AGTL+ Signal Description Table.....................................................................23
Signal Reference Voltages...................................................................................23
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 PECI DC Electrical Limits.....................................................................................25
2-11 Processor Absolute Maximum Ratings...................................................................27
2-12 Voltage and Current Specifications.......................................................................28
2-13 Quad-Core Intel® Xeon® Processor X5482 VCC Static and
Transient Tolerance............................................................................................32
2-14 Quad-Core Intel® Xeon® Processor X5400 Series,
Quad-Core Intel® Xeon® Processor E5400 Series,
Quad-Core Intel® Xeon® Processor L5400 Series
VCC Static and Transient Tolerance......................................................................33
2-15 AGTL+ Signal Group DC Specifications..................................................................37
2-16 CMOS Signal Input/Output Group and TAP Signal Group
DC Specifications...............................................................................................38
2-17 Open Drain Output Signal Group DC Specifications.................................................38
2-18 VCC Overshoot Specifications..............................................................................38
2-19 AGTL+ Bus Voltage Definitions ............................................................................40
2-20 FSB Differential BCLK Specifications .....................................................................40
3-1
3-2
3-3
4-1
4-2
5-1
6-1
Package Loading Specifications............................................................................47
Package Handling Guidelines...............................................................................48
Processor Materials ............................................................................................48
Land Listing by Land Name .................................................................................51
Land Listing by Land Number ..............................................................................61
Signal Definitions...............................................................................................71
Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step) Thermal
Specifications....................................................................................................81
Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table .82
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Specifications .................83
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table ................84
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile B Table ................85
Quad-Core Intel® Xeon® Processor E5400 Series Thermal Specifications..................85
Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile Table ...................86
Quad-Core Intel® Xeon® Processor L5400 Series Thermal Specifications..................87
Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile Table....................88
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10 Quad-Core Intel® Xeon® Processor L5408 Thermal Specifications ...........................88
6-11 Quad-Core Intel® Xeon® Processor L5408 Thermal Profile Table .............................89
6-12 GetTemp0() GetTemp1()Error Codes....................................................................96
7-1
7-2
8-1
8-2
8-3
Power-On Configuration Option Lands...................................................................97
Extended HALT Maximum Power..........................................................................99
PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution................114
Fan Specifications for 4-Pin Active CEK Thermal Solution.......................................114
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution........................114
6
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
Revision History
Revision
Description
Date
001
002
Initial release
November 2007
Added product information for the Quad-Core Intel® Xeon®
Processor L5408.
March 2008
April 2008
Added product information for the Quad-Core Intel® Xeon®
Processor L5400 Series.
003
004
Corrected L1 cache size
Introduced X5492
Updated X5482 power levels on E-step
August 2008
August 2008
Maintains change bars from version 004.
Denoted in the Introduction section that E-step of the X5482 falls
into the 120W X5400 family.
005
Added X5492 processor to Table 7-1 and in Introduction section.
§
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
7
8
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet
1 Introduction
The Quad-Core Intel® Xeon® Processor 5400 Series is a server/workstation processor
utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The
processor is manufactured on Intel’s 45 nanometer process technology combining high
performance with the power efficiencies of a low-power microarchitecture. The Quad-
Core Intel® Xeon® Processor 5400 Series maintains the tradition of compatibility with
IA-32 software. Some key features include on-die, primary 32-kB instruction cache and
32-kB write-back data cache in each core and 12 MB (2 x 6MB) Level 2 cache with
Intel® Advanced Smart Cache architecture. The processors’ Data Prefetch Logic
speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting
in reduced effective bus latency and improved performance. The 1066 MHz Front Side
Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making
8.5 GBytes per second data transfer rates possible. The 1333 MHz Front Side Bus (FSB)
is a quad-pumped bus running off a 333 MHz system clock making 10.66 GBytes per
second data transfer rates possible. The 1600 MHz Front Side Bus (FSB) is a quad-
pumped bus running off a 400 MHz system clock making 12.80 GBytes per second data
transfer rates possible.
Enhanced thermal and power management capabilities are implemented including
Intel® Thermal Monitor 1, Intel® Thermal Monitor 2 and Enhanced Intel SpeedStep®
Technology. These technologies are targeted for dual processor configurations in
enterprise environments. Intel® Thermal Monitor 1 and Intel® Thermal Monitor
provide efficient and effective cooling in high temperature situations. Enhanced Intel
SpeedStep Technology provides power management capabilities to servers and
workstations.
Quad-Core Intel® Xeon® Processor 5400 Series features include Intel® Wide Dynamic
Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions
2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Streaming SIMD Extensions 4.1
(SSE4.1). Advanced Dynamic Execution improves speculative execution and branch
prediction internal to the processor. The floating point and multi-media units include
128-bit wide registers and a separate register for data movement. SSE3 instructions
provide highly efficient double-precision floating point, SIMD integer, and memory
management operations.
The Quad-Core Intel® Xeon® Processor 5400 Series support Intel® 64 Architecture as
an enhancement to Intel's IA-32 architecture. This enhancement allows the processor
to execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details on Intel® 64 Architecture and its programming
model can be found in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, at http://www.intel.com/products/processor/manuals/.
In addition, the Quad-Core Intel® Xeon® Processor 5400 Series supports the Execute
Disable Bit functionality. When used in conjunction with a supporting operating system,
Execute Disable allows memory to be marked as executable or non executable. This
feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. Further details on
Execute Disable can be found at http://www.intel.com/cd/ids/developer/asmo-
na/eng/149308.htm.
The Quad-Core Intel® Xeon® Processor 5400 Series support Intel® Virtualization
Technology for hardware-assisted virtualization within the processor. Intel Virtualization
Technology is a set of hardware enhancements that can improve virtualization
9
solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine
Monitor software enabling multiple, independent software environments inside a single
platform. Further details on Intel Virtualization Technology can be found at
http://developer.intel.com/technology/platform-technology/virtualization/index.htm.
The Quad-Core Intel® Xeon® Processor 5400 Series is intended for high performance
server and workstation systems. The Quad-Core Intel® Xeon® Processor 5400 Series
supports a Dual Independent Bus (DIB) architecture with one processor on each bus,
up to two processor sockets in a system. The DIB architecture provides improved
performance by allowing increased FSB speeds and bandwidth. The Quad-Core Intel®
Xeon® Processor 5400 Series will be packaged in an FC-LGA Land Grid Array package
with 771 lands for improved power delivery. It utilizes a surface mount LGA771 socket
that supports Direct Socket Loading (DSL).
Table 1-1.
Quad-Core Intel® Xeon® Processor 5400 Series
# of
Processor
Cores
L2 Advanced
Cache
Front Side Bus
Frequency
L1 Cache
Package
4
2x6 MB shared
1600 MHz
1333 MHz
1066 MHz
FC-LGA
771 Lands
32 KB instruction per core
32 KB data per core
The Quad-Core Intel® Xeon® Processor 5400 Series-based platforms implement
independent core voltage (VCC) power planes for each processor. FSB termination
voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the Quad-Core Intel® Xeon® Processor 5400
Series including Flexible Motherboard Guidelines (FMB) (see Section 2.13.1). Refer to
the appropriate platform design guidelines for implementation details.
The Quad-Core Intel® Xeon® Processor 5400 Series supports either 1066 MHz,
1333 MHz, or 1600 MHz Front Side Bus operations. The FSB utilizes a split-transaction,
deferred reply protocol and Source-Synchronous Transfer (SST) of address and data to
improve performance. The processor transfers data four times per bus clock (4X data
transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver
addresses two times per bus clock and is referred to as a ‘double-clocked’ or a 2X
address bus. In addition, the Request Phase completes in one clock cycle. The FSB is
also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
10
Commonly used terms are explained here for clarification:
• Quad-Core Intel® Xeon® Processor 5400 Series - Intel 64-bit microprocessor
intended for dual processor servers and workstations based on Intel’s 45
nanometer process, in the PC-LGA 771 package with four processor cores. For this
document “processors” is used as the generic term for the “Quad-Core Intel®
Xeon® Processor 5400 Series”. The term ‘processors’ and “Quad-Core Intel®
Xeon® Processor 5400 Series” are inclusive of Quad-Core Intel® Xeon® Processor
X5482, Quad-Core Intel® Xeon® Processor X5400 Series, Quad-Core Intel®
Xeon® Processor E5400 Series, and Quad-Core Intel® Xeon® Processor L5400
Series.
• Quad-Core Intel® Xeon® Processor X5492– An ultra performance version of
the Quad-Core Intel® Xeon® Processor 5400 Series. For this document “Quad-
Core Intel® Xeon® Processor X5492” is used to call out specifications that are
unique to the Quad-Core Intel® Xeon® Processor X5492 SKU.
• Quad-Core Intel® Xeon® Processor X5482– An ultra performance version of
the Quad-Core Intel® Xeon® Processor 5400 Series. For this document “Quad-
Core Intel® Xeon® Processor X5482” is used to call out specifications that are
unique to the Quad-Core Intel® Xeon® Processor X5482 SKU. E-step version of
the X5482 falls into the X5400 family specifications
• Quad-Core Intel® Xeon® Processor X5400 Series - An accelerated
performance version of the Quad-Core Intel® Xeon® Processor X5400 Series. For
this document “Quad-Core Intel® Xeon® Processor X5400 Series” is used to call
out specifications that are unique to the Quad-Core Intel® Xeon® Processor X5400
Series SKU.
• Quad-Core Intel® Xeon® Processor E5400 Series – A mainstream
performance version of the Quad-Core Intel® Xeon® Processor X5400 Series. For
this document “Quad-Core Intel® Xeon® Processor E5400 Series” is used to call
out specifications that are unique to the Quad-Core Intel® Xeon® Processor E5400
Series SKU.
• Quad-Core Intel® Xeon® Processor L5400 Series - Intel 64-bit
microprocessor intended for dual processor server blades and embedded servers.
The Quad-Core Intel® Xeon® Processor L5400 Series is a lower voltage and lower
power version of the Quad-Core Intel® Xeon® Processor 5400 Series. For this
document “Quad-Core Intel® Xeon® Processor L5400 Series” is used to call out
specifications that are unique to the Quad-Core Intel® Xeon® Processor L5400
Series SKU.
• Quad-Core Intel® Xeon® Processor L5408 - Intel 64-bit microprocessor
intended for dual processor server blades and embedded servers. The Quad-Core
Intel® Xeon® Processor L5408 is a lower voltage and lower power version of the
Quad-Core Intel® Xeon® Processor 5400 Series supporting higher case
temperatures. It supports a Thermal Profile with nominal and short-term conditions
designed to meet Network Equipment Building System (NEBS) level 3 compliance.
For this document “Quad-Core Intel® Xeon® Processor L5408” is used to call out
specifications that are unique to the Quad-Core Intel® Xeon® Processor L5408
SKU.
• FC-LGA (Flip Chip Land Grid Array) Package – The Quad-Core Intel® Xeon®
Processor 5400 Series package is a Land Grid Array, consisting of a processor core
mounted on a pinless substrate with 771 lands, and includes an integrated heat
spreader (IHS).
• LGA771 socket – The Quad-Core Intel® Xeon® Processor 5400 Series interfaces
to the baseboard through this surface mount, 771 Land socket. See the LGA771
Socket Design Guidelines for details regarding this socket.
11
• Processor core – Processor core with integrated L1 cache. L2 cache and system
bus interface are shared between the two cores on the die. All AC timing and signal
integrity specifications are at the pads of the system bus interface.
• Front Side Bus (FSB) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions, as well as interrupt messages, pass between the
processor and chipset over the FSB.
• Dual Independent Bus (DIB) – A front side bus architecture with one processor
on each of several processor buses, rather than a processor bus shared between
two processor agents. The DIB architecture provides improved performance by
allowing increased FSB speeds and bandwidth.
• Flexible Motherboard Guidelines (FMB) – Estimate of the maximum values the
Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time
periods. Actual specifications for future processors may differ.
• Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
• Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any clocks.
Upon exposure to “free air” (that is, unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.
• Symmetric Agent – A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
Multiprocessing (SMP) systems.
• Integrated Heat Spreader (IHS) – A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Thermal Design Power (TDP) – Processor thermal solutions should be designed
to meet this target. It is the highest expected sustainable power while running
known power intensive applications. TDP is not the maximum power that the
processor can dissipate.
• Intel®64 Architecture – An enhancement to Intel's IA-32 architecture that allows
the processor to execute operating systems and applications written to take
advantage of the 64-bit extension technology.
• Enhanced Intel SpeedStep® Technology – Technology that provides power
management capabilities to servers and workstations.
• Platform Environment Control Interface (PECI) – A proprietary one-wire bus
interface that provides a communication channel between Intel processor and
external thermal monitoring devices, for use in fan speed control. PECI
communicates readings from the processor’s digital thermometer. PECI replaces
the thermal diode available in previous processors.
• Intel® Virtualization Technology – Processor virtualization, which when used in
conjunction with Virtual Machine Monitor software enables multiple, robust
independent software environments inside a single platform.
12
• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that
interfaces with a card edge socket and supplies the correct voltage and current to
the processor based on the logic state of the processor VID bits.
• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto
the system board that provides the correct voltage and current to the processor
based on the logic state of the processor VID bits.
• VCC – The processor core power supply.
• VSS – The processor ground.
• VTT – FSB termination voltage.
1.2
1.3
State of Data
The data contained within this document is the most accurate information available by
the publication date of this document.
References
Material and concepts available in the following documents may be beneficial when
reading this document:
Document
Document
Notes
1
Number
®
AP-485, Intel Processor Identification and the CPUID Instruction
241618
2
2
®
Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1
Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A
Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B
Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A
253665
253666
253667
253668
253669
®
®
®
®
Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B
®
®
Intel 64 and IA-32 Intel Architectures Optimization Reference Manual
248966
252046
2
2
®
®
Intel 64 and IA-32 Intel Architectures Software Developer's Manual
Documentation Changes
Quad-Core Intel® Xeon® Processor 5400 Series Specification Update
318585
315889
2
2
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
11.0 Design Guidelines
Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design
Guidelines (TMDG)
318611
1
LGA771 Socket Mechanical Design Guide
313871
318587
2
2
Quad-Core Intel® Xeon® Processor 5400 Series Boundary Scan Descriptive
Language (BSDL) Model
Notes:
1.
2.
Contact your Intel representative for the latest revision of these documents
Document is available publicly at http://developer.intel.com.
§
13
14
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
2 Quad-Core Intel® Xeon®
Processor 5400 Series Electrical
Specifications
2.1
Front Side Bus and GTLREF
Most Quad-Core Intel® Xeon® Processor 5400 Series FSB signals use Assisted
Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides
improved noise margins and reduced ringing through low voltage swings and controlled
edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the
high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with
the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during
the first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as VTT. Because platforms implement separate
power planes for each processor (and chipset), separate VCC and VTT supplies are
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families. Design guidelines for the processor FSB are detailed
in the appropriate platform design guidelines (refer to Section 1.3).
The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END) which are used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and
GTLREF_DATA_END is used for the 4X front side bus signaling group and
GTLREF_ADD_MID and GTLREF_ADD_END is used for the 2X and common clock front
side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See
Table 2-19 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and
GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines
for details. Termination resistors (RTT) for AGTL+ signals are provided on the processor
silicon and are terminated to VTT. The on-die termination resistors are always enabled
on the Quad-Core Intel® Xeon® Processor 5400 Series to control reflections on the
transmission line. Intel chipsets also provide on-die termination, thus eliminating the
need to terminate the bus on the baseboard for most AGTL+ signals.
Some FSB signals do not include on-die termination (RTT) and must be terminated on
the baseboard. See Table 2-8 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the Quad-Core
Intel® Xeon® Processor 5400 Series signal integrity models, which includes buffer and
package models.
15
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
2.2
2.3
Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 223 VCC (power)
and 267 VSS (ground) inputs. All VCC lands must be connected to the processor power
plane, while all VSS lands must be connected to the system ground plane. The
processor VCC lands must be supplied with the voltage determined by the processor
Voltage IDentification (VID) signals. See Table 2-3 for VID definitions.
Twenty two lands are specified as VTT, which provide termination for the FSB and
provides power to the I/O buffers. The platform must implement a separate supply for
these lands which meets the VTT specifications outlined in Table 2-12.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Quad-Core
Intel® Xeon® Processor 5400 Series is capable of generating large average current
swings between low and full power states. This may cause voltages on power planes to
sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage
(CBULK), such as electrolytic capacitors, supply voltage during longer lasting changes in
current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running
condition. Care must be taken in the baseboard design to ensure that the voltage
provided to the processor remains within the specifications listed in Table 2-12. Failure
to do so can result in timing violations or reduced lifetime of the component. For further
information and guidelines, refer to the appropriate platform design guidelines.
2.3.1
2.3.2
2.3.3
V Decoupling
CC
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large voltage swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in Table 2-12). For further information regarding power delivery, decoupling
and layout guidelines, refer to the appropriate platform design guidelines.
VTT Decoupling
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
Front Side Bus AGTL+ Decoupling
The Quad-Core Intel® Xeon® Processor 5400 Series integrates signal termination on
the die, as well as a portion of the required high frequency decoupling capacitance on
the processor package. However, additional high frequency capacitance must be added
to the baseboard to properly decouple the return currents from the FSB. Bulk
decoupling must also be provided by the baseboard for proper AGTL+ bus operation.
Decoupling guidelines are described in the appropriate platform design guidelines.
16
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
2.4
Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the Quad-Core Intel® Xeon®
Processor 5400 Series core frequency is a multiple of the BCLK[1:0] frequency. The
processor bus ratio multiplier is set during manufacturing. The default setting is for the
maximum speed of the processor. It is possible to override this setting using software
(see the Intel® 64 and IA-32 Architectures Software Developer’s Manual). This permits
operation at lower frequencies than the processor’s tested frequency.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core
frequencies lower than the maximum rated processor speed, refer to the Intel® 64 and
Intel® 64 and IA-32 Architectures Software Developer’s Manual.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC specifications for the BCLK[1:0] inputs are provided in
Table 2-20. These specifications must be met while also meeting signal integrity
requirements as outlined in Table 2-20. The Quad-Core Intel® Xeon® Processor 5400
Series utilizes differential clocks. Table 2-1 contains processor core frequency to FSB
multipliers and their corresponding core frequencies.
Table 2-1.
Core Frequency to FSB Multiplier Configuration
Core Frequency
with 400.000 MHz
Bus Clock
Core Frequency
with 333.333 MHz
Bus Clock
Core Frequency
with 266.666 MHz
Bus Clock
Core Frequency to
FSB Multiplier
Notes
1/6
1/7
2.40 GHz
2.80 GHz
3 GHz
2 GHz
1.60 GHz
1.87 GHz
2 GHz
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3 GHz
1/7.5
1/8
3.20 GHz
3.40 GHz
3.60 GHz
3.80 GHz
2.13 GHz
2.27 GHz
2.40 GHz
2.53 GHz
1/8.5
1/9
1/9.5
3.16 GHz
Notes:
1.
2.
3.
Individual processors operate only at or below the frequency marked on the package.
Listed frequencies are not necessarily committed production frequencies.
For valid processor core frequencies, see Quad-Core Intel® Xeon® Processor 5400 Series Specification
Update.
4.
The lowest bus ratio supported by the Quad-Core Intel® Xeon® Processor 5400 Series is 1/6.
2.4.1
Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs which must be pulled up to VTT, and are used
to select the FSB frequency. Please refer to Table 2-15 for DC specifications. Table 2-2
defines the possible combinations of the signals and the frequency associated with each
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
17
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-2.
BSEL[2:0] Frequency Table
BSEL2
BSEL1
BSEL0
Bus Clock Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66 MHz
Reserved
Reserved
Reserved
333.33 MHz
Reserved
400 MHz
Reserved
2.4.2
PLL Power Supply
An on-die PLL filter solution is implemented on the Quad-Core Intel® Xeon® Processor
5400 Series. The VCCPLL input is used for this configuration in Quad-Core Intel® Xeon®
Processor 5400 Series-based platforms. Please refer to Table 2-12 for DC
specifications. Refer to the appropriate platform design guidelines for decoupling and
routing guidelines.
2.5
Voltage Identification (VID)
The Voltage Identification (VID) specification for the Quad-Core Intel® Xeon®
Processor 5400 Series is defined by the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID
signals is the reference VR output voltage to be delivered to the processor Vcc pins.
VID signals are open drain outputs, which must be pulled up to VTT. Please refer to
Table 2-16 for the DC specifications for these signals. A voltage range is provided in
Table 2-12 and changes with frequency. The specifications have been set such that one
voltage regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Table 2-3.
The Quad-Core Intel® Xeon® Processor 5400 Series uses six voltage identification
signals, VID[6:1], to support automatic selection of power supply voltages. Table 2-3
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor
socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply
the voltage that is requested, the voltage regulator must disable itself. See the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details.
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the
Quad-Core Intel® Xeon® Processor 5400 Series; VID7 is always hard wired low at the
voltage regulator.
18
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate
while transitioning to an adjacent VID and its associated processor core voltage (VCC).
This will represent a DC shift in the load line. It should be noted that a low-to-high or
high-to-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Table 2-12 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-13 and Table 2-2.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Table 2-12 and Table 2-14. Refer to the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
19
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-3.
Voltage Identification Definition
HEX VID6 VID5 VID4 VID3 VID2 VID1
V
HEX VID6 VID5 VID4 VID3 VID2 VID1
V
CC_MAX
CC_MAX
7A
78
76
74
72
70
6E
6C
6A
68
66
64
62
60
5E
5C
5A
58
56
54
52
50
4E
4C
4A
48
46
44
42
40
3E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
3C
3A
38
36
34
32
30
2E
2C
2A
28
26
24
22
20
1E
1C
1A
18
16
14
12
10
0E
0C
0A
08
06
04
02
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1
OFF
Notes:
1.
2.
3.
When the “111111” VID pattern is observed, the voltage regulator output should be disabled.
Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5400 Series.
The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
®
Section 6.2.4), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep Technology transitions
(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications
Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is
received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until
power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines.
4.
20
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-4.
Table 2-5.
2.6
Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1
LL_ID0
Description
0
0
0
1
Reserved
®
®
Dual-Core Intel Xeon Processor 5100 series, Dual-Core Intel®
Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon®
Processor 5400 Series
1
1
0
1
Reserved
®
®
Quad-Core Intel Xeon processor 5300 series
Note: The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1
MS_ID0
Description
0
0
1
1
0
1
0
1
Dual-Core Intel® Xeon® Processor 5200 Series
Dual-Core Intel® Xeon® Processor 5100 series
Quad-Core Intel® Xeon® Processor 5300 series
Quad-Core Intel® Xeon® Processor 5400 Series
Note: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be
used for future processor compatibility or for keying.
Reserved, Unused, and Test Signals
All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs can be left unconnected; however, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noted in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (RTT). For details see Table 2-19.
TAP, CMOS Asynchronous inputs, and CMOS Asynchronous outputs do not include on-
die termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guidelines.
The TESTHI signals must be tied to the processor VTT using a matched resistor, where a
matched resistor has a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50Ω, then a value
between 40Ω and 60Ω is required.
21
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
The TESTHI signals must use individual pull-up resistors as detailed below. A matched
resistor must be used for each signal:
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12 - cannot be grouped with other TESTHI signals
2.7
Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference
levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the
AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+
asynchronous outputs can become active anytime and include an active PMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle. Table 2-6 identifies which signals are common
clock, source synchronous and asynchronous.
Table 2-6.
FSB Signal Groups (Sheet 1 of 2)
1
Signal Group
Type
Signals
AGTL+ Common Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#;
AGTL+ Common Clock Output
AGTL+ Common Clock I/O
Synchronous to
BCLK[1:0]
BPM4#, BPM[2:1]#, BPMb[2:1]#
2
2
Synchronous to
BCLK[1:0]
ADS#, AP[1:0]#, BINIT# , BNR# , BPM5#,
BPM3#, BPM0#,BPMb3#, BPMb0#, BR[1:0]#,
2
2
DBSY#, DP[3:0]#, DRDY#, HIT# , HITM# ,
2
LOCK#, MCERR#
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#, ADSTB0#
A[37:36]#
A[35:17]#
ADSTB1#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobes I/O
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Open Drain Output
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#, TDO
CMOS Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#,
STPCLK#
22
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-6.
FSB Signal Groups (Sheet 2 of 2)
1
Signal Group
Type
Signals
BSEL[2:0], VID[6:1]
CMOS Asynchronous Output
FSB Clock
Asynchronous
Clock
BCLK[1:0]
TAP Input
Synchronous to TCK
Synchronous to TCK
Power/Other
TCK, TDI, TMS, TRST#
TDO
TAP Output
Power/Other
COMP[3:0], GTLREF_ADD_MID,
GTLREF_ADD_END, GTLREF_DATA_MID,
GTLREF_DATA_END, LL_ID[1:0], MS_ID[1:0],
PECI, RESERVED, SKTOCC#, TESTIN1,
TESTIN2, TESTHI[12:10], V
,
CC
VCC_DIE_SENSE, VCC_DIE_SENSE2, VCCPLL,
VID_SELECT, VSS_DIE_SENSE,
VSS_DIE_SENSE2, V , V , VTT_OUT,
SS
TT
VTT_SEL
Notes:
1.
2.
Refer to Chapter 5 for signal descriptions.
These signals may be driven simultaneously by multiple agents (Wired-OR).
Table 2-7 outlines the signals which include on-die termination (RTT). Table 2-8 outlines
non AGTL+ signals including open drain signals. Table 2-9 provides signal reference
voltages.
Table 2-7.
AGTL+ Signal Description Table
AGTL+ signals with R
AGTL+ signals with no R
TT
TT
A[37:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BPM[5:0]#,BPMb[3:0]#, RESET#, BR[1:0]#
BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
Table 2-8.
Non AGTL+ Signal Description Table
Signals with R
Signals with no R
TT
TT
1
2
FORCEPR# , PROCHOT#
A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0],
FERR#/PBE#, GTLREF_ADD_MID, GTLREF_ADD_END,
GTLREF_DATA_MID, GTLREF_DATA_END, IERR#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LL_ID[1:0],
MS_ID[1:0], PECI, PWRGOOD, SKTOCC#, SMI#,
STPCLK#, TCK, TDI, TDO, TESTHI[12:8], THERMTRIP#,
TMS, TRDY#, TRST#, VCC_DIE_SENSE,
VCC_DIE_SENSE2, VID[6:1], VID_SELECT,
VSS_DIE_SENSE, VSS_DIE_SENSE2, VTT_SEL
Notes:
1.
2.
These signals have RTT in the package with a 80 Ω pullup to V .
TT
These signals have RTT in the package with a 50 Ω pullup to V .
TT
Table 2-9.
Signal Reference Voltages
GTLREF
CMOS
A[37:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#,
BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#, BR[1:0]#, PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST#
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#,
HIT#, HITM#, LOCK#, MCERR#, RESET#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
23
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
2.8
CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See Section 2.13 for the DC
specifications. See Chapter 6 for additional timing requirements for entering and
leaving the low power states.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain followed by any
other components within the system. A translation buffer should be used to connect to
the rest of the chain unless one of the other components is capable of accepting an
input of the appropriate voltage. Similar considerations must be made for TCK, TDO,
TMS, and TRST#. Two copies of each signal may be required with each driving a
different voltage level.
2.10
Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors and chipset components to external thermal monitoring
devices. The Quad-Core Intel® Xeon® Processor 5400 Series contains Digital Thermal
Sensor (DTS) sprinkled both inside and outside the cores in a die. These sensors are
implemented as analog-to-digital converters calibrated at the factory for reasonable
accuracy to provide a digital representation of relative processor temperature. PECI
provides an interface to relay the highest DTS temperature within a die to external
devices for thermal/fan speed control. More detailed information may be found in the
Platform Environment Control Interface (PECI) Specification.
2.10.1
DC Characteristics
The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical
specifications shown in Table 2-10 is used with devices normally operating from a VTT
interface supply. VTT nominal levels will vary between processor families. All PECI
devices will operate at the VTT level determined by the processor installed in the
system. For specific nominal VTT levels, refer to the appropriate processor EMTS.
24
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-10. PECI DC Electrical Limits
1
Symbol
Definition and Conditions
Min
Max
Units
Notes
V
Input Voltage Range
Hysteresis
-0.150
V
V
V
in
TT
V
0.1 * V
N/A
hysteresis
TT
Negative-edge threshold
voltage
V
V
0.275 * V
0.550 * V
-6.0
0.500 * V
V
V
n
TT
TT
TT
Positive-edge threshold
voltage
0.725 * V
N/A
p
TT
High level output source
I
mA
source
(V
= 0.75 * V )
OH
TT
Low level output sink
(V = 0.25 * V
I
0.5
1.0
50
mA
µA
sink
)
TT
OL
High impedance state leakage
to V
I
N/A
2
TT
leak+
(V
= V
)
OL
leak
High impedance leakage to
GND
I
N/A
N/A
10
µA
pF
2
3
leak-
(V
= V
)
leak
OH
C
Bus capacitance per node
10
bus
Signal noise immunity above
300 MHz
V
0.1 * V
N/A
V
p-p
noise
TT
Note:
1.
2.
3.
V
supplies the PECI interface. PECI behavior does not affect V min/max specifications.
T
T
T
T
The leakage specification applies to powered devices on the PECI bus.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
2.10.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design.
Figure 2-1. Input Device Hysteresis
VTT
Maximum VP
PECI High Range
Minimum VP
Maximum VN
Minimum
Hysteresis Signal Range
Valid Input
Minimum VN
PECI Ground
PECI Low Range
25
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
2.11
Mixing Processors
Intel supports and validates dual processor configurations only in which both
processors operate with the same FSB frequency, core frequency, power segments, and
have the same internal cache sizes. Mixing components operating at different internal
clock frequencies is not supported and will not be validated by Intel. Combining
processors from different power segments is also not supported.
Note:
Processors within a system must operate at the same frequency per bits [12:8] of the
CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated
due to thermal events, Extended HALT, Enhanced Intel SpeedStep Technology
transitions, or assertion of the FORCEPR# signal (See Chapter 6).
Not all operating systems can support dual processors with mixed frequencies. Mixing
processors of different steppings but the same model (as per CPUID instruction) is
supported. Details regarding the CPUID instruction are provided in the AP-485 Intel®
Processor Identification and the CPUID Instruction application note.
2.12
Absolute Maximum and Minimum Ratings
Table 2-11 specifies absolute maximum and minimum ratings only, which lie outside
the functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
26
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-11. Processor Absolute Maximum Ratings
1, 2
Symbol
Parameter
Min
Max
Unit
Notes
V
V
Core voltage with respect to V
-0.30
-0.30
1.35
1.45
V
V
CC
SS
FSB termination voltage with respect to V
TT
SS
T
Processor case temperature
See
Chapter 6
See
Chapter 6
°C
CASE
T
Storage temperature
-40
85
°C
3, 4, 5
STORAGE
Notes:
1.
2.
3.
For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Chapter 3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
4.
5.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long-term reliability of the processor.
2.13
Processor DC Specifications
The processor DC specifications in this section are defined at the processor die
(pads) unless noted otherwise. See Chapter 4 for the Quad-Core Intel® Xeon®
Processor 5400 Series land listings and Chapter 5 for signal definitions. Voltage and
current specifications are detailed in Table 2-12. For platform planning refer to
Table 2-13 and Table 2-14, which provides VCC static and transient tolerances. This
same information is presented graphically in Figure 2-8 and Figure 2-4.
The FSB clock signal group is detailed in Table 2-20. BSEL[2:0] and VID[6:1] signals
are specified in Table 2-15. The DC specifications for the AGTL+ signals are listed in
Table 2-16. Legacy signals and Test Access Port (TAP) signals follow DC specifications
similar to GTL+. The DC specifications for the PWRGOOD input and TAP signal group
are listed in Table 2-16.
Table 2-12 through Table 2-18 list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (TCASE as specified in Chapter 6,
“Thermal Specifications”), clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
2.13.1
Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time periods.
The values are only estimates and actual specifications for future processors may differ.
Processors may or may not have specifications equal to the FMB value in the
foreseeable future. System designers should meet the FMB values to ensure their
systems will be compatible with future Quad-Core Intel® Xeon® Processor 5400
Series.
27
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-12. Voltage and Current Specifications (Sheet 1 of 2)
1, 11
Symbol
VID
Parameter
Min
Typ
Max
Unit Notes
VID range
for processor core
0.850
1.3500
V
V
V
See Table 2-13 and Table 2-14;
Figure 2-7, Figure 2-8, Figure 2-9,
Figure 2-10
V
2, 3, 4, 6, 9
CC
CC
Launch - FMB
V
V
V
V
V
Default VCC Voltage for
initial power up
1.10
± 12.5
450
V
mV
mV
V
2
cc_boot
VID_STEP
VID_SHIFT
TT
VID step size during a
transition
Total allowable DC load line
shift from VID steps
10
8,13
FSB termination voltage (DC
+ AC specification)
1.045
1.455
1.10
1.155
1.605
150
PLL supply voltage (DC + AC
specification)
1.500
V
12
CCPLL
I
I
I
I
I
I
I
I
for Quad-Core Intel®
CC
A
4,5,6,9,18
CC
Xeon® Processor X5482 with
multiple VID
Launch - FMB
I
for Quad-Core Intel®
CC
125
102
60
A
A
A
A
A
A
4,5,6,9
4, 5, 6, 9
4,5,6,9
4,5,6,9
17,18
CC
Xeon® Processor X5400
Series with multiple VID
Launch - FMB
I
for Quad-Core Intel®
CC
CC
Xeon® Processor E5400
Series with multiple VID
Launch - FMB
I
for Quad-Core Intel®
CC
CC
Xeon® Processor L5400
Series with multiple VID
Launch - FMB
I
for Quad-Core Intel®
CC
48
CC
Xeon® Processor L5408 with
multiple VID
Launch - FMB
I
for Quad-Core
CC_RESET
150
125
CC_RESET
CC_RESET
Intel® Xeon® Processor
X5482 with multiple VID
Launch - FMB
I
for Quad-Core
17
CC_RESET
Intel® Xeon® Processor
X5400 Series with multiple
VID
Launch - FMB
I
I
I
I
for Quad-Core
CC_RESET
102
60
A
A
A
17
17
17
CC_RESET
CC_RESET
CC_RESET
Intel® Xeon® Processor
E5400 Series with multiple
VID Launch - FMB
I
for Quad-Core
CC_RESET
Intel® Xeon® Processor
L5400 Series with multiple
VID Launch - FMB
I
for Quad-Core
48
CC_RESET
Intel® Xeon® Processor
L5408 with multiple VID
Launch - FMB
28
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-12. Voltage and Current Specifications (Sheet 2 of 2)
1, 11
Symbol
Parameter
for V supply before V
CC
Min
Typ
Max
Unit Notes
I
I
I
I
8
A
A
A
15
TT
CC
TT
stable
for V supply after V
CC
I
CC
TT
7
stable
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor X5482
130
6,14,18
6,14
CC_TDC
CC_TDC
Launch - FMB
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor X5400
Series
110
80
Launch - FMB
I
I
I
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor E5400
Series
A
A
A
6,14
6,14
6,14
CC_TDC
CC_TDC
CC_TDC
Launch - FMB
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor L5400
Series
50
Launch - FMB
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor L5408
40
Launch - FMB
I
I
DC current that may be
580
200
mA
µA
16
7
CC_VTT_OUT
CC_GTLREF
drawn from V
per land
TT_OUT
I
for
CC
GTLREF_DATA_MID,
GTLREF_DATA_END,
GTLREF_ADD_MID, and
GTLREF_ADD_END
I
I
I
for PLL supply
260
150
mA
A
12
18
CC_VCCPLL
TCC
CC
I
for Quad-Core Intel®
CC
Xeon® Processor X5482
during active thermal control
circuit (TCC)
I
I
I
I
I
for Quad-Core Intel®
CC
125
102
60
A
A
A
A
TCC
TCC
TCC
TCC
Xeon® Processor X5400
Series during active thermal
control circuit (TCC)
I
for Quad-Core Intel®
CC
Xeon® Processor E5400
Series during active thermal
control circuit (TCC)
I
for Quad-Core Intel®
CC
Xeon® Processor L5400
Series during active thermal
control circuit (TCC)
I
for Quad-Core Intel®
48
CC
Xeon® Processor L5408
during active thermal control
circuit (TCC)
Notes:
1.
2.
Unless otherwise noted, all specifications in this table are based on final silicon characterization data.
These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.5 for more information.
29
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
3.
The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz
bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled
in the scope probe.
4.
5.
The processor must not be subjected to any static V level that exceeds the V
associated with any
CC
CC_MAX
particular current. Failure to adhere to this specification can shorten processor lifetime.
specification is based on maximum V loadline. Refer to Figure 2-7, Figure 2-8, Figure 2-9 and
I
CC_MAX
CC
Figure 2-10 for details. The processor is capable of drawing I
for up to 10 ms. Refer to Figure 2-1 for
CC_MAX
further details on the average processor current draw over various time durations.
FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See
Section 2.13.1 for further details on FMB guidelines.
This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END.
6.
7.
8.
9.
V
must be provided via a separate voltage source and must not be connected to V . This specification is
TT
CC
measured at the land.
Minimum V and maximum I are specified at the maximum processor case temperature (TCASE) shown
in Figure 6-2 and Figure 6-3.
CC
CC
10. This specification refers to the total reduction of the load line due to VID transitions below the specified
VID.
11. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
frequency may have different VID settings.
12. This specification applies to the VCCPLL land.
13. Baseboard bandwidth is limited to 20 MHz.
14.
I
is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and
CC_TDC
should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal
excursion. Please see the applicable design guidelines for further details. The processor is capable of
drawing I
indefinitely. Refer to Figure 2-1 for further details on the average processor current draw
CC_TDC
over various time durations. This parameter is based on design characterization and is not tested.
15. This is the maximum total current drawn from the V plane by only one processor with R enabled. This
TT
TT
specification does not include the current coming from on-board termination (R ), through the signal line.
Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine
the total I drawn by the system. This parameter is based on design characterization and is not tested.
TT
TT
16. ICC_VTT_OUT is specified at 1.1 V.
17.
I
is specified while PWRGOOD and RESET# are asserted.
CC_RESET
18. The Quad-Core Intel® Xeon® Processor X5482 is intended for dual processor workstations only.
.
Figure 2-2. Quad-Core Intel® Xeon® Processor X5482 Load Current versus Time
16 0
155
150
14 5
14 0
13 5
13 0
12 5
12 0
0 .0 1
0 .1
1
10
10 0
10 0 0
Time Duration (s)
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2.
Not 100% tested. Specified by design characterization.
30
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-3. Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time
13 0
12 5
12 0
115
110
10 5
10 0
0 .0 1
0 .1
1
10
10 0
10 0 0
Time Duration (s)
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2.
Not 100% tested. Specified by design characterization.
Figure 2-4. Quad-Core Intel® Xeon® Processor E5400 Series Load Current versus Time
10 5
10 0
9 5
9 0
8 5
8 0
75
0 .0 1
0 .1
1
10
10 0
10 0 0
Time Duration (s)
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2.
Not 100% tested. Specified by design characterization.
31
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-5. Quad-Core Intel® Xeon® Processor L5400 Series Load Current versus Time
70
65
60
55
50
45
40
0.01
0.1
1
10
100
1000
Time Duration (s)
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2.
Not 100% tested. Specified by design characterization.
Table 2-13. Quad-Core Intel® Xeon® Processor X5482 VCC Static and
Transient Tolerance (Sheet 1 of 2)
I
(A)
V
(V)
V
(V)
V (V)
CC_Min
Notes
CC
CC_Max
CC_Typ
0
VID - 0.000
VID - 0.006
VID - 0.013
VID - 0.019
VID - 0.025
VID - 0.031
VID - 0.038
VID - 0.044
VID - 0.050
VID - 0.056
VID - 0.063
VID - 0.069
VID - 0.075
VID - 0.081
VID - 0.087
VID - 0.094
VID - 0.100
VID - 0.106
VID - 0.113
VID - 0.119
VID - 0.125
VID - 0.131
VID - 0.138
VID - 0.144
VID - 0.010
VID - 0.016
VID - 0.023
VID - 0.029
VID - 0.035
VID - 0.041
VID - 0.048
VID - 0.054
VID - 0.060
VID - 0.066
VID - 0.073
VID - 0.079
VID - 0.085
VID - 0.091
VID - 0.097
VID - 0.104
VID - 0.110
VID - 0.116
VID - 0.123
VID - 0.129
VID - 0.135
VID - 0.141
VID - 0.148
VID - 0.154
VID - 0.020
VID - 0.026
VID - 0.033
VID - 0.039
VID - 0.045
VID - 0.051
VID - 0.058
VID - 0.064
VID - 0.070
VID - 0.076
VID - 0.083
VID - 0.089
VID - 0.095
VID - 0.101
VID - 0.108
VID - 0.114
VID - 0.120
VID - 0.126
VID - 0.133
VID - 0.139
VID - 0.145
VID - 0.151
VID - 0.158
VID - 0.164
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
32
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-13. Quad-Core Intel® Xeon® Processor X5482 VCC Static and
Transient Tolerance (Sheet 2 of 2)
I
(A)
V
(V)
V
(V)
V (V)
CC_Min
Notes
CC
CC_Max
CC_Typ
120
VID - 0.150
VID - 0.156
VID - 0.163
VID - 0.169
VID - 0.175
VID - 0.181
VID - 0.188
VID - 0.160
VID - 0.166
VID - 0.173
VID - 0.179
VID - 0.185
VID - 0.191
VID - 0.198
VID - 0.170
VID - 0.176
VID - 0.183
VID - 0.189
VID - 0.195
VID - 0.201
VID - 0.208
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
125
130
135
140
145
150
Notes:
1.
The V
and V
loadlines represent static and transient limits. Please see Section 2.13.2 for V
CC_MAX CC
CC_MIN
overshoot specifications.
This table is intended to aid in reading discrete points on Figure 2-7.
2.
3.
The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands
and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Table 2-14. Quad-Core Intel® Xeon® Processor X5400 Series,
Quad-Core Intel® Xeon® Processor E5400 Series,
Quad-Core Intel® Xeon® Processor L5400 Series
VCC Static and Transient Tolerance (Sheet 1 of 2)
I
(A)
V
(V)
V
(V)
V (V)
CC_Min
Notes
CC
CC_Max
CC_Typ
0
VID - 0.000
VID - 0.006
VID - 0.013
VID - 0.019
VID - 0.025
VID - 0.031
VID - 0.038
VID - 0.044
VID - 0.050
VID - 0.056
VID - 0.063
VID - 0.069
VID - 0.075
VID - 0.081
VID - 0.087
VID - 0.094
VID - 0.100
VID - 0.106
VID - 0.113
VID - 0.119
VID - 0.125
VID - 0.131
VID - 0.015
VID - 0.021
VID - 0.028
VID - 0.034
VID - 0.040
VID - 0.046
VID - 0.053
VID - 0.059
VID - 0.065
VID - 0.071
VID - 0.077
VID - 0.084
VID - 0.090
VID - 0.096
VID - 0.103
VID - 0.109
VID - 0.115
VID - 0.121
VID - 0.128
VID - 0.134
VID - 0.140
VID - 0.146
VID - 0.030
VID - 0.036
VID - 0.043
VID - 0.049
VID - 0.055
VID - 0.061
VID - 0.068
VID - 0.074
VID - 0.080
VID - 0.086
VID - 0.093
VID - 0.099
VID - 0.105
VID - 0.111
VID - 0.118
VID - 0.124
VID - 0.130
VID - 0.136
VID - 0.143
VID - 0.149
VID - 0.155
VID - 0.161
1, 2, 3
1, 2, 3
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 6
1, 2, 3, 6
1, 2, 3, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 5, 6
1, 2, 3, 4, 5, 6
33
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-14. Quad-Core Intel® Xeon® Processor X5400 Series,
Quad-Core Intel® Xeon® Processor E5400 Series,
Quad-Core Intel® Xeon® Processor L5400 Series
V
CC Static and Transient Tolerance (Sheet 2 of 2)
I
(A)
V
(V)
V
(V)
V (V)
CC_Min
Notes
CC
CC_Max
CC_Typ
110
VID - 0.138
VID - 0.144
VID - 0.150
VID - 0.156
VID - 0.153
VID - 0.159
VID - 0.165
VID - 0.171
VID - 0.168
VID - 0.174
VID - 0.180
VID - 0.186
1, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
115
120
125
Notes:
1.
The V
and V
loadlines represent static and transient limits. Please see Section 2.13.2 for V
CC_MIN
CC_MAX CC
overshoot specifications.
This table is intended to aid in reading discrete points on Figure 2-8 and Figure 2-9.
2.
3.
The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands
and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
4.
5.
6.
I
I
I
values greater than 102A are not applicable for the Quad-Core Intel® Xeon® Processor E5400 Series.
values greater than 60A are not applicable for the Quad-Core Intel® Xeon® Processor L5400 Series.
values greater than 48A are not applicable for the Quad-Core Intel® Xeon® Processor L5408.
CC
CC
CC
Figure 2-6. VCC Static and Transient Tolerance Load Lines
Icc [A]
0
5
10
15
20
25
30
35
40
45
50
VID - 0.000
VID - 0.010
VID - 0.020
VID - 0.030
VID - 0.040
VID - 0.050
VID - 0.060
VID - 0.070
VID - 0.080
VID - 0.090
VID - 0.100
Vcc
Maximum
VCC
Typical
Vcc
Minimum
34
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-7. Quad-Core Intel® Xeon® Processor X5482 VCC Static and
Transient Tolerance Load Lines
Icc [A]
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150
VID - 0.000
VID - 0.050
VID - 0.100
VID - 0.150
VID - 0.200
VID - 0.250
VCC
Maximum
VCC
Typical
VCC
Minimum
35
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-8. Quad-Core Intel® Xeon® Processor X5400 Series VCC Static and
Transient Tolerance Load Lines
Icc [A]
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
VID - 0.200
VCC
Maximum
VCC
Minimum
VCC
Typical
Figure 2-9. Quad-Core Intel® Xeon® Processor E5400 Series VCC Static and
Transient Tolerance Load Lines
Icc [A]
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95 100 105
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
VCC
Maximum
VCC
Typical
VCC
Minimum
36
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-10. Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient
Tolerance Load Lines
Icc [A]
0
5
10
15
20
25
30
35
40
45
50
55
60
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VCC
Maximum
VCC
Typical
VCC
Minimum
Notes:
1.
The V
and V
loadlines represent static and transient limits. Please see Section 2.13.2 for VCC
CC_MAX
CC_MIN
overshoot specifications.
2.
3.
4.
Refer to Table 2-12 for processor VID information.
Refer to Table 2-13 for V Static and Transient Tolerance
CC
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Table 2-15. AGTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
Input Low Voltage
Input High Voltage
Output High Voltage
Buffer On Resistance
Input Leakage Current
-0.10
0
GTLREF-0.10
V
V
2,4,6
3,6
4,6
5
IL
V
GTLREF+0.10
V
V +0.10
TT
IH
TT
V
R
V
-0.10
N/A
10.25
N/A
V
TT
V
OH
ON
TT
8.25
N/A
12.25
Ω
I
μA
7
± 100
LI
Notes:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
V
IL
value.
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
3.
4.
5.
6.
7.
V
IH
value.
and V
signal quality specifications.
This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
Measured at 0.31*V . R
GTLREF should be generated from V with a 1% tolerance resistor divider. The V referred to in these
specifications is the instantaneous V .
Specified when on-die R and R
V
may experience excursions above V . However, input signal drivers must comply with the
TT
IH
OH
(min) = 0.158*R . R
(typ) = 0.167*R . R
(max) = 0.175*R .
TT
ON
TT
ON
TT
ON TT
TT
TT
TT
are turned off. V between 0 and V .
TT
ON
IN TT
37
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Table 2-16. CMOS Signal Input/Output Group and TAP Signal Group
DC Specifications
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
-0.10
0.7 * V
-0.10
0.9 * V
1.70
0.00
0.3 * V
V
V
2,3
2
IL
TT
V
V
V
+ 0.1
TT
IH
TT
TT
TT
V
0
0.1 * V
V
2
OL
OH
OL
OH
TT
V
V
V
+ 0.1
V
2
TT
TT
I
N/A
N/A
N/A
4.70
mA
mA
μA
4
I
1.70
4.70
5
I
N/A
± 100
6
LI
Notes:
1.
2.
3.
4.
5.
6.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
The V referred to in these specifications refers to instantaneous V .
TT
TT
Refer to the processor I/O Buffer Models for I/V characteristics.
Measured at 0.1*V .
Measured at 0.9*V .
For Vin between 0 V and V . Measured when the driver is tristated.
TT
TT
TT
Table 2-17. Open Drain Output Signal Group DC Specifications
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
Output Low Voltage
Output High Voltage
Output Low Current
Leakage Current
0
0.95 * V
16
N/A
0.20 * V
1.05 * V
50
V
V
OL
OH
OL
LO
TT
V
V
3
2
4
TT
TT
TT
I
I
N/A
N/A
mA
μA
N/A
± 200
Notes:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Measured at 0.2*V .
TT
V
is determined by value of the external pullup resistor to V . Refer to platform design guide for details.
OH
TT
For V between 0 V and V
.
OH
IN
2.13.2
V
Overshoot Specification
CC
The Quad-Core Intel® Xeon® Processor 5400 Series can tolerate short transient
overshoot events where VCC exceeds the VID voltage when transitioning from a high-
to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is
the maximum allowable overshoot above VID). These specifications apply to the
processor die voltage as measured across the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands.
Table 2-18. VCC Overshoot Specifications
Symbol
Parameter
Magnitude of V overshoot above VID
Min
Max
Units
Figure
Notes
V
50
25
mV
µs
2-11
2-11
OS_MAX
CC
T
Time duration of V overshoot above VID
CC
OS_MAX
38
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-11. VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
Notes:
1.
2.
VOS is the measured overshoot voltage.
TOS is the measured time duration above VID.
2.13.3
Die Voltage Validation
Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 2-18 when measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands
and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Overshoot events that
are < 10 ns in duration may be ignored. These measurements of processor die level
overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
2.14
AGTL+ FSB Specifications
Routing topologies are dependent on the processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines for specific
implementation details. In most cases, termination resistors are not required as these
are integrated into the processor silicon. See Table 2-8 for details on which signals do
not include on-die termination. Please refer to Table 2-19 for RTT values.
Valid high and low levels are determined by the input buffers via comparing with a
reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID,
and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END is the reference
voltage for the FSB 4X data signals, GTLREF_ADD_MID, and GTLREF_ADD_END is the
reference voltage for the FSB 2X address signals and common clock signals. Table 2-19
lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and
GTLREF_ADD_END specifications.
39
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard
using high precision voltage divider circuits. Refer to the appropriate platform design
guidelines for implementation details.
Table 2-19. AGTL+ Bus Voltage Definitions
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
GTLREF_DATA_MID, Data Bus Reference
GTLREF_DATA_END Voltage
0.98 *
0.667 *
1.02*0.667
V
2, 3
0.667 * V
V
* V
TT
TT
TT
TT
GTLREF_ADD_MID,
GTLREF_ADD_END
Address Bus Reference
Voltage
0.98 *
0.667 * V
0.667 *
1.02*0.667
* V
V
Ω
Ω
2, 3
4
V
TT
TT
R
Termination
Resistance (pull up)
45
50
55
TT
COMP
COMP Resistance
49.4
49.9
50.4
5
Notes:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of V .
TT
3.
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V
TT
on the baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account
for this resistor tolerance. Refer to the appropriate platform design guidelines for implementation details.
TT
TT
4.
5.
Table 2-20. FSB Differential BCLK Specifications
1
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
V
V
V
Input Low Voltage
-0.150
0.660
0.250
0.0
0.150
0.850
0.550
V
V
V
2-13
2-13
L
Input High Voltage
Absolute Crossing Point
0.710
0.350
H
2-13,
2-14
2,9
CROSS(abs)
V
Relative Crossing Point
0.250 +
0.5 *
Havg
0.700)
N/A
0.550+
0.5 *
Havg
0.700)
V
2-13,
2-14
3,8,9,11
CROSS(rel)
(V
-
(V
-
Δ
Range of Crossing
Points
N/A
N/A
0.140
V
2-13,
2-14
VCROSS
V
V
V
V
Overshoot
N/A
N/A
N/A
N/A
N/A
1.150
N/A
V
V
V
V
2-13
2-13
2-13
2-13
4
5
6
7
OS
US
Undershoot
-0.300
0.200
Ringback Margin
Threshold Region
N/A
RBM
TR
V
-
V
CROSS
CROSS
0.100
+ 0.100
± 100
4
I
Input Leakage Current
N/A
0.6
N/A
μA
10
12
LI
ERRefclk-diffRrise
ERRefclk-diff-Fall
Differential Rising and
falling edge rates
V/ns
2-15
Notes:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to
the falling edge of BCLK1.
Havg H
3.
4.
5.
6.
V
is the statistical average of the V measured by the oscilloscope.
Overshoot is defined as the absolute value of the maximum voltage.
Undershoot is defined as the absolute value of the minimum voltage.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
40
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
7.
Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8.
9.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
V
can be measured directly using “Vtop” on Agilent and “High” on Tektronix oscilloscopes.
Havg
10. For V between 0 V and V .
IN
CROSS
H
11. ΔV
is defined as the total variation of all crossing voltages as defined in note 3.
12. Measured from -200 mV to +200 mV on the differential waveform (derived from REFCLK+ minus REFCLK-).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing. See Figure 2-15.
Figure 2-12. Electrical Test Circuit
Vtt
Vtt
Rtt = 55 Ohms
0.3nH
0.9nH
0.6nH
55 Ohms, 160 ps/in, 600 mils
1.3pF
0.2pF
R
Load
Buffer
Long Package
AC Timings specified at this point (@Buffer pad)
Figure 2-13. Differential Clock Waveform
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
Tp
Tp = T1: BCLK[1:0] period
41
Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-14. Differential Clock Crosspoint Specification
650
600
550
500
450
400
350
300
250
200
550 mV
550 + 0.5 (VHavg - 700)
250 + 0.5 (VHavg - 700)
250 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 2-15. Differential Rising and Falling Edge Rates
§
42
Mechanical Specifications
3 Mechanical Specifications
The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land
Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The
package consists of a processor core mounted on a pinless substrate with 771 lands. An
integrated heat spreader (IHS) is attached to the package substrate and core and
serves as the interface for processor component thermal solutions such as a heatsink.
Figure 3-1 shows a sketch of the processor package components and how they are
assembled together. Refer to the LGA771 Socket Design Guidelines for complete details
on the LGA771 socket.
The package components shown in Figure 3-1 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor Core (die)
• Package Substrate
• Landside capacitors
• Package Lands
Figure 3-1. Processor Package Assembly Sketch
TIM
Core (die)
IHS
Substrate
Package Lands
Capacitors
LGA771 Socket
System Board
Note: This drawing is not to scale and is for reference only.
3.1
Package Mechanical Drawings
The package mechanical drawings are shown in Figure 3-2 through Figure 3-4. The
drawings include dimensions necessary to design a thermal solution for the processor
including:
• Package reference and tolerance dimensions (total height, length, width, and so
forth)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keepout dimensions
• Reference datums
Note:
All drawing dimensions are in mm [in.].
43
Mechanical Specifications
Figure 3-2. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing
(Sheet 1 of 3)
Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution are
available in the processor Thermal/Mechanical Design Guidelines.
44
Mechanical Specifications
Figure 3-3. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing
(Sheet 2 of 3)
45
Mechanical Specifications
Figure 3-4. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing
(Sheet 3 of 3)
Note: The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial
processors.
46
Mechanical Specifications
3.2
3.3
Processor Component Keepout Zones
The processor may contain components on the substrate that define component
keepout zone requirements. Decoupling capacitors are typically mounted to either the
topside or landside of the package substrate. See Figure 3-4 for keepout zones.
Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical load limits should not be exceeded during heatsink assembly,
mechanical stress testing or standard drop and shipping conditions. The heatsink
attach solutions must not include continuous stress onto the processor with the
exception of a uniform load to maintain the heatsink-to-processor thermal interface.
Also, any mechanical system or component testing should not exceed these limits. The
processor package substrate should not be used as a mechanical reference or load-
bearing surface for thermal or mechanical solutions.
Table 3-1.
Package Loading Specifications
Board
Thickness
Parameter
Min
Max
Unit
Notes
1.57 mm
0.062”
80
18
311
70
N
lbf
2.16 mm
0.085”
111
25
311
70
N
Static Compressive
Load
1,2,3,9
lbf
2.54 mm
0.100”
133
30
311
70
N
lbf
311 N (max static
compressive load)
+ 222 N dynamic
loading
N
Dynamic
NA
NA
NA
1,3,4,5,6
1,3,7,8
Compressive Load
70 lbf (max static
compressive load)
+ 50 lbf dynamic
loading
lbf
1.57 mm
0.062”
Transient Bend Limits
750
me
Notes:
1.
2.
3.
These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top
surface.
This is the minimum and maximum static force that can be applied by the heatsink and retention solution
to maintain the heatsink and processor interface.
These specifications are based on limited testing for design characterization. Loading limits are for the
LGA771 socket.
Dynamic compressive load applies to all board thickness.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
4.
5.
6.
Test condition used a heatsink mass of 1 lbm with 50 g acceleration measured at heatsink mass. The
dynamic portion of this specification in the product application can have flexibility in specific values, but the
ultimate product of mass times acceleration should not exceed this dynamic load.
Transient bend is defined as the transient board deflection during manufacturing such as board assembly
and system integration. It is a relatively slow bending event compared to shock and vibration tests.
For more information on the transient bend limits, please refer to the MAS document titled Manufacturing
7.
8.
®
with Intel components using 771-land LGA package that interfaces with the motherboard via a LGA771
socket.
9.
Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines
(TMDG)for information on heatsink clip load metrology.
47
Mechanical Specifications
3.4
Package Handling Guidelines
Table 3-2 includes a list of guidelines on a package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.
Package Handling Guidelines
Parameter
Maximum Recommended
Units
Notes
Shear
311
70
N
lbf
1,4,5
Tensile
Torque
111
25
N
lbf
2,4,5
3,4,5
3.95
35
N-m
LBF-in
Notes:
1.
2.
3.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.
4.
5.
These guidelines are based on limited testing for design characterization and incidental applications (one
time only).
Handling guidelines are for the package only and do not include the limits of the processor socket.
3.5
3.6
Package Insertion Specifications
The Quad-Core Intel® Xeon® Processor 5400 Series can be inserted and removed 15
times from an LGA771 socket, which meets the criteria outlined in the LGA771 Socket
Design Guidelines.
Processor Mass Specifications
The typical mass of the Quad-Core Intel® Xeon® Processor 5400 Series is 21.5 grams
[0.76 oz.]. This includes all components which make up the entire processor product.
3.7
Processor Materials
The Quad-Core Intel® Xeon® Processor 5400 Series is assembled from several
components. The basic material properties are described in Table 3-3.
Table 3-3.
Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel over copper
Fiber-reinforced resin
Gold over nickel
Substrate Lands
3.8
Processor Markings
Figure 3-5 shows the topside markings on the processor. This diagram aids in the
identification of the Quad-Core Intel® Xeon® Processor 5400 Series.
48
Mechanical Specifications
Figure 3-5. Processor Top-side Markings (Example)
Mark Text (Production Mark):
Legend:
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
3200DP/12M/1600
Intel ® Xeon ®
Proc# SXXX COO
i (M) © ‘07
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
FPO
ATPO
S/N
Note: 2D matrix is required for engineering samples only (encoded with ATPO-S/N).
3.9
Processor Land Coordinates
Figure 3-6 and Figure 3-7 show the top and bottom view of the processor land
coordinates, respectively. The coordinates are referred to throughout the document to
identify processor lands.
Figure 3-6. Processor Land Coordinates, Top View
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2 1
AN
AM
AL
AK
AJ
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AH
AG
AF
AE
AD
AC
AB
AA
Y
Address /
Common Clock /
Async
W
W
V
Socket 771
Quadrants
Top View
V
U
U
T
T
R
R
P
N
M
L
P
N
M
L
K
J
K
J
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2 1
Data
VTT / Clocks
49
Mechanical Specifications
Figure 3-7. Processor Land Coordinates, Bottom View
VCC / VSS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
Address /
Common Clock /
Async
W
V
W
V
Socket 771
Quadrants
Bottom View
U
U
T
T
R
R
P
P
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Data
VTT / Clocks
§
50
Land Listing
4 Land Listing
4.1
Quad-Core Intel® Xeon® Processor 5400 Series
Pin Assignments
This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a
listing of all processor lands ordered alphabetically by land name. Table 4-2 is
a listing of all processor lands ordered by land number.
4.1.1
Land Listing by Land Name
Table 4-1.
Land Listing by Land Name
(Sheet 2 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 1 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
A31#
AG5
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Source Sync
Source Sync
Common Clk
Common Clk
Clk
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
A03#
A04#
A05#
A06#
A07#
A08#
A09#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
M5
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
CMOS ASync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
A32#
AH4
AH5
AJ5
AJ6
N4
P6
A33#
L5
A34#
L4
A35#
M4
R4
A36#
A37#
P5
T5
ADS#
D2
U6
ADSTB0#
ADSTB1#
AP0#
R6
T4
AD5
U2
U5
U4
AP1#
U3
V5
BCLK0
BCLK1
BINIT#
BNR#
F28
G28
AD3
C2
V4
Clk
Input
W5
AB6
W6
Y6
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Input/Output
Input/Output
Input/Output
Output
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPMb0#
BPMb1#
BPMb2#
BPMb3#
BPRI#
BR0#
AJ2
AJ1
AD2
AG2
AF2
AG3
G1
Y4
Output
K3
Input/Output
Output
AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
C9
G4
Output
G3
Input/Output
Input
G8
F3
Input/Output
Input
BR1#
H5
51
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 3 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 4 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Pin Name
Direction
Pin Name
Direction
Type
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
D00#
D01#
D02#
D03#
D04#
D05#
D06#
D07#
D08#
D09#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
G29
CMOS ASync
CMOS ASync
CMOS Async
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Output
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBI0#
DBI1#
DBI2#
DBI3#
DBR#
DBSY#
DEFER#
DP0#
DP1#
E15
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Common Clk
Common Clk
Common Clk
Common Clk
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
H30
G30
A13
T1
Output
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
A8
Output
Input
Input
G2
Input
R1
Input
B4
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
C5
A4
C6
A5
B6
B7
A7
A10
A11
B10
C11
D8
B12
C12
D11
G9
F8
F9
E9
D7
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G16
G11
D19
C20
AC2
B2
Input/Output
Input
G7
J16
Input/Output
Input/Output
H15
52
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 5 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 6 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
DP2#
H16
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Open Drain
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
A23
DP3#
J17
C1
A24
AC4
AE4
AE6
AH2
AH7
AJ3
AJ7
AK3
AM2
AN5
AN6
B13
B23
C23
D1
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#/PBE#
FORCEPR#
GTLREF_ADD_END
GTLREF_ADD_MID
C8
G12
G20
A16
B9
E12
G19
C17
R3
AK6
G10
F2
CMOS ASync
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Open Drain
Input
Input
Input
GTLREF_DATA_END H1
Input
GTLREF_DATA_MID
HIT#
H2
D4
E4
Input
Input/Output
Input/Output
Output
D14
D16
E1
HITM#
IERR#
AB2
N2
P3
IGNNE#
INIT#
CMOS ASync
CMOS ASync
CMOS ASync
CMOS ASync
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Open Drain
Input
E23
E24
E5
Input
LINT0
K1
Input
LINT1
L1
Input
E6
LL_ID0
V2
Output
E7
LL_ID1
AA2
C3
Output
E29
F23
F29
F6
LOCK#
Input/Output
Input/Output
Output
MCERR#
MS_ID0
MS_ID1
PECI
AB3
W1
V1
Output
G6
G5
AL2
N1
K4
Input/Output
Output
J2
PROCHOT#
PWRGOOD
REQ0#
J3
CMOS ASync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input
N5
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
T2
REQ1#
J5
Y1
REQ2#
M6
K6
Y3
REQ3#
AL1
AK1
G27
G26
REQ4#
J6
RESERVED
RESERVED
AM6
A20
53
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 7 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 8 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Pin Name
Direction
Pin Name
Direction
Type
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
RS0#
G24
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD25
AD26
AD27
AD28
AD29
AD30
AD8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
F24
F26
F25
G25
W3
AM2
G23
B3
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
CMOS ASync
CMOS ASync
TAP
Input
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AE9
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
RS1#
F5
RS2#
A3
RSP#
H4
SKTOCC#
SMI#
AE8
P2
STPCLK#
TCK
M3
AE1
AD1
AF1
P1
TDI
TAP
TDO
TAP
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22
AF8
TESTHI10
TESTHI11
TESTHI12
TESTIN1
TESTIN2
THERMTRIP#
TMS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Open Drain
TAP
L2
AE3
W2
U1
M2
AC1
E3
TRDY#
TRST#
VCC
Common Clk
TAP
AG1
AA8
AB8
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC8
AD23
AD24
AF9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
54
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 9 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 10 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AG30
AG8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AK26
AK8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG9
AK9
AH11
AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30
AH8
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AM9
AJ9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
AN25
AN26
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
55
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 11 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 12 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Pin Name
Direction
Pin Name
Direction
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AN8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M30
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J8
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
P8
R8
T23
T24
T25
T26
T27
T28
T29
T30
T8
J9
U23
U24
U25
U26
U27
U28
U29
U30
U8
K23
K24
K25
K26
K27
K28
K29
K30
K8
V8
L8
W23
W24
W25
W26
W27
W28
W29
W30
M23
M24
M25
M26
M27
M28
M29
56
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 13 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 14 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VCC
W8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Async
CMOS Async
CMOS Async
CMOS Async
CMOS Async
CMOS Async
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AC3
VCC
AC6
VCC_DIE_SENSE
VCC_DIE_SENSE2
VCCPLL
VID_SELECT
VID1
VID2
VID3
VID4
VID5
VID6
VSS
AN3
AL8
D23
AN7
AL5
AM3
AL6
AK4
AL4
AM5
A12
A15
A18
A2
Output
AC7
Output
Input
AD4
AD7
Output
Output
Output
Output
Output
Output
Output
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE5
VSS
VSS
VSS
VSS
A21
A6
VSS
VSS
A9
VSS
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AE7
VSS
AF7
VSS
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
57
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 15 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 16 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Pin Name
Direction
Pin Name
Direction
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF29
AF3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK23
AK24
AK27
AK28
AK29
AK30
AK5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AF30
AF6
AG10
AG13
AG16
AG17
AG20
AG23
AG24
AG7
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AH6
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AM7
AN1
AN10
AN13
AN16
AN17
AN2
AK10
AK13
AK16
AK17
AK2
AN20
AN23
AN24
B1
AK20
58
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 17 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 18 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B11
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B14
B17
B20
B24
B5
F7
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H3
B8
C10
C13
C16
C19
C22
C24
C4
C7
D12
D15
D18
D21
D24
D3
D5
H6
D6
H7
D9
H8
E11
E14
E17
E2
H9
J4
J7
K2
E20
E25
E26
E27
E28
E8
K5
K7
L23
L24
L25
L26
L27
L28
L29
L3
F1
F10
F13
F16
F19
F22
L30
L6
59
Land Listing
Table 4-1.
Land Listing by Land Name
(Sheet 19 of 20)
Table 4-1.
Land Listing by Land Name
(Sheet 20 of 20)
Pin
No.
Signal Buffer
Type
Pin
No.
Signal Buffer
Pin Name
Direction
Pin Name
Direction
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
V6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
M1
VSS
V7
M7
VSS
W4
N3
VSS
W7
N6
VSS
Y2
N7
VSS
Y5
P23
P24
P25
P26
P27
P28
P29
P30
P4
VSS
Y7
VSS_DIE_SENSE
AN4
AL7
A25
A26
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
E30
F30
AA1
J1
Output
VSS_DIE_SENSE2
VTT
Output
VTT
VTT
VTT
VTT
VTT
P7
VTT
R2
VTT
R23
R24
R25
R26
R27
R28
R29
R30
R5
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
R7
VTT
T3
VTT
T6
VTT
T7
VTT
U7
VTT
V23
V24
V25
V26
V27
V28
V29
V3
VTT_OUT
VTT_OUT
VTT_SEL
Output
Output
Output
F27
V30
60
Land Listing
4.1.2
Land Listing by Land Number
Table 4-2.
Land Listing by Land Number
(Sheet 2 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 1 of 20)
SignalBuffer
SignalBuffer
Direction
Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Type
AA7
VSS
Power/Other
Power/Other
Power/Other
Open Drain
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
TAP
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
D08#
D09#
VSS
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Input/Output
Input/Output
AA8
VCC
AB1
VSS
AB2
IERR#
VSS
Output
COMP0
D50#
VSS
Input
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB3
Input/Output
VSS
VSS
DSTBN3#
D56#
VSS
Input/Output
Input/Output
VSS
VSS
VSS
D61#
VSS
Input/Output
VSS
MCERR#
VSS
Input/Output
A20
A21
A22
A23
A24
A25
A26
A3
RESERVED
VSS
AB30
AB4
Power/Other
Source Sync
A26#
A24#
A17#
VSS
Input/Output
Input/Output
Input/Output
D62#
RESERVED
RESERVED
VTT
Input/Output
AB5
AB6
AB7
Power/Other
Power/Other
Common Clk
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
AB8
VCC
VTT
AC1
TMS
Input
RS2#
D02#
D04#
VSS
Input
AC2
DBR#
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
A4
Input/Output
Input/Output
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC3
A5
VCC
A6
VCC
A7
D07#
DBI0#
VSS
Input/Output
Input/Output
VCC
A8
VCC
A9
VCC
AA1
AA2
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA4
AA5
AA6
VTT_OUT
LL_ID1
VSS
Output
Output
VCC
VSS
AC30
AC4
VCC
VSS
RESERVED
A25#
VSS
VSS
AC5
Source Sync
Power/Other
Power/Other
Power/Other
TAP
Input/Output
VSS
AC6
VSS
AC7
VSS
VSS
AC8
VCC
VSS
AD1
TDI
Input
VSS
AD2
BPM2#
VCC
Common Clk
Power/Other
Power/Other
Power/Other
Output
VSS
AD23
AD24
AD25
A21#
A23#
VSS
Input/Output
Input/Output
VCC
VCC
61
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 3 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 4 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Pin No.
Pin Name
Pin No.
Pin Name
Direction
Type
AD26
AD27
AD28
AD29
AD3
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
AE9
VCC
Power/Other
TAP
AF1
TDO
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
BPM4#
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A28#
A27#
VSS
VSS
VCC
VCC
TRST#
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
Output
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
TAP
BINIT#
VCC
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
TAP
Input/Output
AD30
AD4
VSS
AD5
ADSTB1#
A22#
VSS
Input/Output
Input/Output
AD6
AD7
AD8
VCC
AE1
TCK
Input
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE2
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
VCC
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF3
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE3
VSS
VCC
AF30
AF4
VCC
Input/Output
Input/Output
VCC
AF5
VSS
AF6
VSS
AF7
VSS
AF8
VSS
AF9
VSS
AG1
Input
VSS
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TESTHI12
VSS
Input
AE30
AE4
RESERVED
VSS
AE5
Power/Other
AE6
RESERVED
VSS
AE7
Power/Other
Power/Other
AE8
SKTOCC#
Output
62
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 5 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 6 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Direction
Type
Pin No.
Pin Name
Pin No.
Pin Name
AG18
AG19
AG2
VCC
VCC
BPM3#
VSS
Power/Other
Power/Other
AH27
AH28
AH29
AH3
AH30
AH4
AH5
AH6
AH7
AH8
AH9
AJ1
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input/Output
VCC
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG3
VSS
VCC
VCC
VSS
VCC
A32#
A33#
VSS
Source Sync
Source Sync
Power/Other
Input/Output
Input/Output
VSS
VCC
VCC
VCC
VCC
VCC
BPM5#
VCC
A30#
A31#
A29#
VSS
RESERVED
VCC
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
BPM1#
VSS
Output
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ2
Input/Output
VCC
AG30
AG4
VCC
Input/Output
Input/Output
Input/Output
VSS
AG5
VCC
AG6
VCC
AG7
VSS
AG8
VCC
VCC
VSS
VSS
AG9
VCC
AH1
VCC
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH2
VSS
BPM0#
VSS
Input/Output
VCC
VCC
VSS
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ3
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
RESERVED
VSS
VSS
VSS
VSS
AH20
AH21
AH22
AH23
AH24
AH25
AH26
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
RESERVED
VSS
VCC
VCC
VSS
AJ30
AJ4
Power/Other
Power/Other
Source Sync
Source Sync
VSS
AJ5
A34#
A35#
RESERVED
VCC
Input/Output
Input/Output
VSS
AJ6
VCC
VCC
AJ7
AJ8
Power/Other
63
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 7 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 8 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Pin No.
Pin Name
Pin No.
Pin Name
Direction
Type
AJ9
VCC
Power/Other
AL18
AL19
AL2
VCC
Power/Other
Power/Other
Open Drain
AK1
RESERVED
VSS
VCC
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
PROCHOT#
VSS
Output
VCC
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Async
CMOS Async
CMOS Async
Power/Other
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK3
VSS
VSS
VCC
AL30
AL4
VCC
VCC
VID5
VID1
VID3
Output
Output
Output
VSS
AL5
VSS
AL6
VCC
AL7
VSS_DIE_
SENSE2
VCC
AL8
VCC_DIE_
SENSE2
Power/Other
VSS
VSS
AL9
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
RESERVED
VSS
VCC
VCC
VSS
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
AM1
RESERVED
VSS
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM2
AK30
AK4
Power/Other
CMOS Async
Power/Other
CMOS Async
Power/Other
Power/Other
Power/Other
VID4
VSS
Output
Input
AK5
AK6
FORCEPR#
VSS
AK7
AK8
VCC
AK9
VCC
AL1
RESERVED
VSS
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
AM20
AM21
AM22
AM23
AM24
AM25
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCC
VCC
VSS
VSS
64
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 9 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 10 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Direction
Type
Pin No.
Pin Name
Pin No.
Pin Name
AM26
AM27
AM28
AM29
AM3
VCC
VSS
VSS
VCC
VID2
VCC
VSS
VID6
RESERVED
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B2
D10#
VSS
Source Sync
Power/Other
Source Sync
Input/Output
D13#
RESERVED
VSS
Input/Output
CMOS Async
Power/Other
Power/Other
CMOS Async
Output
Output
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
AM30
AM4
D53#
D55#
VSS
Input/Output
Input/Output
AM5
AM6
D57#
D60#
DBSY#
VSS
Input/Output
Input/Output
Input/Output
AM7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM8
AM9
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B3
AN1
D59#
D63#
RESERVED
VSS
Input/Output
Input/Output
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
VTT
VTT
VTT
VTT
VTT
RS0#
VTT
Input
B30
B4
D00#
VSS
Input/Output
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN3
B5
B6
D05#
D06#
VSS
Input/Output
Input/Output
B7
B8
B9
DSTBP0#
DRDY#
VSS
Input/Output
Input/Output
C1
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
VCC_DIE_
SENSE
Output
Output
D11#
D14#
VSS
Input/Output
Input/Output
AN4
VSS_DIE_
SENSE
Power/Other
D52#
D51#
VSS
Input/Output
Input/Output
AN5
AN6
AN7
AN8
AN9
B1
RESERVED
RESERVED
VID_SELECT
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Output
DSTBP3#
D54#
VSS
Input/Output
Input/Output
VCC
VSS
65
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 11 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 12 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Pin No.
Pin Name
Pin No.
Pin Name
Direction
Type
C2
BNR#
DBI3#
D58#
VSS
Common Clk
Source Sync
Source Sync
Power/Other
Input/Output
Input/Output
Input/Output
D29
D3
VTT
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C3
VSS
D30
D4
VTT
HIT#
Input/Output
RESERVED
VSS
D5
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Common Clk
D6
VSS
VTT
D7
D20#
D12#
VSS
Input/Output
Input/Output
VTT
D8
VTT
D9
VTT
E1
RESERVED
D21#
VSS
VTT
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E2
Input/Output
LOCK#
VTT
Input/Output
C30
C4
DSTBP1#
D26#
VSS
Input/Output
Input/Output
VSS
C5
D01#
D03#
VSS
Input/Output
Input/Output
C6
D33#
D34#
VSS
Input/Output
Input/Output
C7
C8
DSTBN0#
BPMb1#
RESERVED
D22#
D15#
VSS
Input/Output
Output
C9
D39#
D40#
VSS
Input/Output
Input/Output
D1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
Source Sync
Source Sync
Power/Other
Source Sync
Input/Output
Input/Output
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E3
VSS
D42#
D45#
RESERVED
RESERVED
VSS
Input/Output
Input/Output
D25#
RESERVED
VSS
Input/Output
Power/Other
RESERVED
D49#
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Common Clk
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input/Output
VSS
VSS
DBI2#
ADS#
D48#
VSS
Input/Output
Input/Output
Input/Output
VSS
RESERVED
TRDY#
VTT
D20
D21
D22
D23
D24
D25
D26
D27
D28
Common Clk
Power/Other
Common Clk
Input
E30
E4
D46#
VCCPLL
VSS
Input/Output
Input
HITM#
RESERVED
RESERVED
RESERVED
VSS
Input/Output
E5
E6
VTT
E7
VTT
E8
Power/Other
Source Sync
Power/Other
VTT
E9
D19#
VSS
Input/Output
VTT
F1
66
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 13 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 14 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Direction
Type
Pin No.
Pin Name
Pin No.
Pin Name
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F2
VSS
Power/Other
G19
G2
DSTBP2#
COMP2
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
Common Clk
Input/Output
Input
D23#
D24#
VSS
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Input/Output
Input/Output
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G3
DSTBN2#
D44#
Input/Output
Input/Output
Input/Output
Input
D28#
D30#
VSS
Input/Output
Input/Output
D47#
RESET#
RESERVED
RESERVED
RESERVED
RESERVED
BCLK1
D37#
D38#
VSS
Input/Output
Input/Output
GTLREF_ADD_
MID
Input
Clk
Input
BSEL0
CMOS Async
Common Clk
CMOS Async
Common Clk
Power/Other
Output
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F3
D41#
Source Sync
Source Sync
Power/Other
Input/Output
Input/Output
BPMb3#
BSEL2
Input/Output
Output
D43#
G30
G4
VSS
BPMb2#
PECI
Output
RESERVED
RESERVED
RESERVED
RESERVED
VTT_SEL
BCLK0
G5
Input/Output
G6
RESERVED
DEFER#
BPRI#
G7
Common Clk
Common Clk
Source Sync
Power/Other
Input
G8
Input
Power/Other
Clk
Output
Input
G9
D16#
Input/Output
Input
H1
GTLREF_DATA
_END
RESERVED
BR0#
Common Clk
Power/Other
Power/Other
Common Clk
Input/Output
Input
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H2
VSS
VSS
VSS
VSS
VSS
DP1#
DP2#
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
F30
F4
VTT
VSS
F5
RS1#
F6
RESERVED
VSS
F7
Power/Other
Source Sync
Source Sync
Common Clk
Power/Other
Input/Output
Input/Output
F8
D17#
Input/Output
Input/Output
Input/Output
Input
F9
D18#
G1
BPMb0#
G10
GTLREF_ADD_
END
GTLREF_DATA
_MID
Input
G11
G12
G13
G14
G15
G16
G17
G18
DBI1#
DSTBN1#
D27#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
H20
H21
H22
H23
H24
H25
H26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D29#
D31#
D32#
D36#
D35#
67
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 15 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 16 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Pin No.
Pin Name
Pin No.
Pin Name
Direction
Type
H27
H28
H29
H3
VSS
Power/Other
Power/Other
Power/Other
Power/Other
J9
VCC
Power/Other
CMOS Async
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Async
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
CMOS Async
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Open Drain
VSS
K1
LINT0
VSS
Input
VSS
K2
VSS
K23
K24
K25
K26
K27
K28
K29
K3
VCC
H30
H4
BSEL1
RSP#
BR1#
VSS
CMOS Async
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Output
Input
Input
VCC
VCC
H5
VCC
H6
VCC
H7
VSS
VCC
H8
VSS
VCC
H9
VSS
A20M#
VCC
Input
J1
VTT_OUT
VCC
Output
K30
K4
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J2
REQ0#
VSS
Input/Output
Input/Output
VCC
K5
VCC
K6
REQ3#
VSS
VCC
K7
VCC
K8
VCC
VCC
L1
LINT1
TESTHI11
VSS
Input
Input
DP0#
DP3#
VCC
Input/Output
Input/Output
L2
L23
L24
L25
L26
L27
L28
L29
L3
VSS
VCC
VSS
RESERVED
VCC
VSS
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
L30
L4
VSS
VCC
A06#
A05#
VSS
Input/Output
Input/Output
VCC
L5
VCC
L6
VCC
L7
VSS
VCC
L8
VCC
RESERVED
VCC
M1
VSS
J30
J4
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
M2
THERMTRIP#
VCC
Output
VSS
M23
M24
M25
M26
M27
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J5
REQ1#
REQ4#
VSS
Input/Output
Input/Output
VCC
J6
VCC
J7
VCC
J8
VCC
VCC
68
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 17 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 18 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Direction
Type
Pin No.
Pin Name
Pin No.
Pin Name
M28
M29
M3
VCC
VCC
Power/Other
Power/Other
P8
VCC
Power/Other
R1
COMP3
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Open Drain
Input
STPCLK#
VCC
CMOS Async
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
CMOS Async
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Input
R2
M30
M4
R23
R24
R25
R26
R27
R28
R29
R3
VSS
A07#
A03#
REQ2#
VSS
Input/Output
Input/Output
Input/Output
VSS
M5
VSS
M6
VSS
M7
VSS
M8
VCC
VSS
N1
PWRGOOD
IGNNE#
VCC
Input
Input
VSS
N2
FERR#/PBE#
VSS
Output
N23
N24
N25
N26
N27
N28
N29
N3
R30
R4
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
VCC
A08#
VSS
Input/Output
Input/Output
VCC
R5
VCC
R6
ADSTB0#
VSS
VCC
R7
VCC
R8
VCC
VCC
T1
COMP1
RESERVED
VCC
Input
VSS
T2
N30
N4
VCC
T23
T24
T25
T26
T27
T28
T29
T3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A36#
RESERVED
VSS
Input/Output
VCC
N5
VCC
N6
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Async
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Async
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
VCC
N7
VSS
VCC
N8
VCC
VCC
P1
TESTHI10
SMI#
VSS
Input
Input
VCC
P2
VSS
P23
P24
P25
P26
P27
P28
P29
P3
T30
T4
VCC
VSS
A11#
A09#
VSS
Input/Output
Input/Output
VSS
T5
VSS
T6
VSS
T7
VSS
VSS
T8
VCC
VSS
U1
TESTIN2
AP0#
VCC
Input
INIT#
VSS
Input
U2
Input/Output
P30
P4
U23
U24
U25
U26
U27
VSS
VCC
P5
A37#
A04#
VSS
Input/Output
Input/Output
VCC
P6
VCC
P7
VCC
69
Land Listing
Table 4-2.
Land Listing by Land Number
(Sheet 19 of 20)
Table 4-2.
Land Listing by Land Number
(Sheet 20 of 20)
SignalBuffer
Direction
Type
SignalBuffer
Pin No.
Pin Name
Pin No.
Pin Name
Direction
Type
U28
U29
U3
VCC
Power/Other
Power/Other
W8
Y1
VCC
Power/Other
VCC
RESERVED
VSS
AP1#
VCC
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input/Output
Y2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
U30
U4
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y3
VCC
A13#
A12#
A10#
VSS
Input/Output
Input/Output
Input/Output
VCC
U5
VCC
U6
VCC
U7
VCC
U8
VCC
VCC
V1
MS_ID1
LL_ID0
VSS
Output
Output
VCC
V2
RESERVED
VCC
V23
V24
V25
V26
V27
V28
V29
V3
Y30
Y4
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
VSS
A20#
VSS
Input/Output
Input/Output
VSS
Y5
VSS
Y6
A19#
VSS
VSS
Y7
VSS
Y8
VCC
VSS
§
VSS
V30
V4
VSS
A15#
A14#
VSS
Input/Output
Input/Output
V5
V6
V7
VSS
V8
VCC
W1
W2
W23
W24
W25
W26
W27
W28
W29
W3
W30
W4
W5
W6
W7
MS_ID0
TESTIN1
VCC
Output
Input
VCC
VCC
VCC
VCC
VCC
VCC
RESERVED
VCC
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
VSS
A16#
A18#
VSS
Input/Output
Input/Output
70
Signal Definitions
5 Signal Definitions
5.1
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 1 of 8)
Name
A[37:3]#
Type
Description
Notes
38
I/O
A[37:3]# (Address) define a 2 -byte physical memory address
3
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins of all agents on the FSB. A[37:3]# are protected by
parity signals AP[1:0]#. A[37:3]# are source synchronous signals
and are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors
sample a subset of the A[37:3]# lands to determine their power-on
configuration. See Section 7.1.
A20M#
I
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1 MB boundary. Assertion of A20M# is only supported
in real mode.
2
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an I/O write instruction, it must be valid along
with the TRDY# assertion of the corresponding I/O write bus
transaction.
ADS#
I/O
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[37:3]# lands. All bus agents observe
the ADS# activation to begin parity checking, protocol checking,
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction. This signal must be
connected to the appropriate pins on all Quad-Core Intel® Xeon®
Processor 5400 Series FSB agents.
3
3
ADSTB[1:0]#
Address strobes are used to latch A[37:3]# and REQ[4:0]# on their
rising and falling edge. Strobes are associated with signals as shown
below.
Signals
Associated Strobes
REQ[4:0]#, A[16:3]#,
A[37:36]#
ADSTB0#
A[35:17]#
ADSTB1#
AP[1:0]#
I/O
AP[1:0]# (Address Parity) are driven by the request initiator along
with ADS#, A[37:3]#, and the transaction type on the REQ[4:0]#
signals. A correct parity signal is high if an even number of covered
signals are low and low if an odd number of covered signals are low.
This allows parity to be high when all the covered signals are high.
AP[1:0]# must be connected to the appropriate pins of all Quad-Core
Intel® Xeon® Processor 5400 Series FSB agents. The following table
defines the coverage model of these signals.
3
Request Signals
Subphase 1
Subphase 2
A[37:24]#
A[23:3]#
AP0#
AP1#
AP1#
AP1#
AP0#
AP0#
REQ[4:0]#
71
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 2 of 8)
Name
BCLK[1:0]
Type
Description
Notes
I
The differential bus clock pair BCLK[1:0] (Bus Clock) determines the
FSB frequency. All processor FSB agents must receive these signals
to drive their outputs and latch their inputs.
3
All external timing parameters are specified with respect to the rising
edge of BCLK0 crossing V
.
CROSS
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all
processor FSB agents and if used, must connect the appropriate pins
of all such agents. If the BINIT# driver is enabled during power on
configuration, BINIT# is asserted to signal any bus condition that
prevents reliable future operation.
3
If BINIT# observation is enabled during power-on configuration (see
Section 7.1) and BINIT# is sampled asserted, symmetric agents
reset their bus LOCK# activity and bus request arbitration state
machines. The bus agents do not reset their I/O Queue (IOQ) and
transaction tracking state machines upon observation of BINIT#
assertion. Once the BINIT# assertion has been observed, the bus
agents will re-arbitrate for the FSB and attempt completion of their
bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a
priority agent may handle an assertion of BINIT# as appropriate to
the error handling architecture of the system.
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
3
Since multiple agents might need to request a bus stall at the same
time, BNR# is a wired-OR signal which must connect the appropriate
pins of all processor FSB agents. In order to avoid wired-OR glitches
associated with simultaneous edge transitions driven by multiple
drivers, BNR# is activated on specific clock edges and sampled on
specific clock edges.
BPM5#
BPM4#
BPM3#
BPM[2:1]#
BPM0#
I/O
O
I/O
O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins of all FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
2
I/O
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of the
processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the
appropriate platform design guidelines for more detailed information.
BPMb3#
BPMb[2:1]#
BPMb0#
I/O
O
I/O
BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPMb[3:0]# should connect the
appropriate pins of all FSB agents.
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor FSB. It must connect the appropriate pins of all processor
FSB agents. Observing BPRI# active (as asserted by the priority
agent) causes all other agents to stop issuing new requests, unless
such requests are part of an ongoing locked operation. The priority
agent keeps BPRI# asserted until all of its requests are completed,
then releases the bus by deasserting BPRI#.
3
3
BR[1:0]#
I/O
The BR[1:0]# signals are sampled on the active-to-inactive transition
of RESET#. The signal which the agent samples asserted determines
its agent ID. BR0# drives the BREQ0# signal in the system and is
used by the processor to request the bus.
These signals do not have on-die termination and must be
terminated.
72
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 3 of 8)
Name
BSEL[2:0]
Type
Description
Notes
O
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select
the processor input clock frequency. Table 2-2 defines the possible
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the
processors, chipset, and clock synthesizer. All FSB agents must
operate at the same frequency. For more information about these
signals, including termination recommendations, refer to the
appropriate platform design guideline.
COMP[3:0]
D[63:0]#
I
COMP[3:0] must be terminated to VSS on the baseboard using
precision resistors. These inputs configure the AGTL+ drivers of the
processor. Refer to the appropriate platform design guidelines for
implementation details.
I/O
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data path between the processor FSB agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to
indicate a valid data transfer.
3
D[63:0]# are quad-pumped signals, and will thus be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data
signals correspond to a pair of one DSTBP# and one DSTBN#. The
following table shows the grouping of data signals to strobes and
DBI#.
DSTBN#/DST
Data Group
DBI#
BP#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data group
is inverted and therefore sampled active high.
DBI[3:0]#
I/O
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate
the polarity of the D[63:0]# signals. The DBI[3:0]# signals are
activated when the data on the data bus is inverted. If more than half
the data bits, within, within a 16-bit group, would have been asserted
electronically low, the bus agent may invert the data bus signals for
that particular sub-phase for that 16-bit group.
3
DBI[3:0] Assignment to Data Bus
Bus Signal
Data Bus Signals
DBI0#
DBI1#
DBI2#
DBI3#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DBR#
O
DBR# is used only in systems where no debug port connector is
implemented on the system board. DBR# is used by a debug port
interposer so that an in-target probe can drive system reset. If a
debug port connector is implemented in the system, DBR# is a no-
connect on the Quad-Core Intel® Xeon® Processor 5400 Series
package. DBR# is not a processor signal.
DBSY#
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
use. The data bus is released after DBSY# is deasserted. This signal
must connect the appropriate pins on all processor FSB agents.
3
73
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 4 of 8)
Name
DEFER#
Type
Description
Notes
I
DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or I/O agent. This signal
must connect the appropriate pins of all processor FSB agents.
3
3
3
DP[3:0]#
DRDY#
I/O
I/O
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]#
signals. They are driven by the agent responsible for driving
D[63:0]#, and must connect the appropriate pins of all processor
FSB agents.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of all processor FSB
agents.
DSTBN[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
3
Signals
Associated Strobes
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
3
Signals
Associated Strobes
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#/PBE#
O
FERR#/PBE# (floating-point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-
point error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. For additional
information on the pending break event functionality, including the
identification of support of the feature and enable/disable
2
®
information, refer to Vol. 3 of the Intel 64 and IA-32 Architectures
Software Developer’s Manual and the Intel Processor Identification
and the CPUID Instruction application note.
FORCEPR#
I
I
The FORCEPR# (force power reduction) input can be used by the
platform to cause the Quad-Core Intel® Xeon® Processor 5400
Series to activate the Thermal Control Circuit (TCC).
GTLREF_ADD_MID
GTLREF_ADD_END
GTLREF_ADD determines the signal reference level for AGTL+
address and common clock input lands. GTLREF_ADD is used by the
AGTL+ receivers to determine if a signal is a logical 0 or a logical 1.
Please refer to Table 2-19 and the appropriate platform design
guidelines for additional details.
74
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 5 of 8)
Name
Type
Description
Notes
GTLREF_DATA_MID
GTLREF_DATA_END
I
GTLREF_DATA determines the signal reference level for AGTL+ data
input lands. GTLREF_DATA is used by the AGTL+ receivers to
determine if a signal is a logical 0 or a logical 1. Please refer to
Table 2-19 and the appropriate platform design guidelines for
additional details.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any FSB agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
3
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
2
2
This signal does not have on-die termination.
IGNNE#
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-
point instructions. If IGNNE# is deasserted, the processor generates
an exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error. IGNNE# has no effect when
the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of
this signal following an I/O write instruction, it must be valid along
with the TRDY# assertion of the corresponding I/O write bus
transaction.
INIT#
I
I
INIT# (Initialization), when asserted, resets integer registers inside
all processors without affecting their internal caches or floating-point
registers. Each processor then begins execution at the power-on
Reset vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal and must connect the appropriate pins of all
processor FSB agents.
2
2
LINT[1:0]
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all FSB agents. When the APIC functionality is disabled, the
LINT0/INTR signal becomes INTR, a maskable interrupt request
signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on
®
the Pentium processor. Both signals are asynchronous.
These signals must be software configured via BIOS programming of
the APIC register space to be used either as NMI/INTR or LINT[1:0].
Because the APIC is enabled by default after Reset, operation of
these pins as LINT[1:0] is the default configuration.
LL_ID[1:0]
LOCK#
O
The LL_ID[1:0] signals are used to select the correct loadline slope
for the processor. These signals are not connected to the processor
die.
I/O
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of all
processor FSB agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction to the end of
the last transaction.
3
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity of
lock.
75
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 6 of 8)
Name
MCERR#
Type
Description
Notes
I/O
MCERR# (Machine Check Error) is asserted to indicate an
unrecoverable error without a bus protocol violation. It may be driven
by all processor FSB agents.
MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
•
•
•
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus
transaction after it observes an error.
•
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, refer to the
®
Intel 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3.
MS_ID[1:0]
PROCHOT#
O
O
These signals are provided to indicate the Market Segment for the
processor and may be used for future processor compatibility or for
keying. These signals are not connected to the processor die. Both
the bits 0 and 1 are logic 1 and are no connects on the package.
PROCHOT# (Processor Hot) will go active when the processor’s
temperature monitoring sensor detects that the processor has
reached its maximum safe operating temperature. This indicates that
the Thermal Control Circuit (TCC) has been activated, if enabled. The
TCC will remain active until shortly after the processor deasserts
PROCHOT#. See Section 6.2.3 for more details.
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this
signal to be a clean indication that all processor clocks and power
supplies are stable and within their specifications. “Clean” implies
that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on
until they come within specification. The signal must then transition
monotonically to a high state. PWRGOOD can be driven inactive at
any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 2-18, and be followed by
a 1-10 ms RESET# pulse.
2
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
REQ[4:0]#
RESET#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of
all processor FSB agents. They are asserted by the current bus owner
to define the currently active transaction type. These signals are
source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal
description for details on parity checking of these signals.
3
3
I
Asserting the RESET# signal resets all processors to known states
and invalidates their internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at least
1 ms after VCC and BCLK have reached their proper specifications. On
observing active RESET#, all FSB agents will deassert their outputs
within two clocks. RESET# must not be kept asserted for more than
10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These configuration
options are described in the Section 7.1.
This signal does not have on-die termination and must be terminated
on the system board.
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins of all processor FSB agents.
3
76
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 7 of 8)
Name
Type
Description
Notes
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent
responsible for completion of the current transaction) during
assertion of RS[2:0]#, the signals for which RSP# provides parity
protection. It must connect to the appropriate pins of all processor
FSB agents.
3
A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. While
RS[2:0]# = 000, RSP# is also high, since this indicates it is not being
driven by any agent guaranteeing correct parity.
SKTOCC#
SMI#
O
I
SKTOCC# (Socket occupied) will be pulled to ground by the processor
to indicate that the processor is present. There is no connection to
the processor silicon for this signal.
SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt,
processors save the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor
will tri-state its outputs. See Section 7.1.
2
2
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals
to all processor core units except the FSB and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
I
I
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
I
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification support.
TESTHI[12:10]
TESTHI[12:10] must be connected to a VTT power source through a
resistor for proper processor operation. Refer to Section 2.6 for
TESTHI grouping restrictions.
TESTIN1
TESTIN2
I
I
TESTIN1 must be connected to a VTT power source through a resistor
as well as to the TESTIN2 land of the same socket for proper
processor operation.
TESTIN2 must be connected to a VTT power source through a resistor
as well as to the TESTIN1 land of the same socket for proper
processor operation.
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a temperature beyond which
permanent silicon damage may occur. Measurement of the
1
temperature is accomplished through an internal thermal sensor.
Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the
processor junction temperature. To protect the processor its core
voltage (V ) must be removed following the assertion of
CC
THERMTRIP#. Intel also recommends the removal of V when
TT
THERMTRIP# is asserted.
Driving of the THERMTRIP# signals is enabled within 10 μs of the
assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD.
Once activated, THERMTRIP# remains latched until PWRGOOD is de-
asserted. While the de-assertion of the PWRGOOD signal will de-
assert THERMTRIP#, if the processor’s junction temperature remains
at or above the trip level, THERMTRIP# will again be asserted within
10 μs of the assertion of PWRGOOD.
77
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 8 of 8)
Name
Type
Description
Notes
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
®
See the Debug Port Design Guide for Intel 5000 Series Chipset
Memory Controller Hub (MCH) Systems (External Version) for further
information.
TRDY#
TRST#
I
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of all FSB agents.
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
V
The Quad-Core Intel® Xeon® Processor 5400 Series implements an
CCPLL
on-die PLL filter solution. The V
voltage.
input is used as a PLL supply
CCPLL
VCC_DIE_SENSE
VCC_DIE_SENSE2
O
VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low
impedance connection to the processor core power and ground. This
signal should be connected to the voltage regulator feedback signal,
which insures the output voltage (that is, processor voltage) remains
within specification. Please see the applicable platform design guide
for implementation details.
VID[6:1]
O
VID[6:1] (Voltage ID) pins are used to support automatic selection of
power supply voltages (V ). These are CMOS signals that are driven
CC
by the processor and must be pulled up through a resistor.
Conversely, the voltage regulator output must be disabled prior to the
voltage supply for these pins becomes invalid. The VID pins are
needed to support processor voltage specification variations. See
Table 2-4 for definitions of these pins. The VR must supply the
voltage that is requested by these pins, or disable itself.
VID_SELECT
O
O
VID_SELECT is an output from the processor which selects the
appropriate VID table for the Voltage Regulator. This signal is not
connected to the processor die. This signal is a no-connect on the
Quad-Core Intel® Xeon® Processor 5400 Series package.
VSS_DIE_SENSE
VSS_DIE_SENSE2
VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low
impedance connection to the processor core power and ground. This
signal should be connected to the voltage regulator feedback signal,
which insures the output voltage (that is, processor voltage) remains
within specification. Please see the applicable platform design guide
for implementation details.
VTT
P
O
O
The FSB termination voltage input pins. Refer to Table 2-12 for
further details.
VTT_OUT
VTT_SEL
The VTT_OUT signals are included in order to provide a local VTT for
some signals that require termination to VTT on the motherboard.
The VTT_SEL signal is used to select the correct VTT voltage level for
the processor. VTT_SEL is connected to VSS on the Quad-Core Intel®
Xeon® Processor 5400 Series package.
Notes:
1.
2.
3.
For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of
symmetric agents is one. Maximum number of priority agents is zero.
For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of
symmetric agents is two. Maximum number of priority agents is zero.
For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of
symmetric agents is two. Maximum number of priority agents is one.
§
78
Thermal Specifications
6 Thermal Specifications
6.1
Package Thermal Specifications
The Quad-Core Intel® Xeon® Processor 5400 Series requires a thermal solution to
maintain temperatures within its operating limits. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete solution includes both component and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks
attached to the processor integrated heat spreader (IHS). Typical system level thermal
solutions may consist of system fans combined with ducting and venting.
This section provides data necessary for developing a complete thermal solution. For
more information on designing a component level thermal solution, refer to the Quad-
Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines
(TMDG).
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 8
for details on the boxed processor.
6.1.1
Thermal Specifications
To allow the optimal operation and long-term reliability of Intel processor-based
systems, the processor must remain within the minimum and maximum case
temperature (TCASE) specifications as defined by the applicable thermal profile (see
Table 6-1 and Figure 6-1 for the Quad-Core Intel® Xeon® Processor X5482, Table 6-3
and Figure 6-2 for the Quad-Core Intel® Xeon® Processor X5400 Series, Table 6-6 and
Figure 6-3 for the Quad-Core Intel® Xeon® Processor E5400 Series, Table 6-8 and
Figure 6-4 for the Quad-Core Intel® Xeon® Processor L5400 Series and Table 6-11
and Figure 6-5 for the Quad-Core Intel® Xeon® Processor L5408. Thermal solutions
not designed to provide this level of thermal capability may affect the long-term
reliability of the processor and system. For more details on thermal solution design,
please refer to the Quad-Core Intel® Xeon® Processor 5400 Series
Thermal/Mechanical Design Guidelines (TMDG) or Quad-Core Intel® Xeon® Processor
L5408 Series in Embedded Applications Thermal/Mechanical Design Guidelines (TMDG).
The Quad-Core Intel® Xeon® Processor 5400 Series implements a methodology for
managing processor temperatures which is intended to support acoustic noise
reduction through fan speed control and to assure processor reliability. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 6.3. If the value reported via PECI is less than TCONTROL, then the case
temperature is permitted to exceed the Thermal Profile. If the value reported via PECI
is greater than or equal to TCONTROL, then the processor case temperature must remain
at or below the temperature as specified by the thermal profile. The temperature
reported over PECI is always a negative value and represents a delta below the onset of
thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 6.2,
79
Thermal Specifications
Processor Thermal Features). Systems that implement fan speed control must be
designed to use this data. Systems that do not alter the fan speed only need to
guarantee the case temperature meets the thermal profile specifications.
The Quad-Core Intel® Xeon® Processor X5482, and Quad-Core Intel® Xeon®
Processor E5400 Series, and Quad-Core Intel® Xeon® Processor L5400 Series support
a single Thermal Profile (see Figure 6-1, and Figure 6-3 and Figure 6-4; Table 6-1, and
Table 6-6, and Table 6-8). With this Thermal Profile, it is expected that the Thermal
Control Circuit (TCC) would only be activated for very brief periods of time when
running the most power-intensive applications. Refer to the Quad-Core Intel® Xeon®
Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) for details on
system thermal solution design, thermal profiles and environmental considerations.
The Quad-Core Intel® Xeon® Processor L5408 supports a Thermal Profile with nominal
and short-term conditions designed to meet NEBS level 3 compliance (see Figure 6-5).
Operation at either thermal profile should result in virtually no TCC activation. Refer to
the Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications
Thermal/Mechanical Design Guidelines (TMDG).
The Quad-Core Intel® Xeon® Processor X5400 Series supports a dual Thermal Profile,
either of which can be implemented. Both ensure adherence to the Intel reliability
requirements. Thermal Profile A (see Figure 6-2; Table 6-3) is representative of a
volumetrically unconstrained thermal solution (that is, industry enabled 2U heatsink).
In this scenario, it is expected that the Thermal Control Circuit (TCC) would only be
activated for very brief periods of time when running the most power intensive
applications. Thermal Profile B (see Figure 6-2; Table 6-5) is indicative of a constrained
thermal environment (that is, 1U form factor). Because of the reduced cooling
capability represented by this thermal solution, the probability of TCC activation and
performance loss is increased. Additionally, utilization of a thermal solution that does
not meet Thermal Profile B will violate the thermal specifications and may result in
permanent damage to the processor. Intel has developed these thermal profiles to
allow customers to choose the thermal solution and environmental parameters that
best suit their platform implementation. Refer to the Quad-Core Intel® Xeon®
Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) for details on
system thermal solution design, thermal profiles and environmental considerations.
The upper point of the thermal profile consists of the Thermal Design Power (TDP)
defined in Table 6-1 for the Quad-Core Intel® Xeon® Processor X5482, Table 6-3 for
the Quad-Core Intel® Xeon® Processor X5400 Series, Table 6-6 for the Quad-Core
Intel® Xeon® Processor E5400 Series, and Table 6-8 for the Quad-Core Intel® Xeon®
Processor L5400 Series and the associated TCASE values. The lower point of the thermal
profile is the TCASE_MAX at 0 W power (or no power draw)
Analysis indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 6-2 for the Quad-Core Intel® Xeon® Processor X5482 (C-step) and Quad-Core
Intel® Xeon® Processor X5492, Table 6-4 and Table 6-5 for the Quad-Core Intel®
Xeon® Processor X5400 Series, Table 6-7 for the Quad-Core Intel® Xeon® Processor
E5400 Series and Table 6-9Quad-Core Intel® Xeon® Processor L5400 Series instead of
the maximum processor power consumption. The Thermal Monitor feature is intended
to help protect the processor in the event that an application exceeds the TDP
recommendation for a sustained time period. For more details on this feature, refer to
Section 6.2. To ensure maximum flexibility for future requirements, systems should be
designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower
80
Thermal Specifications
power dissipation is currently planned. Intel® Thermal Monitor 1 and Intel®
Thermal Monitor 2 feature must be enabled for the processor to remain within
its specifications.
Table 6-1.
Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step) Thermal
Specifications
Thermal Design
Power
Minimum
Maximum
Core
Frequency
T
T
Notes
CASE
CASE
(W)
(°C)
(°C)
Launch to FMB
150 (X5492 and
X5482 C-step)
5
See Figure 6-1; Table 6-2
1,2,3,4,5,6
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static V and I combination wherein V exceeds V at
CC
CC
CC
CC_MAX
specified I . Please refer to the loadline specifications in Section 2.13.1.
Thermal Design Power (TDP) should be used for the processor thermal solution design targets. TDP is not
CC
2.
the maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based on silicon characterization.
Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® Processor
X5482 may be shipped under multiple VIDs for each frequency.
.
CASE
3.
4.
5.
6.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
The Quad-Core Intel® Xeon® Processor X5482 is intended for dual processor workstations only.
Figure 6-1. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile
Thermal Profile (2U)
75
70
65
60
55
50
Thermal Profile
Y = 0.187*x + 35
45
40
35
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
Pow er [W]
Notes:
1.
2.
Please refer to Table 6-2 for discrete points that constitute the thermal profile.
Implementation of the Quad-Core Intel® Xeon® Processor X5482 Thermal Profile should result in virtually
no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal
Profile will result in increased probability of TCC activation and may incur measurable performance loss.
Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines
(TMDG) for system and environmental implementation details.
3.
81
Thermal Specifications
Table 6-2.
Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile
Table
Power (W)
T
(°C)
CASE_MAX
35.0
35.9
36.9
37.8
38.7
39.7
40.6
41.5
42.5
43.0
44.4
45.3
46.2
47.2
48.1
49.0
50.0
50.9
51.8
52.8
53.7
54.6
55.6
56.5
57.4
58.4
59.3
60.2
61.2
62.1
63.0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
82
Thermal Specifications
Table 6-3.
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Specifications
Thermal
Design Power
(W)
Minimum
CASE
(°C)
Maximum
Core
Frequency
T
T
Notes
CASE
(°C)
Launch to FMB
120
5
See Figure 6-2; Table 6-4;
Table 6-5
1, 2, 3, 4, 5
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static V and I combination wherein V exceeds V at
CC
CC
CC
CC_MAX
specified ICC. Please refer to the loadline specifications in Section 2.13.1.
Thermal Design Power (TDP) should be used for the processor thermal solution design targets. TDP is not
2.
the maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based on silicon characterization.
Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® Processor
X5400 Series may be shipped under multiple VIDs for each frequency.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
.
CASE
3.
4.
5.
Figure 6-2. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profiles A and B
TCASE_MAX is a thermal solution design point. In actuality, units
will not significantly exceed TCASE_MAX_A due to TCC activation.
75
70
65
60
Thermal Profile B
Y = 0.221*x + 43.5
55
Thermal Profile A
Y = 0.168*x + 42.8
50
45
40
0
10
20
30
40
50
60
70
80
90
100
110
120
Pow er [W]
Notes:
1.
Thermal Profile A is representative of a volumetrically unconstrained platform. Please refer to Table 6-4 for
discrete points that constitute the thermal profile.
2.
Implementation of the Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A should result in
virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet Thermal Profile A
will result in increased probability of TCC activation and may incur measurable performance loss. (See
Section 6.2 for details on TCC activation).
3.
4.
Thermal Profile B is representative of a volumetrically constrained platform. Please refer to Table 6-5 for
discrete points that constitute the thermal profile.
Implementation of the Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile B will result in
increased probability of TCC activation and measurable performance loss. Furthermore, utilization of
thermal solutions that do not meet Thermal Profile B do not meet the processor’s thermal specifications
and may result in permanent damage to the processor.
5.
Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines
(TMDG) for system and environmental implementation details.
83
Thermal Specifications
Table 6-4.
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table
Power (W)
T
(°C)
CASE_MAX
42.8
43.6
44.5
45.3
46.2
47.0
47.8
48.7
49.5
50.0
51.2
52.0
52.9
53.7
54.6
55.4
56.2
57.1
57.9
58.8
59.6
60.4
61.3
62.1
63.0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
84
Thermal Specifications
Table 6-5.
Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile B Table
Power (W)
T
(°C)
CASE_MAX
43.5
44.6
45.7
46.8
47.9
49.0
50.1
51.2
52.3
53.4
54.6
55.7
56.8
57.9
59.0
60.1
61.2
62.3
63.4
64.5
65.6
66.7
67.8
68.9
70.0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
Table 6-6.
Quad-Core Intel® Xeon® Processor E5400 Series Thermal Specifications
Thermal
Design Power
(W)
Minimum
CASE
(°C)
Maximum
Core
Frequency
T
T
Notes
CASE
(°C)
Launch to FMB
80
5
See Figure 6-3; Table 6-7
1, 2, 3, 4, 5
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds V
at specified ICC. Please refer to the loadline specifications in Section 2.13.
Thermal Design Power (TDP) should be used for the processor thermal solution design targets. TDP is not
CC_MAX
2.
the maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based on silicon characterization.
.
CASE
3.
4.
Power specifications are defined at all VIDs found in Table 2-12. The Quad-Core Intel® Xeon® Processor
E5400 Series may be shipped under multiple VIDs for each frequency.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
5.
85
Thermal Specifications
Figure 6-3. Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
Thermal Profile
Y = 0.298*x + 43.2
0
10
20
30
40
50
60
70
80
Pow er [W]
Notes:
1.
2.
Please refer to Table 6-7 for discrete points that constitute the thermal profile.
Implementation of the Quad-Core Intel® Xeon® Processor 5400 Series Thermal Profile should result in
virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor
Thermal Profile will result in increased probability of TCC activation and may incur measurable performance
loss. (See Section 6.2 for details on TCC activation).
3.
Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines
(TMDG) for system and environmental implementation details.
Table 6-7.
Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile Table
(Sheet 1 of 2)
Power (W)
T
(°C)
CASE_MAX
43.5
45.0
46.4
47.9
49.4
50.9
52.3
53.8
55.3
56.7
58.2
59.7
61.1
62.6
0
5
10
15
20
25
30
35
40
45
50
55
60
65
86
Thermal Specifications
Table 6-7.
Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile Table
(Sheet 2 of 2)
Power (W)
T
(°C)
CASE_MAX
64.1
70
75
80
65.6
67.0
Table 6-8.
Quad-Core Intel® Xeon® Processor L5400 Series Thermal Specifications
Thermal Design
Power
Minimum
CASE
(°C)
Maximum
Core
Frequency
T
T
Notes
CASE
(°C)
(W)
Launch to FMB
50
5
See Figure 6-4; Table 6-9
1, 2, 3, 4, 5
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds V
at specified ICC. Please refer to the loadline specifications in Section 2.13.
CC_MAX
2.
3.
4.
5.
Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum T
.
CASE
These specifications are based pre-silicon estimates and simulations. These specifications will be updated
with characterized data from silicon measurements in a future release of this document.
Power specifications are defined at all VIDs found in Table 2-12. The Quad-Core Intel® Xeon® Processor
L5400 Series may be shipped under multiple VIDs for each frequency.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
Figure 6-4. Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile
60
58
56
54
52
50
Thermal Profile
Y = 0.298*x + 42.1
48
46
44
42
40
0
10
20
30
40
50
Power [W]
Notes:
1.
2.
Please refer to Table 6-9 for discrete points that constitute the thermal profile.
Implementation of the Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile should result in
virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor
Thermal Profile will result in increased probability of TCC activation and may incur measurable performance
loss. (See Section 6.2 for details on TCC activation).
3.
Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines
(TMDG) for system and environmental implementation details.
87
Thermal Specifications
Table 6-9.
Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile Table
Power (W)
T
(°C)
CASE_MAX
42.1
43.6
45.1
46.6
48.1
49.6
51.0
52.5
54.0
55.5
57.0
0
5
10
15
20
25
30
35
40
45
50
Table 6-10. Quad-Core Intel® Xeon® Processor L5408 Thermal Specifications
Thermal Design
Power
Minimum
Maximum
Core
Frequency
T
T
Notes
CASE
CASE
(W)
(°C)
(°C)
Launch to FMB
40
5
See Figure 6-5; Table 6-11
1, 2, 3, 4, 5
Notes:
1.
These values are specified at V
the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds V
at specified ICC. Please refer to the loadline specifications in Section 2.13.
for all processor frequencies. Systems must be designed to ensure
CC_MAX
CC_MAX
2.
3.
4.
5.
Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based pre-silicon estimates and simulations. These specifications will be updated
with characterized data from silicon measurements in a future release of this document.
Power specifications are defined at all VIDs found in Table 2-12. The Quad-Core Intel® Xeon® Processor
L5408 may be shipped under multiple VIDs for each frequency.
.
CASE
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
88
Thermal Specifications
Figure 6-5. Quad-Core Intel® Xeon® Processor L5408 Thermal Profile
Thermal Profile
90
Short-termThermal Profile may only be used for short term
excursions to higher ambient temperatures, not to exceed 360
hours per year
80
70
Short-TermThermal Profile
Tc = 0.678 * P+ 60
60
Nominal Ther mal Prof ile
Tc = 0.678 * P+ 45
50
40
0
5
10
15
20
25
30
35
40
Power [W]
Notes:
1.
2.
Please refer to Table 6-11 for discrete points that constitute the thermal profile.
Implementation of the Quad-Core Intel® Xeon® Processor L5408 Thermal Profile should result in virtually
no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal
Profile will result in increased probability of TCC activation and may incur measurable performance loss.
(See Section 6.2 for details on TCC activation).
3.
4.
The Nominal Thermal Profile must be used for all normal operating conditions, or for products that do not
require NEBS Level 3 compliance.
The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating
temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances
per year, as compliant with NEBS Level 3.
5.
6.
Utilization of a thermal solution that exceeds the Short-Term Thermal Profile, or which operates at the
Short-Term Thermal Profile for a duration longer than the limits specified in Note 4 above, do not meet the
processor’s thermal specifications and may result in permanent damage to the processor.
Refer to the Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications
Thermal/Mechanical Design Guidelines (TMDG) for system and environmental implementation details.
Table 6-11. Quad-Core Intel® Xeon® Processor L5408 Thermal Profile Table
Power (W)
Nominal T
(°C)
Short-term T
(°C)
CASE_MAX
CASE_MAX
0
45
48
52
55
59
62
65
69
72
60
5
63
67
70
74
77
80
84
87
10
15
20
25
30
35
40
89
Thermal Specifications
6.1.2
Thermal Metrology
The minimum and maximum case temperatures (TCASE) are specified in Table 6-2,
Table 6-4, Table 6-5, and Table 6-7, and Table 6-9 and Table 6-11 are measured at the
geometric top center of the processor integrated heat spreader (IHS). Figure 6-6
illustrates the location where TCASE temperature measurements should be made. For
detailed guidelines on temperature measurement methodology, refer to the Quad-Core
Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG).
Figure 6-6. Case Temperature (TCASE) Measurement Location
Note: Figure is not to scale and is for reference only.
6.2
Processor Thermal Features
®
6.2.1
Intel Thermal Monitor Features
Quad-Core Intel® Xeon® Processor 5400 Series provides two thermal monitor
features, Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2. The Intel® Thermal
Monitor 1 and Intel® Thermal Monitor 2 must both be enabled in BIOS for the
processor to be operating within specifications. When both are enabled, Intel® Thermal
Monitor 2 will be activated first and Intel® Thermal Monitor 1 will be added if Intel®
Thermal Monitor 2 is not effective.
6.2.1.1
Intel® Thermal Monitor 1
The Intel® Thermal Monitor 1 feature helps control the processor temperature by
activating the Thermal Control Circuit (TCC) when the processor silicon reaches its
maximum operating temperature. The TCC reduces processor power consumption as
90
Thermal Specifications
needed by modulating (starting and stopping) the internal processor core clocks. The
temperature at which the Intel® Thermal Monitor 1 activates the thermal control circuit
is not user configurable and is not software visible. Bus traffic is snooped in the normal
manner, and interrupt requests are latched (and serviced during the time that the
clocks are on) while the TCC is active.
When the Intel® Thermal Monitor 1 is enabled, and a high temperature situation exists
(that is, TCC is active), the clocks will be modulated by alternately turning the clocks
off and on at a duty cycle specific to the processor (typically 30 - 50%). Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With thermal solutions designed to the Quad-Core Intel® Xeon® Processor X5482,
Quad-Core Intel® Xeon® Processor X5400 Series, and Quad-Core Intel® Xeon®
Processor E5400 Series, and Quad-Core Intel® Xeon® Processor L5400 Series Thermal
Profile, it is anticipated that the TCC would only be activated for very short periods of
time when running the most power intensive applications. The processor performance
impact due to these brief periods of TCC activation is expected to be so minor that it
would be immeasurable. Refer to the Quad-Core Intel® Xeon® Processor 5400 Series
Thermal/Mechanical Design Guidelines (TMDG) for information on designing a thermal
solution.
The duty cycle for the TCC, when activated by the Intel® Thermal Monitor 1, is factory
configured and cannot be modified. The Intel® Thermal Monitor 1 does not require any
additional hardware, software drivers, or interrupt handling routines.
6.2.1.2
Intel® Thermal Monitor 2
The Quad-Core Intel® Xeon® Processor 5400 Series adds supports for an Enhanced
Thermal Monitor capability known as Intel® Thermal Monitor 2). This mechanism
provides an efficient means for limiting the processor temperature by reducing the
power consumption within the processor. Intel® Thermal Monitor 2 requires support for
dynamic VID transitions in the platform.
Note:
Not all Quad-Core Intel® Xeon® Processor 5400 Series are capable of supporting
Intel® Thermal Monitor 2. More detail on which processor frequencies will support
Intel® Thermal Monitor 2 will be provided in future releases of the Quad-Core Intel®
Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG) when
available. For more details also refer to the Intel® 64 and IA-32 Architectures Software
Developer’s Manual.
When Intel® Thermal Monitor 2 is enabled, and a high temperature situation is
detected, the Thermal Control Circuit (TCC) will be activated for both processor cores.
The TCC causes the processor to adjust its operating frequency (via the bus multiplier)
and input voltage (via the VID signals). This combination of reduced frequency and VID
results in a reduction to the processor power consumption.
A processor enabled for Intel® Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage, which is identical for both
processor cores. The first operating point represents the normal operating condition for
the processor. Under this condition, the core-frequency-to-system-bus multiplier
utilized by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID
that is specified in Table 2-3.
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Thermal Specifications
The second operating point consists of both a lower operating frequency and voltage.
The lowest operating frequency is determined by the lowest supported bus ratio (1/6
for the Quad-Core Intel® Xeon® Processor 5400 Series). When the TCC is activated,
the processor automatically transitions to the new frequency. This transition occurs
rapidly, on the order of 5 µs. During the frequency transition, the processor is unable to
service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered
interrupts will be latched and kept pending until the processor resumes operation at the
new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Intel® Thermal Monitor
2. During the voltage change, it will be necessary to transition through multiple VID
codes to reach the target operating voltage. Each step will be one VID table entry (see
Table 2-3). The processor continues to execute instructions during the voltage
transition. Operation at the lower voltage reduces the power consumption of the
processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to insure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 6-7 for an illustration of this ordering.
Figure 6-7. Intel® Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
fMAX
fTM2
Frequency
VNOM
VTM2
Vcc
Time
T(hysterisis)
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 is
enabled.
6.2.2
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Intel® Thermal Monitor 1 and Intel® Thermal
Monitor 2 features. On-Demand mode is intended as a means to reduce system level
power consumption. Systems utilizing the Quad-Core Intel® Xeon® Processor 5400
92
Thermal Specifications
Series must not rely on software usage of this mechanism to limit the processor
temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the
processor will immediately reduce its power consumption via modulation (starting and
stopping) of the internal core clock, independent of the processor temperature. When
using On-Demand mode, the duty cycle of the clock modulation is programmable via
bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty
cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5%
increments. On-Demand mode may be used in conjunction with the Thermal Monitor;
however, if the system tries to enable On-Demand mode at the same time the TCC is
engaged, the factory configured duty cycle of the TCC will override the duty cycle
selected by the On-Demand mode.
6.2.3
PROCHOT# Signal
An external signal, PROCHOT# (processor hot) is asserted when the processor die
temperature of any processor cores reaches its factory configured trip point. If Thermal
Monitor is enabled (note that Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software
Developer’s Manual for specific register and programming details.
PROCHOT# is designed to assert at or a few degrees higher than maximum TCASE when
dissipating TDP power, and cannot be interpreted as an indication of processor case
temperature. This temperature delta accounts for processor package, lifetime and
manufacturing variations and attempts to ensure the Thermal Control Circuit is not
activated below maximum TCASE when dissipating TDP power. There is no defined or
fixed correlation between the PROCHOT# trip temperature, or the case temperature.
Thermal solutions must be designed to the processor specifications and cannot be
adjusted based on experimental measurements of TCASE, or PROCHOT#.
6.2.4
FORCEPR# Signal
The FORCEPR# (force power reduction) input can be used by the platform to cause the
Quad-Core Intel® Xeon® Processor 5400 Series to activate the TCC. If the Thermal
Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR#
signal. Assertion of the FORCEPR# signal will activate TCC for all processor cores. The
TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an
asynchronous input. FORCEPR# can be used to thermally protect other system
components. To use the VR as an example, when FORCEPR# is asserted, the TCC
circuit in the processor will activate, reducing the current consumption of the processor
and the corresponding temperature of the VR.
It should be noted that assertion of FORCEPR# does not automatically assert
PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high
temperature situation is detected. A minimum pulse width of 500 µs is recommended
when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR#
signal may cause noticeable platform performance degradation.
Refer to the appropriate platform design guidelines for details on implementing the
FORCEPR# signal feature.
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Thermal Specifications
6.2.5
THERMTRIP# Signal
Regardless of whether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 is
enabled, in the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached an elevated temperature (refer to the
THERMTRIP# definition in Table 5-1). At this point, the FSB signal THERMTRIP# will go
active and stay active as described in Table 5-1. THERMTRIP# activation is independent
of processor activity and does not generate any bus cycles. Intel also recommends the
removal of VTT.
6.3
Platform Environment Control Interface (PECI)
6.3.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues.
Figure 6-8 shows an example of the PECI topology in a system with Quad-Core Intel®
Xeon® Processor 5400 Series. PECI uses CRC checking on the host side to ensure
reliable transfers between the host and client devices. Also, data transfer speeds across
the PECI interface are negotiable within a wide range (2Kbps to 2Mbps). The PECI
interface on the Quad-Core Intel® Xeon® Processor 5400 Series is disabled by default
and must be enabled through BIOS.
Figure 6-8. Quad-Core Intel® Xeon® Processor 5400 Series PECI Topology
P rocessor
(Socket 0)
0
x
3
0
D om ain0
G 5
0
x
3
0
D om ain1
P E C I H ost
C ontroller
P rocessor
(Socket 1)
0
x
3
1
D om ain0
0
x
3
1
G 5
D om ain1
6.3.1.1
T
and TCC Activation on PECI-based Systems
CONTROL
Fan speed control solutions based on PECI utilize a TCONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the TCONTROL value as negative. Thermal management algorithms
94
Thermal Specifications
should utilize the relative temperature value delivered over PECI in conjunction with the
CONTROL MSR value to control or optimize fan speeds. Figure 6-9 shows a conceptual
T
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the data below the onset
of thermal control circuit (TCC) activation as needed by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
Figure 6-9. Conceptual Fan Control Diagram of PECI-based Platforms
TCONTROL
Setting
TCC Activation
Temperature
Max
PECI = 0
Fan Speed
(RPM)
PECI = -10
Min
PECI = -20
Temperature
(not intended to depict actual implementation)
6.3.1.2
Processor Thermal Data Sample Rate and Filtering
The Digital Thermal Sensor (DTS) provides an improved capability to monitor device
hot spots, which inherently leads to more varying temperature readings over short time
intervals. The DTS sample interval range can be modified, and a data filtering algorithm
can be activated to help moderate this. The DTS sample interval range is 82us (default)
to 20 ms (max). This value can be set in BIOS.
To reduce the sample rate requirements on PECI and improve thermal data stability vs.
time the processor DTS also implements an averaging algorithm that filters the
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on
by default and can be turned off in BIOS.
Host controllers should utilize the min/max sample times to determine the appropriate
sample rate based on the controller's fan control algorithm and targeted response rate.
The key items to take into account when settling on a fan control algorithm are the DTS
sample rate, whether the temperature filter is enabled, how often the PECI host will
poll the processor for temperature data, and the rate at which fan speed is changed.
Depending on the designer’s specific requirements the DTS sample rate and alpha-beta
filter may have no effect on the fan control algorithm.
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Thermal Specifications
6.3.2
PECI Specifications
6.3.2.1
PECI Device Address
The PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that
each address also supports two domains (Domain0 and Domain1). For more
information on PECI domains, please refer to the Platform Environment Control
Interface (PECI) Specification.
6.3.2.2
6.3.2.3
PECI Command Support
PECI command support is covered in detail in Platform Environment Control Interface
Specification. Please refer to this document for details on supported PECI command
function and codes.
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where PECI is known to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damage. It is recommended that the PECI host controller take appropriate
action to protect the client processor device if valid temperature readings have not
been obtained in response to three consecutive gettemp()s or for a one second time
interval. The host controller may also implement an alert to software in the event of a
critical or continuous fault condition.
6.3.2.4
PECI GetTemp0() and GetTemp1() Error Code Support
The error codes supported for the processor GetTemp0() and GetTemp1() commands
are listed in Table 6-12 below:
Table 6-12. GetTemp0() GetTemp1()Error Codes
Error Code
Description
0x8000h
0x8002h
General sensor error
Sensor is operational, but has detected a temperature below its operational range
(underflow).
§
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Features
7 Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Quad-Core Intel®
Xeon® Processor 5400 Series samples its hardware configuration at reset, on the
active-to-inactive transition of RESET#. For specifics on these options, please refer to
Table 7-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All external resets
reconfigure the processor, for configuration purposes, the processor does not
distinguish between a “warm” reset (PWRGOOD signal remains asserted) and a
“power-on” reset.
Table 7-1.
Power-On Configuration Option Lands
Configuration Option
Output tri state
Land Name
Notes
SMI#
A3#
1,2
1,2
1,2
1,2
1,2
Execute BIST (Built-In Self Test)
Disable MCERR# observation
Disable BINIT# observation
Symmetric agent arbitration ID
A9#
A10#
BR[1:0]#
Notes:
1.
2.
Asserting this signal during RESET# will select the corresponding option.
Address lands not identified in this table as configuration options should not be asserted during RESET#.
Disabling of any of the cores within the Quad-Core Intel® Xeon® Processor 5400
Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR).
This MSR will allow for the disabling of a single core per die within the package.
7.2
Clock Control and Low Power States
The Quad-Core Intel® Xeon® Processor 5400 Series supports the Extended HALT state
(also referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce
power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See Figure 7-1 for a visual representation of the
processor low power states. The Extended HALT state is a lower power state than the
HALT state or Stop Grant state.
The Extended HALT state must be enabled via the BIOS for the processor to
remain within its specifications. For processors that are already running at the
lowest bus to core frequency ratio for its nominal operating point, the processor will
transition to the HALT state instead of the Extended HALT state.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. When the STPCLK# signal is asserted, the processor
enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
processor die. The chipset needs to account for a variable number of processors
asserting the Stop Grant SBC on the bus before allowing the processor to be
transitioned into one of the lower processor power states.
97
Features
7.2.1
7.2.2
Normal State
This is the normal operating state for the processor.
HALT or Extended HALT State
The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state
must be enabled for the processor to remain within its specifications. The
Extended HALT state requires support for dynamic VID transitions in the platform.
7.2.2.1
HALT State
HALT is a low power state entered when the processor have executed the HALT or
MWAIT instruction. When one of the processor cores execute the HALT or MWAIT
instruction, that processor core is halted; however, the other processor continues
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the
front side bus. RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT state. See the Intel® 64 and IA-32 Architecture Software
Developer's Manual.
The system can generate a STPCLK# while the processor is in the HALT state. When the
system deasserts STPCLK#, the processor will return execution to the HALT state.
While in HALT state, the processor will process front side bus snoops and interrupts.
7.2.2.2
Extended HALT State
Extended HALT state is a low power state entered when all processor cores have
executed the HALT or MWAIT instructions and Extended HALT state has been enabled
via the BIOS. When one of the processor cores executes the HALT instruction, that
processor core is halted; however, the other processor core continues normal
operation. The Extended HALT state is a lower power state than the HALT state or Stop
Grant state. The Extended HALT state must be enabled for the processor to remain
within its specifications.
The processor will automatically transition to a lower core frequency and voltage
operating point before entering the Extended HALT state. Note that the processor FSB
frequency is not altered; only the internal core frequency is changed. When entering
the low power state, the processor will first switch to the lower bus to core frequency
ratio and then transition to the lower voltage (VID).
While in the Extended HALT state, the processor will process bus snoops.
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Features
Table 7-2.
Extended HALT Maximum Power
Symbol
Parameter
Min
Typ
Max
Unit
Notes 1
P
Extended HALT State
Power
16
W
2
EXTENDED_HALT
Quad-Core Intel®
Xeon® Processor
X5482
P
Extended HALT State
Power
16
16/20
12
W
W
W
W
2
2,3
2
EXTENDED_HALT
Quad-Core Intel® Xeon®
Processor X5400 Series
P
Extended HALT State
Power
EXTENDED_HALT
Quad-Core Intel® Xeon®
Processor E5400 Series
P
Extended HALT State
Power
EXTENDED_HALT
Quad-Core Intel® Xeon®
Processor L5400 Series
P
Extended HALT State
Power
12
4
EXTENDED_HALT
Quad-Core Intel® Xeon®
Processor L5408
Notes:
1.
Processors running in the lowest bus ratio supported as shown in Table 2-1, will enter the HALT State when
the processor has executed the HALT or MWAIT instruction since the processor is already operating in the
lowest core frequency and voltage operating point.
o
2.
The specification is at Tcase = 40 C and nominal Vcc. The VID setting represents the maximum expected
VID when running in HALT state.
3.
4.
SKUs with Extended HALT state (16W) and without Extended HALT state (20W).
o
The specification is at Tcase = 46 C and nominal Vcc. The VID setting represents the maximum expected
VID when running in HALT state.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will first transition the VID to the original
value and then change the bus to core frequency ratio back to the original value.
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Features
Figure 7-1. Stop Clock State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Extended HALT or HALT State
Normal State
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
BCLK running
Snoops and interrupts allowed
Normal execution
Snoop
Event
Occurs Serviced
Snoop
Event
STPCLK#
Asserted
STPCLK#
De-asserted
Extended HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Snoop Event Occurs
Snoop Event Serviced
Stop Grant State
Stop Grant Snoop State
BCLK running
BCLK running
Snoops and interrupts allowed
Service snoops to caches
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no
later than 20 bus clocks after the response phase of the processor issued Stop Grant
Acknowledge special bus cycle. By default, the Quad-Core Intel® Xeon® Processor
5400 Series will issue two Stop Grant Acknowledge special bus cycles, one for each die.
Once the STPCLK# pin has been asserted, it may only be deasserted once the
processor is in the Stop Grant state. All processor cores will enter the Stop-Grant state
once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop
Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should
not be driven (allowing the level to return to VTT) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the front side bus
should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be
latched and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the front side bus (see Section 7.2.4.1).
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Features
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by
the processor, and only serviced when the processor returns to the Normal state. Only
one occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the front side bus and it
will latch interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
7.2.4
Extended HALT Snoop or HALT Snoop State,
Stop Grant Snoop State
The Extended HALT Snoop state is used in conjunction with the Extended HALT state. If
the Extended HALT state is not enabled in the BIOS, the default Snoop state entered
will be the HALT Snoop state. Refer to the sections below for details on HALT Snoop
state, Stop Grant Snoop state and Extended HALT Snoop state.
7.2.4.1
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop or interrupt transactions on the front side bus
while in Stop-Grant state or in HALT state. During a snoop or interrupt transaction, the
processor enters the HALT/Grant Snoop state. The processor will stay in this state until
the snoop on the front side bus has been serviced (whether by the processor or another
agent on the front side bus) or the interrupt has been latched. After the snoop is
serviced or the interrupt is latched, the processor will return to the Stop-Grant state or
HALT state, as appropriate.
7.2.4.2
Extended HALT Snoop State
The Extended HALT Snoop state is the default Snoop state when the Extended HALT
state is enabled via the BIOS. The processor will remain in the lower bus to core
frequency ratio and VID operating point of the Extended HALT state.
While in the Extended HALT Snoop state, snoops and interrupt transactions are handled
the same way as in the HALT Snoop state. After the snoop is serviced or the interrupt is
latched, the processor will return to the Extended HALT state.
7.3
Enhanced Intel SpeedStep® Technology
Quad-Core Intel® Xeon® Processor 5400 Series supports Enhanced Intel SpeedStep®
Technology. This technology enables the processor to switch between multiple
frequency and voltage points, which results in platform power savings. Enhanced Intel
SpeedStep Technology requires support for dynamic VID transitions in the platform.
Switching between voltage/frequency states is software controlled. For more
configuration details also refer to the Intel® 64 and IA-32 Architectures Software
Developer’s Manual.
Note:
Not all Quad-Core Intel® Xeon® Processor 5400 Series are capable of supporting
Enhanced Intel SpeedStep Technology. More details on which processor frequencies will
support this feature will be provided in the Quad-Core Intel® Xeon® Processor 5400
Series Specification Update.
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Features
Enhanced Intel SpeedStep Technology creates processor performance states (P-states)
or voltage/frequency operating points which are lower power capability states within
the Normal state (see Figure 7-1 for the Stop Clock State Machine for supported P-
states). Enhanced Intel SpeedStep Technology enables real-time dynamic switching
between frequency and voltage points. It alters the performance of the processor by
changing the bus to core frequency ratio and voltage. This allows the processor to run
at different core frequencies and voltages to best serve the performance and power
requirements of the processor and system. The Quad-Core Intel® Xeon® Processor
5400 Series has hardware logic that coordinates the requested voltage (VID) between
the processor cores. The highest voltage that is requested for either of the processor
cores is selected for that processor package. Note that the front side bus is not altered;
only the internal core frequency is changed. In order to run at reduced power
consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
• Multiple voltage/frequency operating points provide optimal performance at
reduced power consumption.
• Voltage/frequency selection is software controlled by writing to processor MSR’s
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, VCC is incremented
in steps (+12.5 mV) by placing a new value on the VID signals and the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and VCC is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
§
102
Boxed Processor Specifications
8 Boxed Processor Specifications
8.1
Introduction
Intel boxed processors are intended for system integrators who build systems from
components available through distribution channels. The Quad-Core Intel® Xeon®
Processor 5400 Series will be offered as an Intel boxed processor.
Intel will offer the Quad-Core Intel® Xeon® Processor 5400 Series with two heat sink
configurations available for each processor frequency: 1U passive/3U+ active
combination solution and a 2U passive only solution. The 1U passive/3U+ active
combination solution is based on a 1U passive heat sink with a removable fan that will
be pre-attached at shipping. This heat sink solution is intended to be used as either a
1U passive heat sink, or a 3U+ active heat sink. Although the active combination
solution with removable fan mechanically fits into a 2U keepout, its use is not
recommended in that configuration.
Quad-Core Intel® Xeon® Processor X5400 Series will include a copper 1U passive/3U+
active combination solution or a copper 2U passive heatsink. Quad-Core Intel® Xeon®
Processor E5400 Series and Quad-Core Intel® Xeon® Processor L5400 Series with
80W and lower TDPs will include an aluminum extruded 1U passive/3U+ active
combination solution or an aluminum extruded 2U passive heatsink.
The 1U passive/3U+ active combination solution in the active fan configuration is
primarily designed to be used in a pedestal chassis where sufficient air inlet space is
present and strong side directional airflow is not an issue. The 1U passive/3U+ active
combination solution with the fan removed and the 2U passive thermal solution require
the use of chassis ducting and are targeted for use in rack mount or pedestal servers.
The retention solution used for these products is called the Common Enabling Kit, or
CEK. The CEK base is compatible with both thermal solutions and uses the same hole
locations as the Intel® Xeon® processor with 800 MHz system bus.
The 1U passive/3U+ active combination solution will utilize a removable fan capable of
4-pin pulse width modulated (PWM) control. Use of a 4-pin PWM controlled active
thermal solution helps customers meet acoustic targets in pedestal platforms through
the motherboards’s ability to directly control the RPM of the processor heat sink fan.
See Section 8.3 for more details on fan speed control, and see Section 6.3 for more on
the PWM and PECI interface along with Digital Thermal Sensors (DTS). Figure 8-1
through Figure 8-3 are representations of the two heat sink solutions.
103
Boxed Processor Specifications
Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series
1U Passive/3U+ Active Combination Heat Sink (With Removable Fan)
Figure 8-2. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 2U Passive Heat Sink
104
Boxed Processor Specifications
Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5400 Series
Thermal Solution (Exploded View)
Notes:
1.
2.
3.
The heat sinks represented in these images are for reference only, and may not represent the final boxed
processor heat sinks.
The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components
in an exploded view.
It is intended that the CEK spring will ship with the base board and be pre-attached prior to shipping.
8.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed processor.
8.2.1
Boxed Processor Heat Sink Dimensions (CEK)
The boxed processor will be shipped with an unattached thermal solution. Clearance is
required around the thermal solution to ensure unimpeded airflow for proper cooling.
The physical space requirements and dimensions for the boxed processor and
assembled heat sink are shown in Figure 8-4 through Figure 8-8. Figure 8-9 through
Figure 8-10 are the mechanical drawings for the 4-pin board fan header and 4-pin
connector used for the active CEK fan heat sink solution.
105
Boxed Processor Specifications
Figure 8-4. Top Side Board Keepout Zones (Part 1)
106
Boxed Processor Specifications
Figure 8-5. Top Side Board Keepout Zones (Part 2)
107
Boxed Processor Specifications
Figure 8-6. Bottom Side Board Keepout Zones
108
Boxed Processor Specifications
Figure 8-7. Board Mounting-Hole Keepout Zones
109
Boxed Processor Specifications
Figure 8-8. Volumetric Height Keep-Ins
110
Boxed Processor Specifications
Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink)
111
Boxed Processor Specifications
Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink)
112
Boxed Processor Specifications
8.2.2
Boxed Processor Heat Sink Weight
8.2.2.1
Thermal Solution Weight
The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink
solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual
processor system will have up to 2010 grams total mass in the heat sinks. This large
mass will require a minimum chassis stiffness to be met in order to withstand force
during shock and vibration.
See Chapter 3 for details on the processor weight.
8.2.3
Boxed Processor Retention Mechanism and Heat Sink
Support (CEK)
Baseboards and chassis designed for use by a system integrator should include holes
that are in proper alignment with each other to support the boxed processor. Refer to
the Server System Infrastructure Specification (SSI-EEB 3.6, TEB 2.1 or CEB 1.1).
These specification can be found at: http://www.ssiforum.org.
Figure 8-3 illustrates the Common Enabling Kit (CEK) retention solution. The CEK is
designed to extend air-cooling capability through the use of larger heat sinks with
minimal airflow blockage and bypass. CEK retention mechanisms can allow the use of
much heavier heat sink masses compared to legacy limits by using a load path directly
attached to the chassis pan. The CEK spring on the secondary side of the baseboard
provides the necessary compressive load for the thermal interface material. The
baseboard is intended to be isolated such that the dynamic loads from the heat sink are
transferred to the chassis pan via the stiff screws and standoffs. The retention scheme
reduces the risk of package pullout and solder joint failures.
All components of the CEK heat sink solution will be captive to the heat sink and will
only require a Phillips screwdriver to attach to the chassis pan. When installing the
CEK, the CEK screws should be tightened until they will no longer turn easily. This
should represent approximately 6-8 inch-pounds of torque. More than that may
damage the retention mechanism components.
8.3
Electrical Requirements
8.3.1
Fan Power Supply (Active CEK)
The 4-pin PWM controlled thermal solution is being offered to help provide better
control over pedestal chassis acoustics. This is achieved though more accurate
measurement of processor die temperature through the processor’s Digital Thermal
Sensors. Fan RPM is modulated through the use of an ASIC located on the baseboard,
that sends out a PWM control signal to the 4th pin of the connector labeled as Control.
This thermal solution requires a constant +12 V supplied to pin 2 of the active thermal
solution and does not support variable voltage control or 3-pin PWM control. See
Table 8-2 for details on the 4-pin active heat sink solution connectors.
If the 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU
fan header it will default back to a thermistor controlled mode, allowing compatibility
with legacy 3-wire designs. When operating in thermistor controlled mode, fan RPM is
automatically varied based on the TINLET temperature measured by a thermistor
located at the fan inlet of the heat sink solution.
113
Boxed Processor Specifications
The fan power header on the baseboard must be positioned to allow the fan heat sink
power cable to reach it. The fan power header identification and location must be
documented in the suppliers platform documentation, or on the baseboard itself. The
baseboard fan power header should be positioned within 177.8 mm [7 in.] from the
center of the processor socket.
Table 8-1.
Table 8-2.
PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution
Description
Min Frequency
Nominal Frequency
Max Frequency
Unit
PWM Control
Frequency Range
21,000
25,000
28,000
Hz
Fan Specifications for 4-Pin Active CEK Thermal Solution
Typ
Steady
Max
Steady
Max
Startup
Description
Min
Unit
+12 V: 12 volt fan power supply
IC: Fan Current Draw
10.8
N/A
12
1
12
13.2
1.5
V
A
1.25
Pulses per fan
revolution
SENSE: SENSE frequency
2
2
2
2
Figure 8-11. Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution
Table 8-3.
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution
Pin Number
Signal
Color
1
2
3
4
Ground
Black
Yellow
Green
Blue
Power: (+12 V)
Sense: 2 pulses per revolution
Control: 21 KHz-28 KHz
8.3.2
Boxed Processor Cooling Requirements
As previously stated the boxed processor will be available in two product
configurations. Each configuration will require unique design considerations. Meeting
the processor’s temperature specifications is also the function of the thermal design of
the entire system, and ultimately the responsibility of the system integrator. The
processor temperature specifications are found in Chapter 6 of this document.
8.3.2.1
1U Passive/3U+ Active Combination Heat Sink Solution (1U Rack
Passive)
In the 1U configuration it is assumed that a chassis duct will be implemented to provide
a minimum airflow of 15 cfm at 0.38 in. H2O (25.5 m3/hr at 94.6 Pa) of flow
impedance. The duct should be carefully designed to minimize the airflow bypass
114
Boxed Processor Specifications
around the heatsink. It is assumed that a 40°C TLA is met. This requires a superior
chassis design to limit the TRISE at or below 5°C with an external ambient temperature
of 35°C. These specifications apply to both copper and aluminum heatsink solutions.
Following these guidelines allows the designer to meet Quad-Core Intel® Xeon®
Processor 5400 Series Thermal Profile and conform to the thermal requirements of the
processor.
8.3.2.2
1U Passive/3U+ Active Combination Heat Sink Solution (Pedestal
Active)
The active configuration of the combination solution is designed to help pedestal
chassis users to meet the thermal processor requirements without the use of chassis
ducting. It may be still be necessary to implement some form of chassis air guide or air
duct to meet the TLA temperature of 40°C depending on the pedestal chassis layout.
Also, while the active thermal solution design will mechanically fit into a 2U volumetric,
it may not provide adequate airflow. This is due to the requirement of additional space
at the top of the thermal solution to allow sufficient airflow into the heat sink fan. Use
of the active configuration in a 2U rackmount chassis is not recommended.
It is recommended that the ambient air temperature outside of the chassis be kept at
or below 35°C. The air passing directly over the processor thermal solution should not
be preheated by other system components. Meeting the processor’s temperature
specification is the responsibility of the system integrator.
8.3.2.3
2U Passive Heat Sink Solution (2U+ Rack or Pedestal)
In the 2U+ passive configuration, it is assumed that a chassis duct will be implemented
to provide a minimum airflow of 27 cfm at 0.182 in. H2O (45.9 m3/hr at 45.3 Pa) of
flow impedance. The duct should be carefully designed to minimize the airflow bypass
around the heatsink. These specifications apply to both copper and aluminum heatsink
solutions. The TLA temperature of 40°C should be met. This may require the use of
superior design techniques to keep TRISE at or below 5°C based on an ambient external
temperature of 35°C.
8.4
Boxed Processor Contents
A direct chassis attach method must be used to avoid problems related to shock and
vibration. The board must not bend beyond specification in order to avoid damage. The
boxed processor contains the components necessary to solve both issues. The boxed
processor will include the following items:
• Quad-Core Intel® Xeon® Processor 5400 Series
• Unattached heat sink solution
• Four screws, four springs, and four heat sink standoffs (all captive to the heat sink)
• Foam air bypass pad and skirt (included with 1U passive/3U+ active solution)
• Thermal interface material (pre-applied on heat sink)
• Installation and warranty manual
• Intel Inside Logo
Other items listed in Figure 8-3 that are required to complete this solution will be
shipped with either the chassis or boards. They are as follows:
• CEK Spring (supplied by baseboard vendors)
• Chassis standoffs (supplied by chassis vendors)
115
Boxed Processor Specifications
§
116
Debug Tools Specifications
9 Debug Tools Specifications
Please refer to the appropriate platform design guidelines for information regarding
debug tool specifications. Section 1.3 provides collateral details.
9.1
Debug Port System Requirements
The Quad-Core Intel® Xeon® Processor 5400 Series debug port is the command and
control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time
control of the processors for system debug. The debug port, which is connected to the
FSB, is a combination of the system, JTAG and execution signals. There are several
mechanical, electrical and functional constraints on the debug port that must be
followed. The mechanical constraint requires the debug port connector to be installed in
the system with adequate physical clearance. Electrical constraints exist due to the
mixed high and low speed signals of the debug port for the processor. While the JTAG
signals operate at a maximum of 75 MHz, the execution signals operate at the common
clock FSB frequency. The functional constraint requires the debug port to use the JTAG
system via a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-
control tools in Quad-Core Intel® Xeon® Processor 5400 Series-based system designs
including tools from vendors other than Intel.
Note:
The debug port and JTAG signal chain must be designed into the processor board to
utilize the XDP for debug purposes except for interposer solutions.
9.2
Target System Implementation
9.2.1
System Implementation
Specific connectivity and layout guidelines for the Debug Port are provided in the
appropriate platform design guidelines.
9.3
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Quad-Core Intel® Xeon® Processor 5400 Series systems.
Tektronix and Agilent should be contacted to obtain specific information about their
logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of Quad-Core Intel® Xeon® Processor 5400 Series-based
multiprocessor systems, the LAI is critical in providing the ability to probe and capture
FSB signals. There are two sets of considerations to keep in mind when designing a
Quad-Core Intel® Xeon® Processor 5400 Series-based system that can make use of
an LAI: mechanical and electrical.
117
Debug Tools Specifications
9.3.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI plugs into
the socket, while the processor plugs into a socket on the LAI. Cabling that is part of
the LAI egresses the system to allow an electrical connection between the processor
and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout
volume, as well as the cable egress restrictions, should be obtained from the logic
analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system. Note that it is possible that the keepout volume
reserved for the LAI may include differerent requirements from the space normally
occupied by the heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
9.3.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB, therefore it is critical to
obtain electrical load models from each of the logic analyzer vendors to be able to run
system level simulations to prove that their tool will work in the system. Contact the
logic analyzer vendor for electrical specifications and load models for the LAI solution
they provide.
§
118
Intel® Xeon® Processor 5400 Series, Features
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Intel® Xeon® Processor 5400 Series, Features
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More innovation - Improved value
Now featuring Intel's second-generation quad-core processor, existing mainstream server platforms, new high-performance computing
(HPC) systems, new workstations, and new business servers each delivers a unique combination of technology targeted at specific IT use
environments. By selecting a platform that is best tuned for the most common IT usages, Intel® servers are able to better optimize
return on investment while extending the leading performance and performance-per-watt advantages enjoyed when using Intel's proven
multi-core technology. Intel® Xeon® processor 54001 series help provide your data center or business with the performance headroom
needed to confidently consolidate applications onto fewer systems using proven virtualization solutions or the compute power necessary
for high-performance computing applications and workstation solutions.
Product matrix
Features and benefits
Thermal solution guide
Intel Xeon processor 5400 series:
Build success into your business performance
Performance:
●
●
●
Up to 25 percent better performance than previous generation quad-core2
Up to 2x better performance than dual-core3
Up to 5x increased performance over single-core4
Energy efficiency:
●
●
●
Up to 38 percent improvement in performance per watt vs. previous generation5
3 GHz quad-core at 80W
Lower idle power reduces system power
Reliability:
Intel-based servers have been a foundation of business technology for nearly 30 years and are built with more reliability features than c
●
For competitive application benchmarks please visit
http://www.intel.com/performance/server/xeon/server.htm?iid=perf_serv_dp_sum+server
The Intel Xeon processor 5400 series is compatible with Intel® 5400, 5100, 5000P, 5000V and 5000X series of chipsets. Server boards ba
optimized for quad core with advanced platform features of dual independent bus and fully buffered DIMM memory technology offering up
of current generation platforms. Improved I/O performance is possible with PCI Express* and the option of Intel® I/O Acceleration Techn
The Intel® Xeon® processor 52001 series is also available for those applications which are not able to take advantage of more than two p
compelling performance and power efficiency at an entry price point for two-socket servers and workstations.
Product briefs
●
Intel® Xeon® Processor 5400 Series product brief (PDF 989KB)
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Intel® Xeon® Processor 5400 Series, Features
●
Intel Xeon processor 5400 series animated product brief (PDF 5.84MB)
Server video demos
Intel Xeon processor 5000 sequence
●
Boxed Intel® Xeon Processor 5400 Series Product Matrix
Processor
Number
FSB
(MHz)
Number of
Cores
Boxed Product Code
Heatsink
Process
Frequency (TDP)
CACHE
D
AT80574KL096N (tray only) not included 45nm
EU80574KL088N (tray only) not included 45nm
X5492
X5482
3.40 GHz (150W)
3.20 GHz (150W)
1600
1600
12M total 4
12M total 4
Y
Y
AT80574KL088NT (tray
not included 45nm
only)
X5482
X5472
3.20 GHz (120W)
3.00 GHz (120W)
1600
1600
12M total 4
12M total 4
Y
Y
EU80574KL080NT (tray
not included 45nm
only)
EU80574KL080N (tray only) not included 45nm
E5472
X5470
X5470
E5462
X5460
X5460
X5450
X5450
E5450
E5450
E5440
E5440
E5430
E5430
L5420
L5420
E5420
E5420
L5410
L5410
E5410
E5410
E5405
E5405
X5272
3.00 GHz (80W)
3.33 GHz (120W)
3.33 GHz (120W)
2.80 GHz (80W)
3.16 GHz (120W)
3.16 GHz (120W)
3.00 GHz (120W)
3.00 GHz (120W)
3.00 GHz (80W)
3.00 GHz (80W)
2.83 GHz (80W)
2.83 GHz (80W)
2.66 GHz (80W)
2.66 GHz (80W)
2.50 GHz (50W)
2.50 GHz (50W)
2.50 GHz (80W)
2.50 GHz (80W)
2.33 GHz (50W)
2.33 GHz (50W)
2.33 GHz (80W)
2.33 GHz (80W)
2.00 GHz (80W)
2.00 GHz (80W)
3.40 GHz (80W)
1600
1333
1333
1600
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1333
1600
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
12M total 4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
BX80574X5470P
BX80574X5470A
EU80574KL072N
BX80574X5460P
BX80574X5460A
BX80574X5450P
BX80574X5450A
BX80574E5450P
BX80574E5450A
BX80574E5440P
BX80574E5440A
BX80574E5430P
BX80574E5430A
BX80574L5420P
BX80574L5420A
BX80574E5420P
BX80574E5420A
BX80574L5410P
BX80574L5410A
BX80574E5410P
BX80574E5410A
BX80574E5405P
BX80574E5405A
AT80573KL0966M
2U Passive
45nm
Active or 1U 45nm
not included 45nm
2U Passive
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
Active or 1U 45nm
2U Passive 45nm
45nm
Active or 1U 45nm
not included 45nm
6M total
2
Y
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Intel® Xeon® Processor 5400 Series, Features
AT80573KJ1006M
AT80573KJ0936M
AT80573JJ0806M
BX80574E5205A
BX80574E5205P
not included 45nm
X5270
X5260
L5240
E5205
E5205
3.50 GHz (80W)
3.33 GHz (80W)
3.20 GHz (40W)
1.86 GHz (65W)
1.86 GHz (65W)
1333
1333
1333
1066
1066
6M total
6M total
6M total
6M total
6M total
2
2
2
2
2
Y
Y
Y
Y
Y
not included 45nm
not included 45nm
Active or 1U 45nm
2U Passive
45nm
Back to Top
Intel® Xeon® Processor 5400 Series Features
Key Features
Benefits
●
●
45nm technology boosts performance on a range of work
Increased headroom for multi-threaded applications and
scenarios.
Multi-core processing
●
●
Helps boost system utilization through virtualization and
responsiveness.
Boosts performance on multiple applications, user enviro
demanding workloads, while enabling denser data center
improved performance per watt.
Enhanced Intel® Core™ microarchitecture
●
The new 45nm Enhanced Intel Core microarchitecture de
more performance per watt in the same platforms and at
level.6
●
●
Reduced idle processor power lowers average server pow
Increases efficiency of L2 cache-to-core data transfers, m
to processor bandwidth.
Up to 12 MB of on-die L2 cache
(2 x 6MB)
●
Reduces latency by storing larger data sets closer to the
number of trips to main memory.
●
●
Up to 6 MB of L2 cache can be allocated to one core.
A suite of processor enhancements that assists virtualiza
more efficient virtualization solutions and greater capabil
OS support.
Intel® Virtualization Technology7 (Intel® VT)
Fully buffered DIMM (FBDIMM) or native DDR2 registered DIMM technology
support (depending on chipset used)
●
●
Flexibility to optimize system for performance and capac
and power efficiency.
Next-generation improvements designed to significantly
across the entire platform through CPU utilization and lat
Intel® I/O Acceleration Technology (Intel® I/OAT) with next generation
improvements
●
New dedicated high-speed bus design enables increased
between each of the processors and the chipset.
Supporting from 1066 up to 1333 or 1600 MHz.
Enhanced Front-Side Bus (FSB)
●
●
Intel® 64 architecture8
Back to Top
Flexibility for 64-bit and 32-bit applications and operating
Boxed Intel® Xeon® Processor 5400 Series Thermal Solution Guide
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Intel® Xeon® Processor 5400 Series, Features
Ordering Code
Thermal Solution
Included with 120W CPUs
Chassis
BX80574xxxxxA10
Non-ducted pedestal or 1U chassis Examples:
Included with 80W and lower CPUs
SC5299-e
SR1500
SR1550
BX80574xxxxxP10
Included with 120W CPUs Included with 80W and lower CPUs Ducted pedestal or 2U chassis
Examples:
SC5400
SR2500
Back to Top
Please refer to the Integration Overview for detailed boxed Intel® Xeon® processor installation instructions. Please consult non-Intel chas
specific boxed Intel Xeon processor compatibility information.
Benchmark for Performance Comparison for the Intel Xeon processor 5400 series: SPECint*_ rate2006: X5460 vs X5365 - Published/mea
rate2006 - October 2, 2007 with 64-Bit SUSE LINUX* Enterprise Server 10 16 GB (8x2 GB). SPEC binaries built with Intel® Compiler 10.1
1 Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not a
families. See www.intel.com/products/processor_number for details.
2Intel® Xeon® processor 5300 series ("CTN"). Up to 25% (1.25x) higher performance X5460 vs X5365 - Published/measured results on S
07.
3 Intel® Xeon® processor 5100 series ("WDC"). Up to 119% (2.19x) higher performance X5460 vs 5160 - Published/measured results on
4 64-bit Intel® Xeon® processor 3.80GHz. Up to 443% (5.43x) higher performance X5460 vs Xeon 3.80 - Published/ measured results on
Oct 2, 07.
5Intel® Xeon® processor 5300 series ("CTN"). Up to 38% (1.38x) higher Perf/Watt E5450 vs E5335 - Published/measured results on SPE
6 Intel Server pre-production platform with twoIntel® Xeon® processor E5450 3.0 GHz, 2x6 MB L2 Cache or E5335, 2x4 MB L2 Cache, 13
Memory DDR2-667 FBDIMM, Microsoft Windows Server 2003 Enterprise* x64 Edition SP1 (64-bit), BEA JRockit* 5.0 P27.2.0. Intel interna
September 2007. Perf/Watt calculated by dividing the performance by measured system power during steady state window.
7 Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) an
platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations
update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
864-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and
Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor
Performance and competitive information is accurate at time of document publication. For latest competitive and performance information
www.intel.com/performance.
9 Backward compatibility for live VM migration also exists with current Intel® Core™ microarchitecture products (Xeon 5100 and Xeon 30
compatibility with future dual and multi-core processors. Contact your preferred VMM vendor for support requirements.
10 Insert processor number where "xxxxx" is located (ex X5355)
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