BXM80536GC1500F [INTEL]
RISC Microprocessor, 64-Bit, 1500MHz, CMOS, CPGA478;
| 型号： | BXM80536GC1500F |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 64-Bit, 1500MHz, CMOS, CPGA478 外围集成电路 |
| 文件： | 总84页 (文件大小：1488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Intel Pentium M Processor on
90 nm Process with 2-MB L2
Cache
Datasheet
January 2006
Document Number: 302189-008
®
IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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®
The Intel Pentium M processor on 90 nm process with 2-MB L2 cache may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across
different processor families. See www.intel.com/products/processor_number for details.
Intel, Pentium, Celeron, MMX, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004—2006, Intel Corporation. All rights reserved
2
Datasheet
Contents
1
Introduction....................................................................................................................................7
1.1
1.2
Terminology..........................................................................................................................9
References ...........................................................................................................................9
2
Low Power Features....................................................................................................................11
2.1
Clock Control and Low Power States .................................................................................11
2.1.1 Normal State..........................................................................................................11
2.1.2 AutoHALT Power-Down State ...............................................................................11
2.1.3 Stop-Grant State....................................................................................................12
2.1.4 HALT/Grant Snoop State.......................................................................................12
2.1.5 Sleep State ............................................................................................................13
2.1.6 Deep Sleep State...................................................................................................13
2.1.7 Deeper Sleep State ...............................................................................................14
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2.2
2.3
2.4
Enhanced Intel SpeedStep Technology ...........................................................................14
Front Side Bus Low Power Enhancements ........................................................................15
Processor Power Status Indicator (PSI#) Signal ................................................................15
3
Electrical Specifications .............................................................................................................17
3.1
Power and Ground Pins......................................................................................................17
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................17
Voltage Identification ..........................................................................................................17
Catastrophic Thermal Protection ........................................................................................18
Signal Terminations and Unused Pins................................................................................19
FSB Frequency Select Signals (BSEL[1:0]) .......................................................................19
FSB Signal Groups.............................................................................................................19
CMOS Signals ....................................................................................................................20
Maximum Ratings...............................................................................................................21
Processor DC Specifications ..............................................................................................21
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
5
Package Mechanical Specifications and Pin Information .......................................................47
4.1
4.2
Processor Pinout and Pin List.............................................................................................54
Alphabetical Signals Reference..........................................................................................70
Thermal Specifications and Design Considerations................................................................77
5.1
Thermal Specifications .......................................................................................................80
5.1.1 Thermal Diode .......................................................................................................80
5.1.2 Thermal Diode Offset.............................................................................................81
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5.1.3 Intel Thermal Monitor...........................................................................................82
Datasheet
3
Figures
2-1 Clock Control States...................................................................................................................11
3-1 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#A)............................31
3-2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#A) ...................32
3-3 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#B)............................33
3-4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#B) ...................34
3-5 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#C) ...........................35
3-6 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#C)...................36
3-7 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#D) ...........................37
3-8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#D)...................38
3-9 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#E)............................39
3-10Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#E) ...................40
3-11Active VCC and ICC Load Line ..................................................................................................43
3-12Deep Sleep VCC and ICC Load Line .........................................................................................44
4-1 Micro-FCPGA Package Top and Bottom Isometric Views .........................................................47
4-2 Micro-FCPGA Package - Top and Side Views...........................................................................48
4-3 Micro-FCPGA Package - Bottom View.......................................................................................49
4-4 Micro-FCBGA Package Top and Bottom Isometric Views .........................................................51
4-5 Micro-FCBGA Package Top and Side Views .............................................................................52
4-6 Micro-FCBGA Package Bottom View.........................................................................................54
4-7 The Coordinates of the Processor Pins as Viewed from the Top of the Package......................55
4
Datasheet
Tables
1-1 References ...................................................................................................................................9
3-1 Voltage Identification Definition ..................................................................................................18
3-2 FSB Pin Groups..........................................................................................................................20
3-3 Processor DC Absolute Maximum Ratings.................................................................................21
3-4 Voltage and Current Specifications - Standard Voltage Processors ..........................................22
3-5 Voltage and Current Specifications - Low Voltage Processors ..................................................24
3-6 Voltage and Current Specifications - Ultra Low Voltage Processors..........................................26
3-7 Voltage and Current Specifications (Continued).........................................................................28
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3-8 Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#A ........................31
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3-9 Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#A ...............32
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3-10Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#B ........................33
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3-11Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#B ...............34
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3-12Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#C........................35
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3-13Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#C...............36
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3-14Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#D........................37
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3-15Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#D...............38
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3-16Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#E ........................39
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3-17Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#E ...............40
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3-18Voltage Tolerances for the Intel Pentium M Processor LV (Active State) ..............................41
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3-19Voltage Tolerances for the Intel Pentium M Processor LV (Deep Sleep State) .....................42
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3-20Voltage Tolerances for the Intel Pentium M Processor ULV (Active State)............................42
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3-21Voltage Tolerances for the Intel Pentium M Processor ULV (Deep Sleep State)...................43
3-22FSB Differential BCLK Specifications.........................................................................................44
3-23AGTL+ Signal Group DC Specifications.....................................................................................45
3-24CMOS Signal Group DC Specifications......................................................................................45
3-25Open Drain Signal Group DC Specifications..............................................................................46
4-1 Micro-FCPGA Package Dimensions...........................................................................................50
4-2 Micro-FCBGA Package Dimensions...........................................................................................53
4-3 Pin Listing by Pin Name..............................................................................................................57
4-4 Pin Listing by Pin Number ..........................................................................................................63
4-5 Signal Description.......................................................................................................................70
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5-1 Power Specifications for the Intel Pentium M Processor..........................................................78
5-2 Thermal Diode Interface .............................................................................................................81
5-3 Thermal Diode Specification.......................................................................................................81
Datasheet
5
Revision History
Revision
Description
Date
001
002
Initial release of datasheet
May 2004
June 2004
Added Intel® Pentium® M processor 725 and 715 specifications
•
•
•
Specifications of Intel® Pentium® M processor Low Voltage 738
and Ultra Low Voltage 733 & 723 added in chapter 3 and chapter
5.
Chapter 2 section 2.1.3 - Missing Stop Grant State title added.
Description was previously merged with Auto Halt state section
and is unchanged.
003
004
July 2004
Table 4 - Max ratings specifications updated
Added Intel® Pentium® M processor 765 specifications
October 2004
•
•
Added Intel® Pentium® M processor 753 and 758 specifications
Added Execute Disable support feature and lead free SLI
(second layer interconnect) Micro-FCPGA packaging
information in chapter 1
005
January 2005
•
•
Added Table 3-20 AGTL + Signal Group Signal DC
Specifications
Table 3-18 - Voltage Tolerances for Intel® Pentium®
processor ULV (Deep Sleep State) updated
M
006
007
008
•
Added Intel® Pentium® M processor 778 specifications
July 2005
July 2005
Updated Intel® Pentium® M processor 753 and 733J specifications
for optimized VID
Added Intel® Pentium® M processor 773 specifications
January 2006
§
6
Datasheet
Introduction
1 Introduction
The Intel® Pentium® M processor based on 90 nm process technology featuring 2-MB L2 cache
and 400-MHz front side bus (FSB) is the next generation high- performance, low-power mobile
processor based on the Intel® Pentium® processor architecture.
Throughout this document, Intel Pentium M processor based on 90 nm technology featuring 2-MB
L2 cache and 400 MHz FSB will be referred to as Pentium M processor, or simply the processor,
including low voltage and ultra low voltage processors.
This document contains specifications for the Pentium M processors 765/ 755/ 745/ 735/ 725/ 715
Δ
Standard Voltage, 778/758/738 Low Voltage and 773/753/733J/733/723 Ultra Low Voltage .
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate
features within each processor family, not across different processor families. See www.intel.com/
products/processor_number for details.
The following list provides some of the key features on this processor:
• Supports Intel® Architecture with Dynamic Execution
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache
• On-die, 2 MB second level cache with Advanced Transfer Cache Architecture
• Way set associativity and ECC (Error Correcting Code) support
• Data Prefetch Logic
• Streaming SIMD extensions 2 (SSE2)
• 400 MHz, source-synchronous FSB
• Advanced power management features including Enhanced Intel SpeedStep® technology
• Micro-FCPGA and Micro-FCBGA packaging technologies
• Manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect.
• Support for MMX™ technology and Internet Streaming SIMD instructions
• The processor’s data prefetch logic fetches data to the L2 cache before L1 cache requests
occurs, resulting in reduced bus cycle penalties and improved performance
• Micro-FCPGA and Micro-FCBGA packaging technologies, including lead free SLI (second
level interconnect) technology for the Micro-FCBGA package (for Pentium M processors 755,
745, 778, 758, 738, 773, 753, 733J/733, 723)
• Execute Disable Bit support for enhanced security (available on processors with CPU
Signature = 06D8h and recommended for implementation on Intel® 915 Express chipset
family-based platforms only)
The Pentium M processor will be manufactured on Intel’s advanced 90 nm process technology
with copper interconnect. The processor maintains support for MMX technology and Internet
Streaming SIMD instructions and full compatibility with IA-32 software. The on-die, 32-KB
Level 1 instruction and data caches along with the 2-MB L2 cache with advanced transfer cache
Datasheet
7
Introduction
architecture enable significant performance improvement over existing mobile processors. The
processor’s data prefetch logic fetches data to the L2 cache before L1 cache requests occurs,
resulting in reduced bus cycle penalties and improved performance.
The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
The Pentium M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The
400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced
Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling
technology with low power enhancements.
The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic
switching between multiple voltage and frequency points. This results in optimal performance
without compromising low power. The processor features the Auto Halt, Stop Grant, Deep Sleep,
and Deeper Sleep low power states.
The Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and
surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-
FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is
referred to as the mPGA479M socket.
Pentium M processors with CPU Signature = 06D8h will also include the Execute Disable Bit
capability. This feature combined with a support operating system allows memory to be marked as
executable or non executable. If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the
system. See the Intel® Architecture Software Developer's Manual for more detailed information.
Intel will validate this feature only on Intel 915 Express chipset family based platforms and
recommends customers implement BIOS changes related to this feature, only on Intel 915 Express
chipset family based platforms.
Note: The term AGTL+ is used to refer to Assisted GTL+ signalling technology on some Intel processors.
8
Datasheet
Introduction
1.1
Terminology
Term
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the “#” symbol implies
that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and
D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also known as
the chipset components).
1.2
References
Material and concepts available in the following documents may be beneficial when reading this
document. Please note that “platform design guides,” when used throughout this document, refers
to the platform design guides listed below:
Table 1-1. References (Sheet 1 of 2)
Document Number/
Location1
Document
Intel® Pentium® M Processor on 90 nm Process with 2-MB L2 Cache -
Specification Update
http://www.intel.com/
design/mobile/specupdt/
302209.htm
Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset Datasheet
http://www.intel.com/
design/mobile/datashts/
305264.htm
Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset Specification
Update
http://www.intel.com/
design/mobile/specupdt/
307167.htm
Intel®855PM Chipset Platform Design Guide: For use with Intel®Pentium® M and http://developer.intel.com/
Intel®Celeron®Processors
design/mobile/desguide/
252614.htm
Intel® 855PM Chipset Memory Controller Hub (MCH) Datasheet
http://developer.intel.com/
design/chipsets/datashts/
252613.htm
Intel® 855PM Chipset MCH DDR 333/200/266 MHz Specification Update
http://developer.intel.com/
design/chipsets/specupdt/
253488.htm
Intel® 855GM/GME Chipset Graphics and Memory Controller Hub (GMCH)
Datasheet
http://developer.intel.com/
design/chipsets/datashts/
252615.htm
Intel® 855GM/GME Chipset Graphics and Memory Controller Hub (GMCH)
Chipset Specification Update
http://developer.intel.com/
design/chipsets/specupdt/
253572.htm
Intel®855GM/855GME Chipset Platform Design Guide
http://developer.intel.com/
design/mobile/desguide/
252616.htm
Datasheet
9
Introduction
Table 1-1. References (Sheet 2 of 2)
Document Number/
Location1
Document
IA-32 Intel® Architecture Software Developer's Manual
Volume 1: Basic Architecture
http://www.intel.com/
design/pentium4/
manuals/index_new.htm
Volume 2A: Instruction Set Reference
Volume 2B: Instruction Set Reference
Volume 3: System Programming Guide
NOTE: Contact your Intel representative for the latest revision and document number of this document.
§
10
Datasheet
Low Power Features
2 Low Power Features
2.1
Clock Control and Low Power States
The Pentium M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep Sleep,
and Deeper Sleep states for optimal power management. See Figure 2-1 for a visual representation
of the processor low-power states.
Figure 2-1. Clock Control States
SLP# asserted
STPCLK# asserted
Stop
Grant
Normal
Sleep
STPCLK# deasserted
SLP# deasserted
STPCLK#
asserted
halt
break
DPSLP#
de-asserted
DPSLP#
asserted
snoop
serviced
HLT
snoop
occurs
STPCLK#
deasserted
instruction
core voltage raised
snoop
occurs
HALT/
Grant
Snoop
Deeper
Sleep
Deep
Sleep
Auto Halt
snoop
serviced
core voltage lowered
V0001-04
Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
2.1.1
2.1.2
Normal State
This is the normal operating state for the processor.
AutoHALT Power-Down State
AutoHALT Power-Down is a low-power state entered when the processor executes the HALT
instruction. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to
immediately initialize itself.
A system management interrupt (SMI) handler will return execution to either Normal state or the
®
AutoHALT Power-Down state. See the IA-32 Intel Architecture Software Developer's Manual,
Volume 3: System Programmer's Guide for more information.
Datasheet
11
Low Power Features
The system can generate a STPCLK# while the processor is in the AutoHALT Power-Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
While in AutoHALT Power-Down state, the processor will process bus snoops and interrupts.
2.1.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven
(allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the FSB should be driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be
deasserted ten or more bus clocks after the de-assertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
FSB (see Section 2.1.3). A transition to the Sleep state (see Section 2.1.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the Normal State. Only one occurrence of each event
will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts
delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
2.1.4
HALT/Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop-Grant state or
in AutoHALT Power-Down state. During a snoop or interrupt transaction, the processor enters the
HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been
serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched.
After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant
state or AutoHALT Power-Down state, as appropriate.
12
Datasheet
Low Power Features
2.1.5
Sleep State
A low power state in which the processor maintains its context, maintains the phase-locked loop
(PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant
state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the
SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state.
SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may
result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or
RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state by asserting the DPSLP# pin. (See Section 2.1.6.) While the processor is in the Sleep
state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.6
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped
during the Deep Sleep state for additional platform level power savings.
BCLK stop/restart timings on 855PM and Intel 855GM chipset-based platforms are as follows:
• Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock
chip will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds.
• Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The platform clock
chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6
BCLK periods later.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after
DPSLP# deassertion, as described above. A period of 30 microseconds (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in
Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant
state will result in unpredictable behavior.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.
Datasheet
13
Low Power Features
2.1.7
Deeper Sleep State
The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
to the platform design guides listed in Table 1-1.
®
2.2
Enhanced Intel SpeedStep Technology
The Pentium M processor features Enhanced Intel SpeedStep technology. Unlike previous
implementations of Intel SpeedStep technology, this technology enables the processor to switch
between multiple frequency and voltage points instead of two. This will enable superior
performance with optimal power savings. Switching between states is software controlled unlike
previous implementations where the GHI# pin is used to toggle between two states. Following are
the key features of Enhanced Intel SpeedStep technology:
• Multiple voltage/frequency operating points provide optimal performance at the lowest power.
• Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model
Specific Registers) thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, Vcc is ramped up by placing a
new value on the VID pins and the PLL then locks to the new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the new
frequency and the Vcc is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in progress, the
new transition is deferred until its completion.
• The processor controls voltage ramp rates internally to ensure glitch free transitions.
• Low transition latency and large number of transitions possible per second.
— Processor core (including L2 cache) is unavailable for up to 10 μs during the frequency
transition
— The bus protocol (BNR# mechanism) is used to block snooping
• No bus master arbiter disable required prior to transition and no processor cache flush
necessary.
• Improved Intel® Thermal Monitor mode.
— When the on-die thermal sensor indicates that the die temperature is too high, the
processor can automatically perform a transition to a lower frequency/voltage specified in
a software programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to acceptable
levels, an up transition to the previous frequency/voltage point occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling
better system level thermal management.
14
Datasheet
Low Power Features
2.3
Front Side Bus Low Power Enhancements
The Pentium M processor incorporates the following front side bus (processor system bus) low
power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic On Die Termination disabling
• Low VCCP (I/O termination voltage)
The Pentium M processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates them only
when data bus activity occurs, resulting in significant power savings with no performance impact.
BPRI# control also allows the processor address and control input buffers to be turned off when the
BPRI# signal is inactive. The on-die termination on the processor FSB buffers is disabled when the
signals are driven low, resulting in additional power savings. The low I/O termination voltage is on
a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all
times.
2.4
Processor Power Status Indicator (PSI#) Signal
The Pentium M processor incorporates the PSI# signal that is asserted when the processor is in a
low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and
deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator,
resulting in platform power savings and extended battery life. PSI# can also be used to simplify
voltage regulator designs since it removes the need for integrated 100 μs timers required to mask
the PWRGOOD signal during Deeper Sleep transitions. It also helps loosen PWRGOOD
monitoring requirements in the Deeper Sleep state.
§
Datasheet
15
Low Power Features
16
Datasheet
Electrical Specifications
3 Electrical Specifications
3.1
Power and Ground Pins
For clean, on-chip power distribution, the Pentium M processor has a large number of VCC (power)
and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins
must be connected to system ground planes. Use of multiple power and ground planes is
recommended to reduce I*R drop. Please refer to the platform design guides for more details. The
processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.1.1
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Pentium M processor core frequency is a
multiple of the BCLK[1:0] frequency. In regards to processor clocking, the Pentium M processor
uses a differential clocking implementation.
3.2
Voltage Identification
The Pentium M processor uses six voltage identification pins, VID[5:0], to support automatic
selection of power supply voltages. The VID pins for the Pentium M processor are CMOS outputs
driven by the processor VID circuitry. Table 3-1 specifies the voltage level corresponding to the
state of VID[5:0]. A “1” in this refers to a high-voltage level and a “0” refers to low-voltage level.
Datasheet
17
Electrical Specifications
Table 3-1. Voltage Identification Definition
VID
VID
VCC
V
VCC
V
5
4
3
2
1
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.708
1.692
1.676
1.660
1.644
1.628
1.612
1.596
1.580
1.564
1.548
1.532
1.516
1.500
1.484
1.468
1.452
1.436
1.420
1.404
1.388
1.372
1.356
1.340
1.324
1.308
1.292
1.276
1.260
1.244
1.228
1.212
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.196
1.180
1.164
1.148
1.132
1.116
1.100
1.084
1.068
1.052
1.036
1.020
1.004
0.988
0.972
0.956
0.940
0.924
0.908
0.892
0.876
0.860
0.844
0.828
0.812
0.796
0.780
0.764
0.748
0.732
0.716
0.700
3.3
Catastrophic Thermal Protection
The Pentium M processor supports the THERMTRIP# signal for catastrophic thermal protection.
An external thermal sensor should also be used to protect the processor and the system against
excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor
internal clocks and activity, leakage current can be high enough such that the processor cannot be
protected in all conditions without the removal of power to the processor. If the external thermal
sensor detects a catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP#
signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent
permanent silicon damage due to thermal runaway.
18
Datasheet
Electrical Specifications
3.4
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future Pentium M processors. See Section 4.2 for a pin listing of the processor and the
location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Unused active high inputs should be connected through a resistor
to ground (VSS). Unused outputs can be left unconnected.
For details on signal terminations, please refer to the platform design guides.
The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1-kΩ,
pull-down resistors.
3.5
3.6
FSB Frequency Select Signals (BSEL[1:0])
These signals are used to select the FSB clock frequency. They should be connected between the
processor and the chipset MCH and clock generator on Intel 915 Express chipset family based
platforms. These signals must be left unconnected on platforms designed with the Intel 855 chipset
family. On these platforms, FSB clock frequency should be configured on the motherboard.
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 3-2 identifies which signals are common clock, source
synchronous, and asynchronous.
Datasheet
19
Electrical Specifications
Table 3-2. FSB Pin Groups
Signal Group
Type
Signals1
AGTL+ Common Clock Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,
TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, PRDY#
AGTL+ Source Synchronous I/O Synchronous
to assoc.
strobe
Signals
Associated Strobe
ADSTB[0]#
REQ[4:0]#, A[16:3]#
A[31:17]#
ADSTB[1]#
D[15:0]#, DINV0#
D[31:16]#, DINV1#
D[47:32]#, DINV2#
D[63:48]#, DINV3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobes
CMOS Input
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output
CMOS Output
CMOS Input
Asynchronous FERR#, IERR#, PROCHOT#, THERMTRIP#
Asynchronous PSI#, VID[5:0], BSEL[1:0]
Synchronous
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output
Synchronous
to TCK
TDO
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]2
Power/Other
COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,
THERMDA, THERMDC, VCC, VCCA[3:0], VCCP, VCCQ[1:0],
V
CC_SENSE, VSS, VSS_SENSE
NOTES:
1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. BPM[2:0}# and PRDY# are AGTL+ output only signals.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
3.7
CMOS Signals
CMOS input signals are shown in Table 3-2. Legacy output FERR#, IERR# and other non-AGTL+
signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not
have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals
are required to be asserted for at least three BCLKs in order for the processor to recognize them.
See Section 3.9 for the DC and AC specifications for the CMOS signal groups.
20
Datasheet
Electrical Specifications
3.8
Maximum Ratings
Table 3-3 lists the processor’s maximum environmental stress ratings. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from electro
static discharge (ESD), one should always take precautions to avoid high static voltages or electric
fields.
Table 3-3. Processor DC Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage
temperature
-40
85
°C
2
VCC
Any processor supply
voltage with respect to VSS
-0.3
-0.1
-0.1
1.6
1.6
1.6
V
V
V
1
VinAGTL+
AGTL+ buffer DC input
voltage with respect to VSS
1, 2
1, 2
VinAsynch_CMOS CMOS buffer DC input
voltage with respect to VSS
NOTES:
1. This rating applies to any processor pin.
2. Contact Intel for storage requirements in excess of one year.
3.9
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless
noted otherwise. See Table 4-3 for the pin signal definitions and signal pin assignments. The DC
specifications for these signals are listed in Table 3-24 and Table 3-25.
Table 3-4 through Table 3-25 list the DC specifications for the Pentium M processor and are valid
only while meeting specifications for junction temperature, clock frequency, and input voltages.
The Highest Frequency mode (HFM) and Lowest Frequency mode (LFM) refer to the highest and
lowest core operating frequencies supported on the processor. Active mode load line specifications
apply in all states except in the Deep Sleep and Deeper Sleep states. V
is the default
CC,BOOT
voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified
otherwise, all specifications for the Pentium M processor are at Tjunction = 100° C. Care should be
taken to read all notes associated with each parameter.
Datasheet
21
Electrical Specifications
Table 3-4. Voltage and Current Specifications - Standard Voltage Processors (Sheet 1 of 2)
VID#A
Typical
VID#B
Typical
VID#C
Typical
VID#D
Typical
VID#E
Typical
Symbol
Parameter
Unit
Notes
VCCD765
Intel® Pentium® M Processor
765 Core VCC FOR Enhanced
Intel SpeedStep® Technology
Operating Points:
V
1, 2
2.1 GHz
1.8 GHz
1.6 GHz
1.4 GHz
1.2 GHz
1.0 GHz
800 MHz
600 MHz
1.340
1.276
1.228
1.180
1.132
1.084
1.036
0.988
1.324
1.260
1.212
1.180
1.132
1.084
1.036
0.988
1.308
1.244
1.212
1.164
1.116
1.084
1.036
0.988
1.356
1.292
1.244
1.196
1.148
1.100
1.052
0.988
VCCD755
Pentium M Processor 755
Core VCC for Enhanced Intel
SpeedStep Technology
Operating Points:
V
1, 2
2.0 GHz
1.8 GHz
1.6 GHz
1.4 GHz
1.2 GHz
1.0 GHz
800 MHz
600 MHz
1.340
1.292
1.244
1.196
1.148
1.100
1.052
0.988
1.324
1.276
1.228
1.180
1.132
1.084
1.036
0.988
1.308
1.276
1.228
1.180
1.132
1.084
1.036
0.988
1.276
1.244
1.196
1.164
1.116
1.084
1.036
0.988
VCCD745
Pentium M Processor 745
Core VCC for Enhanced Intel
SpeedStep Technology
Operating Points:
V
1, 2
1.8 GHz
1.6 GHz
1.4 GHz
1.2 GHz
1.0 GHz
800 MHz
600 MHz
1.340
1.292
1.228
1.164
1.116
1.052
0.988
1.324
1.276
1.212
1.164
1.100
1.052
0.988
1.308
1.260
1.212
1.148
1.100
1.052
0.988
1.276
1.228
1.180
1.132
1.084
1.036
0.988
22
Datasheet
Electrical Specifications
Table 3-4. Voltage and Current Specifications - Standard Voltage Processors (Sheet 2 of 2)
VID#A
Typical
VID#B
Typical
VID#C
Typical
VID#D
Typical
VID#E
Typical
Symbol
Parameter
Unit
Notes
VCCD735
Pentium M Processor 735
Core VCC for Enhanced Intel
SpeedStep Technology
Operating Points:
V
1, 2
1.7 GHz
1.4 GHz
1.2 GHz
1.0 GHz
800 MHz
600 MHz
1.340
1.244
1.180
1.116
1.052
0.988
1.324
1.244
1.180
1.116
1.052
0.988
1.308
1.228
1.164
1.116
1.052
0.988
1.276
1.212
1.148
1.100
1.052
0.988
VCCD725
Pentium M Processor 725
Core VCC for Enhanced Intel
SpeedStep Technology
Operating Points:
V
1, 2
1.6 GHz
1.4 GHz
1.2 GHz
1.0 GHz
800 MHz
600 MHz
1.340
1.276
1.212
1.132
1.068
0.988
1.324
1.260
1.196
1.132
1.068
0.988
1.308
1.244
1.180
1.116
1.052
0.988
1.276
1.228
1.164
1.116
1.052
0.988
VCCD715
Pentium M Processor 715
Core VCC for Enhanced Intel
SpeedStep Technology
Operating Points:
V
1, 2
1.5 GHz
1.2 GHz
1.0 GHz
800 MHz
600 MHz
1.340
1.228
1.148
1.068
0.988
1.324
1.212
1.148
1.068
0.988
1.308
1.212
1.132
1.068
0.988
1.276
1.180
1.116
1.052
0.988
NOTES:
1. The typical values shown are the VID encoded voltages. Static and ripple tolerances (for minimum and
maximum voltages) are defined in the load line tables, Table 3-8 through Table 3-21. Adherence to loadline
specifications for the Pentium M processor is required to ensure reliable processor operation.
2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
Datasheet
23
Electrical Specifications
Table 3-5. Voltage and Current Specifications - Low Voltage Processors (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Note
1, 2
VCCD778
Intel® Pentium®
M
V
Processor, Low Voltage
778 Core VCC for
Enhanced Intel
SpeedStep® Technology
Operating Points:
1.6 GHz
1.5 GHz
1.4 GHz
1.3 GHz
1.2 GHz
1.1 GHz
1.0 GHz
900 GHz
800 MHz
600 MHz
1.116
1.116
1.100
1.084
1.068
1.052
1.052
1.036
1.020
0.988
VCCD758
Pentium M Processor,
Low Voltage,
V
1, 2
758 Core VCC for
Enhanced Intel
SpeedStep Technology
Operating Points:
1.5 GHz
1.4 GHz
1.3 GHz
1.2 GHz
1.1 GHz
1.0 GHz
900 GHz
800 MHz
600 MHz
1.116
1.116
1.100
1.084
1.068
1.052
1.036
1.020
0.988
24
Datasheet
Electrical Specifications
Table 3-5. Voltage and Current Specifications - Low Voltage Processors (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Note
1, 2
VCCD738
Pentium M Processor,
Low Voltage,
V
738 Core VCC for
Enhanced Intel
SpeedStep Technology
Operating Points:
1.4 GHz
1.3 GHz
1.2 GHz
1.1 GHz
1.0 GHz
900 GHz
800 MHz
600 MHz
1.116
1.116
1.100
1.068
1.052
1.036
1.020
0.988
NOTES:
1. The typical values shown are the VID encoded voltages. Static and ripple tolerances (for minimum and
maximum voltages) are defined in the load line tables, Table 3-8 through Table 3-21. Adherence to loadline
specifications for the Pentium M processor is required to ensure reliable processor operation.
2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
Datasheet
25
Electrical Specifications
Table 3-6. Voltage and Current Specifications - Ultra Low Voltage Processors (Sheet 1 of 2)
VID#
GTyp HTyp
VID# VID#I VID#
VID#
VID#
Symbol
Parameter
Min
Typ
Max
Unit
Note
Typ J Typ K Typ L Typ
VCCD773
Intel® Pentium®
Processor, Ultra Low
Voltage,
M
V
2, 3
773 Core VCC for
Enhanced Intel
SpeedStep®
Technology Operating
Points:
1.3 GHz
1.2 GHz
1.1 GHz
1.0 GHz
900 MHz
800 MHz
600 MHz
0.956 0.940 0.924 0.908 0.892 0.876
0.940 0.924 0.908 0.908 0.892 0.876
0.924 0.908 0.892 0.892 0.876 0.860
0.908 0.892 0.876 0.876 0.860 0.860
0.876 0.876 0.860 0.860 0.860 0.844
0.860 0.860 0.844 0.844 0.844 0.844
0.812 0.812 0.812 0.812 0.812 0.812
VCCD753 Pentium M Processor,
Ultra Low Voltage,
753 Core VCC for
Enhanced Intel
V
2, 3
SpeedStep
Technology Operating
Points:
1.2 GHz
1.1 GHz
1.0 GHz
900 MHz
800 MHz
600 MHz
0.956 0.940 0.924 0.908 0.892 0.876
0.940 0.924 0.908 0.892 0.892 0.876
0.908 0.908 0.892 0.876 0.876 0.860
0.892 0.876 0.876 0.860 0.860 0.844
0.860 0.860 0.860 0.844 0.844 0.844
0.812 0.812 0.812 0.812 0.812 0.812
VCCD733J Pentium M Processor,
Ultra Low Voltage,
733J Core VCC for
Enhanced Intel
V
2, 3, 4
SpeedStep
Technology operating
points:
1.1 GHz
1.0 GHz
900 MHz
800 MHz
600 MHz
0.956 0.940 0.924 0.908 0.892 0.876
0.940 0.924 0.908 0.892 0.876 0.876
0.908 0.892 0.892 0.876 0.860 0.860
0.876 0.876 0.860 0.860 0.844 0.844
0.812 0.812 0.812 0.812 0.812 0.812
26
Datasheet
Electrical Specifications
Table 3-6. Voltage and Current Specifications - Ultra Low Voltage Processors (Sheet 2 of 2)
VID#
GTyp HTyp
VID# VID#I VID#
VID#
VID#
Symbol
Parameter
Min
Typ
Max
Unit
Note
Typ J Typ K Typ L Typ
VCCD733 Pentium M Processor,
Ultra Low Voltage,
733 Core VCC for
Enhanced Intel
V
1, 3
SpeedStep
Technology Operating
Points:
1.1 GHz
1.0 GHz
900 MHz
800 MHz
600 MHz
0.940
0.924
0.892
0.876
0.812
VCCD723 Pentium M Processor,
Ultra Low Voltage,
723 Core VCC for
Enhanced Intel
V
1, 3
SpeedStep
Technology Operating
Points:
1.0 GHz
900 MHz
800 MHz
600 MHz
0.940
0.908
0.876
0.812
NOTES:
1. The typical values shown are the VID encoded voltages. Static and ripple tolerances (for minimum and
maximum voltages) are defined in the load line tables, Table 3-8 through Table 3-21. Adherence to loadline
specifications for the Pentium M processor is required to ensure reliable processor operation.
2. These are VID values. Individual processor VID values may be calibrated during manufacturing such that two
devices at the same speed may have different VID settings. Actual voltage supplied to the processor should
be as specified in the load lines in Figure 3-11 and Figure 3-12. Adherence to load line specifications is
required to ensure reliable processor operation.
3. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
4. For 733J, CPU signature = 06D8h.
Datasheet
27
Electrical Specifications
Table 3-7. Voltage and Current Specifications (Continued) (Sheet 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Note
VCC,BOOT Default VCC Voltage for
Initial Power-Up
1.14
1.20
1.26
V
2
VCCP
AGTL+ Termination
voltage
0.997
1.71
1.05
1.8
1.102
1.89
V
2
VCCA
PLL Supply Voltage
V
V
2,
VCCA for
PLL Supply Voltage for
2, 8
778, 758, Pentium M Processors
738 and
753,733J,
778/758/738
1.71
1.425
0.695
1.8
1.5
1.89
1.575
0.795
733, 723
753/733J/733/723
VCCDPRS Transient Deeper Sleep
0.748
V
V
V
V
A
2
Voltage
LP,TR1
VCCDPRS Static Deeper Sleep
0.705
0.669
0.679
0.748
0.726
0.726
0.785
0.783
0.793
25
2
Voltage
VCCDPRS Transient Deeper Sleep
LP,ST1
2, 9
2, 9
5
Voltage
LP,TR2
VCCDPRS Static Deeper Sleep
Voltage
LP,ST2
ICCDES
ICC for Pentium M
Processors
Recommended Design
Target
ICC
ICC for Pentium M
Processors:
A
3, 10
765/755/745/778/758/738/
735/725/715 at LFM Vcc
8.1
765/755/745/735/725/715
at HFM Vcc
21.0
778/758/738 at HFM Vcc
12.0
4.0
773/753/733J/733/723 at
LFM Vcc
773/753/733J at HFM Vcc
773/733/723 at HFM Vcc
7.5
7.0
28
Datasheet
Electrical Specifications
Table 3-7. Voltage and Current Specifications (Continued) (Sheet 2 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Note
4, 10
IAH,
ISGNT
ICC Auto-Halt & Stop-
Grant for Pentium M
Processors:
A
765/755/745/778/758/738/
735/725/715 at LFM Vcc
6.0
765/755/745/735/725/715
at HFM Vcc
15.1
778/758/738 at HFM Vcc
773/753/733J at LFM Vcc
6.4
2.3
733/723 at LFM Vcc
773/753/733J HFM Vcc
733/723 at HFM Vcc
2.1
3.3
3.1
ISLP
ICC Sleep for Pentium M
Processors:
A
4, 10
765/755/745/778/758/738/
735/725/715 at LFM Vcc
5.9
765/755/745/735/725/715
at HFM Vcc
14.8
778/758/738 at HFM Vcc
773/753/733J at LFM Vcc
733/723 at LFM Vcc
6.2
2.2
2.0
3.2
3.0
773/753/733J at HFM Vcc
733/723 at HFM Vcc
IDSLP
ICC Deep Sleep for
Pentium M Processors:
A
4, 10
765/755/745/778/758/738/
735/725/715 at LFM Vcc
5.8
765/755/745/735/725/715
at HFM Vcc
14.2
778/758/738 at HFM Vcc
773/753/733J at LFM Vcc
733/723 at LFM Vcc
5.7
2.1
1.9
2.9
2.7
773/753/733J at HFM Vcc
733/723 at HFM Vcc
Datasheet
29
Electrical Specifications
Table 3-7. Voltage and Current Specifications (Continued) (Sheet 3 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Note
IDPRSLP1
ICC Deeper Sleep @
0.748 V for Pentium M
Processors:
A
4, 9, 10
765/755/745/778/758/738/
735/725/715
2.5
1.6
753/733J/733/723
IDPRSLP1
ICC Deeper Sleep @
0.726 V for Pentium M
Processors:
A
4, 9, 10
765/755/745/778/758/738/
735/725/715
2.3
753/733J/733/723
1.3
0.5
dICC/DT
VCC power supply current
slew rate
A/ns
6, 7
ICCA
ICCP
ICC for VCCA supply
ICC for VCCP supply
120
2.5
mA
A
NOTES:
1. The typical values shown are the VID encoded voltages. Static and ripple tolerances (for minimum and
maximum voltages) are defined in the load line tables i.e., Table 3-8 through Table 3-21. Adherence to
loadline specifications for the Pentium M processor is required to ensure reliable processor operation.
2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe
capacitance, and 1-Mohm minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
3. Specified at VCC,STATIC (nominal) under maximum signal loading conditions.
4. Specified at the VID voltage.
5. The ICCDES(max) specification comprehends future processor HFM frequencies. Platforms should be
designed to this specification.
6. Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7. Measured at the bulk capacitors on the motherboard.
8. Pentium M processors LV and ULV will support VCCA supply voltages of both 1.8 V ±5% and1.5 V ±5%.
9. Deeper sleep voltage of 0.726 V (typical) is supported on LV and ULV Pentium M processors with CPU
signature =06D8h. A typical voltage setting between 0.726 V and 0.748 V may be used but the minimum and
maximum voltages specified in Table 3-7 should not be exceeded.
10.For 733J, CPU signature = 06D8h.
30
Datasheet
Electrical Specifications
®
®
Table 3-8. Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#A
Highest Frequency Mode: VID=1.340V, Offset=0%
Lowest Frequency Mode: VID=0.988V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
Min
I
CC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
1.003
1.002
1.000
Max
1.013
1.012
1.010
0
1.340
1.337
1.334
1.320
1.317
1.314
1.360
1.357
1.355
1.310
1.307
1.304
1.370
1.367
1.365
0.0
0.4
0.9
0.988
0.987
0.985
0.973
0.972
0.971
0.963
0.962
0.961
0.9
1.9
2.8
3.7
4.6
5.6
1.332
1.329
1.326
1.323
1.312
1.309
1.306
1.303
1.352
1.349
1.346
1.343
1.302
1.299
1.296
1.293
1.362
1.359
1.356
1.353
1.3
1.7
2.1
2.6
0.984
0.983
0.982
0.980
0.969
0.968
0.967
0.966
0.999
0.998
0.996
0.995
0.959
0.958
0.957
0.956
1.009
1.008
1.006
1.005
6.5
7.4
8.3
1.321
1.318
1.315
1.300
1.298
1.295
1.341
1.338
1.335
1.290
1.288
1.285
1.351
1.348
1.345
3.0
3.4
3.8
0.979
0.978
0.976
0.964
0.963
0.962
0.994
0.993
0.991
0.954
0.953
0.952
1.004
1.003
1.001
9.3
1.312
1.309
1.307
1.304
1.292
1.289
1.287
1.284
1.332
1.330
1.327
1.324
1.282
1.279
1.277
1.274
1.342
1.340
1.337
1.334
4.3
4.7
5.1
5.5
0.975
0.974
0.973
0.971
0.960
0.959
0.958
0.957
0.990
0.989
0.987
0.986
0.950
0.949
0.948
0.947
1.000
0.999
0.997
0.996
10.2
11.1
12.0
13.0
13.9
14.8
1.301
1.298
1.296
1.281
1.278
1.275
1.321
1.318
1.316
1.271
1.268
1.265
1.331
1.328
1.326
6.0
6.4
6.8
0.970
0.969
0.968
0.955
0.954
0.953
0.985
0.984
0.982
0.945
0.944
0.943
0.995
0.994
0.992
15.7
16.7
1.293
1.290
1.273
1.270
1.313
1.310
1.263
1.260
1.323
1.320
7.2
7.7
0.966
0.965
0.951
0.950
0.981
0.980
0.941
0.940
0.991
0.990
17.6
18.5
19.4
1.287
1.284
1.282
1.267
1.264
1.262
1.307
1.305
1.302
1.257
1.254
1.252
1.317
1.315
1.312
8.1
8.6
9.1
0.964
0.818
0.817
0.949
0.806
0.804
0.979
0.831
0.829
0.939
0.796
0.794
0.989
0.841
0.839
20.4
21.3
22.2
1.279
1.276
1.273
1.259
1.256
1.253
1.299
1.296
1.293
1.249
1.246
1.243
1.309
1.306
1.303
9.6
10.1
0.815
0.814
0.808
0.803
0.801
0.796
0.828
0.826
0.821
0.793
0.791
0.786
0.838
0.836
0.831
11.935
23.1
24.1
25.0
1.271
1.268
1.265
1.250
1.248
1.245
1.291
1.288
1.285
1.240
1.238
1.235
1.301
1.298
1.295
12.435
12.935
13.435
0.807
0.805
0.804
0.794
0.793
0.791
0.819
0.818
0.816
0.784
0.783
0.781
0.829
0.828
0.826
Figure 3-1. Illustration of Active State V Static and Ripple Tolerances (HFM- VID#A)
CC
Highest-Frequency Mode (VID = 1.340V): Active
1.380
1.360
1.314.3040
1.320
1.300
1.280
1.260
1.240
1.220
0
5
10
15
20
25
ICC, A
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
Datasheet
31
Electrical Specifications
®
®
Table 3-9. Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#A
Highest Frequency Mode: VID=1.340V, Offset=-1.2%
Lowest Frequency Mode: VID=0.988V, Offset=-1.2%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.9
1.9
1.324
1.321
1.318
1.304
1.301
1.298
1.344
1.341
1.338
1.294
1.291
1.288
1.354
1.351
1.348
0.0
0.4
0.8
0.976
0.975
0.974
0.961
0.960
0.959
0.991
0.990
0.989
0.951
0.950
0.949
1.001
1.000
0.999
2.8
3.8
1.315
1.313
1.295
1.292
1.336
1.333
1.285
1.282
1.346
1.343
1.2
1.5
0.973
0.972
0.958
0.957
0.987
0.986
0.948
0.947
0.997
0.996
4.7
5.7
6.6
1.310
1.307
1.304
1.290
1.287
1.284
1.330
1.327
1.324
1.280
1.277
1.274
1.340
1.337
1.334
1.9
2.3
2.7
0.970
0.969
0.968
0.956
0.954
0.953
0.985
0.984
0.983
0.946
0.944
0.943
0.995
0.994
0.993
7.6
8.5
9.5
1.301
1.298
1.296
1.281
1.278
1.275
1.321
1.318
1.316
1.271
1.268
1.265
1.331
1.328
1.326
3.1
3.5
3.9
0.967
0.966
0.965
0.952
0.951
0.950
0.982
0.981
0.979
0.942
0.941
0.940
0.992
0.991
0.989
10.4
11.4
12.3
1.293
1.290
1.287
1.273
1.270
1.267
1.313
1.310
1.307
1.263
1.260
1.257
1.323
1.320
1.317
4.3
4.6
5.0
0.963
0.962
0.961
0.949
0.947
0.946
0.978
0.977
0.976
0.939
0.937
0.936
0.988
0.987
0.986
13.3
1.284
1.264
1.304
1.254
1.314
5.4
0.960
0.945
0.975
0.935
0.985
14.2
1.281
1.261
1.301
1.251
1.311
5.8
0.959
0.944
0.974
0.934
0.984
Figure 3-2. Illustration of Deep Sleep State V Static and Ripple Tolerances (LFM- VID#A)
CC
Lowest-Frequency Mode (VID = 0.988V): Deep Sleep
1.010
1.000
0.990
0.980
0.976
0.970
0.960
0.950
0.940
0.930
0.0
1.0
2.0
3.0
4.0
5.0
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
32
Datasheet
Electrical Specifications
®
®
Table 3-10. Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#B
Highest Frequency Mode: VID=1.324V, Offset=0%
Lowest Frequency Mode: VID=0.988V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0
1.324
1.321
1.318
1.304
1.301
1.299
1.344
1.341
1.338
1.294
1.291
1.289
1.354
1.351
1.348
0.0
0.4
0.9
0.988
0.987
0.985
0.973
0.972
0.971
1.003
1.002
1.000
0.963
0.962
0.961
1.013
1.012
1.010
0.9
1.9
2.8
3.7
4.6
5.6
1.316
1.313
1.310
1.307
1.296
1.293
1.290
1.287
1.336
1.333
1.330
1.327
1.286
1.283
1.280
1.277
1.346
1.343
1.340
1.337
1.3
1.7
2.1
2.6
0.984
0.983
0.982
0.980
0.969
0.968
0.967
0.966
0.999
0.998
0.996
0.995
0.959
0.958
0.957
0.956
1.009
1.008
1.006
1.005
6.5
7.4
8.3
1.305
1.302
1.299
1.285
1.282
1.279
1.324
1.322
1.319
1.275
1.272
1.269
1.334
1.332
1.329
3.0
3.4
3.8
0.979
0.978
0.976
0.964
0.963
0.962
0.994
0.993
0.991
0.954
0.953
0.952
1.004
1.003
1.001
9.3
1.296
1.293
1.291
1.288
1.276
1.274
1.271
1.268
1.316
1.313
1.311
1.308
1.266
1.264
1.261
1.258
1.326
1.323
1.321
1.318
4.3
4.7
5.1
5.5
0.975
0.974
0.973
0.971
0.960
0.959
0.958
0.957
0.990
0.989
0.987
0.986
0.950
0.949
0.948
0.947
1.000
0.999
0.997
0.996
10.2
11.1
12.0
13.0
13.9
14.8
1.285
1.282
1.280
1.265
1.262
1.260
1.305
1.302
1.299
1.255
1.252
1.250
1.315
1.312
1.309
6.0
6.4
6.8
0.970
0.969
0.968
0.955
0.954
0.953
0.985
0.984
0.982
0.945
0.944
0.943
0.995
0.994
0.992
15.7
16.7
1.277
1.274
1.257
1.254
1.297
1.294
1.247
1.244
1.307
1.304
7.2
7.7
0.966
0.965
0.951
0.950
0.981
0.980
0.941
0.940
0.991
0.990
17.6
18.5
19.4
20.4
21.3
22.2
1.271
1.268
1.266
1.263
1.260
1.257
1.251
1.249
1.246
1.243
1.240
1.237
1.291
1.288
1.286
1.283
1.280
1.277
1.241
1.239
1.236
1.233
1.230
1.227
1.301
1.298
1.296
1.293
1.290
1.287
8.1
8.6
0.964
0.818
0.817
0.815
0.814
0.808
0.949
0.806
0.804
0.803
0.801
0.796
0.979
0.831
0.829
0.828
0.826
0.821
0.939
0.796
0.794
0.793
0.791
0.786
0.989
0.841
0.839
0.838
0.836
0.831
9.1
9.6
10.1
11.935
23.1
24.1
25.0
1.255
1.252
1.249
1.235
1.232
1.229
1.274
1.272
1.269
1.225
1.222
1.219
1.284
1.282
1.279
12.435
12.935
13.435
0.807
0.805
0.804
0.794
0.793
0.791
0.819
0.818
0.816
0.784
0.783
0.781
0.829
0.828
0.826
Figure 3-3. Illustration of Active State V Static and Ripple Tolerances (HFM- VID#B)
CC
Highest-Frequency Mode (VID = 1.324V): Active
1.380
1.360
1.340
1.312.3024
1.300
1.280
1.260
1.240
1.220
1.200
0
5
10
15
20
25
ICC, A
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
Datasheet
33
Electrical Specifications
®
®
Table 3-11. Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#B
Highest Frequency Mode: VID=1.324V, Offset=-1.2%
Lowest Frequency Mode: VID=0.988V, Offset=-1.2%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.9
1.9
1.308
1.305
1.302
1.288
1.285
1.283
1.328
1.325
1.322
1.278
1.275
1.273
1.338
1.335
1.332
0.0
0.4
0.8
0.976
0.975
0.974
0.961
0.960
0.959
0.991
0.990
0.989
0.951
0.950
0.949
1.001
1.000
0.999
2.8
3.8
1.300
1.297
1.280
1.277
1.319
1.317
1.270
1.267
1.329
1.327
1.2
1.5
0.973
0.972
0.958
0.957
0.987
0.986
0.948
0.947
0.997
0.996
4.7
5.7
6.6
1.294
1.291
1.288
1.274
1.271
1.268
1.314
1.311
1.308
1.264
1.261
1.258
1.324
1.321
1.318
1.9
2.3
2.7
0.970
0.969
0.968
0.956
0.954
0.953
0.985
0.984
0.983
0.946
0.944
0.943
0.995
0.994
0.993
7.6
8.5
9.5
1.285
1.283
1.280
1.266
1.263
1.260
1.305
1.302
1.300
1.256
1.253
1.250
1.315
1.312
1.310
3.1
3.5
3.9
0.967
0.966
0.965
0.952
0.951
0.950
0.982
0.981
0.979
0.942
0.941
0.940
0.992
0.991
0.989
10.4
11.4
12.3
13.3
14.2
1.277
1.274
1.271
1.268
1.266
1.257
1.254
1.251
1.248
1.246
1.297
1.294
1.291
1.288
1.285
1.247
1.244
1.241
1.238
1.236
1.307
1.304
1.301
1.298
1.295
4.3
4.6
5.0
5.4
5.8
0.963
0.962
0.961
0.960
0.959
0.949
0.947
0.946
0.945
0.944
0.978
0.977
0.976
0.975
0.974
0.939
0.937
0.936
0.935
0.934
0.988
0.987
0.986
0.985
0.984
Figure 3-4. Illustration of Deep Sleep State V Static and Ripple Tolerances (LFM- VID#B)
CC
Lowest-Frequency Mode (VID = 0.988V): Deep Sleep
1.010
1.000
0.990
0.980
0.976
0.970
0.960
0.950
0.940
0.930
0.0
1.0
2.0
3.0
4.0
5.0
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
34
Datasheet
Electrical Specifications
®
®
Table 3-12. Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#C
Highest Frequency Mode: VID=1.308V, Offset=0%
Lowest Frequency Mode: VID=0.988V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0
1.308
1.305
1.302
1.288
1.286
1.283
1.328
1.325
1.322
1.278
1.276
1.273
1.338
1.335
1.332
0.0
0.4
0.9
0.988
0.987
0.985
0.973
0.972
0.971
1.003
1.002
1.000
0.963
0.962
0.961
1.013
1.012
1.010
0.9
1.9
2.8
3.7
4.6
5.6
1.300
1.297
1.294
1.291
1.280
1.277
1.274
1.272
1.319
1.317
1.314
1.311
1.270
1.267
1.264
1.262
1.329
1.327
1.324
1.321
1.3
1.7
2.1
2.6
0.984
0.983
0.982
0.980
0.969
0.968
0.967
0.966
0.999
0.998
0.996
0.995
0.959
0.958
0.957
0.956
1.009
1.008
1.006
1.005
6.5
7.4
8.3
1.289
1.286
1.283
1.269
1.266
1.263
1.308
1.305
1.303
1.259
1.256
1.253
1.318
1.315
1.313
3.0
3.4
3.8
0.979
0.978
0.976
0.964
0.963
0.962
0.994
0.993
0.991
0.954
0.953
0.952
1.004
1.003
1.001
9.3
1.280
1.277
1.275
1.272
1.261
1.258
1.255
1.252
1.300
1.297
1.294
1.292
1.251
1.248
1.245
1.242
1.310
1.307
1.304
1.302
4.3
4.7
5.1
5.5
0.975
0.974
0.973
0.971
0.960
0.959
0.958
0.957
0.990
0.989
0.987
0.986
0.950
0.949
0.948
0.947
1.000
0.999
0.997
0.996
10.2
11.1
12.0
13.0
13.9
14.8
1.269
1.266
1.264
1.249
1.247
1.244
1.289
1.286
1.283
1.239
1.237
1.234
1.299
1.296
1.293
6.0
6.4
6.8
0.970
0.969
0.968
0.955
0.954
0.953
0.985
0.984
0.982
0.945
0.944
0.943
0.995
0.994
0.992
15.7
16.7
1.261
1.258
1.241
1.238
1.280
1.278
1.231
1.228
1.290
1.288
7.2
7.7
0.966
0.965
0.951
0.950
0.981
0.980
0.941
0.940
0.991
0.990
17.6
18.5
19.4
20.4
21.3
22.2
1.255
1.252
1.250
1.247
1.244
1.241
1.236
1.233
1.230
1.227
1.224
1.222
1.275
1.272
1.269
1.267
1.264
1.261
1.226
1.223
1.220
1.217
1.214
1.212
1.285
1.282
1.279
1.277
1.274
1.271
8.1
8.6
0.964
0.818
0.817
0.815
0.814
0.808
0.949
0.806
0.804
0.803
0.801
0.796
0.979
0.831
0.829
0.828
0.826
0.821
0.939
0.796
0.794
0.793
0.791
0.786
0.989
0.841
0.839
0.838
0.836
0.831
9.1
9.6
10.1
11.935
23.1
24.1
25.0
1.239
1.236
1.233
1.219
1.216
1.213
1.258
1.255
1.253
1.209
1.206
1.203
1.268
1.265
1.263
12.435
12.935
13.435
0.807
0.805
0.804
0.794
0.793
0.791
0.819
0.818
0.816
0.784
0.783
0.781
0.829
0.828
0.826
Figure 3-5. Illustration of Active State V Static and Ripple Tolerances (HFM- VID#C)
CC
Highest-Frequency Mode (VID = 1.308V): Active
1.360
1.340
1.320
1.308
1.300
1.280
1.260
1.240
1.220
1.200
1.180
0
5
10
15
20
25
ICC, A
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
Datasheet
35
Electrical Specifications
®
®
Table 3-13. Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#C
Highest Frequency Mode: VID=1.308V, Offset=-1.2%
Lowest Frequency Mode: VID=0.988V, Offset=-1.2%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.9
1.9
1.292
1.289
1.287
1.273
1.270
1.267
1.312
1.309
1.306
1.263
1.260
1.257
1.322
1.319
1.316
0.0
0.4
0.8
0.976
0.975
0.974
0.961
0.960
0.959
0.991
0.990
0.989
0.951
0.950
0.949
1.001
1.000
0.999
2.8
3.8
1.284
1.281
1.264
1.261
1.303
1.301
1.254
1.251
1.313
1.311
1.2
1.5
0.973
0.972
0.958
0.957
0.987
0.986
0.948
0.947
0.997
0.996
4.7
5.7
6.6
7.6
8.5
9.5
1.278
1.275
1.272
1.270
1.267
1.264
1.258
1.256
1.253
1.250
1.247
1.244
1.298
1.295
1.292
1.289
1.286
1.284
1.248
1.246
1.243
1.240
1.237
1.234
1.308
1.305
1.302
1.299
1.296
1.294
1.9
2.3
2.7
3.1
3.5
3.9
0.970
0.969
0.968
0.967
0.966
0.965
0.956
0.954
0.953
0.952
0.951
0.950
0.985
0.984
0.983
0.982
0.981
0.979
0.946
0.944
0.943
0.942
0.941
0.940
0.995
0.994
0.993
0.992
0.991
0.989
10.4
11.4
12.3
13.3
14.2
1.261
1.258
1.255
1.253
1.250
1.241
1.239
1.236
1.233
1.230
1.281
1.278
1.275
1.272
1.269
1.231
1.229
1.226
1.223
1.220
1.291
1.288
1.285
1.282
1.279
4.3
4.6
5.0
5.4
5.8
0.963
0.962
0.961
0.960
0.959
0.949
0.947
0.946
0.945
0.944
0.978
0.977
0.976
0.975
0.974
0.939
0.937
0.936
0.935
0.934
0.988
0.987
0.986
0.985
0.984
Figure 3-6. Illustration of Deep Sleep State V Static and Ripple Tolerances (LFM- VID#C)
CC
Lowest-Frequency Mode (VID = 0.988V): Deep Sleep
1.010
1.000
0.990
0.980
0.976
0.970
0.960
0.950
0.940
0.930
0.0
1.0
2.0
3.0
4.0
5.0
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
36
Datasheet
Electrical Specifications
®
®
Table 3-14. Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#D
Highest Frequency Mode: VID=1.276V, Offset=0%
Lowest Frequency Mode: VID=0.988V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
I
CC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0
1.276
1.273
1.270
1.257
1.254
1.251
1.295
1.292
1.290
1.247
1.244
1.241
1.305
1.302
1.300
0.0
0.4
0.9
0.988
0.987
0.985
0.973
0.972
0.971
1.003
1.002
1.000
0.963
0.962
0.961
1.013
1.012
1.010
0.9
1.9
2.8
3.7
4.6
5.6
1.268
1.265
1.262
1.259
1.249
1.246
1.243
1.240
1.287
1.284
1.281
1.278
1.239
1.236
1.233
1.230
1.297
1.294
1.291
1.288
1.3
1.7
2.1
2.6
0.984
0.983
0.982
0.980
0.969
0.968
0.967
0.966
0.999
0.998
0.996
0.995
0.959
0.958
0.957
0.956
1.009
1.008
1.006
1.005
6.5
7.4
8.3
1.257
1.254
1.251
1.237
1.235
1.232
1.276
1.273
1.270
1.227
1.225
1.222
1.286
1.283
1.280
3.0
3.4
3.8
0.979
0.978
0.976
0.964
0.963
0.962
0.994
0.993
0.991
0.954
0.953
0.952
1.004
1.003
1.001
9.3
1.248
1.245
1.243
1.240
1.229
1.226
1.224
1.221
1.267
1.265
1.262
1.259
1.219
1.216
1.214
1.211
1.277
1.275
1.272
1.269
4.3
4.7
5.1
5.5
0.975
0.974
0.973
0.971
0.960
0.959
0.958
0.957
0.990
0.989
0.987
0.986
0.950
0.949
0.948
0.947
1.000
0.999
0.997
0.996
10.2
11.1
12.0
13.0
13.9
14.8
1.237
1.234
1.232
1.218
1.215
1.212
1.256
1.253
1.251
1.208
1.205
1.202
1.266
1.263
1.261
6.0
6.4
6.8
0.970
0.969
0.968
0.955
0.954
0.953
0.985
0.984
0.982
0.945
0.944
0.943
0.995
0.994
0.992
15.7
16.7
1.229
1.226
1.210
1.207
1.248
1.245
1.200
1.197
1.258
1.255
7.2
7.7
0.966
0.965
0.951
0.950
0.981
0.980
0.941
0.940
0.991
0.990
17.6
18.5
19.4
20.4
1.223
1.220
1.218
1.215
1.204
1.201
1.199
1.196
1.242
1.240
1.237
1.234
1.194
1.191
1.189
1.186
1.252
1.250
1.247
1.244
8.1
8.6
9.1
9.6
0.964
0.818
0.817
0.815
0.949
0.806
0.804
0.803
0.979
0.831
0.829
0.828
0.939
0.796
0.794
0.793
0.989
0.841
0.839
0.838
21.3
22.2
1.212
1.209
1.193
1.190
1.231
1.228
1.183
1.180
1.241
1.238
10.1
0.814
0.808
0.801
0.796
0.826
0.821
0.791
0.786
0.836
0.831
11.935
23.1
24.1
25.0
1.207
1.204
1.201
1.187
1.185
1.182
1.226
1.223
1.220
1.177
1.175
1.172
1.236
1.233
1.230
12.435
12.935
13.435
0.807
0.805
0.804
0.794
0.793
0.791
0.819
0.818
0.816
0.784
0.783
0.781
0.829
0.828
0.826
Figure 3-7. Illustration of Active State V Static and Ripple Tolerances (HFM- VID#D)
CC
Highest-Frequency Mode (VID = 1.276V): Active
1.320
1.300
1.280
1.276
1.260
1.240
1.220
1.200
1.180
1.160
0
5
10
15
20
25
ICC, A
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
Datasheet
37
Electrical Specifications
®
®
Table 3-15. Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#D
Highest Frequency Mode: VID=1.276V, Offset=-1.2%
Lowest Frequency Mode: VID=0.988V, Offset=-1.2%
MODE
STATIC Ripple
STATIC
Ripple
ICC, A V , V
ICC, A
V , V
CC
CC
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.9
1.9
1.261
1.258
1.255
1.242
1.239
1.236
1.280
1.277
1.274
1.232
1.229
1.226
1.290
1.287
1.284
0.0
0.4
0.8
0.976
0.975
0.974
0.961
0.960
0.959
0.991
0.990
0.989
0.951
0.950
0.949
1.001
1.000
0.999
2.8
3.8
1.252
1.249
1.233
1.230
1.271
1.268
1.223
1.220
1.281
1.278
1.2
1.5
0.973
0.972
0.958
0.957
0.987
0.986
0.948
0.947
0.997
0.996
4.7
5.7
6.6
7.6
8.5
9.5
1.246
1.244
1.241
1.238
1.235
1.232
1.227
1.225
1.222
1.219
1.216
1.213
1.266
1.263
1.260
1.257
1.254
1.251
1.217
1.215
1.212
1.209
1.206
1.203
1.276
1.273
1.270
1.267
1.264
1.261
1.9
2.3
2.7
3.1
3.5
3.9
0.970
0.969
0.968
0.967
0.966
0.965
0.956
0.954
0.953
0.952
0.951
0.950
0.985
0.984
0.983
0.982
0.981
0.979
0.946
0.944
0.943
0.942
0.941
0.940
0.995
0.994
0.993
0.992
0.991
0.989
10.4
11.4
12.3
13.3
14.2
1.229
1.227
1.224
1.221
1.210
1.207
1.205
1.202
1.249
1.246
1.243
1.240
1.237
1.200
1.197
1.195
1.192
1.189
1.259
1.256
1.253
1.250
1.247
4.3
4.6
5.0
5.4
5.8
0.963
0.962
0.961
0.960
0.959
0.949
0.947
0.946
0.945
0.944
0.978
0.977
0.976
0.975
0.974
0.939
0.937
0.936
0.935
0.934
0.988
0.987
0.986
0.985
0.984
1.218 1.199
Figure 3-8. Illustration of Deep Sleep State V Static and Ripple Tolerances (LFM- VID#D)
CC
Lowest-Frequency Mode (VID = 0.988V): Deep Sleep
1.010
1.000
0.990
0.980
0.976
0.970
0.960
0.950
0.940
0.930
0.0
1.0
2.0
3.0
4.0
5.0
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
38
Datasheet
Electrical Specifications
®
®
Table 3-16. Voltage Tolerances for the Intel Pentium M Processor (Active State) VID#E
Highest Frequency Mode: VID=1.356V, Offset=0%
Lowest Frequency Mode: VID=0.988V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0
1.356
1.353
1.350
1.336
1.333
1.330
1.376
1.374
1.371
1.326
1.323
1.320
1.386
1.384
1.381
0.0
0.4
0.9
0.988
0.987
0.985
0.973
0.972
0.971
1.003
1.002
1.000
0.963
0.962
0.961
1.013
1.012
1.010
0.9
1.9
2.8
3.7
4.6
5.6
1.348
1.345
1.342
1.339
1.327
1.325
1.322
1.319
1.368
1.365
1.362
1.360
1.317
1.315
1.312
1.309
1.378
1.375
1.372
1.370
1.3
1.7
2.1
2.6
0.984
0.983
0.982
0.980
0.969
0.968
0.967
0.966
0.999
0.998
0.996
0.995
0.959
0.958
0.957
0.956
1.009
1.008
1.006
1.005
6.5
7.4
8.3
1.337
1.334
1.331
1.316
1.313
1.311
1.357
1.354
1.351
1.306
1.303
1.301
1.367
1.364
1.361
3.0
3.4
3.8
0.979
0.978
0.976
0.964
0.963
0.962
0.994
0.993
0.991
0.954
0.953
0.952
1.004
1.003
1.001
9.3
1.328
1.325
1.323
1.320
1.308
1.305
1.302
1.300
1.349
1.346
1.343
1.340
1.298
1.295
1.292
1.290
1.359
1.356
1.353
1.350
4.3
4.7
5.1
5.5
0.975
0.974
0.973
0.971
0.960
0.959
0.958
0.957
0.990
0.989
0.987
0.986
0.950
0.949
0.948
0.947
1.000
0.999
0.997
0.996
10.2
11.1
12.0
13.0
13.9
14.8
1.317
1.314
1.312
1.297
1.294
1.291
1.337
1.335
1.332
1.287
1.284
1.281
1.347
1.345
1.342
6.0
6.4
6.8
0.970
0.969
0.968
0.955
0.954
0.953
0.985
0.984
0.982
0.945
0.944
0.943
0.995
0.994
0.992
15.7
16.7
1.309
1.306
1.288
1.286
1.329
1.326
1.278
1.276
1.339
1.336
7.2
7.7
0.966
0.965
0.951
0.950
0.981
0.980
0.941
0.940
0.991
0.990
17.6
18.5
19.4
20.4
1.303
1.300
1.298
1.295
1.283
1.280
1.277
1.275
1.324
1.321
1.318
1.315
1.273
1.270
1.267
1.265
1.334
1.331
1.328
1.325
8.1
8.6
9.1
9.6
0.964
0.818
0.817
0.815
0.949
0.806
0.804
0.803
0.979
0.831
0.829
0.828
0.939
0.796
0.794
0.793
0.989
0.841
0.839
0.838
21.3
22.2
1.292
1.289
1.272
1.269
1.312
1.310
1.262
1.259
1.322
1.320
10.1
0.814
0.808
0.801
0.796
0.826
0.821
0.791
0.786
0.836
0.831
11.935
23.1
24.1
25.0
1.287
1.284
1.281
1.266
1.263
1.261
1.307
1.304
1.301
1.256
1.253
1.251
1.317
1.314
1.311
12.435
12.935
13.435
0.807
0.805
0.804
0.794
0.793
0.791
0.819
0.818
0.816
0.784
0.783
0.781
0.829
0.828
0.826
Figure 3-9. Illustration of Active State V Static and Ripple Tolerances (HFM- VID#E)
CC
Highest-Frequency Mode (VID = 1.356V): Active
1.400
1.356
1.350
1.300
1.250
1.200
0
5
10
15
20
25
ICC, A
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
Datasheet
39
Electrical Specifications
®
®
Table 3-17. Voltage Tolerances for the Intel Pentium M Processor (Deep Sleep State) VID#E
Highest Frequency Mode: VID=1.356V, Offset=-1.2%
Lowest Frequency Mode: VID=0.988V, Offset=-1.2%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.9
1.9
1.340
1.337
1.334
1.319
1.317
1.314
1.360
1.357
1.354
1.309
1.307
1.304
1.370
1.367
1.364
0.0
0.4
0.8
0.976
0.975
0.974
0.961
0.960
0.959
0.991
0.990
0.989
0.951
0.950
0.949
1.001
1.000
0.999
2.8
3.8
1.331
1.328
1.311
1.308
1.352
1.349
1.301
1.298
1.362
1.359
1.2
1.5
0.973
0.972
0.958
0.957
0.987
0.986
0.948
0.947
0.997
0.996
4.7
5.7
6.6
7.6
8.5
9.5
1.326
1.323
1.320
1.317
1.314
1.311
1.305
1.302
1.300
1.297
1.294
1.291
1.346
1.343
1.340
1.337
1.335
1.332
1.295
1.292
1.290
1.287
1.284
1.281
1.356
1.353
1.350
1.347
1.345
1.342
1.9
2.3
2.7
3.1
3.5
3.9
0.970
0.969
0.968
0.967
0.966
0.965
0.956
0.954
0.953
0.952
0.951
0.950
0.985
0.984
0.983
0.982
0.981
0.979
0.946
0.944
0.943
0.942
0.941
0.940
0.995
0.994
0.993
0.992
0.991
0.989
10.4
11.4
12.3
13.3
14.2
1.308
1.306
1.303
1.300
1.297
1.288
1.285
1.282
1.280
1.277
1.329
1.326
1.323
1.320
1.317
1.278
1.275
1.272
1.270
1.267
1.339
1.336
1.333
1.330
1.327
4.3
4.6
5.0
5.4
5.8
0.963
0.962
0.961
0.960
0.959
0.949
0.947
0.946
0.945
0.944
0.978
0.977
0.976
0.975
0.974
0.939
0.937
0.936
0.935
0.934
0.988
0.987
0.986
0.985
0.984
Figure 3-10. Illustration of Deep Sleep State V Static and Ripple Tolerances (LFM- VID#E)
CC
Lowest-Frequency Mode (VID = 0.988V): Deep Sleep
1.010
1.000
0.990
0.980
0.976
0.970
0.960
0.950
0.940
0.930
0.0
1.0
2.0
3.0
4.0
5.0
STATIC
Static Min
Static Max
Ripple Min
Ripple Max
40
Datasheet
Electrical Specifications
®
®
Table 3-18. Voltage Tolerances for the Intel Pentium M Processor LV (Active State)
Highest Frequency Mode: VID=1.116V, Offset=0%
Lowest Frequency Mode: VID=0.988V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
Min
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
1.003
1.002
1.000
Max
1.013
1.012
1.010
0
1.116
1.115
1.113
1.099
1.098
1.097
1.133
1.131
1.130
1.089
1.088
1.087
1.143
1.141
1.140
0.0
0.4
0.9
0.988
0.987
0.985
0.973
0.972
0.971
0.963
0.962
0.961
0.4
0.9
1.3
1.8
2.2
2.7
1.112
1.111
1.109
1.108
1.095
1.094
1.093
1.091
1.129
1.127
1.126
1.125
1.085
1.084
1.083
1.081
1.139
1.137
1.136
1.135
1.3
1.7
2.1
2.6
0.984
0.983
0.982
0.980
0.969
0.968
0.967
0.966
0.999
0.998
0.996
0.995
0.959
0.958
0.957
0.956
1.009
1.008
1.006
1.005
3.1
3.6
4.0
1.107
1.105
1.104
1.090
1.089
1.087
1.123
1.122
1.121
1.080
1.079
1.077
1.133
1.132
1.131
3.0
3.4
3.8
0.979
0.978
0.976
0.964
0.963
0.962
0.994
0.993
0.991
0.954
0.953
0.952
1.004
1.003
1.001
4.4
4.9
5.3
5.8
1.103
1.101
1.100
1.099
1.086
1.085
1.083
1.082
1.119
1.118
1.117
1.115
1.076
1.075
1.073
1.072
1.129
1.128
1.127
1.125
4.3
4.7
5.1
5.5
0.975
0.974
0.973
0.971
0.960
0.959
0.958
0.957
0.990
0.989
0.987
0.986
0.950
0.949
0.948
0.947
1.000
0.999
0.997
0.996
6.2
6.7
7.1
1.097
1.096
1.095
1.081
1.079
1.078
1.114
1.113
1.111
1.071
1.069
1.068
1.124
1.123
1.121
6.0
6.4
6.8
0.970
0.969
0.968
0.955
0.954
0.953
0.985
0.984
0.982
0.945
0.944
0.943
0.995
0.994
0.992
7.6
8.0
1.093
1.092
1.077
1.075
1.110
1.109
1.067
1.065
1.120
1.119
7.2
7.7
0.966
0.965
0.951
0.950
0.981
0.980
0.941
0.940
0.991
0.990
8.1
0.964
0.949
0.979
0.939
0.989
8.4
8.9
1.091
1.089
1.088
1.087
1.085
1.084
1.074
1.073
1.071
1.070
1.069
1.067
1.107
1.106
1.105
1.103
1.102
1.101
1.064
1.063
1.061
1.060
1.059
1.057
1.117
1.116
1.115
1.113
1.112
1.111
9.3
9.8
10.2
10.7
11.1
11.6
12.0
1.083
1.081
1.080
1.066
1.065
1.063
1.099
1.098
1.097
1.056
1.055
1.053
1.109
1.108
1.107
Datasheet
41
Electrical Specifications
®
®
Table 3-19. Voltage Tolerances for the Intel Pentium M Processor LV (Deep Sleep State)
Highest Frequency Mode: VID=1.116V, Offset=-1.2%
Lowest Frequency Mode: VID=0.988V, Offset=-1.2%
MODE
STATIC
Ripple
STATIC
Ripple
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.4
0.8
1.2
1.103
1.101
1.100
1.099
1.086
1.085
1.083
1.082
1.119
1.118
1.117
1.116
1.076
1.075
1.073
1.072
1.129
1.128
1.127
1.126
0.0
0.4
0.8
1.2
0.976
0.975
0.974
0.973
0.961
0.960
0.959
0.958
0.991
0.990
0.989
0.987
0.951
0.950
0.949
0.948
1.001
1.000
0.999
0.997
1.6
2.0
1.098
1.097
1.081
1.080
1.114
1.113
1.071
1.070
1.124
1.123
1.5
1.9
0.972
0.970
0.957
0.956
0.986
0.985
0.947
0.946
0.996
0.995
2.4
2.8
3.3
3.7
4.1
4.5
1.095
1.094
1.093
1.092
1.090
1.089
1.079
1.077
1.076
1.075
1.074
1.072
1.112
1.111
1.110
1.108
1.107
1.106
1.069
1.067
1.066
1.065
1.064
1.062
1.122
1.121
1.120
1.118
1.117
1.116
2.3
2.7
3.1
3.5
3.9
4.3
0.969
0.968
0.967
0.966
0.965
0.963
0.954
0.953
0.952
0.951
0.950
0.949
0.984
0.983
0.982
0.981
0.979
0.978
0.944
0.943
0.942
0.941
0.940
0.939
0.994
0.993
0.992
0.991
0.989
0.988
4.9
5.3
5.7
6.1
1.088
1.087
1.086
1.084
1.071
1.070
1.069
1.068
1.105
1.103
1.102
1.101
1.061
1.060
1.059
1.058
1.115
1.113
1.112
1.111
4.6
5.0
5.4
5.8
0.962
0.961
0.960
0.959
0.947
0.946
0.945
0.944
0.977
0.976
0.975
0.974
0.937
0.936
0.935
0.934
0.987
0.986
0.985
0.984
®
®
Table 3-20. Voltage Tolerances for the Intel Pentium M Processor ULV (Active State)
Highest Frequency Mode: VID=0.940V, Offset=0%
Lowest Frequency Mode: VID=0.812V, Offset=0%
MODE
STATIC
Ripple
STATIC
Ripple
Min
ICC, A
VCC, V
ICC, A
VCC, V
Min
Max
Min
Max
Min
Max
Max
0.835
0.834
0.833
0
0.940
0.939
0.938
0.926
0.925
0.924
0.954
0.953
0.953
0.916
0.915
0.914
0.964
0.963
0.963
0.0
0.2
0.4
0.812
0.811
0.811
0.799
0.799
0.798
0.825
0.824
0.823
0.789
0.789
0.788
0.3
0.5
0.8
1.0
1.3
1.6
0.938
0.937
0.936
0.935
0.924
0.923
0.922
0.921
0.952
0.951
0.950
0.949
0.914
0.913
0.912
0.911
0.962
0.961
0.960
0.959
0.6
0.8
1.1
1.3
0.810
0.809
0.809
0.808
0.797
0.797
0.796
0.796
0.823
0.822
0.822
0.821
0.787
0.787
0.786
0.786
0.833
0.832
0.832
0.831
1.8
2.1
2.3
0.935
0.934
0.933
0.920
0.920
0.919
0.949
0.948
0.947
0.910
0.910
0.909
0.959
0.958
0.957
1.5
1.7
1.9
0.808
0.807
0.806
0.795
0.794
0.794
0.820
0.820
0.819
0.785
0.784
0.784
0.830
0.830
0.829
2.6
2.9
3.1
3.4
0.932
0.931
0.931
0.930
0.918
0.917
0.917
0.916
0.946
0.946
0.945
0.944
0.908
0.907
0.907
0.906
0.956
0.956
0.955
0.954
2.1
2.3
2.5
2.7
0.806
0.805
0.804
0.804
0.793
0.792
0.792
0.791
0.818
0.818
0.817
0.816
0.783
0.782
0.782
0.781
0.828
0.828
0.827
0.826
3.6
3.9
4.1
0.929
0.928
0.928
0.915
0.914
0.913
0.943
0.942
0.942
0.905
0.904
0.903
0.953
0.952
0.952
2.9
3.2
3.4
0.803
0.803
0.802
0.790
0.790
0.789
0.816
0.815
0.815
0.780
0.780
0.779
0.826
0.825
0.825
4.4
4.7
0.927
0.926
0.913
0.912
0.941
0.940
0.903
0.902
0.951
0.950
3.6
3.8
0.801
0.801
0.789
0.788
0.814
0.813
0.779
0.778
0.824
0.823
4.9
5.2
5.4
5.7
6.0
6.2
0.925
0.924
0.924
0.923
0.922
0.921
0.911
0.910
0.910
0.909
0.908
0.907
0.939
0.939
0.938
0.937
0.936
0.935
0.901
0.900
0.900
0.899
0.898
0.897
0.949
0.949
0.948
0.947
0.946
0.945
4.0
4.5
5
0.800
0.831
0.829
0.828
0.826
0.808
0.787
0.818
0.816
0.815
0.813
0.796
0.813
0.843
0.842
0.840
0.839
0.821
0.777
0.808
0.806
0.805
0.803
0.786
0.823
0.853
0.852
0.850
0.849
0.831
5.5
6
11.935
6.5
6.7
7.0
0.921
0.920
0.919
0.906
0.906
0.905
0.935
0.934
0.933
0.896
0.896
0.895
0.945
0.944
0.943
12.435
12.935
13.435
0.807
0.805
0.804
0.794
0.793
0.791
0.819
0.818
0.816
0.784
0.783
0.781
0.829
0.828
0.826
42
Datasheet
Electrical Specifications
®
®
Table 3-21. Voltage Tolerances for the Intel Pentium M Processor ULV (Deep Sleep State)
Highest Frequency Mode: VID=0.940V, Offset=-1.2%
STATIC Ripple
Lowest Frequency Mode: VID=0.812V, Offset=-1.2%
STATIC Ripple
MODE
ICC, A V , V
ICC, A V , V
CC
CC
Min
Max
Min
Max
Min
Max
Min
Max
0.0
0.2
0.4
0.6
0.929
0.928
0.928
0.927
0.915
0.914
0.913
0.913
0.943
0.942
0.942
0.941
0.905
0.904
0.903
0.903
0.953
0.952
0.952
0.951
0.0
0.1
0.3
0.4
0.802
0.802
0.801
0.801
0.758
0.757
0.757
0.756
0.847
0.847
0.846
0.846
0.757
0.756
0.756
0.756
0.848
0.847
0.847
0.847
0.8
1.0
0.926
0.926
0.912
0.912
0.940
0.940
0.902
0.902
0.950
0.950
0.5
0.7
0.801
0.800
0.756
0.756
0.845
0.845
0.755
0.755
0.846
0.846
1.2
1.4
1.6
1.8
2.0
2.2
0.925
0.925
0.924
0.923
0.923
0.922
0.911
0.910
0.910
0.909
0.909
0.908
0.939
0.939
0.938
0.937
0.937
0.936
0.901
0.900
0.900
0.899
0.899
0.898
0.949
0.949
0.948
0.947
0.947
0.946
0.8
0.9
1.1
1.2
1.3
1.5
0.800
0.799
0.799
0.799
0.798
0.798
0.755
0.755
0.754
0.754
0.754
0.753
0.845
0.844
0.844
0.843
0.843
0.843
0.754
0.754
0.754
0.753
0.753
0.752
0.845
0.845
0.845
0.844
0.844
0.843
2.4
2.6
0.922
0.921
0.920
0.907
0.907
0.906
0.936
0.935
0.934
0.897
0.897
0.896
0.946
0.945
0.944
1.6
1.7
0.797
0.797
0.797
0.753
0.752
0.752
0.842
0.842
0.841
0.752
0.752
0.751
0.843
0.843
0.842
2.8
1.9
3.0
0.920 0.906 0.934 0.896 0.944
2.0
0.796 0.752 0.841 0.751 0.842
Figure 3-11. Active V and I Load Line
CC
CC
VCC [V]
Slope= -3.0 mV/A
VCC Max {HFM | LFM}
VCC, DC Max {HFM | LFM}
CC Nom {HFM | LFM}
10mV= RIPPLE
V
VCC, DC Min {HFM | LFM}
VCC Min {HFM | LFM}
+/-1.5% from Nominal =VR Error
I CC
[A]
0
ICC
max
{HFM | LFM}
Datasheet
43
Electrical Specifications
Figure 3-12. Deep Sleep V and I Load Line
CC
CC
VCC [V]
Slope= -3.0 mV/A
10mV= RIPPLE
Vcc nom {HFM | LFM}
- 1.2%
+/-1.5% from Nominal =VR Error
I CC
[A]
0
ICC
max
Deep Sleep
{HFM | LFM}
Table 3-22. FSB Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit Notes1
VL
Input Low Voltage
0
V
V
V
V
VH
Input High Voltage
Crossing Voltage
0.660
0.25
N/A
0.710
0.35
N/A
0.850
0.55
VCROSS
2
6
Range of Crossing Points
0.140
ΔVCROSS
VTH
Threshold Region
Input Leakage Current
Pad Capacitance
VCROSS -0.100
VCROSS+0.100
± 100
V
3
4
5
ILI
µA
pF
Cpad
1.8
2.3
2.75
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
4. For Vin between 0 V and VH.
5. Cpad includes die capacitance only. No package parasitics are included.
6. VCROSS is defined as the total variation of all crossing voltages as defined in note 2
44
Datasheet
Electrical Specifications
Table 3-23. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit Notes1
VCCP
I/O Voltage
0.997
1.05
1.102
V
GTLREF
Reference Voltage
2/3 VCCP -
2%
2/3 VCCP
2/3 VCCP +
2%
V
6
VIH
VIL
Input High Voltage
Input Low Voltage
GTLREF+0.1
-0.1
VCCP+0.1
V
V
3,6
2,4
6
GTLREF-0.1
VOH
RTT
RON
Output High Voltage
Termination Resistance
Buffer On Resistance
VCCP
55
47
63
Ω
7
17.7
24.7
32.9
5
Ω
µA
pF
ILI
Input Leakage Current
Pad Capacitance
± 100
2.75
8
9
Cpad
1.8
2.3
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.
5. This is the pull down driver resistance. Refer to processor I/O buffer models for I/V characteristics. Measured
at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT.
6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these
specifications is the instantaneous VCCP.
7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.
8. Specified with on die RTT and RON are turned off.
9. Cpad includes die capacitance only. No package parasitics are included.
Table 3-24. CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit Notes1
VCCP
VIL
I/O Voltage
0.997
-0.1
1.05
1.102
V
Input Low Voltage
CMOS
0.3*VCCP
V
2, 3
VIH
VOL
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Leakage Current
0.7*VCCP
-0.1
VCCP+0.1
0.1*VCCP
VCCP+0.1
4.08
V
V
2
2
2
4
5
6
0
VOH
0.9*VCCP
1.49
VCCP
V
IOL
mA
mA
µA
pF
IOH
1.49
4.08
ILI
± 100
Cpad
Pad Capacitance
1.0
2.3
3.0
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VCCP referred to in these specifications refers to instantaneous VCCP.
3. Refer to the processor I/O buffer models for I/V characteristics.
4. Measured at 0.1*VCCP.
5. Measured at 0.9*VCCP.
6. For Vin between 0 V and VCCP. Measured when the driver is tristated.
7. Cpad includes die capacitance only. No package parasitics are included
Datasheet
45
Electrical Specifications
Table 3-25. Open Drain Signal Group DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit Notes1
VOH
VOL
IOL
Output High Voltage
Output Low Voltage
Output Low Current
Leakage Current
VCCP
V
V
3
0
0.20
50
16
mA
µA
pF
2
4
5
ILO
± 200
3.0
Cpad
Pad Capacitance
1.7
2.3
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Measured at 0.2 V.
3. VOH is determined by value of the external pullup resistor to VCCP. Please refer to the platform design guides
for details.
4. For Vin between 0 V and VOH
.
5. Cpad includes die capacitance only. No package parasitics are included.
§
46
Datasheet
Package Mechanical Specifications and Pin Information
4 Package Mechanical
Specifications and Pin Information
The Pentium M Processor is available in 478-pin, Micro-FCPGA and 479-ball, Micro-FCBGA
packages. Different views of the Micro-FCPGA package are shown in Figure 4-1 through
Figure 4-3. Package dimensions are shown in Table 4-1. Different views of the Micro-FCBGA
package are shown in Figure 4-4 through Figure 4-6. Package dimensions are shown in Table 4-2.
The Micro-FCBGA package may have capacitors placed in the area surrounding the die. Because
the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care
should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so
may short the capacitors, and possibly damage the device or render it inactive. The use of an
insulating material between the capacitors and any thermal solution should be considered to
prevent capacitor shorting.
Figure 4-1. Micro-FCPGA Package Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
DIE
LABEL
TOP VIEW
BOTTOM VIEW
NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 4-1 for details.
Datasheet
47
Package Mechanical Specifications and Pin Information
Figure 4-2. Micro-FCPGA Package - Top and Side Views
0.286
A
SUBSTRATE KEEPO UT ZO NE
DO NO T CONTACT PACKAG E
INSIDE THIS LINE
7 (K1)
8 places
5 (K)
4 places
1.25 MAX
(A3)
D 1
35 (D )
Ø 0.32 (B)
478 places
A2
E1
2.03 ± 0.08
35 (E)
(A1)
PIN A1 C OR N ER
NOTE: MDie is centered on the Package. All dimensions in millimeters. Values shown for reference only. Refer
to Table 4-1 for details.
48
Datasheet
Package Mechanical Specifications and Pin Information
Figure 4-3. Micro-FCPGA Package - Bottom View
14 (K3)
AF
AD
AB
Y
AE
AC
AA
W
U
V
T
R
P
14 (K3)
N
M
K
L
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13
10 12
15
17
19
21 23
22
25
25X 1.27
(e)
2
4
6
8
14
16
18
20
24
26
25X 1.27
(e)
NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 4-1 for details.
Datasheet
49
Package Mechanical Specifications and Pin Information
Table 4-1. Micro-FCPGA Package Dimensions
Symbol
Parameter
Min
Max
Unit
A
–
Overall height, top of die to package seating plane
1.88
4.74
2.02
5.16
mm
mm
Overall height, top of die to PCB surface, including
socket (Refer to Note 1)
A1
A2
A3
B
Pin length
1.95
2.11
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
each
kPa
g
Die height
0.820
Pin-side capacitor height
Pin diameter
–
1.25
0.36
35.1
35.1
0.28
34.9
34.9
D
Package substrate length
Package substrate width
Die length
E
D1
E1
e
12.54
6.99
1.27
5
Die width
Pin Pitch
K
Package edge keep-out
Package corner keep-out
Pin-side capacitor boundary
Pin count
K1
K3
N
7
14
478
Pdie
W
Allowable pressure on the die for thermal solution
Package weight
–
689
4.5
0.286
mm
Package Surface Flatness
NOTE: Overall height with socket is based on design dimensions of the Micro-FCPGA package with no thermal
solution attached. Values are based on design specifications and tolerances. This dimension is subject
to change based on socket design, OEM motherboard design or OEM SMT process.
50
Datasheet
Package Mechanical Specifications and Pin Information
Figure 4-4. Micro-FCBGA Package Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
DIE
LABEL
TOP VIEW
BOTTOM VIEW
Datasheet
51
Package Mechanical Specifications and Pin Information
Figure 4-5. Micro-FCBGA Package Top and Side Views
SUBSTRATE KEEPOUT ZONE
DO NOT CONTACT PACKAGE
INSIDE THIS LINE
7 (K1)
8 places
0.20
A
5 (K)
4 places
A2
D1
35 (D)
Ø 0.78 (b)
479 places
K2
E1
35 (E)
PIN A1 CORNER
NOTE: Die is centered on the Package. All dimensions in millimeters. Values shown for reference only. Refer to
Table 4-2 for details.
52
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-2. Micro-FCBGA Package Dimensions
Symbol
Parameter
Min
Max
Unit
A
A2
b
Overall height, as delivered (Refer to Note 1)
Die height
2.60
2.85
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
each
mm
kPa
g
0.82
0.78
Ball diameter
D
Package substrate length
Package substrate width
Die length
34.9
34.9
35.1
35.1
E
D1
E1
e
12.54
6.99
1.27
5
Die width
Ball Pitch
K
Package edge keep-out
Package corner keep-out
Die-side capacitor height
Package edge to first ball center
Ball count
K1
K2
S
7
–
–
0.7
1.625
479
N
–
Solder ball coplanarity
Allowable pressure on the die for thermal solution
Package weight
0.2
Pdie
W
689
4.5
NOTE: Overall height as delivered. Values are based on design specifications and tolerances. This dimension
is subject to change based on OEM motherboard design or OEM SMT process.
Datasheet
53
Package Mechanical Specifications and Pin Information
Figure 4-6. Micro-FCBGA Package Bottom View
1.625 (S)
4 places
AF
AE
AD
AC
AB
AA
Y
1.625 (S)
4 places
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
13 15 17
11
10 12 14 16 18
5
7
9
19 21 23 25
25X 1.27
(e)
2
4
6
8
22 24 26
20
25X 1.27
(e)
NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 4-2 for details.
4.1
Processor Pinout and Pin List
Figure 4-7 on the next page shows the top view pinout of the Pentium M Processor. The pin list
arranged in two different formats is shown in the following pages.
54
Datasheet
Package Mechanical Specifications and Pin Information
Figure 4-7. The Coordinates of the Processor Pins as Viewed from the Top of the Package
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
A
B
ITP_CLK
[1]
THER
MDC
ITP_CLK
[0]
IGNNE# IERR#
VSS
INIT#
TEST1
VSS
SLP# DBR#
VSS BPM[2]# PRDY# VSS
BPM
TDO
TCK
VSS
VSS
D[0]#
VSS
VSS
D[6]# D[2]#
VSS
D[4]# D[1]#
VSS
VSS
PROC THER
HOT# MDA
RSVD
VSS
SMI#
VSS
VSS DPSLP#
VSS PREQ# RESET# VSS TRST# BCLK1 BCLK0 VSS
D[7]# D[3]#
VSS D[13]# D[9]#
DSTBP DSTBN
VSS
D[5]#
VCCA[1]
VSS
[1]#
C
C
STP
VSS
BPM
[0]#
BPM
[3]#
THERM
A20M# RSVD
VSS
VCCP
VSS
TMS
VSS
TDI
VCCP
VSS
VSS BSEL[1] VSS BSEL[0]
VSS DPWR# D[8]#
VSS
VSS
VCC
VSS
VSS D[15]# D[12]#
CLK#
TRIP#
[0]#
[0]#
D
D
DINV
[0]#
LINT0
VSS FERR# LINT1
PWR
VCC
VSS
VCC
VSS
VCC
VSS
VCCP
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCCP
VSS
VCCP
VSS
VSS
VCCP
VSS
VCCP
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS D[10]#
VSS
E
E
PSI# VID[0]
VCC
VCC
VSS
VCCP
VSS
VCC
VSS
D[14]# D[11]# VSS
RSVD
VSS
VSS
VCC
VSS
GOOD
F
F
VSS
VID[1] VID[2]
VSS
VSS
VCCP
VCCP
VCCP
VCCP
VSS VCC
VSS D[21]# VCCA[0]
TEST2
G
G
RSVD
VSS
VID[3] VID[4] VCC
VCC
VSS
VCC
VSS
VCCP
VSS
VCCP
VSS D[22]# D[17]#
VSS
H
H
RS[0]# DRDY# VSS
VSS LOCK# BPRI#
VID[5]
VSS
VSS
VCC
VCC D[16]# D[20]# VSS D[29]#
DINV
J
J
VSS D[23]#
VSS D[25]#
[1]#
K
K
DSTBN
[1]#
RS[1]# VSS
HIT# HITM# VSS
VCC
VSS
D[31]# VSS
L
L
DSTBP
[1]#
VCCP
DEFER#
BNR# RS[2]# VSS
VSS D[18]#
VSS D[26]#
M
N
M
N
DBSY# TRDY# VSS
VSS
VCCP
VSS
VCCP D[24]# VSS D[28]# D[19]#
VSS
VCCA[2] ADS#
VSS
BR0# VCCP
VSS
VCCP
VSS
VSS D[27]# D[30]# VSS
COMP COMP
TOP VIEW
P
P
REQ
VSS
[3]#
REQ
[1]#
VCCQ[0]
VSS
A[3]#
VSS
VSS
VCCP
VSS
VCC
VSS
VCCP
VSS
VSS
[0]
[1]
R
R
REQ
VSS
VCCP
A[6]#
VSS
D[39]# D[37]# VSS D[38]#
[0]#
T
T
REQ
[4]#
REQ
[2]#
DINV
[2]#
A[9]#
A[4]#
VSS
VCCP
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCP
VSS
D[34]# VSS
U
U
ADSTB
[0]#
A[13]# VSS
VCCP
VSS D[35]# VSS D[43]# D[41]#
V
V
VSS
A[7]#
A[5]#
VSS
VCC
VCC D[36]# D[42]# VSS D[44]#
DSTBP DSTBN
W
Y
W
Y
A[8]# A[10]# VSS VCCQ[1] VCC
VSS
VSS
VSS
[2]#
[2]#
A[12]# VSS A[15]#
VSS
VCC
VSS
VSS
VCC
VCC D[45]# VSS D[47]# D[32]#
A[11]#
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
VSS
VSS A[16]# A[14]# VSS
COMP COMP
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
D[40]# D[33]# VSS D[46]#
VSS D[50]# D[48]# VSS
VSS
VSS
VCC VSS
VCC
A[24]#
[3]
[2]
VSS A[20]# A[18]# VSS
A[25]# A[19]# VSS
VCC D[51]#
VSS D[52]# D[49]#
VSS D[53]# VCCA[3]
RSVD
DINV
VSS
VSS A[23]# A[21]# VSS
A[28]# VSS
VCC
VSS
VCC
D[60]# VSS D[54]# D[57]# VSS GTLREF
DSTBN DSTBP
A[26]#
[3]#
ADSTB
[1]#
VCC
VSS
A[30]# A[27]# VSS A[22]#
VCC
VSS D[59]# D[55]# VSS
VSS
VSS
VCC
[3]#
[3]#
SENSE
VSS
SENSE
A[31]# VSS A[29]#
A[31]#
A[17]# VSS
RSVD
VSS D[58]# VSS D[62]# D[56]# VSS D[61]# D[63]#
vss
VCC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin B2 is depopulated on the Micro-FCPGA package
VSS
VCC Other
Datasheet
55
Package Mechanical Specifications and Pin Information
This page is intentionally left blank.
56
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Table 4-3. Pin Listing by Pin Name
Pin Name
Direction
Pin
Number
Signal Buffer
Type
BPM[1]#
B8
Common Clock Output
Common Clock Output
Common Clock Input/Output
Common Clock Input
Pin Name
Direction
BPM[2]#
BPM[3]#
BPRI#
BR0#
A9
A[3]#
P4
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
CMOS
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
C9
A[4]#
U4
J3
A[5]#
V3
N4
Common Clock Input/Output
A[6]#
R3
BSEL[1]
BSEL[0]
COMP[0]
COMP[1]
COMP[2]
COMP[3]
D[0]#
C14
C16
P25
P26
AB2
AB1
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
CMOS
Output
A[7]#
V2
CMOS
Output
A[8]#
W1
T4
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A20M#
ADS#
W2
Y4
Y1
U1
D[1]#
AA3
Y3
D[2]#
D[3]#
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
C2
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
N2
Common Clock Input/Output
ADSTB[0]#
ADSTB[1]#
BCLK[0]
BCLK[1]
BNR#
U3
Source Synch
Source Synch
Bus Clock
Input/Output
Input/Output
Input
AE5
B15
B14
L1
Bus Clock
Input
Common Clock Input/Output
Common Clock Output
BPM[0]#
C8
Datasheet
57
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Table 4-3. Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
D[27]#
N24
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
CMOS
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
DBSY#
M2
Common Clock Input/Output
Common Clock Input
D[28]#
D[29]#
D[30]#
D[31]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DBR#
M25
H26
DEFER#
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
DPSLP#
DPWR#
L4
D25
J26
T24
AD20
B7
Source Synch
Source Synch
Source Synch
Source Synch
CMOS
Input/Output
Input/Output
Input/Output
Input/Output
Input
N25
K25
Y26
AA24
T25
C19
H2
Common Clock Input
U23
DRDY#
Common Clock Input/Output
V23
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
FERR#
C23
K24
W25
AE24
C22
L24
W24
AE25
D3
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Open Drain
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
GTLREF
HIT#
AD26
K3
Power/Other
Input
AA26
Y25
Common Clock Input/Output
Common Clock Input/Output
HITM#
K4
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
A7
IERR#
A4
Open Drain
CMOS
Output
Input
Input
input
input
Input
Input
IGNNE#
INIT#
A3
B5
CMOS
ITP_CLK[0]
ITP_CLK[1]
LINT0
A16
A15
D1
CMOS
CMOS
CMOS
LINT1
D4
CMOS
LOCK#
J2
Common Clock Input/Output
Common Clock Output
Common Clock Input
PRDY#
A10
B10
B17
E1
PREQ#
PROCHOT#
PSI#
Open Drain
CMOS
Output
Output
PWRGOOD
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
E4
CMOS
Input
R2
Source Synch
Source Synch
Source Synch
Source Synch
Input/Output
Input/Output
Input/Output
Input/Output
P3
T2
P1
58
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Table 4-3. Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
REQ[4]#
T1
Source Synch
Input/Output
VCC
F18
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
RESET#
RS[0]#
RS[1]#
RS[2]#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SLP#
B11
H1
Common Clock Input
Common Clock Input
Common Clock Input
Common Clock Input
Reserved
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F20
F22
K1
G5
L2
G21
H6
AF7
B2
Reserved
H22
J5
C3
Reserved
E26
G1
Reserved
J21
Reserved
K22
AC1
A6
Reserved
U5
CMOS
Input
Input
Input
Input
Input
Output
V6
SMI#
B4
CMOS
V22
STPCLK#
TCK
C6
CMOS
W5
A13
C12
A12
C5
CMOS
W21
Y6
TDI
CMOS
TDO
Open Drain
Test
Y22
TEST1
TEST2
THERMDA
THERMDC
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
F23
B18
A18
Test
Power/Other
Power/Other
Open Drain
CMOS
THERMTRIP# C17
Output
Input
TMS
TRDY#
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C11
M3
B13
D6
Common Clock Input
CMOS
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
Datasheet
59
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Table 4-3. Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VCC
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
AE11
AE13
AE15
AE17
AE19
AF8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCCP
L21
M6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCQ[0]
VCCQ[1]
VCCSENSE
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VSS
VCC
M22
N5
VCC
VCC
N21
P6
VCC
VCC
P22
R5
VCC
VCC
R21
T6
VCC
VCC
T22
U21
P23
W4
AE7
E2
VCC
VCC
VCC
VCC
Output
VCC
Output
Output
Output
Output
Output
Output
VCC
AF10
AF12
AF14
AF16
AF18
F26
F2
CMOS
VCC
F3
CMOS
VCC
G3
CMOS
VCC
G4
CMOS
VCC
H4
CMOS
VCCA[0]
VCCA[1]
VCCA[2]
VCCA[3]
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
A2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B1
VSS
A5
N1
VSS
A8
AC26
D10
VSS
A11
A14
A17
A20
A23
A26
B3
VSS
D12
VSS
D14
VSS
D16
VSS
E11
VSS
E13
VSS
E15
VSS
B6
F10
VSS
B9
F12
VSS
B12
B16
B19
B22
B25
F14
VSS
F16
VSS
K6
VSS
L5
VSS
60
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Table 4-3. Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VSS
C1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
F13
F15
F17
F19
F21
F24
G2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C7
C10
C13
C15
C18
C21
C24
D2
G6
G22
G23
G26
H3
D5
D7
D9
H5
D11
D13
D15
D17
D19
D21
D23
D26
E3
H21
H25
J1
J4
J6
J22
J24
K2
K5
E6
K21
K23
K26
L3
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
L6
L22
L25
M1
M4
M5
M21
M24
N3
F4
F5
F7
N6
F9
N22
N23
F11
Datasheet
61
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Table 4-3. Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VSS
N26
P2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P5
P21
P24
R1
R4
R6
R22
R25
T3
AB5
AB7
AB9
T5
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
T21
T23
T26
U2
U6
U22
U24
V1
V4
AC5
V5
AC8
V21
V25
W3
W6
W22
W23
W26
Y2
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
Y5
AD4
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AD7
AD9
AD11
AD13
AD15
AD17
AD19
62
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-3. Pin Listing by Pin Name
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
Input
VSS
AD22
AD25
AE3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A13
TCK
CMOS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSSENSE
A14
VSS
Power/Other
CMOS
A15
ITP_CLK[1]
ITP_CLK[0]
VSS
input
input
AE6
A16
CMOS
AE8
A17
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
A18
THERMDC
D[0]#
VSS
A19
Input/Output
A20
A21
D[6]#
D[2]#
VSS
Input/Output
Input/Output
A22
A23
A24
D[4]#
D[1]#
VSS
Input/Output
Input/Output
A25
A26
AF5
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
VSS
AF9
A[16]#
A[14]#
VSS
Input/Output
Input/Output
AF11
AF13
AF15
AF17
AF19
AF21
AF24
AF6
VCC
VSS
VCC
VSS
VCC
Output
VSS
VCC
Table 4-4. Pin Listing by Pin Number
VSS
Pin
Number
Signal Buffer
Type
VCC
Pin Name
Direction
VSS
A2
VSS
Power/Other
CMOS
VCC
A3
IGNNE#
IERR#
VSS
Input
VSS
A4
Open Drain
Power/Other
CMOS
Output
VCC
A5
VSS
A6
SLP#
Input
VCC
A7
DBR#
VSS
CMOS
Output
VSS
A8
Power/Other
VCC
A9
BPM[2]#
PRDY#
VSS
Common Clock Output
Common Clock Output
Power/Other
VSS
A10
A11
A12
D[40]#
D[33]#
Input/Output
Input/Output
TDO
Open Drain
Output
Datasheet
63
Package Mechanical Specifications and Pin Information
Table 4-4. Pin Listing by Pin Number
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
AA25
AA26
AB1
VSS
Power/Other
Source Synch
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Reserved
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
D[46]#
COMP[3]
COMP[2]
VSS
Input/Output
Input/Output
Input/Output
VSS
VCC
AB2
VSS
AB3
VCC
AB4
A[24]#
VSS
Input/Output
VSS
AB5
VCC
AB6
VCC
VSS
AB7
VSS
VCC
AB8
VCC
D[51]#
VSS
Input/Output
AB9
VSS
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
VCC
D[52]#
D[49]#
VSS
Input/Output
Input/Output
VSS
VCC
VSS
D[53]#
VCCA[3]
VSS
Input/Output
VCC
VSS
VCC
AD2
A[23]#
A[21]#
VSS
Input/Output
Input/Output
VSS
AD3
VCC
AD4
VSS
AD5
A[26]#
A[28]#
VSS
Input/Output
Input/Output
VCC
AD6
VSS
AD7
VCC
AD8
VCC
VSS
AD9
VSS
D[50]#
D[48]#
VSS
Input/Output
Input/Output
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
VCC
VSS
VCC
RSVD
VSS
VSS
AC2
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
VCC
AC3
A[20]#
A[18]#
VSS
Input/Output
Input/Output
VSS
AC4
VCC
AC5
VSS
AC6
A[25]#
A[19]#
VSS
Input/Output
Input/Output
VCC
AC7
VSS
AC8
DINV[3]#
D[60]#
VSS
Input/Output
Input/Output
AC9
VCC
AC10
VSS
64
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-4. Pin Listing by Pin Number
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
AD23
AD24
AD25
AD26
AE1
D[54]#
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Reserved
Input/Output
Input/Output
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
B1
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Reserved
D[57]#
VSS
VCC
VSS
GTLREF
A[30]#
A[27]#
VSS
VCC
Input/Output
Input/Output
VSS
AE2
VCC
AE3
VSS
AE4
A[22]#
ADSTB[1]#
VSS
Input/Output
Input/Output
VCC
AE5
VSS
AE6
VCC
AE7
VCCSENSE
VSS
Output
VSS
AE8
D[58]#
VSS
Input/Output
AE9
VCC
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
VSS
D[62]#
D[56]#
VSS
Input/Output
Input/Output
VCC
VSS
VCC
D[61]#
D[63]#
VCCA[1]
RSVD
VSS
Input/Output
Input/Output
VSS
VCC
VSS
B2
VCC
B3
Power/Other
CMOS
VSS
B4
SMI#
Input
Input
VCC
B5
INIT#
CMOS
VSS
B6
VSS
Power/Other
CMOS
D[59]#
D[55]#
VSS
Input/Output
Input/Output
B7
DPSLP#
BPM[1]#
VSS
Input
B8
Common Clock Output
Power/Other
B9
DSTBN[3]#
DSTBP[3]#
VSS
Input/Output
Input/Output
B10
B11
PREQ#
RESET#
VSS
Common Clock Input
Common Clock Input
Power/Other
B12
B13
B14
B15
B16
B17
B18
B19
B20
A[31]#
VSS
Input/Output
TRST#
BCLK[1]
BCLK[0]
VSS
CMOS
Input
Input
Input
AF2
Bus Clock
AF3
A[29]#
A[17]#
VSS
Input/Output
Input/Output
Bus Clock
AF4
Power/Other
Open Drain
Power/Other
Power/Other
Source Synch
AF5
PROCHOT#
THERMDA
VSS
Output
AF6
VSSSENSE
RSVD
VCC
Output
AF7
AF8
Power/Other
D[7]#
Input/Output
Datasheet
65
Package Mechanical Specifications and Pin Information
Table 4-4. Pin Listing by Pin Number
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
B21
B22
B23
B24
B25
B26
C1
D[3]#
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
CMOS
Input/Output
D7
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
CMOS
VSS
D8
VCC
D[13]#
D[9]#
Input/Output
Input/Output
D9
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
VCCP
VSS
VSS
D[5]#
Input/Output
Input
VCCP
VSS
VSS
C2
A20M#
RSVD
VSS
VCCP
VSS
C3
Reserved
C4
Power/Other
Test
VCCP
VSS
C5
TEST1
STPCLK#
VSS
C6
CMOS
Input
VCC
C7
Power/Other
VSS
C8
BPM[0]#
BPM[3]#
VSS
Common Clock Output
Common Clock Input/Output
Power/Other
VCC
C9
VSS
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
VCC
TMS
CMOS
Input
Input
VSS
TDI
CMOS
D[10]#
DINV[0]#
VSS
Input/Output
Input/Output
VSS
Power/Other
CMOS
BSEL[1]
VSS
Output
Power/Other
CMOS
PSI#
VID[0]
VSS
Output
Output
BSEL[0]
Output
Output
E2
CMOS
THERMTRIP# Open Drain
E3
Power/Other
CMOS
VSS
Power/Other
Common Clock Input
E4
PWRGOOD
VCC
Input
DPWR#
D[8]#
E5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
CMOS
Input/Output
E6
VSS
VSS
E7
VCC
DSTBP[0]#
DSTBN[0]#
VSS
Input/Output
Input/Output
E8
VSS
E9
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
VSS
D[15]#
D[12]#
LINT0
VSS
Input/Output
Input/Output
Input
VCCP
VSS
VCCP
VSS
D2
Power/Other
Open Drain
CMOS
D3
FERR#
LINT1
VSS
Output
Input
VCCP
VSS
D4
D5
Power/Other
Power/Other
VCC
D6
VCC
VSS
66
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-4. Pin Listing by Pin Number
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
E19
E20
E21
E22
E23
E24
E25
E26
F1
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Reserved
G5
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
VSS
G6
VSS
VCC
G21
G22
G23
G24
G25
G26
H1
VCC
VSS
VSS
D[14]#
D[11]#
VSS
Input/Output
Input/Output
VSS
D[22]#
D[17]#
VSS
Input/Output
Input/Output
RSVD
VSS
Power/Other
CMOS
RS[0]#
DRDY#
VSS
Common Clock Input
Common Clock Input/Output
Power/Other
F2
VID[1]
VID[2]
VSS
Output
Output
H2
F3
CMOS
H3
F4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Test
H4
VID[5]
VSS
CMOS
Output
F5
VSS
H5
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
F6
VCC
H6
VCC
F7
VSS
H21
H22
H23
H24
H25
H26
J1
VSS
F8
VCC
VCC
F9
VSS
D[16]#
D[20]#
VSS
Input/Output
Input/Output
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
VCCP
VSS
VCCP
VSS
D[29]#
VSS
Input/Output
VCCP
VSS
J2
LOCK#
BPRI#
VSS
Common Clock Input/Output
Common Clock Input
Power/Other
J3
VCCP
VSS
J4
J5
VCC
Power/Other
VCC
J6
VSS
Power/Other
VSS
J21
J22
J23
J24
J25
J26
K1
VCC
Power/Other
VCC
VSS
Power/Other
VSS
D[23]#
VSS
Source Synch
Power/Other
Source Synch
Source Synch
Input/Output
VCC
TEST2
VSS
D[25]#
DINV[1]#
RS[1]#
VSS
Input/Output
Input/Output
Power/Other
Source Synch
Power/Other
Reserved
D[21]#
VCCA[0]
RSVD
VSS
Input/Output
Common Clock Input
Power/Other
K2
K3
HIT#
Common Clock Input/Output
Common Clock Input/Output
Power/Other
G2
Power/Other
CMOS
K4
HITM#
VSS
G3
VID[3]
VID[4]
Output
Output
K5
G4
CMOS
K6
VCCP
Power/Other
Datasheet
67
Package Mechanical Specifications and Pin Information
Table 4-4. Pin Listing by Pin Number
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
K21
K22
K23
K24
K25
K26
L1
VSS
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
N23
N24
N25
N26
P1
VSS
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS
VCC
D[27]#
D[30]#
VSS
Input/Output
Input/Output
VSS
DSTBN[1]#
D[31]#
VSS
Input/Output
Input/Output
REQ[3]#
VSS
Input/Output
P2
BNR#
RS[2]#
VSS
Common Clock Input/Output
Common Clock Input
Power/Other
P3
REQ[1]#
A[3]#
Input/Output
Input/Output
L2
P4
L3
P5
VSS
L4
DEFER#
VCCP
VSS
Common Clock Input
Power/Other
P6
VCCP
VSS
L5
P21
P22
P23
P24
P25
P26
R1
L6
Power/Other
VCCP
VCCQ[0]
VSS
L21
L22
L23
L24
L25
L26
M1
VCCP
VSS
Power/Other
Power/Other
D[18]#
DSTBP[1]#
VSS
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Input/Output
Input/Output
COMP[0]
COMP[1]
VSS
Input/Output
Input/Output
D[26]#
VSS
Input/Output
R2
REQ[0]#
A[6]#
Input/Output
Input/Output
R3
M2
DBSY#
TRDY#
VSS
Common Clock Input/Output
Common Clock Input
Power/Other
R4
VSS
M3
R5
VCCP
VSS
M4
R6
M5
VSS
Power/Other
R21
R22
R23
R24
R25
R26
T1
VCCP
VSS
M6
VCCP
VSS
Power/Other
M21
M22
M23
M24
M25
M26
N1
Power/Other
D[39]#
D[37]#
VSS
Input/Output
Input/Output
VCCP
D[24]#
VSS
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
D[38]#
REQ[4]#
REQ[2]#
VSS
Input/Output
Input/Output
Input/Output
D[28]#
D[19]#
VCCA[2]
ADS#
VSS
Input/Output
Input/Output
T2
T3
N2
Common Clock Input/Output
Power/Other
T4
A[9]#
Input/Output
N3
T5
VSS
N4
BR0#
VCCP
VSS
Common Clock Input/Output
Power/Other
T6
VCCP
VSS
N5
T21
T22
T23
T24
N6
Power/Other
VCCP
VSS
N21
N22
VCCP
VSS
Power/Other
Power/Other
DINV[2]#
Input/Output
68
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-4. Pin Listing by Pin Number
Table 4-4. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
T25
T26
U1
D[34]#
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
Y1
A[12]#
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Input/Output
VSS
Y2
VSS
A[13]#
VSS
Input/Output
Y3
A[15]#
A[11]#
VSS
Input/Output
Input/Output
U2
Y4
U3
ADSTB[0]#
A[4]#
Input/Output
Input/Output
Y5
U4
Y6
VCC
U5
VCC
Y21
Y22
Y23
Y24
Y25
Y26
VSS
U6
VSS
VCC
U21
U22
U23
U24
U25
U26
V1
VCCP
VSS
D[45]#
VSS
Input/Output
D[35]#
VSS
Input/Output
D[47]#
D[32]#
Input/Output
Input/Output
D[43]#
D[41]#
VSS
Input/Output
Input/Output
V2
A[7]#
Input/Output
Input/Output
V3
A[5]#
V4
VSS
V5
VSS
V6
VCC
V21
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W6
W21
W22
W23
W24
W25
W26
VSS
VCC
D[36]#
D[42]#
VSS
Input/Output
Input/Output
D[44]#
A[8]#
Input/Output
Input/Output
Input/Output
A[10]#
VSS
VCCQ[1]
VCC
VSS
VCC
VSS
VSS
DSTBP[2]#
DSTBN[2]#
VSS
Input/Output
Input/Output
Datasheet
69
Package Mechanical Specifications and Pin Information
4.2
Alphabetical Signals Reference
Table 4-5. Signal Description (Sheet 1 of 7)
Name
A[31:3]#
Type
Description
Input/
Output
A[31:3]# (Address) define a 232-byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
must connect the appropriate pins of both agents on the Intel®Pentium®
M
Processor FSB. A[31:3]# are source synchronous signals and are latched into
the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which
are sampled before RESET# is deasserted.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new
transaction.
ADSTB[1:0]#
Input/
Output
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
A[31:17]#
ADSTB[0]#
ADSTB[1]#
BCLK[1:0]
BNR#
Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB
agents must receive these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS
.
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BPM[2:0]#
BPM[3]
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[3:0]# should connect the appropriate pins of all Intel®
Pentium® M FSB agents.This includes debug or performance monitoring tools.
Output
Input/
Output
Please refer to the platform design guides for more detailed information.
BPRI#
BR0#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It
must connect the appropriate pins of both FSB agents. Observing BPRI# active
(as asserted by the priority agent) causes the other agent to stop issuing new
requests, unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
Input/
Output
BR0# is used by the processor to request the bus. The arbitration is done
between Intel®Pentium® M (Symmetric Agent) and Intel 855 chipset family
MCH-M (High Priority Agent).
70
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 2 of 7)
Name
Type
Description
BSEL[1:0]
Output
These signals are used to select the FSB clock frequency. They should be
connected between the processor and the chipset MCH and clock generator on
Intel 915 chipset family based platforms. These signals must be left
unconnected on platforms designed with the Intel 855 chipset family. On these
platforms, FSB clock frequency should be configured on the motherboard.
COMP[3:0]
D[63:0]#
Analog
COMP[3:0] must be terminated on the system board using precision (1%
tolerance) resistors. Refer to the platform design guides for more details on
implementation.
Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the FSB agents, and must connect the appropriate pins on both agents.
The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups
DSTBN#/
Data Group
DINV#
DSTBP#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DINV# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DINV# signal. When the DINV#
signal is active, the corresponding data group is inverted and therefore sampled
active high.
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where no debug port
is implemented on the system board. DBR# is used by a debug port interposer
so that an in-target probe can drive system reset. If a debug port is implemented
in the system, DBR# is a no connect in the system. DBR# is not a processor
signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
the FSB to indicate that the data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the appropriate pins on both
FSB agents.
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or Input/Output agent. This signal must
connect the appropriate pins of both FSB agents.
Datasheet
71
Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 3 of 7)
Name
Type
Description
DINV[3:0]#
Input/
Output
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the
polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the
data on the data bus is inverted. The bus agent will invert the data bus signals if
more than half the bits, within the covered group, would change level in the next
cycle.
DINV[3:0]# Assignment To Data Bus
Bus Signal
Data Bus Signals
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DPSLP#
Input
Input
DPSLP# when asserted on the platform causes the processor to transition from
the Sleep State to the Deep Sleep state. In order to return to the Sleep state,
DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and
also connects to the Intel 855 chipset family MCH-M component.
DPWR#
DRDY#
DPWR# is a control signal from the Intel® 852/855 and 915 chipset family used
to reduce power on the Intel® Pentium® M data bus input buffers.
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both FSB agents.
DSTBN[3:0]#
Input/
Data strobe used to latch in D[63:0]#.
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
DSTBP[3:0]#
Input/
Data strobe used to latch in D[63:0]#.
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
72
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 4 of 7)
Name
Type
Description
FERR#/PBE#
Output
FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal
and its meaning is qualified with STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating point when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event.
For additional information on the pending break event functionality, including
identification of support of the feature and enable/disable information, refer to
Volume 3 of the Intel ꢀ Architecture Software Developer’s Manual and the Intel ꢀ
Processor Identification and CPUID Instruction application note.
For termination requirements please refer to the platform design guides.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine
if a signal is a logical 0 or logical 1. Please refer to the platform design guides for
details on GTLREF implementation.
HIT#
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Either FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
HITM#
Input/
Output
IERR#
Output
Input
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the FSB. This transaction may optionally be converted to an external error
signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted
until the assertion of RESET#, BINIT#, or INIT#.
For termination requirements please refer to the platform design guides.
IGNNE#
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output Write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST)
For termination requirements please refer to the platform design guides.
ITP_CLK[1:0]
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
used as BCLK[1:0] references for a debug port implemented on an interposer. If
a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the
system. These are not processor signals.
Datasheet
73
Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 5 of 7)
Name
Type
Description
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC
Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those
names on the Pentium Processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the
APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the
default configuration.
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins of both FSB agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.
PRDY#
Output
Input
Probe Ready signal used by debug tools to determine processor debug
readiness.
Please refer to the platform design guides for more implementation details.
PREQ#
Probe Request signal used by debug tools to request debug operation of the
processor.
Please refer to the platform design guides for more implementation details.
PROCHOT#
Output
PROCHOT# (Processor Hot) will go active when the processor temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit
has been activated, if enabled. See Chapter 5 for more details.
For termination requirements please refer to the platform design guides.
This signal may require voltage translation on the motherboard. Please refer to
the platform design guides for more details.
PSI#
Output
Input
Processor Power Status Indicator signal. This signal is asserted when the
processor is in a lower state (Deep Sleep and Deeper Sleep). See Section 2.1.6
for more details.
PWRGOOD
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. Clean implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
For termination requirements please refer to the platform design guides.
REQ[4:0]#
RESET#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB
agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[0]#.
Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least two milliseconds after
VCC and BCLK have reached their proper specifications. On observing active
RESET#, both FSB agents will deassert their outputs within two clocks. All
processor straps must be valid within the specified setup time before RESET# is
deasserted.
Please refer to the Platform Design Guides for termination requirements and
implementation details. There is a 55 ohm (nominal) on die pullup resistor on this
signal.
74
Datasheet
Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 6 of 7)
Name
RS[2:0]#
Type
Description
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of both FSB agents.
RSVD
SLP#
Reserved/ These pins are RESERVED and must be left unconnected on the board.
No
Connect
However, it is recommended that routing channels to these pins on the board be
kept open for possible future use. Please refer to the platform design guides for
more details.
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will recognize only assertion of the RESET# signal, deassertion of SLP#, and
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal
clock signals to the bus and processor core units. If DPSLP# is asserted while in
the Sleep state, the processor will exit the Sleep state and transition to the Deep
Sleep state.
SMI#
Input
Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tristate
its outputs.
STPCLK#
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK
TDI
Input
Input
TCK (Test Clock) provides the clock input for the processor test bus (also known
as the Test Access Port).
Please refer to the platform design guides for termination requirements and
implementation details.
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
Please refer to the platform design guides for termination requirements and
implementation details.
TDO
Output
Input
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
Please refer to the platform design guides for termination requirements and
implementation details.
TEST1,
TEST2
TEST1 and TEST2 must have a stuffing option of separate pull down resistors to
VSS. Please refer to the platform design guides for more details.
THERMDA
Other
Other
Thermal Diode Anode.
Thermal Diode Cathode.
THERMDC
THERMTRIP#
Output
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature
to ensure that there are no false trips. The processor will stop all execution when
the junction temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
For termination requirements please refer to the platform design guides .
Datasheet
75
Package Mechanical Specifications and Pin Information
Table 4-5. Signal Description (Sheet 7 of 7)
Name
TMS
Type
Description
Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
Please refer to the platform design guides for termination requirements and
implementation details.
TRDY#
TRST#
Input
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of both FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. Please refer to the platform design guides for
termination requirements and implementation details.
VCC
Input
Input
Processor core power supply.
VCCA[3:0]
VCCA provides isolated power for the internal processor core PLL’s. Refer to the
platform design guides for complete implementation details.
VCCP
Input
Input
Processor I/O power supply.
VCCQ[1:0]
Quiet power supply for on die COMP circuitry. These pins should be connected
to VCCP on the motherboard. However, these connections should enable addition
of decoupling on the VCCQ lines if necessary.
VCCSENSE
VID[5:0]
Output
Output
VCCSENSE is an isolated low impedance connection to processor core power
(VCC). It can be used to sense or measure power near the silicon with little noise.
Please refer to the platform design guides for termination recommendations and
more details.
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (Vcc). Unlike some previous generations of processors, these
are CMOS signals that are driven by the Intel®Pentium® M processor. The
voltage supply for these pins must be valid before the VR can supply Vcc to the
processor. Conversely, the VR output must be disabled until the voltage supply
for the VID pins becomes valid. The VID pins are needed to support the
processor voltage specification variations. See Table 3-1 for definitions of these
pins. The VR must supply the voltage that is requested by the pins, or disable
itself.
VSSSENSE
Output
VSSSENSE is an isolated low impedance connection to processor core VSS. It can
be used to sense or measure ground near the silicon with little noise. Please
refer to the platform design guides for termination recommendations and more
details.
§§
76
Datasheet
Thermal Specifications and Design Considerations
5 Thermal Specifications and
Design Considerations
The Pentium M Processor requires a thermal solution to maintain temperatures within operating
limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating
limits may result in permanent damage to the processor and potentially other components in the
system. As processor technology changes, thermal management becomes increasingly crucial
when building computer systems. Maintaining the proper thermal environment is key to reliable,
long-term system operation. A complete thermal solution includes both component and system
level thermal management features. Component level thermal solutions include active or passive
heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm
contact to the die while maintaining processor mechanical specifications such as pressure. A
typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that
is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air
from the processor fan may also be used to cool other platform components or lower the internal
ambient temperature within the system.
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the
system/processor thermal solution should be designed such that the processor must remain within
the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal
design power (TDP) value listed in Table 5-1. Thermal solutions not design to provide this level of
thermal capability may affect the long-term reliability of the processor and system.
The maximum junction temperature is defined by an activation of the processor Intel Thermal
Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are
unlikely to cause the processor to consume the theoretical maximum power dissipation for
sustained time periods. Intel recommends that complete thermal solution designs target the TDP
indicated in Table 5-1. The Intel Thermal Monitor feature is designed to help protect the processor
in the unlikely event that an application exceeds the TDP recommendation for a sustained period of
time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases the Intel
Thermal Monitor feature must be enabled for the processor to remain within specification.
Datasheet
77
Thermal Specifications and Design Considerations
®
Table 5-1. Power Specifications for the Intel Pentium M Processor (Sheet 1 of 3)
Processor
Number
Core Frequency
& Voltage
Thermal Design
Power
Symbol
Unit
Notes
TDP
765
2.1 GHz & HFM Vcc
2.0 GHz & HFM Vcc
1.8 GHz & HFM Vcc
1.7 GHz & HFM Vcc
1.6 GHz & HFM Vcc
1.5 GHz & HFM Vcc
1.6 GHz & HFM Vcc
1.5 GHz & HFM Vcc
1.4 GHz & HFM Vcc
600 MHz & LFM Vcc
21
21
21
21
21
21
10
10
10
7.5
W
At 100°C, Notes 1,
4, 5
755
745
735
725
715
778
758
738
765/755/745/
735/725/715 &
778/758/738
773
753
733J
733
723
1.3 GHz & HFM Vcc
1.2 GHz & HFM Vcc
1.1 GHz & HFM Vcc
1.1 GHz & HFM Vcc
1.0 GHz & HFM Vcc
600 MHz & LFM Vcc
5.5
5.5
5.5
5.0
5.0
3.0
773/753/733J/
733/723
Processor
Number
Symbol
Parameter
Min
Typ
Max
Unit
Notes
PAH,
765/755/745/
735/725/715
Auto Halt, Stop Grant
Power:
W
At 50°C, Note 2
PSGNT
LFM Vcc
HFM Vcc
3.3
10.9
778/758/738
773/753/733J
733/723
Auto Halt, Stop Grant
Power:
W
W
W
At 50°C, Note 2
At 50°C, Note 2, 5
At 50°C, Note 2
LFM Vcc
HFM Vcc
3.3
4.2
Auto Halt, Stop Grant
Power:
LFM Vcc
HFM Vcc
1.1
1.9
Auto Halt, Stop Grant
Power:
LFM Vcc
HFM Vcc
1.0
1.8
78
Datasheet
Thermal Specifications and Design Considerations
®
Table 5-1. Power Specifications for the Intel Pentium M Processor (Sheet 2 of 3)
Processor
Number
Symbol
Parameter
Min
Typ
Max
Unit
Notes
PSLP
765/755/745/
735/725/715
Sleep Power:
LFM Vcc
W
At 50 °C, Note 2
3.2
HFM Vcc
10.5
778/758/738
773/753/733J
733/723
Sleep Power:
LFM Vcc
W
W
W
W
W
W
W
At 50 °C, Note 2
At 50 °C, Note 2, 5
At 50 °C, Note 2
At 35 °C, Note 2
At 35 °C, Note 2
At 35 °C, Note 2, 5
At 35 °C, Note 2
3.2
4.0
HFM Vcc
Sleep Power:
LFM Vcc
1.0
1.7
HFM Vcc
Sleep Power:
LFM Vcc
0.9
1.7
HFM Vcc
PDSLP
765/755/745/
735/725/715
Deep Sleep Power:
LFM Vcc
2.5
8.8
HFM Vcc
778/758/738
773/753/733J
733/723
Deep Sleep Power:
LFM Vcc
2.5
2.9
HFM Vcc
Deep Sleep Power:
LFM Vcc
0.7
HFM Vcc
1.25
Deep Sleep Power:
LFM Vcc
0.6
1.2
0.8
HFM Vcc
PDPRSL 765/755/745/
Deeper Sleep Power
@ 0.748V
W
W
At 35 °C, Note 2
735/725/715 &
778/758/738
P1
753/733J/733/
723
Deeper Sleep Power
(ULV only)@ 0.748V
0.5
At 35 °C, Note 2, 5
Datasheet
79
Thermal Specifications and Design Considerations
®
Table 5-1. Power Specifications for the Intel Pentium M Processor (Sheet 3 of 3)
Processor
Number
Symbol
Parameter
Min
Typ
Max
Unit
Notes
PDPRSL 765/755/745/
Deeper Sleep Power
@ 0.726V
0.7
W
At 35 °C, Note 2
735/725/715 &
778/758/738
P2
753/733J/733/
723
Deeper Sleep Power
(ULV only)@ 0.726
0.4
W
At 35 °C, Note 2, 5
Notes 3, 4
TJ
Junction
Temperature
0
100
°C
NOTES:
1. The Thermal Design Power (TDP) specification should be used to design the processor thermal solution. The
TDP is not the maximum theoretical power the processor can dissipate.
2. Not 100% tested. These power specifications are determined by characterization of the processor currents at
higher temperatures and extrapolating the values for the temperature indicated.
3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to
indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5. For 733J, CPU Signature = 06D8h.
5.1
Thermal Specifications
5.1.1
Thermal Diode
The Pentium M Processor incorporates two methods of monitoring die temperature, the Intel
Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1) must
be used to determine when the maximum specified processor junction temperature has been
reached. The second method, the thermal diode, can be read by an off-die analog/digital converter
(a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal
diode may be used to monitor the die temperature of the processor for thermal management or
instrumentation purposes but cannot be used to indicate that the maximum T of the processor has
J
been reached. When using the thermal diode, a temperature offset value must be read from a
processor Model Specific register (MSR) and applied. See Section 5.1.2 for more details. Please
see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not
asserted. Table 5-2 and Table 5-3 provide the diode interface and specifications.
Note: The reading of the external thermal sensor (on the motherboard) connected to the processor
thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die.
This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the
location of the thermal diode and the hottest location on the die, and time based variations in the die
temperature measurement. Time-based variations can occur when the sampling rate of the thermal
diode (by the thermal sensor) is slower than the rate at which the T temperature can change.
J
Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading
may be characterized using the Intel Thermal Monitor’s Automatic mode activation of thermal
control circuit. This temperature offset must be taken into account when using the processor
thermal diode to implement power management events.
80
Datasheet
Thermal Specifications and Design Considerations
5.1.2
Thermal Diode Offset
A temperature offset value (specified as Toffset in Table 5-3) will be programmed into a
Pentium M Processor Model Specific Register (MSR). This offset is determined by using a thermal
diode ideality factor mean value of n = 1.0022 (shown in Table 5-3) as a reference. This offset must
be applied to the junction temperature read by the thermal diode. Any temperature adjustments due
to differences between the reference ideality value of 1.0022 and the default ideality values
programmed into the on-board thermal sensors, will have to be made before the above offset is
applied.
Table 5-2. Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
THERMDC
B18
A18
Thermal diode anode
Thermal diode cathode
Table 5-3. Thermal Diode Specification
Symbol
Parameter
Min
Typ
Max
Unit
Notes
IFW
Forward Bias Current
5
300
11
μA
Note 1
2, 6
Toffset
Thermal diode temperature
offset
-4
°C
n
Reference Diode Ideality
Factor used to calculate
temperature offset
1.0022
3.06
Notes 2, 3, 4
2, 3, 5
RT
Series Resistance
Ohms
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not
support or recommend operation of the thermal diode when the processor power supplies are not within their
specified tolerance range.
2. Characterized at 100 °C.
3. Not 100% tested. Specified by design/characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
IFW=Is *(e(qVD/nkT) -1)
Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant,
and T = absolute temperature (Kelvin).
Value shown in the table is not the Pentium M Processor thermal diode ideality factor. It is a reference value
used to calculate the Pentium M Processor thermal diode temperature offset.
5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction
temperature. RT as defined includes the pins of the processor but does not include any socket resistance or
board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by
remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Another application is that a temperature offset can be manually calculated and programmed into an offset
register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT*(N-1)*IFWmin]/[(no/q)*ln N
6. Offset value is programmed in processor Model Specific Register.
Datasheet
81
Thermal Specifications and Design Considerations
5.1.3
Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the TCC when the
processor silicon reaches its maximum operating temperature. The temperature at which Intel
Thermal Monitor activates the thermal control circuit is not user configurable and is not software
visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and
serviced during the time that the clocks are on) while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the TCC would
only be activated for very short periods of time when running the most power intensive
applications. The processor performance impact due to these brief periods of TCC activation is
expected to be so minor that it would not be detectable. An under-designed thermal solution that is
not able to prevent excessive activation of the TCC in the anticipated ambient environment may
cause a noticeable performance loss, and may affect the long-term reliability of the processor. In
addition, a thermal solution that is significantly under designed may not be capable of cooling the
processor even when the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting and
stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep technology
transition when the processor silicon reaches its maximum operating temperature. The Intel
Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. If
both modes are activated, Automatic mode takes precedence.
Caution: The Intel Thermal Monitor Automatic Mode mst be enabled via BIOS for the processor to be
operating within specifications.
There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2. These
modes are selected by writing values to the Model Specific registers (MSRs) of the processor. After
Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches
the maximum allowed value for operation.
Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the
processor will perform an Enhanced Intel SpeedStep technology transition to a lower operating
point. When the processor temperature drops below the critical level, the processor will make an
Enhanced Intel SpeedStep technology transition to the last requested operating point. Intel Thermal
Monitor 2 is the recommended mode on the Intel® Pentium® M processors.
If a processor load based Enhanced Intel SpeedStep technology transition (through MSR write) is
initiated when an Intel Thermal Monitor 2 period is active, there are two possible results:
1.If the processor load based Enhanced Intel SpeedStep technology transition target frequency is
higher than the Intel Thermal Monitor 2 transition based target frequency, the processor load-
based transition will be deferred until the Intel Thermal Monitor 2 event has been completed.
2.If the processor load-based Enhanced Intel SpeedStep technology transition target frequency is
lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will
transition to the processor load-based Enhanced Intel SpeedStep technology target frequency
point.
When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists, the clocks will
be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are
processor speed dependent and will decrease linearly as processor core frequencies increase. Once
the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A
small amount of hysteresis has been included to prevent rapid active/inactive transitions of the
TCC when the processor temperature is near the trip point. The duty cycle is factory configured
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Thermal Specifications and Design Considerations
and cannot be modified. Also, automatic mode does not require any additional hardware, software
drivers, or interrupt handling routines. Processor performance will be decreased by the same
amount as the duty cycle when the TCC is active, however, with a properly designed and
characterized thermal solution the TCC most likely will never be activated, or only will be
activated briefly during the most power intensive applications.
The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Intel Thermal Monitor
Control Register is written to a 1, the TCC will be activated immediately, independent of the
processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the
clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor Control
Register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in On-Demand
mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in
12.5% increments. On-Demand mode may be used at the same time Automatic mode is enabled,
however, if the system tries to enable the TCC via On-Demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its
temperature is above the thermal trip point. Bus snooping and interrupt latching are also active
while the TCC is active.
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor feature also
includes one ACPI register, one performance counter register, three model specific registers
(MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the
Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an
interrupt upon the assertion or deassertion of PROCHOT#.
Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and
Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be
used as a safeguard to maintain the processor junction temperature within the 100 °C (maximum)
specification. If the platform thermal solution is not able to maintain the processor junction
temperature within the maximum specification, the system must initiate an orderly shutdown to
prevent damage. If the processor enters one of the above low power states with PROCHOT#
already asserted, PROCHOT# will remain asserted until the processor exits the Low Power state
and the processor junction temperature drops below the thermal trip point.
If automatic mode is disabled, the processor will be operating out of specification. Regardless of
enabling the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the
processor will automatically shut down when the silicon has reached a temperature of
approximately 125 °C. At this point the FSB signal THERMTRIP# will go active. THERMTRIP#
activation is independent of processor activity and does not generate any bus cycles. When
THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified
in Chapter 3.
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Thermal Specifications and Design Considerations
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