D64569-007 [INTEL]
Intel Server Board S5000VCL; 英特尔服务器主板S5000VCL
| 型号： | D64569-007 |
| 厂家： | 
INTEL |
| 描述： | Intel Server Board S5000VCL |
| 文件： | 总76页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Server Board S5000VCL
Technical Product Specification
Intel order number: D64569-007
Revision 2.3
January 2008
Enterprise Platforms and Services Division -
Marketing
Intel® Server Board S5000VCL TPS
Table of Contents
Revision History
Date
Revision
Number
Modifications
Sept. 2006
Nov. 2006
Jan. 2007
1.0
Initial release.
Added technical updates and SAS board information.
2.0
2.1
Removed processor that is not supported by board; added Post-Code Diagnostic
LED information.
Sept. 2007
Jan. 2008
2.2
2.3
Updated product codes and processor information.
Updated processor information.
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Server Board S5000VCL may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata
are available on request.
Intel Corporation server baseboards support peripheral components and contain a number of
high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s
own chassis are designed and tested to meet the intended thermal requirements of these
components when the fully integrated system is used together. It is the responsibility of the
system integrator that chooses not to use Intel developed server building blocks to consult
vendor datasheets and operating parameters to determine the amount of air flow required for
their specific application and environmental conditions. Intel Corporation can not be held
responsible if components fail or the server board does not operate correctly when used outside
any of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2008.
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Table of Contents
Intel® Server Board S5000VCL TPS
Table of Contents
1. Introduction ..........................................................................................................................1
1.1 Server Board Use Disclaimer ..................................................................................1
2. Product Overview.................................................................................................................2
2.1
2.2
Feature Set..............................................................................................................2
Server Board Layout................................................................................................3
Intel® Light-Guided Diagnostics LED Locations.......................................................4
External I/O Connector Locations............................................................................5
2.2.1
2.2.2
3. Functional Architecture.......................................................................................................6
3.1
3.1.1
Intel® 5000V Memory Controller Hub (MCH) ...........................................................8
System Bus Interface...............................................................................................8
Processor Support...................................................................................................8
Memory Sub-system..............................................................................................10
Intel® 6321ESB I/O Controller Hub ........................................................................12
PCI Sub-system.....................................................................................................13
Serial ATA Support................................................................................................13
Parallel ATA (PATA) Support ................................................................................14
USB 2.0 Support....................................................................................................14
Video Support........................................................................................................14
Network Interface Controller (NIC) ........................................................................15
Intel® I/O Acceleration Technolgy ..........................................................................16
Super I/O ...............................................................................................................16
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.4
3.4.1
3.5
4. Platform Management........................................................................................................19
5. Connector / Header Locations and Pin-outs....................................................................20
5.1
5.2
5.3
5.4
5.5
Board Connectors..................................................................................................20
Power Connectors .................................................................................................21
Riser Card Slots.....................................................................................................22
SSI Control Panel Connector.................................................................................22
I/O Connector Pinout Definition .............................................................................23
VGA Connector......................................................................................................23
NIC Connectors .....................................................................................................23
IDE Connector .......................................................................................................24
SATA Connectors..................................................................................................25
5.5.1
5.5.2
5.5.3
5.5.4
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5.5.5
5.5.6
5.5.7
Serial Port Connectors...........................................................................................26
Keyboard and Mouse Connector...........................................................................26
USB Connector......................................................................................................27
Fan Headers..........................................................................................................28
5.6
6. Jumper Block Settings ......................................................................................................29
6.1
6.1.1
6.1.2
6.2
6.3
Recovery Jumper Blocks.......................................................................................29
CMOS Clear and Password Reset Usage Procedure ...........................................30
BMC Force Update Procedure ..............................................................................31
BIOS Select Jumper ..............................................................................................31
PCIe Select Jumper...............................................................................................32
7. Intel® Light Guided Diagnostics........................................................................................33
7.1
7.2
7.3
5-Volt Standby System Status / Fault LED............................................................33
DIMM LEDs ...........................................................................................................35
Post Code Diagnostic LEDs ..................................................................................36
8. Power and Environmental Specifications........................................................................37
8.1
8.2
Intel® Server Board S5000VCL Design Specifications ..........................................37
Baseboard Power Requirements...........................................................................38
Processor Power Support......................................................................................38
Power Supply Output Requirements .....................................................................38
Turn On No Load Operation ..................................................................................39
Grounding..............................................................................................................40
Standby Outputs....................................................................................................40
Remote Sense.......................................................................................................40
Voltage Regulation ................................................................................................40
Dynamic Loading...................................................................................................41
Capacitive Loading ................................................................................................41
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 Closed-Loop Stability.............................................................................................41
8.2.11 Common Mode Noise............................................................................................41
8.2.12 Ripple / Noise ........................................................................................................42
8.2.13 Soft Starting...........................................................................................................42
8.2.14 Timing Requirements.............................................................................................42
8.2.15 Residual Voltage Immunity in Standby Mode........................................................44
9. Regulatory and Certification Information.........................................................................45
9.1
9.1.1
Product Regulatory Compliance............................................................................45
Product Safety Compliance ...................................................................................45
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9.1.2
9.1.3
Product EMC Compliance – Class A Compliance .................................................46
Certifications / Registrations / Declarations...........................................................46
Product Regulatory Compliance Markings ............................................................47
Electromagnetic Compatibility Notices ..................................................................48
FCC Verification Statement (USA) ........................................................................48
ICES-003 (Canada) ...............................................................................................49
Europe (CE Declaration of Conformity) .................................................................49
VCCI (Japan).........................................................................................................49
BSMI (Taiwan).......................................................................................................50
RRL (Korea)...........................................................................................................50
CNCA (CCC-China)...............................................................................................50
Restriction of Hazardous Substances (RoHS) Compliance...................................51
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.4
Appendix A: Integration and Usage Tips................................................................................52
Appendix B: Sensor Tables .....................................................................................................53
Appendix C: POST Error Messages and Handling ................................................................55
Appendix D: POST Code Diagnostic LED Decoder ...............................................................58
Appendix E: Supported Intel® Server Chassis.......................................................................62
Glossary.....................................................................................................................................64
Reference Documents..............................................................................................................67
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List of Figures
List of Figures
Figure 1. Components and Connector Location Diagram.............................................................3
Figure 2. Intel® Light-Guided Diagnostics LED Locations.............................................................4
Figure 3. ATX I/O Layout ..............................................................................................................5
Figure 4. Functional Block Diagram..............................................................................................7
Figure 5. CEK Processor Mounting ..............................................................................................9
Figure 6. Memory Layout............................................................................................................10
Figure 7. SMBUS Block Diagram................................................................................................19
Figure 8. Recovery Jumper Blocks (J3A1, J1C2, J1C4).............................................................30
Figure 9. System Status / Fault LED Location............................................................................33
Figure 10. DIMM LED Locations.................................................................................................35
Figure 11. POST Code Diagnostic LED Location.......................................................................36
Figure 12. Output Voltage Timing...............................................................................................43
Figure 13. Turn On/Off Timing (Power Supply Signals)..............................................................44
Figure 14. Diagnostic LED Placement Diagram .........................................................................58
Figure 15. Intel® Server System SR1530CL/SR1530CLR..........................................................62
Figure 16. Intel® Server System SR1530HCL/SR1530HCLR.....................................................63
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List of Tables
Intel® Server Board S5000VCL TPS
List of Tables
Table 2. I2C Addresses for Memory Module SMB ......................................................................10
Table 3. Maximum Six-DIMM System Memory Configuration – x4 Single Rank ........................10
Table 4. Maximum Six-DIMM System Memory Configuration – x8 Dual Rank...........................11
Table 5. PCI Bus Segment Characteristics.................................................................................13
Table 6. Video Modes.................................................................................................................15
Table 7. NIC2 Status LED...........................................................................................................16
Table 8. Serial A Port Header Pin-out (External DB9)................................................................17
Table 9. Internal Serial B Port Header Pin-out............................................................................17
Table 10. Board Connector Matrix..............................................................................................20
Table 11. Power Connector Pin-out (J3K3) ................................................................................21
Table 12. 12V Power Connector Pin-out (J9E1).........................................................................21
Table 13. Power Supply Signal Connector Pin-out (J9C1).........................................................22
Table 14. Front Panel SSI Standard 24-pin Connector Pin-out (J2K2) ......................................22
Table 15. VGA Connector Pin-out (J7A1)...................................................................................23
Table 16. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA5A1)......................................23
Table 17. 44-pin IDE Connector Pin-out (J2K5) .........................................................................24
Table 18. SATA Connector Pin-out (J1J2, J1J1)........................................................................25
Table 19. SATA / SAS Connector Pin-out (J1G2, J1G1, J1F1, J1E4)........................................25
Table 20. 9-pin Serial Header Pin-out (J8A1, J1A1)...................................................................26
Table 21. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A2) ...........................................26
Table 22. External USB Connector Pin-out (J9A2).....................................................................27
Table 23. Internal USB Connector Pin-out (J3K1)......................................................................27
Table 24. CPU Fan Connector Pin-out (J2K3, J2K4) .................................................................28
Table 25. PCI Fan Connector Pin-out (J1K1) .............................................................................28
Table 26. Recovery Jumpers (J3A1, J1C1, J1C2)......................................................................29
Table 27. BIOS Select Jumper (J3A2) .......................................................................................32
Table 28. PCI Express* x4/x8 Select Jumper (J1E1) .................................................................32
Table 29. Server Board Design Specifications ...........................................................................37
Table 30. Dual-Core Intel® Xeon® processor 5100 series and Quad-Core Intel® Xeon®
processor 5300 series TDP Guidelines................................................................................38
Table 31. 400W Load Ratings ....................................................................................................39
Table 32. No-load Operating Range...........................................................................................39
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List of Tables
Table 33. Voltage Regulation Limits ...........................................................................................40
Table 34. Transient Load Requirements.....................................................................................41
Table 35. Capacitive Loading Conditions ...................................................................................41
Table 36. Ripple and Noise.........................................................................................................42
Table 37. Output Voltage Timing ................................................................................................42
Table 38. Turn On/Off Timing .....................................................................................................43
Table 39. POST Error Messages and Handling..........................................................................55
Table 40. POST Error Beep Codes ............................................................................................57
Table 41. BMC Beep Codes .......................................................................................................57
Table 42. Example POST Progress Code LED ..........................................................................58
Table 43. Diagnostic LED POST Code Decoder ........................................................................59
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List of Tables
Intel® Server Board S5000VCL/S5000VCLSASBB TPS
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Overview
1. Introduction
This Technical Product Specification (TPS) provides board-specific information about the
features, functionality, and high-level architecture of the Intel® Server Board S5000VCL. See the
Intel® 5000 Series Chipsets Server Board Family Datasheet more information about board sub-
systems, including chipset, BIOS, system management, and system management software.
There are four product codes of the Intel Server Board S5000VCL:
•
•
•
•
SS5000VCL
S5000VCLSASBB
BBS5000VCLR
BBS5000VCLSASR
All references to the Intel® Server Board S5000VCL refer to all product codes listed above,
unless noted otherwise.
1.1 Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain high-density VLSI and
power delivery components that need adequate airflow to cool. Intel ensures through its own
chassis development and testing that when Intel server building blocks are used together, the
fully integrated system will meet the intended thermal requirements of these components. It is
the responsibility of the system integrator who chooses not to use Intel developed server
building blocks to consult vendor datasheets and operating parameters to determine the amount
of air flow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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Product Overview
Intel® Server Board S5000VCL TPS
2. Product Overview
The Intel® Server Board S5000VCL is a monolithic printed circuit boards that support the high-
density 1U server market.
2.1 Feature Set
Feature
Processors
Description
771-pin LGA sockets supporting one or two Dual-Core Intel® Xeon® processors 5100
series, low-voltage Quad-Core® Xeon® processors 5300 series, and low-voltage Quad-
Core® Xeon® processors 5400 series with system bus speeds of 1066 MHz or 1333
MHz.
For a complete list of supported processors, see the following link:
http://support.intel.com/support/motherboards/server/S5000VCL
Memory
Chipset
Six keyed DIMM slots support fully buffered DIMM technology (FBDIMM) memory. 240-
pin DDR2-677 FBDIMMs must be used.
Intel® 5000V Chipset family, which includes the following components:
Intel® 5000V Memory Controller Hub
Intel® 6321ESB I/O Controller Hub
On-board Connectors /
Headers
External connections:
Stacked PS/2* ports for keyboard and mouse
Two RJ45 NIC connectors for 10/100/1000 Mb connections
Two USB 2.0 ports
Video connector
Com 1 or Serial A (DB9)
Internal connectors/headers:
One USB port header, capable of providing two USB 2.0 ports
One DH10 Serial B header
Six SATA ports or four SAS ports via the Intel® 6321ESB I/O Controller Hub.
These ports support 3Gb/s and integrated SW RAID 0 or 1
One 40-pin (power + I/O) ATA/100 connector for optical drive support
SSI-compliant 24-pin control panel header
SSI-compliant 24-pin main power connector support the ATX-12 V standard on
the first 20 pins
8-pin +12 V processor power connector
Add-in PCI, PCI-X*, PCI
Express* Cards
One PCI super-slot that will support one 1U riser card with one PCI-X* and one PCI
Express* connectors
On-board Video
ATI* ES1000 video controller with 16 MB DDR SDRAM
On-board Hard Drive
Controller
Six 3 Gb/s SATA ports, or four SAS ports
Intel® Embedded Server RAID Technology II with RAID levels 0, 1, 10
Two 10/100/1000 NICs supporting Intel® I/O Acceleration Technology
LAN
System Fans
Two CPU 4-pin fan headers supporting two system blowers and one 3-pin fan header
supporting a system fan
Support for Intel® System Management Software
System Management
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Product Overview
2.2 Server Board Layout
A
B
C D
E
Z
Y
F
G
H
X
W
V
U
T
I
S
R
Q
P
O
N
M
L
K
J
AF002052
Figure 1. Components and Connector Location Diagram
Description Description
A
B
C
D
E
F
G
H
I
Post code Diagnostic LEDs
System Fault/Status LED
Speaker
O
System Fan Header
SATA 0
P
Q
SATA 1
Super Slot (Slot 6)
R
SSI 24-pin Control Panel Header
CPU 1 Fan Header
SATA 2 / SAS 0
SATA 3 / SAS 1
SATA 4 / SAS 2
SATA 5 / SAS 3
Battery
External IO Connectors
Main Power Connector
Power Supply Auxiliary Connector
CPU Power Connector
FBDIMM Slots
S
T
U
V
W
J
CPU Socket 1
X
K
L
CPU Socket 2
Y
SATA SGPIO
CPU 2 Fan Header
Dual Port USB 2.0 Header
Primary IDE Connector
Z
Serial B Port Header
M
N
Not shown
SAS GPIO (SAS version of the server board only)
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Product Overview
Intel® Server Board S5000VCL TPS
2.2.1
Intel® Light-Guided Diagnostics LED Locations
B
A
D
H
G
F
E
C
AF002053
Description
Description
A
B
C
D
E
Post-Code Diagonstic LEDs
System Fault / Status LED
CPU 1 Fault LED
E
F
CPU 2 Fan Fault LED
CPU 1 Fan Fault LED
System Fan Fault LED
5 VSB LED
G
H
DIMM Fault LEDs
CPU 2 Fault LED
Figure 2. Intel® Light-Guided Diagnostics LED Locations
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Product Overview
2.2.2
External I/O Connector Locations
A
B
C
E
G
D
F
NIC1
NIC2
10/100/ 10/100/
1000 Mb 1000 Mb
Serial A
USB
0-1
Network
AF001640
Figure 3. ATX I/O Layout
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Functional Architecture
Intel® Server Board S5000VCL TPS
3. Functional Architecture
The architecture and design of the Intel® Server Board S5000VCL is based on the Intel® 5000V
Chipset. The chipset is for systems based on the Dual-Core Intel® Xeon® processor 5100 series,
low-voltage Quad-Core Intel® Xeon® processor 5300 series and low-voltage Quad-Core Intel®
Xeon® processor 5400 series with system bus speeds of 1067 MHz and 1333 MHz.
The chipset has two main components: the Intel® 5000V Memory Controller Hub (MCH) for the
host bridge and the Intel® 6321ESB I/O Controller Hub for the I/O subsystem.
This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up this server board. For in depth information
on each of the chipset components and each of the functional architecture blocks, see the Intel®
5000 Series Chipsets Server Board Family Datasheet.
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Functional Architecture
1333 MT/s
Super Slot
Serial Port B (Internal)
Serial Port A (Back Panel)
PCI-X* 64-bit/133 MHz
PCI-Express x4 (ESB2, Port 1)
PCI-Express x4 (ESB2, Port 2)
PATA
ATI*
ES1000
Video
PCI-X x4
GBE
LSI* 1064E
SATA0
SATA1
SATA2 / SAS0
SATA3 / SAS1
SATA4 / SAS2
SATA5 / SAS3
Figure 4. Functional Block Diagram
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Functional Architecture
Intel® Server Board S5000VCL TPS
3.1 Intel® 5000V Memory Controller Hub (MCH)
The memory controller hub (MCH) is a single 1432 pin FCBGA package that includes these
core platform functions:
•
•
•
•
•
System bus interface for the processor sub-system
Memory controller
PCI Express* ports including the enterprise south bridge interface (ESI)
FBD thermal management
SMBUS interface
3.1.1
System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus
interfaces that connect to the processors. Each front side bus on the MCH uses a 64-bit wide
1066- or 1333-MHz data bus. The 1333-MHz data bus can transfer data at up to 10.66 GB/s.
The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory.
The MCH is the priority agent for both front side bus interfaces, and is optimized for one
processor on each bus.
3.1.2
Processor Support
The server board supports one or two Dual-Core Intel® Xeon® processors 5100 series or low
voltage Quad-Core Intel® Xeon® processor 5300 series, or low voltage Quad-Core Intel® Xeon®
processor 5400 series with system bus speeds of 1066 MHz, and 1333 MHz, and core
frequencies starting at 1.6 GHz. Previous generations of the Intel® Xeon® processor are not
supported.
For a complete list of supported processors, see the following link:
http://support.intel.com/support/motherboards/server/S5000VCL
Note: Only Dual-Core Intel® Xeon® processors 5100 series or low-voltage Quad-Core Intel®
Xeon® processor 5300 and 5400 series, that support system bus speeds of 1066 MHz, and
1333 MHz are supported.
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Functional Architecture
3.1.2.1
Processor Population Rules
When two processors are installed, both must be of identical revision, core voltage, and
bus/core speed. When only one processor is installed, it must be in the socket labeled CPU1.
The other socket must be empty.
The board provides up to 90A max, 70A TDC per processor. Processors with higher current
requirements are not supported.
3.1.2.2
Common Enabling Kit (CEK) Design Support
The server board complies with Intel’s common enabling kit (CEK) processor mounting and heat
sink retention solution. The server board ships with a CEK spring snapped onto the underside of
the server board, beneath each processor socket. The heat sink attaches to the CEK, over the
top of the processor and the thermal interface material (TIM). See the figure below for the
stacking order of the chassis, CEK spring, server board, TIM, and heat sink.
The CEK spring is removable, allowing for the use of non-Intel heat sink retention solutions.
Heatsink assembly
Thermal Interface
Material (TIM)
Server Board
CEK Spring
Chassis
AF001010
Figure 5. CEK Processor Mounting
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Functional Architecture
Intel® Server Board S5000VCL TPS
3.1.3
Memory Sub-system
The MCH masters two fully buffered DIMM (FBDIMM) memory channels. FBDIMM memory
utilizes a narrow high-speed frame-oriented interface referred to as a channel. The two
channels are routed to six DIMM slots and support registered DDR2-667 FBDIMM memory
(stacked or unstacked). Peak FBDIMM memory data bandwidth in dual channel mode is
8.0GB/s (2x4.0 GB/s) with DDR2-667/PC2-5300 (3.0 ns at CL5).
Channel A
Channel B
AF001011
Figure 6. Memory Layout
To boot the system, the system BIOS uses a dedicated I2C bus to retrieve DIMM information
needed to program the MCH memory registers.
Table 1. I2C Addresses for Memory Module SMB
Device
Address
DIMM A1
0xA0
DIMM A2
DIMM A3
DIMM B1
DIMM B2
DIMM B3
0xA2
A4
A0
A2
A4
3.1.3.1
Supported Memory
Up to six DDR2-667 fully-buffered DIMMs (FBD memory) can be installed.
Table 2. Maximum Six-DIMM System Memory Configuration – x4 Single Rank
DRAM Technology x4 Single Rank
Maximum Capacity Non-Mirrored
Mode
256 Mb
512 Mb
1.5 GB
3 GB
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Functional Architecture
1024 Mb
2048 Mb
6 GB
12 GB
Table 3. Maximum Six-DIMM System Memory Configuration – x8 Dual Rank
DRAM Technology x8 Dual Rank
Maximum Capacity Non-Mirrored
Mode
256 Mb
512 Mb
1.5 GB
3 GB
6 GB
1024 Mb
2048 Mb
12 GB
Note: DDR2 DIMMs that are not fully buffered are NOT supported. See the Intel® Server Board
S5000VCL Tested Memory List for a list of supported memory.
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Functional Architecture
Intel® Server Board S5000VCL TPS
3.1.3.2
DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller. The operating
mode is determined by the number of DIMMs installed. DIMMs must be populated in pairs in
DIMM slot order: A1 & B1, A2 & B2. DIMMs within a pair must be identical with respect to size,
speed, and organization, but DIMM capacities can be different across different DIMM pairs.
Note: The server board supports single DIMM mode operation. Intel will only validate and
support this configuration with a single 512 MB x8 FBDIMM installed in DIMM slot A1.
3.2 Intel® 6321ESB I/O Controller Hub
The Intel® 6321ESB I/O Controller Hub is a multi-function device that provides four distinct
functions: an IO Controller, a PCI-X* Bridge, a GB Ethernet Controller, and a baseboard
management controller (BMC). Each function within the controller hub has its own set of
configuration registers. Once configured, each appears to the system as a distinct hardware
controller.
The controller hub provides the gateway to all PC-compatible I/O devices and features. The
server board uses these Intel® 6321ESB I/O Controller Hub features:
1. PCI-X* bus interface
2. Six channel SATA interface w/SATA busy and fault LED control
3. Dual GbE MAC
4. Baseboard management controller (BMC)
5. Single ATA interface, with Ultra DMA 100 capability
6. Universal Serial Bus 2.0 (USB) interface
7. Removable media drives
8. LPC bus interface
9. PC-compatible timer/counter and DMA controllers
10. APIC and 8259 interrupt controller
11. Power management
12. System RTC
13. VT technology
14. General purpose I/O
For additional information, see the Intel® 5000 Series Chipsets Server Board Family Datasheet.
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Functional Architecture
3.2.1
PCI Sub-system
The primary I/O buses support one Super Slot connector, which supports one PCI riser
assembly that supports two PCI slots: one low-profile PCI Express* x8, and either a mid-height
PCI-X* 133, or one low-profile PCI Express*x4 and one mid-height PCI Express x4. The PCI
bus complies with the PCI Local Bus Specification, Revision 2.3. The PCI-X bus complies with
PCI-X Local BUS Specification, Revision 2.0, the PCI Express ports comply with the PCI
Express Base Specification, Revision 1.0a. PCI 32 supports the VGA ATI* ES1000 video
controller.
Table 4. PCI Bus Segment Characteristics
PCI Bus Segment
PXA
Voltage
Width
Speed
Type
On-board Device
Support
Full-height riser slot
3.3V/5.0V
64 bit
133 MHz PCI-X*
6321ESB
PE1, PE2
3.3V
x8
20 Gb/S
PCI
Low-profile riser slot
Express*
BNB PCI Express*
Ports 4, 5
3.2.1.1
PXA: 64-bit, 133MHz PCI Subsystem
One 64-bit PCI-X* bus segment is directed through the 6321ESB ICH6. This PCI-X segment,
PXA, supports up to three PCI add-in cards on the full-height riser card.
3.2.1.2
PE2: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the 6321ESB. This PCI Express segment,
PE2, supports one x8 PCI Express segment to the proprietary I/O module mezzanine connector.
3.2.1.3
PCI Riser Slot
The primary I/O buses for this server board supports one Super Slot connector which supports
one PCI riser assembly supporting two PCI slots:
•
•
One low-profile PCI Express* x8 and one mid-height PCI-X* 133
Or one low-profile PCI Express*x4 and one mid-height PCI Express* x4.
3.2.2
Serial ATA Support
The Intel® 6321ESB I/O Controller Hub has an integrated Serial ATA (SATA) controller that
supports independent DMA operation on six ports and supports data transfer rates of up to
3.0 Gb/s. The six SATA ports on the server board are numbered SATA-0 thru SATA-5. The
SATA ports can be enabled/disabled and/or configured through the BIOS Setup Utility.
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3.2.2.1
Intel® Embedded Server RAID Technology Support
The embedded Intel® Embedded Server RAID Technology solution offers data stripping (RAID
Level 0) and data mirroring (RAID Level 1). For higher performance, data stripping alleviates
disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA
port offers.
Data mirroring is for data security. If a disk fails, a mirrored copied of the failed disk is brought
on-line. There is no loss of either PCI resources (request/grant pair) or add-in card slots.
Intel® Embedded Server RAID Technology functionality requires these items:
15. Intel® 6321ESB I/O Controller Hub
16. Intel® Embedded Server RAID Technology Option ROM
17. Intel® Application Accelerator RAID edition drivers, most recent revision
•
At least two SATA hard disk drives
Intel® Embedded Server RAID Technology is not available in these configurations:
18. The SATA controller in compatible mode
•
Intel® Embedded Server RAID Technology has been disabled
3.2.3
Parallel ATA (PATA) Support
The integrated IDE controller of the 6321ESB ICH6 provides one IDE channel. It redefines
signals on the IDE cable to allow both host and target throttling of data and transfer rates of up
to 100 MB/s. The IDE channel provides optical drive support. The BIOS initializes and supports
ATAPI devices such as LS-120/240, CD-ROM, CD-RW and DVD-ROM. The IDE channel is
accessed through a high-density 40-pin connector ((J2K5) that provides I/O signals. The ATA
channel can be configured and enabled or disabled through the BIOS Setup Utility.
3.2.4
USB 2.0 Support
The USB controller functionality integrated into the 6321ESB provides the interface for up to
four USB 2.0 ports. Two external connectors are located on the back edge of the server board
and one internal 2x5 header supports two optional USB 2.0 ports.
3.3 Video Support
An ATI* ES1000 PCI graphics accelerator with 16 MB of video DDR SDRAM and support
circuitry for an embedded SVGA video sub-system is provided. The ATI ES1000 chip contains
an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin BGA. One
4M x 16 x 4 bank DDR SDRAM chip provides 16 MB of video memory.
The SVGA sub-system supports modes up to 1024 x 768 resolution in 8 / 16 / 32 bpp modes
under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate.
Video is accessed using a standard 15-pin VGA connector found on the back edge of the server
board. Video signals are also made available through the 120-pin bridge-board connector that
provides signals for an optional video connector on the control panel. Video is routed to both the
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Functional Architecture
rear video connector and a control panel video connector. Video is present at both connectors
simultaneously and cannot be disabled at either connector individually. Video monitors can be
hot-plugged.
3.3.1.1
Video Modes
The ATI* ES1000 chip supports all standard IBM* VGA modes. The table shows the 2D modes
supported for both CRT and LCD.
Table 5. Video Modes
2D Video Mode Support
2D Mode
640x480
Refresh Rate (Hz)
8 bpp
16 bpp
32 bpp
Supported
60, 72, 75, 85, 90, 100, Supported
120, 160, 200
Supported
800x600
1024x768
1152x864
60, 70, 72, 75, 85, 90,
100, 120, 160
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
60, 70, 72, 75, 85, 90,
100
43, 47, 60, 70, 75, 80,
85
1280x1024
1600x1200
60, 70, 74, 75
52
Supported
Supported
Supported
Supported
Supported
Supported
3.3.1.2
Video Memory Interface
The memory controller sub-system of the ES1000 arbitrates requests from the direct memory
interface, the VGA graphics controller, the drawing co-processor, the display controller, the
video scalar, and the hardware cursor. Requests are serviced in a manner that ensures display
integrity and maximum CPU/co-processor drawing performance.
The server board supports a 16 MB (4 Meg x 16-bit x four banks) DDR SDRAM device for video
memory.
3.4 Network Interface Controller (NIC)
Network interface support is provided from the built in Dual GbE MAC features of the 6321ESB
in conjunction with the Intel® 82563EB compact Physical Layer Transceiver (PHY). Together,
they provide support for dual LAN ports designed for 10/100/1000 Mbps operation.
The 82563EB device is based upon proven PHY technology integrated into Intel’s gigabit
Ethernet controllers. The physical layer circuitry provides a standard IEEE 802.3 Ethernet
interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and
802.3ab). The 82563EB device can transmit and receive data at rates of 1000 Mbps, 100 Mbps,
or 10 Mbps.
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Intel® Server Board S5000VCL TPS
Each network interface controller (NIC) drives two LEDs located on each network interface
connector. The link/activity LED at the right of the connector indicates network connection when
on, and Transmit/Receive activity when blinking. The speed LED at the left indicates 1000-Mbps
operation when amber, 100-Mbps operation when green, and 10-Mbps when off.
Table 6. NIC2 Status LED
LED Color
LED State
NIC State
Off
10 Mbps
Green/Amber (Left)
Green
Amber
On
100 Mbps
1000 Mbps
Active Connection
Green (Right)
Blinking
Transmit / Receive activity
3.4.1
Intel® I/O Acceleration Technolgy
Intel® I/O Acceleration Technology moves network data efficiently through Intel® Xeon®
processor-based servers for improved application responsiveness across diverse operating
systems and virtualized environments.
Intel® I/OAT improves network application responsiveness by unleashing the power of Intel®
Xeon® processors through efficient network data movement and reduced system overhead. Intel
multi-port network adapters with Intel I/OAT provide high-performance I/O for server
consolidation and virtualization via stateless network acceleration that seamlessly scales across
multiple ports and virtual machines. Intel I/OAT provides safe and flexible network acceleration
through tight integration into popular operating systems and virtual machine monitors, avoiding
the support risks of third-party network stacks and preserving existing network requirements
such as teaming and failover.
3.5 Super I/O
Legacy I/O support is provided by a National Semiconductor* PC87427 Super I/O device. This
chip contains the necessary circuitry to support these functions:
•
•
•
•
•
GPIOs
Serial ports
Keyboard and mouse support
Wake up control
System health support
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Functional Architecture
3.5.1.1
Serial Ports
The server board provides an external DB9 serial port and an internal serial header.
Table 7. Serial A Port Header Pin-out (External DB9)
RJ45
Signal
Abbreviation
DB9
1
Request to Send
RTS
7
4
3
5
9
2
2
3
4
5
6
7
8
Data Terminal Ready
Transmitted Data
Signal Ground
Ring Indicator
DTR
TD
SGND
RI
Received Data
DCD or DSR
RD
DCD/DSR
CTS
1 or 6 (see note)
8
Clear To Send
Table 8. Internal Serial B Port Header Pin-out
Pin
Signal Name
DCD
Serial Port A Header Pin-out
1
2
3
4
5
6
7
8
9
DSR
RX
RTS
TX
CTS
DTR
RI
GND
Note: The RJ45-to-DB9 adapter should match the configuration of the serial device used. One
of two pin-out configurations is used, depending on whether the serial device requires a DSR or
DCD signal. The final adapter configuration should also match the desired pin-out of the RJ45
connector, as it can also be configured to support either DSR or DCD.
3.5.1.2
Floppy Disk Controller
The server board does not support a floppy disk controller (FDC) interface, but the system BIOS
recognizes USB floppy devices.
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3.5.1.3
Keyboard and Mouse Support
Dual stacked PS/2 ports on the back edge of the server board support a keyboard and mouse.
Either port can support a mouse or keyboard. Neither port supports hot plugging.
3.5.1.4
Wake-up Control
The super I/O contains functionality allows events to power-on and power-off the system.
3.5.1.5
System Health Support
The super I/O provides an interface via GPIOs for BIOS and system management firmware to
activate the diagnostic LEDs, the FRU fault indicator LEDs for processors, FBDIMMS, fans, and
the system status LED. See section 7 to locate the LEDs.
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Platform Management
4. Platform Management
The platform management sub-system is based on the integrated baseboard management
controller (BMC) features of the Intel® 6321ESB I/O Controller Hub. The onboard platform
management subsystem consists of communication buses, sensors, system BIOS, and system
management firmware.
See Appendix B for onboard sensor data. For additional platform management information see
the Intel® 5000 Series Chipsets Server Board Family Datasheet.
LM4
Figure 7. SMBUS Block Diagram
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5. Connector / Header Locations and Pin-outs
5.1 Board Connectors
Table 9. Board Connector Matrix
Connector
Quantity
Server Board Reference Designators
Connector Type
CPU Power
Pin
Count
Power supply
3
J9E1
8
J9B1
Main Power
P/S Aux
24
5
J9C1
CPU
2
8
1
1
2
J8H1, J5H1
CPU Sockets
DIMM Sockets
Card Edge
771
240
98
40
4
Main Memory
Super Slot
IDE
J7A2, J7A3, J7A4, J7A5, J8A2, J8A3
J4B2
J2K5
Shrouded Header
Header
CPU Blowers #1
and #2
J2K3, J2K4
System Fan
Battery
2
1
1
2
1
1
1
2
J1K1
Header
3
XBT3E1
J9A2
Battery Holder
PS2, stacked
External
3
Keyboard/Mouse
Rear USB
12
4
J9A2
Serial Port A
Serial Port B
Video connector
J8A1
External
9
J1A1
Header
9
J7A1
External, D-Sub
15
14
LAN connector
10/100/1000
JA6A1, JA5A1
External LAN connector
with built-in magnetic
SSI Control Panel
Internal USB
1
1
2
4
4
J2K2
Header
Header
Header
Header
Jumper
24
10
7
J3K1
Serial ATA (SATA)
SATA/SAS
J1J1, J1J2
J1G2, J1G1, J1F1, J1E4
J1C2, J1C4
7
System Recovery
Setting Jumpers
3
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Connector / Header Locations and Pin-outs
5.2 Power Connectors
The main power supply connection is obtained using an SSI compliant 2x12 pin connector
(J9B1). Two additional power related connectors; one SSI compliant 2x4 pin power connector
(J9E1) supports additional 12V. One SSI compliant 1x5 pin connector (J9C1) provides I2C
monitors the power supply.
Table 10. Power Connector Pin-out (J3K3)
Pin
Signal
+3.3Vdc
Color
Orange
Pin
13
Signal
+3.3Vdc
Color
Orange
1
2
3
4
5
6
7
8
9
+3.3Vdc
GND
Orange
Black
Red
14
15
16
17
18
19
20
21
22
23
24
-12Vdc
GND
Blue
Black
Green
Black
Black
Black
White
Red
+5Vdc
GND
PS_On#
GND
Black
Red
+5Vdc
GND
GND
Black
Gray
GND
PWR_OK
5VSB
RSVD_(-5V)
+5Vdc
+5Vdc
+5Vdc
GND
Purple
Yellow
Yellow
Orange
10
11
12
+12Vdc
+12Vdc
+3.3Vdc
Red
Red
Black
Table 11. 12V Power Connector Pin-out (J9E1)
Pin
Signal
Color
Black
1
2
3
4
5
6
7
8
GND
GND
GND
GND
Black
Black
Black
+12Vdc
+12Vdc
+12Vdc
+12Vdc
Yellow/Black
Yellow/Black
Yellow/Black
Yellow/Black
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Table 12. Power Supply Signal Connector Pin-out (J9C1)
Pin
1
Signal
Color
Orange
SMB_CLK_ESB_FP_PWR_R
2
3
4
5
SMB_DAT_ESB_FP_PWR_R
SMB_ALRT_3_ESB_R
3.3V SENSE-
Black
Red
Yellow
Green
3.3V SENSE+
5.3 Riser Card Slots
The server board has one riser card slot. The riser card slot is capable of supporting one riser
card that supports one PCI-X* 133 full-height / mid-length add-in card and one low-profile PCI
Express* x8 add-in-card.
5.4 SSI Control Panel Connector
The server board provides a 24-pin SSI control panel connector (J2K2) for use with non-Intel
chassis. The following table provides the pin-out for this connector.
Table 13. Front Panel SSI Standard 24-pin Connector Pin-out (J2K2)
Pin
Signal Name
P3V3_STBY
Control Panel Pin-out
Pin
Signal Name
P3V3_STBY
1
3
5
7
9
2
4
6
8
O
O
O
O
O
O
O
O
O
O
O
O
O
Key
P5V_STBY
Power
LED
FP_PWR_LED_L
P3V3
FP_ID_LED_L
Cool Fault
O
O
O
O
O
O
O
O
O
O
FP_STATUS_LED1_R
FP_STATUS_LED2_R
LAN_ACT_A_L
HDD
LED
System
Fault
HDD_LED_ACT_R
FP_PWR_BTN_L
GND
10
12
14
16
18
20
22
24
11
13
15
17
19
21
23
Power
Button
LAN A
Link / Act
LAN_LINKA_L
Reset
Button
Reset Button
GND
PS_I2C_3VSB_SDA
PS_I2C_3VSB_SCL
FP_CHASSIS_INTRU
LAN_ACT_B_L
SMBus
Intruder
Sleep
Button
FP_ID_BTN_L
TEMP_SENSOR
FP_NMI_BTN_L
LAN B
Link / Act
NMI
LAN_LINKB_L
O
O
O
O
O
O
O
O
ID LED
ID Button
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Connector / Header Locations and Pin-outs
5.5 I/O Connector Pinout Definition
5.5.1
VGA Connector
The following table details the pin-out of the VGA connector (J7A1).
Table 14. VGA Connector Pin-out (J7A1)
Pin
Signal Name
V_IO_R_COnN
Description
Red (analog color signal R)
1
2
3
4
5
6
7
8
9
V_IO_G_COnN
V_IO_B_COnN
TP_VID_COnN_B4
GND
Green (analog color signal G)
Blue (analog color signal B)
No connection
Ground
GND
Ground
GND
Ground
GND
Ground
TP_VID_COnN_B9
GND
No Connection
Ground
10
11
12
13
14
15
TP_VID_COnN_B11
V_IO_DDCDAT
V_IO_HSYNC_COnN
V_IO_VSYNC_COnN
V_IO_DDCCLK
No connection
DDCDAT
HSYNC (horizontal sync)
VSYNC (vertical sync)
DDCCLK
5.5.2
NIC Connectors
The server board provides two RJ45 NIC connectors oriented side-by-side on the back edge of
the board (JA6A1, JA5A1). The pin-out for each connector is identical.
Table 15. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA5A1)
Pin
Signal Name
GND
Pin
Signal Name
NIC_A_MDI0P
1
2
3
4
5
6
7
8
9
P1V8_NIC
10
NIC_A_MDI0N
NIC_LINKA_1000_N (LED
NIC_LINKA_100_N (LED)
NIC_ACT_LED_N
NIC_LINK_LED_N
GND
NIC_A_MDI3P
NIC_A_MDI3N
NIC_A_MDI2P
NIC_A_MDI2N
NIC_A_MDI1P
NIC_A_MDI1N
11 (D1)
12 (D2)
13 (D3)
14
15
16
GND
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5.5.3
IDE Connector
The server board includes an IDE connector that supports a single slimline optical drive such as
a CD-ROM or DVD-ROM drive. The connector has 44 pins providing support for both power and
I/O singles.
Table 16. 44-pin IDE Connector Pin-out (J2K5)
Pin
Signal Name
Pin
Signal Name
1
3
5
7
9
ESB_PLT_RST_IDE_N
2
4
6
8
GND
RIDE_DD_7
RIDE_DD_6
RIDE_DD_5
RIDE_DD_4
RIDE_DD_3
RIDE_DD_2
RIDE_DD_1
RIDE_DD_0
GND
RIDE_DD_8
RIDE_DD_9
RIDE_DD_10
RIDE_DD_11
RIDE_DD_12
RIDE_DD_13
RIDE_DD_14
RIDE_DD_15
KEY
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
RIDE_DDREQ
RIDE_DIOW_N
RIDE_DIOR_N
RIDE_PIORDY
RIDE_DDACK_N
IRQ_IDE
GND
GND
GND
GND
GND
TP_PIDE_32
IDE_PRI_CBLSNS
RIDE_DA2
RIDE_DCS3_N
GND
RIDE_DA1
RIDE_DA0
RIDE_DCS1_N
LED_IDE_N
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Connector / Header Locations and Pin-outs
5.5.4
SATA Connectors
The server board provides two SATA (Serial ATA) connectors: SATA-0 (J1J2), SATA-1 (J1J1),
and four SATA (Serial ATA) / SAS (serial-attached SCSI) connectors: SATA-2 / SAS-0 (J1G2),
SATA-3 / SAS-1 (J1G1), SATA-4 / SAS-2 (J1F1), and SATA-5 / SAS-3 (J1E4).
Table 17. SATA Connector Pin-out (J1J2, J1J1)
Pin
Signal Name
GND
Description
1
2
3
4
5
6
7
GND1
SATA#_TX_P_C
SATA#_TX_N_C
GND
Positive side of transmit differential pair
Negative side of transmit differential pair
GND2
SATA#_RX_N_C
SATA#_RX_P_C
GND
Negative side of Receive differential pair
Positive side of Receive differential pair
GND3
Table 18. SATA / SAS Connector Pin-out (J1G2, J1G1, J1F1, J1E4)
Pin
Signal Name
GND
Description
1
2
3
4
5
6
7
GND1
SATA#_TX_P_C
SATA#_TX_N_C
GND
Positive side of transmit differential pair
Negative side of transmit differential pair
GND2
SATA#_RX_N_C
SATA#_RX_P_C
GND
Negative side of Receive differential pair
Positive side of Receive differential pair
GND3
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5.5.5
Serial Port Connectors
The server board provides one external 9-pin Serial ‘A’ port (J8A1) and one internal 9-pin Serial
B port header (J1A1). The following tables define the pin-outs for each.
Table 19. 9-pin Serial Header Pin-out (J8A1, J1A1)
Pin
Signal Name
SPA_DCD
Description
DCD (carrier detect)
1
2
3
4
5
6
7
8
9
SPA_DSR
SPA_SIN
SPA_CTS
TP_SPA_RI
SPA_RTS
SPA_SOUT
SPA_DTR
GND
DSR (data set ready)
RXD (receive data)
CTS (clear to send)
RI (Ring Indicate)
RTS (request to send)
SOUT (serial out)
DTR (Data terminal ready)
Ground
5.5.6
Keyboard and Mouse Connector
Two stacked PS/2 ports (J9A2) are support both a keyboard and a mouse. Either PS/2 port can
support a mouse or a keyboard. The following table details the pin-out of the PS/2 connector.
Table 20. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A2)
Pin
1
Signal Name
KB_DATA_F
Description
Keyboard Data
2
NC
No Connect
Ground
3
GND
4
P5V_KB_F
KB_CLK_F
NC
Keyboard / mouse power
Keyboard Clock
No Connect
Mouse Data
No Connect
Ground
5
6
7
MS_DATA_F
NC
8
9
GND
10
11
12
13
14
15
16
17
P5V_KB_F
MS_CLK_F
NC
Keyboard / mouse power
Mouse Clock
No Connect
Ground
GND
GND
Ground
GND
Ground
GND
Ground
GND
Ground
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Connector / Header Locations and Pin-outs
5.5.7
USB Connector
The following table details the pin-out of the external USB connectors (J9A2) found on the back
edge of the server board.
Table 21. External USB Connector Pin-out (J9A2)
Pin
Signal Name
Description
1
USB_OC1_LAN
USB_Power
2
3
4
5
6
7
8
USB_P1N_LAN
USB_P1P_LAN
GND
DATAL1 (Differential data line paired with DATAH1)
DATAH1 (Differential data line paired with DATAL1)
Ground
USB_OC0_LAN
USB_P0N_LAN
USB_P0P_LAN
GND
USB_Power
DATAH0 (Differential data line paired with DATAL0)
DATAH0 (Differential data line paired with DATAL0)
Ground
One 2x5 connector on the server board (J3K1) provides an option to support an additional USB
2.0 port.
Table 22. Internal USB Connector Pin-out (J3K1)
Pin
Signal Name
P5V
Description
USB Power
1
2
3
4
5
6
7
8
9
P5V
USB Power
USB_ESB_P5N
USB_ESB_P4N
USB_ESB_P5P
USB_ESB_P4P
Ground
USB Port 5 Negative Signal
USB Port 4 Negative Signal
USB Port 5 Positive Signal
USB Port 4 Positive Signal
Ground
Ground
Ground
--
No Pin
10
NC
No Conncet
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Connector / Header Locations and Pin-outs
Intel® Server Board S5000VCL TPS
5.6 Fan Headers
The server board incorporates a system fan circuit that supports two SSI compliant 4-pin fan
connectors and one 3-pin connector. The 3-pin connector (J1K1) is for system cooling fans. The
two 4-pin fan connectors are for processor cooling fans: CPU1 fan (J2K3) and CPU2 fan (J2K4).
The 4-pin connectors can support CPU fans that draw a maximum of 1.2 amps each. The
system fan connectors can be found towards the front edge of the server board, CPU1 fan
(J2K3), CPU2 fan (J2K4) and system fan (J1K1). These connectors support a maximum fan
load of 3.5 Amps each. With the proper sensor data record (SDR) installed, Intel® System
Management Software can monitor all system fans in use.
The pin configuration for each fan connector is identical.
Table 23. CPU Fan Connector Pin-out (J2K3, J2K4)
Pin
Signal Name
Ground
Type
GND
Description
GROUND is the power supply ground
1
2
3
4
12V
Power
Out
In
Power supply 12V
Fan Tach
Fan PWM
FAN_TACH signal is connected to the BMC to monitor the fan speed
FAN_PWM signal to control fan speed
Table 24. PCI Fan Connector Pin-out (J1K1)
Pin
Signal Name
Ground
Type
GND
Description
GROUND is the power supply ground
1
2
3
12V
Power
Out
Power supply 12V
Fan Tach
FAN_TACH signal is connected to the BMC to monitor the fan speed
Note: Intel Corporation server baseboards support peripheral components and contain a
number of high-density VLSI and power delivery components that need adequate airflow to cool.
Intel’s own chassis are designed and tested to meet the intended thermal requirements of these
components when the fully integrated system is used together. It is the responsibility of the
system integrator that chooses not to use Intel developed server building blocks to consult
vendor datasheets and operating parameters to determine the amount of air flow required for
their specific application and environmental conditions. Intel Corporation can not be held
responsible if components fail or the server board does not operate correctly when used outside
any of their published operating or non-operating limits.
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Revision 2.3
Intel® Server Board S5000VCL TPS
Jumper Block Settings
6. Jumper Block Settings
The server board has several 3-pin jumper blocks that can be used to configure, protect, or
recover specific features of the server board. Pin 1 on each jumper block is denoted by “▼”.
6.1 Recovery Jumper Blocks
Table 25. Recovery Jumpers (J3A1, J1C1, J1C2)
Jumper Name
J3A1: BMC Force
Update
Pins
1-2
What happens at system reset…
BMC Firmware Force Update Mode – Disabled (Default)
2-3
1-2
2-3
BMC Firmware Force Update Mode – Enabled
J1C4: Password
Clear
These pins should have a jumper in place for normal system operation. (Default)
If these pins are jumpered, administrator and user passwords will be cleared on the next
reset. These pins should not be jumpered for normal operation.
J1C2: CMOS
Clear
These pins should have a jumper in place for normal system operation. (Default)
1-2
2-3
If these pins are jumpered, the CMOS settings will be cleared on the next reset. These
pins should not be jumpered for normal operation
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Jumper Block Settings
Intel® Server Board S5000VCL TPS
Force Update
J3A1
3
3
1-2: Disabled
2-3: Enabled
CMOS CLR
J1C2
1-2: Normal
Operation (Default)
3
3
2-3: CLEAR CMOS
PASSWORD CLR
J1C4
1-2: Normal
Operation (Default)
3
3
2-3: CLEAR
PASSWORD
AF001016
Figure 8. Recovery Jumper Blocks (J3A1, J1C2, J1C4)
6.1.1
CMOS Clear and Password Reset Usage Procedure
The CMOS Clear and Password Reset recovery features are designed for minimal system down
time. The usage procedure for these two features has changed from previous generation Intel
server boards. The following procedure outlines the new usage model.
1. Power down and remove AC power.
2. Open server.
3. Move jumper from the Default operating position (Pins1-2) to the Reset/Clear position
(Pins 2-3).
4. Wait 5 seconds.
5. Move jumper back to default position (Pins 1-2).
6. Close the server chassis.
7. Reconnect AC and power up the server.
The password and/or CMOS is cleared and can be reset in BIOS setup.
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Revision 2.3
Intel® Server Board S5000VCL TPS
Jumper Block Settings
6.1.2
BMC Force Update Procedure
When performing a standard BMC firmware update procedure, the update utility places the
BMC into an update mode, allowing the firmware to load safely onto the flash device. In the
unlikely event that the BMC firmware update process fails due to the BMC not being in the
proper update state, the server board provides a BMC Force Update jumper which will force the
BMC into the proper update state. The following procedure should be following in the event the
standard BMC firmware update process fails.
1. Power down and remove AC power.
2. Open the server.
3. Move jumper from the Default operating position (pins1-2) to the Enabled position (pins
2-3).
4. Close the server chassis.
5. Reconnect AC and power up the server.
6. Perform the BMC firmware update procedure that is documented in README.TXT file
that is included in the given BMC Firmware Update package.
7. After successful completion of the firmware update process, the firmware update utility
may generate an error stating that the BMC is still in update mode.
8. Power down and remove the AC power.
9. Open the server.
10. Move the jumper from the Enabled position (pins 2-3) to the Disabled position (pins 1-2).
11. Close the server chassis.
12. Reconnect AC and power up the server.
Note: Normal BMC functionality is disabled with the Force BMC Update jumper set to the
“Enabled” position. The server should never be run with the BMC Force Update jumper set in
this position and should only be used when the standard firmware update process fails. This
jumper should remain in the Default – Disabled position when the server is running normally.
6.2 BIOS Select Jumper
The jumper block located at J3A2, is used to select which BIOS image the system will boot to.
Pin 1 on the jumper is identified by ‘▼’. This jumper should only be moved to force the BIOS to
boot to the secondary bank, which may hold a different version of BIOS.
The rolling BIOS feature of the server board will automatically alternate the Boot BIOS to the
secondary bank if the BIOS image in the primary bank is corrupted and cannot boot.
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Jumper Block Settings
Intel® Server Board S5000VCL TPS
Table 26. BIOS Select Jumper (J3A2)
Pins
What happens at system reset…
1-2
Force BIOS to bank 2
2-3
System is configured for normal operation (bank 1) (Default)
6.3 PCIe Select Jumper
The jumper block located at J1E1 is used to select which PCI Express* speed to use. Pin 1 on
the jumper is identified by ‘▼’. This jumper will need to be moved to support the PCI Express
speed.
Table 27. PCI Express* x4/x8 Select Jumper (J1E1)
Pins
1-2
2-3
Description
PCI Express* two x4
PCI Express one x8 (Default)
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Intel® Server Board S5000VCL TPS
Intel® Light Guided Diagnostics
7. Intel® Light Guided Diagnostics
The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level
issues. This section shows the location of each LED and provides a high level-usage
description. For a more detailed description of what drives the diagnostic LED operation, see
the Intel® 5000 Series Chipsets Server Board Family Datasheet.
7.1 5-Volt Standby System Status / Fault LED
Several system management features of this server board require that 5-volt standby voltage be
supplied from the power supply. The BMC within the 6321ESB, and onboard NICs require this
voltage be present when the system is off. The 5-volt Standby System Status LED is illuminated
when AC power is applied to the platform and 5-volt standby voltage is supplied to the server
board by the power supply. See the figure below to locate this LED.
System Status /
Fault LED
AF001642
Figure 9. System Status / Fault LED Location
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Intel® Light Guided Diagnostics
Intel® Server Board S5000VCL TPS
When the AC power is first applied to the system and 5-volt standby is present, the BMC on the
server board requires 15-20 seconds to initialize. During this time, the system status LED blinks
amber and green, and the power button functionality is disabled, preventing the server from
powering up. Once BMC initialization has completed, the status LED will stop blinking and the
power button functionality is restored and can be used to turn on the server.
The bi-color 5V Standby System Status LED operates as follows:
Color
Off
Green / Alternating
State
Criticality
Not ready
Description
N/A
AC power off
Not ready
Pre-DC power on – 15-20 second BMC initialization when AC is
applied to the server. Control Panel buttons are disabled until the
BMC initialization is complete.
Amber
Blink
Green
Green
Solid on
Blink
System OK
Degraded
System booted and ready.
System degraded
Unable to use all of the installed memory (more than one DIMM
installed).
Correctable errors over a threshold of 10 and migrating to a
spare DIMM (memory sparing). This indicates that the user no
longer has spared DIMMs indicating a redundancy lost
condition. Corresponding DIMM LED should light up.
In mirrored configuration, when memory mirroring takes place
and system loses memory redundancy. This is not covered by
the bullet above.
Redundancy loss such as power-supply or fan. This does not
apply to non-redundant sub-systems.
PCI-e link errors
CPU failure / disabled – if there are two processors and one of
them fails
Fan alarm – Fan failure. Number of operational fans should be
more than minimum number needed to cool the system
Non-critical threshold crossed – Temperature and voltage
Amber
Amber
Blink
Non-critical
Non-fatal alarm – system is likely to fail
Critical voltage threshold crossed
VRD hot asserted
Minimum number of fans to cool the system not present or failed
In non-sparing and non-mirroring mode if the threshold of ten
correctable errors is crossed within the window
Solid on
Critical, non-
recoverable
Fatal alarm – system has failed or shutdown
DIMM failure when there is one DIMM present, no good memory
present
Run-time memory uncorrectable error in non-redundant mode
IERR signal asserted
Processor 1 missing
Temperature (CPU ThermTrip, memory TempHi, critical
threshold crossed)
No power good – power fault
Processor configuration error (for instance, processor stepping
mismatch)
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Intel® Server Board S5000VCL TPS
Intel® Light Guided Diagnostics
7.2 DIMM LEDs
The server board provides a memory fault LED for each DIMM slot. The DIMM fault LED is
illuminated when the system BIOS disables the specified DIMM after it reaches a specified
number of given failures or if specific critical DIMM failures are detected. See the Intel® 5000
Series Chipsets Server Board Family Datasheet.
A
AF001525
Figure 10. DIMM LED Locations
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Intel® Light Guided Diagnostics
Intel® Server Board S5000VCL TPS
7.3 Post Code Diagnostic LEDs
During the system boot process, BIOS executes a number of platform configuration processes,
each of which is assigned a specific hex POST code number. As each configuration routine is
started, BIOS will display the given POST code to the POST Code Diagnostic LEDs found on
the back edge of the server board. To assist in troubleshooting a system hang during the POST
process, the Diagnostic LEDs can be used to identify the last POST process to be executed.
See Appendix C for a complete description of how these LEDs are read, and for a list of all
supported POST codes.
TP02312
Figure 11. POST Code Diagnostic LED Location
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Power and Environmental Specifications
8. Power and Environmental Specifications
8.1 Intel® Server Board S5000VCL Design Specifications
Operating the server board at conditions beyond those shown in the table may cause
permanent damage to the system. Exposure to absolute maximum rating conditions for
extended periods may affect system reliability.
Table 28. Server Board Design Specifications
Operating Temperature
Non-Operating Temperature
DC Voltage
0º C to 55º C 1 (32º F to 131º F)
-40º C to 70º C (-40º F to 158º F)
± 5% of all nominal voltages
Shock (Unpackaged)
Shock (Packaged)
Trapezoidal, 50 g, 170 inches/sec
< 20 lbs
≥ 20 to < 40
≥ 40 to < 80
≥ 80 to < 100
≥100 to < 120
≥120
36 inches
30 inches
24 inches
18 inches
12 inches
9 inches
Vibration (Unpackaged)
Operating Temperature
Non-Operating Temperature
DC Voltage
5 Hz to 500 Hz 3.13 g RMS random
5º C to 50º C 1 (32º F to 131º F)
-40º C to 70º C (-40º F to 158º F)
± 5% of all nominal voltages
Trapezoidal, 50 g, 170 inches/sec
24 inches
Shock (Unpackaged)
Shock (Packaged) (≥ 40 lbs to < 80 lbs)
Vibration (Unpackaged)
5 Hz to 500 Hz 3.13 g RMS random
Note:
1 The chassis design must provide proper airflow to avoid exceeding the Dual-Core Intel® Xeon® processor
5100 series or Quad-Core Intel® Xeon® processor 5300 series maximum case temperature.
Disclaimer Note: Intel Corporation server boards support add-in peripherals and contain a
number of high-density VLSI and power delivery components that need adequate airflow to cool.
Intel ensures through its own chassis development and testing that when Intel server building
blocks are used together, the fully integrated system will meet the intended thermal
requirements of these components. It is the responsibility of the system integrator who chooses
not to use Intel developed server building blocks to consult vendor datasheets and operating
parameters to determine the amount of air flow required for their specific application and
environmental conditions. Intel Corporation cannot be held responsible, if components fail or the
server board does not operate correctly when used outside any of their published operating or
non-operating limits.
Revision 2.3
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Power and Environmental Specifications
Intel® Server Board S5000VCL TPS
8.2 Baseboard Power Requirements
This section provides power supply design guidelines for a system using the Intel® Server Board
S5000VCL, including voltage and current specifications and power supply on/off sequencing
characteristics.
8.2.1
Processor Power Support
The server board supports the Thermal Design Point (TDP) guideline for Dual-Core Intel® Xeon®
processors 5100 series and Quad-Core Intel® Xeon® processor 5300 series. The Flexible
Motherboard Guidelines (FMB) has also been followed to help determine the suggested thermal
and current design values for anticipating future processor needs. The following table provides
maximum values for Icc, TDP power and T
for the Dual-Core Intel® Xeon® processor 5100
CASE
series family and Quad-Core Intel® Xeon® processor 5300 series family.
Table 29. Dual-Core Intel® Xeon® processor 5100 series and Quad-Core Intel® Xeon® processor
5300 series TDP Guidelines
TDP Power
Max TCASE
Icc MAX
108 W
70º C
90 A
Note: These values are for reference only. The Dual-Core Intel® Xeon® processor 5100 series
and Quad-Core Intel® Xeon® processor 5300 series Datasheet contains the actual specifications
for the processor. If the values found in the Dual-Core Intel® Xeon® processor 5100 series
Datasheet are different than those published here, the Dual-Core Intel® Xeon® processor 5100
series Datasheet values will supersede these, and should be used.
8.2.2
Power Supply Output Requirements
This section is for reference purposes only. Its intent is to provide guidance to system designers
for determining a proper power supply for use with this server board. The contents of this
section specify the power supply requirements Intel used to develop a power supply for its 1U
server system.
The following table defines power and current ratings for this 400 W power supplies. The
combined output power of all outputs shall not exceed the rated output power. The power
supply must meet both static and dynamic voltage regulation requirements for the minimum
loading conditions.
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Intel® Server Board S5000VCL TPS
Power and Environmental Specifications
Table 30. 400W Load Ratings
Voltage Minimum Continuous Maximum Continuous Peak
+3.3 V 1
+5 V 1
+12 V 2
+12 V 3
+12 V 4
+12 V 5
-12 V
1.5 A
1.0 A
0.5 A
0.5 A
0.5 A
0.5 A
0 A
10 A
20 A
16 A
16 A
16 A
16 A
0.5 A
3.0 A
18 A
18 A
+5 VSB
0.1 A
3.5 A
Notes:
1. Combined 3.3 V and 5 V power shall not exceed 100 W.
2. Maximum continuous total DC output power should not exceed 400 W.
3. Peak load on the combined 12 V output shall not exceed 49 A.
4. Maximum continuous load on the combined 12 V output shall not exceed 44 A.
5. Peak total DC output power should not exceed 650 W.
6. Peak power and current loading shall be supported for a minimum of 12 seconds.
8.2.3 Turn On No Load Operation
At power on the system shall present a no load condition to the power supply. In this no load
state the voltage regulation limits for the 3.3V and 5V are relaxed to +/-10% and the +12V rails
relaxed to +10/-8%. When operating loads are applied the voltages must regulated to there
normal limits.
Table 31. No-load Operating Range
Voltage Minimum Continuous Maximum Continuous Peak
+3.3 V
0 A
0 A
0 A
0 A
0 A
0 A
0 A
0.1 A
7 A
+5 V
5 A
+12 V 1
+12 V 2
+12 V 3
+12 V 4
-12 V
5 A
7 A
7 A
5 A
6 A
5 A
0.5 A
3.0 A
+5 VSB
3.5 A
Notes:
1. Maximum continuous total DC output power should not exceed 400 W.
2. Peak load on the combined 12 V output shall not exceed 49 A.
3. Maximum continuous load on the combined 12 V output shall not exceed 44 A.
4. Peak total DC output power should not exceed 650 W.
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Power and Environmental Specifications
Intel® Server Board S5000VCL TPS
8.2.4
Grounding
The grounds of the pins of the power supply output connector provide the power return path.
The output connector ground pins shall be connected to safety ground (power supply enclosure).
This grounding should be well designed to ensure passing the maximum allowed
common mode noise levels.
The power supply shall be provided with a reliable protective earth ground. All secondary
circuits shall be connected to protective earth ground. Resistance of the ground returns to
chassis shall not exceed 1.0 mΩ. This path may be used to carry DC current.
8.2.5
Standby Outputs
The 5 VSB output shall be present when an AC input greater than the power supply turn on
voltage is applied.
8.2.6
Remote Sense
The power supply has remote sense return (ReturnS) to regulate out ground drops for all output
voltages: +3.3 V, +5 V, +12 V1, +12 V2, +12 V3, -12 V, and 5 VSB. The power supply uses
remote sense (3.3 VS) to regulate out drops in the system for the +3.3 V output. The +5 V, +12
V1, +12 V2, +12 V3, –12 V and 5 VSB outputs only use remote sense referenced to the
ReturnS signal.
The remote sense input impedance to the power supply must be greater than 200 Ω on 3.3 VS
and 5 VS; this is the value of the resistor connecting the remote sense to the output voltage
internal to the power supply. Remote sense must be able to regulate out a minimum of a
200 mV drop on the +3.3 V output.
The remote sense return (ReturnS) must be able to regulate out a minimum of a 200 mV drop in
the power ground return. The current in any remote sense line shall be less than 5 mA to
prevent voltage sensing errors. The power supply must operate within specification over the full
range of voltage drops from the power supply’s output connector to the remote sense points.
8.2.7
Voltage Regulation
The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
Table 32. Voltage Regulation Limits
Parameter
Tolerance
Minimum
Nominal
Maximum
Units
+ 3.3V
- 5% / +5%
+3.14
+3.30
+3.46
Vrms
+ 5V
+ 12V
- 12V
- 5% / +5%
- 5% / +5%
- 5% / +9%
- 5% / +5%
+4.75
+11.40
-11.40
+4.75
+5.00
+12.00
-12.00
+5.00
+5.25
+12.60
-13.08
+5.25
Vrms
Vrms
Vrms
Vrms
+ 5VSB
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Intel® Server Board S5000VCL TPS
Power and Environmental Specifications
8.2.8
Dynamic Loading
The output voltages shall remain within limits for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50 Hz
and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere within the MIN load to the MAX load
conditions.
Table 33. Transient Load Requirements
Output
Load Slew Rate
Test Capacitive Load
Δ Step Load Size
(See note 2)
6.0 A
+3.3 V
+5 V
0.25 A/μsec
0.25 A/μsec
0.25 A/μsec
0.25 A/μsec
250 μF
400 μF
2200 μF 1, 2
4.0 A
18.0 A
0.5 A
12 V
+5 VSB
20 μF
Notes:
1. Step loads on each 12 V output may happen simultaneously.
2. The +12 V should be tested with 2200 μF evenly split between the four +12 V rails.
8.2.9
Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive
loading ranges.
Table 34. Capacitive Loading Conditions
Output
Minimum
Maximum
Units
+3.3 V
250
6,800
μF
+5 V
+12 V
-12 V
400
4,700
11,000
350
μF
μF
μF
μF
500 each
1
+5 VSB
20
350
8.2.10
Closed-Loop Stability
The power supply shall be unconditionally stable under all line/load/transient load conditions
including capacitive load ranges. A minimum of: 45 degrees phase margin and -10 dB gain
margin is required. The power supply manufacturer shall provide proof of the unit’s closed-loop
stability with local sensing through the submission of bode plots. Closed-loop stability must be
ensured at the maximum and minimum loads as applicable.
8.2.11
Common Mode Noise
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency
band of 10 Hz to 30 MHz.
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Power and Environmental Specifications
Intel® Server Board S5000VCL TPS
•
The measurement shall be made across a 100 Ω resistor between each of the DC
outputs, including ground, at the DC power connector and chassis ground (power
subsystem enclosure).
•
The test set-up shall use an FET probe such as Tektronix* model P6046 or equivalent.
8.2.12
Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A
10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor are placed at the point of
measurement.
Table 35. Ripple and Noise
+3.3 V
50mVp-p
+5 V
50mVp-p
+12 V
120mVp-p
-12 V
120mVp-p
+5 VSB
50mVp-p
8.2.13
Soft Starting
The power supply shall contain a control circuit which provides a monotonic soft start for its
outputs without overstress of the AC line or any power supply components at any specified AC
line or load conditions. There is no requirement for rise time on the 5 V standby, but the turn
on/off shall be monotonic.
8.2.14
Timing Requirements
These are the timing requirements for the power supply operation. The output voltages must
rise from 10% to within regulation limits (Tvout_rise) within 5 to 70 ms, except for 5VSB; it is
allowed to rise from 1.0 to 25 ms. All outputs must rise monotonically. Each output voltage
shall reach regulation within 50 ms (Tvout_on) of each other during turn on of the power supply.
Each output voltage shall fall out of regulation within 400 msec (Tvout_off) of each other during
turn off. The following diagrams show the timing requirements for the power supply being turned
on and off via the AC input with PSOn held low, and the PSOn signal with the AC input applied.
Table 36. Output Voltage Timing
Item
Tvout_rise
Tvout_on
Description
Output voltage rise time from each main output.
All main outputs must be within regulation of each other
within this time.
Minimum
5.0 *
Maximum
70 *
50
Units
msec
msec
T vout_off
All main outputs must leave regulation within this time.
400
msec
*The 5 VSB output voltage rise time shall be from 1.0 ms to 25.0 ms
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Intel® Server Board S5000VCL TPS
Power and Environmental Specifications
V out
10% V out
V1
V2
V3
V4
T
vout_off
T
T
vout_rise
vout_on
AF001023
Figure 12. Output Voltage Timing
Table 37. Turn On/Off Timing
Item
Tsb_on_delay
Description
Minimum
Maximum
1500
Units
msec
Delay from AC being applied to 5VSB being within regulation.
T ac_on_delay
Tvout_holdup
Tpwok_holdup
Tpson_on_delay
Delay from AC being applied to all output voltages being
within regulation.
msec
msec
msec
msec
2500
Time all output voltages stay within regulation after loss of
AC. Measured at 75% of maximum load.
21
20
5
Delay from loss of AC to de-assertion of PWOK. Measured at
75% of maximum load.
Delay from PSOn# active to output voltages within regulation
limits.
Delay from PSOn# deactive to PWOK being de-asserted.
400
50
T pson_pwok
Tpwok_on
msec
msec
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
100
1
500
T pwok_off
Tpwok_low
Tsb_vout
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
msec
msec
msec
msec
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSOn signal.
100
50
70
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
1000
T5VSB_holdup
Time the 5VSB output voltage stays within regulation after
loss of AC.
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Power and Environmental Specifications
Intel® Server Board S5000VCL TPS
AC Input
T
vout_holdup
V out
T
pwok_low
T
AC_on_delay
T
T
sb_on_delay
T
T
T
T
pwok_on
pwok_off
pson_pwok
pwok_on
pwok_off
sb_on_delay
T
PWOK
5 VSB
PSON
T
pwok_holdup
T
5VSB_holdup
T
sb_vout
T
pson_on_delay
AC turn on/off cycle
PSON turn on/off cycle
AF001024
Figure 13. Turn On/Off Timing (Power Supply Signals)
8.2.15
Residual Voltage Immunity in Standby Mode
The power supply shall be immune to any residual voltage placed on its outputs (typically a
leakage voltage through the system from standby output) up to 500 mV. There shall be no
additional heat generated, nor stress of any internal components with this voltage applied to any
individual output, and all outputs simultaneously. It also should not trip the power supply
protection circuits during turn on.
Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV
when AC voltage is applied and the PSOn# signal is de-asserted.
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Regulatory and Certification Information
9. Regulatory and Certification Information
WARNING
To ensure regulatory compliance, you must adhere to the assembly instructions in this guide to
ensure and maintain compliance with existing product certifications and approvals. Use only the
described, regulated components specified in this guide. Use of other products / components
will void the UL listing and other regulatory approvals of the product and will most likely result in
noncompliance with product regulations in the region(s) in which the product is sold.
To help ensure EMC compliance with your local regional rules and regulations, before computer
integration, make sure that the chassis, power supply, and other modules have passed EMC
testing using a server board with a microprocessor from the same family (or higher) and
operating at the same (or higher) speed as the microprocessor used on this server board. The
final configuration of your end system product may require additional EMC compliance testing.
For more information please contact your local Intel Representative.
This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class
B device.
9.1 Product Regulatory Compliance
Intended Application – This product was evaluated as Information Technology Equipment
(ITE), which may be installed in offices, schools, computer rooms, and similar commercial type
locations. The suitability of this product for other product categories and environments (such as:
medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.),
other than an ITE application, may require further evaluation. This is an FCC Class A device.
Integration of it into a Class B chassis does not result in a Class B device.
9.1.1
Product Safety Compliance
UL60950 – CSA 60950 (USA / Canada)
•
•
•
•
•
•
•
•
EN60950 (Europe)
IEC60950 (International)
CB Certificate & Report, IEC60950 (report to include all country national deviations)
GOST R 50377-92 – Listed on one System License (Russia)
Belarus License – Listed on System License (Belarus)
CE - Low Voltage Directive 73/23/EEE (Europe)
IRAM Certification (Argentina)
Revision 2.3
Intel order number: D64569-007
45
Regulatory and Certification Information
Intel® Server Board S5000VCL TPS
9.1.2
Product EMC Compliance – Class A Compliance
•
FCC /ICES-003 - Emissions (USA/Canada) Verification
CISPR 22 – Emissions (International)
EN55022 - Emissions (Europe)
•
•
•
•
•
•
•
•
•
•
•
EN55024 - Immunity (Europe)
CE – EMC Directive 89/336/EEC (Europe)
VCCI Emissions (Japan)
AS/NZS 3548 Emissions (Australia / New Zealand)
BSMI CNS13438 Emissions (Taiwan)
GOST R 29216-91 Emissions - Listed on one System License (Russia)
GOST R 50628-95 Immunity –Listed on one System License (Russia)
Belarus License – Listed on one System License (Belarus)
RRL MIC Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea)
9.1.3
Certifications / Registrations / Declarations
UL Certification or NRTL (US/Canada)
•
•
•
•
•
•
•
•
•
•
CE Declaration of Conformity (CENELEC Europe)
FCC/ICES-003 Class A Attestation (USA/Canada)
C-Tick Declaration of Conformity (Australia)
MED Declaration of Conformity (New Zealand)
BSMI Certification (Taiwan)
GOST – Listed on one System License (Russia)
Belarus – Listed on one System License (Belarus)
RRL Certification (Korea)
Ecology Declaration (International)
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Regulatory and Certification Information
9.2 Product Regulatory Compliance Markings
The server board is provided with the following regulatory marks.
Regulatory Compliance
UL Mark
Region
USA/Canada
Marking
CE Mark
Europe
EMC Marking (Class A)
BSMI Marking (Class A)
Canada
Taiwan
CANADA ICES-003 CLASS A
CANADA NMB-003 CLASSE A
C-tick Marking
RRL MIC Mark
Australia / New Zealand
Korea
Country of Origin
Model Designation
Exporting Requirements
Regulatory Identification
MADE IN xxxxx (Provided by label, not silk
screen)
Examples (Intel® Server Board S5000VCL) for
boxed type boards; or Board PB number for non-
boxed boards (typically high-end boards)
Revision 2.3
Intel order number: D64569-007
47
Regulatory and Certification Information
Intel® Server Board S5000VCL TPS
9.3 Electromagnetic Compatibility Notices
9.3.1
FCC Verification Statement (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to two conditions: (1)
This device may not cause harmful interference, and (2) this device must accept any
interference received, including interference that may cause undesired operation.
Intel Corporation
5200 N.E. Elam Young Parkway
Hillsboro, OR 97124-6497
Phone: 1-800-628-8686
This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is no
guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning
the equipment off and on, the user is encouraged to try to correct the interference by one or
more of these measures:
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and the receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver
is connected.
•
Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the grantee of this device could void
the user’s authority to operate the equipment. The customer is responsible for ensuring
compliance of the modified product.
All cables used to connect to peripherals must be shielded and grounded. Operation with cables,
connected to peripherals that are not shielded and grounded may result in interference to radio
and TV reception.
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Regulatory and Certification Information
9.3.2
ICES-003 (Canada)
Cet appareil numérique respecte les limites bruits radioélectriques applicables aux
appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur:
“Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications.
English translation of the notice above:
This digital apparatus does not exceed the Class B limits for radio noise emissions from digital
apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,”
ICES-003 of the Canadian Department of Communications.
9.3.3
Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive
(73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark
to illustrate its compliance.
9.3.4
VCCI (Japan)
English translation of the notice above:
This is a Class B product based on the standard of the Voluntary Control Council for
Interference (VCCI) from Information Technology Equipment. If this is used near a radio or
television receiver in a domestic environment, it may cause radio interference. Install and use
the equipment according to the instruction manual.
Revision 2.3
Intel order number: D64569-007
49
Regulatory and Certification Information
Intel® Server Board S5000VCL TPS
9.3.5
BSMI (Taiwan)
The BSMI Certification Marking and EMC warning is located on the outside rear area of the
product.
9.3.6
RRL (Korea)
Following is the RRL certification information for Korea.
English translation of the notice above:
1. Type of Equipment (Model Name): On License and Product
2. Certification No.: On RRL certificate. Obtain certificate from local Intel representative
3. Name of Certification Recipient: Intel Corporation
4. Date of Manufacturer: Refer to date code on product
5. Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product
9.3.7
CNCA (CCC-China)
The CCC Certification Marking and EMC warning is located on the outside rear area of
the product.
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Regulatory and Certification Information
9.4 Restriction of Hazardous Substances (RoHS)
Compliance
Intel has a system in place to restrict the use of banned substances in accordance with the
European Directive 2002/95/EC. Compliance is based on declaration that materials banned in
the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an
approved/pending RoHS exemption applies.
Note: RoHS implementing details are not fully defined and may change.
Threshold limits and banned substances are noted below.
•
•
Quantity limit of 0.1% by mass (1000 PPM) for:
-
-
-
-
Lead
Mercury
Hexavalent Chromium
Polybrominated Biphenyls Diphenyl Ethers (PBDE)
Quantity limit of 0.01% by mass (100 PPM) for:
Cadmium
-
Revision 2.3
Intel order number: D64569-007
51
Appendix A: Integration and Usage Tips
Intel® Server Board S5000VCL TPS
Appendix A: Integration and Usage Tips
•
•
When adding or removing components or peripherals from the server board, AC power
must be removed. With AC power plugged into the server board, 5-volt standby is still
present even though the server board is powered off.
When two processors are installed, both must be of identical revision, core voltage,
and bus/core speed. Mixed processor steppings is supported. However, the stepping
of one processor can not be greater then one stepping back of the other.
•
•
Processors must be installed in order. CPU 1 is located near the edge of the server
board and must be populated to operate the board.
Only fully buffered DIMMs (FBD) are supported on this server board. For a list of
supported memory for this server board, see the Intel® Server Board S5000VCL
Tested Memory List.
•
•
For a list of Intel supported operating systems, add-in cards, and peripherals for this
server board, see the Intel® Server Board S5000VCL Tested Hardware and OS List.
Only Dual-Core Intel® Xeon® processors 5100 series or low- voltage Quad-Core Intel®
Xeon® processor 5300 series, with system bus speeds of 1066, or 1333 MHz are
supported on this server board. Previous generation Intel® Xeon® processors are not
supported.
−
For a complete list of supported processors, see the following link:
http://support.intel.com/support/motherboards/server/S5000VCL
•
•
•
Removing AC power before performing the CMOS clear operation will cause the
system to automatically power up and immediately power down after the procedure is
followed and AC power is re-applied. If this happens remove the AC power cord again,
wait 30 seconds, and then reconnect the AC power cord. Power up the system and
proceed to the <F2> BIOS setup utility to reset desired settings.
Normal BMC functionality is disabled with the force BMC update jumper set to the
“enabled” position (pins 2-3). The server should never be run with the BMC force
update jumper set in this position and should only be used when the standard firmware
update process fails. This jumper should remain in the default (disabled) position (pins
1-2) when the server is running normally.
When performing a BIOS update, the BIOS select jumper must be set to its default
position (pins 2-3).
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Appendix B: Sensor Tables
Appendix B: Sensor Tables
This appendix lists the sensor identification numbers and information regarding the sensor type,
name, supported thresholds, assertion and de-assertion information, and a brief description of
the sensor purpose. See the Intelligent Platform Management Interface Specification, Version
1.5, for sensor and event/reading-type table information.
•
•
•
Sensor Type
The Sensor Type references the values enumerated in the Sensor Type Codes table in
the IPMI specification. It provides the context in which to interpret the sensor, e.g., the
physical entity or characteristic that is represented by this sensor.
Event / Reading Type
The Event/Reading Type references values from the Event/Reading Type Code Ranges
and Generic Event/Reading Type Codes tables in the IPMI specification. Note that digital
sensors are a specific type of discrete sensors, which have only two states.
Event Offset/Triggers
Event Thresholds are ‘supported event generating thresholds’ for threshold types of
sensors.
-
[u,l][nr,c,nc] upper nonrecoverable, upper critical, upper noncritical, lower
nonrecoverable, lower critical, lower noncritical
-
uc, lc upper critical, lower critical
Event Triggers are ‘supported event generating offsets’ for discrete type sensors.
The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type
Codes tables in the IPMI specification, depending on whether the sensor
event/reading type is generic or a sensor specific response.
•
•
Assertion / De-assertion Enables
Assertion and de-assertion indicators reveal the type of events the sensor can generate:
-
-
As: Assertions
De: De-assertion
Readable Value / Offsets
-
Readable Value indicates the type of value returned for threshold and other non-
discrete type sensors.
-
Readable Offsets indicate the offsets for discrete sensors that are readable via the
Get Sensor Reading command. Unless otherwise indicated, all event triggers are
readable, i.e., Readable Offsets consists of the reading type offsets that do not
generate events.
Revision 2.3
Intel order number: D64569-007
53
Appendix B: Sensor Tables
Intel® Server Board S5000VCL TPS
•
Event Data
This is the data that is included in an event message generated by the associated
sensor. For threshold-based sensors, these abbreviations are used:
-
-
R: Reading value
T: Threshold value
•
Rearm Sensors
-
The rearm is a request for the event status for a sensor to be rechecked and
updated upon a transition between good and bad states. Rearming the sensors can
be done manually or automatically. This column indicates the type supported by the
sensor. The following abbreviations are used in the comment column to describe a
sensor:
A: Auto-rearm
M: Manual rearm
•
Default Hysteresis
-
Hysteresis setting applies to all thresholds of the sensor. This column provides the
count of hysterisis for the sensor, which can be 1 or 2 (positive or negative
hysteresis).
•
•
Criticality
-
-
Criticality is a classification of the severity and nature of the condition. It also controls
the behavior of the Control Panel Status LED.
Standby
Some sensors operate on standby power. These sensors may be accessed and / or
generate events when the main (system) power is off, but AC power is present.
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Appendix C: POST Error Messages and Handling
Appendix C: POST Error Messages and Handling
Whenever possible, the BIOS will output the current boot progress codes on the video screen.
Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class,
subclass, and operation information. The class and subclass fields point to the type of hardware
that is being initialized. The operation field represents the specific initialization activity. Based on
the data bit availability to display progress codes, a progress code can be customized to fit the
data width. The higher the data bit, the higher the granularity of information that can be sent on
the progress port. The progress codes may be reported by the system BIOS or option ROMs.
The Response section in the table is divided into two types:
•
Pause: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and user input is required to continue. The user can take immediate corrective
action or choose to continue booting.
•
Halt: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and the system cannot boot unless the error is resolved. The user needs to replace
the faulty part and restart the system.
Table 38. POST Error Messages and Handling
Error Code
004C
Error Message
Response
Pause
Keyboard / interface error
CMOS date / time not set
Configuration cleared by jumper
Passwords cleared by jumper
Configuration default loaded
Password check failed
0012
5220
5221
5223
0048
0141
0146
8110
8111
8120
8121
8130
8131
8160
8161
8190
8198
0192
0194
0195
0197
8300
8306
Pause
Pause
Pause
Pause
Halt
PCI resource conflict
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Halt
Insufficient memory to shadow PCI ROM
Processor 01 internal error (IERR) on last boot
Processor 02 internal error (IERR) on last boot
Processor 01 thermal trip error on last boot
Processor 02 thermal trip error on last boot
Processor 01 disabled
Processor 02 disabled
Processor 01 unable to apply BIOS update
Processor 02 unable to apply BIOS update
Watchdog timer failed on last boot
Operating system boot watchdog timer expired on last boot
L3 cache size mismatch
CPUID, processor family are different
Front side bus mismatch
Halt
Pause
Pause
Pause
Pause
Processor speeds mismatched
Baseboard management controller failed self-test
Front panel controller locked
Revision 2.3
Intel order number: D64569-007
55
Appendix C: POST Error Messages and Handling
Intel® Server Board S5000VCL TPS
Error Code
8305
Error Message
Response
Pause
Hotswap controller failed
84F2
84F3
84F4
84FF
8500
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
852A
852B
852C
852D
852E
852F
8540
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
858A
858B
858C
858D
858E
858F
8600
Baseboard management controller failed to respond
Baseboard management controller in update mode
Sensor data record empty
Pause
Pause
Pause
Pause
System event log full
Memory Component could not be configured in the selected RAS mode.
DIMM_A1 failed Self Test (BIST).
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
DIMM_A2 failed Self Test (BIST).
DIMM_A3 failed Self Test (BIST).
DIMM_A4 failed Self Test (BIST).
DIMM_B1 failed Self Test (BIST).
DIMM_B2 failed Self Test (BIST).
DIMM_B3 failed Self Test (BIST).
DIMM_B4 failed Self Test (BIST).
DIMM_C1 failed Self Test (BIST).
DIMM_C2 failed Self Test (BIST).
DIMM_C3 failed Self Test (BIST).
DIMM_C4 failed Self Test (BIST).
DIMM_D1 failed Self Test (BIST).
DIMM_D2 failed Self Test (BIST).
DIMM_D3 failed Self Test (BIST).
DIMM_D4 failed Self Test (BIST).
Memory Component lost redundancy during the last boot.
DIMM_A1 Correctable ECC error encountered.
DIMM_A2 Correctable ECC error encountered.
DIMM_A3 Correctable ECC error encountered.
DIMM_A4 Correctable ECC error encountered.
DIMM_B1 Correctable ECC error encountered.
DIMM_B2 Correctable ECC error encountered.
DIMM_B3 Correctable ECC error encountered.
DIMM_B4 Correctable ECC error encountered.
DIMM_C1 Correctable ECC error encountered.
DIMM_C2 Correctable ECC error encountered.
DIMM_C3 Correctable ECC error encountered.
DIMM_C4 Correctable ECC error encountered.
DIMM_D1 Correctable ECC error encountered.
DIMM_D2 Correctable ECC error encountered.
DIMM_D3 Correctable ECC error encountered.
DIMM_D4 Correctable ECC error encountered.
Primary and secondary BIOS IDs do not match.
Override jumper is set to force boot from lower alternate BIOS bank of flash
ROM
8601
8602
8603
WatchDog timer expired (secondary BIOS may be bad!)
Secondary BIOS checksum fail
Pause
Pause
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Appendix C: POST Error Messages and Handling
POST Error Beep Codes
The following table lists POST error beep codes. Prior to system video initialization, the BIOS
uses these beep codes to inform users on error conditions. The beep code is followed by a user
visible code on POST Progress LEDs.
Table 39. POST Error Beep Codes
Beeps
3
Error Message
Memory error
POST Progress Code
Description
System halted because a fatal error related to the memory
was detected.
6
BIOS rolling back
error
The system has detected a corrupted BIOS in the flash
part, and is rolling back to the last good BIOS.
The BMC may generate beep codes upon detection of failure conditions. Beep codes are
sounded each time the problem is discovered, such as on each power-up attempt, but are not
sounded continuously. Codes that are common across all Intel® server boards and systems that
use the Intel® 5000 Series Chipsets are listed in Table 40. Each digit in the code is represented
by a sequence of beeps whose count is equal to the digit.
Table 40. BMC Beep Codes
Code
1-5-2-1
Reason for Beep
CPU: Empty slot / population error – Processor
slot 1 is not populated.
Associated Sensors
CPU Population Error
Supported?
Yes
1-5-2-2
1-5-2-3
1-5-2-4
1-5-4-2
CPU: No processors (terminators only)
N/A
N/A
No
No
No
Yes
CPU: Configuration error (e.g., VID mismatch)
CPU: Configuration error (e.g., BSEL mismatch) N/A
Power fault: DC power unexpectedly lost (power Power Unit – power unit
good dropout)
failure offset
1-5-4-3
1-5-4-4
Chipset control failure
Power control fault
N/A
No
Power Unit – soft power
control failure offset
Yes
Revision 2.3
Intel order number: D64569-007
57
Appendix D: POST Code Diagnostic LED Decoder
Intel® Server Board S5000VCL TPS
Appendix D: POST Code Diagnostic LED Decoder
During the system boot, the BIOS executes platform configuration processes, each of which is
assigned a specific hex POST code number. As each configuration routine is started, the BIOS
displays the POST code on the POST Code Diagnostic LEDs on the back edge of the server
board. The Diagnostic LEDs identify the last POST process to be executed.
Each POST code is represented by a combination of colors from the four LEDs. The LEDs are
capable of displaying three colors: green, red, and amber. The POST codes are divided into an
upper nibble and a lower nibble. Each bit in the upper nibble is represented by a red LED and
each bit in the lower nibble is represented by a green LED. If both bits are set in the upper and
lower nibbles then both the red and green LEDs are lit, resulting in an amber color. If both bits
are clear, then the LED is off.
Example: The BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are
decoded as:
•
•
red bits = 1010b = Ah
green bits = 1100b = Ch
Since the red bits correspond to the upper nibble and the green bits correspond to the lower
nibble, the two are concatenated as ACh.
Table 41. Example POST Progress Code LED
8h
4h
2h
1h
LEDs
ACh
Result
Red
Green
Red
Green
Red
Green
Red
Green
1
1
0
1
1
0
0
0
Amber
Green
Red
Off
MSB
LSB
Diagnostic LEDs
USB Port
USB Port
Back edge of baseboard
MSB
LSB
Figure 14. Diagnostic LED Placement Diagram
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Appendix D: POST Code Diagnostic LED Decoder
Table 42. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
Host Processor
OFF
LSB
0x10h
0x11h
0x12h
0x13h
Chipset
0x21h
Memory
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
0x28h
PCI Bus
0x50h
0x51h
0x52h
0x53h
0x54h
0x55h
0x56h
0x57h
USB
OFF
OFF
OFF
OFF
OFF
OFF
G
R
A
R
A
Power-on initialization of the host processor (bootstrap processor)
Host processor cache initialization (including AP)
Starting application processor initialization
SMM initialization
OFF
OFF
OFF
G
Off
Off
R
G
Initializing a chipset component
Off
Off
Off
Off
Off
Off
G
Off
Off
G
A
A
R
R
A
A
R
Off
G
Reading configuration data from memory (SPD on DIMM)
Detecting presence of memory
Off
G
Programming timing parameters in the memory controller
Configuring memory parameters in the memory controller
Optimizing memory controller settings
G
G
Off
G
G
Initializing memory, such as ECC init
Off
Off
Testing memory
Off
Off
Off
Off
Off
Off
Off
Off
R
R
R
R
A
A
A
A
Off
Off
G
R
A
R
A
R
A
R
A
Enumerating PCI busses
Allocating resources to PCI busses
Hot Plug PCI controller initialization
Reserved for PCI bus
G
Off
Off
G
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
G
Reserved for PCI bus
0x58h
0x59h
G
G
R
R
Off
Off
R
A
Resetting USB bus
Reserved for USB devices
ATA / ATAPI / SATA
0x5Ah
0x5Bh
G
G
R
R
G
G
R
A
Resetting PATA / SATA bus and all devices
Reserved for ATA
SMBUS
0x5Ch
G
G
A
A
Off
Off
R
A
Resetting SMBUS
0x5Dh
Reserved for SMBUS
Local Console
0x70h
Off
Off
Off
R
R
R
R
R
A
R
A
R
Resetting the video controller (VGA)
Disabling the video controller (VGA)
Enabling the video controller (VGA)
0x71h
0x72h
Remote Console
0x78h
0x79h
0x7Ah
G
R
R
R
R
R
A
R
A
R
Resetting the console controller
Disabling the console controller
Enabling the console controller
G
G
Revision 2.3
Intel order number: D64569-007
59
Appendix D: POST Code Diagnostic LED Decoder
Diagnostic LED Decoder
Intel® Server Board S5000VCL TPS
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
Keyboard (PS2 or USB)
LSB
0x90h
0x91h
0x92h
0x93h
0x94h
0x95h
R
R
R
R
R
R
Off
Off
Off
Off
G
Off
Off
G
R
A
R
A
R
A
Resetting the keyboard
Disabling the keyboard
Detecting the presence of the keyboard
Enabling the keyboard
G
Off
Off
Clearing keyboard input buffer
G
Instructing keyboard controller to run Self Test (PS2 only)
Mouse (PS2 or USB)
0x98h
0x99h
A
A
A
A
Off
Off
Off
Off
Off
Off
G
R
A
R
A
Resetting the mouse
Detecting the mouse
0x9Ah
Detecting the presence of mouse
Enabling the mouse
0x9Bh
G
Fixed Media
0xB0h
R
R
Off
Off
R
R
R
A
Resetting fixed media device
Disabling fixed media device
0xB1h
0xB2h
Detecting presence of a fixed media device (IDE hard drive detection,
etc.)
R
Off
Off
A
A
R
A
0xB3h
R
Enabling / configuring a fixed media device
Removable Media
0xB8h
0xB9h
0xBAh
A
A
Off
Off
R
R
R
A
Resetting removable media device
Disabling removable media device
Detecting presence of a removable media device (IDE CDROM
detection, etc.)
A
Off
G
A
R
R
R
0xBCh
A
Enabling / configuring a removable media device
Boot Device Selection
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0XDA
0xDB
0xDC
0xDE
0xDF
R
R
R
R
R
R
R
R
A
A
A
A
A
A
A
R
R
R
R
A
A
A
A
R
R
R
R
A
A
A
Off
Off
G
R
A
R
A
R
A
R
A
R
A
R
A
R
R
A
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
G
Off
Off
G
G
Off
Off
G
G
Off
G
G
Pre-EFI Initialization (PEI) Core
0xE0h
0xE2h
R
R
R
R
R
A
Off
Off
Started dispatching early initialization modules (PEIM)
Initial memory found, configured, and installed correctly
60
Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Diagnostic LED Decoder
Appendix D: POST Code Diagnostic LED Decoder
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
LSB
0xE1h
0xE3h
R
R
R
R
A
G
Reserved for initialization module use (PEIM)
Reserved for initialization module use (PEIM)
R
G
Driver Execution Environment (DXE) Core
0xE4h
0xE5h
R
R
R
A
A
A
R
R
A
Off
G
Entered EFI driver execution phase (DXE)
Started dispatching drivers
0xE6h
Off
Started connecting drivers
DXE Drivers
0xE7h
R
A
A
A
A
A
A
R
R
R
A
A
A
R
R
A
A
A
G
Off
G
Waiting for user input
0xE8h
Checking password
0xE9h
Entering BIOS setup
0xEAh
Off
Off
G
Flash Update
0xEEh
Calling Int 19. One beep unless silent boot is enabled.
Unrecoverable boot failure / S3 resume failure
0xEFh
Runtime Phase / EFI Operating System Boot
0xF4h
0xF5h
0xF8h
R
R
A
A
R
R
R
A
Entering Sleep state
Exiting Sleep state
Operating system has requested EFI to close boot services
(ExitBootServices ( ) has been called)
A
A
A
R
R
R
R
R
A
R
A
R
0xF9h
0xFAh
Operating system has switched to virtual address mode
(SetVirtualAddressMap ( ) has been called)
Operating system has requested the system to reset (ResetSystem ()
has been called)
Pre-EFI Initialization Module (PEIM) / Recovery
0x30h
0x31h
0x34h
0x35h
0x3Fh
Off
Off
Off
Off
G
Off
Off
G
R
R
R
R
A
R
A
R
A
A
Crisis recovery has been initiated because of a user request
Crisis recovery has been initiated by software (corrupt flash)
Loading crisis recovery capsule
G
Handing off control to the crisis recovery capsule
Unable to complete crisis recovery.
G
Revision 2.3
Intel order number: D64569-007
61
Appendix E: Supported Intel® Server Chassis
Intel® Server Board S5000VCL TPS
Appendix E: Supported Intel® Server Chassis
The Intel® Server Board S5000VCL/S5000VCLR (SATA) is supported in these Intel 1U high
density rack mount server systems: Intel® Server System SR1530CL/SR1530CLR and Intel®
Server System SR1530HCL/SR1530HCLR.
The Intel® Server Board S5000VCLSASBB/BBS5000VCLSASR (SAS) is supported in the Intel®
Server System SR1530HCLS/SR1530HCLSR.
See the Intel® Server Systems SR1535CL/SR1530HCL/SR1530HCLS and
SR1535CLR/SR1530HCLR/SR1530HCLSR Technical Product Specification for more
information.
E
D
C
B
A
F
G
H
I
A
AF001026
A
B
C
D
E
Rack handles
F
G
H
I
400 watt power supply
Processor air duct
Slimline drive bay (drive not included)
Power supply fans
Fan modules
Intel® Server Board S5000VCL
PCI add-in riser assembly
Hard drive bays (drives not included)
Figure 15. Intel® Server System SR1530CL/SR1530CLR
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Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Appendix E: Supported Intel® Server Chassis
F
E
D
C
B
A
G
H
M
L
K
I
J
A
AF001612
A
B
C
D
E
F
Rack handles
H
400 W power supply
Air baffle
I
Front panel board
Power supply fans
Processor air duct
Full-height PCI riser card
J
Control panel
K
L
M
Hard drive bays (drives not included)
Optical drive bay (drive not included)
Hard drive bay (drive not included)
Low-profile PCI riser card
Intel® Server Board S5000VCL
G
Figure 16. Intel® Server System SR1530HCL/SR1530HCLR
Revision 2.3
Intel order number: D64569-007
63
Glossary
Intel® Server Board S5000VCL TPS
Glossary
Term
Definition
ACPI
Advanced Configuration and Power Interface
AP
Application Processor
APIC
ASIC
ASMI
BIOS
BIST
BMC
Bridge
BSP
byte
Advanced Programmable Interrupt Control
Application Specific Integrated Circuit
Advanced Server Management Interface
Basic Input/Output System
Built-In Self Test
Baseboard Management Controller
Circuitry connecting one computer bus to another, allowing an agent on one to access the other
Bootstrap Processor
8-bit quantity.
CBC
Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they
bridge the IPMB buses of multiple chassis.
CEK
Common Enabling Kit
CHAP
CMOS
Challenge Handshake Authentication Protocol
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes
of memory, which normally resides on the server board.
DPC
EEPROM
EHCI
EMP
EPS
ESB2
FBD
FMB
FRB
FRU
FSB
GB
Direct Platform Control
Electrically Erasable Programmable Read-Only Memory
Enhanced Host Controller Interface
Emergency Management Port
External Product Specification
Enterprise South Bridge 2
Fully Buffered DIMM
Flexible Mother Board
Fault Resilient Booting
Field Replaceable Unit
Front Side Bus
1024MB
GPIO
GTL
HSC
Hz
General Purpose I/O
Gunning Transceiver Logic
Hot-Swap Controller
Hertz (1 cycle/second)
Inter-Integrated Circuit Bus
Intel® Architecture
I2C
IA
IBF
Input Buffer
ICH
I/O Controller Hub
ICMB
IERR
IFB
Intelligent Chassis Management Bus
Internal Error
I/O and Firmware Bridge
Interrupt
INTR
IP
Internet Protocol
64
Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Term
Glossary
Definition
IPMB
IPMI
IR
Intelligent Platform Management Bus
Intelligent Platform Management Interface
Infrared
ITP
In-Target Probe
KB
1024 bytes
KCS
LAN
LCD
LED
LPC
LUN
MAC
MB
Keyboard Controller Style
Local Area Network
Liquid Crystal Display
Light Emitting Diode
Low Pin Count
Logical Unit Number
Media Access Control
1024KB
MCH
MD2
MD5
ms
Memory Controller Hub
Message Digest 2 – Hashing Algorithm
Message Digest 5 – Hashing Algorithm – Higher Security
milliseconds
MTTR
Mux
Memory Type Range Register
Multiplexor
NIC
Network Interface Controller
NMI
Nonmaskable Interrupt
OBF
OEM
Ohm
PEF
PEP
PIA
Output Buffer
Original Equipment Manufacturer
Unit of electrical resistance
Platform Event Filtering
Platform Event Paging
Platform Information Area (This feature configures the firmware for the platform hardware)
Programmable Logic Device
PLD
PMI
Platform Management Interrupt
Power-On Self Test
POST
PSMI
PWM
RAM
RASUM
RISC
ROM
RTC
SDR
SECC
SEEPROM
SEL
Power Supply Management Interface
Pulse-Width Modulation
Random Access Memory
Reliability, Availability, Serviceability, Usability, and Manageability
Reduced Instruction Set Computing
Read Only Memory
Real-Time Clock (Component of ICH peripheral chip on the server board)
Sensor Data Record
Single Edge Connector Cartridge
Serial Electrically Erasable Programmable Read-Only Memory
System Event Log
SIO
Server Input/Output
SMI
Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)
Server Management Mode
SMM
Revision 2.3
Intel order number: D64569-007
65
Glossary
Intel® Server Board S5000VCL TPS
Term
Definition
SNMP
Simple Network Management Protocol
To Be Determined
TBD
TIM
Thermal Interface Material
Universal Asynchronous Receiver/Transmitter
User Datagram Protocol
UART
UDP
UHCI
UTC
VID
Universal Host Controller Interface
Universal time coordinare
Voltage Identification
VRD
Word
ZIF
Voltage Regulator Down
16-bit quantity
Zero Insertion Force
66
Intel order number: D64569-007
Revision 2.3
Intel® Server Board S5000VCL TPS
Reference Documents
Reference Documents
•
Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 2.3
Intel order number: D64569-007
67
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