D8088 [INTEL]
8-BIT HMOS MICROPROCESSOR; 8位微处理器HMOS
| 型号： | D8088 |
| 厂家： | 
INTEL |
| 描述： | 8-BIT HMOS MICROPROCESSOR |
| 文件： | 总30页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8088
8-BIT HMOS MICROPROCESSOR
8088/8088-2
Y
Y
Y
Y
8-Bit Data Bus Interface
Byte, Word, and Block Operations
Y
Y
Y
16-Bit Internal Architecture
8-Bit and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal,
Including Multiply and Divide
Direct Addressing Capability to 1 Mbyte
of Memory
Two Clock Rates:
Ð 5 MHz for 8088
Ð 8 MHz for 8088-2
Y
Y
Y
Direct Software Compatibility with 8086
CPU
14-Word by 16-Bit Register Set with
Symmetrical Operations
Available in EXPRESS
Ð Standard Temperature Range
Ð Extended Temperature Range
24 Operand Addressing Modes
The Intel 8088 is a high performance microprocessor implemented in N-channel, depletion load, silicon gate
technology (HMOS-II), and packaged in a 40-pin CERDIP package. The processor has attributes of both 8-
and 16-bit microprocessors. It is directly compatible with 8086 software and 8080/8085 hardware and periph-
erals.
231456–2
Figure 2. 8088 Pin Configuration
231456–1
Figure 1. 8088 CPU Functional Block Diagram
August 1990
Order Number: 231456-006
8088
Table 1. Pin Description
The following pin function descriptions are for 8088 systems in either minimum or maximum mode. The ‘‘local
bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to
additional bus buffers).
Symbol
AD7–AD0
Pin No. Type
Name and Function
9–16
I/O ADDRESS DATA BUS: These lines constitute the time multiplexed
memory/IO address (T1) and data (T2, T3, Tw, T4) bus. These lines are
active HIGH and float to 3-state OFF during interrupt acknowledge and
local bus ‘‘hold acknowledge’’.
A15–A8
2–8, 39
O
ADDRESS BUS: These lines provide address bits 8 through 15 for the
entire bus cycle (T1–T4). These lines do not have to be latched by ALE
to remain valid. A15–A8 are active HIGH and float to 3-state OFF
during interrupt acknowledge and local bus ‘‘hold acknowledge’’.
A19/S6, A18/S5, 35–38
A17/S4, A16/S3
O
ADDRESS/STATUS: During T1, these are the four most significant
address lines for memory operations. During I/O operations, these lines
are LOW. During memory and I/O operations, status information is
available on these lines during T2, T3, Tw, and T4. S6 is always low.
The status of the interrupt enable flag bit (S5) is updated at the
beginning of each clock cycle. S4 and S3 are encoded as shown.
This information indicates which segment register is presently being
used for data accessing.
These lines float to 3-state OFF during local bus ‘‘hold acknowledge’’.
S4
S3
Characteristics
0 (LOW)
0
1 (HIGH)
1
S6 is 0 (LOW)
0
1
0
1
Alternate Data
Stack
Code or None
Data
RD
32
O
READ: Read strobe indicates that the processor is performing a
memory or I/O read cycle, depending on the state of the IO/M pin or
S2. This signal is used to read devices which reside on the 8088 local
bus. RD is active LOW during T2, T3 and Tw of any read cycle, and is
guaranteed to remain HIGH in T2 until the 8088 local bus has floated.
This signal floats to 3-state OFF in ‘‘hold acknowledge’’.
READY
INTR
22
18
I
I
READY: is the acknowledgement from the addressed memory or I/O
device that it will complete the data transfer. The RDY signal from
memory or I/O is synchronized by the 8284 clock generator to form
READY. This signal is active HIGH. The 8088 READY input is not
synchronized. Correct operation is not guaranteed if the set up and hold
times are not met.
INTERRUPT REQUEST: is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table located in
system memory. It can be internally masked by software resetting the
interrupt enable bit. INTR is internally synchronized. This signal is active
HIGH.
TEST
23
I
TEST: input is examined by the ‘‘wait for test’’ instruction. If the TEST
input is LOW, execution continues, otherwise the processor waits in an
‘‘idle’’ state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
2
8088
Table 1. Pin Description (Continued)
Name and Function
Symbol
Pin No.
Type
NMI
17
I
NON-MASKABLE INTERRUPT: is an edge triggered input which causes a
type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup
table located in system memory. NMI is not maskable internally by
software. A transition from a LOW to HIGH initiates the interrupt at the end
of the current instruction. This input is internally synchronized.
RESET
CLK
21
19
I
I
RESET: causes the processor to immediately terminate its present activity.
The signal must be active HIGH for at least four clock cycles. It restarts
execution, as described in the instruction set description, when RESET
returns LOW. RESET is internally synchronized.
CLOCK: provides the basic timing for the processor and bus controller. It is
asymmetric with a 33% duty cycle to provide optimized internal timing.
a
g
: is the 5V 10% power supply pin.
CC
V
40
1, 20
33
V
CC
GND
GND: are the ground pins.
MN/MX
I
MINIMUM/MAXIMUM: indicates what mode the processor is to operate in.
The two modes are discussed in the following sections.
e
functions which are unique to minimum mode are described; all other pin functions are as described above.
The following pin function descriptions are for the 8088 minimum mode (i.e., MN/MX
V
). Only the pin
CC
Symbol Pin No. Type
Name and Function
IO/M
28
O
STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a
memory access from an I/O access. IO/M becomes valid in the T4 preceding a
e
e
bus cycle and remains valid until the final T4 of the cycle (I/O
LOW). IO/M floats to 3-state OFF in local bus ‘‘hold acknowledge’’.
HIGH, M
WR
29
O
WRITE: strobe indicates that the processor is performing a write memory or write
I/O cycle, depending on the state of the IO/M signal. WR is active for T2, T3, and
Tw of any write cycle. It is active LOW, and floats to 3-state OFF in local bus
‘‘hold acknowledge’’.
INTA
ALE
24
25
O
O
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW
during T2, T3, and Tw of each interrupt acknowledge cycle.
ADDRESS LATCH ENABLE: is provided by the processor to latch the address
into an address latch. It is a HIGH pulse active during clock low of T1 of any bus
cycle. Note that ALE is never floated.
DT/R
DEN
27
26
O
O
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use
a data bus transceiver. It is used to control the direction of data flow through the
transceiver. Logically, DT/R is equivalent to S1 in the maximum mode, and its
e
3-state OFF in local ‘‘hold acknowledge’’.
e
timing is the same as for IO/M (T
HIGH, R
LOW). This signal floats to
DATA ENABLE: is provided as an output enable for the data bus transceiver in a
minimum system which uses the transceiver. DEN is active LOW during each
memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is
active from the middle of T2 until the middle of T4, while for a write cycle, it is
active from the beginning of T2 until the middle of T4. DEN floats to 3-state OFF
during local bus ‘‘hold acknowledge’’.
3
8088
Table 1. Pin Description (Continued)
Symbol Pin No. Type
Name and Function
HOLD,
HLDA
31, 30
I, O HOLD: indicates that another master is requesting a local bus ‘‘hold’’. To be
acknowledged, HOLD must be active HIGH. The processor receiving the ‘‘hold’’
request will issue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or
Ti clock cycle. Simultaneous with the issuance of HLDA the processor will float
the local bus and control lines. After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it
will again drive the local bus and control lines. HOLD and HLDA have internal
pull-up resistors.
Hold is not an asynchronous input. External synchronization should be provided if
the system cannot otherwise guarantee the set up time.
SSO
34
O
STATUS LINE: is logically equivalent to SO in the maximum mode. The
combination of SSO, IO/M and DT/R allows the system to completely decode the
current bus cycle status.
IO/M
DT/R
SSO
Characteristics
1(HIGH)
1
1
1
0(LOW)
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
e
The following pin function descriptions are for the 8088/8288 system in maximum mode (i.e., MN/MX
GND). Only the pin functions which are unique to maximum mode are described; all other pin functions are as
described above.
Symbol Pin No. Type
S2, S1, S0 26–28
Name and Function
O
STATUS: is active during clock high of T4, T1, and T2, and is returned to the
passive state (1,1,1) during T3 or during Tw when READY is HIGH. This status is
used by the 8288 bus controller to generate all memory and I/O access control
signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning
of a bus cycle, and the return to the passive state in T3 and Tw is used to
indicate the end of a bus cycle.
These signals float to 3-state OFF during ‘‘hold acknowledge’’. During the first
clock cycle after RESET becomes active, these signals are active HIGH. After
this first clock, they float to 3-state OFF.
S2
S1
S0
Characteristics
0(LOW)
0
0
0
1(HIGH)
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
4
8088
Table 1. Pin Description (Continued)
Name and Function
Symbol
Pin No. Type
RQ/GT0,
RQ/GT1
30, 31
I/O
REQUEST/GRANT: pins are used by other local bus masters to force the
processor to release the local bus at the end of the processor’s current bus
cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/
GT1. RQ/GT has an internal pull-up resistor, so may be left unconnected.
The request/grant sequence is as follows (See Figure 8):
1. A pulse of one CLK wide from another local bus master indicates a local
bus request (‘‘hold’’) to the 8088 (pulse 1).
2. During a T4 or TI clock cycle, a pulse one clock wide from the 8088 to the
requesting master (pulse 2), indicates that the 8088 has allowed the local
bus to float and that it will enter the ‘‘hold acknowledge’’ state at the next
CLK. The CPU’s bus interface unit is disconnected logically from the local
bus during ‘‘hold acknowledge’’. The same rules as for HOLD/HOLDA apply
as for when the bus is released.
3. A pulse one CLK wide from the requesting master indicates to the 8088
(pulse 3) that the ‘‘hold’’ request is about to end and that the 8088 can
reclaim the local bus at the next CLK. The CPU then enters T4.
Each master-master exchange of the local bus is a sequence of three
pulses. There must be one idle CLK cycle after each bus exchange. Pulses
are active LOW.
If the request is made while the CPU is performing a memory cycle, it will
release the local bus during T4 of the cycle when all the following conditions
are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge
sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will
follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently
active memory cycle apply with condition number 1 already satisfied.
LOCK
29
O
O
LOCK: indicates that other system bus masters are not to gain control of the
system bus while LOCK is active (LOW). The LOCK signal is activated by
the ‘‘LOCK’’ prefix instruction and remains active until the completion of the
next instruction. This signal is active LOW, and floats to 3-state off in ‘‘hold
acknowledge’’.
QS1, QS0
24, 25
QUEUE STATUS: provide status to allow external tracking of the internal
8088 instruction queue.
The queue status is valid during the CLK cycle after which the queue
operation is performed.
QS1
QS0
Characteristics
0(LOW)
0
1(HIGH)
1
0
1
0
1
No Operation
First Byte of Opcode from Queue
Empty the Queue
Subsequent Byte from Queue
Ð
34
O
Pin 34 is always high in the maximum mode.
5
8088
231456–3
Figure 3. Memory Organization
dressing needs of programs. The segment register
to be selected is automatically chosen according to
the rules of the following table. All information in one
segment type share the same logical attributes (e.g.
code or data). By structuring memory into relocat-
able areas of similar characteristics and by automati-
cally selecting segment registers, programs are
shorter, faster, and more structured.
FUNCTIONAL DESCRIPTION
Memory Organization
The processor provides a 20-bit address to memory
which locates the byte being referenced. The memo-
ry is organized as a linear array of up to 1 million
bytes, addressed as 00000(H) to FFFFF(H). The
memory is logically divided into code, data, extra
data, and stack segments of up to 64K bytes each,
with each segment falling on 16-byte boundaries
(See Figure 3).
Word (16-bit) operands can be located on even or
odd address boundaries. For address and data oper-
ands, the least significant byte of the word is stored
in the lower valued address location and the most
significant byte in the next higher address location.
The BIU will automatically execute two fetch or write
cycles for 16-bit operands.
All memory references are made relative to base ad-
dresses contained in high speed segment registers.
The segment types were chosen based on the ad-
Memory
Segment
Segment Selection Rule
Reference Used
Register Used
Instructions
Stack
CODE (CS)
STACK (SS)
Automatic with all instruction prefetch.
All stack pushes and pops. Memory references
relative to BP base register except data references.
Local Data
DATA (DS)
Data references when: relative to stack, destination
of string operation, or explicity overridden.
External (Global) Data
EXTRA (ES)
Destination of string operations: Explicitly selected
using a segment override.
6
8088
Certain locations in memory are reserved for specific
CPU operations (See Figure 4). Locations from ad-
dresses FFFF0H through FFFFFH are reserved for
operations including a jump to the initial system ini-
tialization routine. Following RESET, the CPU will al-
ways begin execution at location FFFF0H where the
jump must be located. Locations 00000H through
003FFH are reserved for interrupt operations. Four-
byte pointers consisting of a 16-bit segment address
and a 16-bit offset address direct program flow to
one of the 256 possible interrupt service routines.
The pointer elements are assumed to have been
stored at their respective places in reserved memory
prior to the occurrence of interrupts.
figuration. The definition of a certain subset of the
pins changes, dependent on the condition of the
strap pin. When the MN/MX pin is strapped to GND,
the 8088 defines pins 24 through 31 and 34 in maxi-
mum mode. When the MN/MX pin is strapped to
V , the 8088 generates bus control signals itself on
CC
pins 24 through 31 and 34.
The minimum mode 8088 can be used with either a
multiplexed or demultiplexed bus. The multiplexed
bus configuration is compatible with the MCS-85
multiplexed bus peripherals. This configuration (See
Figure 5) provides the user with a minimum chip
count system. This architecture provides the 8088
processing power in a highly integrated form.
The demultiplexed mode requires one latch (for 64K
addressability) or two latches (for a full megabyte of
addressing). A third latch can be used for buffering if
the address bus loading requires it. A transceiver
can also be used if data bus buffering is required
(See Figure 6). The 8088 provides DEN and DT/R to
control the transceiver, and ALE to latch the ad-
dresses. This configuration of the minimum mode
provides the standard demultiplexed bus structure
with heavy bus buffering and relaxed bus timing re-
quirements.
Minimum and Maximum Modes
The requirements for supporting minimum and maxi-
mum 8088 systems are sufficiently different that
they cannot be done efficiently with 40 uniquely de-
fined pins. Consequently, the 8088 is equipped with
a strap pin (MN/MX) which defines the system con-
The maximum mode employs the 8288 bus control-
ler (See Figure 7). The 8288 decodes status lines
S0, S1, and S2, and provides the system with all bus
control signals. Moving the bus control to the 8288
provides better source and sink current capability to
the control lines, and frees the 8088 pins for extend-
ed large system features. Hardware lock, queue
status, and two request/grant interfaces are provid-
ed by the 8088 in maximum mode. These features
allow co-processors in local bus and remote bus
configurations.
231456–4
Figure 4. Reserved Memory Locations
7
8088
231456–5
Figure 5. Multiplexed Bus Configuration
8
8088
231456–6
Figure 6. Demultiplexed Bus Configuration
231456–7
Figure 7. Fully Buffered System Using Bus Controller
9
8088
id throughout each bus cycle. In addition, the bus
can be demultiplexed at the processor with a single
address latch if a standard, non-multiplexed bus is
desired for the system.
Bus Operation
The 8088 address/data bus is broken into three
partsÐthe lower eight address/data bits (AD0–
AD7), the middle eight address bits (A8–A15), and
the upper four address bits (A16–A19). The ad-
dress/data bits and the highest four address bits are
time multiplexed. This technique provides the most
efficient use of pins on the processor, permitting the
use of a standard 40 lead package. The middle eight
address bits are not multiplexed, i.e. they remain val-
Each processor bus cycle consists of at least four
CLK cycles. These are referred to as T1, T2, T3, and
T4 (See Figure 8). The address is emitted from the
processor during T1 and data transfer occurs on the
bus during T3 and T4. T2 is used primarily for chang-
231456–8
Figure 8. Basic System Timing
10
8088
ing the direction of the bus during read operations. In
the event that a ‘‘NOT READY’’ indication is given
by the addressed device, ‘‘wait’’ states (Tw) are in-
serted between T3 and T4. Each inserted ‘‘wait’’
state is of the same duration as a CLK cycle. Periods
can occur between 8088 driven bus cycles. These
are referred to as ‘‘idle’’ states (Ti), or inactive CLK
cycles. The processor uses these cycles for internal
housekeeping.
which use register DX as a pointer, have full address
capability, while the direct I/O instructions directly
address one or two of the 256 I/O byte locations in
page 0 of the I/O address space. I/O ports are ad-
dressed in the same manner as memory locations.
Designers familiar with the 8085 or upgrading an
8085 design should note that the 8085 addresses
I/O with an 8-bit address on both halves of the 16-
bit address bus. The 8088 uses a full 16-bit address
on its lower 16 address lines.
During T1 of any bus cycle, the ALE (address latch
enable) signal is emitted (by either the processor or
the 8288 bus controller, depending on the MN/MX
strap). At the trailing edge of this pulse, a valid ad-
dress and certain status information for the cycle
may be latched.
EXTERNAL INTERFACE
Processor Reset and Initialization
Status bits S0, S1, and S2 are used by the bus con-
troller, in maximum mode, to identify the type of bus
transaction according to the following table:
Processor initialization or start up is accomplished
with activation (HIGH) of the RESET pin. The 8088
RESET is required to be HIGH for greater than four
clock cycles. The 8088 will terminate operations on
the high-going edge of RESET and will remain dor-
mant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset se-
quence for approximately 7 clock cycles. After this
interval the 8088 operates normally, beginning with
the instruction in absolute locations FFFF0H (See
Figure 4). The RESET input is internally synchroniz-
ed to the processor clock. At initialization, the HIGH
to LOW transition of RESET must occur no sooner
than 50 ms after power up, to allow complete initiali-
zation of the 8088.
S2
S1
S0
Characteristics
0(LOW)
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
0
0
1(HIGH)
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (No Bus Cycle)
1
1
1
Status bits S3 through S6 are multiplexed with high
order address bits and are therefore valid during T2
through T4. S3 and S4 indicate which segment reg-
ister was used for this bus cycle in forming the ad-
dress according to the following table:
NMI asserted prior to the 2nd clock after the end of
RESET will not be honored. If NMI is asserted after
that point and during the internal reset sequence,
the processor may execute one instruction before
responding to the interrupt. A hold request active
immediately after RESET will be honored before the
first instruction fetch.
S
4
S
Characteristics
3
0(LOW)
0
0
Alternate Data (Extra Segment)
Stack
All 3-state outputs float to 3-state OFF during
RESET. Status is active in the idle state for the first
clock after RESET becomes active and then floats
to 3-state OFF. ALE and HLDA are driven low.
1
0
1
1(HIGH)
1
Code or None
Data
S5 is a reflection of the PSW interrupt enable bit. S6
is always equal to 0.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts
and software aspects of hardware interrupts are
specified in the instruction set description in the
iAPX 88 book or the iAPX 86,88 User’s Manual.
Hardware interrupts can be classified as nonmaska-
ble or maskable.
I/O Addressing
In the 8088, I/O operations can address up to a
maximum of 64K I/O registers. The I/O address ap-
pears in the same format as the memory address on
bus lines A15–A0. The address lines A19–A16 are
zero in I/O operations. The variable I/O instructions,
11
8088
Interrupts result in a transfer of control to a new pro-
gram location. A 256 element table containing ad-
dress pointers to the interrupt service program loca-
tions resides in absolute locations 0 through 3FFH
(See Figure 4), which are reserved for this purpose.
Each element in the table is 4 bytes in size and cor-
responds to an interrupt ‘‘type.’’ An interrupting de-
vice supplies an 8-bit type number, during the inter-
rupt acknowledge sequence, which is used to vector
through the appropriate element to the new interrupt
service program location.
enable bit will be zero unless specifically set by an
instruction.
During the response sequence (See Figure 9), the
processor executes two successive (back to back)
interrupt acknowledge cycles. The 8088 emits the
LOCK signal (maximum mode only) from T2 of the
first bus cycle until T2 of the second. A local bus
‘‘hold’’ request will not be honored until the end of
the second bus cycle. In the second bus cycle, a
byte is fetched from the external interrupt system
(e.g., 8259A PIC) which identifies the source (type)
of the interrupt. This byte is multiplied by four and
used as a pointer into the interrupt vector lookup
table. An INTR signal left HIGH will be continually
responded to within the limitations of the enable bit
and sample period. The interrupt return instruction
includes a flags pop which returns the status of the
original interrupt enable bit when it restores the
flags.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable inter-
rupt (NMI) pin which has higher priority than the
maskable interrupt request (INTR) pin. A typical use
would be to activate a power failure routine. The
NMI is edge-triggered on a LOW to HIGH transition.
The activation of this pin causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state
of greater than two clock cycles, but is not required
to be synchronized to the clock. Any higher going
transition of NMI is latched on-chip and will be serv-
iced at the end of the current instruction or between
whole moves (2 bytes in the case of word moves) of
a block type instruction. Worst case response to
NMI would be for multiply, divide, and variable shift
instructions. There is no specification on the occur-
rence of the low-going edge; it may occur before,
during, or after the servicing of NMI. Another high-
going edge triggers another response if it occurs af-
ter the start of the NMI procedure. The signal must
be free of logical spikes in general and be free of
bounces on the low-going edge to avoid triggering
extraneous responses.
HALT
When a software HALT instruction is executed, the
processor indicates that it is entering the HALT state
in one of two ways, depending upon which mode is
strapped. In minimum mode, the processor issues
ALE, delayed by one clock cycle, to allow the sys-
tem to latch the halt status. Halt status is available
on IO/M, DT/R, and SSO. In maximum mode, the
processor issues appropriate HALT status on S2,
S1, and S0, and the 8288 bus controller issues one
ALE. The 8088 will not leave the HALT state when a
local bus hold is entered while in HALT. In this case,
the processor reissues the HALT indicator at the
end of the local bus hold. An interrupt request or
RESET will force the 8088 out of the HALT state.
Maskable Interrupt (INTR)
Read/Modify/Write (Semaphore)
Operations via LOCK
The 8088 provides a single interrupt request input
(INTR) which can be masked internally by software
with the resetting of the interrupt enable (IF) flag bit.
The interrupt request signal is level triggered. It is
internally synchronized during each clock cycle on
the high-going edge of CLK. To be responded to,
INTR must be present (HIGH) during the clock peri-
od preceding the end of the current instruction or the
end of a whole move for a block type instruction.
During interrupt response sequence, further inter-
rupts are disabled. The enable bit is reset as part of
the response to any interrupt (INTR, NMI, software
interrupt, or single step), although the FLAGS regis-
ter which is automatically pushed onto the stack re-
flects the state of the processor prior to the inter-
rupt. Until the old FLAGS register is restored, the
The LOCK status information is provided by the
processor when consecutive bus cycles are required
during the execution of an instruction. This allows
the processor to perform read/modify/write opera-
tions on memory (via the ‘‘exchange register with
memory’’ instruction), without another system bus
master receiving intervening memory cycles. This is
useful in multiprocessor system configurations to ac-
complish ‘‘test and set lock’’ operations. The LOCK
signal is activated (LOW) in the clock cycle following
decoding of the LOCK prefix instruction. It is deacti-
vated at the end of the last bus cycle of the instruc-
tion following the LOCK prefix. While LOCK is active,
a request on a RQ/GT pin will be recorded, and then
honored at the end of the LOCK.
12
8088
231456–9
Figure 9. Interrupt Acknowledge Sequence
going) edge of this signal is used to latch the ad-
dress information, which is valid on the address/
data bus (AD0–AD7) at this time, into the
8282/8283 latch. Address lines A8 through A15 do
not need to be latched because they remain valid
throughout the bus cycle. From T1 to T4 the IO/M
signal indicates a memory or I/O operation. At T2
the address is removed from the address/data bus
and the bus goes to a high impedance state. The
read control signal is also asserted at T2. The read
(RD) signal causes the addressed device to enable
its data bus drivers to the local bus. Some time later,
valid data will be available on the bus and the ad-
dressed device will drive the READY line HIGH.
When the processor returns the read signal to a
HIGH level, the addressed device will again 3-state
its bus drivers. If a transceiver is required to buffer
the 8088 local bus, signals DT/R and DEN are pro-
vided by the 8088.
External Synchronization via TEST
As an alternative to interrupts, the 8088 provides a
single software-testable input pin (TEST). This input
is utilized by executing a WAIT instruction. The sin-
gle WAIT instruction is repeatedly executed until the
TEST input goes active (LOW). The execution of
WAIT does not consume bus cycles once the queue
is full.
If a local bus request occurs during WAIT execution,
the 8088 3-states all output drivers. If interrupts are
enabled, the 8088 will recognize interrupts and pro-
cess them. The WAIT instruction is then refetched,
and reexecuted.
Basic System Timing
In minimum mode, the MN/MX pin is strapped to
and the processor emits bus control signals
V
A write cycle also begins with the assertion of ALE
and the emission of the address. The IO/M signal is
again asserted to indicate a memory or I/O write
operation. In T2, immediately following the address
emission, the processor emits the data to be written
into the addressed location. This data remains valid
until at least the middle of T4. During T2, T3, and
Tw, the processor asserts the write control signal.
The write (WR) signal becomes active at the begin-
ning of T2, as opposed to the read, which is delayed
somewhat into T2 to provide time for the bus to
float.
CC
compatible with the 8085 bus structure. In maximum
mode, the MN/MX pin is strapped to GND and the
processor emits coded status information which the
8288 bus controller uses to generate MULTIBUS
compatible bus control signals.
System TimingÐMinimum System
(See Figure 8)
The read cycle begins in T1 with the assertion of the
address latch enable (ALE) signal. The trailing (low
13
8088
The basic difference between the interrupt acknowl-
edge cycle and a read cycle is that the interrupt ac-
knowledge (INTA) signal is asserted in place of the
read (RD) signal and the address bus is floated.
(See Figure 9) In the second of two successive INTA
cycles, a byte of information is read from the data
bus, as supplied by the interrupt system logic (i.e.
8259A priority interrupt controller). This byte identi-
fies the source (type) of the interrupt. It is multiplied
by four and used as a pointer into the interrupt vec-
tor lookup table, as described earlier.
the same way the 8086 does with the distinction of
handling only 8 bits at a time. Sixteen-bit operands
are fetched or written in two consecutive bus cycles.
Both processors will appear identical to the software
engineer, with the exception of execution time. The
internal register structure is identical and all instruc-
tions have the same end result. The differences be-
tween the 8088 and 8086 are outlined below. The
engineer who is unfamiliar with the 8086 is referred
to the iAPX 86, 88 User’s Manual, Chapters 2 and 4,
for function description and instruction set informa-
tion. Internally, there are three differences between
the 8088 and the 8086. All changes are related to
the 8-bit bus interface.
Bus TimingÐMedium Complexity
Systems
The queue length is 4 bytes in the 8088, whereas
#
the 8086 queue contains 6 bytes, or three words.
The queue was shortened to prevent overuse of
the bus by the BIU when prefetching instructions.
This was required because of the additional time
necessary to fetch instructions 8 bits at a time.
(See Figure 10)
For medium complexity systems, the MN/MX pin is
connected to GND and the 8288 bus controller is
added to the system, as well as a latch for latching
the system address, and a transceiver to allow for
bus loading greater than the 8088 is capable of han-
dling. Signals ALE, DEN, and DT/R are generated
by the 8288 instead of the processor in this configu-
ration, although their timing remains relatively the
same. The 8088 status outputs (S2, S1, and S0) pro-
vide type of cycle information and become 8288 in-
puts. This bus cycle information specifies read
(code, data, or I/O), write (data or I/O), interrupt ac-
knowledge, or software halt. The 8288 thus issues
control signals specifying memory read or write, I/O
read or write, or interrupt acknowledge. The 8288
provides two types of write strobes, normal and ad-
vanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write.
The advanced write strobes have the same timing
as read strobes, and hence, data is not valid at the
leading edge of write. The transceiver receives the
usual T and OE inputs from the 8288’s DT/R and
DEN outputs.
To further optimize the queue, the prefetching al-
#
gorithm was changed. The 8088 BIU will fetch a
new instruction to load into the queue each time
there is a 1 byte hole (space available) in the
queue. The 8086 waits until a 2-byte space is
available.
The internal execution time of the instruction set
#
is affected by the 8-bit interface. All 16-bit fetches
and writes from/to memory take an additional
four clock cycles. The CPU is also limited by the
speed of instruction fetches. This latter problem
only occurs when a series of simple operations
occur. When the more sophisticated instructions
of the 8088 are being used, the queue has time to
fill and the execution proceeds as fast as the exe-
cution unit will allow.
The 8088 and 8086 are completely software com-
patible by virtue of their identical execution units.
Software that is system dependent may not be com-
pletely transferable, but software that is not system
dependent will operate equally as well on an 8088
and an 8086.
The pointer into the interrupt vector table, which is
passed during the second INTA cycle, can derive
from an 8259A located on either the local bus or the
system bus. If the master 8289A priority interrupt
controller is positioned on the local bus, a TTL gate
is required to disable the transceiver when reading
from the master 8259A during the interrupt acknowl-
edge sequence and software ‘‘poll’’.
The hardware interface of the 8088 contains the ma-
jor differences between the two CPUs. The pin as-
signments are nearly identical, however, with the fol-
lowing functional changes:
A8–A15ÐThese pins are only address outputs
#
on the 8088. These address lines are latched in-
ternally and remain valid throughout a bus cycle
in a manner similar to the 8085 upper address
lines.
The 8088 Compared to the 8086
The 8088 CPU is an 8-bit processor designed
around the 8086 internal structure. Most internal
functions of the 8088 are identical to the equivalent
8086 functions. The 8088 handles the external bus
BHE has no meaning on the 8088 and has been
eliminated.
#
14
8088
SSO provides the SO status information in the
minimum mode. This output occurs on pin 34 in
minimum mode only. DT/R, IO/M, and SSO pro-
vide the complete bus status in minimum mode.
IO/M has been inverted to be compatible with the
MCS-85 bus structure.
#
#
#
ALE is delayed by one clock cycle in the mini-
mum mode when entering HALT, to allow the
status to be latched with ALE.
231456–10
Figure 10. Medium Complexity System Timing
15
8088
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
a
Ambient Temperature Under Bias ÀÀÀÀ0 C to 70 C
§
§
§
§
§
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
a
Case Temperature (Plastic) ÀÀÀÀÀÀÀÀÀ0 C to 95 C
§
a
Case Temperature (CERDIP) ÀÀÀÀÀÀÀÀ0 C to 75 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
b
a
§
Voltage on Any Pin with
Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1.0 to 7V
b
a
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5 Watt
D.C. CHARACTERISTICS
e
e
0 C to 75 C for P8088-2 only
is not exceeded)
e
(CERDIP) 0 C to 75 C,
(T
T
0 C to 70 C, T
§
(Plastic)
e
0 C to 95 C, T
CASE
§
§
§
§
§
A
CASE
e
is guaranteed as long as T
0 C to 55 C and T
§
§
§
§
A
CASE
T
A
CASE
e
e
5V 5% for 8088-2 and Extended Temperature EXPRESS)
g
5V 10% for 8088, V
g
(V
CC
CC
Symbol
Parameter
Min
Max
Units
V
Test Conditions
(Note 1)
(Notes 1, 2)
b
a
0.8
V
V
V
V
I
Input Low Voltage
0.5
IL
a
CC
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
V
0.5
V
IH
e
0.45
V
I
I
2.0 mA
OL
OH
OL
e b
2.4
V
400 mA
OH
e
8088
Power Supply Current: 8088-2
P8088
340
350
250
mA
T
25 C
§
CC
A
s
s
g
g
a
I
I
Input Leakage Current
10
10
mA
mA
V
0V
V
V
(Note 3)
LI
LO
IN
CC
s
s
Output and I/O Leakage Current
Clock Input Low Voltage
Clock Input High Voltage
0.45V
V
OUT
V
CC
b
V
V
0.5
0.6
CL
a
3.9
V
1.0
V
CH
CC
e
e
C
Capacitance If Input Buffer
(All Input Except
AD –AD , RQ/GT)
15
pF
fc
fc
1 MHz
1 MHz
IN
IO
0
7
C
Capacitance of I/O Buffer
AD –AD , RQ/GT)
15
pF
0
7
NOTES:
1. V tested with MN/MX Pin
e
e
0V
5V
IL
V
tested with MN/MX Pin
IH
MN/MX Pin is a strap Pin
2. Not applicable to RQ/GT0 and RQ/GT1 Pins (Pins 30 and 31)
e
e
3. HOLD and HLDA I Min
LI
30 mA, Max
500 mA
16
8088
A.C. CHARACTERISTICS
e
e
0 C to 80 C for P8088-2 only
e
(CERDIP) 0 C to 75 C,
(T
T
0 C to 70 C, T
§
(Plastic)
e
0 C to 95 C, T
CASE
§
§
§
§
§
A
CASE
e
is guaranteed as long as T
0 C to 55 C and T
§
§
§
§
A
CASE
T
A
is not exceeded)
CASE
e
e
5V 5% for 8088-2 and Extended Temperature EXPRESS)
g
5V 10% for 8088, V
g
(V
CC
CC
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS
8088
8088-2
Test
Symbol
Parameter
Units
Conditions
Min
200
118
69
Max
Min
Max
TCLCL
CLK Cycle Period
500
125
68
500
ns
ns
ns
ns
ns
ns
ns
ns
TCLCH
TCHCL
TCH1CH2
TCL2CL2
TDVCL
CLK Low Time
CLK High Time
CLK Rise Time
CLK Fall Time
44
10
10
10
10
From 1.0V to 3.5V
From 3.5V to 1.0V
Data in Setup Time
Data in Hold Time
30
10
35
20
10
35
TCLDX
TR1VCL
RDY Setup Time into 8284
(Notes 1, 2)
TCLR1X
TRYHCH
TCHRYX
TRYLCL
RDY Hold Time into 8284
(Notes 1, 2)
0
0
ns
ns
ns
ns
READY Setup Time
into 8088
118
30
68
20
READY Hold Time
into 8088
b
b
8
READY Inactive to CLK
(Note 3)
8
THVCH
TINVCH
HOLD Setup Time
35
30
20
15
ns
ns
INTR, NMI, TEST Setup Time
(Note 2)
TILIH
TIHIL
Input Rise Time (Except CLK)
Input Fall Time (Except CLK)
20
12
20
12
ns
ns
From 0.8V to 2.0V
From 2.0V to 0.8V
17
8088
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
8088
Min
8088-2
Min
Test
Symbol
Parameter
Units
Conditions
Max
Max
TCLAV
TCLAX
TCLAZ
TLHLL
TCLLH
TCHLL
TLLAX
Address Valid Delay
Address Hold Time
Address Float Delay
ALE Width
10
10
110
10
10
60
ns
ns
ns
ns
ns
ns
ns
TCLAX
80
TCLAX
50
b
TCLCH 20
b
TCLCH 10
ALE Active Delay
ALE Inactive Delay
80
85
50
55
b
TCHCL 10
b
TCHCL 10
Address Hold Time to
ALE Inactive
TCLDV
TCHDX
Data Valid Delay
Data Hold Time
10
10
110
10
10
60
ns
ns
ns
ns
ns
ns
ns
b
TCLCH 30
b
TCLCH 30
TWHDX Data Hold Time after WR
TCVCTV Control Active Delay 1
TCHCTV Control Active Delay 2
TCVCTX Control Inactive Delay
10
10
10
0
110
110
110
10
10
10
0
70
60
70
TAZRL
Address Float to READ
Active
TCLRL
TCLRH
TRHAV
RD Active Delay
RD Inactive Delay
10
10
165
150
10
10
100
80
ns
ns
ns
b
TCLCL 45
b
TCLCL 40
RD Inactive to Next
Address Active
TCLHAV HLDA Valid Delay
TRLRH RD Width
TWLWH WR Width
TAVAL Address Valid to ALE Low TCLCH 60
10
160
10
100
ns
ns
ns
ns
ns
ns
b
b
2TCLCL 50
2TCLCL 75
b
b
2TCLCL 40
2TCLCL 60
b
b
TCLCH 40
TOLOH Output Rise Time
TOHOL Output Fall Time
20
12
20
12
From 0.8V to 2.0V
From 2.0V to 0.8V
NOTES:
1. Signal at 8284A shown for reference only. See 8284A data sheet for the most recent specifications.
2. Set up requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state (8 ns into T3 state).
18
8088
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
231456–11
A.C. Testing; Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V
for a logic ‘‘0’’. Timing measurements are made at 1.5V for both a
logic ‘‘1’’ and logic ‘‘0’’.
231456–12
C
Includes Jig Capacitance
L
WAVEFORMS
BUS TIMINGÐMINIMUM MODE SYSTEM
231456–13
19
8088
WAVEFORMS (Continued)
BUS TIMINGÐMINIMUM MODE SYSTEM (Continued)
231456–14
NOTES:
1. All signals switch between V
and V unless otherwise specified.
OL
OH
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.
2
3
w
w
3. Two INTA cycles run back-to-back. The 8088 local ADDR/DATA bus is floating during both INTA cycles. Control
signals are shown for the second INTA cycle.
4. Signals at 8284 are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
20
8088
A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
8088
8088-2
Test
Symbol
Parameter
Units
Conditions
Min
200
118
69
Max
Min
Max
TCLCL
CLK Cycle Period
500
125
68
500
ns
ns
ns
ns
ns
ns
ns
ns
TCLCH
TCHCL
TCH1CH2
TCL2CL1
TDVCL
CLK Low Time
CLK High Time
CLK Rise Time
CLK Fall Time
44
10
10
10
10
From 1.0V to 3.5V
From 3.5V to 1.0V
Data in Setup Time
Data in Hold Time
30
10
35
20
10
35
TCLDX
TR1VCL
RDY Setup Time into 8284
(Notes 1, 2)
TCLR1X
RDY Hold Time into 8284
(Notes 1, 2)
0
0
ns
TRYHCH
TCHRYX
TRYLCL
READY Setup Time into 8088
READY Hold Time into 8088
118
30
68
20
ns
ns
ns
b
b
8
READY Inactive to CLK
(Note 4)
8
TINVCH
Setup Time for Recognition
(INTR, NMI, TEST) (Note 2)
30
15
ns
TGVCH
TCHGX
TILIH
RQ/GT Setup Time
30
40
15
30
ns
ns
ns
ns
RQ Hold Time into 8088
Input Rise Time (Except CLK)
Input Fall Time (Except CLK)
20
12
20
12
From 0.8V to 2.0V
From 2.0V to 0.8V
TIHIL
21
8088
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
8088
Min
8088-2
Min
Test
Conditions
Symbol
Parameter
Units
Max
Max
TCLML
Command Active Delay
(Note 1)
10
35
10
35
ns
TCLMH Command Inactive Delay
(Note 1)
10
35
10
35
65
ns
ns
TRYHSH READY Active to
Status Passive (Note 3)
110
TCHSV Status Active Delay
10
10
110
130
110
10
10
60
70
60
ns
ns
ns
ns
ns
ns
TCLSH
TCLAV
TCLAX
TCLAZ
TSVLH
Status Inactive Delay
Address Valid Delay
Address Hold Time
Address Float Delay
10
10
10
10
TCLAX
80
15
TCLAX
50
15
Status Valid to ALE High
(Note 1)
TSVMCH Status Valid to MCE High
(Note 1)
15
15
15
15
ns
ns
TCLLH
CLK Low to ALE Valid
(Note 1)
TCLMCH CLK Low to MCE (Note 1)
TCHLL ALE Inactive Delay (Note 1)
TCLMCL MCE Inactive Delay (Note 1)
TCLDV Data Valid Delay
15
15
15
15
15
60
ns
ns
ns
ns
ns
ns
15
10
10
5
110
10
10
5
TCHDX Data Hold Time
e
C
20–100 pF for
L
TCVNV Control Active Delay
(Note 1)
45
45
45
45
All 8088 Outputs
in Addition to
Internal Loads
TCVNX Control Inactive Delay
(Note 1)
10
0
10
0
ns
ns
TAZRL
Address Float to
Read Active
TCLRL
TCLRH
RD Active Delay
RD Inactive Delay
10
10
165
150
10
10
100 ns
80
ns
ns
b
TCLCL 45
b
TCLCL 40
TRHAV RD Inactive to Next
Address Active
TCHDTL Direction Control
Active Delay (Note 1)
50
30
50
30
ns
ns
TCHDTH Direction Control
Inactive Delay (Note 1)
TCLGL
GT Active Delay
85
85
50
50
ns
ns
ns
TCLGH GT Inactive Delay
TRLRH RD Width
b
2TCLCL 75
b
2TCLCL 50
TOLOH Output Rise Time
TOHOL Output Fall Time
20
12
20
12
ns From 0.8V to 2.0V
ns From 2.0V to 0.8V
NOTES:
1. Signal at 8284 or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T3 and wait states.
4. Applies only to T2 state (8 ns into T3 state).
22
8088
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
231456–11
A.C. Testing; Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V
for a logic ‘‘0’’. Timing measurements are made at 1.5V for both a
logic ‘‘1’’ and logic ‘‘0’’.
231456–12
C
Includes Jig Capacitance
L
WAVEFORMS (Continued)
BUS TIMINGÐMAXIMUM MODE SYSTEM
231456–15
23
8088
WAVEFORMS (Continued)
BUS TIMINGÐMAXIMUM MODE SYSTEM (USING 8288)
NOTES:
1. All signals switch between V
231456–16
and V unless otherwise specified.
OL
OH
2. RDY is sampled near the end of T , T , T to determine if T machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycles.
2
3
w
w
4. Two INTA cycles run back-to-back. The 8088 local ADDR/DATA bus is floating during both INTA cycles. Control for
pointer address is shown for second INTA cycle.
5. Signals at 8284 or 8288 are shown for reference only.
6. The issuance of the 8288 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and
DEN) lags the active high 8288 CEN.
7. All timing measurements are made at 1.5V unless otherwise noted.
8. Status inactive in state just prior to T .
4
24
8088
WAVEFORMS (Continued)
BUS LOCK SIGNAL TIMING
(MAXIMUM MODE ONLY)
ASYNCHRONOUS SIGNAL RECOGNITION
231456–18
NOTE:
1. Setup requirements for asynchronous signals only to
guarantee recognition at next CLK.
231456–17
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTE:
1. The coprocessor may not drive the busses outside the region shown without risking contention.
231456–19
HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
231456–20
25
8088
8086/8088 Instruction Set Summary
Mnemonic and
Description
Instruction Code
DATA TRANSFER
e
MOV
Move:
7 6 5 4 3 2 1 0
1 0 0 0 1 0 d w
1 1 0 0 0 1 1 w
1 0 1 1 w reg
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Register/Memory to/from Register
Immediate to Register/Memory
Immediate to Register
mod reg r/m
mod 0 0 0 r/m
data
e
1
data
data if w
e
data if w
1
Memory to Accumulator
1 0 1 0 0 0 0 w
1 0 1 0 0 0 1 w
1 0 0 0 1 1 1 0
1 0 0 0 1 1 0 0
addr-low
addr-high
addr-high
Accumulator to Memory
addr-low
Register/Memory to Segment Register
Segment Register to Register/Memory
mod 0 reg r/m
mod 0 reg r/m
e
PUSH
Push:
Register/Memory
Register
1 1 1 1 1 1 1 1
0 1 0 1 0 reg
0 0 0 reg 1 1 0
mod 1 1 0 r/m
Segment Register
e
POP
Pop:
Register/Memory
Register
1 0 0 0 1 1 1 1
0 1 0 1 1 reg
0 0 0 reg 1 1 1
mod 0 0 0 r/m
Segment Register
e
XCHG
Exchange:
Register/Memory with Register
Register with Accumulator
1 0 0 0 0 1 1 w
1 0 0 1 0 reg
mod reg r/m
e
IN
Input from:
Fixed Port
1 1 1 0 0 1 0 w
1 1 1 0 1 1 0 w
port
Variable Port
e
OUT
Output to:
Fixed Port
1 1 1 0 0 1 1 w
1 1 1 0 1 1 1 w
1 1 0 1 0 1 1 1
1 0 0 0 1 1 0 1
1 1 0 0 0 1 0 1
1 1 0 0 0 1 0 0
1 0 0 1 1 1 1 1
1 0 0 1 1 1 1 0
1 0 0 1 1 1 0 0
1 0 0 1 1 1 0 1
port
Variable Port
e
XLAT
Translate Byte to AL
e
LEA
LDS
LES
Load EA to Register
Load Pointer to DS
Load Pointer to ES
mod reg r/m
mod reg r/m
mod reg r/m
e
e
e
LAHF
SAHF
Load AH with Flags
Store AH into Flags
e
e
PUSHF
Push Flags
Pop Flags
e
POPF
26
8088
8086/8088 Instruction Set Summary (Continued)
Mnemonic and
Description
Instruction Code
ARITHMETIC
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
e
ADD
Add:
Reg./Memory with Register to Either
Immediate to Register/Memory
Immediate to Accumulator
0 0 0 0 0 0 d w
1 0 0 0 0 0 s w
0 0 0 0 0 1 0 w
mod reg r/m
mod 0 0 0 r/m
data
e
e
data
data if s:w
01
e
e
data if w
1
1
e
ADC
Add with Carry:
Reg./Memory with Register to Either
Immediate to Register/Memory
Immediate to Accumulator
0 0 0 1 0 0 d w
1 0 0 0 0 0 s w
0 0 0 1 0 1 0 w
mod reg r/m
mod 0 1 0 r/m
data
data
data if s:w
01
data if w
e
INC
Increment:
Register/Memory
Register
1 1 1 1 1 1 1 w
0 1 0 0 0 reg
mod 0 0 0 r/m
e
e
e
AAA
BAA
SUB
ASCII Adjust for Add
Decimal Adjust for Add
Subtract:
0 0 1 1 0 1 1 1
0 0 1 0 0 1 1 1
Reg./Memory and Register to Either
Immediate from Register/Memory
Immediate from Accumulator
0 0 1 0 1 0 d w
1 0 0 0 0 0 s w
0 0 1 0 1 1 0 w
mod reg r/m
mod 1 0 1 r/m
data
e
e
data
data if s:w
01
01
e
e
data if w
1
1
e
SSB
Subtract with Borrow
Reg./Memory and Register to Either
Immediate from Register/Memory
Immediate from Accumulator
0 0 0 1 1 0 d w
1 0 0 0 0 0 s w
0 0 0 1 1 1 w
mod reg r/m
mod 0 1 1 r/m
data
data
data if s:w
data if w
e
DEC
Decrement:
Register/memory
Register
1 1 1 1 1 1 1 w
0 1 0 0 1 reg
1 1 1 1 0 1 1 w
mod 0 0 1 r/m
mod 0 1 1 r/m
e
e
NEG
CMP
Change sign
Compare:
Register/Memory and Register
Immediate with Register/Memory
Immediate with Accumulator
0 0 1 1 1 0 d w
1 0 0 0 0 0 s w
0 0 1 1 1 1 0 w
0 0 1 1 1 1 1 1
0 0 1 0 1 1 1 1
1 1 1 1 0 1 1 w
1 1 1 1 0 1 1 w
1 1 0 1 0 1 0 0
1 1 1 1 0 1 1 w
1 1 1 1 0 1 1 w
1 1 0 1 0 1 0 1
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
mod reg r/m
mod 1 1 1 r/m
data
e
data
data if s:w
01
e
data if w
1
e
e
e
AAS
DAS
MUL
ASCII Adjust for Subtract
Decimal Adjust for Subtract
Multiply (Unsigned)
mod 1 0 0 r/m
mod 1 0 1 r/m
0 0 0 0 1 0 1 0
mod 1 1 0 r/m
mod 1 1 1 r/m
0 0 0 0 1 0 1 0
e
IMUL
AAM
Integer Multiply (Signed)
ASCII Adjust for Multiply
e
e
DIV
Divide (Unsigned)
e
IDIV
AAD
CBW
CWD
Integer Divide (Signed)
e
e
e
ASCII Adjust for Divide
Convert Byte to Word
Convert Word to Double Word
27
8088
8086/8088 Instruction Set Summary (Continued)
Mnemonic and
Description
Instruction Code
LOGIC
7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
1 1 0 1 0 0 v w
7 6 5 4 3 2 1 0
mod 0 1 0 r/m
mod 1 0 0 r/m
mod 1 0 1 r/m
mod 1 1 1 r/m
mod 0 0 0 r/m
mod 0 0 1 r/m
mod 0 1 0 r/m
mod 0 1 1 r/m
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
e
NOT
Invert
e
SHL/SAL
Shift Logical/Arithmetic Left
e
e
e
e
e
e
SHR
SAR
ROL
ROR
RCL
RCR
Shift Logical Right
Shift Arithmetic Right
Rotate Left
Rotate Right
Rotate Through Carry Flag Left
Rotate Through Carry Right
e
AND
And:
Reg./Memory and Register to Either
Immediate to Register/Memory
Immediate to Accumulator
0 0 1 0 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 0 0 1 0 w
mod reg r/m
mod 1 0 0 r/m
data
e
e
data
data if w
1
1
e
e
data if w
1
1
e
TEST
And Function to Flags. No Result:
Register/Memory and Register
1 0 0 0 0 1 0 w
mod reg r/m
Immediate Data and Register/Memory
Immediate Data and Accumulator
1 1 1 1 0 1 1 w
1 0 1 0 1 0 0 w
mod 0 0 0 r/m
data
data
data if w
data if w
e
OR
Or:
Reg./Memory and Register to Either
Immediate to Register/Memory
Immediate to Accumulator
0 0 0 0 1 0 d w
1 0 0 0 0 0 0 w
0 0 0 0 1 1 0 w
mod reg r/m
mod 0 0 1 r/m
data
e
e
data
data if w
1
1
e
e
data if w
1
1
e
XOR
Exclusive or:
Reg./Memory and Register to Either
Immediate to Register/Memory
Immediate to Accumulator
0 0 1 1 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 1 0 1 0 w
mod reg r/m
mod 1 1 0 r/m
data
data
data if w
data if w
STRING MANIPULATION
e
REP
Repeat
1 1 1 1 0 0 1 z
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
e
MOVS
CMPS
SCAS
LODS
STOS
Move Byte/Word
e
e
e
e
Compare Byte/Word
Scan Byte/Word
Load Byte/Wd to AL/AX
Stor Byte/Wd from AL/A
CONTROL TRANSFER
e
CALL
Call:
Direct Within Segment
Indirect Within Segment
Direct Intersegment
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1
1 0 0 1 1 0 1 0
disp-low
mod 0 1 0 r/m
offset-low
disp-high
offset-high
seg-high
seg-low
Indirect Intersegment
1 1 1 1 1 1 1 1
mod 0 1 1 r/m
28
8088
8086/8088 Instruction Set Summary (Continued)
Mnemonic and
Description
Instruction Code
e
JMP
Unconditional Jump:
7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 1 1 1
1 1 1 0 1 0 1 0
7 6 5 4 3 2 1 0
disp-low
7 6 5 4 3 2 1 0
Direct Within Segment
Direct Within Segment-Short
Indirect Within Segment
Direct Intersegment
disp-high
disp
mod 1 0 0 r/m
offset-low
seg-low
offset-high
seg-high
Indirect Intersegment
1 1 1 1 1 1 1 1
mod 1 0 1 r/m
e
RET
Return from CALL:
Within Segment
1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0
1 1 0 0 1 0 1 1
1 1 0 0 1 0 1 0
0 1 1 1 0 1 0 0
0 1 1 1 1 1 0 0
Within Seg Adding Immed to SP
Intersegment
data-low
data-high
data-high
Intersegment Adding Immediate to SP
data-low
disp
e
JE/JZ
Jump on Equal/Zero
e
JL/JNGE
Jump on Less/Not Greater
or Equal
disp
e
JLE/JNG
Jump on Less or Equal/
Not Greater
0 1 1 1 1 1 1 0
0 1 1 1 0 0 1 0
disp
disp
e
e
JB/JNAE
JBE/JNA
Jump on Below/Not Above
or Equal
Jump on Below or Equal/
Not Above
0 1 1 1 0 1 1 0
0 1 1 1 1 0 1 0
0 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0
0 1 1 1 0 1 0 1
disp
disp
disp
disp
disp
e
JP/JPE
Jump on Parity/Parity Even
Jump on Overflow
Jump on Sign
e
e
JO
JS
e
e
JNE/JNZ
JNL/JGE
Jump on Not Equal/Not Zero
Jump on Not Less/Greater
or Equal
0 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1
0 1 1 1 0 0 1 1
disp
disp
disp
e
e
e
e
JNLE/JG
JNB/JAE
JNBE/JA
JNP/JPO
Jump on Not Less or Equal/
Greater
Jump on Not Below/Above
or Equal
Jump on Not Below or
Equal/Above
0 1 1 1 0 1 1 1
0 1 1 1 1 0 1 1
0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 1
1 1 1 0 0 0 1 0
1 1 1 0 0 0 0 1
disp
disp
disp
disp
disp
disp
Jump on Not Par/Par Odd
e
e
JNO
JNS
Jump on Not Overflow
Jump on Not Sign
e
LOOP
Loop CX Times
e
LOOPZ/LOOPE
Loop While Zero/Equal
e
LOOPNZ/LOOPNE
Loop While Not
Zero/Equal
1 1 1 0 0 0 0 0
1 1 1 0 0 0 1 1
disp
disp
e
JCXZ
Jump on CX Zero
Interrupt
e
INT
Type Specified
Type 3
1 1 0 0 1 1 0 1
1 1 0 0 1 1 0 0
1 1 0 0 1 1 1 0
1 1 0 0 1 1 1 1
type
e
e
INTO
IRET
Interrupt on Overflow
Interrupt Return
29
8088
8086/8088 Instruction Set Summary (Continued)
Mnemonic and
Description
Instruction Code
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PROCESSOR CONTROL
e
e
e
e
e
CLC
CMC
STC
CLD
STD
Clear Carry
1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 1
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 0 1 1 x x x
1 1 1 1 0 0 0 0
Complement Carry
Set Carry
Clear Direction
Set Direction
e
CLI
STI
Clear Interrupt
Set Interrupt
e
e
HLT
Halt
e
WAIT
Wait
e
ESC
Escape (to External Device)
mod x x x r/m
e
LOCK
Bus Lock Prefix
REG is assigned according to the following table:
NOTES:
e
e
0)
16-Bit (w
1)
8-Bit (w
Segment
e
e
e
e
e
AL
AX
CX
DS
ES
8-bit accumulator
16-bit accumulator
Count register
Data segment
Extra segment
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
111 DI
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
00 ES
01 CS
10 SS
11 DS
Above/below refers to unsigned value
Greater
e
less positive (more negative) signed values
more positive:
e
Less
e
e
0 then ‘‘from’’ reg
if d
if w
1 then ‘‘to’’ reg; if d
e
e
0 then byte
1 then word instruction; if w
instruction
Instructions which reference the flag register file as a 16-bit
object use the symbol FLAGS to represent the file:
e
e
if mod
if mod
11 then r/m is treated as a REG field
e
00 then DISP
absent
0*, disp-low and disp-high are
e
FLAGS
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
e
e
disp-low sign-extended to
if mod
if mod
01 then DISP
16 bits, disp-high is absent
©
Mnemonics
Intel, 1978
e
e
10 then DISP
disp-high; disp-low
e
e
a
a
a
a
a
a
a
a
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
000 then EA
001 then EA
010 then EA
011 then EA
100 then EA
101 then EA
110 then EA
111 then EA
(BX)
(SI)
(DI)
(SI)
(DI)
DISP
DISP
DISP
DISP
e
e
e
e
e
e
e
e
e
e
e
e
e
e
(BX)
(BP)
(BP)
(SI)
DATA SHEET REVISION REVIEW
The following list represents key differences be-
tween this and the -005 data sheet. Please review
this summary carefully.
a
DISP
DISP
a
a
(DI)
(BP)
(BX)
DISP*
DISP
a
1. The Intel 8088 implementation technology
(HMOS) has been changed to (HMOS-II).
DISP follows 2nd byte of instruction (before data if re-
quired)
e
e
e
then EA disp-high:
*except if mod
disp-low.
00 and r/m
e
if s:w
and
if s:w
01 then 16 bits of immediate data form the oper-
11 then an immediate data byte is sign extended
e
to form the 16-bit operand
e
e
register
e
1; if v 1 then ‘‘count’’ in (CL)
if v
0 then ‘‘count’’
e
x
don’t care
z is used for string primitives for comparison with ZF FLAG
SEGMENT OVERRIDE PREFIX
0 0 1 reg 1 1 0
30
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