D87C251SP16 [INTEL]
Microcontroller, 8-Bit, UVPROM, 8051 CPU, 16MHz, CMOS, CDIP40;
| 型号： | D87C251SP16 |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 8-Bit, UVPROM, 8051 CPU, 16MHz, CMOS, CDIP40 可编程只读存储器 CD 微控制器 |
| 文件： | 总36页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
J Real Time and Programmed Wait State
Bus Operation
J Binary-code Compatible with MCS® 51
J User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
J Pin Compatible with 44-lead PLCC and
J 32 Programmable I/O Lines
40-lead PDIP MCS 51 Sockets
J Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
J Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes, Words,
and Double Words
J Three Flexible 16-bit Timer/counters
J Hardware Watchdog Timer
J Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
J Programmable Counter Array
— High-speed Output
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
J Linear Addressing
J Programmable Serial I/O Port
— Framing Error Detection
J 256-Kbyte Expanded External Code/Data
Memory Space
— Automatic Address Recognition
J ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
J High-performance CHMOS Technology
J Static Standby to 16-MHz Operation
J Complete System Development
Support
J 16-bit Internal Code Fetch
J 64-Kbyte Extended Stack Space
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
J On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
J Package Options (PDIP, PLCC, and
J 8-bit, “Min” 2-clock External Code Fetch
Ceramic DIP)
in
Page Mode
J Fast MCS 251 Instruction Pipeline
This document contains information on products with “[M] [C] '94 '95 C” as the last line of the top marking
diagram. A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-
code compatible with MCS 51 microcontrollers and pin compatible with 40-lead PDIP and 44-lead PLCC
MCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing,
and efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with
8
Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without
ROM/OTPROM/EPROM. A variety of features can be selected by new user-programmable configurations.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of
any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor varia-
tions to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2004
July 2004
Order Number: 272783-004
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
I/O Ports and
Peripheral Signals
System Bus and I/O Ports
P0.7:0
P1.7:0
P2.7:0
P3.7:0
Code
OTPROM/ROM
8 Kbytes
or
Data RAM
512 Bytes
or
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
1024 Bytes
16 Kbytes
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Peripheral
Interface
Bus Interface
Timer/
Counters
Code Bus (16)
Code Address (24)
Interrupt
Handler
Instruction Sequencer
PCA
SRC1 (8)
SRC2 (8)
Serial I/O
Clock
&
Reset
Data
Register
File
Memory
Interface
ALU
Peripherals
DST (16)
®
MCS 251 Microcontroller Core
Clock & Reset
8XC251SA/SB/SP/SQ Microcontroller
A4214-01
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram
2
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Quality and Reliability Handbook (order number
210997).
TEMPERATURE RANGE
With the commercial (standard) temperature option,
the device operates over the temperature range
0°C to +70°C. The express temperature option
provides -40°C to +85°C device operation.
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
change depending on operating conditions and
application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology.
PROLIFERATION OPTIONS
Table 2. Thermal Characteristics
Table 1 lists the proliferation options. See Figure 2
for the 8XC251SA/SB/SP/SQ family nomenclature.
Package Type
44-lead PLCC
θJA
θJC
46°C/W
45°C/W
30.5°C/W
16°C/W
16°C/W
10°C/W
Table 1. Proliferation Options
40-lead PDIP
8XC251SA/SB/SP/SQ
(0 – 16 MHz; 5 V ±10%)
40-lead Ceramic DIP
80C251SB16
80C251SQ16
83C251SA16
83C251SB16
83C251SP16
83C251SQ16
87C251SA16
87C251SB16
87C251SP16
87C251SQ16
CPU-only
PACKAGE OPTIONS
CPU-only
ROM
Table 3 lists the 8XC251SA/SB/SP/SQ packages.
ROM
Table 3. Package Information
ROM
ROM
Pkg.
Definition
44 ld. PLCC
Temperature
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
OTPROM/EPROM
OTPROM/EPROM
OTPROM/EPROM
OTPROM/EPROM
X
X
X
X
X
40 ld. Plastic DIP
40 ld. Ceramic DIP
44 ld. PLCC
40 ld. Plastic DIP
PROCESS INFORMATION
NOTE: To address the fact that many of the pack-
age prefix variables have changed, all
package prefix variables in this document
are now indicated with an "x".
This device is manufactured on a complimentary
high-performance
metal-oxide
semiconductor
(CHMOS) process. Additional process and reliability
information is available in Intel’s Components
3
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
X
XX
8
X
X
XXXXX XX
A2815-01
Figure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature
Table 4. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in
Options
no mark
Commercial operating temperature range (0°C to 70°C) with
Intel standard burn-in.
X
Express operating temperature range (-40°C to 85°C) with
Intel standard burn-in.
Packaging Options
X
X
44-lead Plastic Leaded Chip Carrier (PLCC)
40-lead Plastic Dual In-line Package (PDIP)
40-lead Ceramic Dual In-line Package (Ceramic DIP)
Without ROM/OTPROM/EPROM
ROM
X
Program Memory Options
0
3
7
User programmable OTPROM/EPROM
CHMOS
Process Information
Product Family
C
251
SA
SB
8-bit control architecture
Device Memory Options
1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM
1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without
ROM/OTPROM/EPROM
SP
SQ
512-byte RAM/8-Kbyte ROM/OTPROM/EPROM
512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without
ROM/OTPROM/EPROM
Device Speed
16
External clock frequency
NOTES:
1. To address the fact that many of the package prefix variables have changed, all package prefix vari-
ables in the document are now indicated with an "x".
4
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8XC251SA/SB/SP/SQ Memory Map
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
External Memory (FF:FFF8H–FF:FFFFH are internally decoded for Configuration
Byte data in all ROM/OTPROM/EPROM devices with EA# = 1. For all devices
with EA# = 0, the last 8 bytes of the external address range FF:XFF8H–
FF:XFFFH contain Configuration Byte information).
1, 3, 10
FF:3FFFH
FF:0000H
External memory or for internal ROM/OTPROM/EPROM devices: 16-Kbytes of
internal addresses as determined by the EA# pin (Table 8). Note: 8-Kbyte internal 3, 4, 5
ROM/OTPROM/EPROM array addresses end at FF:1FFFH.
FE:FFFFH
FE:0000H
External Memory
Reserved
3
FD:FFFFH
FD:0000H
6
FC:FFFFH
FC:0000H
Reserved
6
FB:FFFFH
04:0000H
Reserved
6
03:FFFFH
03:0000H
Reserved
6
02:FFFFH
02:0000H
Reserved
6
01:FFFFH
01:0000H
External Memory
3
00:FFFFH
00:E000H
External memory or with EMAP# bit = 0 this address range for 16-Kbyte devices
is redirected to internal ROM/OTPROM/EPROM array region.
5, 7
7
00:DFFFH
00:0420H
External Memory
00:041FH
00:0080H
On-chip RAM (512 byte RAM devices end at 00:021FH
On-chip RAM
7
00:007FH
00:0020H
8
00:001FH
00:0000H
Storage for R0–R7 of Register File
2, 9
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. The special function registers (SFRs) and the register file have separate internal address spaces.
3. Data in this area is accessible by indirect addressing only.
4. Devices can reset into different internal or external starting locations depending on the state of EA#
and configuration register information (see EA#. See also UCONFIG1:0 bit definitions).
5. The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map
into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal
ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte
ROM/OTPROM/EPROM devices.
6. This reserved area returns unspecified values and writes no data.
7. Data is accessible by direct and indirect addressing.
8. Data is accessible by direct, indirect, and bit addressing.
9. Data is accessible by direct, indirect, and register addressing.
10. Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
5
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
8XC251SA/SB/SP/SQ 44-lead PLCC Package
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
7
8
9
39
38
37
36
35
34
33
32
31
30
29
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
10
11
12
13
14
15
16
17
P3.0 / RXD
EA# / V
PP
V
V
CC2
SS2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
View of component as
mounted on PC board
P3.5 / T1
A4205-02
Figure 3. 8XC251SA/SB/SP/SQ 44-lead PLCC Package
6
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
V
P1.0 / T2
P1.1 / T2EX
P1.2 / ECI
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
2
3
P1.3 / CEX0
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
4
5
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
6
7
8
9
V
EA# /
P3.0 / RXD
10
11
12
13
14
15
16
17
18
19
20
PP
P3.1 / TXD
ALE / PROG#
PSEN#
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
A15 / P2.7
A14 / P2.6
A13 / P2.5
A12 / P2.4
A11 / P2.3
A10 / P2.2
A9 / P2.1
View of
component
as mounted
on PC board
P3.5 / T1
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
A8 / P2.0
SS
A4206-03
Figure 4. 8XC251SA/SB/SP/SQ 40-lead PDIP and Ceramic DIP Packages
7
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. PLCC/DIP Lead Assignments Listed by Functional Category
Address & Data
Name PLCC
AD0/P0.0
Input/Output
Name PLCC
DIP
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
8
DIP
1
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
19
9
P1.0/T2
2
3
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
P1.1/T2EX
P1.2/ECI
2
4
3
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
P3.0/RXD
5
4
6
5
7
6
8
7
9
8
11
13
16
17
10
11
14
15
A9/P2.1
P3.1/TXD
A10/P2.2
P3.4/T0
A11/P2.3
P3.5/T1
A12/P2.4
A13/P2.5
Power & Ground
A14/P2.6
Name
VCC
PLCC
44
DIP
A15/P2.7
40
P3.7/RD#/A16
P1.7/CEX4/A17/WCLK
VCC2
12
VSS
22
20
31
VSS1
1
VSS2
23, 34
35
Processor Control
Name PLCC
EA#/VPP
DIP
12
13
31
9
P3.2/INT0#
P3.3/INT1#
EA#/VPP
RST
14
15
35
10
21
20
Bus Control & Status
Name
P3.6/WR#
PLCC
18
DIP
16
P3.7/RD#/A16
ALE/PROG#
PSEN#
19
17
30
29
XTAL1
18
19
33
XTAL2
32
8
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 7. Lead Assignments Arranged by Lead Number
PLCC
1
DIP
Name
PLCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DIP
Name
VSS1
VSS2
2
1
2
P1.0/T2
21
22
23
24
25
26
27
28
29
30
A8/P2.0
A9/P2.1
3
P1.1/T2EX
P1.2/ECI
4
3
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
PSEN#
5
4
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
RST
6
5
7
6
8
7
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
P3.0/RXD
VCC2
ALE/PROG#
VSS2
11
12
13
14
15
16
17
18
19
20
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
31
32
33
34
35
36
37
38
39
40
EA#/VPP
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VCC
P3.5/T1
P3.6/WR#
P3.7/RD#/A16
XTAL2
XTAL1
VSS
9
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SIGNAL DESCRIPTIONS
Table 8. Signal Descriptions
Signal
Name
Alternate
Function
Type
Description
A17
O
18th Address Bit (A17). Output to memory as 18th external address
P1.7/CEX4/
bit (A17) in extended bus applications, depending on the values of bits WCLK
RD0 and RD1 in configuration byte UCONFIG0 (see Table 9). See also
RD# and PSEN#.
A16
O
O
Address Line 16. See RD#.
RD#
A15:8†
AD7:0†
Address Lines. Upper address lines for the external bus.
P2.7:0
P0.7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data lines
for external memory.
ALE
O
Address Latch Enable. ALE signals the start of an external bus cycle PROG#
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
CEX4:0
EA#
I/O
I
Programmable Counter Array (PCA) Input/Output Pins. These are P1.6:3
input signals for the PCA capture mode and output signals for the PCA P1.7/A17/
compare mode and PCA PWM mode.
WAIT#
External Access. Directs program memory accesses to on-chip or off- VPP
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if
the address is within the range of the on-chip
ROM/OTPROM/EPROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip
ROM/OTPROM/EPROM, EA# must be strapped to ground.
ECI
I
I
PCA External Clock Input. External clock input to the 16-bit PCA
P1.2
timer.
INT1:0#
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON P3.3:2
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
PROG#
P0.7:0
I
Programming Pulse. The programming pulse is applied to this pin for ALE
programming the on-chip OTPROM.
I/O
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
T2
P1.1
T2EX
P1.2
ECI
P1.7:3
CEX3:0
CEX4/A17/
/WAIT#/
WCLK
P2.7:0
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
A15:8
† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
10
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. Signal Descriptions (Continued)
Signal
Name
Alternate
Type
Description
Function
P3.0
P3.1
I/O
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
RXD
TXD
P3.3:2
P3.5:4
P3.6
INT1:0#
T1:0
WR#
P3.7
RD#/A16
PSEN#
O
O
Program Store Enable. Read signal output. This output is asserted
for a memory address range that depends on bits RD0 and RD1 in
configuration byte UCONFIG0 (see RD# and Table 9):
—
RD#
Read or 17th Address Bit (A16). Read signal output to external data P3.7/A16
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and
):
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins
are driven to their reset conditions when a voltage greater than VIH1 is
applied, whether or not the oscillator is running. This pin has an inter-
nal pulldown resistor, which allows the device to be reset by connect-
—
ing a capacitor between this pin and VCC
.
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
RXD
T1:0
T2
I/O
I
Receive Serial Data. RXD sends and receives data in serial I/O mode P3.0
0 and receives data in serial I/O modes 1, 2, and 3.
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
P3.5:4
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal P1.0
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
T2EX
TXD
I
Timer 2 External Input. In timer 2 capture mode, a falling edge ini-
tiates a capture of the timer 2 registers. In auto-reload mode, a falling
edge causes the timer 2 registers to be reloaded. In the up-down
counter mode, this signal determines count direction: 1=up, 0=down.
P1.1
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 P3.1
and transmits serial data in serial I/O modes 1, 2, and 3.
VCC
PWR Supply Voltage. Connect this pin to the +5V supply voltage.
—
—
VCC2
PWR Secondary Supply Voltage 2. This supply voltage connection is pro-
vided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB
as a pin-for-pin replacement for the 8XC51FX, VSS2 can be uncon-
nected without loss of compatibility. (Not available on DIP)
VPP
VSS
I
Programming Supply Voltage. The programming supply voltage is
EA#
—
applied to this pin for programming the on-chip OTPROM/EPROM.
GND Circuit Ground. Connect this pin to ground.
† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
11
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. Signal Descriptions (Continued)
Signal
Alternate
Function
Type
Description
Name
VSS1
GND Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground
is recommended. However, when using the 8XC251SA/SB/SP/SQ as
a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected
without loss of compatibility. (Not available on DIP)
—
VSS2
GND Secondary Ground 2. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this pin to
ground is recommended. However, when using the 8XC251SB as a
pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected
without loss of compatibility. (Not available on DIP)
—
WAIT#
I
Real Time Wait State Input. The real time WAIT# input is enabled by P1.6/CEX3
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.
WCLK
O
Wait Clock Output. The real time WCLK output is driven at port 1.7
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with
a period of one-half the ocillator frequency.
P1.7/CEX4/
A17
WR#
O
I
Write. Write signal output to external memory.
P3.6
—
XTAL1
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin. XTAL1
is the clock source for internal timing.
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
—
† The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
Table 9. Memory Signal Selections (RD1:0)
P1.7/CEX/
RD1:0
RD#
PSEN#
WR#
Features
A17
0
0
1
1
0
1
0
1
A17
RD# = A16
Asserted for
Asserted for writes to all
256-Kbyte external
memory
all addresses memory locations
P1.7/CEX4 RD# = A16
P1.7/CEX4 P3.7 only
Asserted for
all addresses memory locations
Asserted for writes to all
128-Kbyte external
memory
Asserted for
all addresses memory locations
Asserted for writes to all
One additional port
pin
P1.7/CEX4 Asserted for
Asserted for
≥ 80:0000H
Asserted for all compati-
ble MCS 51 memory
locations
Compatible with
MCS 51 microcon-
trollers
≤ 7F:FFFFH
12
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS†
Ambient Temperature under Bias:
Commercial ..........................................0°C to +70°C
Express .............................................-40°C to +85°C
Storage Temperature ..............................-65°C to +150°C
NOTICE: This document contains informa-
tion on products in the design phase of
development. Do not finalize a design with
this information. Revised information will be
published when the product is available.
Verify with your local Intel Sales Office that
you have the latest datasheet before finaliz-
ing a design.
Voltage on EA#/V Pin to VSS.................. 0 V to +13.0 V
PP
Voltage on Any other Pin to VSS .............. -0.5 V to +6.5 V
IOL per I/O Pin..........................................................15 mA
Power Dissipation ................................................... 1.5 W
NOTE:
†
WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the
“Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Maximum power dissipation is based on
package heat-transfer limitations, not
device power consumption.
OPERATING CONDITIONS†
TA (Ambient Temperature Under Bias):
Commercial ..........................................0°C to +70°C
Express .............................................-40°C to +85°C
VCC (Digital Supply Voltage) ...................... 4.5 V to 5.5 V
VSS .............................................................................. 0 V
13
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated.
Table 10. DC Characteristics at VCC = 4.5 – 5.5 V
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VIL
Input Low Voltage
(except EA#)
-0.5
0.2VCC – 0.1
V
VIL1
VIH
Input Low Voltage
(EA#)
0
0.2VCC – 0.3
VCC + 0.5
V
V
V
V
Input High Voltage
(except XTAL1, RST)
0.2VCC + 0.9
0.7VCC
VIH1
VOL
Input High Voltage
(XTAL1, RST)
VCC + 0.5
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
(Note 1, Note 2)
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V
V
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
(Note 1, Note 2)
VOH
Output High Voltage
(Port 1, 2, 3, ALE,
PSEN#)
VCC – 0.3
VCC – 0.7
VCC – 1.5
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
(Note 3)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
ports 1–3
26 mA
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to
sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from high to low. In applications where capacitive load-
ing exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qual-
ify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
14
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 10. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VOH1
Output High Voltage
(Port 0 in External
Address)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
Voh2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
IOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
IIL
ILI
ITL
Logical 0 Input Cur-
rent (Port 1, 2, 3)
-50
µA
µA
µA
VIN = 0.45 V
0.45 < VIN < VCC
VIN = 2.0 V
Input Leakage Cur-
rent (Port 0)
+/-10
-650
Logical 1-to-0 Transi-
tion Current (Port 1,
2, 3)
Rrst
Cio
RST Pulldown Resis-
tor
40
225
kΩ
Pin Capacitance
10
pF
FOSC = 16 MHz
TA = 25 °C
(Note 4)
Ipd
Powerdown Current
Idle Mode Current
Operating Current
10
< 20
7
µA
mA
mA
(Note 4)
Idl
5
FOSC = 16 MHz
FOSC = 16 MHz
(Note 4)
ICC
20
45
(Note 4)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
ports 1–3
26 mA
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to
sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from high to low. In applications where capacitive load-
ing exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qual-
ify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
15
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
VCC
IPD
VCC
P0
VCC
EA#
RST
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
(NC)
XTAL2
XTAL1
VSS
All other 8XC251SA/SB/SP/SQ pins are unconnected.
A4208-01
Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V
16
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
A.C. Characteristics
Table 11 lists AC timing parameters for the
8XC251SA/SB/SP/SQ with no wait states. External
wait states can be added by extending
PSEN#/RD#/WR# and/or by extending ALE. In the
table, Notes 3 and 5 mark parameters affected by an
ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.
Figures 6–11 show the bus cycles with the timing
parameters.
Table 11. AC Characteristics (Capacitive Loading = 50 pF)
@ Max Fosc (1)
Min Max
N/A N/A
N/A
Fosc Variable
Min Max
16
Symbol
Parameter
Units
FOSC
Tosc
XTAL1 Frequency
1/FOSC
0
MHz
ns
N/A
83.3
62.5
@ 12 MHz
@ 16 MHz
Tlhll
Tavll
Tllax
ALE Pulse Width
@ 12 MHz
ns
73.3
52.5
(3)
(1+2M)
@ 16 MHz
T
OSC – 10
Address Valid to ALE Low
@ 12 MHz
ns
63.3
42.5
(3)
(1+2M)
TOSC – 20
@ 16 MHz
Address Hold after ALE Low
@ 12 MHz
ns
10
10
10
@ 16 MHz
TRLRH (2) RD# or PSEN# Pulse Width
ns
156.6
115
@ 12 MHz
@ 16 MHz
(4)
2(1+N)
T
OSC – 10
Twlwh
WR# Pulse Width
@ 12 MHz
ns
156.6
115
(4)
2(1+N)
TOSC – 10
@ 16 MHz
Tllrl (2)
ALE Low to RD# or PSEN# Low
@ 12 MHz
ns
63.3
42.5
TOSC – 20
@ 16 MHz
Tlhax
ALE High to Address Hold
@ 12 MHz
ns
83.3
62.5
(3)
(1+2M)
TOSC
@ 16 MHz
NOTES:
1. 16 MHz.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M=Number of wait states (0 or 1) for ALE.
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#
5. “Typical” specifications are untested and not guaranteed.
17
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Capacitive Loading = 50 pF) (Continued)
@ Max Fosc (1)
Fosc Variable
Symbol
Parameter
Units
Min
Max
Min
Max
TRLDV (2) RD#/PSEN# Low to valid Data/Instruction In
ns
(4)
116.6
75
@ 12 MHz
@ 16 MHz
2(1+N)
Tosc – 50
TRHDX (2) Data/Instruction Hold Time. Occurs after
RD#/PSEN# are exerted to VOH
0
0
ns
ns
TRLAZ (2) RD#/PSEN# Low to Address Float
Typ.=0 2
(5)
Typ. = 0
(5)
2
Trhdz1
Instruction Float after RD#/PSEN# High
ns
ns
10
@ 12 MHz
@ 16 MHz
10
10
Trhdz2
Data Float after RD#/PSEN# High
@ 12 MHz
176.6
135
2Tosc
+10
@ 16 MHz
Trhlh1
TRHLH2
TWHLH
Tavdv1
RD#/PSEN# High to ALE High (Instruction)
ns
ns
ns
10
10
@ 12 MHz
@ 16 MHz
10
RD#/PSEN# High to ALE High (Data)
@ 12 MHz
176.6
135
2Tosc + 10
2Tosc + 10
@ 16 MHz
WR# High to ALE High
@ 12 MHz
176.6
135
@ 16 MHz
Address (P0) Valid to Valid Data/Instruction In
ns
263.2
180
@ 12 MHz
@ 16 MHz
(3)
4(1+M/2)
TOSC – 70
Tavdv2
Address (P2) Valid to Valid Data/Instruction In
ns
278.2
195
@ 12 MHz
@ 16 MHz
(3)
4(1+M/2)
T
OSC – 55
TAVDV3
Address (P0) Valid to Valid Instruction In
ns
116.6
75
@ 12 MHz
@ 16 MHz
2TOSC
– 50
NOTES:
1. 16 MHz.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M=Number of wait states (0 or 1) for ALE.
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#
5. “Typical” specifications are untested and not guaranteed.
18
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Capacitive Loading = 50 pF) (Continued)
@ Max Fosc (1)
Fosc Variable
Symbol
Parameter
Units
Min
Max
Min
Max
Tavrl (2)
Address Valid to RD#/PSEN# Low
@ 12 MHz
ns
146.6
105
(3)
2(1+M)
TOSC – 20
@ 16 MHz
Tavwl1
Address (P0) Valid to WR# Low
@ 12 MHz
ns
156.6
115
(3)
2(1+M)
TOSC – 10
@ 16 MHz
TAVWL2
Address (P2) Valid to WR# Low
@ 12 MHz
ns
166.6
125
(3)
2(1+M)
TOSC
@ 16 MHz
TWHQX
Data Hold after WR# High
@ 12 MHz
ns
63.3
42.5
TOSC – 20
@ 16 MHz
TQVWH
Data Valid to WR# High
@ 12 MHz
ns
143.6
102
(4)
2(1+N)
TOSC – 23
@ 16 MHz
TWHAX
WR# High to Address Hold
@ 12 MHz
ns
146.6
105
2TOSC – 20
@ 16 MHz
NOTES:
1. 16 MHz.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M=Number of wait states (0 or 1) for ALE.
4. In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#
5. “Typical” specifications are untested and not guaranteed.
19
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
SYSTEM BUS TIMINGS
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
RLRH
†
T
T
RHLH2
LLRL
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ2
†
T
AVLL
T
LLAX
T
RHDX
D7:0
P0
A7:0
†
Data In
T
AVRL
†
T
AVDV1
†
T
AVDV2
A15:8/A16/A17
P2/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4210-01
Figure 6. External Read Data Bus Cycle in Nonpage Mode
20
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
RLRH
T
RHLH1
†
T
LLRL
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ1
†
T
T
LLAX
AVLL
T
RHDX
P0
A7:0
D7:0
†
Instruction In
T
AVRL
†
T
T
AVDV1
†
AVDV2
P2/A16/A17
A15:8/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4211-01
Figure 7. External Instruction Bus Cycle in Nonpage Mode
21
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
†
ALE
T
LHLL
†
T
WLWH
T
WHLH
WR#
†
T
LHAX
†
T
QVWH
T
T
AVLL
LLAX
T
WHQX
P0
A7:0
D7:0
†
Data Out
T
AVWL1
†
T
T
AVWL2
WHAX
P2/A16/A17
A15:8/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4179-01
Figure 8. External Write Data Bus Cycle in Nonpage Mode
22
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
RLRH
†
T
T
RHLH2
LLRL
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ2
†
T
AVLL
T
LLAX
T
RHDX
D7:0
P2
A15:8
†
Data In
T
AVRL
†
T
AVDV1
†
T
AVDV2
A7:0/A16/A17
P0/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4212-01
Figure 9. External Read Data Bus Cycle in Page Mode
23
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
†
ALE
T
LHLL
†
T
WLWH
T
WHLH
WR#
†
T
LHAX
†
T
T
QVWH
AVLL
T
LLAX
T
WHQX
P2
A15:8
D7:0
†
Data Out
T
AVWL1
†
T
T
AVWL2
WHAX
P0/A16/A17
A7:0/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4182-01
Figure 10. External Write Data Bus Cycle in Page Mode
24
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
LLRL
†††
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
T
RHDZ1
T
LHAX
†
T
AVLL
T
RHDX
LLAX
P2
A15:8
D7:0
D7:0
†
Instruction In
Instruction In
T
AVRL
†
T
T
AVDV3
AVDV1
†
T
AVDV2
P0/A16/A17
A7:0/A16/A17
A7:0/A16/A17
††
††
Page Miss
Page Hit
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2TOSC); a page miss requires two states (4TOSC).
††
†††
During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
A4213-02
Figure 11. External Instruction Bus Cycle in Page Mode
25
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
AC Characteristics — Serial Port, Shift Register Mode
Table 12. Serial Port Timing — Shift Register Mode
Symbol
TXLXL
Parameter
Min
12TOSC
Max
Units
ns
Serial Port Clock Cycle Time
TQVSH
TXHQX
TXHDX
TXHDV
Output Data Setup to Clock Rising Edge
Output Data hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
10TOSC – 133
2TOSC – 117
0
ns
ns
ns
10TOSC – 133
ns
T
XLXL
TXD
T
XHQX
†
†
Set TI
T
QVXH
RXD
(Out)
0
1
2
7
4
6
3
5
†
T
AV
T
T
XHDV
XHDX
Set RI
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 12. Serial Port Waveform — Shift Register Mode
26
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
External Clock Drive
Table 13. External Clock Drive
Symbol
1/TCLCL
TCHCX
Parameter
Oscillator Frequency (FOSC
High Time
Min
Max
Units
MHz
ns
)
16
20
20
TCLCX
Low Time
ns
TCLCH
Rise Time
10
10
ns
TCHCL
Fall Time
ns
TCLCH
TCHCX
VCC – 0.5
0.7 VCC
TCLCX
0.2 VCC – 0.1
0.45 V
TCHCL
TCLCL
A4119-01
Figure 13. External Clock Drive Waveforms
Outputs
Inputs
VCC – 0.5
0.45 V
0.2 VCC + 0.9
0.2 VCC – 0.1
VIH MIN
VOL MAX
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 14. AC Testing Input, Output Waveforms
27
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
VLOAD + 0.1 V
VLOAD
VOH – 0.1 V
Timing Reference
Points
VOL + 0.1 V
VLOAD – 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 20 mA.
A4117-01
Figure 15. Float Waveforms
VCC
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
VCC
P3
P1
A0 - A7
RST
Address
(16 Bits)
Data
(8 Bits)
P2
A8 - A15
EA#/V
Programming
Signals
pp
XTAL1
ALE/PROG#
PSEN#
4 MHz
to
6 MHz
XTAL2
VSS
Program/Verify Mode
(8 Bits)
P0
A4209-01
Figure 16. Setup for Programming and Verifying Nonvolatile Memory
28
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
Information in Figures 17 and 18 define the
configuration bits. Figure 19 shows the
waveforms for the programming and verification
cycles, and Table 15 lists the timing specifica-
The 87C251SA/SB/SP/SQ has several areas of
nonvolatile memory that can be programmed
and/or verified: on-chip code memory (16
Kbytes), lock bits (3 bits), encryption array (128
bytes), and signature bytes (3 bytes). The
8XC251SA/SB/SP/SQ User’s Manual (Order
Number: 272795) provides procedures for
programming and verifying the nonvolatile
memory.
tions.
The
signature
bytes
of
the
83C251SA/SB/SP/SQ ROM versions and the
87C251SA/SB/SP/SQ OTP versions are factory
programmed. Table 16 lists the addresses and
the contents of the signature bytes.
Factory-programmed ROM and OTPROM
versions of 8XC251SA/SB/SP/SQ use configu-
ration byte information supplied in a separate
hexadecimal disk file. 8XC251SA/SB/SP/SQ
devices without internal ROM/OTPROM/EPROM
arrays fetch configuration byte information from
external application memory based on an internal
address range of FF:FFF9:8H.
Figure 16 shows the setup for programming
and/or verifying the nonvolatile memory. Table 14
lists the programming and verification operations
and indicates which operations apply to the
different versions of the 87C251SA/SB/SP/SQ. It
also specifies the signals on the programming
input
(PROG#)
and
the
ports.
The
ROM/OTPROM/EPROM mode (port 0) specifies
the operation (program or verify) and the base
address of the memory area. The addresses
(ports 1 and 3) are relative to the base address.
NOTE:
(On-chip
memory
for
an
8-Kbyte
The VPP source in Figure 16 must be well
ROM/OTPROM/EPROM device is located at
address range FF:0000H–FF:1FFFH. On-chip
memory for a 16-Kbyte ROM/OTPROM/EPROM
device is located at address range FF:0000H–
regulated and free of glitches. The voltage
on the VPP pin must not exceed the
specified maximum, even under transient
conditions.
FF:3FFFH.
The
other
areas
of
the
ROM/OTPROM/EPROM are outside the memory
address space and are accessible only during
programming and verification.)
29
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 14. Programming and Verification Modes
8XC251SA/S
Addresses
B/SP/SQ
X = 7 X = 3
Y
Mode
PROG#
P0
P2
Notes
P1 (high), P3 (low)
Program on-chip code
memory
5 Pulses
High
68H Data
28H Data
0000H–3FFFH (16K)
000H-1FFFH (8K)
1
Verify on-chip code
memory
Y
Y
0000H–3FFFH (16K)
0000H-1FFFH (8K)
Program configuration
bytes
2
2
Verify configuration
bytes
Program lock bits
Verify lock bits
Y
Y
Y
25 Pulses 6BH
High 2BH Data
25 Pulses 6CH Data
XX
0001H–0003H
0000H
1, 3
4
Y
Y
Program encryption
array
0000H–007FH
1
Verify signature bytes
Y
High
29H Data 0030H, 0031H, 0060H
NOTES:
1. The PROG# pulse waveform is shown in Figure 19.
2. Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use config-
uration byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ
devices without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from
external application memory based on an internal address range of FF:FFF9:8H.
3. When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with
the address as follows: LB3 - 0003H, LB2 - 0002H, LB1 - 0001H
4. The three lock bits are verified in a single operation. The states of the lock bits appear simulta-
neously at port 2 as follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High = programmed.
30
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Address FF:FFF8H
UCONFIG0
7
0
UCON
WSA1#
WSA0#
XALE#
RD1
RD0
PAGE#
SRC
Bit
Number
Bit
Mnemonic
Function
7
UCON
Configuration byte location selector:
Clearing this bit causes the device to fetch configuration information
from on-chip memory. Setting this bit causes the device to locate
configuration information based upon the state of EA# during reset
(EA# = VCC = on-chip; EA# = VSS = off-chip).
6:5
WSA1#,
WSA0#
Wait State Select (for all pages except 01H). WSA0# is identical to
the WSA bit defined in the 8XC251SB A-step:
(see Note)
WSA1#WSA0# Description
1
1
0
0
1
0
1
0
No wait states (01: page controlled by CONFIG1)
Insert 1 wait state for all pages except the 01: page
Insert 2 wait states for all pages except the 01: page
Insert 3 wait states for all pages except the 01: page
4
XALE#
Extend Ale:
If this bit is set, the time of the ALE pulse is TOSC. Clearing this bit
extends the time of the ALE pulse from TOSC to 3TOSC, which adds
one external wait state.
3:2
RD1, RD0
RD# and PSEN# function select:
RD1RD0RD# RangeP1.7/CEX4/A17 PSEN# Range
0
0
1
1
0 RD# = A16A17onlyAll Addresses
1 RD# = A16P1.7/CEX4All Addresses
0 P3.7 onlyP1.7/CEX4All Addresses
1 ≤ 7F:FFFFHP1.7/CEX4≥ 80:0000H
1
0
PAGE#
SRC
Page Mode Select:
Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0).
Set this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0
(compatible with MCS 51 microcontrollers)).
Source Mode/Binary Mode Select:
Set this bit for source mode. Clear this bit for binary mode (binary-
code compatible with MCS 51 microcontrollers).
Figure 17. Configuration Byte 0
NOTE:
Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use configura-
tion byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices
without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external
application memory based on an internal address range of FF:FFF9:8H.
31
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
.
Address FF:FFF9H
UCONFIG1
7
0
—
—
—
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit
Bit
Mnemonic
Function
Number
7:5
4
—
Reserved; set these bits when writing to UCONFIG1.
Interrupt Mode:
INTR
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the
PC register and the PSW1 register). If this byte is clear, interrupts push 2
bytes onto the stack (the 2 lower bytes of the PC register).
3
WSB
Wait State B. Only use this bit for A-step compatibility:
Clear this bit to generate one external wait state for memory region 01:.
Set this bit for no wait states for region 01:.
2:1
WSB1#,
WSB0#
Wait States (01:XXXXH page only)
WSB1# WSB0# Description
11 No wait states
10 Insert 1 wait state for the 01: page
01 Insert 2 wait states for the 01: page
00 Insert 3 wait states for the 01: page
0
EMAP#
EPROM MAP:
Clearing this bit maps the upper 8 Kbytes of on-chip code memory
(FF:2000H–FF:3FFFH) to 00:E000H–00:FFFFH. If this bit is set, the
upper 8 Kbytes of on-chip code memory are mapped only to FF:2000H–
FF:3FFFH. If this bit is set mapping does not occur.
Figure 18. Configuration Byte 1
NOTE:
Factory-programmed ROM and OTPROM versions of 8XC251SA/SB/SP/SQ use configuration byte
information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices without
internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external application
memory based on an internal address range of FF:FFF9:8H.
32
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Programming Cycle
Verification Cycle
P1, P3
P2
Address (16 Bits)
Address
T
AVQV
Data In (8 Bits)
Data Out
T
T
GHDX
DVGL
T
T
GHAX
AVGL
T
GHGL
PROG#
1
2
3
4
5
T
GHSL
T
GLGH
T
SHGL
12.75V
EA#/V
PP
5V
T
T
ELQV
EHQZ
T
EHSH
P0
Mode (8 Bits)
Mode
A4128-01
Figure 19. Timing for Programming and Verification of Nonvolatile Memory
33
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 15. Nonvolatile Memory Programming and Verification Characteristics at
TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V
Symbol
Vpp
Definition
Min
Max
13.5
75
Units
D.C. Volts
mA
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
12.5
Ipp
Fosc
TAVGL
TGHAX
TDVGL
TGHDX
TEHSH
TSHGL
TGHSL
TGLGH
TAVQV
TELQV
TEHQZ
TGHGL
4.0
48TOSC
48TOSC
48TOSC
48TOSC
48TOSC
10
6.0
MHz
Address Setup to PROG# Low
Address Hold after PROG#
Data Setup to PROG# Low
Data Hold after PROG#
ENABLE High to VPP
VPP Setup to PROG# Low
VPP Hold after PROG#
µs
µs
µs
10
PROG# Width
90
110
Address to Data Valid
48TOSC
48TOSC
48TOSC
ENABLE Low to Data Valid
Data Float after ENABLE
PROG# High to PROG# Low
0
10
µs
NOTE: Notation for timing parameters:
A = Address
Q = Data out
D = Data
E = Enable
V = Valid
G = PROG#
X = No Longer Valid
H = High
Z = Floating
L = Low
S = Supply (VPP
)
Table 16. Contents of the Signature Bytes
ADDRESS
CONTENTS
DEVICE TYPE
Indicates Intel Devices
30H
31H
60H
60H
60H
60H
60H
60H
60H
60H
61H
89H
40H
7AH
7BH
4AH
4BH
FAH
FBH
CAH
CBH
55H
Indicates MCS251 core product
Indicates 83C251SA device
Indicates 83C251SB device
Indicates 83C251SP device
Indicates 83C251SQ device
Indicates 87C251SA device
Indicates 87C251SB device
Indicates 87C251SP device
Indicates 87C251SQ device
Indicates 8XC251SA/SB/SP/SQ B-step products
34
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Revision History
The following changes appear in the -004 datasheet:
1. To address the fact that many of the package prefix variables have changed, all package prefix variables
in the document are now indicated with an "x".
The (-003) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with “[M] [C] '94
'95 C” as the last line of the topside marking. This datasheet replaces earlier product information. The
following changes appear in the -003 datasheet:
1. UCONFIG0.7 (UCON) is now defined.
2. Real time wait state operation is described in the datasheet.
3. Memory map reserved locations are newly defined.
The (-002) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with “[M] [C] '94
'95 B” as the last line of the topside marking. This datasheet replaces earlier product information. The
following changes appear in the -002 datasheet:
1. A corrected PDIP diagram appears on page 7.
2. A corrected formula to calculate TLHLL is described on page 17.
3. The RD#/PSEN# waveform is changed in Figure 11 on page 25.
35
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