DD28F032SA [INTEL]
32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY; 32兆位（ 2兆×16 ， 4 MBIT ×8 ） FlashFile记忆
| 型号： | DD28F032SA |
| 厂家： | 
INTEL |
| 描述： | 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile MEMORY |
| 文件： | 总49页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
DD28F032SA
32-MBIT (2 MBIT X 16, 4 MBIT X 8)
FlashFile™ MEMORY
User-Selectable 3.3V or 5V VCC
Revolutionary Architecture
100% Backwards-Compatible with
Intel 28F016SA
User-Configurable x8 or x16 Operation
70 ns Maximum Access Time
Pipelined Command Execution
Program during Erase
28.6 MB/sec Burst Write Transfer Rate
1 Million Typical Erase Cycles per Block
2 mA Typical ICC in Static Mode
2 µA Typical Deep Power-Down
56-Lead, 1.2 x 14 x 20 mm Advanced
Dual Die TSOP Package Technology
State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
64 Independently Lockable Blocks
Intel’s DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and communication products. With innovative
capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal
choice for designing embedded mass storage flash memory systems.
The DD28F032SA is the result of highly-advanced packaging innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).
The DD28F032SA is the highest density, highest performance nonvolatile read/program solution for solid-
state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA
16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read
performance and selective block locking provide a highly flexible memory component suitable for high-density
memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The DD28F032SA’s dual read voltage
enables the design of memory cards which can be read/written in 3.3V and 5.0V systems interchangeably. Its
x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.
December 1996
Order Number: 290490-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
E
DD28F032SA
CONTENTS
PAGE
PAGE
1.0 PRODUCT OVERVIEW................................... 5
6.0 ELECTRICAL SPECIFICATIONS..................19
6.1 Absolute Maximum Ratings........................19
6.2 Capacitance...............................................20
6.3 Timing Nomenclature.................................21
6.4 DC Characteristics (VCC = 3.3V ± 0.3V).....24
6.5 DC Characteristics (VCC = 5.0V ± 0.5V)....26
2.0 DEVICE PINOUT............................................. 6
2.1 Lead Descriptions........................................ 8
3.0 MODES OF OPERATION ............................. 10
4.0 MEMORY MAPS........................................... 11
6.6 AC Characteristics—Read Only
Operations ...................................................28
4.1 Extended Status Registers Memory Map... 12
6.7 Power-Up and Reset Timings.....................32
5.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS................ 13
6.8 AC Characteristics for WE#—Controlled
Command Write Operations.........................33
5.1 Bus Operations for Word-Wide Mode
(BYTE# = VIH).............................................. 13
6.9 AC Characteristics for CEX#—Controlled
Write Operations ..........................................37
5.2 Bus Operations for Byte-Wide Mode
(BYTE# = VIL) .............................................. 13
6.10 AC Characteristics for Page Buffer Write
Operations ...................................................41
5.3 28F008SA Compatible Mode Command
Bus Definitions............................................. 14
6.11 Erase and Word/Byte Program
Performance, Cycling Performance and
Suspend Latency .........................................44
5.4 28F016SA-Performance Enhancement
Command Bus Definitions............................ 15
5.5 Compatible Status Register ....................... 16
5.6 Global Status Register............................... 17
5.7 Block Status Register ................................ 18
7.0 DERATING CURVES ....................................45
8.0 MECHANICAL SPECIFICATIONS................47
APPENDIX A: Device Nomenclature/
Ordering Information .....................................48
APPENDIX B: Additional Information...............49
3
DD28F032SA
Number
E
REVISION HISTORY
Description
-001
-002
-003
—Original Version
—Never Published
—Full Datasheet with Specifications
—CE0#, CE1# control 28F016SA No. 1
—CE0#, CE2# control 28F016SA No. 2
-004
—DC Characteristics (3.3V VCC): ICCR1 (TTL): BYTE# = VIL or VIH
—Full Chip Erase Time (3.3V VCC) = 51.2 sec typ
—Full Chip Erase Time (5.0V VCC) = 38.4 sec typ
—Section 6.7: Added specifications tPHEL3, tPHEL5
—TSOP dimension A1 = 0.05 mm (min)
—Revised Product Status to Preliminary
—tWHGL (3.3V) = 120 ns
—Minor cosmetic changes
-005
—Updated AC/DC parameters
4
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DD28F032SA
These new commands and features include:
1.0 PRODUCT OVERVIEW
•
•
•
•
•
Page Buffer Writes to Flash
The DD28F032SA is a high-performance 32-Mbit
(33,554,432-bit) block erasable nonvolatile random
access memory organized as either 2 Mword x 16,
or 4 Mbyte x 8. The DD28F032SA is built using
two 28F016SA chips encapsulated in a single
56- lead TSOP Type I package. The DD28F032SA
includes sixty-four 64-KB (65,536) blocks or sixty-
four 32-KW (32,768) blocks.
Command Queueing Capability
Automatic Data Programs during Erase
Software Locking of Memory Blocks
Two-Byte Successive Programs in 8-bit
Systems
•
Erase All Unlocked Blocks
The DD28F032SA architecture allows operations
to be performed on a single, 16-Mbit chip at a
time.
These operations can only be performed on one
16-Mbit device at a time. If the WSM is busy
performing an operation, the system should not
attempt to select the other device.
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease of use.
Writing of memory data is performed in either byte
or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 64 blocks in typically
0.6 sec, independent of the other blocks, which is
a 65% improvement over the 28F008SA.
Among the significant enhancements on the
DD28F032SA:
•
•
•
3.3V Low Power Capability
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve typically
1 million block erase cycles by providing wear-
leveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems. Additionally, wear leveling
of block erase cycles can be used to minimize the
program/erase performance differences across
blocks.
Improved Program Performance
Dedicated Block Program/Erase Protection
A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/program
operation.
The DD28F032SA will be available in a 56-lead,
1.2 mm thick, 14 mm x 20 mm Dual Die TSOP
Type I package. This form factor and pinout allow
for very high board layout densities. The
DD28F032SA is pinout and footprint compatible
with the 28F016SA.
The DD28F032SA incorporates two Page Buffers
of 256 bytes (128 words) on each 28F016SA to
allow page data programs. This feature can
improve a system program performance by up to
4.8 times over previous flash memory devices.
Two Command User Interfaces (CUI) serve as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
All operations are started by a sequence of
command writes to the device. Three Status
Registers (described in detail later) and a RY/BY#
output pin provide information on the progress of
the requested operation.
Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write command sequence to
the CUI in the same way as the 28F016SA
16-Mbit FlashFile memory.
The DD28F032SA allows queueing of the next
operation while the memory executes the current
operation. This eliminates system overhead when
writing several bytes in a row to the array or
erasing several blocks at the same time. The
DD28F032SA can also perform program
operations to one block of memory while
performing erase of another block. However,
simultaneous program and/or erase operations are
not allowed on both 28F016SA devices. See
Modes of Operation, Section 3.0.
A super-set of commands has been added to the
basic 28F008SA (8-Mbit FlashFile memory)
command-set to achieve higher program
performance and provide additional capabilities.
5
DD28F032SA
E
The DD28F032SA provides user-selectable block
locking to protect code or data such as device
drivers, PCMCIA card information, ROM-
executable O/S or application code. Each block
has an associated nonvolatile lock-bit which
determines the lock status of the block. In
addition, the DD28F032SA has a master Write
Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits
are set.
The BYTE# pin allows either x8 or x16
read/programs to the DD28F032SA. BYTE# at
logic low selects 8-bit mode with address A0
selecting between low byte and high byte. On the
other hand, BYTE# at logic high enables 16-bit
operation with address A1 becoming the lowest
order address and address A0 is not used (don’t
care). A device block diagram is shown in Figure
1.
The DD28F032SA is specified for a maximum
access time of 70 ns (tACC) at 5.0V operation
(4.75V to 5.25V) over the commercial temperature
range (0°C to +70°C). A corresponding maximum
access time of 150 ns at 3.3V (3.0V to 3.6V and
0°C to +70°C) is achieved for reduced power
consumption applications.
The DD28F032SA contains three types of Status
Registers to accomplish various functions:
•
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory’s Status Register. This register, when
used alone, provides a straightforward upgrade
The DD28F032SA incorporates an Automatic
Power Saving (APS) feature which substantially
reduces the active current when the device is in
static mode of operation (addresses not
switching).
capability to the DD28F032SA from
28F008SA-based design.
a
•
•
A Global Status Register (GSR) which informs
the system of Command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin is driven low. This mode provides additional
write protection by acting as a device reset pin
during power transitions. In the deep power-down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.
64 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 4
and 5.
A CMOS standby mode of operation is enabled
when either CE0#, or both CE1# and CE2#,
transition high and RP# stays high with all input
control pins at CMOS levels.
The DD28F032SA incorporates an open drain
RY/BY# output pin. This feature allows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array. Other configurations of the RY/BY# pin are
enabled via special CUI commands and are
described in detail in the 16-Mbit Flash Product
Family User’s Manual.
2.0 DEVICE PINOUT
The DD28F032SA Standard 56-Lead Dual Die
TSOP Type I pinout configuration is shown in
Figure 2.
The DD28F032SA also incorporates three chip-
enable input pins, CE0#, CE1# and CE2#. The
active low combination of CE0# and CE1# controls
the first 28F016SA. The active low combination of
CE0# and CE2# controls the second 28F016SA.
6
E
DD28F032SA
DQ
DQ
8-15
0-7
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
3/5#
I/O Logic
BYTE#
Data
Queue
Registers
ID
Register
CSR
Page
Buffers
CE0#
CE1#
OE#
ESRs
WE#
Data
Comparator
WP#
RP#
Input
Buffer
Y
Y Gating/Sensing
Decoder
RY/BY#
V
Address
Queue
Latches
X
PP
Program/Erase
Voltage Switch
Decoder
3/5#
V
CC
Address
Counter
GND
0490_01
Figure 1. Block Diagram of 16-Mbit Devices in DD28F032SA
Architectural Evolution Includes Page Buffers, Queue Registers and Extended Registers
7
DD28F032SA
E
2.1 Lead Descriptions
Symbol
A0
Type
Name and Function
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is
high).
A1–A15
INPUT
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A
6-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512 columns. These
addresses are latched during data programs.
A16–A20
DQ0–DQ7
BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks in each of
the two 28F016SAs. These addresses are latched during data programs,
block erase and lock block operations.
INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
DQ8–DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CE0#
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. CE0#/CE1# enable/disable the first
28F016SA (16 Mbit No. 1) while CE0#/CE2# enable/disable the second
28F016SA (16 Mbit No. 2). CE0# active low enables chip operation while
CE1# or CE2# select between the first and second device, respectively
CE1# and CE2# must not be active low simultaneously. Reference Table
3.0.
CEX# =
CE1# or
CE2#
RP#
OE#
INPUT
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
INPUT
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CE # overrides OE#, and OE# overrides WE#.
x
WE#
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
RY/BY#
OPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it
OUTPUT
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE0#/CE1#/CE2# are high), except if a
RY/BY#
Pin Disable command is issued.
8
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DD28F032SA
2.1 Lead Descriptions (Continued)
Symbol
Type
Name and Function
WP#
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile
lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent data programs or block erases. When WP# is high, all blocks
can be written or erased regardless of the state of the lock-bits. The WP#
input buffer is disabled when RP# transitions low (deep power-down
mode).
BYTE#
INPUT
INPUT
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then
input or output on DQ0-7, and DQ8-15 float. Address A0 selects between
the high and low byte. BYTE# high places the device in x16 mode, and
turns off the A0 input buffer. Address A1 then becomes the lowest order
address.
3/5#
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V
operation. 3/5# low configures internal circuits for 5.0V operation.
NOTES:
Reading the array with 3/5# high in a 5.0V system could damage the
device.
There is a significant delay from 3/5# switching to valid data.
VPP
VCC
GND
NC
SUPPLY
SUPPLY
SUPPLY
ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks
or writing words/bytes/pages into the flash array.
DEVICE POWER SUPPLY (3.3V ± 0.3V, 5.0V ± 0.5V, 5.0V ± 0.25V):
Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
Lead may be driven or left floating.
9
DD28F032SA
E
28F016SV 28F016SA
28F016SA 28F016SV
3/5#
3/5#
CE1#
56
1
2
3
4
5
6
7
WP#
WE#
OE#
3/5#
CE1#
WP#
WE#
OE#
WP#
WE#
OE#
CE1
#
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CE2
#
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
RY/BY#
DQ15
DQ7
RY/BY# RY/BY#
DQ15
DQ7
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ14
DQ6
DQ14
DQ6
8
9
GND
GND
10
11
12
13
14
15
16
17
18
19
20
DQ13 DQ13
DQ5
DQ12
DQ4
VCC
DQ5
DQ12
DQ4
DD28F032SA
56-LEAD TSOP PINOUT
DQ12
DQ
4
VCC
CE0
#
VPP
RP#
A11
A10
A9
CE0# CE0#
VCC
GND
DQ11
DQ 3
DQ 10
DQ 2
VCC
DQ 9
DQ 1
DQ 8
DQ 0
A0
VPP
RP#
A11
A10
A9
VPP
RP#
A11
A10
A9
GND
DQ11
DQ3
GND
DQ11
DQ3
14mm x 20mm
TOP VIEW
DQ10 DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
A8
GND
A7
A6
A5
A4
A3
A2
A8
A8
21
GND GND
22
23
24
25
26
27
28
A7
A6
A5
A4
A3
A2
A1
A7
A6
A5
A4
A3
A2
A1
BYTE#
NC
BYTE# BYTE#
30
29
NC
NC
NC
NC
NC
A1
0490_02
Figure 2. Dual Die TSOP Pinout Configuration
3.0 MODES OF OPERATION
RP#
CE0#
CE1#
CE2#
28F016SA
No. 1
28F016SA
No. 2
DD28F032SA
Chip
0
1
1
1
1
1
X
1
0
0
0
0
X
X
0
1
1
0
X
X
1
0
1
0
DPD
DPD
Standby
DPD
Standby
Active
Standby
Standby
Active
Active
Standby
Active
Standby
Standby
Standby
Illegal Condition
NOTES:
X = Don’t Care
DPD = Deep Power-Down
28F016SA No. 1 = First 16-Mbit Device
28F016SA No. 2 = Second 16-Mbit Device
10
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DD28F032SA
4.0 MEMORY MAPS
1FFFFF
1FFFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
28F016SA No. 1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
28F016SA No. 2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
1F0000
1EFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1B0000
1AFFFF
1A0000
19FFFF
1A0000
19FFFF
190000
18FFFF
190000
18FFFF
180000
17FFFF
180000
17FFFF
170000
16FFFF
170000
16FFFF
160000
15FFFF
160000
15FFFF
150000
14FFFF
150000
14FFFF
140000
13FFFF
140000
13FFFF
130000
12FFFF
130000
12FFFF
120000
11FFFF
120000
11FFFF
110000
10FFFF
110000
10FFFF
100000
0FFFFF
100000
0FFFFF
0F0000
0EFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0B0000
0AFFFF
0A0000
09FFFF
0A0000
09FFFF
090000
08FFFF
090000
08FFFF
8
080000
07FFFF
080000
07FFFF
7
070000
06FFFF
070000
06FFFF
6
060000
05FFFF
060000
05FFFF
5
050000
04FFFF
050000
04FFFF
4
040000
03FFFF
040000
03FFFF
3
030000
02FFFF
030000
02FFFF
2
020000
01FFFF
020000
01FFFF
1
010000
00FFFF
010000
00FFFF
0
000000
000000
0490_03
Figure 3. DD28F032SA Memory Map (Byte-Wide Mode)
11
DD28F032SA
E
4.1 Extended Status Registers Memory Map for Either 28F016SA No. 1 or
28F016SA No. 2
x8 MODE
A[20-0]
x16 MODE
A[20-1]
1F0006H
F8003H
RESERVED
GSR
RESERVED
GSR
1F0005H
1F0004H
1F0003H
F8002H
RESERVED
BSR 31
RESERVED
BSR 31
1F0002H
1F0001H
1F0000H
F8001H
F8000H
RESERVED
RESERVED
RESERVED
RESERVED
.
.
.
.
.
.
010002H
000006H
08001H
RESERVED
RESERVED
00003H
00002H
RESERVED
GSR
RESERVED
GSR
000005H
000004H
RESERVED
BSR 0
RESERVED
BSR 0
000003H
000002H
00001H
00000H
RESERVED
RESERVED
RESERVED
RESERVED
000001H
000000H
0490_04
0490_05
Figure 4. Extended Status Register Memory
Map (Byte-Wide Mode)
Figure 5. Extended Status Register Memory
Map (Word-Wide Mode)
12
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DD28F032SA
5.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
5.1 Bus Operations for Word-Wide Mode (BYTE# = V )
IH
Mode
Notes
1,2,7
1,6,7
1,6,7
RP# CEX#(8) CE0#
OE#
VIL
VIH
X
WE#
VIH
VIH
X
A1
X
DQ0–15 RY/BY#
Read
VIH
VIH
VIH
VIL
VIL
VIL
VIL
DOUT
High Z
High Z
X
X
X
Output Disable
Standby
X
VIL
VIH
VIH
VIH
VIL
VIH
X
Deep Power-Down
Manufacturer ID
Device ID
1,3
4
VIL
VIH
VIH
VIH
X
X
X
X
X
VIL
VIH
X
High Z
0089H
66A0H
DIN
VOH
VOH
VOH
X
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
4
Write
1,5,6
5.2 Bus Operations for Byte-Wide Mode (BYTE# = V )
IL
Mode
Notes
1,2,7
1,6,7
1,6,7
RP# CEX#(8) CE0#
OE#
VIL
VIH
X
WE#
VIH
VIH
X
A0
X
DQ0–7
DOUT
RY/BY#
Read
VIH
VIH
VIH
VIL
VIL
VIL
VIL
X
X
X
Output Disable
Standby
X
High Z
High Z
VIL
VIH
VIH
VIH
VIL
VIH
X
Deep Power-Down
Manufacturer ID
Device ID
1,3
4
VIL
VIH
VIH
VIH
X
X
X
X
X
VIL
VIH
X
High Z
89H
VOH
VOH
VOH
X
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
4
A0H
DIN
Write
1,5,6
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH
.
2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down
mode, RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.
4.
A and A at VIL provide device manufacturer codes in x8 and x16 modes respectively. A and A1 at VIH provide device ID
0 1 0
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully
completed when VPP = VPPH.
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to
V
OH when the WSM is not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations; for example, a Status Register read during a
data program operation.
8. CEX# = CE1# or CE2#.
13
DD28F032SA
E
5.3 28F008SA Compatible Mode Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Notes
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Addr
X
Data
Oper
Read
Read
Read
Addr
AA
IA
Data
AD
Read Array
xxFFH
xx90H
xx70H
xx50H
xx40H
xx10H
xx20H
xxB0H
Intelligent Identifier
1
2
3
X
ID
Read Compatible Status Register
Clear Status Register
X
X
CSRD
X
Word/Byte Program
X
Write
Write
Write
Write
PA
PA
BA
X
PD
PD
Alternate Word/Byte Program
Block Erase/Confirm
X
X
xxD0H
xxD0H
Erase Suspend/Resume
X
ADDRESS
DATA
A = Array Address
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
PD = Program Data
NOTES:
1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters data program, block erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.4. Also clears GSR.4 and all BSR.4 and BSR.2 bits.
4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.
See Status Register definitions.
14
E
DD28F032SA
5.4 28F016SA-Performance Enhancement Command Bus Definitions
First Bus Cycle
Data(12)
Second Bus Cycle
Third Bus Cycle
Command
Mode Notes
Oper Addr
Oper Addr Data(12) Oper Addr
Data
Read Extended
Status Register
1
Write
X
xx71H
Read
RA
GSRD
BSRD
Page Buffer Swap
7
Write
Write
Write
X
X
X
xx72H
xx75H
xx74H
Read Page Buffer
Read PBA
Write PBA
PD
PD
Single Load to Page
Buffer
Sequential Load to
Page Buffer
x8
4,6,10
Write
X
xxE0H
Write
X
X
BCL
Write
Write
X
BCH
x16
x8
4,5,6,10 Write
3,4,9,10 Write
X
X
xxE0H
xx0CH
Write
Write
WCL
X
WCH
Page Buffer Write to
Flash
A
BC(L,H) Write
WCL Write
PA
BC(H,L)
0
x16
x8
4,5,10
3
Write
Write
Write
Write
X
X
X
X
xx0CH
xxFBH
xx77H
xx97H
Write
Write
Write
Write
X
PA
PA
WCH
Two-Byte Write
A
WD(L,H) Write
xxD0H
WD(H,L)
0
Lock Block/Confirm
BA
X
Upload Status
Bits/Confirm
2
xxD0H
Upload Device
Information
Write
Write
Write
Write
Write
X
X
X
X
X
xx99H
xxA7H
xx96H
xx96H
xx96H
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
xxD0H
xxD0H
xx01H
xx02H
xx03H
xx04H
Erase All Unlocked
Blocks/Confirm
RY/BY# Enable to
Level-Mode
8
8
8
RY/BY# Pulse-On-
Write
RY/BY# Pulse-On-
Erase
RY/BY# Disable
Sleep
8
Write
Write
Write
X
X
X
xx96H
xxF0H
xx80H
11
Abort
ADDRESS
DATA
BA = Block Address
AD = Array Data
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
PBA = Page Buffer Address
RA = Extended Register Address
PA = Program Address
X = Don’t Care
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
15
DD28F032SA
E
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3.
A0 is automatically complemented to load the second byte of data. BYTE# must be at V .
IL
The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DQ0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.
6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between availablePage Buffers (0 or 1).
8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.
9. Program address, PA, is the destination address in the flash array which must match the source address in the Page
Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual.
10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.
11. To ensure that the DD28F032SA’s power consumption during sleep mode reads the deep power-down current level, the
system also needs to de-select the chip by taking either or both CE # or CE1#/CE2# high.
0
12. The upper byte of the data bus (DQ8–15) during command programs is a “Don’t Care” in x16 operation of the device.
5.5 Compatible Status Register
WSMS
7
ESS
6
ES
5
DWS
4
VPPS
3
R
2
R
1
R
0
NOTES:
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase
suspend, block erase or data program) before
the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
0 = Erase In Progress/Completed
If DWS and ES are set to “1” during a block
erase attempt, an improper command sequence
was entered. Clear the CSR and attempt the
operation again.
CSR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA WRITE STATUS
1 = Error in Data Program
0 = Data Program Successful
The VPPS bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The
WSM interrogates VPP’s level only after the Data
Program or Block Erase command sequences
have been entered, and informs the system if
CSR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
V
PP has not been switched on. VPPS is not
guaranteed to report accurate feedback between
PPL and VPPH
V
.
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
16
E
DD28F032SA
5.6 Global Status Register
WSMS
7
OSS
6
DOS
5
DSS
4
QS
3
PBAS
2
PBS
1
PBSS
0
NOTES:
[1] RY/BY# output or WSMS bit must be checked
to determine completion of an operation (block
lock, erase suspend, any RY/BY# reconfig-
uration, Upload Status Bits, block erase or data
program) before the appropriate Status bit (OSS
or DOS) is checked for success.
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
0 = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
0 = Operation Successful or Currently
Running
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
0 = Device Not in Sleep
MATRIX = 5/4
If operation currently running, then GSR.7 = 0.
If device pending sleep, then GSR.7 = 0.
0 0 = Operation Successful or Currently
Running
0 1 = Device in Sleep Mode or Pending
Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or Aborted
Operation aborted: unsuccessful due to Abort
command.
GSR.3 = QUEUE STATUS
1 = Queue Full
0 = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers Available
0 = No Page Buffer Available
Each 28F016SA device contains two Page
Buffers.
GSR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy
Selected Page Buffer is currently busy with WSM
operation
GSR.0 = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
0 = Page Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.
17
DD28F032SA
E
5.7 Block Status Register
BS
7
BLS
6
BOS
5
BOAS
4
QS
VPPS
2
R
1
R
0
3
NOTES:
BSR.7 = BLOCK STATUS
1 = Ready
[1] RY/BY# output or BS bit must be checked to
determine completion of an operation (block lock,
erase suspend, any RY/BY# reconfiguration,
Upload Status Bits, block erase or data program)
before the appropriate Status bits (BOS, BLS) is
checked for success.
0 = Busy
BSR.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Program/Erase
0 = Block Locked for Program/Erase
BSR.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
0 = Operation Successful or
Currently Running
BSR.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
The BOAS bit will not be set until BSR.7 = 1.
0 = Operation Not Aborted
MATRIX 5/4
0 0 = Operation Successful or
Currently Running
0 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
Operation halted via Abort command.
BSR.3 = QUEUE STATUS
1 = Queue Full
0 = Queue Available
BSR.2 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.
18
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DD28F032SA
6.0 ELECTRICAL SPECIFICATIONS
NOTICE: This is a production datasheet. The specifications
are subject to change without notice. Verify with your local
Intel Sales office that you have the latest datasheet before
finalizing a design.
6.1 Absolute Maximum Ratings*
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
Temperature Under Bias ....................0°C to +80°C
Storage Temperature ...................–65°C to +125°C
VCC = 3.3V ± 0.3V Systems
Symbol
Parameter
Notes Min
Max Units Test Conditions
TA
Operating Temperature, Commercial
1
0
70
°C
Ambient
Temperature
VCC
VPP
V
VCC with Respect to GND
2
2,3
2
–0.2
7.0
V
V
PP Supply Voltage with Respect to GND
–0.2 14.0
V
V
Voltage on any Pin (except VCC,VPP) with
Respect to GND
VCC
–0.5
+ 0.5
I
Current into Any Non-Supply Pin
Output Short Circuit Current
5
4
± 30
100
mA
mA
IOUT
V
CC = 5.0V ± 0.5V, VCC = 5.0V ± 0.25V Systems(6)
Symbol
Parameter
Notes Min
Max Units Test Conditions
TA
Operating Temperature, Commercial
1
0
70
°C
Ambient
Temperature
VCC
VPP
V
VCC with Respect to GND
2
2,3
2
–0.2
7.0
V
V
V
VPP Supply Voltage with Respect to GND
–0.2 14.0
Voltage on Any Pin (except VCC,VPP) with
Respect to GND
–2.0
7.0
I
Current into Any Non-Supply Pin
Output Short Circuit Current
5
4
± 30
100
mA
mA
IOUT
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to–2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for
periods <20 ns.
3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. This specification also applies to pins marked “NC.”
6. 5% VCC specifications refer to the DD28F032SA-070 in its High Speed Test configuration.
19
DD28F032SA
E
6.2 Capacitance
For a 3.3V System:
Symbol
Parameter
Notes Typ
Max Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
1
1
12
16
24
50
pF
pF
pF
TA = +25°C,
f = 1.0 MHz
COUT
CLOAD
Capacitance Looking into an
Output Pin
16
TA = +25°C,
f = 1.0 MHz
Load Capacitance Driven by
For VCC = 3.3V ± 0.3V
Outputs for Timing Specifications
Equivalent Load Timing Circuit
2.5
ns
50Ω Transmission Line
Delay
For a 5.0V System:
Symbol
Parameter
Notes Typ
Max Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
1
1
12
16
pF
pF
pF
TA = +25°C,
f = 1.0 MHz
COUT
CLOAD
Capacitance Looking into an
Output Pin
16
24
TA = +25°C,
f = 1.0 MHz
100
Load Capacitance Driven by
For VCC = 5.0V ± 0.5V
Outputs for Timing Specifications
30
pF
For VCC = 5.0V ±
0.25V
Equivalent Testing Load Circuit for
2.5
2.5
ns
ns
25Ω Transmission Line
V
CC ± 10%
Delay
Equivalent Testing Load Circuit for
83Ω Transmission Line
V
CC ± 5%
Delay
NOTE:
1. Sampled, not 100% tested.
20
E
DD28F032SA
6.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tOE
tACC
tAS
tELQV time(t) from CEX# (E) going low (L) to the outputs (Q) becoming valid (V)
tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)
tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tDH
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
Address Inputs
Pin States
A
D
H
L
High
Low
Data Inputs
Q
E
Data Outputs
V
X
Z
Valid
CEX# (Chip Enable)
BYTE# (Byte Enable)
OE# (Output Enable)
WE# (Write Enable)
RP# (Deep Power-Down Pin)
RY/BY# (Ready Busy)
Any Voltage Level
3/5# Pin
Driven, but not necessarily valid
High Impedance
F
G
W
P
R
V
Y
5V
3V
VCC at 4.5V Minimum
VCC at 3.0V Minimum
21
DD28F032SA
E
2.4
2.0
0.8
2.0
0.8
INPUT
OUTPUT
TEST POINTS
0.45
0490_06
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at V
IH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Transient Input/Output Reference Waveform (VCC = 5.0V) for Standard Test Configuration(1)
3.0
OUTPUT
INPUT
1.5
TEST POINTS
1.5
0.0
0490_07
AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 7. Transient Input/Output Reference Waveform (VCC = 3.3V)
and High Speed Reference Waveform (2) (VCC = 5.0V ± 5%)
NOTES:
1. Testing characteristics for DD28F032SA-080/DD28F032SA-100.
2. Testing characteristics for DD28F032SA-070/DD28F032SA-150.
22
E
DD28F032SA
2.5 ns of 25 Transmission Line
Ω
Test
From Output
under Test
Point
Total Capacitance = 100 pF
0490-08
Figure 8. Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 10%)
2.5 ns of 50
Ω
Transmission Line
From Output
under Test
Test
Point
Total Capacitance = 50 pF
Figure 9. Transient Equivalent Testing Load Circuit (VCC = 3.3V ± 0.3V)
0490-09
Ω
2.5 ns of 83 Transmission Line
From Output
under Test
Test
Point
Total Capacitance = 30 pF
0490-10
Figure 10. High Speed Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 5%)
23
DD28F032SA
E
6.4 DC Characteristics
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C
3/5# = Pin Set High for 3.3V Operations
Symbol
IIL
Parameter
Notes
Min
Typ
Max Units
Test Conditions
VCC = VCC Max
IN = VCC or GND
VCC = VCC Max
IN = VCC or GND
VCC = VCC Max
Input Load Current
1
± 2
± 20
200
µA
µA
µA
V
Output Leakage
Current
ILO
1
V
VCC Standby
Current
ICCS
1,5,6,8
100
CE0#, CEX#, RP#, = VCC
±
0.2V
BYTE#, WP#, 3/5# = VCC
±
0.2V or GND ± 0.2V
VCC= VCC Max
2
8
mA
CE0#, CEX#, RP# = VIH
BYTE#, WP#, 3/5# = VIH or
VIL
VCC Deep Power-
Down Current
RP# = GND ± 0.2V
BYTE# = VCC ± 0.2V or GND
± 0.2V
ICCD
1
2
10
30
µA
VCC = VCC Max
ICCR1
VCC Read Current
1,4,5,6
25
mA
CMOS: CE0#, CEX# = GND
± 0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
f = 6.67 MHz, IOUT = 0 mA
TTL: CE0#, CEX# = VIL,
BYTE# = VIL or VIH’
26
8
34
12
mA
mA
Inputs = VIL or VIH
f = 6.67 MHz, IOUT = 0 mA
ICCW
VCC Program
Current for Word or
Byte
1,7
Program in Progress
VCC Block Erase
Current
ICCE
1,7
1,2,6,7
1
6
3
12
6
mA
mA
Block Erase in Progress
VCC Erase
CE0#, CEX# = VIH
ICCES
Suspend Current
Block Erase Suspended
IPPS
IPPR
IPPD
VPP Standby/
Read Current
± 2
130
0.4
± 20
400
10
µA
µA
µA
V
V
PP ≤ VCC
PP > VCC
VPP Deep Power-
Down Current
1
RP# = GND ± 0.2V
24
E
DD28F032SA
6.4 DC Characteristics (Continued)
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C
3/5# Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Min
Typ
Max Units
Test Conditions
VPP = VPPH
IPPW
VPP Program
Current for Word or
Byte
1
10
15
mA
Program in Progress
VPP = VPPH
IPPE
VPP Block Erase
Current
1
1
4
10
mA
µA
Block Erase in Progress
VPP Erase
VPP = VPPH
IPPES
130
400
0.8
Suspend Current
Block Erase Suspended
VIL
VIH
Input Low Voltage
Input High Voltage
–0.3
2.0
V
V
VCC
± 0.3
VCC = VCC Min
VOL
Output Low Voltage
0.4
V
V
I
OL = 4 mA
VCC = VCC Min
OH = –2.0 mA
VCC = VCC Min
OH = –100 µA
Output High
Voltage
VOH
1
2
2.4
I
VCC
VOH
– 0.2
I
VPP during Normal
Operations
VPPL
VPPH
3
0.0
6.5
V
V
VPP during
11.4 12.0 12.6
Program/Erase
Operations
VCC Program/Erase
Lock Voltage
VLKO
2.0
V
NOTES:
1. All current are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V, T = 25°C. These currents are
valid for all product versions (package and speeds).
2.
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR
3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the
range between VPPH and VPPL
.
.
4. Automatic Power Savings (APS) reduces ICCR to <1 mA in static operation.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH
6. CEX# = CE1# or CE2#.
.
7. If operating with TTL levels, add 4 mA of VCC Standby Current to max ICCR1, ICCR2, ICCW, ICCE and ICCES
.
8. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.
Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.
25
DD28F032SA
E
6.5 DC Characteristics
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
3/5# Pin Set Low for 5.0V Operations
Symbol
IIL
Parameter
Notes
Min
Typ
Max Units
Test Conditions
V
V
CC = VCC Max
Input Load Current
1
± 2
± 20
200
µA
µA
µA
IN = VCC or GND
Output Leakage
Current
V
V
CC = VCC Max
ILO
1
IN = VCC or GND
V
CC = VCC Max
ICCS
VCC Standby
Current
1,5,6,8
100
CE0#, CEX#, RP# = VCC
0.2V
±
BYTE#, WP#, 3/5# = VCC
0.2V or GND ± 0.2V
±
V
CC = VCC Max
4
8
mA
CE0#, CEX#, RP# = VIH
BYTE#, WP#, 3/5#
VIL
V
IH or
=
RP# = GND ± 0.2V
ICCD
VCC Deep Power-
Down Current
1
4
25
60
µA
BYTE# = VCC ± 0.2V or GND
± 0.2V
VCC = VCC Max
ICCR1
VCC Read Current
1,4,5,
6,7
50
mA
CMOS: CE0#, CEX# = GND ±
0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
V
CC ± 0.2V
f = 10 MHz, IOUT = 0 mA
TTL: CE0#, CEX# = VIL,
BYTE# = VIL or VIH,
Inputs = VIL or VIH
52
30
64
35
mA
mA
f = 10 MHz, IOUT = 0 mA
VCC = VCC Max
ICCR2
VCC Read Current
1,4,5,
6,7
CMOS: CE0#, CEX# = GND ±
0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V
Inputs = GND ± 0.2V or
V
CC ± 0.2V
f = 5 MHz, IOUT = 0 mA
TTL: CE0#, CEX# = VIL,
BYTE# = VIL or VIH,
Inputs = VIL or VIH
32
25
39
35
mA
mA
f = 5 MHz, IOUT = 0 mA
ICCW
VCC Prog. Current
for Word or Byte
1,7
Program in Progress
26
E
DD28F032SA
6.5 DC Characteristics (Continued)
V
CC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
3/5# Pin Set Low for 5.0V Operations
Symbol
Parameter
Notes
Min
Typ
Max Units
Test Conditions
VCC Block Erase
ICCE
1,7
18
25
10
mA
mA
Block Erase in Progress
Current
VCC Erase Suspend
Current
CE0#, CEX# = VIH
ICCES
1,2,6,7
1
5
Block Erase Suspended
IPPS
IPPR
IPPD
VPP Standby/
Read Current
± 2
130
0.4
± 20
400
10
µA
µA
µA
V
V
PP ≤ VCC
PP > VCC
VPP Deep Power-
Down Current
1
1
RP# = GND ± 0.2V
VPP
=
VPPH
IPPW
VPP Prog. Current
for Word or Byte
7
12
mA
Program in Progress
VPP Block Erase
Current
VPP
Block Erase in Progress
VPP
Block Erase Suspended
=
VPPH
IPPE
1
1
5
10
400
0.8
mA
µA
VPP Erase
=
VPPH
IPPES
130
Suspend Current
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
2.0
V
V
VCC
+ 0.5
VOL
Output Low Voltage
0.45
V
V
V
CC = VCC Min, IOL = 5.8 mA
Output High
Voltage
0.85
VCC
VOH
1
2
VCC = VCC Min, IOH = –2.5 mA
VCC
VOH
V
CC = VCC Min, IOH = –100 µA
– 0.4
VPP during Normal
Operations
VPP during Prog.
Erase Operations
VCC Program/Erase
Lock Voltage
VPPL
VPPH
3
0.0
6.5
V
V
V
11.4 12.0 12.6
2.0
VLKO
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T = +25°C. These currents are
valid for all product versions (package and speeds).
2.
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the
range between VPPH and VPPL
.
4. Automatic Power Saving (APS) reduces ICCR to <2 mA in static operation.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH
6. CEX#= CE1# or CE2#.
.
7. If operating with TTL levels, add 4 mA of VCC standby current. to max ICCR1, ICCR2, ICCW, ICCE and ICCES
.
8. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.
Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.
27
DD28F032SA
E
(1)
Notes
2
6.6 AC Characteristics—Read Only Operations
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C
Versions (5)
Parameter
Read Cycle Time
DD28F032SA-150
Symbol
tAVAV
Min
Max
Units
150
ns
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
Address to Output Delay
CEX# to Output Delay
RP# High to Output Delay
OE# to Output Delay
150
150
750
50
ns
ns
ns
2
3
3
3
3
3
ns
CEX# to Output in Low Z
CEX# to Output in High Z
OE# to Output in Low Z
OE# to Output in High Z
0
0
0
ns
35
20
ns
ns
ns
Output Hold from Address, CEX# or
OE# Change, Whichever Occurs First
ns
tFLQV
tFHQV
BYTE# to Output Delay
3
150
ns
tFLQZ
BYTE# Low to Output in High Z
CEX# Low to BYTE# High or Low
3
3
40
5
ns
ns
tELFL
tELFH
For Extended Status Register Reads
tAVEL Address Setup to CEX# Going Low
tAVGL Address Setup to OE# Going Low
3,4
3,4
0
0
ns
ns
28
E
DD28F032SA
(1)
6.6 AC Characteristics—Read Only Operations (Continued)
V
CC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
VCC ± 5%
VCC ± 10%
Notes
DD28F032SA-
070(6)
Versions(5)
Units
DD28F032SA-
DD28F032SA-
100(7)
080(7)
Sym
tAVAV
tAVQV
Parameter
Min
Max
Min
Max
Min
Max
Read Cycle Time
70
80
100
ns
ns
Address to
70
70
80
80
100
100
550
40
Output Delay
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
CEX# to Output
Delay
2
ns
ns
ns
ns
ns
ns
ns
ns
RP# to Output
Delay
400
30
480
35
OE# to Output
Delay
2
3
3
3
3
3
CEX# to Output
in Low Z
0
0
0
0
0
0
0
0
0
CEX# to Output
in High Z
25
25
30
15
30
15
OE# to Output in
Low Z
OE# to Output in
High Z
Output Hold from
Address, CEX#
or OE# Change,
Whichever
Occurs First
tFLQV
tFHQV
BYTE# to Output
Delay
3
70
80
100
ns
tFLQZ
BYTE# Low to
Output in High Z
3
3
25
5
30
5
30
5
ns
ns
tELFL
tELFH
CEX# Low to
BYTE# High or
Low
For Extended Status Register Reads
tAVEL
Address Setup to
CEX# Going Low
3,4
0
0
0
0
0
0
ns
ns
tAVGL
Address Setup to
OE# Going Low
3,4
29
DD28F032SA
E
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact in tELQV
3. Sampled, not 100% tested.
.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device speeds are defined as:
70/80 ns at VCC = 5.0V equivalent to
150 ns at VCC = 3.3V
100 ns at VCC = 5.0V equivalent to
150 ns at VCC = VCC = 3.3V
6. See AC Input/Output Reverence Waveforms and AC Testing Load Circuits for High Speed Test Configuration.
7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
V
IH
ADDRESSES (A)
V
ADDRESSES STABLE
IL
t
AVAV
V
IH
(1)
CEx# (E)
t
AVEL
V
IL
t
EHQZ
V
IH
t
AVGL
OE# (G)
V
IL
t
GHQZ
V
IH
WE# (W)
V
t
GLQV
IL
t
t
ELQV
OH
t
GLQX
t
V
ELQX
OH
HIGH Z
HIGH Z
DATA (D/Q)
V
VALID OUTPUT
OL
t
AVQV
5.0V
V
CC
GND
V
t
PHQV
IH
RP# (P)
V
IL
0490-11
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.
Figure 11. Read Timing Waveforms
30
E
DD28F032SA
V
IH
ADDRESSES STABLE
ADDRESSES (A)
V
IL
t
AVAV
V
IH
(1)
CEx #(E)
V
IL
t
= t
AVFL
ELFL
tEHQZ
V
IH
t
AVEL
OE# (G)
t
GHQZ
V
IL
t
ELFL
t
AVGL
V
IH
t
= t
AVQV
FLQV
BYTE# (F)
t
GLQV
V
IL
t
t
OH
ELQV
t
GLQX
V
t
OH
ELQX
HIGH Z
HIGH Z
HIGH Z
DATA
OUTPUT
DATA (DQ0-DQ7)
DATA OUTPUT
V
OL
t
AVQV
t
V
FLQZ
OH
DATA (DQ8-DQ15)
HIGH Z
DATA
OUTPUT
V
OL
0490-12
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.
Figure 12. BYTE# Timing Waveforms
31
DD28F032SA
E
6.7 Power-Up and Reset Timings
V
Power-Up
CC
RP#
(P)
tYHPH
tYLPH
3/5#
(Y)
5.0V
tPLYL
4.5V
3.3V
V
CC
0V
(3V,5V)
tPL5V
CE
#
X
tPHEL3
tPHEL5
Address
(A)
Valid
Valid
tAVQV
tAVQV
Valid 3.3V Outputs
Data
(Q)
Valid 5.0V Outputs
tPHQV
tPHQV
0490-13
Figure 13. VCC Power-Up and RP# Reset Waveforms
Symbol
Parameter
Notes
Min
Max
Units
µs
tPLYL
RP# Low to 3/5# Low (High)
0
tPLYH
tYLPH
tYHPH
tPL5V
tPL3V
3/5# Low (High) to RP# High
1
2
2
0
µs
µs
RP# Low to VCC at 4.5V Minimum (to VCC at
3.0V min or 3.6V max)
tPHEL3
tPHEL5
tAVQV
RP# High to CE# Low (3.3V VCC
)
1
1
3
3
500
330
RP# High to CE# Low (5V VCC
)
Address Valid to Data Valid for VCC = 5.0V ± 10%
RP# High to Data Valid for VCC = 5.0V ± 10%
80
ns
ns
tPHQV
480
NOTES:
CE0#, CEX# and OE# are switched low after Power-Up.
1. The tYLPH/tYHPH and tPHEL3/tPHEL5 times must be strictly followed to guarantee all other read and program specifications.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for the DD28F032SA-80 and 5.0V VCC operation.
Refer to the AC Characteristics-Read Only Operations for 3.3V VCC operation and all other speed options.
32
E
DD28F032SA
(1)
6.8 AC Characteristics for WE#—Controlled Command Write Operations
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C
Versions
Parameter
Write Cycle Time
DD28F032SA-150
Symbol
tAVAV
tVPWH
tPHEL
Notes
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
100
480
10
75
85
75
10
10
10
75
0
VPP Setup to WE# Going High
RP# Setup to CEX# Going Low
CEX# Setup to WE# Going Low
Address Setup to WE# Going High
Data Setup to WE# Going High
WE# Pulse Width
3
tELWL
tAVWH
tDVWH
tWLWH
tWHDX
tWHAX
tWHEH
tWHWL
tGHWL
tWHRL
tRHPL
2,6
2,6
Data Hold from WE# High
Address Hold from WE# High
CEX# Hold from WE# High
WE# Pulse Width High
2
2
Read Recovery before Write
WE# High to RY/BY# Going Low
100
RP# Hold from Valid Status Register
3
0
(CSR, GSR, BSR) Data and RY/BY# High
tPHWL
tWHGL
tQVVL
RP# High Recovery to WE# Going Low
Write Recovery before Read
1
120
0
µs
ns
µs
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High
tWHQV
1
Duration of Word/Byte Program Operation
Duration of Block Erase Operation
4,5
4
5
9
Note 7
10
µs
tWHQV
2
0.3
sec
33
DD28F032SA
E
(1)
6.8 AC Characteristics for WE#—Controlled Command Write Operations
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
Versions
VCC ± 5% DD28F032SA-070
Unit
VCC ± 10%
DD28F032SA-080 DD28F032SA-100
Min Typ Max Min Typ Max Min Typ Max
Sym
Parameter
Notes
Write Cycle
Time
VPP Setup to
WE# Going
High
RP# Setup to
CEX# Going
Low
CEX# Setup
to WE# Going
Low
tAVAV
70
80
100
100
ns
ns
tVPWH
tPHEL
tELWL
tAVWH
tDVWH
3
100
100
480
0
480
0
480
0
ns
ns
ns
ns
Address
2,6
2,6
50
60
50
60
50
60
Setup to WE#
Going High
Data Setup to
WE# Going
High
WE# Pulse
Width
Data Hold
from WE#
High
Address Hold
from WE#
High
CEX# Hold
from WE#
High
tWLWH
tWHDX
40
0
50
0
50
0
ns
ns
2
2
tWHAX
10
10
10
10
10
10
ns
ns
tWHEH
WE# Pulse
Width High
Read
Recovery
before Write
WE# High to
RY/BY#
tWHWL
tGHWL
30
0
30
0
50
0
ns
ns
tWHRL
100
100
100
ns
Going Low
34
E
DD28F032SA
(1)
6.8 AC Characteristics for WE#—Controlled Command Write Operations
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
Versions
VCC ± 5% DD28F032SA-070
Unit
VCC ± 10%
DD28F032SA-080 DD28F032SA-100
Min Typ Max Min Typ Max Min Typ Max
Sym
Parameter
Notes
RP# Hold
from Valid
Status
tRHPL
3
0
0
0
ns
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High
RP# High
Recovery to
WE# Going
Low
tPHWL
1
1
1
µs
Write
tWHGL
60
0
65
0
65
0
ns
µs
Recovery
before Read
VPP Hold from
Valid Status
Register
tQVVL
(CSR, GSR,
BSR) Data
and RY/BY#
High
Duration of
Word/Byte
Program
Operation
Duration of
Block Erase
Operation
tWHQV
1
4,5
4
4.5
0.3
6
Note 4.5
7
6
Note 4.5
7
6
Note µs
7
tWHQV
2
10
0.3
10
0.3
10
sec
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.
1. Read timings during data program and block erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested
4. Data program/block erase durations aremeasured to valid Status Register data.
5. Word/byte program operations are typically performed with 1 programming pulse.
6. Address and data are latched on the rising edge of WE# for all command write operations.
7. This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for
more information.
35
DD28F032SA
E
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
WRITE READ EXTENDED
REGISTER COMMAND
DEEP
WRITE DATA-WRITE OR
AUTOMATED DATA-WRITE
OR ERASE DELAY
READ EXTENDED
STATUS REGISTER DATA
POWER-DOWN
ERASE SETUP COMMAND
V
IH
ADDRESSES (A)
A
A=RA
IN
V
NOTE 1
IL
t
t
AVAV
WHAX
WHAX
READ COMPATIBLE
STATUS REGISTER DATA
t
AVWH
V
NOTE 3
IH
ADDRESSES (A)
V
A
IN
NOTE 2
IL
t
t
t
AVAV
AVWH
V
V
IH
IL
CEx # (E)
NOTE 4
t
t
ELWL
WHEH
t
WHGL
V
V
IH
IL
OE# (G)
t
t
t
WHWL
WHQV1,2
GHWL
V
V
IH
IL
WE# (W)
t
t
WLWH
DVWH
t
WHDX
V
IH
IL
HIGH Z
t
DATA (D/Q)
D
D
D
D
D
IN
IN
IN
OUT
IN
V
PHWL
t
WHRL
V
OH
OL
RY/BY# (R)
V
t
RHPL
V
IH
IL
NOTE 5
RP# (P)
V
t
t
QVVL
VPWH
V
PPH
V
V
PPL
IH
V
(V)
PP
V
IL
0490-14
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high
5. RP# low transition is only to show tRHPL; not valid for above Read and Program cycles.
Figure 14. AC Waveforms for Command Write Operations
36
E
DD28F032SA
(1)
6.9 AC Characteristics for CE #—Controlled Command Write Operations
X
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C
Versions
Parameter
Write Cycle Time
DD28F032SA-150
Symbol
Notes
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAV
150
100
480
0
tVPEH
tPHWL
tWLEL
tAVEH
tDVEH
tELEH
tEHDX
tEHAX
tEHWH
tEHEL
tGHEL
tEHRL
tRHPL
VPP Setup to CEX# Going High
RP# Setup to WE# Going Low
WE# Setup to CEX# Going Low
Address Setup to CEX# Going High
Data Setup to CEX# Going High
CEX# Pulse Width
3
2,6
2,6
75
85
75
10
10
10
75
0
Data Hold from CEX# High
Address Hold from CEX# High
WE# Hold from CEX# High
CEX# Pulse Width High
2
2
Read Recovery before Write
CEX# High to RY/BY# Going Low
100
RP# Hold from Valid Status Register
3
0
(CSR, GSR, BSR) Data and RY/BY# High
tPHEL
tEHGL
tQVVL
RP# High Recovery to CEX# Going Low
Write Recovery before Read
1
120
0
µs
ns
µs
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High
tEHQV
1
Duration of Word/Byte Program Operation
Duration of Block Erase Operation
4,5
4
5
9
Note 7
10
µs
tEHQV
2
0.3
sec
37
DD28F032SA
E
(1)
6.9 AC Characteristics for CE #—Controlled Command Write Operations
X
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
Versions
VCC ± 5% DD28F032SA-070
Unit
VCC ± 10%
DD28F032SA-080 DD28F032SA-100
Min Typ Max Min Typ Max Min Typ Max
Sym
Parameter
Notes
Write Cycle
Time
VPP Setup to
CEX# Going
High
RP# Setup to
WE# Going
Low
WE# Setup to
CEX# Going
Low
Address Setup
to CEX# Going
High
Data Setup to
CEX# Going
High
tAVAV
70
80
100
100
ns
ns
tVPEH
tPHWL
tWLEL
tAVEH
tDVEH
3
3
100
100
480
0
480
0
480
0
ns
ns
ns
ns
2,6
2,6
50
60
50
60
50
60
CEX# Pulse
Width
Data Hold
from CEX#
High
Address Hold
from CEX#
High
WE# Hold
from CEX#
High
tELEH
tEHDX
40
0
50
0
50
0
ns
ns
2
2
tEHAX
10
10
10
10
10
10
ns
ns
tEHWH
CEX# Pulse
Width High
Read
Recovery
before Write
CEX# High to
RY/BY# Going
Low
tEHEL
tGHEL
30
0
30
0
50
0
ns
ns
tEHRL
100
100
100
ns
ns
RP# Hold from
Valid Status
Register
tRHPL
3
0
0
0
(CSR, GSR,
BSR) Data
and RY/BY#
High
38
E
DD28F032SA
(1)
6.9 AC Characteristics for CE #—Controlled Command Write Operations
X
(Continued)
VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
Versions
VCC ± 5% DD28F032SA-070
Unit
VCC ± 10%
DD28F032SA-080 DD28F032SA-100
Min Typ Max Min Typ Max Min Typ Max
Sym
Parameter
Notes
RP# High
Recovery to
CEX#
tPHEL
1
1
1
µs
Going Low
Write
Recovery
before Read
VPP Hold from
Valid Status
Register
tEHGL
60
0
65
0
80
0
ns
µs
tQVVL
(CSR, GSR,
BSR) Data at
RY/BY# High
Duration of
Word/Byte
Program
Operation
Duration of
Block Erase
Operation
tEHQV
1
4,5
4
4.5
0.3
6
Note 4.5
7
6
Note 4.5
7
6
Note µs
7
tEHQV
2
10
0.3
10
0.3
10
sec
NOTES:
For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.
1. Read timings during data program and block erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Data program/block erase durations are measured to valid Status Register data.
5. Word/byte program operations are typically performed with 1 programming pulse.
6. Address and data are latched on the rising edge of CEX# for all command write operations.
7. This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for
more information.
39
DD28F032SA
E
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
WRITE READ EXTENDED
REGISTER COMMAND
DEEP
WRITE DATA-WRITE OR
AUTOMATED DATA-WRITE
OR ERASE DELAY
READ EXTENDED
STATUS REGISTER DATA
POWER-DOWN
ERASE SETUP COMMAND
V
IH
ADDRESSES (A)
A
A=RA
IN
V
NOTE 1
IL
t
t
t
AVAV
EHAX
EHAX
READ COMPATIBLE
STATUS REGISTER DATA
t
AVEH
V
NOTE 3
IH
ADDRESSES (A)
V
A
IN
NOTE 2
IL
t
t
AVAV
AVEH
V
V
IH
IL
WE# (W)
t
t
WLEL
EHWH
t
EHGL
V
V
IH
IL
OE# (G)
t
t
t
EHEL
EHQV1,2
GHEL
V
V
IH
IL
CEx#(E)
NOTE 4
t
ELEH
DVEH
t
t
EHDX
V
IH
IL
HIGH Z
t
DATA (D/Q)
D
D
D
D
D
IN
IN
IN
OUT
IN
V
PHEL
t
EHRL
V
OH
OL
RY/BY# (R)
V
t
RHPL
V
IH
IL
NOTE 5
RP# (P)
V
t
t
QVVL
VPEH
V
PPH
V
V
PPL
IH
V
(V)
PP
V
IL
0490_15
NOTES:
1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/block erase operations.
4. For 28F016SA No. 1:CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 15. Alternate AC Waveforms for Command Write Operations
40
E
DD28F032SA
(1)
6.10 AC Characteristics for Page Buffer Write Operations
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C
Versions
DD28F032SA-150
Min Typ Max
Symbol
Parameter
Write Cycle Time
Notes
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAV
150
10
0
tELWL
tAVWL
tDVWH
tWLWH
tWHDX
tWHAX
tWHEH
tWHWL
tGHWL
tWHGL
CEX# Setup to WE# Going Low
Address Setup to WE# Going Low
Data Setup to WE# Going High
WE# Pulse Width
3
2
75
75
10
10
10
75
0
Data Hold from WE# High
Address Hold from WE# High
CEX# Hold from WE# High
WE# Pulse Width High
2
2
Read Recovery before Write
Write Recovery before Read
120
41
DD28F032SA
E
6.10 AC Characteristics for Page Buffer Write Operations(1) (Continued)
V
CC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C
Versions
DD28F032SA-070 DD28F032SA-080 DD28F032SA-100
Symbol
Parameter
Notes Min Typ Max Min Typ Max Min Typ Max Unit
tAVAV
Write Cycle
Time
70
0
80
0
100
0
ns
CEX# Setup to
tELWL
ns
WE# Going
Low
Address Setup
to WE# Going
Low
tAVWL
tDVWH
tWLWH
3
2
0
0
0
ns
ns
ns
Data Setup to
WE# Going
High
50
40
50
50
50
50
WE# Pulse
Width
Data Hold from
WE# High
tWHDX
tWHAX
tWHEH
2
2
0
0
0
ns
ns
ns
Address Hold
from WE# High
10
10
10
10
10
10
CEX# Hold from
WE# High
WE# Pulse
Width High
tWHWL
tGHWL
tWHGL
30
0
30
0
50
0
ns
ns
ns
Read Recovery
before Write
Write Recovery
before Read
60
65
80
NOTES:
For 28F016SA No. 1: CEX # is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX # is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.
1. These are WE#-controlled write timings, equivalent CEX#-controlled write timings apply.
2. Sampled, not 100% tested.
3. Address must be valid during the entire WE# low pulse or the entire CE # low pulse (for CEX #-controlled write timings).
X
42
E
DD28F032SA
V
IH
t
WHEH
CEx#
(E)
V
IL
t
ELWL
V
IH
t
WE#
(W)
WHWL
V
IL
t
AVWL
t
WLWH
t
WHAX
V
IH
ADDRESSES (A)
VALID
V
IL
t
t
WHDX
DVWH
V
IH
HIGH Z
DATA
(D/Q)
D
IN
V
IL
0490-16
Figure 16. Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
43
DD28F032SA
E
6.11 Erase and Word/Byte Write Performance, Cycling Performance
(3)
and Suspend Latency
V
CC = 3.3V ± 0.3V, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C
Sym
Parameter
Notes
2,4
Min
Typ(1)
3.26
Max
Units Test Conditions
Page Buffer Byte Write Time
Page Buffer Word Write Time
Word/Byte Program Time
Block Program Time
Note 6
Note 6
µs
µs
2,4
6.53
tWHRH
tWHRH
tWHRH
1
2
9
Note 6 µs
2
3
2
2
2
2
0.6
0.3
0.8
2.1
1.0
10
sec
sec
Byte Program
Word Program
Block Program Time
Block Erase Time
sec
sec
Full Chip Erase Time
51.2
7.0
Erase Suspend Latency Time
to Read
µs
Auto Erase Suspend Latency
Time to Program
10.0
µs
Erase Cycles
5
100,000 1,000,000
Cycles
V
CC = 5.0V ± 0.5V, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C
Sym
Parameter
Notes
Min
Typ(1)
2.76
5.51
6
Max
Note 6
Note 6
Note 6
2.1
Units Test Conditions
Page Buffer Byte Write Time
Page Buffer Word Write Time
Word/Byte Program Time
Block Program Time
2,4
2,4
2
µs
µs
µs
tWHRH
tWHRH
tWHRH
1
2
3
2
0.4
sec
sec
Byte Program
Word Program
Block Program Time
2
0.2
1.0
Block Erase Time
2
0.6
10
sec
sec
Full Chip Erase Time
2
38.4
5.0
Erase Suspend Latency Time
to Read
µs
Auto Erase Suspend Latency
Time to Program
8.0
µs
Erase Cycles
5
100,000 1,000,000
Cycles
NOTES:
1. +25°C, VCC = 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. This assumes using the full Page Buffer to program to the flash memory (256 bytes or 128words).
5. 1,000,000 cycle performance assumes the application uses block retirement techniques.
6. This information will be available in a technical paper. Please call Intel’s Application hotline or your local Intel sales office for
more information.
44
E
DD28F032SA
7.0 DERATING CURVES
290489-19.eps
290489-16.eps
Figure 19. ICC vs. Frequency (VCC = 3.6V) for x8
or x16 Operation
Figure 17. ICC vs. Frequency (VCC = 5.5V) for x8
or x16 Operation
290489-18.eps
290489-21.eps
Figure 18. ICC during Block Erase
Figure 20. IPP during Block Erase
45
DD28F032SA
E
290489-24.eps
Figure 21. Access Time (tACC) vs. Output Loading
290490-26.eps
290489-25.eps
Figure 23. IPP during Page Buffer Write
Operation
Figure 22. IPP during Word Write Operation
46
E
DD28F032SA
8.0 MECHANICAL SPECIFICATIONS
Z
A2
SEE DETAIL
O
O
e
E
Y
O
O
D1
A1
D
SEATING
PLANE
SEE DETAIL A
A
DETAIL B
DETAIL A
C
Ø
L
b
290490-26
Figure 24. Mechanical Specifications of the Dual Die 56-Lead TSOP Type I Package
Family: Dual Die Thin Small Out-Line Package
Symbol
Millimeters
Nominal
Notes
Minimum
Maximum
A
1.20
A
0.05
1
2
A
0.965
0.100
0.115
18.20
13.80
0.995
0.150
0.125
18.40
14.00
0.50
1.025
0.200
0.135
18.60
14.20
b
c
D
1
E
e
D
L
19.80
0.500
20.00
0.600
56
20.20
0.700
N
0°
3°
5°
Y
Z
0.100
0.350
0.150
0.250
47
DD28F032SA
E
APPENDIX A
DEVICE NOMENCLATURE/ORDERING INFORMATION
D D 2 8 F 0 3 2 S A - 0 7 0
DUAL DIE
ACCESS SPEED (ns)
70 ns
100 ns
NOTES:
Two valid combinations of speeds exist:
DD28F032SA-070, DD28F032SA-080, DD28F032SA-150
or
DD28F032SA-100, DD28F032SA-150
Option
Order Code
Valid Combinations
VCC = 3.3V
± 0.3V, 50 pF
VCC = 5.0V
± 5%, 30 pF
VCC = 5.0V
± 10%, 100 pF
1
2
DD28F032SA-070
DD28F032SA-100
DD28F032SA-150
DD28F032SA-150
DD28F032SA-070
DD28F032SA-080
DD28F032SA-100
48
E
DD28F032SA
APPENDIX B
ADDITIONAL INFORMATION
(1,2)
Order Number
297372
Document/Tool
16-Mbit Flash Product Family User’s Manual
28F016SA 16-Mbit FlashFile™ Memory Datasheet
28F016SV FlashFile™ Memory Datasheet
290489
290528
290429
28F008SA 8-Mbit FlashFile™ Memory Datasheet
AP-357 Power Supply Solutions for Flash Memory
AP-374 Flash Memory Write Protection Techniques
292092
292123
292124
AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA”
292126
AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV,
28F016XS, 28F016XD
292127
292144
292159
294016
AP-378 System Optimization Using the Enhanced Features of the 28F016SA
AP-393 28F016SV Compatibility with 28F016SA
AP-607 Multi-Site Layout Planning with Intel’s Flash File™ Components
ER-33 ETOX™ Flash Memory Technology– Insight to Intel’s Fourth Generation
Process Innovation
297534
Small and Low-Cost Power Supply Solutions for Intel’s Flash Memory Products
(Technical Paper)
297508
FLASHBuilder Design Resource Tool
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
49
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DD2B040HA2
Telecom and Datacom Connector, 40 Contact(s), Male, Right Angle, Surface Mount Terminal
JAE
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