DJCE6353882077_技术文档

CE6353

Nordig Unified DVB-T COFDM Terrestrial

Demodulator for

PC-TV and Hand-held Digital TV (DTV)

Data Sheet

February 2006

Features

•

Compliant with ETSI 300 744 DVB-T, Unified

Nordig and DTG performance specifications

Ordering Information

DJCE6353 882077

WJCE6353 882206

64 Pin LQFP Trays

64 Pin LQFP* Trays

DJCE6353 S L9EN 882128 64 Pin LQFP Tape and Reel

WJCE6353 S L9G5 882170 64 Pin LQFP* Tape and Reel

High performance with fast fully blind acquisition

and tracking capability

Low power consumption: less than 0.32 W, and

eco-friendly standby and sleep modes

*Pb Free Matte Tin

•

Digital filtering of adjacent channels

•

Pre and post Viterbi-decoder bit error rates, and

uncorrectable block count

Single 8 MHz SAW filter for 6, 7 & 8 MHz OFDM

Superior single frequency network performance

Fast AGC to track out signal fades

Good Doppler tracking capability

Enhanced frequency capture range to include

triple offsets

•

External 4 MHz clock or single low-cost

20.48 MHz crystal, tolerance up to +/-200 ppm

Automatic mode (2 K/8 K), guard and spectral

inversion detection

Very low driver software overhead due to on-chip

state-machine control

Novel RF level detect facility via a separate ADC

Figure 1 - Block Diagram

1

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Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

D55752-001

CE6353

Data Sheet

Applications

•

Digital terrestrial set-top boxes

Integrated digital televisions

Personal video recorders

PC-TV receivers

Portable applications

Description

The CE6353 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds,

with margin, the performance requirements of all known DVB-T digital terrestrial television standards, including

Unified Nordig and DTG.

A high performance 10 bit on-chip ADC is used to sample the 44 or 36 MHz IF analog signal. Advanced digital

filtering of the upper and lower channel enables a single 8 MHz channel SAW filter to be used for 6, 7 and 8 MHz

OFDM signal reception. All sampling and other internal clocks are derived from a single 20.48 MHz crystal or a 4

MHz clock input, the tolerance of which may be relaxed as much as 200 ppm.

The CE6353 has a wide frequency capture range able to automatically compensate for the combined offset

introduced by the tuner xtal and broadcaster triple frequency offsets.

An on-chip state machine controls all acquisition and tracking operations of the CE6353 as well as controlling the

tuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanism

ensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead.

Also included in the design is a 7-bit ADC to detect the RF signal strength and thereby efficiently control the tuner

RF AGC.

Users have access to all the relevant signal quality information, including input signal power level, signal-to-noise

ratio, pre-Viterbi BER, post-Viterbi BER, and the uncorrectable block counts. The error rate monitoring periods are

programmable over a wide range.

The device is packaged in a 10 x 10 mm 64-pin LQFP and is very low power.

2

Intel Corporation

CE6353

Data Sheet

Table of Contents

1.0 Pin & Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Pin Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Pin Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 IF to Baseband Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Adjacent Channel Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5 Interpolation and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6 Carrier Frequency Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Symbol Timing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.8 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.9 Common Phase Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10 Channel Equalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.11 Impulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.12 Transmission Parameter Signalling (TPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.13 De-Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.14 Symbol and Bit De-Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.15 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.16 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.17 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.18 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.19 De-scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.20 MPEG Transport Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.2 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.3 Examples of 2-Wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.4 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 Data Output Header Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 MPEG Data Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 MPEG Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.4 MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.5 MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4.1 Selection of External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4.1.1 Loop Gain Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4.1.2 List of Equation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4.1.3 Calculating Crystal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.1.4 Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.1.5 Oscillator/Clock Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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Intel Corporation

CE6353

Data Sheet

List of Figures

Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - Pin Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7 - MPEG Output Data Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11 - External Clocking via AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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Intel Corporation

CE6353

Data Sheet

List of Tables

Table 1 - Pin Names - numeric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2 - Pin Names - alphabetical order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3 - Timing of 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5

Intel Corporation

CE6353

Data Sheet

1.0 Pin & Package Details

1.1 Pin Outline

Figure 2 - Pin Outline

6

Intel Corporation

CE6353

Data Sheet

1.2 Pin Allocation

Function

Vss

17

Function

SADD1

Function

49

Function

1

2

3

4

5

6

7

8

9

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

Vdd

MDO0

Vdd

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SADD0

CVdd

Vss

RFLEV

CLK2/GPP0

DATA2/GPP1

CVdd

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

MDO1

MDO2

MDO3

MDO4

Vdd

Vss

CLK1

DATA1

IRQ

PLLVdd

PLLGND

XTI

Vss

CVdd

Vss

CVdd

Vss

XTO

Vss

MDO5

MDO6

MDO7

CVdd

Vss

RESET

SLEEP

STATUS

Vss

AGC2/GPP2

AGC1

10

11

12

13

14

15

16

PLLTEST

OSCMODE

AVdd

GPP3

SMTEST

Vdd

Vss

AGnd

VIN

MOCLK

BKERR

MICLK

CVdd

Vss

VIN

MOSTRT

MOVAL

AGnd

Table 1 - Pin Names - numeric

Function

42

Function

GPP3

43

Function

PLLTEST

26

Function

54

AGC1

Vdd

VIN

Vss

AGC2/GPP2

AGnd

41

29

32

28

62

4

IRQ

6

PLLVdd

RESET

RFLEV

SADD0

SADD1

N/C

21

9

30

31

1

MDO0

MDO1

MDO2

MDO3

MDO4

MDO5

MDO6

MDO7

MICLK

MOCLK

49

50

51

52

53

56

57

58

63

61

AGnd

34

18

17

16

15

12

10

44

11

AVdd

3

BKERR

CLK1

8

14

20

25

38

40

46

CLK2/GPP0

CVdd

35

7

N/C

CVdd

19

37

39

SLEEP

SMTEST

STATUS

CVdd

Table 2 - Pin Names - alphabetical order

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Intel Corporation

CE6353

Data Sheet

CVdd

59

64

5

MOSTRT

MOVAL

47

Vdd

2

Vss

XTI

55

60

23

24

CVdd

48

27

22

13

33

45

DATA1

OSCMODE

PLLGND

DATA2/GPP1

36

XTO

Table 2 - Pin Names - alphabetical order (continued)

1.3 Pin Description

Pin Description Table

Pin No

Name

Pin Description

I/O

Type

V

mA

MPEG pins

47

MOSTRT

MOVAL

MPEG packet start

O

I

1

3.3

5

48

MPEG data valid

MPEG data bus

MPEG clock out

Block error

49-53, 56-58

MDO(0:4)/MDO(5:7)

CMOS Tristate

61

62

63

11

MOCLK

BKERR

MICLK

STATUS

IRQ

MPEG clock in

Status output

CMOS

O

1

6

Interrupt output

Open drain

Control pins

4

Serial clock

I

CMOS

5

CLK1

5

Serial data

I/O Open drain

6

DATA1

23

Low phase noise oscillator

I

XTI

24

XTO

O

I

10

SLEEP

Device power down

Serial address set

Production test (only set low)

Serial clock tuner

Serial data tuner

3.3

5

12, 15-18

SADD(4:0)

SMTEST

CLK2/GPP0

DATA2/GPP1

AGC1

I

CMOS

I

44

35

36

42

41

43

9

I/O

6

5

Primary AGC

O

I/O

I

Open drain

5

AGC2/GPP2

GPP(3)

Secondary AGC

5

General purpose I/O

Device reset

5

CMOS

5

RESET

27

26

OSCMODE

Crystal oscillator mode

PLL analog test

I

CMOS

3.3

PLLTEST

O

(tristated)

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Intel Corporation

CE6353

Data Sheet

Pin Description Table (continued)

Pin No

Name

Pin Description

I/O

Type

V

mA

Analog inputs

30

VIN

positive input

I

31

negative input

RF level

VIN

34

I

RFLEV

Supply pins

21

PLLVdd

PLLGnd

CVdd

PLL supply

S

1.8

0

22

7, 19, 37, 39, 59, 64

2, 13, 45, 54,

Core logic power

I/O ring power

1.8

3.3

0

Vdd

1, 3, 8, 14, 20, 25,

38, 40, 46, 55, 60

Vss

Core and I/O ground

ADC analog supply

S

28

AVdd

AGnd

Vdd

S

1.8

0

29, 32

33

2nd ADC supply

3.3

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Intel Corporation

CE6353

Data Sheet

2.0 Functional Description

A functional block diagram of the CE6353 OFDM demodulator is shown in Figure 3. This accepts an IF analog

signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and

frequency synchronization operations are all digital and there are no analog control loops except the AGC. The

frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to

combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,

the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC

can be switched from one stream to another with minimal interruption to the transport stream.

Figure 3 - OFDM Demodulator Diagram

The FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder

separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to

provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures

minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi

and Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at

the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting

intervals of these are programmable over a very wide range.

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Intel Corporation

CE6353

Data Sheet

Figure 4 - FEC Block Diagram

The FSM controller shown in Figure 3 controls both the demodulator and the FEC. It also drives the 2-wire bus to

the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the

received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This

mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software

overhead in the host driver.

The algorithms and architectures used in the CE6353 have been optimized to minimize power consumption.

2.1 Analog-to-Digital Converter

The CE6353 has a high performance 10-bit analog-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz

bandwidth OFDM signal, with its spectrum centred at:

•

36.17 MHz IF

43.75 MHz IF

5 - 10 MHz near-zero IF

An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highly

programmable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.

2.2 Automatic Gain Control

An AGC module compares the absolute value of the digitized signal with a programmable reference. The error

signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which

has to be RC low-pass filtered to obtain the voltage to control the amplifier.

The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC

clipping and a small value results in excessive quantization noise. Hence the optimum value has been determined

assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit

theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This

reference or target value may have to be lowered slightly for some applications. Slope control bits have been

provided for the AGCs and these have to be set correctly depending on the gain-versus-voltage slope of the gain

control amplifiers.

11

Intel Corporation

CE6353

Data Sheet

The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking.

The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being

established. This is one of the features of CE6353 used to minimize acquisition time. A robust AGC lock

mechanism is provided and the other parts of the CE6353 begin to acquire only after the AGC has locked.

2.3 IF to Baseband Conversion

Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at

approximately 8.9 MHz. The first step of the demodulation process is to convert this signal to a complex (in-phase

and quadrature) signal in baseband. A correction for spectral inversion is implemented during this conversion

process. Note also that the CE6353 has control mechanisms to search automatically for an unknown spectral

inversion status.

2.4 Adjacent Channel Filtering

Adjacent channels, in particular the Nicam digital sound signal associated with analog channels, are filtered prior to

the FFT.

2.5 Interpolation and Clock Synchronization

CE6353 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the

signal at a fixed rate, for example, 45.056 MHz. Conversion of the 45.056 MHz signal to the OFDM sample rate is

achieved using the time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by

factors 6/8 and 7/8 for 6 and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is

programmed in a CE6353 register (defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phase

locked loop in the CE6353 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the

sampling clock.

2.6 Carrier Frequency Synchronization

There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to

broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes,

without the need for an analog frequency control (AFC) loop.

The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these values

can be increased, if necessary, by programming an on-chip register (see 7.4.1). It is recommended that a larger

capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to

adjust the tuner. After the OFDM module has locked (the AFC will have been previously disabled), the frequency

offset can be read from an on-chip register.

2.7 Symbol Timing Synchronization

This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-

symbol interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated

to dynamically adapt to time-variations in the transmission channel.

2.8 Fast Fourier Transform

The FFT module uses the trigger information from the timing synchronization module to set the start point for an

FFT. It then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain. An

extremely hardware-efficient and highly accurate algorithm has been used for this purpose.

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Intel Corporation

CE6353

Data Sheet

2.9 Common Phase Error Correction

This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of

the tuner phase noise on system performance.

2.10 Channel Equalization

This consists of two parts. The first part involves estimating the channel frequency response from pilot information.

Efficient algorithms have been used to track time-varying channels with a minimum of hardware.

The second part involves applying a correction to the data carriers based on the estimated frequency response of

the channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.

2.11 Impulse Filtering

CE6353 contains several mechanisms to reduce the impact of impulse noise on system performance.

2.12 Transmission Parameter Signalling (TPS)

An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS

carriers in every symbol and all these carry one bit of TPS. These bits, when combined, include information about

the transmission mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition,

the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are

in odd frames. The TPS module extracts all the TPS data, and presents these to the host processor in a structured

manner.

2.13 De-Mapper

This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature

components of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithm

depends on the constellation (QPSK, 16QAM or 64QAM) and the hierarchy (α = 0, 1, 2 or 4). Soft decisions for both

low- and high-priority data streams are generated.

2.14 Symbol and Bit De-Interleaving

The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-

interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions

to the FEC in the original order.

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Intel Corporation

CE6353

Data Sheet

2.15 Viterbi Decoder

The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream.

The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branch

metrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor

memory. The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-back

depth of 128 is used to minimize any loss in performance, especially at high code rates.

The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors

at its input, on the assumption that the Viterbi output BER is significantly lower than its input BER.

2.16 MPEG Frame Aligner

The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to

ensure correct lock and to prevent loss of lock due to noise impulses.

2.17 De-interleaver

Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a

number of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The de-

interleaver is a memory unit which implements the inverse of the convolutional interleaving function introduced by

the transmitter.

2.18 Reed-Solomon Decoder

Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a

systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of

correcting up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors.

In addition to efficiently performing this decoding function, the Reed-Solomon decoder in CE6353 keeps a count of

the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This

information can be used to compute the post-Viterbi BER.

2.19 De-scrambler

The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a

pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transport packets. The TEI bit of the packet

header may be set if required to indicate uncorrectable packets.

2.20 MPEG Transport Interface

MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present

the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard

ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the CE6353

with a clock provided by the user.

14

Intel Corporation

CE6353

Data Sheet

3.0 Interfaces

3.1 2-Wire Bus

3.1.1 Host

The primary 2-wire bus serial interface uses pins:

•

DATA1 (pin 5) serial data, the most significant bit is sent first.

CLK1 (pin 4) serial clock.

The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.

In TNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:

ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1]

Not programmable

VSS VDD

SADD[1] SADD[0]

VDD VDD

VSS

VDD

When the CE6353 is powered up, the RESET pin 9 should be held low for at least 50 ms after VDD has reached

normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus

address. ADDR[0] is the R/W bit.

The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive

mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD

register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following

byte. Not all addresses are valid and many are reserved registers that must not be changed from their default

values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access

the reserved registers accidentally.

Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address

is not recognized, the CE6353 will ignore all activity until a valid chip address is received. The 2-wire bus START

command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a

particular read register with a write command, followed immediately with a read data command. If required, this

could next be followed with a write command to continue from the latest address. RADD would not be sent in this

case. Finally, a STOP command should be sent to free the bus.

When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out

is the contents of register 00.

3.1.2 Tuner

The CE6353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. See register

GPP_CTL address 0x8C.

Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.

The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.

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Intel Corporation

CE6353

Data Sheet

3.1.3 Examples of 2-Wire Bus Messages

KEY:

S

Start condition

Stop condition

Acknowledge

CE6353 output

W

R

Write (= 0)

Read (= 1)

P

A

NA

NOT Acknowledge

Italics

RADD Register Address

Write operation - as a slave receiver:

S

DEVICE

W

A

RADD

(n)

A

DATA

A

DATA

(reg n+1)

A

P

ADDRESS

(reg n)

Read operation - CE6353 as a slave transmitter:

S

DEVICE

R

A

DATA

A

DATA

A

DATA NA

P

ADDRESS

(reg 0)

(reg 1)

(reg 2)

Write/read operation with repeated start - CE6353 as a slave transmitter:

S

DEVICE

W

A

RADD

(n)

A

S

DEVICE

R

A

DATA

A

DATA

NA

P

ADDRESS

(reg n)

(reg n+1)

3.1.4 Primary 2-Wire Bus Timing

t_BUFF

Sr

P

DATA1

t_LOW

t_R

t_F

CLK1

P

S

t_SU;STO

t_HIGH

t_SU;DATt_SU;STA

t_HD;STA

t_HD;DAT

Figure 5 - Primary 2-Wire Bus Timing

Where:

S = Start

Sr = Restart, i.e., start without stopping first.

P = Stop.

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Intel Corporation

CE6353

Data Sheet

Value

Parameter

Symbol

Unit

Min.

Max.

CLK clock frequency (Primary)

f_CLK

0

400 ¹

kHz

ns

Bus free time between a STOP and START condition.

Hold time (repeated) START condition.

LOW period of CLK clock.

t_BUFF

t_HD;STA

t_LOW

200

1300

600

200

100

HIGH period of CLK clock.

t_HIGH

Set-up time for a repeated START condition.

Data hold time (when input).

t_SU;STA

t_HD;DAT

t_SU;DAT

t_R

Data set-up time

Rise time of both CLK and DATA signals.

note ²

Fall time of both CLK and DATA signals, (100 pF to ground). t_F

Set-up time for a STOP condition. t_SU;STO

Table 3 - Timing of 2-Wire Bus

20

200

1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.

2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.

17

Intel Corporation

CE6353

Data Sheet

3.2 MPEG

3.2.1 Data Output Header Format

188 byte packet output

184 Transport packet bytes

Transport

Packet

Header

4 bytes

1st byte

2nd byte

0

1

0

1

TEI

MDO[7]

MDO[0]

Figure 6 - DVB Transport Packet Header Byte

After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.

Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any

uncorrectable packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note

that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at

output).

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Intel Corporation

CE6353

Data Sheet

3.2.2 MPEG Data Output Signals

The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in

the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running

clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 with

MOCLKINV = ‘1’, the default state, see register 0x50.

All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK

(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.

A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during

the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of

a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet

where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.

188 byte packet n

1st byte packet n

MOCLKINV=1

1st byte packet n+1

MOCLK

MDO7:0

MOSTRT

MOVAL

BKERR

Tp

Ti

Figure 7 - MPEG Output Data Waveforms

3.2.3 MPEG Output Timing

Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80^oC, Output load = 10pF.

Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10^oC, Output load = 10pF.

MOCLK frequency = 45.06 MHz.

19

Intel Corporation

CE6353

Data Sheet

3.2.4 MOCLKINV = 1

Delay conditions

Maximum Minimum

Parameter

Units

Data output delay t_D

Setup Time t_SU

Hold Time t_H

3.0

7.0

1.0

10.0

ns

MOCLK

t_D

MDO

MOSTRT

MOVAL

BKERRB

BKERR

}

t_SU

t_H

Figure 8 - MPEG Timing - MOCLKINV = 1

3.2.5 MOCLKINV = 0

MDOSWAP = 0

Delay conditions

Units

Parameter

Maximum

Minimum

Data output delay t_D

Setup Time t_SU

Hold Time t_H

3.0

1.0

18.0

1.0

20.0

0.2

ns

The hold time is better when MOCLKINV = 1, therefore this should be used if possible.

MOCLK

t_D

MDO

MOSTRT

MOVAL

BKERRB

BKERR

}

t_SU

t_H

Figure 9 - MPEG Timing - MOCLKINV = 0

20

Intel Corporation

CE6353

Data Sheet

4.0 Electrical Characteristics

4.1 Recommended Operating Conditions

Parameter

Symbol

Min.

3.0

Typ.

Max.

Units

3.3

1.8

3.6

Power supply voltage:

periphery

core

VDD

CVDD

IDD_P

IDD_C

XTI

V

1.62

1.98

Power supply current:

periphery ¹

core

mA

mA ²

MHz

kHz

°C

1

170

20.48

Input clock frequency ³

16.00

-10

25.00

400

80

CLK1 primary serial clock frequency ⁴

Ambient operating temperature

fCLK

1. Current from the 3.3 V supply will be mainly dependent on the external loads.

2. Current given is for optimum performance, lower current is possible with reduced performance.

3. The min/max frequencies given are those supported by the oscillator cell. Required system frequencies are as defined in the design

manual. Frequencies outside these limits are acceptable with an external clock signal.

4. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.

4.2 Absolute Maximum Ratings

Maximum Operating Conditions

Parameter

Symbol

Min.

Max.

Unit

Power supply

VDD

CVDD

VI

-0.3

-55

+3.6

+2.0

V

Voltage on input pins (5 V rated)

Voltage on input pins (3.3 V rated)

Voltage on output pins (5 V rated)

Voltage on output pins (3.3 V rated)

Storage temperature

5.5

V

VI

VDD + 0.3

5.5

V

VO

V

VO

VDD + 0.3

150

V

TSTG

TOP

TJ

°C

Operating ambient temperature

Junction temperature

-10

80

125

Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for

extended periods may reduce reliability. Functionality at or above these conditions is not implied.

21

Intel Corporation

CE6353

Data Sheet

4.3 DC Electrical Characteristics

DC Electrical Characteristics

Parameter

Conditions

Pins

Symbol

VDD

Min.

Typ.

Max. Unit

Operating

periphery

3.0

3.3

3.6

V

voltage

core

CVDD

1.62

1.8

170

300

1.98

V

Supply current ¹

1.62>CVDD>1.98

IDDCORE

mA

μA

Supply current sleep mode

Outputs

Output levels

IOH 2mA

3.0>VDD>3.6

MDO(7:0), MOVAL, VOH

MOSTRT, MOCLK,

2.4

V

STATUS, BKERR

IOL 2mA

3.0>VDD>3.6

VOL

0.4

IOL 6mA

3.0>VDD>3.6

GPP(3:0), DATA1,

AGC1, AGC2, IRQ

VOL

V

Output capacitance

Not including track MDO(7:0), MOVAL,

MOSTRT, MOCLK,

3.0

3.6

pF

STATUS, BKERR

GPP(3:0), DATA1,

AGC1, AGC2,IRQ

pF

Output leakage (tri-state)

Inputs

1

μA

Input levels

3.0>VDD>3.6

-0.5 ≥ Vin ≥

VDD+0.5V

MICLK, SADD(4:0) VIH

SLEEP, OSCMODE

2.0

V

Input levels

3.0>VDD>3.6

-0.5 ≥ Vin ≥ +5.5V DATA1, RESET

GPP(3:0), CLK1,

VIH

VIL

Input levels

3.0>VDD>3.6

All inputs

0.8

±1

V

Input leakage Current

Input capacitance

SLEEP, SMTEST,

MICLK, CLK1,

OSCMODE

μA

pF

Capacitances do

not include track

1.8

3.6

Input capacitance

SADD(4:0), DATA1,

GPP(3:0)

pF

1. Current given is for optimum performance, lower current is possible with reduced performance.

4.4 Crystal Specification and External Clocking

Parallel resonant fundamental frequency (preferred)

Tolerance over operating temperature range

Tolerance overall

20.4800 MHz

± 150 ppm

± 200 ppm

27 pF

Typical load capacitance

Drive level

Equivalent series resistance

0.4 mW max

<25 Ω

22

Intel Corporation

CE6353

Data Sheet

XTI

XT0

OSCMODE

XTI

C1

C2

Figure 10 - Crystal Oscillator Circuit

4.4.1 Selection of External Components

The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is

greater than unity. Correct selection of the two capacitors is very important and the following method is

recommended to obtain values for C1 and C2.

4.4.1.1 Loop Gain Equation

Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to

ensure that oscillations will occur across all variations in temperature, process and supply voltage, and that the

circuit will exhibit good start-up characteristics.

C

_out.g_m

C_in

C_out+ C_in

R_f.C_in

1

-1

Equation 1 - - A =

+

Z_in

Z_o

1

Equation 2 -

- Z_in=

(2.π.f.C_out)².ESR

4.4.1.2 List of Equation Parameters

A

total loop gain (between 5 and 25)

C1 + Cpar

Cin

Cout C2 + Cpar

Cpar parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track

capacitances, package capacitance and cell input capacitance. Normally Cpar ≈ 4pF.

Zo

gm

Rf

9.143 kΩ - output impedance of amplifier at 1.8 V operation - typical

8.736 mA/V - transconductance of amplifier at 1.8 V operation -typical

2.3 MΩ - internal feedback resistor

ESR

f

maximum equivalent series resistance of crystal - given by crystal manufacturer (Ω)

fundamental frequency of crystal (Hz)

23

Intel Corporation

CE6353

Data Sheet

4.4.1.3 Calculating Crystal Power Dissipation

To calculate the power dissipated in a crystal the following equation can be used.

2

V_pp

P_c=

Equation 3 -

8.Z_in

Pc = power dissipated in crystal at resonant frequency (W)

Vpp = maximum peak to peak output swing of amplifier is 1.8 V for all CVDD

Zin = crystal network impedance (see Equation 2)

4.4.1.4 Capacitor Values

Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with

Equation 4 below.

g_m

A

2

1

.

C_in= C_out

=

Equation 4 -

-

(2.π.f)².ESR

when: C₁= C₂= C_out- C_par

R_fZ_o

Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.

Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the

resulting crystal load capacitance C_L(see Equation 5) is close to the crystal manufacturers recommended C_L

(standard values for C_Lare 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency.

C_out. C_in

- C_L=

C_par12

+

Equation 5 -

C_out+ C_in

C_par12= parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin

capacitance (including any socket used) and the printed circuit board’s track-to-track capacitance.

C_par12≈ 2pF.

If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s

recommended C_Lmay be acceptable. Larger values of C_Ltend to reduce the influence of circuit variations and

tolerances on frequency stability. Smaller values of C_Ltend to reduce startup time and crystal power dissipation.

Care must however be taken that C_Ldoes not fall outside the crystal pulling range or the circuit may fail to start up

altogether. It is also possible to quote C_Lto the crystal manufacturer who can then cut a crystal to order which will

resonate, under the specified load conditions, at the desired frequency.

Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is

not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain

condition is still satisfied. This must be done using Equation 1.

C₂

Note:

2 >

> 0.5

C₁

24

Intel Corporation

CE6353

Data Sheet

4.4.1.5 Oscillator/Clock Application Notes

•

On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible.

Other signal tracks must not be allowed to cross through this area. The component tracks should preferably

be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal

pins. It is also advisable to provide a ground plane for the circuit to reduce noise.

•

External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0V and CVDD)

and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell’s

amplitude clamping circuit.

An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To

limit the current taken from the signal source a resistor should be placed between the clock source and XTI.

The recommended value for this series resistor is 470 Ω for a clock signal switching between 0 V and

CVDD. The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left

unconnected in this configuration.

•

AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty

cycle of the OSCOUT signal cannot be guaranteed in such a configuration.

AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that

the circuit shown in Figure 11 be used to correctly bias the oscillator inputs: The common-mode voltage VCM

for XTI and XTO, (set by the 36 kΩ and 22 kΩ resistors) must be 800 mV < VCM < CVDD and the amplitude

Vpp of the clock signal must be >100 mV.

XTO

XTI

Vdd

OSCMODE

36k

100k

10nF

External clock

22k

10nF

Figure 11 - External Clocking via AC Coupling

•

External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode

voltage VCM for the differential clock signals must be 800 mV < VCM < CVDD, and the peak-to-peak signal

amplitude Vpp must be >100 mV. It is recommended that differential clock signals have VCM = 1.0V. For

Vpp > 400 mV a resistor of >390 Ω in series with XTI or XTO may be required to limit the current taken from

or supplied to the clock sources.

25

Intel Corporation

CE6353

Data Sheet

5.0 Application Circuit

Figure 12 - Typical Application Circuit

26

Intel Corporation


型号：	DJCE6353882077
厂家：	INTEL
描述：	Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV) NorDig统一DVB -T COFDM地面解调器为PC-TV和手持式数字电视（ DTV ）电视 PC
文件：	总26页 (文件大小：470K)
中文：	中文翻译
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DJCE6353882077 [INTEL]

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