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E28F016SV-080 [INTEL]

16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY; 16 - MBIT （1 MBIT ×16 ， 2 MBIT ×8） FlashFile记忆
E28F016SV-080
型号： E28F016SV-080
厂家： INTEL    INTEL
描述：

16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
16 - MBIT （1 MBIT ×16 ， 2 MBIT ×8） FlashFile记忆

闪存 存储 内存集成电路 光电二极管
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E
28F016SV  
16-MBIT (1 MBIT x 16, 2 MBIT x 8)  
FlashFile™ MEMORY  
Includes Commercial and Extended Temperature Specifications  
SmartVoltage Technology  
Backwards-Compatible with 28F016SA,  
28F008SA Command Set  
User-Selectable 3.3V or 5V VCC  
User-Selectable 5V or 12V VPP  
Revolutionary Architecture  
Multiple Command Execution  
Program during Erase  
Command Super-Set of the Intel  
28F008SA  
65 ns Access Time  
1 Million Erase Cycles per Block  
30.8 MB/sec Burst Write Transfer Rate  
Page Buffer Program  
0.48 MB/sec Sustainable Write Transfer  
Rate  
2 µA Typical Deep Power-Down  
32 Independently Lockable Blocks  
Configurable x8 or x16 Operation  
56-Lead TSOP and SSOP Type I  
Packages  
State-of-the-Art 0.6 µm ETOX™ IV Flash  
Technology  
Intel’s 28F016SV 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for  
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative  
capabilities, low-power operation, user-selectable VPP voltage and high read/program performance, the  
28F016SV enables the design of truly mobile, high-performance personal computing and communications  
products.  
The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state  
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and  
28F016SA 16-Mbit FlashFile memories), extended cycling, flexible VCC and VPP voltage (SmartVoltage  
technology), fast program and read performance and selective block locking, provide a highly-flexible memory  
component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives.  
The 28F016SV’s dual read voltage enables the design of memory cards which can be read/written in 3.3V  
and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor  
interface. The flexible block locking option enables bundling of executable application software in a Resident  
Flash Array or memory card. The 28F016SV is manufactured on Intel’s 0.6 µm ETOX IV process technology.  
July 1997  
Order Number: 290528-007  
7/11/97 11:03 AM 29052807.DOC  
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or  
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of  
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to  
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or  
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life  
saving, or life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
The 28F016SV may contain design defects or errors known as errata which may cause the product to deviate from published  
specifications. Current characterized errata are available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be  
obtained from:  
Intel Corporation  
P.O. Box 7641  
Mt. Prospect, IL 60056-7641  
or call 1-800-879-4683  
or visit Intel’s Website at http:\\www.intel.com  
COPYRIGHT © INTEL CORPORATION, 1997  
CG-041493  
*Third-party brands and names are the property of their respective owners.  
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28F016SV FlashFile™ MEMORY  
CONTENTS  
PAGE  
PAGE  
1.0 INTRODUCTION .............................................7  
1.1 Enhanced Features......................................7  
1.2 Product Overview.........................................7  
5.0 ELECTRICAL SPECIFICATIONS..................25  
5.1 Absolute Maximum Ratings........................25  
5.2 Capacitance ...............................................26  
5.3 DC Characteristics (VCC = 3.3V ± 0.3V) .....29  
2.0 DEVICE PINOUT.............................................9  
5.4 DC Characteristics (VCC = 5V ± 0.5V)  
5V ± 0.25V) ..................................................33  
2.1 Lead Descriptions ......................................11  
5.5 Timing Nomenclature .................................37  
5.6 AC Characteristics—Read Only Operations38  
5.7 Power-Up and Reset Timings.....................43  
3.0 MEMORY MAPS ...........................................15  
3.1 Extended Status Registers Memory Map ...16  
4.0 BUS OPERATIONS, COMMANDS AND  
STATUS REGISTER DEFINITIONS................17  
5.8 AC Characteristics for WE#—Controlled  
Command Write Operations .........................44  
4.1 Bus Operations for Word-Wide Mode  
(BYTE# = VIH)..............................................17  
5.9 AC Characteristics for CE#—Controlled  
Command Write Operations ........................49  
)
4.2 Bus Operations for Byte-Wide Mode  
(BYTE# = VIL)...............................................17  
5.10 AC Characteristics for WE#—Controlled  
Page Buffer Program Operations..................54  
4.3 28F008SA—Compatible Mode Command  
Bus Definitions .............................................18  
5.11 AC Characteristics for CE#—Controlled  
Page Buffer Program Operations..................56  
4.4 28F016SV—Performance Enhancement  
Command Bus Definitions............................19  
5.12 Erase and Word/Byte Program  
Performance.................................................58  
4.5 Compatible Status Register........................21  
4.6 Global Status Register ...............................22  
4.7 Block Status Register.................................23  
4.8 Device Configuration Code.........................24  
6.0 MECHANICAL SPECIFICATIONS.................60  
APPENDIX A: Device Nomenclature and  
Ordering Information .....................................61  
APPENDIX B: Ordering Information .................63  
3
28F016SV FlashFile™ MEMORY  
E
REVISION HISTORY  
Number  
Description  
Original Version  
-001  
-002  
Added 28F016SV-065/-070 at 5V VCC and 28F016SV-075 at 3.3V VCC  
Improved burst write transfer rate to 30.8 MB/sec.  
Added 56-lead SSOP Type I packaging information.  
Changed VPPLK from 2V to 1.5V.  
.
Increased ICCR at 5V VCC and 3.3V VCC  
:
I
I
I
I
CCR1 from 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) @ VCC = 3.3V  
CCR2 from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) @ VCC = 3.3V  
CCR1 from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) @ VCC = 5V  
CCR2 from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) @ VCC = 5V  
Moved AC Characteristics for Extended Register Reads into separate table.  
Increased VPP MAX from 13V to 14V.  
Added Erase Suspend Command Latency times to Section 5.12  
Modified Device Nomenclature Section to include SSOP package option and Ordering  
Information  
Changed definition of “NC.” Removed “No internal connection to die” from description.  
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.  
-003  
Added Note to Sleep Command (Section 4.4) denoting that the chip must be de-selected  
in order for the power consumption in sleep mode to reach deep power-down  
levels.  
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.  
Increased IPPR (VPP Read Current) for VPP> VCC to 200 µA at VCC = 3.3V and VCC = 5V  
Changed VCC = 5V DC Characteristics (Section 5.5) marked with Note 1 to indicate  
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns  
and a TTL rise/fall time of <10 ns.  
Corrected the graphical representation of tWHGL and tEHGL in Figures 15 and 16.  
Increased Typical “Page Buffer Byte/Word Program Times” from 6.0 µs to 8.0 µs (Byte)  
and 12.1 µs to 16.0 µs (Word) @ VCC = 3.3V/5V and VPP = 5V:  
Increased Typ. “Byte/Word Program Times” (tWHRH1A/tWHRH1B) for VPP = 5V (Section  
5.12)  
t
t
WHRH1A from 16.5 µs to 29.0 µs and tWHRH1B from 24.0 µs to 35.0 µs at VCC =3.3V  
WHRH1A from 11.0 µs to 20.0 µs and tWHRH1B from 16.0 µs to 25.0 µs at VCC = 5V  
Increased Typical “Block Program Times” (t WHRH2/tWHRH3)for VPP =5V (Section 5.12):  
t
t
WHRH2 from 1.1 sec to 1.9 sec and t WHRH3 from 0.8 sec to 1.2 sec at VCC = 3.3V  
WHRH2 from 0.8 sec to 1.4 sec and t WHRH3 from 0.6 sec to 0.85 sec at VCC = 5V  
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase  
Suspend Latency Time to Read;” modified typical values and added Min/Max  
values at VCC =3.3/5V and VPP =5V/12V (Section 5.12)  
Added “Erase Suspend Latency Time to Program” Specifications to Section 5.12  
Minor cosmetic changes throughout document  
4
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28F016SV FlashFile™ MEMORY  
REVISION HISTORY (Continued)  
Number  
Description  
-004  
Added 3/5# pin to Block Diagram (Figure 1), Pinout Configurations (Figures 2 and 3),  
Product Overview (Section 1.1) and Lead Descriptions (Section 2.1)  
Added 3/5# pin to Test Conditions of ICCS Specifications  
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.5)  
Increased tPHQV Specifications at 5V VCC to 400 ns for E28F016SV 065 devices  
and 480 ns for E28F106SV 070 devices.  
Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t5VPH  
and t3VPH specifications; Added tPLYL, tPLYH, tYLPH, and tYHPH specifications  
Added tPHEL3 and tPHEL5 specifications to Power-Up and Reset Timings (Section 5.9)  
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)  
Corrected SSOP Mechanical Spec. B (max) from 0.20 mm to 0.40 mm (Section 6.0)  
Minor cosmetic changes throughout document.  
-005  
Updated DC Specifications: ICCD, IPPES  
Updated AC Specifications: Page Buffer Reads: (tAVAV, tAVQV, tELQV, and tFLQV/tFHQV)  
Page Buffer WE#-Controlled Command Writes (tELWL  
)
CE#-Controlled Command Write Parameters (tAVAV, tELEH, tEHEL  
)
Combined Commercial and Extended Temperature information into single datasheet.  
Updated AC Specifications: Page Buffer Reads: (tAVAV, tAVQV, tELQV, and tFLQV/tFHQV)  
Updated Disclaimer  
-006  
-007  
5
28F016SV FlashFile™ MEMORY  
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6
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28F016SV FlashFile™ MEMORY  
The implementation of a new architecture, with  
many enhanced features, will improve the device  
operating characteristics and result in greater  
product reliability and ease-of-use.  
1.0 INTRODUCTION  
The documentation of the Intel 28F016SV memory  
device includes this datasheet, a detailed user’s  
manual, and a number of application notes and  
design tools, all of which are referenced in  
Appendix B.  
The 28F016SV  
technology, providing VCC operation at both 3.3V  
and 5V and program and erase capability at VPP  
12V or 5V. Operating at VCC 3.3V, the  
incorporates  
SmartVoltage  
=
=
The datasheet is intended to give an overview of  
the chip feature-set and of the operating AC/DC  
specifications. The 16-Mbit Flash Product Family  
User’s Manual provides complete descriptions of  
the user modes, system interface examples and  
detailed descriptions of all principles of operation.  
It also contains the full list of software algorithm  
flowcharts, and a brief section on compatibility  
with the Intel 28F008SA.  
28F016SV consumes approximately one half the  
power consumption at 5V VCC, while 5V VCC  
provides the highest read performance capability.  
VPP = 5V operation eliminates the need for a  
separate 12V converter, while VPP  
maximizes program/erase performance.  
=
12V  
In  
addition to the flexible program and erase  
voltages, the dedicated VPP gives complete code  
protection with VPP ≤ VPPLK  
.
A significant 28F016SV change occurred between  
datasheet revisions 290528-003 and 290528-004.  
This change centers around the addition of a 3/5#  
pin to the device’s pinout configuration. Figures 2  
and 3 show the 3/5# pin assignment for TSOP and  
SSOP Type 1 packages. Intel recommends that all  
customers obtain the latest revisions of 28F016SV  
documentation.  
A 3/5# input pin configures the device’s internal  
circuitry for optimal 3.3V or 5V read/program  
operation.  
A Command User Interface (CUI) serves as the  
system interface between the microprocessor or  
microcontroller and the internal memory operation.  
Internal Algorithm Automation allows byte/word  
programs and block erase operations to be  
1.1 Enhanced Features  
executed using  
a
Two-Program command  
sequence to the CUI in the same way as the  
28F008SA 8-Mbit FlashFile™ memory.  
The 28F016SV is backwards compatible with the  
28F016SA and offers the following enhancements:  
A super-set of commands has been added to the  
basic 28F008SA command-set to achieve higher  
program performance and provide additional  
capabilities. These new commands and features  
include:  
•
SmartVoltage Technology  
Selectable 5V or 12V VPP  
•
•
VPP Level Bit in Block Status Register  
Additional RY/BY# Configuration  
Pulse-On-Program/Erase  
•
•
•
•
•
Page Buffer Programs to Flash  
Command Queuing Capability  
•
Additional Upload Device Information  
Command Feedback  
Automatic Data Programs during Erase  
Software Locking of Memory Blocks  
Device Proliferation Code  
Device Configuration Code  
Two-Byte Successive Programs in 8-bit  
Systems  
•
Erase All Unlocked Blocks  
1.2 Product Overview  
Writing of memory data is performed in either byte  
or word increments typically within µs  
(12V  
PP)—a 33% improvement over the  
28F008SA. A block erase operation erases one of  
the 32 blocks in typically 0.6 sec (12V VPP),  
independent of the other blocks, which is about a  
65% improvement over the 28F008SA.  
The 28F016SV is a high-performance, 16-Mbit  
(16,777,216-bit) block erasable, nonvolatile  
random access memory, organized as either  
1 Mword x 16 or 2 Mbyte x 8. The 28F016SV  
includes thirty-two 64-KB (65,536 byte) blocks or  
thirty-two 32-KW (32,768 word) blocks. A chip  
memory map is shown in Figure 4.  
6
V
7
28F016SV FlashFile™ MEMORY  
E
Each block can be written and erased a minimum  
of 100,000 cycles. Systems can achieve one  
million Block Erase Cycles by providing wear-  
leveling algorithms and graceful block retirement.  
These techniques have already been employed in  
many flash file systems and hard disk drive  
designs.  
•
32 Block Status Registers (BSRs) which  
provide block-specific status information such  
as the block lock-bit status.  
The GSR and BSR memory maps for byte-wide  
and word-wide modes are shown in Figures 5  
and 6.  
The 28F016SV incorporates two Page Buffers of  
256 bytes (128 words) each to allow page data  
programs. This feature can improve a system  
program performance by up to 4.8 times over  
previous flash memory devices, which have no  
Page Buffers.  
The 28F016SV incorporates an open drain  
RY/BY# output pin. This feature allows the user to  
OR-tie many RY/BY# pins together in a multiple  
memory configuration such as a Resident Flash  
Array.  
Other configurations of the RY/BY# pin are  
enabled via special CUI commands and are  
described in detail in the 16-Mbit Flash Product  
Family User’s Manual.  
All operations are started by a sequence of  
Program commands to the device. Three Status  
Registers (described in detail later in this  
datasheet) and a RY/BY# output pin provide  
information on the progress of the requested  
operation.  
The 28F016SV’s enhanced Upload Device  
Information command provides access to  
additional information that the 28F016SA  
previously did not offer. This command uploads  
the Device Revision Number, Device Proliferation  
Code and Device Configuration Code to the page  
buffer. The Device Proliferation Code for the  
28F016SV is 01H, and the Device Configuration  
Code identifies the current RY/BY# configuration.  
Section 4.4 documents the exact page buffer  
address locations for all uploaded information. A  
subsequent Page Buffer Swap and Page Buffer  
Read command sequence is necessary to read  
the correct device information.  
While the 28F008SA requires an operation to  
complete before the next operation can be  
requested, the 28F016SV allows queuing of the  
next operation while the memory executes the  
current operation. This eliminates system  
overhead when writing several bytes in a row to  
the array or erasing several blocks at the same  
time. The 28F016SV can also perform program  
operations to one block of memory while  
performing erase of another block.  
The 28F016SV provides selectable block locking  
to protect code or data such as Device Drivers,  
PCMCIA card information, ROM-Executable O/S  
or Application Code. Each block has an  
associated nonvolatile lock-bit which determines  
the lock status of the block. In addition, the  
28F016SV has a master Write Protect pin (WP#)  
which prevents any modifications to memory  
blocks whose lock-bits are set.  
The 28F016SV also incorporates a dual chip-  
enable function with two input pins, CE0# and  
CE1#. These pins have exactly the same  
functionality as the regular chip-enable pin, CE#,  
on the 28F008SA. For minimum chip designs,  
CE1# may be tied to ground and system logic may  
use CE0# as the chip enable input. The 28F016SV  
uses the logical combination of these two signals  
to enable or disable the entire chip. Both CE0# and  
CE1# must be active low to enable the device. If  
either one becomes inactive, the chip will be  
disabled. This feature, along with the open drain  
RY/BY# pin, allows the system designer to reduce  
the number of control pins used in a large array of  
16-Mbit devices.  
The 28F016SV contains three types of Status  
Registers to accomplish various functions:  
•
A Compatible Status Register (CSR) which is  
100% compatible with the 28F008SA FlashFile  
memory Status Register. The CSR, when used  
alone, provides  
a straightforward upgrade  
capability to the 28F016SV from a 28F008SA-  
based design.  
The BYTE# pin allows either x8 or x16  
read/programs to the 28F016SV. BYTE# at logic  
low selects 8-bit mode with address A0 selecting  
between the low byte and high byte. On the other  
hand, BYTE# at logic high enables 16-bit  
operation with address A1 becoming the lowest  
•
A Global Status Register (GSR) which informs  
the system of command Queue status, Page  
Buffer status, and overall Write State Machine  
(WSM) status.  
8
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28F016SV FlashFile™ MEMORY  
order address and address A0 is not used (don’t  
care). A device block diagram is shown in Figure  
1.  
operation) is required from RP# switching high  
until outputs are again valid. In the Deep Power-  
Down state, the WSM is reset (any current  
operation will abort) and the CSR, GSR and BSR  
registers are cleared.  
The 28F016SV is specified for a maximum access  
time of 65 ns (tACC) at 5V operation (4.75V to  
5.25V) over the commercial temperature range  
(0°C to +70°C). A corresponding maximum access  
time of 75 ns at 3.3V (3.0V to 3.6V and 0°C to  
+70°C) is achieved for reduced power  
consumption applications.  
A CMOS standby mode of operation is enabled  
when either CE0# or CE1# transitions high and  
RP# stays high with all input control pins at CMOS  
levels. In this mode, the device typically draws an  
I
CC standby current of 70 µA at 5V VCC.  
The 28F016SV incorporates an Automatic Power  
Saving (APS) feature, which substantially reduces  
the active current when the device is in static  
mode of operation (addresses not switching). In  
APS mode, the typical ICC current is 1 mA at 5V  
(3.0 mA at 3.3V).  
The 28F016SV will be available in 56-lead,  
1.2 mm thick, 14 mm x 20 mm TSOP and 56-lead,  
1.8 mm thick, 16 mm x 23.7 SSOP Type I  
packages. The form factor and pinout of these two  
packages allow for very high board layout  
densities.  
A deep power-down mode of operation is invoked  
when the RP# (called PWD# on the 28F008SA)  
pin transitions low. This mode brings the device  
power consumption to less than 2.0 µA, typically,  
and provides additional program protection by  
2.0 DEVICE PINOUT  
The 28F016SV 56-lead TSOP and 56-lead SSOP  
Type I pinout configurations are shown in Figures  
2 and 3.  
acting as  
a device reset pin during power  
transitions. A reset time of 400 ns (5V VCC  
9
28F016SV FlashFile™ MEMORY  
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DQ  
DQ  
8-15  
0-7  
Output  
Buffer  
Output  
Buffer  
Input  
Buffer  
Input  
Buffer  
3/5#  
I/O Logic  
BYTE#  
Data  
Queue  
Registers  
ID  
Register  
CSR  
Page  
Buffers  
CE  
CE  
#
0
ESRs  
#
1
OE#  
WE#  
Data  
Comparator  
WP#  
RP#  
Input  
Buffer  
Y
Y Gating/Sensing  
Decoder  
RY/BY#  
V
Address  
Queue  
Registers  
PP  
X
Program/Erase  
Voltage Switch  
Decoder  
3/5#  
V
CC  
Address  
Counter  
GND  
0528_01  
Figure 1. 28F016SV Block Diagram  
Architectural Evolution Includes SmartVoltage Technology,  
Page Buffers, Queue Registers and Extended Registers  
10  
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28F016SV FlashFile™ MEMORY  
2.1 Lead Descriptions  
Symbol  
Type  
Name and Function  
A0  
INPUT  
BYTE-SELECT ADDRESS: Selects between high and low byte when  
device is in x8 mode. This address is latched in x8 data programs. Not  
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is  
high).  
A1–A15  
INPUT  
INPUT  
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.  
A
6–15 selects 1 of 1024 rows, and A1–5 selects 16 of 512 columns. These  
addresses are latched during data programs.  
A16–A20  
DQ0–DQ7  
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These  
addresses are latched during data programs, erase and lock block  
operations.  
INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI program  
cycles. Outputs array, buffer, identifier or status data in the appropriate  
read mode. Floated when the chip is de-selected or the outputs are  
disabled.  
DQ8–DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program  
operations. Outputs array, buffer or identifier data in the appropriate read  
mode; not used for Status Register reads. Floated when the chip is de-  
selected or the outputs are disabled.  
CE0#, CE1#  
INPUT  
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,  
decoders and sense amplifiers. With either CE0# or CE1# high, the device  
is de-selected and power consumption reduces to standby levels upon  
completion of any current data program or erase operations. Both CE0#  
and CE1# must be low to select the device.  
All timing specifications are the same for both signals. Device Selection  
occurs with the latter falling edge of CE0# or CE1#. The first rising edge of  
CE0# or CE1# disables the device.  
RP#  
INPUT  
RESET/POWER-DOWN: RP# low places the device in a deep power-  
down state. All circuits that consume static power, even those circuits  
enabled in standby mode, are turned off. When returning from deep  
power-down, a recovery time of tPHQV is required to allow these circuits to  
power-up.  
When RP# goes low, any current or pending WSM operation(s) are  
terminated, and the device is reset. All Status Registers return to ready  
(with all status flags cleared).  
Exit from deep power-down places the device in read array mode.  
OE#  
WE#  
INPUT  
INPUT  
OUTPUT ENABLE: Gates device data through the output buffers when  
low. The outputs float to tri-state off when OE# is high.  
NOTE:  
CE # overrides OE#, and OE# overrides WE#.  
x
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue  
Registers and Address Queue Latches. WE# is active low, and latches  
both address and data (command or array) on its rising edge.  
Page Buffer addresses are latched on the falling edge of WE#.  
11  
28F016SV FlashFile™ MEMORY  
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2.1 Lead Descriptions (Continued)  
Symbol  
Type  
Name and Function  
RY/BY#  
OPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it  
OUTPUT  
INPUT  
indicates that the WSM is busy performing an operation. RY/BY# floating  
indicates that the WSM is ready for new operations (or WSM has  
completed all pending operations), or erase is suspended, or the device is  
in deep power-down mode. This output is always active (i.e., not floated  
to tri-state off when OE# or CE0#, CE1# are high), except if a RY/BY# Pin  
Disable command is issued.  
WP#  
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile  
lock-bit for each block. When WP# is low, those locked blocks as  
reflected by the Block-Lock Status bits (BSR.6), are protected from  
inadvertent data programs or erases. When WP# is high, all blocks can  
be written or erased regardless of the state of the lock-bits. The WP#  
input buffer is disabled when RP# transitions low (deep power-down  
mode).  
BYTE#  
3/5#  
INPUT  
INPUT  
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then  
input or output on DQ0–7, and DQ8–15 float. Address A0 selects between  
the high and low byte. BYTE# high places the device in x16 mode, and  
turns off the A0 input buffer. Address A1 then becomes the lowest order  
,
address.  
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V  
operation. 3/5# low configures internal circuits for 5V operation.  
NOTE:  
Reading the array with 3/5# high in a 5V system could damage the  
device. Reference the power-up and reset timings (Section 5.7) for 3/5#  
switching delay to valid data.  
VPP  
SUPPLY  
PROGRAM/ERASE POWER SUPPLY (12V ± 0.6V, 5V ± 0.5V) : For  
erasing memory array blocks or writing words/bytes/pages into the flash  
array. VPP = 5V ± 0.5V eliminates the need for a 12V converter, while  
connection to 12V ± 0.6V maximizes Program/Erase Performance.  
NOTE:  
Successful completion of program and erase attempts is inhibited with  
VPP at or below 1.5V. Program and erase attempts with VPP between 1.5V  
and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious  
results and should not be attempted.  
VCC  
SUPPLY  
DEVICE POWER SUPPLY (3.3V ± 0.3V, 5V ± 0.5V, 5.0 ± 0.25V):  
To switch 3.3V to 5V (or vice versa), first ramp VCC down to GND, and  
then power to the new VCC voltage.  
Do not leave any power pins floating.  
GND  
NC  
SUPPLY  
GROUND FOR ALL INTERNAL CIRCUITRY:  
Do not leave any ground pins floating.  
NO CONNECT:  
Lead may be driven or left floating.  
12  
E
28F016SV FlashFile™ MEMORY  
28F016SA 28F032SA  
28F032SA 28F016SA  
56  
1
2
3
4
5
6
7
WP#  
WE#  
OE#  
RY/BY#  
DQ15  
DQ7  
DQ14  
DQ6  
GND  
DQ13  
DQ5  
WP#  
WE#  
OE#  
RY/BY# RY/BY#  
DQ15  
DQ7  
DQ14  
DQ6  
GND  
WP#  
WE#  
OE#  
3/5#  
CE1# CE1#  
3/5#  
3/5#  
CE1#  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
NC  
A20  
A19  
A18  
A17  
A16  
VCC  
A15  
A14  
A13  
A12  
NC  
A20  
A19  
A18  
A17  
A16  
VCC  
A15  
A14  
A13  
A12  
CE #  
2
A20  
A19  
A18  
A17  
A16  
VCC  
A15  
A14  
A13  
A12  
DQ15  
DQ7  
DQ14  
DQ6  
8
9
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
DQ13 DQ13  
DQ5  
DQ12  
DQ4  
VCC  
DQ5  
DQ12  
DQ4  
E28F016SV  
56-LEAD TSOP PINOUT  
DQ12  
DQ4  
VCC  
VCC  
CE0# CE0# CE0#  
42  
41  
40  
GND  
DQ11  
DQ3  
DQ10  
DQ 2  
VCC  
DQ 9  
DQ 1  
DQ 8  
DQ 0  
A0  
VPP  
RP#  
A11  
A10  
A9  
VPP  
RP#  
A11  
A10  
A9  
VPP  
RP#  
A11  
A10  
A9  
GND  
DQ11  
DQ3  
GND  
DQ11  
DQ3  
14 mm x 20 mm  
TOP VIEW  
39  
38  
37  
36  
35  
34  
33  
32  
31  
DQ10 DQ10  
DQ 2  
VCC  
DQ 9  
DQ 1  
DQ 8  
DQ 0  
A0  
BYTE# BYTE#  
NC  
NC  
DQ2  
VCC  
DQ9  
DQ1  
DQ8  
DQ0  
A0  
A8  
A8  
A8  
GND GND GND  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
26  
27  
28  
BYTE#  
NC  
NC  
30  
29  
NC  
NC  
NOTE:  
56-lead TSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet.  
0528_02  
Figure 2. 28F016SV 56-Lead TSOP Pinout Configuration  
Shows Compatibility with 28F016SA/28F032SA  
13  
28F016SV FlashFile™ MEMORY  
E
28F016SA  
28F016SA  
VPP  
CE0#  
A12  
CE0 #  
A12  
1
56  
VPP  
2
3
4
5
6
55  
54  
R/P#  
A11  
R/P#  
A11  
A13  
A13  
A14  
53  
52  
51  
50  
A10  
A9  
A1  
A10  
A9  
A1  
A14  
A15  
A15  
3/5#  
3/5#  
A2  
A2  
CE1 #  
NC  
CE1#  
NC  
7
8
49  
48  
47  
46  
A3  
A4  
A5  
A6  
A3  
A4  
A5  
A6  
A20  
A20  
9
A19  
A18  
A19  
A18  
10  
11  
12  
13  
DA28F016SV  
56-LEAD SSOP  
STANDARD PINOUT  
A17  
A16  
VCC  
A17  
A16  
VCC  
45  
A7  
A7  
44  
43  
42  
GND  
A8  
GND  
A8  
14  
15  
16 mm x 23.7 mm  
TOP VIEW  
GND  
DQ6  
VCC  
VCC  
GND  
DQ6  
41  
40  
39  
DQ9  
DQ1  
DQ8  
DQ9  
DQ1  
DQ8  
16  
17  
18  
19  
DQ14  
DQ7  
DQ14  
DQ7  
DQ15  
DQ15  
38  
37  
36  
DQ0  
A0  
DQ0  
A0  
RY/BY# RY/BY#  
20  
21  
22  
23  
BYTE#  
BYTE#  
OE#  
OE#  
WE#  
WP#  
DQ13  
DQ5  
WE#  
WP#  
DQ13  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
NC  
NC  
24  
25  
26  
27  
28  
DQ2  
DQ2  
DQ5  
DQ12  
DQ4  
VCC  
DQ10  
DQ10  
DQ12  
DQ4  
DQ3  
DQ11  
GND  
DQ3  
DQ11  
GND  
VCC  
NOTE:  
56-lead SSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet.  
0528_03  
Figure 3. 56-Lead SSOP Pinout Configuration  
14  
E
28F016SV FlashFile™ MEMORY  
3.0 MEMORY MAPS  
A[20-0]  
1FFFFF  
A[20-1]  
FFFFF  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
31  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
32-Kword Block  
1F0000  
1EFFFF  
F8000  
F7FFF  
30  
32-Kword Block  
1E0000  
1DFFFF  
F0000  
EFFFF  
29  
32-Kword Block  
1D0000  
1CFFFF  
E8000  
E7FFF  
28  
32-Kword Block  
1C0000  
1BFFFF  
E0000  
DFFFF  
27  
32-Kword Block  
1B0000  
1AFFFF  
D8000  
D7FFF  
26  
32-Kword Block  
1A0000  
19FFFF  
D0000  
CFFFF  
25  
32-Kword Block  
190000  
18FFFF  
C8000  
C7FFF  
24  
32-Kword Block  
180000  
17FFFF  
C0000  
BFFFF  
23  
32-Kword Block  
170000  
16FFFF  
B8000  
B7FFF  
22  
32-Kword Block  
160000  
15FFFF  
B0000  
A8FFF  
21  
32-Kword Block  
150000  
14FFFF  
A8000  
A7FFF  
20  
32-Kword Block  
140000  
13FFFF  
A0000  
9FFFF  
19  
32-Kword Block  
130000  
12FFFF  
98000  
97FFF  
18  
32-Kword Block  
120000  
11FFFF  
90000  
8FFFF  
17  
32-Kword Block  
110000  
10FFFF  
88000  
87FFF  
16  
32-Kword Block  
100000  
0FFFFF  
80000  
7FFFF  
15  
32-Kword Block  
0F0000  
0EFFFF  
78000  
77FFF  
14  
32-Kword Block  
0E0000  
0DFFFF  
70000  
6FFFF  
13  
32-Kword Block  
0D0000  
0CFFFF  
68000  
67FFF  
12  
32-Kword Block  
0C0000  
0BFFFF  
60000  
5FFFF  
11  
32-Kword Block  
0B0000  
0AFFFF  
58000  
57FFF  
10  
32-Kword Block  
0A0000  
09FFFF  
50000  
4FFFF  
9
32-Kword Block  
090000  
08FFFF  
48000  
47FFF  
8
8
32-Kword Block  
080000  
07FFFF  
40000  
3FFFF  
7
7
32-Kword Block  
070000  
06FFFF  
38000  
37FFF  
6
6
32-Kword Block  
060000  
05FFFF  
30000  
2FFFF  
5
5
32-Kword Block  
050000  
04FFFF  
28000  
27FFF  
4
4
32-Kword Block  
040000  
03FFFF  
20000  
1FFFF  
3
3
32-Kword Block  
030000  
02FFFF  
18000  
17FFF  
2
2
32-Kword Block  
020000  
01FFFF  
10000  
0FFFF  
1
1
32-Kword Block  
010000  
00FFFF  
08000  
07FFF  
0
0
32-Kword Block  
000000  
00000  
Byte-Wide (x8) Mode  
Word-Wide (x16) Mode  
0528_04  
Figure 4. 28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)  
15  
28F016SV FlashFile™ MEMORY  
E
3.1 Extended Status Registers Memory Map  
A[20-0]  
x8 MODE  
A[20-1]  
x16 MODE  
1F0006H  
F8003H  
RESERVED  
GSR  
RESERVED  
GSR  
1F0005H  
1F0004H  
1F0003H  
F8002H  
RESERVED  
RESERVED  
BSR 31  
BSR 31  
1F0002H  
1F0001H  
1F0000H  
F8001H  
F8000H  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
.
.
.
.
.
.
010002H  
000006H  
08001H  
RESERVED  
RESERVED  
00003H  
00002H  
RESERVED  
GSR  
RESERVED  
GSR  
000005H  
000004H  
RESERVED  
BSR 0  
RESERVED  
BSR 0  
000003H  
000002H  
00001H  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
000001H  
000000H  
00000H  
0528_05  
0528_06  
Figure 5. Extended Status Register Memory  
Map (Byte-Wide Mode)  
Figure 6. Extended Status Register Memory  
Map (Word-Wide Mode)  
16  
E
28F016SV FlashFile™ MEMORY  
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS  
4.1 Bus Operations for Word-Wide Mode (BYTE# = V )  
IH  
Mode  
Notes  
1,2,7  
1,6,7  
1,6,7  
RP#  
VIH  
VIH  
VIH  
CE1#  
VIL  
CE0#  
VIL  
OE#  
VIL  
VIH  
X
WE#  
VIH  
VIH  
X
A1  
X
DQ0–15 RY/BY#  
Read  
DOUT  
High Z  
High Z  
X
X
X
Output Disable  
Standby  
VIL  
VIL  
X
VIL  
VIH  
VIH  
VIH  
VIL  
VIH  
X
Deep Power-Down  
Manufacturer ID  
Device ID  
1,3  
4
VIL  
VIH  
VIH  
VIH  
X
X
X
X
X
VIL  
VIH  
X
High Z  
0089H  
66A0H  
DIN  
VOH  
VOH  
VOH  
X
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
VIL  
4,8  
1,5,6  
Write  
4.2 Bus Operations for Byte-Wide Mode (BYTE# = V )  
IL  
Mode  
Notes  
1,2,7  
1,6,7  
1,6,7  
RP#  
VIH  
VIH  
VIH  
CE1#  
VIL  
CE0#  
VIL  
OE#  
VIL  
VIH  
X
WE#  
VIH  
VIH  
X
A0  
X
DQ0–7  
DOUT  
RY/BY#  
Read  
X
X
X
Output Disable  
Standby  
VIL  
VIL  
X
High Z  
High Z  
VIL  
VIH  
VIH  
VIH  
VIL  
VIH  
X
Deep Power-Down  
Manufacturer ID  
Device ID  
1,3  
4
VIL  
VIH  
VIH  
VIH  
X
X
X
X
X
VIL  
VIH  
X
High Z  
89H  
VOH  
VOH  
VOH  
X
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
VIL  
4,8  
1,5,6  
A0H  
DIN  
Write  
NOTES:  
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH  
.
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode.  
RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation  
is in progress.  
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.  
4.  
A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A and A1 at VIH provide device ID  
0
codes in x8 and x16 modes respectively. All other addresses are set to zero.  
5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or  
PP = VPPH2  
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to  
OH when the WSM is not busy or in erase suspend mode.  
V
.
V
7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a  
program operation).  
8. The 28F016SV shares an identical device identifier (66A0H in word-wide mode, A0H in byte-wide mode) with the  
28F016SA. See application note AP-393 28F016SV Compatibility with 28F016SA for software and hardware techniques to  
differentiate between the 28F016SV and 28F016SA.  
17  
28F016SV FlashFile™ MEMORY  
E
4.3 28F008SA—Compatible Mode Command Bus Definitions  
First Bus Cycle  
Second Bus Cycle  
Command  
Read Array  
Notes  
Oper  
Write  
Write  
Write  
Write  
Write  
Write  
Write  
Write  
Addr  
X
Data(4)  
xxFFH  
xx90H  
xx70H  
xx50H  
xx40H  
xx10H  
xx20H  
xxB0H  
Oper  
Read  
Read  
Read  
Addr  
AA  
IA  
Data(4)  
AD  
Intelligent Identifier  
1
2
3
X
ID  
Read Compatible Status Register  
Clear Status Register  
X
X
CSRD  
X
Word/Byte Program  
X
Write  
Write  
Write  
Write  
PA  
PA  
BA  
X
PD  
PD  
Alternate Word/Byte Program  
Block Erase/Confirm  
X
X
xxD0H  
xxD0H  
Erase Suspend/Resume  
X
ADDRESS  
DATA  
AA = Array Address  
AD = Array Data  
BA = Block Address  
IA = Identifier Address  
PA = Program Address  
X = Don’t Care  
CSRD = CSR Data  
ID = Identifier Data  
PD = Program Data  
NOTES:  
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.  
2. The CSR is automatically available after device enters data program, erase, or suspend operations.  
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register  
definitions.  
4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.  
18  
E
28F016SV FlashFile™ MEMORY  
4.4 28F016SV—Performance Enhancement Command Bus Definitions  
Command  
Mode  
Notes  
First Bus Cycle  
Second Bus Cycle  
Third Bus Cycle  
Oper Addr Data(13) Oper  
Addr  
Data(13)  
Oper  
Addr  
Data  
Read Extended  
Status Register  
1
7
Write  
X
xx71H  
Read  
RA  
GSRD  
BSRD  
Page Buffer Swap  
Write  
Write  
Write  
X
X
X
xx72H  
xx75H  
xx74H  
Read Page Buffer  
Read  
Write  
PBA  
PBA  
PD  
PD  
Single Load to Page  
Buffer  
Sequential Load to  
Page Buffer  
x8  
4,6,10  
Write  
X
xxE0H  
Write  
X
X
BCL  
Write  
X
BCH  
x16  
x8  
4,5,6,10 Write  
3,4,9,10 Write  
X
X
xxE0H  
xx0CH  
Write  
Write  
WCL  
Write  
Write  
X
WCH  
Page Buffer Write to  
Flash  
A
BC(L,H)  
PA  
BC(H,L)  
0
x16  
x8  
4,5,10  
3
Write  
Write  
Write  
Write  
X
X
X
X
xx0CH  
xxFBH  
xx77H  
xx97H  
Write  
Write  
Write  
Write  
X
WCL  
Write  
PA  
PA  
WCH  
Two-Byte Program  
Lock Block/Confirm  
A
WD(L,H) Write  
xxD0H  
WD(H,L)  
0
BA  
X
Upload Status  
Bits/Confirm  
2
xxD0H  
Upload Device  
Information/Confirm  
11  
Write  
Write  
Write  
Write  
Write  
X
X
X
X
X
xx99H  
xxA7H  
xx96H  
xx96H  
xx96H  
Write  
Write  
Write  
Write  
Write  
X
X
X
X
X
xxD0H  
xxD0H  
xx01H  
xx02H  
xx03H  
Erase All Unlocked  
Blocks/Confirm  
RY/BY# Enable to  
Level-Mode  
8
8
8
RY/BY#  
Pulse-On-Write  
RY/BY#  
Pulse-On-Erase  
RY/BY# Disable  
8
8
Write  
Write  
X
X
xx96H  
xx96H  
Write  
Write  
X
X
xx04H  
xx05H  
RY/BY# Pulse-On-  
Write/Erase  
Sleep  
Abort  
12  
Write  
Write  
X
X
xxF0H  
xx80H  
ADDRESS  
DATA  
AD = Array Data  
BA = Block Address  
WC (L,H) = Word Count (Low, High)  
BC (L,H) = Byte Count (Low, High)  
WD (L,H) = Write Data (Low, High)  
PBA = Page Buffer Address  
RA = Extended Register Address  
PA = Program Address  
X = Don’t Care  
PD = Page Buffer Data  
BSRD = BSR Data  
GSRD = GSR Data  
19  
28F016SV FlashFile™ MEMORY  
E
NOTES:  
1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps.  
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the  
actual lock-bit status.  
3.  
A
A
0 is automatically complemented to load second byte of data. BYTE# must be at V .  
0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.  
IL  
4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the  
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page  
Buffer expandability.  
5. In x16 mode, only the lower byte DQ0–7 is used for WCL and WCH. The upper byte DQ8–15 is a don’t care.  
6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.  
7. This command allows the user to swap between available Page Buffers (0 or 1).  
8. These commands reconfigure RY/BY# output to one of three pulse-modes or enable and disable the RY/BY# function.  
9. Program address, PA, is the Destination address in the flash array which must match the Source address in the Page  
Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual.  
10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.  
11. After writing the Upload Device Information command and the Confirm command, the following information is output at  
Page Buffer addresses specified below:  
Address  
Information  
06H, 07H (Byte Mode)  
03H (Word Mode)  
1EH (Byte Mode)  
0FH (DQ0–7)(Word Mode)  
1FH (Byte Mode)  
Device Revision Number  
Device Revision Number  
Device Configuration Code  
Device Configuration Code  
Device Proliferation Code (01H)  
Device Proliferation Code (01H)  
0FH (DQ8–15)(Word Mode)  
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of all  
other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation  
by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also corresponds to  
data written to the 28F016SV after writing the RY/BY# Reconfiguration command.  
12. To ensure that the 28F016SV’s power consumption during sleep mode reaches the deep power-down current level, the  
system also needs to de-select the chip by taking either or both CE # or CE1# high.  
0
13. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.  
20  
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28F016SV FlashFile™ MEMORY  
4.5 Compatible Status Register  
WSMS  
7
ESS  
6
ES  
5
DWS  
4
VPPS  
3
R
2
R
1
R
0
NOTES:  
CSR.7 = WRITE STATE MACHINE STATUS  
RY/BY# output or WSMS bit must be checked to  
determine completion of an operation (erase,  
erase suspend, or data program) before the  
appropriate Status bit (ESS, ES or DWS) is  
checked for success.  
1 = Ready  
0 = Busy  
CSR.6 = ERASE-SUSPEND STATUS  
1 = Erase Suspended  
0 = Erase in Progress/Completed  
CSR.5 = ERASE STATUS  
1 = Error in Block Erasure  
0 = Successful Block Erase  
If DWS and ES are set to “1” during an erase  
attempt, an improper command sequence was  
entered. Clear the CSR and attempt the  
operation again.  
CSR.4 = DATA-WRITE STATUS  
1 = Error in Data Program  
0 = Data Program Successful  
CSR.3 = VPP STATUS  
1 = VPP Error Detect, Operation Abort  
0 = VPP OK  
The VPPS bit, unlike an A/D converter, does not  
provide continuous indication of VPP level. The  
WSM interrogates VPP’s level only after the Data  
Program or Erase command sequences have  
been entered, and informs the system if VPP has  
not been switched on. VPPS is not guaranteed to  
report accurate feedback between VPPLK(max)  
and VPPH1(min), between VPPH1(max) and  
VPPH2(min) and above VPPH2(max).  
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS  
These bits are reserved for future use; mask them out when polling the CSR.  
21  
28F016SV FlashFile™ MEMORY  
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4.6 Global Status Register  
WSMS  
7
OSS  
6
DOS  
5
DSS  
4
QS  
3
PBAS  
2
PBS  
1
PBSS  
0
NOTES:  
GSR.7 = WRITE STATE MACHINE STATUS  
[1] RY/BY# output or WSMS bit must be checked  
to determine completion of an operation (block  
lock, suspend, any RY/BY# reconfiguration,  
Upload Status Bits, erase or data program)  
before the appropriate Status bit (OSS or DOS)  
is checked for success.  
1 = Ready  
0 = Busy  
GSR.6 = OPERATION SUSPEND STATUS  
1 = Operation Suspended  
0 = Operation in Progress/Completed  
GSR.5 = DEVICE OPERATION STATUS  
1 = Operation Unsuccessful  
0 = Operation Successful or Currently  
Running  
GSR.4 = DEVICE SLEEP STATUS  
1 = Device in Sleep  
0 = Device Not in Sleep  
MATRIX 5/4  
0 0 = Operation Successful or Currently  
Running  
0 1 = Device in Sleep Mode or Pending  
Sleep  
If operation currently running, then GSR.7 = 0.  
If device pending sleep, then GSR.7 = 0.  
1 0 = Operation Unsuccessful  
1 1 = Operation Unsuccessful or  
Aborted  
Operation aborted: Unsuccessful due to Abort  
command.  
GSR.3 = QUEUE STATUS  
1 = Queue Full  
0 = Queue Available  
GSR.2 = PAGE BUFFER AVAILABLE STATUS  
1 = One or Two Page Buffers Available  
0 = No Page Buffer Available  
The device contains two Page Buffers.  
GSR.1 = PAGE BUFFER STATUS  
1 = Selected Page Buffer Ready  
0 = Selected Page Buffer Busy  
Selected Page Buffer is currently busy with WSM  
operation  
GSR.0 = PAGE BUFFER SELECT STATUS  
1 = Page Buffer 1 Selected  
0 = Page Buffer 0 Selected  
NOTE:  
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.  
GSR.7 provides indication when all queued operations are completed.  
22  
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28F016SV FlashFile™ MEMORY  
4.7 Block Status Register  
BS  
7
BLS  
6
BOS  
5
BOAS  
4
QS  
VPPS  
2
VPPL  
1
R
0
3
NOTES:  
BSR.7 = BLOCK STATUS  
1 = Ready  
[1] RY/BY# output or BS bit must be checked to  
determine completion of an operation (block lock,  
suspend, erase or data program) before the  
appropriate Status bits (BOS, BLS) is checked  
for success.  
0 = Busy  
BSR.6 = BLOCK LOCK STATUS  
1 = Block Unlocked for Program/Erase  
0 = Block Locked for Program/Erase  
BSR.5 = BLOCK OPERATION STATUS  
1 = Operation Unsuccessful  
0 = Operation Successful or  
Currently Running  
BSR.4 = BLOCK OPERATION ABORT STATUS  
1 = Operation Aborted  
The BOAS bit will not be set until BSR.7 = 1.  
0 = Operation Not Aborted  
MATRIX 5/4  
0 0 = Operation Successful or  
Currently Running  
0 1 = Not a Valid Combination  
1 0 = Operation Unsuccessful  
1 1 = Operation Aborted  
Operation halted via Abort command.  
BSR.3 = QUEUE STATUS  
1 = Queue Full  
0 = Queue Available  
BSR.2 = VPP STATUS  
1 = VPP Error Detect, Operation Abort  
0 = VPP OK  
BSR.1 = VPP LEVEL  
BSR.1 is not guaranteed to report accurate  
feedback between the VPPH1 and VPPH2 voltage  
ranges. Programs and erases with VPP between  
1 = VPP Detected at 5V ± 10%  
0 = VPP Detected at 12V ± 5%  
V
V
V
PPLK(max) and VPPH1(min), between  
PPH1(max) and VPPH2(min), and above  
PPH2(max) produce spurious results and should  
not be attempted.  
BSR.1 was a RESERVED bit on the 28F016SA.  
BSR.0 = RESERVED FOR FUTURE ENHANCEMENTS  
This bits is reserved for future use; mask it out when polling the BSRs.  
NOTE:  
1. When multiple operations are queued, checking BSR.7 only provides indication of completion or that particular block.  
GSR.7 provides indication when all queued operations are completed.  
23  
28F016SV FlashFile™ MEMORY  
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4.8 Device Configuration Code  
R
7
R
6
R
5
R
4
R
RB2  
2
RB1  
1
RB0  
0
3
NOTES:  
DCC.2-DCC.0 = RY/BY# CONFIGURATION  
(RB2–RB0)  
Undocumented combinations of RB2–RB0 are  
reserved by Intel Corporation for future  
implementations and should not be used.  
001 =Level Mode (Default)  
010 =Pulse-On-Program  
011 = Pulse-On-Erase  
100 = RY/BY# Disabled  
101 = Pulse-On-Program/Erase  
DCC.7–DCC.3 =  
RESERVED FOR FUTURE ENHANCEMENTS  
These bits are reserved for future use; mask them out when reading the Device Configuration Code.  
Set these bits to “0” when writing the desired RY/BY# configuration to the device.  
24  
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28F016SV FlashFile™ MEMORY  
5.0 ELECTRICAL SPECIFICATIONS  
NOTICE: This is  
a
production datasheet. The  
specifications are subject to change without notice. Verify  
with your local Intel Sales office that you have the latest  
datasheet before finalizing a design.  
5.1 Absolute Maximum Ratings*  
*WARNING: Stressing the device beyond the “Absolute  
Maximum Ratings” may cause permanent damage.  
These are stress ratings only. Operation beyond the  
“Operating Conditions” is not recommended and  
extended exposure beyond the "Operating Conditions"  
may affect device reliability.  
Temperature Under Bias ....................0°C to +80°C  
Storage Temperature ...................–65°C to +125°C  
VCC = 3.3V ± 0.3V Systems  
Sym  
Parameter  
Notes Min  
Max Units  
Test Conditions  
TA  
Operating Temperature, Commercial  
1
0
70  
°C  
V
Ambient Temperature  
VCC VCC with Respect to GND  
2
–0.2  
7.0  
VPP  
V
V
PP Supply Voltage with Respect to GND  
2,3  
2,5  
–0.2 14.0  
V
Voltage on Any Pin (except VCC,VPP) with  
Respect to GND  
VCC  
–0.5  
V
+ 0.5  
I
Current into Any Non-Supply Pin  
5
4
± 30  
mA  
mA  
IOUT Output Short Circuit Current  
CC = 5V ± 0.5V, 5V ± 0.25V Systems(6)  
100  
V
Sym  
Parameter  
Notes Min  
Max Units  
Test Conditions  
TA  
Operating Temperature, Commercial  
1
0
70  
°C  
V
Ambient Temperature  
VCC VCC with Respect to GND  
2
–0.2  
7.0  
VPP VPP Supply Voltage with Respect to GND  
2,3  
2,5  
–0.2 14.0  
V
Voltage on Any Pin (except VCC,VPP) with  
V
–2.0  
7.0  
V
Respect to GND  
I
Current into Any Non-Supply Pin  
5
4
± 30  
mA  
mA  
IOUT Output Short Circuit Current  
100  
NOTES:  
1. Operating temperature is for commercial product defined by this specification.  
2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to–2.0V for periods  
<20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for  
periods <20 ns.  
3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.  
4. Output shorted for no more than one second. No more than one output shorted at a time.  
5. This specification also applies to pins marked “NC.”  
6. 5% VCC specifications refer to the 28F016SV-065 and 28F016SV-070 in its high speed test configuration.  
25  
28F016SV FlashFile™ MEMORY  
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5.2 Capacitance  
For a 3.3V ± 0.3V System:  
Sym  
CIN  
Parameter  
Notes  
Typ  
Max  
Units  
Test Conditions  
Capacitance Looking into an  
Address/Control Pin  
1
6
8
pF  
TA = +25°C, f = 1.0 MHz  
COUT  
Capacitance Looking into an  
Output Pin  
1
8
12  
50  
pF  
pF  
TA = +25°C, f = 1.0 MHz  
CLOAD  
Load Capacitance Driven by  
1,2  
Outputs for Timing Specifications  
For 5V ± 0.5V, 5V ± 0.25V System:  
Sym  
CIN  
Parameter  
Notes  
Typ  
Max  
Units  
Test Conditions  
Capacitance Looking into an  
Address/Control Pin  
1
6
8
pF  
TA = +25°C, f = 1.0 MHz  
COUT  
Capacitance Looking into an  
Output Pin  
1
8
12  
100  
30  
pF  
pF  
pF  
TA = +25°C, f = 1.0 MHz  
For VCC = 5V ± 0.5V  
For VCC = 5V ± 0.25V  
CLOAD  
Load Capacitance Driven by  
Outputs for Timing Specifications  
1,2  
NOTE:  
1. Sampled, not 100% tested. Guaranteed by design.  
2. To obtain iBIS models for the 28F016SV, please contact your local Intel/Distribution Sales Office.  
26  
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28F016SV FlashFile™ MEMORY  
2.4  
2.0  
0.8  
2.0  
INPUT  
OUTPUT  
TEST POINTS  
0.8  
0.45  
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at V  
IH  
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.  
0528_07  
Figure 7. Transient Input/Output Reference Waveform for  
V
CC = 5V ± 10% (Standard Testing Configuration)(1)  
3.0  
0.0  
OUTPUT  
INPUT  
1.5  
TEST POINTS  
1.5  
AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.  
Input rise and fall times (10% to 90%) <10 ns.  
0528_08  
Figure 8. Transient Input/Output Reference Waveform for VCC = 3.3V ± 0.3V  
and VCC = 5V ± 5% (High Speed Testing Configuration)(2)  
NOTES:  
1. Testing characteristics for 28F016SV-070 (Standard Testing Configuration) and 28F016SV-080.  
2. Testing characteristics for 28F016SV-065/28F016SV-075 and 28F016SV-70 (High Speed Testing Configuration)/  
28F016SV-120.  
27  
28F016SV FlashFile™ MEMORY  
E
2.5 ns of 25 Transmission Line  
Ω
Test  
From Output  
under Test  
Point  
Total Capacitance = 100 pF  
0528_09  
Figure 9. Transient Equivalent Testing Load Circuit  
(28F016SV-070/-080 at VCC = 5V ± 10%)  
2.5 ns of 50  
Ω
Transmission Line  
From Output  
under Test  
Test  
Point  
Total Capacitance = 50 pF  
0528_10  
Figure 10. Transient Equivalent Testing Load Circuit  
(28F016SV-075/-120 at VCC = 3.3V ± 0.3V)  
Ω
2.5 ns of 83 Transmission Line  
From Output  
under Test  
Test  
Point  
Total Capacitance = 30 pF  
0528_11  
Figure 11. High Speed Transient Equivalent Testing Load Circuit  
(28F016SV-065/-070 at VCC = 5V ± 5%)  
28  
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28F016SV FlashFile™ MEMORY  
5.3 DC Characteristics  
VCC = 3.3V ± 10%V, TA = 0°C to +70°C, –40°C to +70°C  
3/5# = Pin Set High for 3.3V Operations  
Temp  
Commercial  
Extended  
Typ Max Units  
Sym  
Parameter  
Notes Min  
Typ Max  
Min  
Test Conditions  
ILI  
Input Load  
Current  
1
± 1  
± 1  
µA  
VCC = VCC Max  
V
IN = VCC or GND  
VCC = VCC Max  
OUT = VCC or GND  
ILO  
Output  
Leakage  
Current  
1
± 10  
± 10  
µA  
V
ICCS  
VCC Standby  
Current  
1,5  
70  
130  
70  
130  
µA  
VCC = VCC Max  
CE0#, CE1#, RP# =  
V
CC ± 0.2V  
BYTE#, WP#, 3/5#  
= VCC ±0.2V or  
GND ± 0.2V  
1
4
1
4
mA VCC = VCC Max  
CE0#, CE1#, RP# =  
VIH  
BYTE#, WP#, 3/5#  
= VIH or VIL  
ICCD  
VCC Deep  
Power-Down  
Current  
1
2
10  
50  
5
15  
55  
µA  
RP# = GND ± 0.2V  
BYTE# = VCC  
±
0.2V or GND ±  
0.2V  
ICCR1  
VCC Read  
Current  
1,4,5  
40  
40  
mA VCC = VCC Max  
CMOS: CE0#, CE1#  
= GND ± 0.2V,  
BYTE# = GND ±  
0.2V or VCC  
±
0.2V, Inputs =  
GND ± 0.2V or  
VCC ± 0.2V  
TTL: CE0#, CE1# =  
VIL, BYTE# = VIL  
or VIH, Inputs =  
VIL or VIH  
f = 8 MHz, IOUT  
0 mA  
=
29  
28F016SV FlashFile™ MEMORY  
E
5.3 DC Characteristics (Continued)  
VCC = 3.3V ± 10%V, TA = 0°C to +70°C, –40°C to +70°C  
3/5# = Pin Set High for 3.3V Operations  
Temp  
Commercial  
Extended  
Typ Max Units  
Sym  
ICCR  
Parameter  
Notes Min  
Typ Max  
Min  
Test Conditions  
2
VCC Read  
Current  
1,4,  
5,6  
20  
30  
20  
35  
mA VCC = VCC Max  
CMOS: CE0#, CE1#  
= GND ± 0.2V,  
BYTE# = GND ±  
0.2V or VCC  
±
0.2V, Inputs =  
GND ± 0.2V or  
VCC ± 0.2V  
TTL: CE0#, CE1# =  
VIL, BYTE# = VIL  
or VIH, Inputs =  
V
IL or VIH  
f = 4 MHz, IOUT  
0 mA  
=
ICCW VCC Program  
Current for  
1,6  
1,6  
1,2  
8
8
6
9
1
12  
17  
12  
17  
4
8
8
6
9
1
12  
17  
12  
17  
4
mA  
VPP = 12V ± 5%  
Program in  
Progress  
Word or Byte  
mA VPP = 5V ± 10%  
Program in  
Progress  
ICCE  
VCC Block  
Erase  
mA  
VPP = 12V ± 5%  
Block Erase in  
Progress  
Current  
mA VPP = 5V ± 10%  
Block Erase in  
Progress  
ICCES VCC Erase  
Suspend  
mA CE0#, CE1# = VIH  
Block Erase  
Current  
Suspended  
IPPS  
IPPR  
IPPD  
VPP Standby/  
Read Current  
1
1
± 1  
30  
± 10  
200  
5
± 3  
70  
± 10  
200  
5
µA  
µA  
µA  
VPP ≤ VCC  
VPP > VCC  
VPP Deep  
Power-Down  
Current  
0.2  
0.2  
RP# = GND ± 0.2V  
30  
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28F016SV FlashFile™ MEMORY  
5.3 DC Characteristics (Continued)  
VCC = 3.3V ± 10%V, TA = 0°C to +70°C, –40°C to +70°C  
3/5# = Pin Set High for 3.3V Operations  
Temp  
Commercial  
Extended  
Typ Max Units  
Sym  
Parameter  
Notes Min  
Typ Max  
Min  
Test Conditions  
IPPW  
VPP Program  
Current for  
Word or Byte  
1,6  
10  
15  
4
15  
10  
15  
4
15  
mA VPP = 12V ± 5%  
Program in  
Progress  
25  
25  
mA VPP = 5V ± 10%  
Program in  
Progress  
IPPE  
VPP Erase  
Current  
1,6  
10  
10  
mA VPP = 12V ± 5%  
Block Erase in  
Progress  
14  
30  
20  
14  
70  
20  
mA VPP = 5V ± 10%  
Block Erase in  
Progress  
IPPES VPP Erase  
Suspend  
1
200  
200  
µA  
VPP = VPPH1 or  
VPPH2  
Current  
Block Erase  
Suspended  
VIL  
Input Low  
Voltage  
6
6
6
–0.3  
2.0  
0.8  
0.8  
V
V
V
VIH  
VOL  
Input High  
Voltage  
VCC  
+ 0.3  
0.4  
VCC  
+ 0.3  
Output Low  
Voltage  
0.4  
VCC = VCC Min and  
I
OL = 4 mA  
31  
28F016SV FlashFile™ MEMORY  
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5.3 DC Characteristics (Continued)  
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C  
3/5# = Pin Set High for 3.3V Operations  
Temp  
Comm/Ext  
Typ  
Sym  
Parameter  
Output High  
Notes  
Min  
Max Units  
Test Conditions  
VOH1  
6
2.4  
V
VCC = VCC Min  
Voltage  
VCC  
–
IOH = –2.0 mA  
VCC = VCC Min  
VOH2  
6
3,6  
3
0.2  
V
I
OH = –100 µA  
VPPLK  
VPPH1  
VPP Program/Erase  
Lock Voltage  
0.0  
4.5  
1.5  
5.5  
V
V
VPP during  
5.0  
Program/Erase  
Operations  
VPPH2  
VPP during  
3
11.4 12.0 12.6  
V
V
Program/Erase  
Operations  
VLKO  
VCC Program/Erase  
Lock Voltage  
2.0  
NOTES:  
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12V or 5V, T = +25°C. These currents  
are valid for all product versions (package and speeds).  
2.  
I
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of  
CCES and ICCR  
.
3. Block erases, word/byte programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the  
ranges between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max).  
4. Automatic Power Savings (APS) reduces ICCR to 3.0 mA typical in static operation.  
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH  
.
6. Sampled, but not 100% tested. Guaranteed by design.  
32  
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28F016SV FlashFile™ MEMORY  
5.4 DC Characteristics  
VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
3/5# = Pin Set Low for 5V Operations  
Temp  
Notes  
1
Commercial  
Min Typ Max  
Extended  
Sym  
Parameter  
Min  
Typ Max Units  
Test Conditions  
ILI  
Input Load  
Current  
± 1  
± 1  
µA  
µA  
V
V
CC = VCC Max  
IN = VCC or GND  
ILO  
Output  
1
± 10  
± 10  
VCC = VCC Max  
Leakage  
Current  
V
OUT = VCC or GND  
ICCS  
VCC Standby  
Current  
1,5  
70  
130  
70  
130  
µA  
V
CC = VCC Max  
CE0#, CE1#, RP# =  
CC ± 0.2V  
V
BYTE#, WP#, 3/5#  
= VCC ± 0.2V or  
GND ± 0.2V  
2
4
2
4
mA VCC = VCC Max,  
CE0#, CE1#, RP# =  
VIH  
BYTE#, WP#, 3/5#  
= VIH or VIL  
ICCD  
VCC Deep  
Power-Down  
Current  
1
2
10  
95  
5
15  
µA  
RP# = GND ± 0.2V  
BYTE# = VCC  
±
0.2V or GND ±  
0.2V  
ICCR1  
VCC Read  
Current  
1,4,5  
75  
75  
105  
mA VCC = VCC Max  
CMOS: CE0#, CE1#  
= GND ± 0.2V,  
BYTE# = GND ±  
0.2V or VCC  
±
0.2V, Inputs =  
GND ± 0.2V or,  
V
CC ± 0.2V  
TTL: CE0#, CE1# =  
VIL, BYTE# = VIL  
or VIH, Inputs =  
V
IL or VIH  
f = 10 MHz, IOUT  
0 mA  
=
33  
28F016SV FlashFile™ MEMORY  
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5.4 DC Characteristics (Continued)  
VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
3/5# = Pin Set Low for 5V Operations  
Temp  
Notes  
Commercial  
Min Typ Max  
Extended  
Typ Max Units  
Sym  
ICCR  
Parameter  
Min  
Test Conditions  
2
VCC Read  
Current  
1,4,  
5,6  
45  
55  
45  
60  
mA VCC = VCC Max  
CMOS: CE0#, CE1#  
= GND ± 0.2V,  
BYTE# = GND ±  
0.2V or VCC  
±
0.2V, Inputs =  
GND ± 0.2V or  
V
CC ± 0.2V  
TTL: CE0#, CE1# =  
VIL, BYTE# = VIL  
or VIH, Inputs =  
V
IL or VIH  
f = 5 MHz, IOUT  
0 mA  
=
ICCW VCC Program  
Current for  
1,6  
1,6  
25  
25  
18  
20  
35  
40  
25  
30  
25  
25  
18  
20  
35  
40  
25  
30  
mA  
VPP = 12V ± 5%  
Program in  
Progress  
Word or Byte  
mA VPP = 5V ± 10%  
Program in  
Progress  
ICCE  
VCC Block  
Erase  
mA  
VPP = 12V ± 5%  
Block Erase in  
Progress  
Current  
mA VPP = 5V ± 10%  
Block Erase in  
Progress  
ICCES VCC Erase  
Suspend  
1,2  
1
2
4
2
4
mA CE0#, CE1# = VIH  
Block Erase  
Current  
Suspended  
IPPS  
VPP Standby  
/Read  
± 1  
± 10  
± 3  
± 10  
µA  
V
PP ≤ VCC  
IPPR  
IPPD  
Current  
30  
200  
5
70  
200  
5
µA  
µA  
V
PP > VCC  
VPP Deep  
Power-  
1
0.2  
0.2  
RP# = GND ± 0.2V  
Down Current  
34  
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28F016SV FlashFile™ MEMORY  
5.4 DC Characteristics (Continued)  
VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
3/5# = Pin Set Low for 5V Operations  
Temp  
Notes  
1,6  
Commercial  
Min Typ Max  
Extended  
Typ Max Units  
Sym  
Parameter  
Min  
Test Conditions  
IPPW  
V
PP Program  
7
12  
7
12  
mA VPP  
Program in  
Progress  
mA VPP ± 10%  
=
± 5%  
12V  
Current for  
Word or Byte  
17  
5
22  
17  
5
22  
=
5V  
Program in  
Progress  
IPPE  
VPP Block  
Erase  
1,6  
10  
10  
mA VPP  
=
± 5%  
12V  
Block Erase in  
Progress  
Current  
16  
30  
20  
16  
30  
20  
mA VPP  
=
± 10%  
5V  
Block Erase in  
Progress  
IPPES VPP Erase  
Suspend  
1
200  
200  
µA  
VPP = VPPH1 or  
VPPH2  
Current  
Block Erase  
Suspended  
VIL  
VIH  
Input Low  
Voltage  
6
6
–0.5  
2.0  
0.8  
0.8  
V
V
Input High  
Voltage  
VCC+  
VCC+  
0.5  
0.5  
35  
28F016SV FlashFile™ MEMORY  
E
5.4 DC Characteristics (Continued)  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
5V  
5V  
3/5# = Pin Set Low for  
Operations  
5V  
Temp  
Notes  
6
Comm/Extended  
Sym  
VOL  
Parameter  
Min  
Typ  
Max Units  
Test Conditions  
Output Low Voltage  
0.45  
V
V
V
CC = VCC Min  
OL = 5.8 mA  
VCC = VCC Min  
OH = –2.5 mA  
CC = VCC Min  
OH = –100 µA  
I
VOH  
1
2
Output High  
Voltage  
6
6
0.85  
VCC  
I
VOH  
VCC  
0.4  
–
V
I
VPPLK  
VPPH1  
VPP Program/Erase  
Lock Voltage  
3,6  
0.0  
1.5  
5.5  
V
V
VPP during  
4.5  
5.0  
Program/Erase  
Operations  
VPPH2  
VPP during  
11.4 12.0 12.6  
V
V
Program/Erase  
Operations  
VLKO  
VCC Program/Erase  
Lock Voltage  
2.0  
NOTES:  
1. All currents are in RMS unless otherwise noted. Typical values at VCC  
=
, V  
=
or , T = 25°C. These currents are  
12V 5V  
5V  
PP  
valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a  
TTL rise/fall time of <10 ns.  
2.  
I
I
CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of  
CCES and ICCR.  
3. Block erases, word/byte programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the  
ranges between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max).  
4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in Static operation.  
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH  
.
6. Sampled, not 100% tested. Guaranteed by design.  
36  
E
28F016SV FlashFile™ MEMORY  
5.5 Timing Nomenclature  
All 3.3V system timings are measured from where signals cross 1.5V.  
For  
systems use the standard JEDEC cross point definitions (standard testing) or from where signals  
5V  
cross 1.5V (high speed testing).  
Each timing parameter consists of 5 characters. Some common examples are defined below:  
tCE  
tOE  
tACC  
tAS  
tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V)  
tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)  
t
AVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)  
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)  
tDH  
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)  
Pin Characters  
Address Inputs  
Pin States  
A
D
H
L
High  
Low  
Data Inputs  
Q
E
Data Outputs  
V
X
Z
Valid  
CE# (Chip Enable)  
BYTE# (Byte Enable)  
OE# (Output Enable)  
WE# (Write Enable)  
RP# (Deep Power-Down Pin)  
RY/BY# (Ready Busy)  
Any Voltage Level  
3/5# Pin  
Driven, but Not Necessarily Valid  
High Impedance  
F
G
W
P
R
V
Y
5V  
3V  
VCC at 4.5V Minimum  
VCC at 3.0V Minimum  
37  
28F016SV FlashFile™ MEMORY  
E
Units  
(1)  
5.6 AC Characteristics—Read Only Operations  
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C  
Temp  
Speed  
Notes  
Commercial  
–75  
Extended  
Commercial  
–120  
Sym  
Parameter  
–100  
Min  
Max  
Min  
Max  
Min  
Max  
100  
tAVAV Read Cycle Time  
75  
85(10)  
120  
ns  
ns  
ns  
ns  
100  
100  
tAVQV Address to Output Delay  
tELQV CE# to Output Delay  
75  
85(10)  
75  
120  
120  
2,8  
85(10)  
620  
45  
tPHQV RP# High to Output  
Delay  
480  
620  
45  
tGLQV OE# to Output Delay  
tELQX CE# to Output in Low Z  
tEHQZ CE# to Output in High Z  
tGLQX OE# to Output in Low Z  
tGHQZ OE# to Output in High Z  
2
3,8  
3,8  
3
40  
30  
20  
ns  
ns  
ns  
ns  
ns  
ns  
0
0
0
0
0
0
0
0
0
50  
20  
50  
20  
3
tOH  
Output Hold from  
Address, CE# or OE#  
Change, Whichever  
Occurs First  
3,8  
tFLQV BYTE# to Output Delay  
tFHQV  
3
75  
85(10)  
100  
120  
ns  
tFLQZ BYTE# Low to Output in  
High Z  
3
30  
30  
5
30  
5
ns  
ns  
tELFL CE# Low to BYTE# High  
3,8  
5
or Low  
tELFH  
Extended Status Register Reads  
tAVEL  
Address Setup to CE#  
Going Low  
3,4,  
8,9  
0
0
0
0
0
0
ns  
ns  
tAVGL  
Address Setup to OE#  
Going Low  
3,4,9  
38  
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28F016SV FlashFile™ MEMORY  
(1)  
± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
5.6 AC Characteristics—Read Only Operations (Continued)  
VCC  
=
± 0.5V,  
5V 5V  
Temp  
Speed  
VCC  
Commercial  
Comm/Ext  
–65  
–70  
–80  
Sym  
Parameter  
± 5%V  
± 10%  
± 10%  
Units  
5V  
5V  
5V  
Load  
Notes  
30 pF  
50 pF  
50 pF  
Min  
Max  
Min  
Max  
Min  
Max  
tAVAV  
tAVQV  
tELQV  
Read Cycle Time  
65  
70  
80  
ns  
ns  
ns  
ns  
Address to Output Delay  
CE# to Output Delay  
65  
65  
70  
70  
80  
80  
2,8  
2
tPHQV RP# to Output Delay  
400  
480(6)  
400(7)  
480  
tGLQV  
OE# to Output Delay  
30  
30(6)  
35(7)  
35  
ns  
tELQX  
tEHQZ  
tGLQX  
CE# to Output in Low Z  
CE# to Output in High Z  
OE# to Output in Low Z  
3,8  
3,8  
3
0
0
0
0
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
25  
15  
25  
15  
30  
20  
tGHQZ OE# to Output in High Z  
3
tOH  
Output Hold from  
Address, CE# or OE#  
Change, Whichever  
Occurs First  
3,8  
tFLQV  
tFHQV  
tFLQZ  
BYTE# to Output Delay  
3
65  
70  
80  
ns  
BYTE# Low to Output in  
High Z  
3
25  
5
25  
5
30  
5
ns  
ns  
tELFL  
tELFH  
CE# Low to BYTE#  
High or Low  
3,8  
Extended Status Register Reads  
tAVEL  
Address Setup to CE#  
Going Low  
3,4,8,9  
0
0
0
0
0
0
ns  
ns  
tAVGL  
Address Setup to OE#  
Going Low  
3,4,9  
39  
28F016SV FlashFile™ MEMORY  
E
NOTES:  
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8.  
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE#, without impacting tELQV  
3. Sampled, not 100% tested. Guaranteed by design  
.
4. This timing parameter is used to latch the correct BSR data onto the outputs.  
5. Device speeds are defined as:  
65/70 ns at V  
CC  
=
equivalent to  
5V  
75 ns at V = 3.3V  
CC  
70/80 ns at V  
CC  
=
5V  
equivalent to  
120 ns at V = 3.3V  
CC  
6. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
7. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
8. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
9. The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the  
last control signal to become active (CE #, CE # or OE#). For example, if CE # and CE # are activated prior to OE# for  
0
1
0
1
an Extended Status Register read, specification tAVGL must be met. On the other hand, if either CE # or CE # (or both) are  
0
1
activated after OE#, specification tAVEL must be referenced.  
10. Page Buffer Reads only.  
40  
E
28F016SV FlashFile™ MEMORY  
STANDBY  
DEVICE AND  
ADDRESS SELECTION  
OUTPUTS ENABLED  
DATA VALID  
STANDBY  
V
V
POWER-UP  
POWER-DOWN  
CC  
CC  
V
IH  
ADDRESSES (A)  
ADDRESSES STABLE  
V
IL  
t
AVAV  
V
IH  
(1)  
CEx# (E)  
t
AVEL  
V
IL  
t
EHQZ  
V
IH  
OE# (G)  
V
t
AVGL  
IL  
t
GHQZ  
V
IH  
WE# (W)  
V
t
GLQV  
IL  
t
ELQV  
GLQX  
t
ELQX  
t
OH  
t
V
OH  
HIGH Z  
DATA (D/Q)  
V
HIGH Z  
VALID OUTPUT  
OL  
t AVQV  
5.0V  
V
CC  
GND  
V
t
PHQV  
IH  
RP# (P)  
V
IL  
0528_12  
NOTE:  
CEX # is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
Figure 12. Read Timing Waveforms  
41  
28F016SV FlashFile™ MEMORY  
E
V
IH  
ADDRESSES STABLE  
ADDRESSES (A)  
V
IL  
t
AVAV  
V
IH  
(1)  
CEx #(E)  
V
IL  
t
= t  
AVFL  
ELFL  
tEHQZ  
V
IH  
t
AVEL  
OE# (G)  
V
t
IL  
GHQZ  
t
ELFL  
t
AVGL  
V
t
= t  
AVQV  
IH  
FLQV  
BYTE# (F)  
t
GLQV  
t
V
ELQV  
IL  
t
t
GLQX  
OH  
V
tELQX  
OH  
DATA  
OUTPUT ON  
DQ0-DQ7  
HIGH Z  
HIGH Z  
HIGH Z  
DATA OUTPUT  
DATA (DQ0-DQ7)  
V
V
OL  
t
FLQZ  
t
AVQV  
OH  
DATA (DQ8-DQ15)  
HIGH Z  
DATA  
OUTPUT  
V
OL  
0528_13  
NOTE:  
CEX # is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
Figure 13. BYTE# Timing Waveforms  
42  
E
28F016SV FlashFile™ MEMORY  
5.7 Power-Up and Reset Timings  
V
POWER-UP  
CC  
RP#  
tYHPH  
tYLPH  
(P)  
3/5#  
(Y)  
5.0V  
tPLYL  
4.5V  
3.3V  
V
CC  
0V  
(3V,5V)  
tPL5V  
CE  
#
X
tPHEL3  
tPHEL5  
Address  
(A)  
Valid  
Valid  
tAVQV  
tAVQV  
Valid 3.3V Outputs  
Data  
(Q)  
Valid 5.0V Outputs  
tPHQV  
tPHQV  
0528_14  
Figure 14. VCC Power-Up and RP# Reset Waveforms  
Symbol  
tPLYL  
Parameter  
Notes  
Min  
Max  
Unit  
RP# Low to 3/5# Low (High)  
0
µs  
tPLYH  
tYLPH  
3/5# Low (High) to RP# High  
1
2
2
0
µs  
µs  
tYHPH  
tPL5V  
RP# Low to VCC at 4.5V minimum  
(to VCC at 3.0V min or 3.6V max)  
tPL3V  
tPHEL3  
tPHEL5  
tAVQV  
RP# High to CE# Low (3.3V VCC  
)
1
1
3
3
405  
330  
ns  
ns  
ns  
ns  
RP# High to CE# Low (5V VCC  
)
Address Valid to Data Valid for VCC = 5V ± 10%  
RP# High to Data Valid for VCC = 5V ± 10%  
70  
tPHQV  
400  
NOTES:  
CE0#, CE1# and OE# are switched low after Power-Up.  
1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and program specifications for the  
28F016SV.  
2. The power supply may start to switch concurrently with RP# going low.  
3. The address access time and RP# high to data valid time are shown for  
VCC operation of the 28F016SV-070 (Standard  
5V  
Test Configuration). Refer to the AC Characteristics-Read Only Operations for 3.3V VCC and  
Configuration) values.  
VCC (High Speed Test  
5V  
43  
28F016SV FlashFile™ MEMORY  
E
(1)  
5.8 AC Characteristics for WE#—Controlled Command Write Operations  
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; –40°C to +85°C  
Temp  
Speed  
Notes  
Commercial  
Extended  
Commercial  
Sym  
Parameter  
–75  
–100  
–120  
Unit  
Min  
Typ Max Min  
Typ Max Min  
Typ Max  
t
t
Write Cycle Time  
75  
100  
100  
120  
100  
ns  
ns  
AVAV  
1,2  
V
Setup to WE#  
PP  
3
100  
VPWH  
Going High  
t
t
t
t
RP# Setup to CE#  
Going Low  
3,7  
3,7  
2,6  
2,6  
480  
480  
10  
480  
10  
ns  
ns  
ns  
ns  
PHEL  
(12)  
0,10  
CE# Setup to WE#  
Going Low  
ELWL  
AVWH  
DVWH  
Address Setup to WE#  
Going High  
60  
60  
70  
75  
Data Setup to WE#  
Going High  
70  
75  
t
t
WE# Pulse Width  
60  
5
70  
10  
75  
10  
ns  
ns  
WLWH  
Data Hold from WE#  
High  
2
2
WHDX  
t
t
Address Hold from  
WE# High  
5
5
10  
10  
10  
10  
ns  
ns  
WHAX  
WHEH  
CE# Hold from WE#  
High  
3,7  
t
t
WE# Pulse Width High  
15  
0
30  
0
45  
0
ns  
ns  
WHWL  
Read Recovery before  
Write  
3
3
3
GHWL  
t
t
WE# High to RY/BY#  
Going Low  
100  
100  
100  
ns  
ns  
WHRL  
RHPL  
RP# Hold from Valid  
Status Register (CSR,  
GSR, BSR) Data and  
RY/BY# High  
0
0
0
t
t
t
RP# High Recovery to  
WE# Going Low  
3
0.480  
55  
1
75  
0
1
95  
0
µs  
ns  
µs  
PHWL  
Write Recovery before  
Read  
WHGL  
1,2  
QVVL  
V
Hold from Valid  
3
0
PP  
Status Register (CSR,  
GSR, BSR) Data and  
RY/BY# High  
44  
E
28F016SV FlashFile™ MEMORY  
(1)  
5.8 AC Characteristics for WE#—Controlled Command Write Operations  
(Continued)  
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; –40°C to +85°C  
Temp  
Speed  
Notes  
Commercial  
Extended  
Commercial  
Sym  
Parameter  
–75  
–100  
–120  
Unit  
Min  
Typ Max Min  
Typ Max Min  
Typ Max  
t
1
Duration of Program  
Operation  
3,4,5,  
11  
5
9
TBD  
5
9
TBD  
5
9
TBD  
µs  
WHQV  
t
2
Duration of Block Erase  
Operation  
3,4  
0.3  
0.8  
10  
0.3  
0.8  
10  
0.3  
0.8  
10  
sec  
WHQV  
45  
28F016SV FlashFile™ MEMORY  
E
(1)  
5.8AC Characteristics for WE#—Controlled Command Write Operations  
(Continued)  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
5V  
5V  
Temp  
Speed  
VCC  
Commercial  
Extended  
–65  
± 5%  
–70  
–80  
Sym  
Parameter  
± 10%  
± 10%  
Unit  
5V  
30 pF  
5V  
5V  
Load  
50 pF  
50 pF  
Notes Min Typ Max Min Typ Max Min Typ Max  
tAVAV  
Write Cycle Time  
65  
70  
80  
ns  
ns  
tVPWH  
VPWH2  
tPHEL  
1
VPP Setup to WE#  
Going High  
3
100  
100  
100  
t
480(9)  
RP# Setup to CE#  
Going Low  
3,7  
3,7  
2,6  
2,6  
300  
0
480  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
300(10)  
tELWL  
CE# Setup to WE#  
Going Low  
0
tAVWH Address Setup to  
WE# Going High  
40  
40  
40  
0
50(9)  
40(10)  
50  
50  
50  
0
tDVWH Data Setup to  
WE# Going High  
50(9)  
40(10)  
tWLWH WE# Pulse Width  
40(9)  
45(10)  
tWHDX Data Hold from  
WE# High  
2
2
0
tWHAX Address Hold from  
WE# High  
5
10  
10  
10  
30  
0
tWHEH CE# Hold from  
WE# High  
3,7  
5
10(9)  
5(10)  
tWHWL WE# Pulse Width  
High  
15  
0
30(9)  
15(10)  
tGHWL Read Recovery  
before Write  
3
3
0
tWHRL WE# High to  
RY/BY# Going  
Low  
100  
100  
100  
tRHPL  
RP# Hold from  
Valid Status  
3
0
0
0
ns  
Register (CSR,  
GSR, BSR) Data  
and RY/BY# High  
46  
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28F016SV FlashFile™ MEMORY  
(1)  
5.8AC Characteristics for WE#—Controlled Command Write Operations  
(Continued)  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
5V  
5V  
Temp  
Commercial  
Extended  
Speed  
–65  
± 5%  
–70  
–80  
Sym  
Parameter  
V
± 10%  
± 10%  
5V  
Unit  
CC  
5V  
5V  
Load  
Notes  
3
30 pF  
Typ  
50 pF  
Typ  
50 pF  
Typ  
Min  
Max  
Min  
Max  
Min  
Max  
(9)  
1
t
RP# High  
0.300  
1
µs  
PHWL  
Recovery to WE#  
Going Low  
(10)  
0.300  
t
Write Recovery  
before Read  
55  
0
60  
65  
0
ns  
µs  
WHGL  
V
Hold from  
t
t
1
3
0
PP  
QVVL  
Valid Status  
2
QVVL  
Register (CSR,  
GSR, BSR) Data  
and RY/BY# High  
t
t
1
2
Duration of  
Program Operation  
3,4,5,  
11  
4.5  
0.3  
6
TBD  
10  
4.5  
0.3  
6
TBD  
10  
4.5  
0.3  
6
TBD  
10  
µs  
WHQV  
Duration of Block  
Erase Operation  
3,4  
0.6  
0.6  
0.6  
sec  
WHQV  
NOTES:  
1. Read timings during program and erase are the same as for normal read.  
2. Refer to command definition tables for valid address and data values.  
3. Sampled, not 100% tested. Guaranteed by design.  
4. Program/erase durations are measured to valid Status Register (CSR) Data. V = 12V ± 0.6V.  
PP  
5. Word/byte program operations are typically performed with 1 Programming Pulse.  
6. Address and Data are latched on the rising edge of WE# for all command write operations.  
7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
8. Device speeds are defined as:  
65/70 ns at V  
CC  
=
equivalent to  
5V  
75 ns at V = 3.3V  
CC  
70/80 ns at V  
CC  
=
5V  
equivalent to  
120 ns at V = 3.3V  
CC  
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales  
office for more information.  
12. Page Buffer Programs only.  
47  
28F016SV FlashFile™ MEMORY  
E
WRITE VALID ADDRESS  
& DATA (DATA-WRITE) OR  
ERASE CONFIRM COMMAND  
WRITE READ EXTENDED  
REGISTER COMMAND  
DEEP  
POWER-DOWN  
WRITE DATA-WRITE OR  
ERASE SETUP COMMAND  
AUTOMATED DATA-WRITE  
OR ERASE DELAY  
READ EXTENDED  
STATUS REGISTER DATA  
V
IH  
ADDRESSES (A)  
A
A=RA  
IN  
V
NOTE 1  
IL  
t
t
t
AVAV  
WHAX  
WHAX  
READ COMPATIBLE  
STATUS REGISTER DATA  
t
AVWH  
V
NOTE 3  
IH  
ADDRESSES (A)  
V
A
IN  
NOTE 2  
IL  
t
t
AVAV  
AVWH  
V
V
IH  
IL  
CEx # (E)  
NOTE 4  
t
t
ELWL  
WHEH  
t
WHGL  
V
V
IH  
IL  
OE# (G)  
t
t
t
GHWL  
WHWL  
WHQV1,2  
V
V
IH  
IL  
WE# (W)  
t
WLWH  
DVWH  
t
t
WHDX  
V
V
IH  
IL  
HIGH Z  
t
DATA (D/Q)  
D
D
D
D
D
IN  
IN  
OUT  
IN  
IN  
PHWL  
t
WHRL  
V
OH  
OL  
RY/BY# (R)  
V
t
RHPL  
V
IH  
IL  
NOTE 5  
RP# (P)  
V
t
t
QVVL2  
VPWH2  
V
PPH2  
V
V
PPH1  
PPLK  
V
(V)  
PP  
NOTE 6  
t
VPWH1  
t
QVVL1  
V
IL  
NOTE 7  
0528_15  
NOTES:  
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.  
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.  
3. This cycle is invalid when using CSRD for verification during data program/erase operations.  
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.  
5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.  
6. VPP voltage during program/erase operations valid at both 12V and  
.
5V  
7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.  
Figure 15. AC Waveforms for Command Write Operations  
48  
E
28F016SV FlashFile™ MEMORY  
(1)  
5.9 AC Characteristics for CE#—Controlled Command Write Operations  
VCC = 3.3V ± 0.3V, TA = 0°C +70°C, –40°C +85°C  
Temp  
Speed  
Notes  
Commercial  
Extended  
Commercial  
Sym  
Parameter  
–80  
–100  
–120  
Unit  
Min  
80  
Typ Max Min Typ Max Min Typ Max  
tAVAV  
Write Cycle Time  
100  
100  
120  
100  
ns  
ns  
tVPEH1,2 VPP Setup to CE#  
Going High  
3,7  
3
100  
tPHWL  
tWLEL  
tAVEH  
tDVEH  
RP# Setup to WE#  
Going Low  
480  
0
480  
0
480  
0
ns  
ns  
ns  
ns  
WE# Setup to CE#  
Going Low  
3,7  
Address Setup to  
CE# Going High  
2,6,7  
2,6,7  
60  
60  
70  
70  
75  
75  
Data Setup to CE#  
Going High  
CE# Pulse Width  
7
65  
10  
70  
10  
75  
10  
ns  
ns  
tELEH  
tEHDX  
Data Hold from CE#  
High  
2,7  
tEHAX  
tEHWH  
tEHEL  
tGHEL  
tEHRL  
tRHPL  
Address Hold from  
CE# High  
2,7  
3
10  
5
30  
0
10  
ns  
ns  
ns  
ns  
ns  
ns  
WE# hold from CE#  
High  
10  
100 45  
0
CE# Pulse Width  
High  
7
15  
0
Read Recovery  
before Write  
3
0
1
CE# High to  
RY/BY# Going Low  
3,7  
3
100  
100  
RP# Hold from  
Valid Status  
0
75  
0
Register (CSR,  
GSR, BSR) Data  
and RY/BY# High  
tPHEL  
RP# High Recovery  
to CE# Going Low  
3,7  
0.480  
0
1
µs  
ns  
tEHGL  
Write Recovery  
before Read  
55  
95  
49  
28F016SV FlashFile™ MEMORY  
E
(1)  
5.9 AC Characteristics for CE#—Controlled Command Write Operations  
(Continued)  
VCC = 3.3V ± 0.3V, TA = 0°C +70°C, –40°C +85°C  
Temp  
Speed  
Notes  
3
Commercial  
Extended  
Commercial  
Sym  
Parameter  
–80  
–100  
–120  
Unit  
Min  
Typ Max Min Typ Max Min Typ Max  
tQVVL1,2 VPP Hold from Valid  
Status Register  
0
0
µs  
(CSR, GSR, BSR)  
Data and RY/BY#  
High  
tEHQV  
1
2
Duration of Program 3,4,5,11  
Operation  
5
9
TBD  
10  
5
9
TBD  
10  
5
9
TBD  
10  
µs  
tEHQV  
Duration of Block  
Erase Operation  
3,4  
0.3  
0.8  
0.3 0.8  
0.3 0.8  
sec  
50  
E
28F016SV FlashFile™ MEMORY  
(1)  
5.9AC Characteristics for CE#—Controlled Command Write Operations  
(Continued)  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0° to +70°C, –40°C to +85°C  
5V  
5V  
Temp  
Commercial  
Extended  
Speed  
–65  
± 5%  
–70  
–80  
Sym  
Parameter  
V
± 10%  
± 10%  
5V  
Unit  
CC  
5V  
5V  
Load  
30 pF  
Typ  
50 pF  
Typ  
50 pF  
Typ  
Notes  
Min  
65  
Max  
Min  
70  
Max  
Min  
80  
Max  
t
t
Write Cycle Time  
ns  
ns  
AVAV  
1,2  
V
Setup to CE#  
PP  
3,7  
3
100  
100  
100  
VPEH  
PHWL  
WLEL  
AVEH  
DVEH  
ELEH  
EHDX  
EHAX  
EHWH  
EHEL  
GHEL  
EHRL  
RHPL  
Going High  
(9)  
480  
t
t
t
t
t
t
t
t
t
t
t
t
RP# Setup to WE#  
Going Low  
300  
0
480  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(10)  
300  
WE# Setup to CE#  
Going Low  
3,7  
2,6,7  
2,6,7  
7
0
(9)  
Address Setup to  
CE# Going High  
40  
40  
45  
0
50  
45  
50  
50  
50  
0
(10)  
(9)  
Data Setup to CE#  
Going High  
50  
45  
(10)  
(9)  
CE# Pulse Width  
45  
50  
(10)  
Data Hold from CE#  
High  
2,7  
2,7  
3,7  
7
0
Address Hold from  
CE# High  
10  
5
10  
10  
10  
30  
0
(9)  
WE# Hold from CE#  
High  
10  
5
(10)  
(9)  
CE# Pulse Width  
High  
15  
0
30  
(10)  
15  
Read Recovery  
before Write  
3
0
CE# High to RY/BY#  
Going Low  
3,7  
3
100  
100  
100  
RP# Hold from Valid  
Status Register  
(CSR, GSR, BSR)  
Data and RY/BY#  
High  
0
0
0
51  
28F016SV FlashFile™ MEMORY  
E
(1)  
5.9AC Characteristics for CE#—Controlled Command Write Operations  
(Continued)  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0° to +70°C, –40°C to +85°C  
5V  
5V  
Temp  
Commercial  
Extended  
Speed  
–65  
± 5%  
–70  
–80  
Sym  
Parameter  
V
± 10%  
± 10%  
5V  
Unit  
CC  
5V  
5V  
Load  
Notes  
3,7  
30 pF  
Typ  
50 pF  
Typ  
50 pF  
Typ  
Min  
Max  
Min  
Max  
Min  
Max  
(9)  
1
t
t
t
RP# High Recovery  
to CE# Going Low  
0.300  
1
µs  
ns  
µs  
PHEL  
(10)  
0.300  
Write Recovery  
before Read  
55  
0
60  
65  
0
EHGL  
QVVL  
1,2  
V
Hold from Valid  
3
0
PP  
Status Register  
(CSR, GSR, BSR)  
Data at RY/BY# High  
t
t
1
Duration of Program 3,4,5,11  
Operation  
4.5  
0.3  
6
TBD  
10  
4.5  
0.3  
6
TBD  
10  
4.5  
0.3  
6
TBD  
10  
µs  
EHQV  
2
Duration of Block  
Erase Operation  
3,4  
0.6  
0.6  
0.6  
sec  
EHQV  
NOTES:  
1. Read timings during program and erase are the same as for normal read.  
2. Refer to command definition tables for valid address and data values.  
3. Sampled, not 100% tested. Guaranteed by design.  
4. Program/erase durations are measured to valid Status Data. V = 12V ± 0.6V.  
PP  
5. Word/byte program operations are typically performed with 1 Programming Pulse.  
6. Address and Data are latched on the rising edge of CE# for all command write operations.  
7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
8. Device speeds are defined as:  
65/70 ns at V  
CC  
=
equivalent to  
5V  
75 ns at V = 3.3V  
CC  
70/80 ns at V  
CC  
=
5V  
equivalent to  
120 ns at V = 3.3V  
CC  
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales  
office for more information.  
52  
E
28F016SV FlashFile™ MEMORY  
WRITE VALID ADDRESS  
& DATA (DATA-WRITE) OR  
ERASE CONFIRM COMMAND  
WRITE READ EXTENDED  
REGISTER COMMAND  
DEEP  
POWER-DOWN  
WRITE DATA-WRITE OR  
ERASE SETUP COMMAND  
AUTOMATED DATA-WRITE  
OR ERASE DELAY  
READ EXTENDED  
STATUS REGISTER DATA  
V
IH  
ADDRESSES (A)  
V
A
A=RA  
IN  
NOTE 1  
IL  
t
t
AVAV  
EHAX  
EHAX  
READ COMPATIBLE  
STATUS REGISTER DATA  
t
AVEH  
V
NOTE 3  
IH  
ADDRESSES (A)  
V
A
IN  
NOTE 2  
IL  
t
t
t
AVAV  
AVEH  
V
V
IH  
IL  
WE# (W)  
t
t
WLEL  
EHWH  
t
EHGL  
V
V
IH  
IL  
OE# (G)  
t
t
t
GHEL  
EHEL  
EHQV1,2  
V
V
IH  
IL  
CEx#(E)  
NOTE 4  
t
ELEH  
DVEH  
t
t
EHDX  
V
V
IH  
IL  
HIGH Z  
t
DATA (D/Q)  
D
D
D
D
D
IN  
IN  
IN  
OUT  
IN  
PHEL  
t
EHRL  
V
OH  
OL  
RY/BY# (R)  
V
t
RHPL  
V
IH  
IL  
NOTE 5  
RP# (P)  
V
t
t
QVVL2  
VPEH2  
V
PPH2  
V
V
V
PPH1  
PPLK  
IL  
V
(V)  
PP  
NOTE 6  
t
t
VPEH1  
QVVL1  
NOTE 7  
0528_16  
NOTES:  
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.  
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.  
3. This cycle is invalid when using CSRD for verification during data program/erase operations.  
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.  
5. RP# low transition is only to show tRHPL; not valid for above read and write cycles.  
6. VPP voltage during program/erase operations valid at both 12V and  
.
5V  
7. VPP voltage equal to or below VPPLK provides complete flash memory array protection.  
Figure 16. Alternate AC Waveforms for Command Write Operations  
53  
28F016SV FlashFile™ MEMORY  
E
(1)  
5.10 AC Characteristics for WE#—Controlled Page Buffer Write Operations  
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C  
Temp  
Commercial/Extended  
Sym  
Parameter  
Speed  
Notes  
2
–75, –100, –120  
Unit  
Min  
Typ  
Max  
tAVWL  
Address Setup to WE# Going Low  
0
ns  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
5V  
5V  
Temp  
Speed  
VCC  
Commercial  
Comm/Ext  
–65  
± 5%  
–70  
–80  
Sym  
Parameter  
± 10%  
± 10%  
Unit  
5V  
30 pF  
5V  
5V  
Load  
50 pF  
50 pF  
Notes Min Typ Max Min Typ Max Min Typ Max  
tAVWL Address Setup to  
WE# Going Low  
2
0
0
0
ns  
NOTES:  
1. All other specifications for WE#—Controlled Write Operations can be found in section 5.8.  
2. Address must be valid during the entire WE# low pulse.  
3. Device speeds are defined as:  
65/70 ns at V  
CC  
=
equivalent to  
5V  
75 ns at V = 3.3V  
CC  
70/80 ns at V  
CC  
=
5V  
equivalent to  
120 ns at V = 3.3V  
CC  
4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
54  
E
28F016SV FlashFile™ MEMORY  
V
IH  
CEx#  
(E)  
V
Note 1  
IL  
t
WHEH  
t
ELWL  
V
IH  
t
WE#  
(W)  
WHWL  
V
t
IL  
AVWL  
t
WLWH  
t
WHAX  
V
IH  
ADDRESSES (A)  
V
VALID  
IL  
t
t
WHDX  
DVWH  
V
IH  
HIGH Z  
DATA  
(D/Q)  
D
IN  
V
IL  
0528_17  
NOTE:  
1. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
Figure 17. WE#—Controlled Page Buffer Write Timing Waveforms  
(Loading Data to the Page Buffer)  
55  
28F016SV FlashFile™ MEMORY  
E
(1)  
5.11 AC Characteristics for CE#—Controlled Page Buffer Write Operations  
V
CC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C  
Temp  
Commercial/Extended  
Sym  
Parameter  
Speed  
Notes  
2,3  
–75, –100, –120  
Unit  
Min  
Typ  
Max  
tAVEL  
Address Setup to CE# Going Low  
0
ns  
VCC  
=
± 0.5V,  
± 0.25V, TA = 0°C to +70°C, –40°C to +85°C  
5V  
5V  
Temp  
Speed  
VCC  
Commercial  
Comm/Ext  
–65  
± 5%  
–70  
–80  
Sym  
Parameter  
± 10%  
± 10%  
Unit  
5V  
30 pF  
5V  
5V  
Load  
50 pF  
50 pF  
Notes Min Typ Max Min Typ Max Min Typ Max  
2,3  
tAVEL  
Address Setup to  
CE# Going Low  
0
0
0
ns  
NOTES:  
1. All other specifications for CE#—Controlled Write Operations can be found in Section 5.9.  
2. Address must be valid during the entire WE# low pulse.  
3. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
4. Device speeds are defined as:  
65/70 ns at V  
CC  
=
equivalent to  
5V  
75 ns at V = 3.3V  
CC  
70/80 ns at V  
CC  
=
5V  
equivalent to  
120 ns at V = 3.3V  
CC  
5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.  
56  
E
28F016SV FlashFile™ MEMORY  
V
IH  
WE#  
(W)  
V
IL  
t
EHWH  
t
WLEL  
V
IH  
CEx#  
(E)  
t
EHEL  
Note 1  
V
t
IL  
AVEL  
t
ELEH  
t
EHAX  
V
IH  
ADDRESSES (A)  
V
VALID  
IL  
t
t
EHDX  
DVEH  
V
IH  
HIGH Z  
DATA  
(D/Q)  
D
IN  
V
IL  
0528_18  
NOTE:  
1. CEx# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.  
Figure 18. CE#—Controlled Page Buffer Write Timing Waveforms  
(Loading Data to the Page Buffer)  
57  
28F016SV FlashFile™ MEMORY  
E
(3,5)  
5.12 Erase and Word/Byte Program Performance  
VCC = 3.3V ± 0.3V, VPP  
=
± 0.5V, TA = 0°C to +70°C  
5V  
Symbol  
Parameter  
Notes  
2,6,7  
2,6,7  
2,7  
Min  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
1.0  
Typ(1)  
Max Units Test Conditions  
Page Buffer Byte Write Time  
Page Buffer Word Write Time  
8.0  
16.0  
29.0  
35.0  
1.9  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
75  
µs  
µs  
tWHRH1A Byte Program Time  
tWHRH1B Word Program Time  
µs  
2,7  
µs  
tWHRH  
2
3
Block Program Time  
Block Program Time  
Block Erase Time  
2,7  
sec Byte Prog. Mode  
tWHRH  
2,7  
1.2  
sec Word Prog. Mode  
2,7  
1.4  
sec  
sec  
µs  
Full Chip Erase Time  
2,7  
44.8  
12  
Erase Suspend Latency Time  
to Read  
4
Auto Erase Suspend Latency  
Time to Program  
4.0  
15  
80  
µs  
V
CC = 3.3V ± 0.3V, VPP = 12V ± 0.6V, TA = 0°C to +70°C  
Symbol  
Parameter  
Notes  
2,6,7  
2,6,7  
2,7  
Min  
TBD  
TBD  
5
Typ(1)  
2.2  
4.4  
9
Max Units Test Conditions  
Page Buffer Byte Write Time  
Page Buffer Word Write Time  
Word/Byte Program Time  
Block Program Time  
TBD  
TBD  
TBD  
2.1  
µs  
µs  
tWHRH  
tWHRH  
tWHRH  
1
2
3
µs  
2,7  
TBD  
TBD  
0.3  
0.6  
0.3  
0.8  
25.6  
9
sec Byte Prog. Mode  
Block Program Time  
2,7  
1.0  
sec Word Prog. Mode  
Block Erase Time  
2
10  
sec  
sec  
µs  
Full Chip Erase Time  
2,7  
TBD  
1.0  
TBD  
55  
Erase Suspend Latency Time  
to Read  
4
Auto Erase Suspend Latency  
Time to Program  
4.0  
12  
60  
µs  
58  
E
28F016SV FlashFile™ MEMORY  
(3,5)  
5.12 Erase and Word/Byte Program Performance  
VCC = 5V ± 0.5V, 5V ± 0.25V, VPP = 5V ± 0.5V, TA = 0°C to +70°C  
(Continued)  
Symbol  
Parameter  
Notes  
2,6,7  
2,6,7  
2,7  
Min  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
1.0  
Typ(1)  
Max  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
55  
Units Test Conditions  
Page Buffer Byte Write Time  
8.0  
16.0  
20  
µs  
µs  
µs  
µs  
Page Buffer Word Write Time  
tWHRH1A Byte Program Time  
tWHRH1B Word Program Time  
2,7  
25  
tWHRH  
2
3
Block Program Time  
Block Program Time  
Block Erase Time  
2,7  
1.4  
0.85  
1.0  
32.0  
9
sec  
sec  
sec  
sec  
µs  
Byte Prog. Mode  
Word Prog. Mode  
tWHRH  
2,7  
2,7  
Full Chip Erase Time  
2,7  
Erase Suspend Latency Time  
to Read  
4
Auto Erase Suspend Latency  
Time to Program  
3.0  
12  
60  
µs  
VCC = 5V ± 0.5V, 5V ± 0.25V, VPP = 12V ± 0.6V, TA = 0°C to +70°C  
Symbol  
Parameter  
Page Buffer Byte Write Time  
Page Buffer Word Write Time  
Word/Byte Program Time  
Block Program Time  
Notes  
2,6,7  
2,6,7  
2,7  
Min  
TBD  
TBD  
4.5  
Typ(1)  
2.1  
4.1  
6
Max  
TBD  
TBD  
TBD  
2.1  
Units Test Conditions  
µs  
µs  
µs  
tWHRH  
tWHRH  
tWHRH  
1
2
3
2,7  
TBD  
TBD  
0.3  
0.4  
0.2  
0.6  
19.2  
7
sec  
sec  
sec  
sec  
µs  
Byte Prog. Mode  
Word Prog. Mode  
Block Program Time  
2,7  
1.0  
Block Erase Time  
2
10  
Full Chip Erase Time  
2,7  
TBD  
1.0  
TBD  
40  
Erase Suspend Latency Time  
to Read  
4
Auto Erase Suspend Latency  
Time to Program  
3.0  
10  
45  
µs  
NOTES:  
1. +25°C, and nominal voltages.  
2. Excludes system-level overhead.  
3. These performance numbers are valid for all speed versions.  
4. Specification applies to interrupt latency for single block erase. Suspend latency for erase all unlocked blocks operation  
extends the maximum latency time to 270 µs.  
5. Sampled, but not 100% tested. Guaranteed by design.  
6. Assumes using the full Page Buffer to Program to Flash (256 bytes or 128 words).  
7. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales  
office for more information.  
59  
28F016SV FlashFile™ MEMORY  
E
6.0 MECHANICAL SPECIFICATIONS  
048928.eps  
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead TSOP Type I Package  
Family: Thin Small Out-Line Package  
Symbol  
Millimeters  
Nominal  
Notes  
Minimum  
Maximum  
A
1.20  
A
A
0.050  
0.965  
0.100  
0.115  
18.20  
13.80  
1
2
0.995  
0.150  
0.125  
18.40  
14.00  
0.50  
1.025  
0.200  
0.135  
18.60  
14.20  
b
c
D
1
E
e
D
L
19.80  
0.500  
20.00  
0.600  
56  
20.20  
0.700  
N
0°  
3°  
5°  
Y
Z
0.100  
0.350  
0.150  
0.250  
60  
E
28F016SV FlashFile™ MEMORY  
a
He  
E
R1  
A2  
b
R2  
L
1
Detail A  
D
A
e
B
Y
C
A1  
1
See Detail A  
0528_20  
Figure 20. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package  
Family: Shrink Small Out-Line Package  
Symbol  
Millimeters  
Nominal  
1.80  
Notes  
Minimum  
Maximum  
1.90  
A
A1  
A2  
B
0.47  
1.18  
0.52  
0.57  
1.28  
1.38  
0.25  
0.30  
0.40  
C
0.13  
0.15  
0.20  
D
23.40  
13.10  
23.70  
13.30  
0.80  
24.00  
13.50  
E
e1  
He  
N
15.70  
0.45  
16.00  
56  
16.30  
L1  
Y
0.50  
0.55  
0.10  
4°  
a
2°  
3°  
3°  
4°  
b
5°  
R1  
R2  
0.15  
0.15  
0.20  
0.20  
0.25  
0.25  
61  
28F016SV FlashFile™ MEMORY  
E
APPENDIX A  
DEVICE NOMENCLATURE AND ORDERING  
INFORMATION  
Product line designator for all Intel Flash products  
-
5
E28F0 16SV 06  
Package  
Access Speed (ns)  
DA = Commercial Temp.  
65 ns (5V, 30 pF), 70 ns (5V), 75 ns (3.3V)  
70 ns (5V, 30 pF), 80 ns (5V), 120 ns (3.3V)  
56-Lead SSOP  
E = Commercial Temp.  
56-Lead TSOP  
T = Extended Temp.  
56-Lead SSOP  
Device Type  
V = SmartVoltage  
Product Family  
S = FlashFile™ Memory  
Device Density  
016 = 16 Mbit  
0528_21  
Valid Combinations  
Option  
Order Code  
VCC = 3.3V ± 0.3V,  
50 pF load,  
VCC  
=
± 10%,  
VCC  
=
± 5%, 30  
5V  
5V  
pF load  
100 pF load  
1.5V I/O Levels(1)  
TTL I/O Levels(1)  
1.5V I/O Levels(1)  
E28F016SV-070  
E28F016SV-065  
DA28F016SV-070  
DA28F016SV-065  
DT28F016SV-080  
1
2
3
4
5
E28F016SV 070  
E28F016SV 065  
DA28F016SV 070  
DA28F016SV 065  
DT28F016SV 080  
E28F016SV-120  
E28F016SV-075  
DA28F016SV-120  
DA28F016SV-075  
DT28F016SV-100  
E28F016SV-080  
E28F016SV-070  
DA28F016SV-080  
DA28F016SV-070  
DT28F016SV-080  
NOTE:  
1. See Section 5.2 for Transient Input/Output Reference Waveforms and Testing Load Circuits.  
62  
E
28F016SV FlashFile™ MEMORY  
APPENDIX B  
(1,2)  
ADDITIONAL INFORMATION  
Order Number  
Document/Tool  
16-Mbit Flash Product Family User’s Manual  
28F008SA Datasheet  
297372  
290429  
290490  
DD28F032SA 32-Mbit (2 bit x 16, 4 Mbit x 8) FlashFile™ Memory  
Datasheet)  
292092  
292123  
292126  
AP-357 Power Supply Solutions for Flash Memory  
AP-374 Flash Memory Write Protection Techniques  
AP-377 16-Mbit Flash Product Family Software Drivers,  
28F016SA/28F016SV/28F016XS/28F016XD  
292144  
292159  
AP-393 28F016SV Compatibility with 28F016SA  
AP-607 Multi-Site Layout Planning with Intel’s FlashFile™ Components,  
Including ROM Capability  
292163  
292165  
294016  
AP-610 Flash Memory In-System Code and Data Update Techniques  
AB-62 Compiled Code Optimizations for Flash Memories  
ER-33 ETOX™ Flash Memory Technology—Insight to Intel’s Fourth  
Generation Process Innovation  
297508  
FLASHBuilder Utility  
Contact Intel/Distribution  
Sales Office  
Flash Cycling Utility  
Contact Intel/Distribution  
Sales Office  
28F016SV iBIS Model  
Contact Intel/Distribution  
Sales Office  
28F016SV VHDL  
Contact Intel/Distribution  
Sales Office  
28F016SV Timing Designer Library Files  
28F016SV Orcad and ViewLogic Schematic Symbols  
Contact Intel/Distribution  
Sales Office  
NOTES:  
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should  
contact their local Intel or distribution sales office.  
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.  
63  

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