E28F400BX-B60 [INTEL]
4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY; 4兆位（ 256K X 16 ， 512K ×8 ）， BOOT BLOCK闪存系列
| 型号： | E28F400BX-B60 |
| 厂家： | 
INTEL |
| 描述： | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 文件： | 总50页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-MBIT (256K X 16, 512K X 8)
BOOT BLOCK
FLASH MEMORY FAMILY
28F400BX-T/B, 28F004BX-T/B
Y
Y
Y
x8/x16 Input/Output Architecture
Ð 28F400BX-T, 28F400BX-B
Ð For High Performance and High
Integration 16-bit and 32-bit CPUs
Very High-Performance Read
Ð 60/80/120 ns Maximum Access Time
Ð 30/40/40 ns Maximum Output Enable
Time
Y
Y
x8-only Input/Output Architecture
Ð 28F004BX-T, 28F004BX-B
Ð For Space Constrained 8-bit
Applications
Low Power Consumption
Ð 20 mA Typical Active Read Current
Reset/Deep Power-Down Input
Ð 0.2 mA I
Typical
Ð Acts as Reset for Boot Operations
CC
Y
Y
Upgradeable to Intel’s Smart Voltage
Products
Y
Extended Temperature Operation
b a
40 C to 85 C
Optimized High-Density Blocked
Architecture
Ð One 16-KB Protected Boot Block
Ð Two 8-KB Parameter Blocks
Ð One 96-KB Main Block
Ð
§
§
Write Protection for Boot Block
Y
Y
Hardware Data Protection Feature
Ð Erase/Write Lockout During Power
Transitions
Ð Three 128-KB Main Blocks
Ð Top or Bottom Boot Locations
Y
Industry Standard Surface Mount
Packaging
Ð 28F400BX: JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
Y
Y
Extended Cycling Capability
Ð 100,000 Block Erase Cycles
Automated Word/Byte Write and Block
Erase
Ð Command User Interface
Ð Status Registers
Ð Erase Suspend Capability
Ð 28F004BX: 40-Lead TSOP
Y
Y
12V Word/Byte Write and Block Erase
e
e
g
12V 5% Standard
g
12V 10% Option
Ð V
Ð V
PP
PP
Y
Y
SRAM-Compatible Write Interface
Automatic Power Savings Feature
ETOXTM III Flash Technology
Ð 5V Read
Ð 1 mA Typical I
CC
Static Operation
Active Current in
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290451-005
28F400BX-T/B, 28F004BX-T/B
Intel’s 4-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec-
tive erasure, automated write and erase operations and standard microprocessor interface. The 4-Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/out-
put control, very high speed, low power, an industry standard ROM compatible pinout and surface mount
packaging. The 4-Mbit flash family is an easy upgrade from Intel’s 2-Mbit Boot Block Flash Memory Family.
The Intel 28F400BX-T/B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F400BX-T and 28F400BX-B are
4,194,304-bit non-volatile memories organized as either 524,288 bytes or 262,144 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.
The Intel 28F004BX-T/B are 8-bit wide flash memories with 4,194,304 bits organized as 524,288 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F400BX-T/28F004BX-T provide block locations compatible with
Intel’s MCS-186 family, 80286, i386TM, i486TM, i860TM and 80960CA microprocessors. The 28F400BX-B/
28F004BX-B provide compatibility with Intel’s 80960KX and 80960SX families as well as other embedded
microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 60 ns, these 4-Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down
mode lowers the total V power consumption to 1 mW. This is critical in handheld battery powered systems.
CC
For very low power applications using a 3.3V supply, refer to the Intel 28F400BL-T/B, 28F004BL-T/B 4-Mbit
Boot Block Flash Memory Family datasheet.
Manufactured on Intel’s 0.8 micron ETOX III process, the 4-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4-Mbit density level.
2
28F400BX-T/B, 28F004BX-T/B
Follow these guidelines to ensure compatibility:
1.0 PRODUCT FAMILY OVERVIEW
Ý
1. Connect DU (WP on SmartVoltage products) to
a control signal or to V or GND.
Throughout this datasheet the 28F400BX refers to
both the 28F400BX-T and 28F400BX-B devices and
28F004BX refers to both the 28F004BX-T and
28F004BX-B devices. The 4-Mbit flash memory fam-
ily refers to both the 28F400BX and 28F004BX prod-
ucts. This datasheet comprises the specifications for
four separate products in the 4-Mbit flash memory
family. Section 1 provides an overview of the 4-Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F400BX and 28F004BX products respectively.
Section 4 combines a description of the family’s
principles of operations. Finally Section 5 describes
the family’s operating specifications.
CC
2. If adding a switch on V for write protection,
PP
switch to GND for complete write protection.
3. Allow for connecting 5V to V and disconnect
PP
12V from the V line, if desired.
PP
1.2 Main Features
The 28F400BX/28F004BX boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.
Seven Separately Erasable Blocks including a
Hardware-Lockable boot block (16,384 Bytes),
Two parameter blocks (8,192 Bytes each) and
Four main blocks (1 block of 98,304 Bytes and 3
blocks of 131,072 Bytes) are included on the 4-Mbit
family. An erase operation erases one of the main
blocks in typically 2.4 seconds and the boot or pa-
rameter blocks in typically 1.0 seconds independent
of the remaining blocks. Each block can be indepen-
dently erased and programmed 100,000 times.
Product Family
X8/X16 Products
28F400BX-T
X8-Only Products
28F004BX-T
28F400BX-B
28F004BX-B
1.1 Designing for Upgrade to
SmartVoltage Products
The Boot Block is located at either the top
(28F400BX-T, 28F004BX-T) or the bottom
(28F400BX-B, 28F004BX-B) of the address map in
order to accommodate different microprocessor pro-
tocols for boot code location. The hardware locka-
ble boot block provides the most secure code stor-
age. The boot block is intended to store the kernel
code required for booting-up a system. When the
Today’s high volume boot block products are up-
gradable to Intel’s SmartVoltage boot block prod-
ucts that provide program and erase operation at 5V
or 12V V
and read operation at 3V or 5V V
.
PP
CC
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:
Ý
1. DU pin is replaced by WP to provide a means
Ý
RP pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
to lock and unlock the boot block with logic sig-
nals.
Ý
be performed. When the RP pin is at or below 6.5V
2. 5V Program/Erase operation uses proven pro-
g
the boot block is locked and program and erase op-
erations to the boot block are ignored.
gram and erase techniques with 5V 10% ap-
plied to V
.
PP
The 28F400BX products are available in the ROM/
EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
3. Enhanced circuits optimize performance at 3.3V
.
V
CC
Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifica-
tions.
package as shown in Figures
3 and 4. The
28F004BX products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
When you design with 12V V boot block products
PP
you should provide the capability in your board de-
sign to upgrade to SmartVoltage products.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the 28F400BX
and 28F004BX flash memory products.
3
28F400BX-T/B, 28F004BX-T/B
Ý
Ý
When the CE and RP pins are at V
BYTE pin (28F400BX-only) is at either V
Program and Erase Automation allows program
and erase operations to be executed using a two-
write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there-
by unburdening the microprocessor or microcontrol-
ler. Writing of memory data is performed in word or
byte increments for the 28F400BX family and in byte
increments for the 28F004BX family typically within
9 ms which is a 100% improvement over current
flash memory products.
and the
CC
Ý
or
CC
GND the CMOS Standby mode is enabled where
is typically 50 mA.
I
CC
A Deep Power-Down Mode is enabled when the
Ý
RP pin is at ground minimizing power consumption
and providing write protection during power-up con-
current during deep power-down mode
is 0.20 mA typical. An initial maximum access time
ditions. I
CC
Ý
or Reset Time of 300 ns is required from RP
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recog-
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Ý
nized. When RP is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre-
vents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP to reset the memory to nor-
mal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
Maximum Access Time of 60 ns (t
over the commercial temperature range (0 C to
) is achieved
§
ACC
Ý
70 C), 5% V
supply voltage range (4.75V to
§
CC
5.25V) and 30 pF output load. Maximum Access
Time of 70 ns (t ) is achieved over the commer-
cial temperature range, 10% V supply range (4.5V
ACC
Ý
4-Mbit family and the RP functionality for data pro-
CC
to 5.5V) and 100 pF output load.
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec-
Ý
ognize any operation until RP returns to its normal
state.
I
maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation. I Erase
PP
PP
current is 30 mA maximum. V erase and pro-
PP
gramming voltage is 11.4V to 12.6V (V
e
12V
5%) under all operating conditions. As an op-
For the 28F400BX, Byte-wide or Word-wide In-
put/Output Control is possible by controlling the
PP
g
tion, V can also vary between 10.8V to 13.2V (V
e
block erase cycles.
Ý
Ý
BYTE pin. When the BYTE pin is at a logic low
the device is in the byte-wide mode (x8) and data is
PP
PP
10%) with a guaranteed number of 100
g
12V
[ ]
read and written through DQ 0:7 . During the byte-
[
]
wide mode, DQ 8:14 are tri-stated and DQ15/A-1
becomes the lowest order address pin. When the
Typical I Active Current of 25 mA is achieved
CC
for the X16 products (28F400BX). Typical I
Ý
BYTE pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
Ac-
tive Current of 20 mA is achieved for the X8 prod-
CC
[ ]
through DQ 0:15 .
ucts (28F400BX, 28F004BX). Refer to the I active
CC
current derating curves in this datasheet.
The 4-Mbit boot block flash memory family is also
designed with an Automatic Power Savings (APS)
feature to minimize system battery current drain and
allows for very low power designs. Once the device
is accessed to read array data, APS mode will imme-
diately put the memory in static mode of operation
where I
active current is typically 1 mA until the
CC
next read is initiated.
4
28F400BX-T/B, 28F004BX-T/B
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 4-Mbit flash memory
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash memory products’ power-down
mode provides added flexibility for these battery-
operated portable designs which require operation
at very low power levels.
1.3 Applications
The 4-Mbit boot block flash memory family com-
bines high density, high performance, cost-effective
flash memories with blocking and hardware protec-
tion capabilities. Its flexibility and versatility will re-
duce costs throughout the product life cycle. Flash
memory is ideal for Just-In-Time production flow, re-
ducing system inventory and costs, and eliminating
component handling during the production phase.
The 4-Mbit flash memory products also provide ex-
cellent design solutions for Digital Cellular Phone
and Telecommunication switching applications re-
quiring high performance, high density storage capa-
bility coupled with modular software designs, and a
small form factor package (X8-only bus). The
4-Mbit’s blocking scheme allows for an easy seg-
mentation of the embedded code with; 16 Kbytes of
Hardware-Protected Boot code, 4 Main Blocks of
program code and 2 Parameter Blocks of 8 Kbytes
each for frequently updatable data storage and diag-
nostic messages (e.g., phone numbers, authoriza-
tion codes). Figure 2 is an example of such an appli-
cation with the 28F004BX-T.
During the product life cycle, when code updates or
feature enhancements become necessary, flash
memory will reduce the update costs by allowing ei-
ther a user-performed code change via floppy disk
or a remote code change via a serial link. The 4-Mbit
boot block flash memory family provides full func-
tion, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-able applications
storage, Digital Cellular Phone program and data
storage, Telecommunication boot/firmware, Print-
er firmware/font storage and various other embed-
ded applications where both program and data stor-
age are required.
These are a few actual examples of the wide range
of applications for the 4-Mbit Boot Block flash mem-
ory family which enable system designers achieve
the best possible product design. Only your imagina-
tion limits the applicability of such a versatile product
family.
Reprogrammable systems such as personal com-
puters, are ideal applications for the 4-Mbit flash
memory products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor tech-
nology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of
a 28F400BX-T application.
5
28F400BX-T/B, 28F004BX-T/B
290451–4
Figure 1. 28F400BX Interface to Intel386TMEX Embedded Processor
290451–24
Figure 2. 28F004BX Interface to INTEL 80C188EB 8-Bit Embedded Processor
6
28F400BX-T/B, 28F004BX-T/B
The 28F004BX 40-Lead TSOP pinout shown in Fig-
ure 5 is 100% compatible and provides a density
upgrade for the 2-Mbit Boot Block flash memory or
the 28F002BX.
1.4 Pinouts
The 28F400BX 44-Lead PSOP pinout follows the in-
dustry standard ROM/EPROM pinout as shown in
Figure 3. Furthermore, the 28F400BX 56-Lead
TSOP pinout shown in Figure 4 provides density up-
grades to future higher density boot block memories.
290451–25
Figure 3. PSOP Lead Configuration for x8/x16 28F400BX
7
28F400BX-T/B, 28F004BX-T/B
290451–3
Figure 4. TSOP Lead Configuration for x8/x16 28F400BX
290451–20
Figure 5. TSOP Lead Configuration for x8 28F004BX
8
28F400BX-T/B, 28F004BX-T/B
1.5 28F400BX Pin Descriptions
Symbol
A –A
Type
Name and Function
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write
cycle.
0
17
A
9
I
ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this mode A
9 0
Ý
decodes between the manufacturer and device ID’s. When BYTE is at a logic low only the
lower byte of the signatures are read. DQ /A is a don’t care in the signature mode when
b
15
1
Ý
BYTE is low.
Ý
Ý
DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle during a
program command. Inputs commands to the command user interface when CE and WE
DQ –DQ
0
I/O
7
Ý
Ý
are active. Data is internally latched during the write and program cycles. Outputs array,
Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled.
Ý
Ý
DQ –DQ
8
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle during a
program command. Data is internally latched during the write and program cycles. Outputs
array data. The data pins float to tri-state when the chip is deselected or the outputs are
15
e
Ý
disabled as in the byte-wide mode (BYTE
‘‘0’’). In the byte-wide mode DQ /A
b
15 1
becomes the lowest order address for data output on DQ -DQ .
7
0
Ý
Ý
CE
RP
I
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
Ý
Ý
amplifiers. CE is active low; CE high deselects the memory device and reduces power
consumption to standby levels. If CE and RP are high, but not at a CMOS high level, the
Ý
Ý
Ý
Ý
standby current will increase due to current flow through the CE and RP input stages.
RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in deep power-
down mode. Locks the boot block from program/erase.
Ý
When RP is at logic high level and equals 6.5V maximum the boot block is locked and
cannot be programmed or erased.
e
Ý
When RP
erased.
11.4V minimum the boot block is unlocked and can be programmed or
Ý
When RP is at a logic low level the boot block is locked, the deep power-down mode is
enabled and the WSM is reset preventing any blocks from being programmed or erased,
therefore providing data protection during power transitions.
Ý
When RP transitions from logic low to logic high the flash memory enters the read-array
mode.
Ý
OE
I
I
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a read cycle.
Ý
OE is active low.
Ý
Ý
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE is active
Ý
low. Addresses and data are latched on the rising edge of the WE pulse.
WE
Ý
Ý
BYTE ENABLE: Controls whether the device operates in the byte-wide mode (x8) or the
BYTE
Ý
word-wide mode (x16). BYTE pin must be controlled at CMOS levels to meet 100A CMOS
e
Ý
current in the standby mode. BYTE
and programmed on DQ –DQ and DQ /A
b
1
‘‘0’’ enables the byte-wide mode, where data is read
becomes the lowest order address that
0
7
15
decodes between the upper and lower byte. DQ –DQ are tri-stated during the byte-wide
e
8
14
‘‘1’’ enables the word-wide mode where data is read and programmed on
Ý
mode. BYTE
DQ –DQ
.
15
0
V
V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming
data in each block.
PP
k
Note: V
PP
V
memory contents cannot be altered.
PPLMAX
g
g
DEVICE POWER SUPPLY (5V 10%, 5V 5%)
CC
GND
NC
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
DON’T USE PIN: Pin should not be connected to anything.
DU
9
28F400BX-T/B, 28F004BX-T/B
1.6 28F004BX Pin Descriptions
Symbol
A –A
Type
I
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
0
18
A
I
ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this
9
mode A decodes between the manufacturer and device ID’s.
9
0
Ý
Ý
DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
during a program command. Inputs commands to the command user interface when
DQ –DQ
0
I/O
7
Ý
Ý
CE and WE are active. Data is internally latched during the write and program
cycles. Outputs array, Intelligent Identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.
Ý
Ý
CE
RP
I
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
Ý
Ý
sense amplifiers. CE is active low; CE high deselects the memory device and
Ý
Ý
reduces power consumption to standby levels. If CE and RP are high, but not at
a CMOS high level, the standby current will increase due to current flow through the
Ý
Ý
CE and RP input stages.
RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
Ý
When RP is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
e
Ý
When RP
or erased.
11.4V minimum the Boot Block is unlocked and can be programmed
Ý
When RP is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power transitions.
Ý
When RP transitions from logic low to logic high, the flash memory enters the
read-array mode.
Ý
OE
I
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
Ý
read cycle. OE is active low.
Ý
Ý
WE
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
Ý
is active low. Addresses and data are latched on the rising edge of the WE pulse.
V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
PP
k
NOTE: V
PP
V
memory contents cannot be altered.
PPLMAX
g
g
DEVICE POWER SUPPLY (5V 10%, 5V 5%)
V
CC
GND
NC
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
DON’T USE PIN: Pin should not be connected to anything.
DU
10
28F400BX-T/B, 28F004BX-T/B
2.0 28F400BX WORD/BYTE-WIDE PRODUCTS DESCRIPTION
Figure 6. 28F400BX Word/Byte Block Diagram
11
28F400BX-T/B, 28F004BX-T/B
2.1.2 BLOCK MEMORY MAP
2.1 28F400BX Memory Organization
Two versions of the 28F400BX product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F400BX-T
memory map is inverted from the 28F400BX-B
memory map.
2.1.1 BLOCKING
The 28F400BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F400BX is
a random read/write memory, only erasure is per-
formed by block.
2.1.2.1. 28F400BX-B Memory Map
The 28F400BX-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H. In the
28F400BX-B the first 8-Kbyte parameter block re-
sides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH. The three 128-Kbyte main
block resides in memory space from 10000H to
1FFFFH, 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 7.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
Ý
erased when RP is not at 12V. The boot block can
be erased and written when RP is held at 12V for
Ý
(Word Addresses)
3FFFFH
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address lo-
cations of the boot block for the 28F400BX-T and
28F400BX-B.
128-Kbyte MAIN BLOCK
30000H
2FFFFH
2.1.1.2 Parameter Block Operation
128-Kbyte MAIN BLOCK
The 28F400BX has 2 parameter blocks (8-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa-
rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks pro-
vide for more efficient memory utilization when deal-
ing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for ad-
dress locations of the parameter blocks for the
28F400BX-T and 28F400BX-B.
20000H
1FFFFH
128-Kbyte MAIN BLOCK
10000H
0FFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
03000H
02FFFH
8-Kbyte PARAMETER BLOCK
02000H
2.1.1.3 Main Block Operation
01FFFH
16-Kbyte BOOT BLOCK
Four main blocks of memory exist on the 28F400BX
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F400BX-T
and 28F400BX-B products.
00000H
Figure 7. 28F400BX-B Memory Map
12
28F400BX-T/B, 28F004BX-T/B
2.1.2.2 28F400BX-T Memory Map
(Word Addresses)
The 28F400BX-T device has the 16-Kbyte boot
block located from 3E000H to 3FFFFH to accom-
modate those microprocessors that boot from the
top of the address map. In the 28F400BX-T the first
8-Kbyte parameter block resides in memory space
from 3D000H to 3DFFFH. The second 8-Kbyte pa-
rameter block resides in memory space from
3C000H to 3CFFFH. The 96-Kbyte main block re-
sides in memory space from 30000H to 3BFFFH.
The three 128-Kbyte main blocks reside in memory
space from 20000H to 2FFFFH, 10000H to 1FFFFH
and 00000H to 0FFFFH as shown below in Figure 8.
3FFFFH
16-Kbyte BOOT BLOCK
3E000H
3DFFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
3D000H
3CFFFH
3C000H
3BFFFH
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
30000H
2FFFFH
20000H
1FFFFH
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
10000H
0FFFFH
00000H
Figure 8. 28F400BX-T Memory Map
13
28F400BX-T/B, 28F004BX-T/B
3.0 28F004BX PRODUCT DESCRIPTION
Figure 9. 28F004BX Byte-Wide Block Diagram
14
28F400BX-T/B, 28F004BX-T/B
3.1.2 BLOCK MEMORY MAP
3.1 28F004BX Memory Organization
Two versions of the 28F004BX product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BX-T
memory map is inverted from the 28F004BX-B
memory map.
3.1.1 BLOCKING
The 28F004BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F004BX is
a random read/write memory, only erasure is per-
formed by block.
3.1.2.1 28F004BX-B Memory Map
The 28F004BX-B device has the 16-Kbyte boot
block located from 00000H to 03FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H. In the
28F004BX-B the first 8-Kbyte parameter block re-
sides in memory from 04000H to 05FFFH. The sec-
ond 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128-Kbyte main block reside in
memory space from 20000H to 3FFFFH, 40000H to
5FFFFH and 60000H to 7FFFFH. See Figure 10.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
Ý
or erased when RP is not at 12V. The boot block
can be erased and programmed when RP is held
Ý
7FFFFH
at 12V for the duration of the erase or program oper-
ation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BX-T and 28F004BX-B.
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
3.1.1.2 Parameter Block Operation
40000H
3FFFFH
The 28F004BX has 2 parameter blocks (8-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa-
rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map sec-
tion for address locations of the parameter blocks
for the 28F004BX-T and 28F004BX-B.
128-Kbyte MAIN BLOCK
20000H
1FFFFH
96-Kbyte MAIN BLOCK
08000H
07FFFH
8-Kbyte PARAMETER BLOCK
06000H
05FFFH
8-Kbyte PARAMETER BLOCK
04000H
03FFFH
16-Kbyte BOOT BLOCK
3.1.1.3 Main Block Operation
00000H
Four main blocks of memory exist on the 28F004BX
c
Figure 10. 28F004BX-B Memory Map
c
(3
128-Kbyte blocks and 1
96-Kbyte blocks).
See the following section on Block Memory Map for
the address location of these blocks for the
28F004BX-T and 28F004BX-B.
15
28F400BX-T/B, 28F004BX-T/B
3.1.2.2 28F004BX-T Memory Map
4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
The 28F004BX-T device has the 16-Kbyte boot
block located from 7C000H to 7FFFFH to accom-
modate those microprocessors that boot from the
top of the address map. In the 28F004BX-T the first
8-Kbyte parameter block resides in memory space
from 7A000H to 7BFFFH. The second 8-Kbyte pa-
rameter block resides in memory space from
78000H to 79FFFH. The 96-Kbyte main block re-
sides in memory space from 60000H to 77FFFH.
The three 128-Kbyte main blocks reside in memory
space from 40000H to 5FFFFH, 20000H to 3FFFFH
and 00000H to 1FFFFH.
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 4-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
The CUI allows for 100% TTL-level control inputs,
fixed power supplies during erasure and program-
ming, and maximum EPROM compatibility.
In the absence of high voltage on the V pin, the
PP
4-Mbit boot block flash family will only successfully
execute the following commands: Read Array, Read
Status Register, Clear Status Register and Intelli-
gent Identifier mode. The device provides standard
EPROM read, standby and output disable opera-
tions. Manufacturer Identification and Device Identi-
fication data can be accessed through the CUI or
7FFFFH
16-Kbyte BOOT BLOCK
7C000H
7BFFFH
8-Kbyte PARAMETER BLOCK
7A000H
through the standard EPROM A high voltage ac-
9
79FFFH
8-Kbyte PARAMETER BLOCK
cess (V ) for PROM programming equipment.
ID
78000H
77FFFH
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the V pin. In addition, high voltage on V al-
lows write and erase of the device. All functions as-
sociated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
96-Kbyte MAIN BLOCK
PP
PP
60000H
5FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
128-Kbyte MAIN BLOCK
20000H
1FFFFH
Ý
WE interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
128-Kbyte MAIN BLOCK
00000H
4.1 28F400BX Bus Operations
Figure 11. 28F004BX-T Memory Map
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
16
28F400BX-T/B, 28F004BX-T/B
e
Ý
Table 1. Bus Operations for WORD-WIDE Mode (BYTE
V
)
IH
Ý
Ý
Ý
Ý
WE
Mode
Notes
RP
CE
OE
A
A
0
V
DQ
0–15
9
PP
Read
1, 2
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
OUT
IH
IL
IL
IH
Output Disable
V
IH
X
X
X
X
X
X
High Z
High Z
High Z
0089H
IH
IH
IL
IH
Standby
V
X
X
IH
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
9
V
X
X
X
IL
IH
IH
3, 4
V
V
V
V
V
V
V
ID
V
IL
IL
IL
IL
IH
IH
IL
3, 4, 5
V
V
V
ID
V
4470H
4471H
IH
Write
6, 7, 8
V
IH
V
V
V
X
X
X
D
IL
IH
IL
IN
e
Ý
Table 2. Bus Operations for BYTE-WIDE Mode (BYTE
V )
IL
Ý
Ý
Ý
Ý
WE
Mode
Notes RP
CE
OE
A
A
A
V
DQ
DQ
b
X
X
X
X
X
9
0
1
PP
0–7
8–14
Read
1, 2, 3
V
V
V
V
V
V
V
V
X
X
X
D
OUT
High Z
High Z
High Z
High Z
High Z
IH
IL
IL
IH
Output Disable
Standby
V
IH
X
X
X
X
X
X
X
X
X
X
High Z
High Z
High Z
89H
IH
IH
IL
IH
V
X
X
IH
Deep Power-Down
9
4
V
X
X
X
IL
Intelligent
Identifier (Mfr)
V
V
V
V
V
V
V
V
IH
V
V
IH
IL
IL
IL
IL
IL
IH
ID
IL
Intelligent
Identifier (Device)
4, 5
V
V
IH
V
V
X
X
X
X
70H
71H
High Z
High Z
IH
IH
ID
IH
Write
6, 7, 8
V
V
IL
X
X
D
IN
NOTES:
1. Refer to DC Characteristics.
2. X can be V , V for control pins and addresses, V
, V
or V
for V
.
PP
L IH
3. See DC Characteristics for V
PPL
, V , V voltages.
PPH
PPL PPH HH ID
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A –A
e
X.
1
17
e
6. Refer to Table 4 for valid D during a write operation.
5. Device ID
4470H for 28F400BX-T and 4471H for 28F400BX-B.
IN
7. Command writes for Block Erase or Word/Byte Write are only executed when V
e
V
.
PP
PPH
Ý
8. To write or erase the boot block, hold RP at V
.
HH
9. RP must be at GND 0.2V to meet the 1.2 mA maximum deep power-down current.
Ý
g
17
28F400BX-T/B, 28F004BX-T/B
4.2 28F004BX Bus Operations
Table 3. Bus Operations
Ý
Ý
Ý
Ý
WE
Mode
Notes
RP
CE
OE
A
A
0
V
DQ
0–7
9
PP
Read
1, 2
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
OUT
IH
IL
IL
IH
Output Disable
V
IH
X
X
X
X
X
X
High Z
High Z
High Z
89H
IH
IH
IL
IH
Standby
V
X
X
IH
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
9
V
X
X
X
IL
IH
IH
3, 4
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IH
IH
ID
ID
IL
3, 4, 5
V
V
V
V
78H
79H
IH
Write
6, 7, 8
V
IH
V
V
IH
V
IL
X
X
X
D
IN
IL
NOTES:
1. Refer to DC Characteristics.
2. X can be V or V for control pins and addresses, V
, V
or V
for V
.
PP
IL IH
3. See DC Characteristics for V
PPL
, V , V voltages.
PPH
PPL PPH HH ID
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A –A
e
X.
1
18
e
6. Refer to Table 4 for valid D during a write operation.
5. Device ID
78H for 28F004BX-T and 79H for 28F004BX-B.
IN
7. Command writes for Block erase or byte program are only executed when V
e
V
PPH
.
PP
Ý
6. Program or erase the Boot block by holding RP at V
.
HH
9. RP must be at GND 0.2V to meet the 1.2 mA maximum deep power-down current.
Ý
g
4.3.1.2 Input Control
4.3 Read Operations
Ý
With WE at logic-high level (V ), input to the de-
vice is disabled. Data Input/Output pins (DQ 0:15
The 4-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be dis-
cussed in detail in the ‘‘Write Operations’’ section.
IH
[
]
[
]
Ý
or DQ 0:7 ) are controlled by OE .
4.3.2 INTELLIGENT IDENTIFIERS
28F400BX PRODUCTS
During power-up conditions (V supply ramping), it
CC
takes a maximum of 600 ns from when V
4.5V minimum to valid data on the outputs.
is at
CC
The manufacturer and device codes are read via the
CUI or by taking the A pin to 12V. Writing 90H to
4.3.1 READ ARRAY
9
the CUI places the device into Intelligent Identifier
read mode. A read of location 00000H outputs the
manufacturer’s identification code, 0089H, and loca-
tion 00001H outputs the device code; 4470H for
28F400BX-T, 4471H for 28F400BX-B. When
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode com-
mand to the CUI. The 4-Mbit boot block flash family
has three control functions, all of which must be
logically active, to obtain data at the outputs.
Ý
BYTE is at a logic low only the lower byte of the
above signatures is read and DQ /A is a ‘‘don’t
Ý
Chip-Enable CE is the device selection control.
b
15
1
Ý
Power-Down RP is the device power control. Out-
is the DATA INPUT/OUTPUT
care’’ during Intelligent Identifier mode. A read array
command must be written to the memory to return to
the read array mode.
Ý
put-Enable OE
[
]
[
]
(DQ 0:15 or DQ 0:7 ) direction control and when
active is used to drive data from the selected memo-
ry on to the I/O bus.
28F004BX PRODUCTS
4.3.1.1 Output Control
The manufacturer and device codes are also read
via the CUI or by taking the A pin to 12V. Writing
9
Ý
With OE at logic-high level (V ), the output from
the device is disabled and data input/output pins
IH
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location 00000H out-
puts the manufacturer’s identification code, 89H,
and location 00001H outputs the device code; 78H
for 28F004BX-T, 79H for 28F004BX-B.
[
]
[
(DQ 0:15 or DQ 0:7 are tri-stated. Data input is
then controlled by WE
]
Ý
.
18
28F400BX-T/B, 28F004BX-T/B
Ý
However, if RP is not at V
when a program or
HH
4.4 Write Operations
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for Status Regis-
ter Definitions) is set to indicate the failure to com-
plete the operation.
Commands are written to the CUI using standard mi-
croprocessor write timings. The CUI serves as the
interface between the microprocessor and the inter-
nal chip operation. The CUI can decipher Read Ar-
ray, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program com-
mands. In the event of a read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state ma-
chine that a write or erase has been requested. Dur-
ing a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. Durlng an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full com-
mand set. The CUI will stay in the current command
state until the microprocessor issues another com-
mand.
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a ‘‘1’’, which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Device Mode
Codes
The CUI will successfully initiate an erase or write
operation only when V is within its voltage range.
00
10
20
40
50
70
90
B0
D0
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
PP
Depending upon the application, the system design-
er may choose to make the V
power supply
PP
Program Setup
switchable, available only when memory updates
are desired. The system designer can also choose
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
to ‘‘hard-wire’’ V
to 12V. The 4-Mbit boot block
flash family is designed to accommodateÐeither de-
PP
Ý
sign practice. It is recommended that RP be tied to
logical Reset for data protection during unstable
CPU reset function as described in the ‘‘Product
Family Overview’’ section.
Erase Resume/Erase Confirm
Read Array
4.4.2.2 Command Function Descriptions
4.4.1 BOOT BLOCK WRITE OPERATIONS
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 4-Mbit
boot block flash family commands.
In the case of Boot Block modifications (write and
e
Ý
erase), RP is set to V
tion to V at high voltage.
12V typically, in addi-
HH
PP
19
28F400BX-T/B, 28F004BX-T/B
Table 4. Command Definitions
Bus
Notes
First Bus Cycle
Second Bus Cycle
Command
Cycles
Req’d
8
1
Operation Address Data Operation Address Data
Read Array
1
3
2
1
2
2
2
2
Write
Write
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
40H
B0H
10H
Intelligent Identifier
2, 4
3
Read
Read
IA
X
IID
Read Status Register
X
SRD
Clear Status Register
X
Erase Setup/Erase Confirm
Word/Byte Write Setup/Write
Erase Suspend/Erase Resume
5
BA
WA
X
Write
Write
Write
Write
BA
WA
X
D0H
WD
6, 7
D0H
WD
Alternate Word/Byte
Write Setup/Write
6, 7
WA
WA
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
e
2. IA
Identifier Address: 00H for manufacturer code, 01H for device code.
e
3. SRD
Data read from Status Register.
Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
e
4. IID
e
5. BA
6. WA
WD
Address within the block being erased.
Address to be written.
Data to be written at location WD.
e
e
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus DQ –DQ
to avoid burning additional current.
e
]
[
X (28F400BX-only) which is either V or V
CC SS
8
15
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recom-
mended that the customer use any command other
than the valid commands specified above. Intel re-
serves the right to redefine these codes for future
functions.
This is one of the two commands that is executable
while the state machine is operating. After this com-
mand is written, a read of the device will output the
contents of the status register, regardless of the ad-
dress presented to the device.
The device automatically enters this mode after pro-
gram or erase has completed.
Read Array (FFH)
This single write command points the read path at
Ý
Ý
the array. If the host CPU performs a CE /OE
Clear Status Register (50H)
controlled read immediately following a two-write se-
quence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchro-
nization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after pro-
gramming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A is used in this mode, all
0
other address inputs are ignored).
20
28F400BX-T/B, 28F004BX-T/B
Ý
Ý
control pins, with the exclusion of RP . RP will
immediately shut down the WSM and the remainder
of the chip. During a suspend operation, the data
and address latches will remain closed, but the ad-
dress pads are able to drive the address into the
read path.
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Pro-
gram Setup. Both commands are included to ac-
commodate efforts to achieve an industry standard
command code set.
Erase Resume (D0H)
This command will cause the CUI to clear the Sus-
pend state and set the WSM Status bit to a ‘‘0’’, but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algo-
rithm. While the WSM finishes the algorithm, the de-
vice will output Status Register contents. Note that
the WSM cannot be suspended during program-
ming.
4.4.3 STATUS REGISTER
The 4-Mbit boot block flash family contains a status
register which may be read to determine when a pro-
gram or erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing this com-
mand, all subsequent Read operations output data
from the status register until another command is
written to the CUI. A Read Array command must be
written to the CUI to return to the Read Array mode.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a ‘‘1’’, place the device into the
Read Status Register state, and wait for another
command.
[
]
The status register bits are output on DQ 0:7
whether the device is in the byte-wide (x8) or word-
wide (x16) mode for the 28F400BX. In the word-wide
Erase Confirm (D0H)
[
]
mode the upper byte, DQ 8:15 is set to 00H during
a Read Status command. In the byte-wide mode,
If the previous command was an Erase Setup com-
mand, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is exe-
cuting, the device will output Status Register data
[
]
DQ 8:14 are tri-stated and DQ /A
low order address function.
retains the
b
15
1
It should be noted that the contents of the status
Ý
register are latched on the falling edge of OE or
CE whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
Ý
when OE is toggled low. Status Register data can
only be updated by toggling either OE or CE low.
Ý
Ý
Ý
Ý
Ý
the status register. CE or OE must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
Erase Suspend (B0H)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will set
an output that directs the WSM to suspend Erase
operations, and then return to responding to only
Read Status Register or to the Erase Resume com-
mands. Once the WSM has reached the Suspend
state, it will set an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CUI will not respond to any other com-
mands. The WSM will also set the WSM Status bit to
a ‘‘1’’. The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input
The Status Register is the interface between the mi-
croprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits ‘‘Three’’ through ‘‘Seven’’ and clears bits
‘‘Six’’ and ‘‘Seven’’, but cannot clear status bits
‘‘Three’’ through ‘‘Five’’. These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.
21
28F400BX-T/B, 28F004BX-T/B
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
WSMS ESS
ES
5
PS
4
VPPS
3
R
2
R
1
R
0
7
6
NOTES:
e
e
e
SR.7
WRITE STATE MACHINE STATUS
Ready
Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase comple-
tion, before the Program or Erase Status bits are
checked for success.
1
0
e
e
e
SR.6
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to ‘‘1’’. ESS bit re-
mains set to ‘‘1’’ until an Erase Resume command is
issued.
1
0
e
e
e
SR.5
ERASE STATUS
Error in Block Erasure
Successful Block Erase
When this bit is set to ‘‘1’’. WSM has applied the maxi-
mum number of erase pulses to the block and is still
unable to successfully perform an erase verify.
1
0
e
e
e
SR.4
PROGRAM STATUS
Error In Byte/Word Program
Successful Byte/Word Program
When this bit is set to ‘‘1’’, WSM has attempted but
failed to Program a byte or word.
1
0
e
e
e
SR.3
V
PP
V
PP
V
PP
STATUS
Low Detect; Operation Abort
OK
The V Status bit unlike an A/D converter, does not
PP
1
0
provide continuous indication of V
level. The WSM
level only after the byte write or
PP
interrogates the V
PP
block erase command sequences have been entered
and informs the system if V has not been switched
PP
on. The V Status bit is not guaranteed to report ac-
PP
curate feedback between V
and V
.
PPH
PPL
e
FUTURE ENHANCEMENTS
SR.2–SR.0
RESERVED FOR
These bits are reserved for future use and should be
masked out when polling the Status Register.
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure con-
ditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in se-
quence). The status register may then be read to
determine if an error occurred during that program-
ming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI fol-
lowed by a second write which specifies the address
and data to be programmed. The write state ma-
chine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed mem-
ory word (byte), and
2. Verify that the desired bits are sufficiently pro-
grammed.
Programming of the memory results in specific bits
within a byte or word being changed to a ‘‘0’’.
If the user attempts to program ‘‘1’’s, there will be no
change of the memory cell content and no error oc-
curs.
22
28F400BX-T/B, 28F004BX-T/B
Similar to erasure, the status register indicates
whether programming is complete. While the pro-
gram sequence is executing, bit 7 of the status regis-
ter is a ‘‘0’’. The status register can be polled by
While the erase sequence is executing, Bit 7 of the
status register is a ‘‘0’’.
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a ‘‘1’’ to indicate an
Ý
Ý
toggling either CE or OE to determine when the
program sequence is complete. Only the Read
Status Register command is valid while program-
ming is active.
Erase Failure. If V was not within acceptable limits
PP
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status regis-
ter is set to a ‘‘1’’ to indicate a Program Failure. If
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bits of the status register is set to a ‘‘1’’ to indicate
an Erase Failure, and Bit 3 is set to a ‘‘1’’ to identify
that V
limits.
supply voltage was not within acceptable
PP
Bit 3 is set then V was not within acceptable limits,
PP
and the WSM will not execute the programming se-
quence.
The status register should be cleared before at-
tempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be ac-
complished until the CUI is given the appropriate
command. A Read Array command must first be giv-
en before memory contents can be read.
The status register should be cleared before at-
tempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be ac-
complished until the CUI is given the appropriate
command. A Read Array command must first be giv-
en before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
Figure 12 shows a system software flowchart for de-
vice byte programming operation. Figure 13 shows a
similar flowchart for device word programming oper-
ation (28F400BX-only).
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the mem-
ory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se-
quence at a predetermined point in the erase algo-
rithm. The status register must be read to determine
when the erase operation has been suspended.
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
[
]
CUI, along with the addresses, A 12:17 for the
[
]
28F400BX or A 12:18 for the 28F004BX, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is is-
sued. Block erasure results in all bits within the block
being set to ‘‘1’’.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block
2. Verify that all bits within the block are sufficiently
programmed
Figure 15 shows a system software flowchart detail-
ing the operation.
3. Erase all bits within the block and
4. Verify that all bits within the block are sufficiently
erased
23
28F400BX-T/B, 28F004BX-T/B
During Erase Suspend mode, the chip can go into a
4.4.6 EXTENDED CYCLING
Ý
pseudo-standby mode by taking CE to V and the
active current is now a maximum of 10 mA. If the
IH
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 4-Mbit
boot block flash family is designed for 100,000 pro-
gram/erase cycles on each of the seven blocks. The
combination of low electric fields, clean oxide pro-
cessing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.
Ý
chip is enabled while in this mode by taking CE to
, the Erase Resume command can be issued to
resume the erase operation.
V
IL
Upon completion of reads from any block other than
the block being erased, the Erase Resume com-
mand must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in or-
der to continue.
24
28F400BX-T/B, 28F004BX-T/B
Bus
Command
Comments
Operation
e
40H
Write
Write
Setup
Data
e
programmed
Program
Address
Byte to be
Program
Data to be programmed
e
programmed
Address
Byte to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update
Status Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290451–6
Full Status Check Procedure
Bus
Operation
Command
Comments
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Check SR.4
e
1
Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290451–7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
25
28F400BX-T/B, 28F004BX-T/B
Bus
Command
Comments
Operation
e
40H
Write
Write
Setup
Data
e
programmed
Program
Address
Word to be
Program
Data to be programmed
e
programmed
Address
Word to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update
Status Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
290451–8
Full Status Check Procedure
Bus
Command
Comments
Operation
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Check SR.4
e
1
Word Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290451–9
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated Word Programming Flowchart
26
28F400BX-T/B, 28F004BX-T/B
Bus
Command
Comments
Operation
e
20H
Write
Write
Setup
Erase
Data
e
Address
erased
Within block to be
e
D0H
Erase
Data
e
Address
erased
Within block to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update
Status Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
290451–10
Full Status Check Procedure
Bus
Command
Comments
Operation
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Standby
Check SR.4,5
e
Both 1
Error
Command Sequence
Check SR.5
e
1
Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290451–11
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
27
28F400BX-T/B, 28F004BX-T/B
Bus
Command
Comments
Operation
e
Write
Read
Erase
Data
B0H
Suspend
Status Register Data.
Ý
Ý
Toggle OE or CE to
update Status Register
Standby
Standby
Check SR.7
e
1
Ready
Check SR.6
e
1
Suspended
e
FFH
Write
Read Array
Data
Read
Write
Read array data from block
other than that being
erased.
e
Erase Resume Data
D0H
290451–12
Figure 15. Erase Suspend/Resume Flowchart
maximum I current is 3 mA and typical I current
CC
CC
4.5 Power Consumption
is 1 mA. The device stays in this static state with
outputs valid until a new location is read.
4.5.1 ACTIVE POWER
4.5.3 STANDBY POWER
Ý
Ý
With CE at a logic-low level and RP at a logic-
high level, the device is placed in the active mode.
Ý
With CE at a logic-high level (V ), and the CUI in
read mode, the memory is placed in standby mode
IH
The device I
CC
10 MHz with TTL input signals.
current is a maximum 60 mA at
where the maximum I
standby current is 100 mA
CC
with CMOS input signals. The standby operation dis-
ables much of the device’s circuitry and substantially
reduces device power consumption. The outputs
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low pwer fea-
ture during active mode of operation. The 4-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the de-
vice to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device’s pow-
er consumption by entering the APS mode where
[
]
[
(DQ 0:15 or DQ 0:7 ) are placed in a high-imped-
ance state independent of the status of the OE
]
Ý
signal. When the 4-Mbit boot block flash family is
deselected during erase or program functions, the
devices will continue to perform the erase or pro-
gram function and consume program or erase active
power until program or erase is completed.
28
28F400BX-T/B, 28F004BX-T/B
Ý
Ý
active. Since both WE and CE must be low for a
command write, driving either signal to V will inhibit
4.5.4 RESET/DEEP POWERDOWN
IH
The 4-Mbit boot block flash family supports a typical
of 0.2 mA in deep power-down mode. One of the
target markets for these devices is in portable equip-
ment where the power consumption of the machine
is of prime importance. The 4-Mbit boot block flash
writes to the device. The CUI architecture provides
an added level of protection since alteration of mem-
ory contents can only occur after successful com-
pletion of the two-step command sequences. Finally
I
CC
Ý
the device is disabled until RP is brought to V
,
IH
Ý
family has a RP pin which places the device in the
deep powerdown mode. When RP is at a logic-low
regardless of the state of its control inputs. This fea-
ture provides yet another level of memory protec-
tion.
Ý
g
(GND 0.2V), all circuits are turned off and the de-
vice typically draws 0.2 mA of V current.
CC
Ý
During read modes, the RP pin going low dese-
lects the memory and places the output drivers in a
high impedance state. Recovery from the deep pow-
er-down state, requires a maximum of 300 ns to ac-
4.7 Power Supply Decoupling
Flash memory’s power switching characteristics re-
quire careful device decoupling methods. System
designers are interested in 3 supply current issues:
cess valid data (t
).
PHQV
Standby current levels (I
Active current levels (I
)
#
#
#
CCS
Ý
During erase or program modes, RP low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
)
CCR
Transient peaks produced by falling and rising
Ý
edges of CE
.
Ý
corrupted by the RP function. As in the read mode
above, all internal circuitry is turned off to achieve
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 mF ceramic capacitor
the 0.2 mA current level.
Ý
RP transitions to V or turning power off to the
device will clear the status register.
IL
connected between each V
and GND, and be-
tween its V and GND. These high frequency, low-
Ý
This use of RP during system reset is important
CC
with automated write/erase devices. When the sys-
tem comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization fol-
PP
inherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1
V TRACE ON PRINTED CIRCUIT
PP
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Ý
lowing a system reset through the use of the RP
Ý
input. In this application RP is controlled by the
same RESET signal that resets the system CPU.
V
PP
designer. The V
power supply trace by the printed circuit board
pin supplies the flash memory
PP
Ý
cells current for programming and erasing. One
should use similar trace widths and layout consider-
ations given to the V
quate V
power supply trace. Ade-
supply traces and decoupling will de-
CC
4.6 Power-up Operation
PP
crease spikes and overshoots.
The 4-Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions. Upon power-
up the 4-Mbit boot block flash family is indifferent as
Ý
V , V AND RP TRANSITIONS
CC PP
4.7.2
The CUI latches commands as issued by system
to which power supply, V or V , powers-up first.
PP CC
Power supply sequencing is not required.
Ý
or CE tran-
sitions or WSM actions. Its state upon power-up, af-
software and is not altered by V
PP
ter exit from deep power-down mode or after V
transitions below V
Array mode.
The 4-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
CC
(Lockout voltage), is Read
LKO
In addition, on power-up the user must either drop
After any word/byte write or block erase operation is
complete and even after V transitions down to
Ý
CE low or present a new address to ensure valid
data at the outputs.
PP
, the CUI must be reset to Read Array mode via
V
PPL
the Read Array command when accesses to the
flash memory are desired.
A system designer must guard against spurious
when V
writes for V
voltages above V
is
PP
CC
LKO
29
28F400BX-T/B, 28F004BX-T/B
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Commercial Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
(1)
§
§
During Block Erase
and Word/Byte WriteÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
§
§
b
a
Temperature Under BiasÀÀÀÀÀÀÀ 10 C to 80 C
§
§
Extended Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C
b
a
§
§
During Block Erase
and Word/Byte Write ÀÀÀÀÀÀÀÀÀ 40 C to 85 C
b
a
§
§
b
a
Temperature Under BiasÀÀÀÀÀÀÀ 40 C to 85 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C
§
b
a
§
§
Voltage on Any Pin
(except V , V , A and RP
with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V
Ý
b
)
CC PP
9
(2)
a
Ý
Voltage on Pin RP or Pin A
with Respect to GND ÀÀÀÀÀ 2.0V to 13.5V
9
b
(2, 3)
a
V Program Voltage with Respect
PP
to GND during Block Erase
(2, 3)
(2)
b
a
and Word/Byte Write ÀÀÀÀÀ 2.0V to 14.0V
V
Supply Voltage
CC
b
a
with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V
(4)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
0
Max
70
Units
T
A
Operating Temperature
C
§
V
V
V
CC
V
CC
Supply Voltage (10%)
Supply Voltage (5%)
5
6
4.50
4.75
5.50
5.25
V
CC
CC
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
b
b
2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods
a
k
20 ns. Maximum DC voltage on input/output pins is V
for periods 20 ns.
a
0.5V which, during transitions, may overshoot to V
2.0V
CC
CC
k
3. Maximum DC voltage on V may overshoot to 14.0V for periods 20 ns. Maximum DC voltage on RP or A may
k
a
Ý
PP
k
9
overshoot to 13.5V for periods
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. 10% specifications reference the 28F400BX-60/28F004BX-60 in their standard test configuration, and the
28F400BX-80/28F004BX-80.
6. 5% V specifications reference the 28F400BX-60/28F004BX-60 in their high speed test configuration.
20 ns.
V
CC
CC
DC CHARACTERISTICS
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
e
g
I
Input Load Current
1
1.0
mA
V
V
V
Max
CC
or GND
LI
CC
e
V
IN
CC
e
g
I
Output Leakage Current
1
10
mA
V
V
V
Max
CC
or GND
CC
LO
CC
e
V
OUT
30
28F400BX-T/B, 28F004BX-T/B
DC CHARACTERISTICS (Continued)
Symbol
Parameter
Notes Min Typ
Max
Unit
mA V
Test Conditions
e
V Max
CC
I
V
Standby Current
1, 3
1.5
CCS
CC
CC
e
e
Ý
Ý
CE
RP
V
IH
e
100
mA V
V
Max
CC
e
Ý
CC
e
Ý
g
0.2V
CE
28F400BX:
RP
V
CC
e
Ý
g
BYTE
V
CC
0.2V or GND
e
Ý
mA RP
g
GND 0.2V
I
I
V
V
Deep Powerdown Current
Read Current for
1
0.20
20
1.2
55
CCD
CCR
CC
CC
e
f (Max)
e
GND
Ý
1, 5,
6, 10
mA V
V
e
Max, CE
CC
CC
e
28F400BX Word-Wide
and Byte-Wide Mode
and 28F004BX
10 MHz, f (Typ)
0 mA
5 MHz
e
CMOS Inputs
I
OUT
Byte-Wide Mode
e
e
V
Ý
20
60
mA V
V
Max, CE
CC
CC
IL
e
e
f (Max)
10 MHz, f (Typ)
0 mA
TTL Inputs
5 MHz
e
I
OUT
I
I
I
V
V
V
Word/Byte Write Current 1, 4
65
30
10
mA Word or Byte Write in Progress
mA Block Erase in Progress
mA Block Erase Suspended,
CCW
CCE
CC
CC
CC
Block Erase Current
1, 4
1, 2
Erase Suspend Current
5
CCES
e
Ý
CE
V
IH
s
V
CC
g
I
I
I
I
V
V
V
V
Standby Current
1
1
15
mA V
PPS
PPD
PPR
PPW
PP
PP
PP
PP
PP
e
Ý
g
Deep PowerDown Current
Read Current
5.0
mA RP
GND 0.2V
l
V
CC
1
200
40
mA V
PP
e
V
PPH
Word Write Current
1, 4
mA V
PP
Word Write in Progress
e
V
PPH
I
I
I
I
I
V
V
V
Byte Write Current
1, 4
1, 4
1
30
30
mA V
PPW
PPE
PP
PP
PP
PP
Byte Write in Progress
e
V
PPH
Block Erase Current
Erase Suspend Current
mA V
PP
Block Erase in Progress
e
V
PPH
200
500
mA V
PPES
PP
Block Erase Suspended
e
V
HH
Ý
RP Boot Block Unlock
Current
Ý
1, 4
mA RP
Ý
RP
ID
e
A
A
Intelligent Identifier Current 1, 4
Intelligent Identifier Voltage
500
13.0
0.8
a
mA A
V
ID
9
9
9
V
V
V
V
11.5
V
V
V
ID
b
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
IL
2.0
V
0.5
IH
OL
CC
e
e
0.45
V
V
V
5.8 mA
Min
CC
CC
I
OL
31
28F400BX-T/B, 28F004BX-T/B
DC CHARACTERISTICS (Continued)
Symbol
Parameter
Notes
Min
Typ Max Unit
Test Conditions
e
V
Output High Voltage (TTL)
2.4
V
V
V
Min
OH1
CC
CC
e b
I
2.5 mA
e
V Min
OH
V
Output High Voltage (CMOS)
0.85 V
V
V
OH2
CC
CC
CC
e b
I
2.5 mA
OH
b
e
V
V
0.4
V
Min
100 mA
CC
CC
CC
e b
I
OH
V
V
V
V
V
V
V
V
V
during Normal Operations
during Erase/Write Operations
during Erase/Write Operations
Erase/Write Lock Voltage
3
7
8
0.0
6.5
12.0 12.6
12.0 13.2
V
V
V
V
V
PPL
PPH
PPH
LKO
HH
PP
PP
PP
CC
11.4
10.8
2.0
Ý
RP Unlock Voltage
11.5
13.0
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
12.0V, T 25 C. These currents
5.0V, V
PP
§
CC
2. I
of I
is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
.
CCES
and I
CCES
CCR
e
3. Block Erases and Word/Byte Writes are inhibited when V
V
PPL
and not guaranteed in the range between V and
PPH
PP
V .
PPL
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I
to less than 1 mA typical in static operation.
CCR
g
g
6. CMOS Inputs are either V
0.2V or GND 0.2V. TTL Inputs are either V or V .
IL
CC
5% for applications requiring 100,000 block erase cycles.
10% for applications requiring wider V tolerances at 100 block erase cycles.
IH
e
e
g
g
7. V
8. V
12.0V
12.0V
PP
PP
PP
capacitance numbers.
9. For the 28F004BX address pin A follows the C
10. I
10 OUT
typical is 20 mA for X16 Active Read Current.
CCR
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
85
Unit
b
T
A
Operating Temperature
40
C
§
V
CC
V
CC
Supply Voltage (10%)
5
4.50
5.50
V
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
Parameter
Notes Min Typ Max Unit
Test Conditions
e
g
I
I
I
Input Load Current
1
1.0 mA
V
V
V
Max
CC
or GND
LI
CC
e
V
IN
CC
e
g
Output Leakage Current
1
10 mA
V
V
V
Max
CC
or GND
CC
LO
CCS
CC
e
V
OUT
e
V
V
Standby Current
1, 3
1.5 mA
V
CE
V
Max
CC
CC
CC
e
e
Ý
Ý
Ý
RP
RP
V
V
IH
e
100 mA
V
CC
CE
V
Max
CC
e
Ý
e
Ý
g
RP
0.2V
CC
28F400BX:
Ý
e
g
BYTE
V
0.2V or GND
CC
e
Ý
mA RP
g
GND 0.2V
I
Deep Power-Down Current
CC
1
0.20 20
CCD
32
28F400BX-T/B, 28F004BX-T/B
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol
Parameter
Notes Min Typ
Max
Unit
Test Conditions
e
10 MHz, I
e
GND
e
0 mA
Ý
I
V
Read Current for 28F400BX 1, 5,
60
mA V
f
V Max, CE
CC
CCR
CC
CC
e
CMOS Inputs
Word-Wide and Byte-Wide Mode 6, 10
28F004BX Byte-Wide Mode
OUT
e
10 MHz, I
e
V
e
0 mA
Ý
65
mA V
f
V
Max, CE
CC
CC
IL
e
TTL Inputs
OUT
I
I
I
V
CC
V
CC
V
CC
Word Write Current
Block Erase Current
Erase Suspend Current
1
1
70
40
10
mA Word Write in Progress
mA Block Erase in Progress
mA Block Erase Suspended,
CCW
CCE
1, 2
5
CCES
e
Ý
CE
V
IH
s
V
CC
g
I
I
I
I
V
PP
V
PP
V
PP
V
PP
Standby Current
1
1
1
1
15
mA V
PPS
PPD
PPR
PPW
PP
e
Ý
g
Deep Power-Down Current
Read Current
5.0
mA RP
GND 0.2V
l
V
CC
200
40
mA V
PP
e
V
PPH
Word Write Current
mA V
PP
Word Write in Progress
e
V
PPH
I
I
I
I
I
V
V
V
Byte Write Current
1
1
30
30
mA V
PPW
PPE
PP
PP
PP
PP
Byte Write in Progress
e
V
PPH
Block Erase Current
Erase Suspend Current
mA V
PP
Block Erase in Progress
e
V
PPH
1
200
500
mA V
PPES
PP
Block Erase Suspended
e
V
HH
Ý
RP Boot Block Unlock
Current
Ý
1, 4
1
mA RP
Ý
RP
e
A
A
Intelligent Identifier Current
Intelligent Identifier Current
500
13.0
0.8
a
mA A
V
ID
ID
9
9
9
V
V
V
V
11.5
V
V
V
ID
b
0.5
2.0
Input Low Voltage
Input High Voltage
Output Low Voltage
IL
V
0.5
IH
OL
CC
e
e
0.45
V
V
V
Min
CC
CC
5.8 mA
I
OL
e
e b
V
Output High Voltage (TTL)
2.4
V
V
V
Min
CC
2.5 mA
OH1
CC
I
OH
33
28F400BX-T/B, 28F004BX-T/B
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol
Parameter
Notes
Min
Typ Max Unit
Test Conditions
e
V
Output High Voltage (CMOS)
0.85 V
V
V
V
Min
2.5 mA
OH2
CC
CC
CC
e b
I
OH
b
e
V
V
0.4
V
Min
100 mA
CC
CC
CC
e b
I
OH
V
V
V
V
V
V
V
V
V
during Normal Operations
during Erase/Write Operations
during Erase/Write Operations
Erase/Write Lock Voltage
3
7
8
0.0
6.5
12.0 12.6
12.0 13.2
V
V
V
V
V
PPL
PPH
PPH
LKO
HH
PP
PP
PP
CC
11.4
10.8
2.0
Ý
RP Unlock Voltage
11.5
13.0
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
12.0V, T 25 C. These currents
5.0V, V
PP
§
CC
2. I
of I
is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
.
CCES
and I
CCES
CCR
e
3. Block Erases and Word/Byte Writes are inhibited when V
V
PPL
and not guaranteed in the range between V
and
PP
PPH
V .
PPL
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces I
to less than 1 mA typical in static operation.
CCR
g
g
6. CMOS Inputs are either V
0.2V or GND 0.2V. TTL Inputs are either V or V .
IL
CC
5% for applications requiring 100,000 block erase cycles.
10% for applications requiring wider V tolerances at 100 block erase cycles.
IH
e
e
g
g
7. V
8. V
12.0V
12.0V
PP
PP
PP
capacitance numbers.
9. For the 28F004BX address pin A follows the C
10. I
10 OUT
typical is 20 mA for X16 Active Read Current.
CCR
(1)
e
e
1 MHz
CAPACITANCE
T
A
25 C, f
§
Symbol
Parameter
Input Capacitance
Output Capacitance
Typ
6
Max
8
Unit
pF
Conditions
e
C
C
V
V
0V
IN
IN
e
0V
10
12
pF
OUT
OUT
NOTE:
1. Sampled, not 100% tested.
34
28F400BX-T/B, 28F004BX-T/B
(1)
STANDARD TEST CONFIGURATION
STANDARD
AC INPUT/OUTPUT REFERENCE WAVEFORM
STANDARD
AC TESTING LOAD CIRCUIT
290451–14
Logic ‘‘1’’ and
) for a logic ‘‘0’’. Input timing begins at V (2.0 V ) and V
AC test inputs are driven at
(0.45 V
(0.8 V
to 90%)
V
(2.4
V
)
for
a
V
OL
OH
TTL
TTL IH TTL IL
). Output timing ends at V and V . Input rise and fall times (10%
TTL IH IL
k
10 ns.
290451–13
e
C
L
C
L
100 pF
Includes Jig Capacitance
e
R
L
3.3 KX
(2)
HIGH SPEED TEST CONFIGURATION
HIGH SPEED
AC INPUT/OUTPUT REFERENCE WAVEFORM
HIGH SPEED
AC TESTING LOAD CIRCUIT
290451–22
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a logic ‘‘0’’.
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
k
(10% to 90%)
10 ns.
290451–21
e
C
L
C
L
30 pF
Includes Jig Capacitance
e
R
L
3.3 KX
NOTES:
1. Testing characteristics for 28F400BX-60/28F004BX-60 in standard test configuration and 28F400BX-80/28F004BX-80.
2. Testing characteristics for 28F400BX-60/28F004BX-60 in high speed test configuration.
35
28F400BX-T/B, 28F004BX-T/B
(1)
AC CHARACTERISTICSÐRead Only Operations
(4)
28F400BX-60
g
V
CC
5%
(4)
28F004BX-60
Versions
Symbol
(5)
(5)
(5)
(5)
(5)
(5)
Unit
28F400BX-60
28F400BX-80
28F400BX-120
g
V
10%
CC
28F004BX-60
28F004BX-80
28F004BX-120
Parameter
Notes Min
Max
Min
Max
Min
Max
Min
Max
t
t
t
AVAV RC
Read Cycle Time
60
70
80
120
ns
ns
t
AVQV ACC
Address to
60
70
80
120
Output Delay
Ý
CE to Output Delay
t
t
t
ELQV CE
2
60
70
80
120
300
ns
ns
Ý
RP High to
t
PHQV PWH
300
300
300
Output Delay
Ý
OE to Output Delay
t
t
t
t
GLQV OE
2
3
3
30
20
35
25
40
30
40
30
ns
ns
ns
Ý
CE to Output Low Z
t
ELQX LZ
0
0
0
0
0
0
0
0
0
0
0
0
Ý
CE High to Output
t
EHQZ HZ
High Z
Ý
OE to Output Low Z
t
t
t
GLQX OLZ
3
3
ns
ns
Ý
OE High to Output
t
GHQZ DF
20
25
30
30
High Z
t
Output Hold from
Addresses,
3
ns
OH
Ý Ý
CE or OE Change,
Whichever is First
t
t
Input Rise Time
Input Fall Time
10
10
5
10
10
5
10
10
5
10
10
5
ns
ns
ns
IR
IF
Ý
CE to BYTE
Ý
t
t
3
3, 6
3
ELFL
ELFH
Switching
Low or High
Ý
BYTE Switching
t
t
60
20
70
25
80
30
120
30
ns
ns
FHQV
FLQZ
High to Valid
Output Delay
Ý
BYTE Switching
Low to
Output High Z
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
Ý
2. OE may be delayed up to t –t
3. Sampled, not 100% tested.
Ý
after the falling edge of CE without impact on t
.
CE
CE OE
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
Ý
6. t , BYTE switching low to valid output delay, will be equal to t
FLQV
valid.
, measured from the time DQ /A becomes
AVQV 15 -1
36
28F400BX-T/B, 28F004BX-T/B
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICSÐRead Only Operations
(1)
(4)
T28F400BX-80
Versions
T28F004BX-80
Max
Unit
Symbol
Parameter
Notes
Min
t
t
t
t
Read Cycle Time
80
ns
ns
AVAV
AVQV
RC
Address to
80
ACC
Output Delay
Ý
CE to Output Delay
t
t
t
t
80
ns
ns
ELQV
PHQV
CE
Ý
RP High to
300
PWH
Output Delay
Ý
OE to Output Delay
t
t
t
t
t
t
2
40
30
ns
ns
ns
GLQV
ELQX
EHQZ
OE
Ý
CE to Output Low Z
0
0
0
LZ
Ý
CE High to Output
HZ
High Z
Ý
OE to Output Low Z
t
t
t
t
3
3
ns
ns
GLQX
OLZ
Ý
OE High to Output
30
GHQZ
DF
High Z
t
Output Hold from
Addresses,
3
ns
OH
Ý Ý
CE or OE Change,
Whichever is First
t
t
Input Rise Time
Input Fall Time
10
10
5
ns
ns
ns
IR
IF
Ý
CE to BYTE
Ý
t
t
3
3, 5
3
ELFL
ELFH
Switching
Low or High
Ý
BYTE Switching
t
t
80
30
ns
ns
FHQV
FLQZ
High to Valid
Output Delay
Ý
BYTE Switching
Low to
Output High Z
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
Ý
2. OE may be delayed up to t –t
3. Sampled, not 100% tested.
Ý
after the falling edge of CE without impact on t
.
CE
CE OE
4. See Standard Test Configuration.
Ý
5. t
, BYTE switching low to valid output delay, will be equal to t
FLQV
from the time DQ /A
15
becomes valid.
b
1
AVQV
37
28F400BX-T/B, 28F004BX-T/B
Figure 16. A.C. Waveforms for Read Operations
38
28F400BX-T/B, 28F004BX-T/B
290451–26
290451–27
Figure 17. I (RMS) vs Frequency
e
Figure 18. I (RMS) vs Frequency
CC
CC
5.5V for x16 Operation
e
5.5V) for x8 Operation
(V
(V
CC
CC
290451–28
Figure 19. T
vs Output Load Capacitance
ACC
39
28F400BX-T/B, 28F004BX-T/B
Ý
Figure 20. BYTE Timing Diagram for Both Read and Write Operations for 28F400BX
40
28F400BX-T/B, 28F004BX-T/B
(1)
Ý
AC CHARACTERISTICSÐWE Controlled Write Operations
(9)
28F400BX-60
g
V
5%
CC
(9)
28F004BX-60
Versions
(10)
(10)
(10)
(10)
(10)
(10)
Unit
28F400BX-60
28F400BX-80
28F400BX-120
g
V
CC
10%
28F004BX-60
28F004BX-80
28F004BX-120
Symbol
Parameter
Notes Min
Max
Min
70
Max
Min
80
Max
Min
120
215
Max
t
t
t
t
Write Cycle Time
60
ns
ns
AVAV
WC
Ý
RP High
215
215
215
PHWL
PS
Recovery to
Ý
WE Going Low
Ý
CE Setup to WE
Ý
t
t
t
t
t
t
0
0
0
0
ns
ns
ns
ns
ns
ELWL
CS
Going Low
Ý
t
PHHWH PHS
RP
V
HH
Setup to
6, 8
5, 8
3
100
100
50
100
100
50
100
100
50
100
100
50
Ý
WE Going High
Ý
Setup to WE
t
t
t
V
VPWH
AVWH
DVWH
VPS
AS
PP
Going High
Address Setup to
Ý
WE Going High
Ý
Data Setup to WE
Going High
4
50
50
50
50
DS
Ý
WE Pulse Width
t
t
t
WLWH WP
50
0
50
0
60
0
60
0
ns
ns
t
t
t
Data Hold from
4
3
WHDX
WHAX
WHEH
DH
AH
CH
Ý
WE High
t
t
t
t
Address Hold from
10
10
10
6
10
10
20
6
10
10
20
6
10
10
20
6
ns
ns
ns
ms
Ý
WE High
Ý
CE Hold from
Ý
WE High
Ý
WE Pulse
t
WHWL WPH
WHQV1
Width High
Duration of
Word/Byte
Programming
Operation
2, 5
t
t
Duration of Erase
Operation (Boot)
2, 5, 6
2, 5
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
s
s
WHQV2
Duration of Erase
Operation
WHQV3
(Parameter)
t
t
Duration of Erase
Operation (Main)
2, 5
5, 8
0.6
0
0.6
0
0.6
0
0.6
0
s
WHQV4
t
V
Hold from
ns
QVVL
VPH
PP
Valid SRD
41
28F400BX-T/B, 28F004BX-T/B
(1)
AC CHARACTERISTICSÐWE Controlled Write Operations (Continued)
Ý
(9)
28F400BX-60
g
V
CC
5%
(9)
28F004BX-60
Versions
(10)
(10)
(10)
(10)
(10)
(10)
Unit
28F400BX-60
28F400BX-80
28F400BX-120
g
V
CC
10%
28F004BX-60
28F004BX-80
28F004BX-120
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Ý
t
t
t
QVPH PHH
RP
V
Hold 6, 8
0
0
0
0
ns
ns
HH
from Valid SRD
Boot-Block
7, 8
100
100
100
100
PHBR
Relock Delay
t
t
Input Rise Time
Input Fall Time
10
10
10
10
10
10
10
10
ns
ns
IR
IF
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter-
nally which includes verify and margining operations.
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
.
IN
.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7
IN
e
1).
until operation completes successfully.
Ý
6. For Boot Block Program/Erase, RP should be held at V
HH
is required for successful relocking of the Boot Block.
7. Time t
PHBR
8. Sampled but not 100% tested.
9. See High Speed Test Configuration.
10. See Standard Test Configuration.
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE
e
g
12.0V 5%
V
PP
28F400BX-60
28F004BX-60
28F400BX-80
28F004BX-80
28F400BX-120
28F004BX-120
Parameter
Notes
Unit
(1)
(1)
(1)
Min Typ
Max Min Typ
Max Min Typ
Max
Boot/Parameter
Block Erase Time
2
2
2
2
1.0
2.4
1.2
0.6
7
1.0
2.4
1.2
0.6
7
1.0
2.4
1.2
0.6
7
s
s
s
s
Main Block
Erase Time
14
4.2
2.1
14
4.2
2.1
14
4.2
2.1
Main Block Byte
Program Time
Main Block Word
Program Time
NOTES:
1. 25 C
2. Excludes System-Level Overhead.
§
42
28F400BX-T/B, 28F004BX-T/B
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE
e
g
12.0V 10%
V
PP
28F400BX-60
28F004BX-60
28F400BX-80
28F004BX-80
28F400BX-120
28F004BX-120
(1)
Max
Parameter
Notes
Unit
(1)
(1)
Min Typ
Max Min Typ
Max Min Typ
Boot/Parameter
Block Erase Time
2
2
2
2
5.8
14
40
60
20
10
5.8
14
40
60
20
10
5.8
40
60
20
10
s
s
s
s
Main Block
Erase Time
14
Main Block Byte
Program Time
6.0
3.0
6.0
3.0
6.0
3.0
Main Block Word
Program Time
NOTES:
1. 25 C
2. Excludes System-Level Overhead.
§
EXTENDED TEMPERATURE OPERATION
Ý
AC CHARACTERISTICSÐWE Controlled Write Operations
(1)
(9)
(9)
T28F400BX-80
T28F004BX-80
(4)
Versions
Unit
Symbol
Parameter
Write Cycle Time
Notes
Min
80
Max
t
t
t
ns
ns
AVAV
PHWL
WC
Ý
t
RP High Recovery to
220
PS
Ý
WE Going Low
Ý
Ý
CE Setup to WE Going Low
t
t
t
t
0
ns
ns
ELWL
CS
Ý
Going High
Ý
RP
V
Setup to WE
HH
6, 8
100
PHHWH
PHS
Ý
V Setup to WE Going High
t
t
t
t
5, 8
3
100
60
ns
ns
VPWH
AVWH
VPS
PP
Ý
Address Setup to WE
Going High
AS
Ý
Data Setup to WE Going High
t
t
t
t
t
t
t
t
t
t
t
t
t
4
60
60
0
ns
ns
ns
ns
ns
ns
ms
DVWH
WLWH
WHDX
WHAX
WHEH
WHWL
WHQV1
DS
Ý
WE Pulse Width
WP
DH
AH
Ý
Data Hold from WE High
4
3
Ý
Address Hold from WE High
10
10
20
7
Ý
Ý
CE Hold from WE High
CH
Ý
WE Pulse Width High
WPH
Duration of Word/Byte
Programming Operation
2, 5
t
Duration of Erase Operation (Boot)
2, 5, 6
0.4
s
WHQV2
43
28F400BX-T/B, 28F004BX-T/B
EXTENDED TEMPERATURE OPERATION
(1)
AC CHARACTERISTICSÐWE Controlled Write Operations (Continued)
Ý
(9)
T28F400BX-80
(4)
Versions
(9)
T28F004BX-80
Unit
Symbol
Parameter
Notes
Min
Max
t
Duration of Erase Operation
(Parameter)
2, 5
0.4
s
WHQV3
t
t
t
t
Duration of Erase Operation (Main)
2, 5
5, 8
6, 8
7, 8
0.7
0
s
WHQV4
QVVL
t
t
V
PP
Hold from Valid SRD
ns
ns
ns
ns
ns
VPH
Ý
RP
V
HH
Hold from Valid SRD
0
QVPH
PHBR
PHH
Boot-Block Relock Delay
Input Rise Time
100
10
t
t
IR
Input Fall Time
10
IF
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter-
nally which includes verify and margining operations.
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
.
IN
.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7
IN
e
1).
until operation completes successfully.
Ý
6. For Boot Block Program/Erase, RP should be held at V
HH
is required for successful relocking of the Boot Block.
7. Time t
PHBR
8. Sampled but not 100% tested.
9. See Standard Test Configuration.
EXTENDED TEMPERATURE OPERATION
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE
e
g
12.0V 5%
V
PP
T28F400BX-80
T28F004BX-80
Parameter
Notes
Unit
(1)
Min
Typ
Max
Boot/Parameter
Block Erase Time
2
2
2
2
1.5
3.0
1.4
0.7
10.5
s
s
s
s
Main Block
Erase Time
18
5.0
2.5
Main Block Byte
Program Time
Main Block Word
Program Time
NOTES:
1. 25 C
2. Excludes System-Level Overhead.
§
44
28F400BX-T/B, 28F004BX-T/B
Ý
Figure 21. AC Waveforms for a Write and Erase Operations (WE -Controlled Writes)
45
28F400BX-T/B, 28F004BX-T/B
(1, 9)
Ý
AC CHARACTERISTICSÐCE -CONTROLLED WRITE OPERATIONS
(10)
28F400BX-60
g
V
5%
CC
(10)
28F004BX-60
Versions
(11)
(11)
(11)
(11)
(11)
(11)
Unit
28F400BX-60
28F400BX-80
28F400BX-120
g
V
10%
CC
28F004BX-60
28F004BX-80
28F004BX-120
Symbol
Parameter
Notes
Min
60
Max
Min
70
Max
Min
80
Max
Min
120
215
Max
t
t
t
t
Write Cycle Time
ns
ns
AVAV
WC
Ý
RP High
215
215
215
PHEL
PS
Recovery
Ý
to CE Going Low
Ý
t
t
t
t
t
t
WE Setup to
0
0
0
0
ns
ns
ns
ns
ns
WLEL
WS
Ý
CE Going Low
Ý
t
PHHEH PHS
RP
V
HH
Setup to 6, 8
100
100
50
100
100
50
100
100
50
100
100
50
Ý
CE Going High
Ý
t
t
t
V
Setup to CE
VPS PP
Going High
5, 8
3
VPEH
AVEH
DVEH
Address Setup to
AS
Ý
CE Going High
Data Setup to
Ý
CE Going High
4
50
50
50
50
DS
Ý
CE Pulse Width
t
t
t
t
50
0
50
0
60
0
60
0
ns
ns
ELEH
CP
Data Hold from
4
3
EHDX
DH
Ý
CE High
t
t
t
t
t
AH
Address Hold
10
10
10
6
10
10
20
6
10
10
20
6
10
10
20
6
ns
ns
ns
ms
EHAX
Ý
from CE High
Ý
WE Hold from
t
EHWH WH
Ý
CE High
Ý
CE Pulse
t
EHEL
CPH
Width High
Duration of Word/ 2, 5
Byte Programming
Operation
EHQV1
t
t
Duration of Erase 2, 5, 6
Operation (Boot)
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
s
s
EHQV2
Duration of Erase
Operation
2, 5
EHQV3
(Parameter)
t
t
t
t
Duration of Erase
Operation (Main)
2, 5
5, 8
6, 8
7
0.6
0
0.6
0
0.6
0
0.6
0
s
EHQV4
QVVL
QVPH
PHBR
t
t
V
Hold from
ns
ns
ns
VPH PP
Valid SRD
Ý
RP
V
HH
Hold
0
0
0
0
PHH
from Valid SRD
Boot-Block
100
100
100
100
Relock Delay
46
28F400BX-T/B, 28F004BX-T/B
(1, 9)
Ý
AC CHARACTERISTICSÐCE -CONTROLLED WRITE OPERATIONS
(Continued)
(10)
28F400BX-60
g
V
CC
5%
(10)
28F004BX-60
Versions
(11)
(11)
(11)
(11)
(11)
Unit
28F400BX-60
28F400BX-80
28F400BX-120
g
V
CC
10%
(11)
28F004BX-60
28F004BX-80
28F004BX-120
Symbol
Parameter
Input Rise Time
Input Fall Time
Notes
Min
Max
10
10
Min
Max
10
10
Min
Max
10
10
Min
Max
10
10
t
t
ns
ns
IR
IF
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE in systems where
Ý
Ý
CE defines the write pulse-width (within a longer WE timing waveform), all set-up, hold and inactive WE times
Ý
should be measured relative to the CE waveform.
Ý
Ý
Ý
Ý
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics notes for WE -Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See High Speed Test Configuration.
11. See Standard Test Configuration.
EXTENDED TEMPERATURE OPERATION
(1, 9)
Ý
AC CHARACTERISTICSÐCE -CONTROLLED WRITE OPERATIONS
(10)
(10)
T28F400BX-80
T28F004BX-80
Versions
Unit
Symbol
Parameter
Write Cycle Time
Notes
Min
80
220
0
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
AVAV
PHEL
WLEL
PHHEH
VPEH
AVEH
DVEH
ELEH
EHDX
EHAX
EHWH
EHEL
EHQV1
WC
Ý
Ý
RP High Recovery to CE Going Low
PS
Ý
Ý
WE Setup to CE Going Low
WS
PHS
VPS
AS
Ý
Ý
Setup to CE Going High
RP
V
HH
6, 8
5, 8
3
100
100
60
60
60
0
Ý
Setup to CE Going High
V
PP
Ý
Address Setup to CE Going High
Ý
Data Setup to CE Going High
4
DS
Ý
CE Pulse Width
CP
Ý
Data Hold from CE High
4
3
DH
Ý
Address Hold from CE High
10
10
20
7
AH
Ý
Ý
WE Hold from CE High
WH
CPH
Ý
CE Pulse Width High
Duration of Word/Byte Programming
Operation
2, 5
47
28F400BX-T/B, 28F004BX-T/B
Ý
Figure 22. Alternate A.C. Waveforms for Write and Erase Operations (CE -Controlled Writes)
48
28F400BX-T/B, 28F004BX-T/B
EXTENDED TEMPERATURE OPERATION
Ý
AC CHARACTERISTICSÐCE -CONTROLLED WRITE OPERATIONS
(1, 9)
(Continued)
(10)
(10)
T28F400BX-80
T28F004BX-80
Versions
Unit
Symbol
Parameter
Notes
2, 5, 6
2, 5
Min
0.4
0.4
0.7
0
Max
t
t
t
t
t
t
Duration of Erase Operation (Boot)
Duration of Erase Operation (Parameter)
Duration of Erase Operation (Main)
s
EHQV2
s
EHQV3
EHQV4
QVVL
2, 5
s
t
t
V
Hold from Valid SRD
PP
5, 8
ns
ns
ns
ns
ns
VPH
PHH
Ý
RP
V
Hold from Valid SRD
HH
6, 8
0
QVPH
PHBR
Boot-Block Relock Delay
Input Rise Time
7
100
10
t
t
IR
IF
Input Fall Time
10
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE in systems where
Ý
Ý
CE defines the write pulse-width (within a longer WE timing waveform), all set-up, hold and inactive WE times
Ý
should be measured relative to the CE waveform.
Ý
Ý
Ý
Ý
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics for WE -Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.
ORDERING INFORMATION
290451–18
VALID COMBINATIONS:
E28F400BX-T60
E28F400BX-B60
E28F400BX-T80
E28F400BX-B80
E28F400BX-T120
E28F400BX-B120
PA28F400BX-T60
PA28F400BX-B60
PA28F400BX-T80
PA28F400BX-B80
PA28F400BX-T120
PA28F400BX-B120
TE28F400BX-T80
TE28F400BX-B80
TB28F400BX-T80
TB28F400BX-B80
290451–30
VALID COMBINATIONS:
E28F004BX-T60
E28F004BX-B60
E28F004BX-T80
E28F004BX-B80
TE28F004BX-T80
TE28F004BX-B80
E28F004BX-T120
E28F004BX-B120
49
28F400BX-T/B, 28F004BX-T/B
ADDITIONAL INFORMATION
References
Order Number
Document
290448
290449
290450
290531
290530
290539
292098
292148
28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet
28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet
28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
AP-363 ‘‘Extended Flash BIOS Concepts for Portable Computers’’
AP-604 ‘‘Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace
EEPROM’’
292178
292130
292154
AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’
AB-57 ‘‘Boot Block Architecture for Safe Firmware Updates’’
AB-60 ‘‘2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family’’
Revision History
Number
Description
-001
-002
Original Version
Removed -70 speed bin.
Integrated -70 characteristics into -60 speed bin.
Added Extended Temperature characteristics.
Ý
Modified BYTE Timing Diagram.
Ý
PWD renamed to RP for JEDEC standardization compatibility.
-003
Combined V Read current for 28F400BX Word-Wide Mode and Byte-Wide Mode and
CC
28F004BX Byte-Wide Mode in DC Characteristics tables.
Added Boot Black Unlock Current specifications in DC Characteristics tables.
in DC Characteristics: Extended Temperature Operation table.
CCW
Improved I
Improved t
and I
CCR
, t
, t
, t
, t
, t
, t
and t
specifications for
FLQZ
Extended Temperature Operations AC CharacteristicsÐRead and Write Operations.
AVAV AVQV ELQV GLQV EHQZ GHQZ FHQV
-004
Added specifications for 120 ns access time product version; 28F400BX-120 and
28F004BX-120.
Included permanent change on write timing parameters for -80 ns product versions. Write
pulse width (t
t
and t ) increases from 50 ns to 60 ns. Write pulse width high (t
CP
) decreases from 30 ns to 20 ns. Total write cycle time (t ) remains unchanged.
WC
and
WP
WPH
CPH
Added I
Added I
test condition note for typical frequency value in DC Characteristics table.
CMOS specification.
CCR
OH
Added 28F400BX interface to Intel386TMEX Embedded Processor block diagram.
Added description of how to design for upgrading to SmartVoltage Boot Block products.
-005
Added references to input rise/fall times.
50
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