EP2A25F672I8 [INTEL]
Loadable PLD, 1.94ns, CMOS, PBGA672, 27 X 27 MM, 1 MM PITCH, FINE LINE, BGA-672;
| 型号： | EP2A25F672I8 |
| 厂家： | 
INTEL |
| 描述： | Loadable PLD, 1.94ns, CMOS, PBGA672, 27 X 27 MM, 1 MM PITCH, FINE LINE, BGA-672 栅 可编程逻辑 |
| 文件： | 总68页 (文件大小：481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6. Configuring APEX II
Devices
CF51004-2.1
TM
APEX II devices can be configured using one of four configuration
schemes. All configuration schemes use either a microprocessor or
configuration device.
Introduction
APEX II devices can be configured using the passive serial (PS), fast
passive parallel (FPP), passive parallel asynchronous (PPA), and Joint
Test Action Group (JTAG) configuration schemes. The configuration
scheme used is selected by driving the APEX II device MSEL1and MSEL0
pins either high or low as shown in Table 6–1. If your application only
requires a single configuration mode, the MSELpins can be connected to
VCC (VCCIO of the I/O bank where the MSELpin resides) or to ground. If
your application requires more than one configuration mode, you can
switch the MSELpins after the FPGA is configured successfully. Toggling
these pins during user-mode does not affect the device operation;
however, the MSELpins must be valid before a reconfiguration is
initiated.
Table 6–1. APEX II Configuration Schemes
MSEL1
MSEL0
Configuration Scheme
0
1
0
0
PS
FPP
1
1
PPA
(1)
(1)
JTAG Based (2)
Notes to Table 6–1:
(1) Do not leave the MSELpins floating; connect them to a low- or high-logic level.
These pins support the non-JTAG configuration scheme used in production. If
only JTAG configuration is used, you should connect the MSELpins to ground.
(2) JTAG-based configuration takes precedence over other configuration schemes,
which means MSELpin settings are ignored.
Altera Corporation
August 2005
6–1
Passive Serial Configuration
Table 6–2 shows the approximate configuration file sizes for APEX II
devices.
Table 6–2. APEX II Raw Binary File (.rbf) Sizes
Device
Data Size (Bits)
Data Size (Bytes)
EP2A15
EP2A25
EP2A40
EP2A70
4,358,512
6,275,200
9,640,528
17,417,088
544,814
784,400
1,208,320
2,177,136
Use the data in Table 6–2 only to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
®
®
However, for any specific version of the Quartus II or MAX+PLUS II
software, all designs targeted for the same device will have the same
configuration file size.
The following chapter describes in detail how to configure APEX II
devices using the supported configuration schemes. The last section
describes the device configuration pins available. In this chapter, the
generic term device(s) or FPGA(s) will include all APEX II devices.
f
For more information on setting device configuration options or creating
configuration files, refer to Software Settings, chapter 6 and 7 n volume 2
of the Configuration Handbook.
You can perform APEX II PS configuration using an Altera configuration
device, an intelligent host (e.g., a microprocessor or Altera MAX
device), or a download cable.
Passive Serial
Configuration
®
®
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, EPC2, or EPC1 device, to configure APEX II devices
using a serial configuration bitstream. Configuration data is stored in the
configuration device. Figure 6–1 shows the configuration interface
connections between the APEX II device and a configuration device.
1
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
6–2
Altera Corporation
August 2005
Configuration Handbook, Volume 1
Configuring APEX II Devices
f
For more information on the enhanced configuration device and flash
interface pins (e.g., PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), refer to the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet in the Configuration Handbook.
Figure 6–1. Single Device PS Configuration Using an Enhanced Configuration
Device
VCC (1)
VCC (1)
Enhanced
Configuration
Device
1 kΩ
(3)
1 kΩ
(3)
APEX II Device
DCLK
DATA
DCLK
DATA0
nSTATUS
(3)
OE
(3)
nCS
CONF_DONE
nCONFIG
nINIT_CONF (2)
nCEO
nCE
N.C.
MSEL0
MSEL1
GND
GND
Notes to Figure 6–1:
(1) The pull-up resistor should be connected to the same supply voltage as the
configuration device.
(2) The nINIT_CONFpin (available on enhanced configuration devices and EPC2
devices only) has an internal pull-up resistor that is always active, meaning an
external pull-up resistor is not required on the nINIT_CONF/nCONFIGline. The
nINIT_CONFpin does not need to be connected if its functionality is not used. If
nINIT_CONFis not used or not available (e.g., on EPC1 devices), nCONFIGmust
be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ and EPC2 devices’ OEand nCSpins have
internal programmable pull-up resistors. If internal pull-up resistors are used,
external pull-up resistors should not be used on these pins. The internal pull-up
resistors are used by default in the Quartus II software. To turn off the internal pull-
up resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
f
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Operating Conditions
table of the Enhanced Configuration Devices (EPC4, EPC8, & EPC16)
Data Sheet or the Configuration Devices for SRAM-based LUT Devices
Data Sheet.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONFJTAG instruction to initiate FPGA configuration. The
nINIT_CONFpin does not need to be connected if its functionality is not
used. If nINIT_CONFis not used or not available (e.g., on EPC1 devices),
nCONFIGmust be pulled to VCC either directly or through a resistor. An
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August 2005
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Passive Serial Configuration
internal pull-up on the nINIT_CONFpin is always active in enhanced
configuration devices and EPC2 devices, which means an external pull-
up resistor is not required if nCONFIGis tied to nINIT_CONF.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 μs. During POR, the device resets and holds
nSTATUSlow, and tri-states all user I/O pins. The configuration device
also goes through a POR delay to allow the power supply to stabilize. The
POR time for EPC2, EPC1, and EPC1441 devices is 200 ms (maximum),
and for enhanced configuration devices, the POR time can be set to either
100 ms or 2 ms, depending on its PORSELpin setting. If the PORSELpin
is connected to GND, the POR delay is 100 ms. During this time, the
configuration device drives its OEpin low. This low signal delays
configuration because the OEpin is connected to the target device’s
nSTATUSpin. When both devices complete POR, they release their open-
drain OEor nSTATUSpin, which is then pulled high by a pull-up resistor.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
APEX II devices have weak pull-up resistors on the user I/O pins which
are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the APEX II Programmable Logic Device Family Data Sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIGor
nSTATUSare low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIGor nSTATUSpin low.
1
VCCINTand VCCIOpins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels to begin the configuration process.
When nCONFIGgoes high, the device comes out of reset and releases the
nSTATUSpin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up on the
OEpin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal pull-
up resistor is not used, an external 1-kΩpull-up resistor on the
OE/nSTATUSline is required. Once nSTATUSis released, the FPGA is
ready to receive configuration data and the configuration stage begins.
6–4
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Configuration Handbook, Volume 1
August 2005
Configuring APEX II Devices
When nSTATUSis pulled high, OEof the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The APEX II device receives configuration
data on its DATA0pin and the clock is received on the DCLKpin. Data is
latched into the FPGA on the rising edge of DCLK.
After the FPGA has received all configuration data successfully, it releases
the open-drain CONF_DONEpin, which is pulled high by a pull-up
resistor. Since CONF_DONEis tied to the configuration device’s nCSpin,
the configuration device is disabled when CONF_DONEgoes high.
Enhanced configuration and EPC2 devices have an optional internal pull-
up resistor on the nCSpin. This option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If this internal pull-up is not used, an external 1-kΩpull-up resistor on the
nCS/CONF_DONEline is required. A low-to-high transition on
CONF_DONEindicates configuration is complete and initialization of the
device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSRpin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will supply itself with
enough clock cycles for proper initialization. You also have the flexibility
to synchronize initialization of multiple devices by using the CLKUSR
option. You can turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General tab of the Device &
Pin Options dialog box. Supplying a clock on CLKUSRwill not affect the
configuration process. After all configuration data is accepted and
CONF_DONEgoes high, APEX II devices require 40 clock cycles to
properly initialize.
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August 2005
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Passive Serial Configuration
An optional INIT_DONEpin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONEpin is used, it will be high due to an external 1-kΩpull-
up resistor when nCONFIGis low and during the beginning of
configuration. Once the option bit to enable INIT_DONEis programmed
into the device (during the first frame of configuration data), the
INIT_DONEpin goes low. When initialization is complete, the
INIT_DONEpin is released and pulled high. This low-to-high transition
signals that the FPGA has entered user mode. In user-mode, the user I/O
pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device drives DCLK
low and DATAhigh at the end of configuration.
If an error occurs during configuration, the FPGA drives its nSTATUSpin
low, resetting itself internally. Since the nSTATUSpin is tied to OE, the
configuration device will also be reset. If the Auto-Restart Configuration
After Error option available in the Quartus II software from the General
tab of the Device & Pin Options dialog box is turned on, the FPGA
automatically initiates reconfiguration if an error occurs. The APEX II
device will release its nSTATUSpin after a reset time-out period
(maximum of 40 µs). When the nSTATUSpin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
this option is turned off, the external system must monitor nSTATUSfor
errors and then pulse nCONFIGlow for at least 8 µs to restart
configuration. The external system can pulse nCONFIGif nCONFIGis
under system control rather than tied to VCC
.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONEhas not gone high, it recognizes that the FPGA
has not configured successfully. Enhanced configuration devices wait for
64 DCLKcycles after the last configuration bit was sent for CONF_DONEto
reach a high state. EPC2 devices wait for 16 DCLKcycles. In this case, the
configuration device pulls its OEpin low, which in turn drives the target
device’s nSTATUSpin low. If the Auto-Restart Configuration After Error
option is set in the software, the target device resets and then releases its
nSTATUSpin after a reset time-out period (maximum of 40 µs). When
nSTATUSreturns high, the configuration device tries to reconfigure the
FPGA.
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August 2005
Configuring APEX II Devices
When CONF_DONEis sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully;
therefore, your system should not pull CONF_DONElow to delay
initialization. Instead, use the CLKUSR option to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONEpins are tied together.
1
If the optional CLKUSRpin is being used and nCONFIGis pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSRcontinues toggling during the time
nSTATUSis low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIGpin low. The nCONFIGpin should be low for at least
8 µs. When nCONFIGis pulled low, the FPGA also pulls nSTATUSand
CONF_DONElow and all I/O pins are tri-stated. Since CONF_DONEis
pulled low, this will activate the configuration device since it will see its
nCSpin drive low. Once nCONFIGreturns to a logic high state and
nSTATUSis released by the FPGA, reconfiguration begins.
Figure 6–2 shows how to configure multiple devices with a configuration
device. This circuit is similar to the configuration device circuit for a
single device, except APEX II devices are cascaded for multi-device
configuration.
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August 2005
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Passive Serial Configuration
Figure 6–2. Multi-Device PS Configuration Using an Enhanced Configuration Device
VCC(1)
VCC(1)
1 kΩ
1 kΩ
(3)
(3)
Enhanced
Configuration
Device
APEX II Device 2
DCLK
APEX II Device 1
DCLK
DCLK
DATA
MSEL0
MSEL0
DATA0
nSTATUS
DATA0
nSTATUS
MSEL1
(3)
MSEL1
OE
(3)
CONF_DONE
nCONFIG
nCS
CONF_DONE
nCONFIG
nINIT_CONF(2)
GND
GND
N.C.
nCE
nCEO
nCE
nCEO
GND
Notes to Figure 6–2:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used
or not available (e.g., on EPC1 devices), nCONFIGmust be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ and EPC2 devices’ OEand nCSpins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
1
Enhanced configuration devices (EPC4, EPC8, and EPC16)
cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device’s Programmer Object File (.pof) from each project’s
SRAM Object File (.sof). You can combine multiple SOFs using the
Quartus II software.
f
For more information on how to create configuration files for multi-
device configuration chains, refer to Software Settings, chapter 6 and 7 in
volume 2 of the Configuration Handbook.
6–8
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Altera Corporation
August 2005
Configuring APEX II Devices
In multi-device PS configuration, the first device’s nCEpin is connected
to GND while its nCEOpin is connected to nCEof the next device in the
chain. The last device’s nCEinput comes from the previous device, while
its nCEOpin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEOpin drives low to activate
the second device’s nCEpin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they can
require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DCLKand DATAlines are buffered
for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OEor nSTATUSpins. Similarly, since all device
CONF_DONEpins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUSand CONF_DONEpins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUSpin low. This low
signal drives the OEpin low on the enhanced configuration device and
drives nSTATUSlow on all FPGAs, which causes them to enter a reset
state. This behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUSpins after a reset time-out period
(maximum of 40 µs). When all the nSTATUSpins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-Restart Configuration After Error option is turned off, the external
system must monitor nSTATUSfor errors and then pulse nCONFIGlow
for at least 8 µs to restart configuration. The external system can pulse
nCONFIGif nCONFIGis under system control rather than tied to VCC
.
The enhanced configuration devices also support parallel configuration
of up to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode
allows enhanced configuration devices to concurrently configure FPGAs
or a chain of FPGAs. In addition, these devices do not have to be the same
device family or density; they can be any combination of Altera FPGAs.
An individual enhanced configuration device DATAline is available for
each targeted FPGA. Each DATAline can also feed a daisy chain of FPGAs.
Figure 6–3 shows how to concurrently configure multiple devices using
an enhanced configuration device.
Altera Corporation
August 2005
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 6–3. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device
V
V
CC
(1)
(1)
CC
Enhanced
Configuration
Device
1 kΩ
(3) (3)
1 kΩ
APEX II Device 1
DCLK
DCLK
DATA0
DATA0
nSTATUS
CONF_DONE
nCONFIG
DATA1
N.C. nCEO
DATA[2..6]
OE (3)
nCE
MSEL1
MSEL0
nCS (3)
nINIT_CONF (2)
GND
APEX II Device 2
DATA 7
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
N.C. nCEO
nCE
MSEL1
MSEL0
GND
GND
APEX II Device 8
DCLK
DATA0
nSTATUS
CONF_DONE
N.C. nCEO
nCONFIG
nCE
MSEL1
MSEL0
GND
GND
Notes to Figure 6–3:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used
or not available (e.g., on EPC1 devices), nCONFIGmust be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ and EPC2 devices’ OEand nCSpins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
6–10
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August 2005
Configuration Handbook, Volume 1
Configuring APEX II Devices
The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 6–3 to
select the appropriate configuration mode for the fastest configuration
times.
Table 6–3. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
2
3
4
5
6
7
8
1-bit PS
2-bit PS
4-bit PS
4-bit PS
8-bit PS
8-bit PS
8-bit PS
8-bit PS
Note to Table 6–3:
(1) Assume that each DATAline is only configuring one device, not a daisy chain of
devices.
For example, if you configure three FPGAs, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2lines, the corresponding SOF
data is transmitted from the configuration device to the FPGA. For
DATA3, you can leave the corresponding Bit3line blank in the Quartus
II software. On the printed circuit board (PCB), leave the DATA3line from
the enhanced configuration device unconnected. Figure 6–4 shows the
Quartus II Convert Programming Files window (Tools menu) setup for
this scheme.
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August 2005
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 6–4. Software Settings for Configuring Devices Using n-Bit PS Modes
Alternatively, you can daisy chain two FPGAs to one DATAline while the
other DATAlines drive one device each. For example, you could use the 2-
bit PS mode to drive two FPGAs with DATABit0(EP2A15 and EP2A25
devices) and the third device (the EP2A40 device) with DATA Bit1. This
2-bit PS configuration scheme requires less space in the configuration
flash memory, but can increase the total system configuration time. See
Figure 6–5.
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August 2005
Configuring APEX II Devices
Figure 6–5. Software Settings for Daisy Chaining Two FPGAs on One DATA Line
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEOpins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLKand DATAlines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 6–6 shows multi-device
PS configuration when the APEX II devices are receiving the same
configuration data.
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August 2005
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 6–6. Multiple-Device PS Configuration Using an Enhanced Configuration Device When FPGAs
Receive the Same Data
(1)
V
V
CC
(1)
CC
Enhanced
Configuration
Device
1 KΩ
GND
GND
(3) (3) 1 KΩ
APEX II Device 1
DCLK
DATA0
nSTATUS
DCLK
DATA0
(3)
OE
(3)
nCS
nINIT_CONF (2)
CONF_DONE
nCONFIG
(4)
N.C. nCEO
nCE
MSEL1
MSEL0
APEX II Device 2
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
(4)
N.C. nCEO
nCE
MSEL1
MSEL0
GND
APEX II Device 8
DCLK
DATA0
nSTATUS
CONF_DONE
(4)
N.C. nCEO
nCONFIG
nCE
MSEL1
MSEL0
GND
GND
Notes to Figure 6–6:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used
or not available (e.g., on EPC1 devices), nCONFIGmust be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ and EPC2 devices’ OEand nCSpins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
(4) The nCEOpins of all devices are left unconnected when configuring the same configuration data into multiple
devices.
6–14
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August 2005
Configuration Handbook, Volume 1
Configuring APEX II Devices
You can cascade several EPC2 or EPC1 devices to configure multiple
APEX II devices. The first configuration device in the chain is the master
configuration device, while the subsequent devices are the slave devices.
The master configuration device sends DCLKto the APEX II devices and
to the slave configuration devices. The first EPC device’s nCSpin is
connected to the CONF_DONEpins of the FPGAs, while its nCASCpin is
connected to nCSof the next configuration device in the chain. The last
device’s nCSinput comes from the previous device, while its nCASCpin
is left floating. When all data from the first configuration device is sent, it
drives nCASClow, which in turn drives nCSon the next configuration
device. Because a configuration device requires less than one clock cycle
to activate a subsequent configuration device, the data stream is
uninterrupted.
1
Enhanced configuration devices EPC4, EPC8, and EPC16 cannot
be cascaded.
Since all nSTATUSand CONF_DONEpins are tied together, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect CONF_DONEgoing high
at the end of configuration, it resets the entire chain by pulling its OEpin
low. This low signal drives the OEpin low on the slave configuration
device(s) and drives nSTATUSlow on all FPGAs, causing them to enter a
reset state. This behavior is similar to the FPGA detecting an error in the
configuration data.
Figure 6–7 shows how to configure multiple devices using cascaded
EPC2 or EPC1 devices.
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August 2005
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 6–7. Multi-Device PS Configuration Using Cascaded EPC2 or EPC1 Devices
VCC(1)
VCC(1)
VCC(1)
1 kΩ (3)
(3) 1 kΩ 1 kΩ (2)
EPC2/EPC1
Device 1
DCLK
DATA
OE (3)
EPC2/EPC1
Device 2
APEX II Device 2
DCLK
APEX II Device 1
DCLK
DATA0
MSEL0
MSEL1
MSEL0
DATA0
nSTATUS
DCLK
DATA
nSTATUS
MSEL1
CONF_DONE
nCONFIG
(3)
nCS
nINIT_CONF (2)
CONF_DONE
nCONFIG
nCS
OE
nCASC
GND
GND
N.C.
nINIT_CONF
nCE
nCEO
nCE
nCEO
GND
Notes to Figure 6–7:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used
or not available (e.g., on EPC1 devices), nCONFIGmust be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ and EPC2 devices’ OEand nCSpins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the FPGA can be connected to nINIT_CONF, which allows the
INIT_CONF JTAG instruction to initiate FPGA configuration. The
nINIT_CONFpin does not need to be connected if its functionality is not
used. If nINIT_CONFis not used or not available (e.g., on EPC1 devices),
nCONFIGmust be pulled to VCC either directly or through a resistor. An
internal pull-up resistor on the nINIT_CONFpin is always active in the
enhanced configuration devices and the EPC2 devices, which means an
external pull-up is not required if nCONFIGis tied to nINIT_CONF. If
multiple EPC2 devices are used to configure an APEX II device(s), only
the first EPC2 has its nINIT_CONFpin tied to the device’s nCONFIGpin.
You can use a single configuration chain to configure APEX II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONEand
nSTATUSpins must be tied together.
6–16
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August 2005
Configuration Handbook, Volume 1
Configuring APEX II Devices
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains
chapter 8 in volume 2 of the Configuration Handbook.
Figure 6–8 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 6–8. APEX II PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
tCH
tDSU
tCL
DCLK
DATA
tOEZX
tDH
D2
D0
D1
D3
Dn
tCO
Tri-State
User I/O
User Mode
Tri-State
INIT_DONE
(1)
Note to Figure 6–8:
(1) APEX II devices enter user-mode 40 clock cycles after CONF_DONEgoes high. The initialization clock can come from
the APEX II internal oscillator or the CLKUSRpin.
f
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, and EPC16) Data Sheet or the Configuration Devices for
SRAM-based LUT Devices Data Sheet in the Configuration Handbook.
Device configuration options and how to create configuration files are
discussed further in Section II, Software Settings, chapter 6 and 7 in
volume 2 of the Configuration Handbook.
PS Configuration Using a Microprocessor
In the PS configuration scheme, an intelligent host (e.g., a microprocessor
or CPLD) can transfer configuration data from a storage device (e.g., flash
memory) to the target APEX II devices. Configuration data can be stored
in RBF, HEX, or TTF format. Figure 6–9 shows the configuration interface
connections between the APEX II device and a microprocessor for single
device configuration.
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August 2005
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Configuration Handbook, Volume 1
Passive Serial Configuration
Figure 6–9. Single Device PS Configuration Using a Microprocessor
Memory
(1)
VCC
VCC (1)
1 kΩ
ADDR
DATA0
APEX II Device
1 kΩ
MSEL1
MSEL0
CONF_DONE
nSTATUS
GND
N.C.
nCE
nCEO
Microprocessor
GND
DATA0
nCONFIG
DCLK
Note to Figure 6–9:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal
for the device.
Upon power-up, the APEX II device goes through a POR for
approximately 5 µs. During POR, the device resets and holds nSTATUS
low, and tri-states all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins are tri-stated. APEX II devices have weak pull-up
resistors on the user I/O pins which are on before and during
configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the APEX II Programmable Logic Device Family Data Sheet.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIGor nSTATUSare low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIGpin.
1
VCCINTand VCCIOpins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIGgoes high, the device comes out of reset and releases the
open-drain nSTATUSpin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUSis released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUSis
pulled high, the microprocessor should place the configuration data one
bit at a time on the DATA0pin. The least significant bit (LSB) of each data
byte must be sent first.
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Configuration Handbook, Volume 1
August 2005
Configuring APEX II Devices
The APEX II device receives configuration data on its DATA0pin and the
clock is received on the DCLKpin. Data is latched into the FPGA on the
rising edge of DCLK. Data is continuously clocked into the target device
until CONF_DONEgoes high. After the FPGA has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 1-kΩpull-up resistor. A low-to-
high transition on CONF_DONEindicates configuration is complete and
initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSRpin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLKto the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSRoption. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSRwill not affect the configuration process. After all
configuration data has been accepted and CONF_DONEgoes high,
APEX II devices require 40 clock cycles to initialize properly.
An optional INIT_DONEpin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONEpin is used it will be high due to an external 1-kΩ
pull-up when nCONFIGis low and during the beginning of configuration.
Once the option bit to enable INIT_DONEis programmed into the device
(during the first frame of configuration data), the INIT_DONEpin will go
low. When initialization is complete, the INIT_DONEpin will be released
and pulled high. The microprocessor must be able to detect this low-to-
high transition which signals the FPGA has entered user mode. In user-
mode, the user I/O pins will no longer have weak pull-up resistors and
will function as assigned in your design. To ensure DCLKand DATAare
not left floating at the end of configuration, the microprocessor must
drive them either high or low, whichever is convenient on your board.
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Passive Serial Configuration
Handshaking signals are not used in PS configuration mode. Therefore,
the configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLKperiod
exists, which means you can pause configuration by halting DCLKfor an
indefinite amount of time.
If an error occurs during configuration, the FPGA drives its nSTATUSpin
low, resetting itself internally. The low signal on the nSTATUSpin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option (available in the Quartus II software from
the General tab of the Device & Pin Options dialog box) is turned on, the
APEX II device releases nSTATUSafter a reset time-out period (maximum
of 40 µs). After nSTATUSis released and pulled high by a pull-up resistor,
the microprocessor can try to reconfigure the target device without
needing to pulse nCONFIGlow. If this option is turned off, the
microprocessor must generate a low-to-high transition (with a low pulse
of at least 8 µs) on nCONFIGto restart the configuration process.
The microprocessor can also monitor the CONF_DONEand INIT_DONE
pins to ensure successful configuration. The CONF_DONEpin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONEor INIT_DONEhave not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSRpin is being used and nCONFIGis pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSRcontinues toggling during the time
nSTATUSis low (maximum of 40 µs).
When the FPGA is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIGpin low-to-high. The nCONFIGpin must be
low for at least 8 µs. When nCONFIGis pulled low, the FPGA also pulls
nSTATUSand CONF_DONElow and all I/O pins are tri-stated. Once
nCONFIGreturns to a logic high state and nSTATUSis released by the
FPGA, reconfiguration begins.
Figure 6–10 shows how to configure multiple devices using a
microprocessor. This circuit is similar to the PS configuration circuit for a
single device, except APEX II devices are cascaded for multi-device
configuration.
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August 2005
Configuring APEX II Devices
Figure 6–10. Multi-Device PS Configuration Using a Microprocessor
Memory
VCC (1) VCC (1)
ADDR
DATA0
APEX II Device 1
APEX II Device 2
MSEL1
1 kΩ
1 kΩ
MSEL1
MSEL0
MSEL0
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
GND
GND
nCE
nCEO
nCE
Microprocessor
GND
nCEO
N.C.
DATA0
DATA0
nCONFIG
DCLK
nCONFIG
DCLK
Note to Figure 6–10:
(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PS configuration the first device’s nCEpin is connected to
GND while its nCEOpin is connected to nCEof the next device in the
chain. The last device’s nCEinput comes from the previous device, while
its nCEOpin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEOpin drives low to activate
the second device’s nCEpin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. You should pay special attention to the configuration signals
because they can require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLKand DATAlines
are buffered for every fourth device. Because all device CONF_DONEpins
are tied together, all devices initialize and enter user mode at the same
time.
Since all nSTATUSand CONF_DONEpins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUSpin low. This
behavior is similar to a single FPGA detecting an error.
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August 2005
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Passive Serial Configuration
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUSpins after a reset time-out period (maximum of 40
µs). After all nSTATUSpins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIGlow. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIGto restart the configuration process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEOpins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. You should pay special
attention to the configuration signals because they can require buffering
to ensure signal integrity and prevent clock skew problems. Specifically,
ensure that the DCLKand DATAlines are buffered for every fourth device.
Devices must be the same density and package. All devices will start and
complete configuration at the same time. Figure 6–11 shows multi-device
PS configuration when both APEX II devices are receiving the same
configuration data.
Figure 6–11. Multiple-Device PS Configuration Using a Microprocessor When Both FPGAs Receive the Same
Data
Memory
VCC (1) VCC (1)
ADDR
DATA0
APEX II Device
APEX II Device
1 kΩ
1 kΩ
MSEL1
MSEL1
MSEL0
MSEL0
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
GND
GND
nCE
nCE
nCEO
N.C. (2)
Microprocessor
GND
nCEO
N.C. (2)
GND
DATA0
DATA0
nCONFIG
DCLK
nCONFIG
DCLK
Notes to Figure 6–11:
(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
(2) The nCEOpins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
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August 2005
Configuration Handbook, Volume 1
Configuring APEX II Devices
You can use a single configuration chain to configure APEX II devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONEand
nSTATUSpins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains
chapter 8 in volume 2 of the Configuration Handbook.
Figure 6–12 shows the timing waveform for the PS configuration for
APEX II devices using a microprocessor.
Figure 6–12. APEX II PS Configuration Using a Microprocessor Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (1)
tSTATUS
tCF2ST0
tCLK
CONF_DONE (2)
t
CH tCL
tCF2CD
tST2CK
(3)
DCLK
DATA
tDH
Bit 2 Bit 3
Bit n
Bit 0 Bit 1
(3)
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 6–12:
(1) Upon power-up, the APEX II device holds nSTATUSlow for not more than 5 µs after VCC reaches its minimum
requirement.
(2) Upon power-up, before and during configuration, CONF_DONEis low.
(3) DATA0and DCLKshould not be left floating after configuration. It should be driven high or low, whichever is more
convenient.
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Passive Serial Configuration
Table 6–4 defines the timing parameters for APEX II devices for PS
configuration.
Table 6–4. PS Timing Parameters for APEX II Devices Note (1)
Symbol
Parameter
Min
Max
200
200
Units
ns
tCF2CD
nCONFIGlow to CONF_DONElow
tCF2ST0 nCONFIGlow to nSTATUSlow
tCFG nCONFIGlow pulse width
ns
8
µs
tSTATUS nSTATUSlow pulse width
10
40
µs
tCF2ST1 nCONFIGhigh to nSTATUShigh
µs
1 (2)
tCF2CK
tST2CK
tDSU
tDH
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge on DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLKhigh time
40
1
µs
µs
10
0
ns
ns
tCH
7.5
7.5
15
ns
tCL
DCLKlow time
ns
tCLK
DCLKperiod
ns
fMAX
tCD2UM
DCLKmaximum frequency
66
8
MHz
µs
2
CONF_DONEhigh to user mode (3)
Notes to Table 6–4:
(1) This information is preliminary.
(2) This value is applicable if users do not delay configuration by extending the nSTATUSlow pulse width.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device. If the clock source is CLKUSR, multiply the clock period by 40 for APEX II devices to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings, chapters 6 and 7 in volume 2 of
the Configuration Handbook.
Configuring Using the MicroBlaster Driver
The MicroBlasterTM software driver allows you to configure Altera’s
FPGAs through the ByteBlasterMV cable in PS mode. The MicroBlaster
software driver supports a RBF programming input file and is targeted
for embedded passive serial configuration. The source code is developed
for the Windows NT operating system, although you can customize it to
run on other operating systems. For more information on the
MicroBlaster software driver, go to the Altera web site
http://www.altera.com).
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August 2005
Configuring APEX II Devices
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB Blaster universal serial bus (USB) port download cable,
TM
TM
MasterBlaster serial/USB communications cable, ByteBlaster II
TM
parallel port download cable, and the ByteBlasterMV parallel port
download cable.
In PS configuration with a download cable, an intelligent host (e.g., a PC)
transfers data from a storage device to the FPGA via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
Upon power-up, the APEX II device goes through a POR for
approximately 5 μs. During POR, the device resets and holds nSTATUS
low, and tri-states all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins are tri-stated. APEX II devices have weak pull-up
resistors on the user I/O pins which are on before and during
configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the APEX II Programmable Logic Device Family Data Sheet.
The configuration cycle consists of 3 stages: reset, configuration and
initialization. While nCONFIGor nSTATUSare low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIGpin.
1
VCCINTand VCCIOpins on the banks where the configuration,
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIGgoes high, the device comes out of reset and releases the
open-drain nSTATUSpin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUSis released the FPGA is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA0pin. The configuration data is clocked into
the target device until CONF_DONEgoes high.
When using a download cable, setting the Auto-Restart Configuration After
Error option does not affect the configuration cycle because you must
manually restart configuration in the Quartus II software when an error
occurs. Additionally, the Enable user-supplied start-up clock (CLKUSR)
option has no affect on the device initialization since this option is
disabled in the SOF when programming the FPGA using the Quartus II
programmer and download cable. Therefore, if you turn on the CLKUSR
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Passive Serial Configuration
option, you do not need to provide a clock on CLKUSRwhen you are
configuring the FPGA with the Quartus II programmer and a download
cable. Figure 6–13 shows PS configuration for APEX II devices using a
USB Blaster, MasterBlaster, ByteBlaster II or ByteBlasterMV cable.
Figure 6–13. PS Configuration Using a USB Blaster, MasterBlaster,
ByteBlaster II, or ByteBlasterMV Cable
VCC (1) VCC (1)
VCC (1) VCC (1)
1 kΩ
1 kΩ
1 kΩ 1 kΩ
APEX II Device
(2)
CONF_DONE
MSEL0
VCC (1)
nSTATUS
MSEL1
1 kΩ
(2)
GND
GND
nCE
nCEO
N.C.
Download Cable
10-Pin Male Header
(PS Mode)
DCLK
DATA0
nCONFIG
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 6–13:
(1) The pull-up resistor should be connected to the same supply voltage as the USB
Blaster, MasterBlaster (VIOpin), ByteBlaster II or ByteBlasterMV cable.
(2) The pull-up resistors on DATA0and DCLKare only needed if the download cable is
the only configuration scheme used on your board. This is to ensure that DATA0
and DCLKare not left floating after configuration. For example, if you are also
using a configuration device, the pull-up resistors on DATA0and DCLKare not
needed.
(3) Pin 6 of the header is a VIOreference voltage for the MasterBlaster output driver.
VIOshould match the device’s VCCIO. Refer to the MasterBlaster Serial/USB
Communications Cable Data Sheet for this value. In the ByteBlasterMV, this pin is
a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCE
when it is used for Active Serial programming, otherwise it is a no connect.
You can use a download cable to configure multiple APEX II devices by
connecting each device’s nCEOpin to the subsequent device’s nCEpin.
The first device’s nCEpin is connected to GND while its nCEOpin is
connected to the nCEof the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEOpin is left floating.
All other configuration pins, nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONEare connected to every device in the chain. Because all
CONF_DONEpins are tied together, all devices in the chain initialize and
enter user mode at the same time.
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Configuring APEX II Devices
In addition, because the nSTATUSpins are tied together, the entire chain
halts configuration if any device detects an error. The Auto-Restart
Configuration After Error option does not affect the configuration cycle
because you must manually restart configuration in the Quartus II
software when an error occurs.
Figure 6–14 shows how to configure multiple APEX II devices with a
download cable.
Figure 6–14. Multi-Device PS Configuration using a USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV Cable
VCC (1)
VCC (1)
Download Cable
10-Pin Male Header
(PS Mode)
1 kΩ
VCC (1)
(2)
1 kΩ
1 kΩ
APEX II Device 1
Pin 1
VCC (1)
CONF_DONE
VCC
MSEL0
MSEL1
nSTATUS
DCLK
1 kΩ
VCC (1)
1 kΩ
(2)
GND
VIO (3)
GND
GND
nCEO
nCE
DATA0
nCONFIG
GND
CONF_DONE
nSTATUS
DCLK
MSEL0
MSEL1
GND
nCE
nCEO
N.C.
DATA0
nCONFIG
APEX II Device 2
Notes to Figure 6–14:
(1) The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIOpin),
ByteBlaster II or ByteBlasterMV cable.
(2) The pull-up resistors on DATA0and DCLKare only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0and DCLKare not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0and DCLKare not needed.
(3) Pin 6 of the header is a VIOreference voltage for the MasterBlaster output driver. VIOshould match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCEwhen it
is used for Active Serial programming, otherwise it is a no connect.
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Passive Serial Configuration
If you are using a download cable to configure device(s) on a board that
also has configuration devices, you should electrically isolate the
configuration device from the target device(s) and cable. One way to
isolate the configuration device is to add logic, such as a multiplexer, that
can select between the configuration device and the cable. The
multiplexer chip should allow bidirectional transfers on the nSTATUS
and CONF_DONEsignals. Another option is to add switches to the five
common signals (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
between the cable and the configuration device. The last option is to
remove the configuration device from the board when configuring the
FPGA with the cable. Figure 6–15 shows a combination of a configuration
device and a download cable to configure an FPGA.
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Configuring APEX II Devices
Figure 6–15. PS Configuration with a Download Cable and Configuration Device Circuit
V
(1)
CC
Download Cable
10-Pin Male Header
(PS Mode)
V
(1)
CC
1 kΩ
(5)
(5)
1 kΩ
APEX II Device
(1)
V
CC
Pin 1
CONF_DONE
V
CC
1 kΩ
(4)
MSEL0
nSTATUS
DCLK
MSEL1
nCE
GND
VIO (2)
GND
GND
nCEO N.C.
(3)
(3)
(3)
DATA0
nCONFIG
GND
Configuration
Device
(3)
DCLK
DATA
(5)
OE
(3)
(5)
nCS
nINIT_CONF (4)
Notes to Figure 6–15:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) Pin 6 of the header is a VIOreference voltage for the MasterBlaster output driver. VIOshould match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCEwhen it
is used for Active Serial programming, otherwise it is a no connect.
(3) You should not attempt configuration with a download cable while a configuration device is connected to an
APEX II device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device.
(4) The nINIT_CONFpin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG
line. The nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used
or not available (e.g., on EPC1 devices), nCONFIGmust be pulled to VCC either directly or through a resistor.
(5) The enhanced configuration devices’ and EPC2 devices’ OEand nCSpins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-up resistors on configuration device option when generating programming files.
f
For more information on how to use the USB Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cables, refer to the following data sheets.
■
■
■
■
USB Blaster USB Port Download Cable Data Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Altera Corporation
August 2005
6–29
Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
Fast Passive Parallel (FPP) configuration in APEX II devices is designed
Fast Passive
Parallel
Configuration
to meet the continuously increasing demand for faster configuration
times. APEX II devices are designed with the capability of receiving byte-
wide configuration data per clock cycle, and guarantee a configuration
time of less than 100 ms with a 66-MHz configuration clock.
FPP configuration of APEX II devices can be performed using an Altera
enhanced configuration device or an intelligent host, such as a
microprocessor.
FPP Configuration Using an Enhanced Configuration Device
In the FPP configuration scheme, an enhanced configuration device sends
a byte of configuration data every DCLKcycle to the APEX II device.
Configuration data is stored in the configuration device. Figure 6–16
shows the configuration interface connections between the APEX II
device and the enhanced configuration device for single device
configuration.
1
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
f
For more information on the enhanced configuration device and flash
interface pins, such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0], refer to the Enhanced Configuration Devices (EPC4, EPC8, &
EPC16) Data Sheet in the Configuration Handbook.
6–30
Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
Figure 6–16. Single Device FPP Configuration Using an Enhanced
Configuration Device
V
(1)
V
(1)
CC
CC
Enhanced
Configuration
Device
1 kΩ
1 kΩ
(3) (3)
APEX II Device
DCLK
DCLK
DATA[7..0]
DATA[7..0]
nSTATUS
OE
(3)
nCS (3)
nINIT_CONF (2)
CONF_DONE
nCONFIG
V
CC
nCEO
nCE
N.C.
MSEL1
MSEL0
GND
GND
Notes to Figure 6–16:
(1) The pull-up resistor should be connected to the same supply voltage as the
configuration device.
(2) The nINIT_CONFpin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT_CONF/nCONFIGline. The nINIT_CONFpin
does not need to be connected if its functionality is not used. If nINIT_CONFis not
used, nCONFIGmust be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OEand nCSpins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option when
generating programming files.
f
The value of the internal pull-up resistors on the enhanced configuration
devices can be found in the Operating Conditions table of the Enhanced
Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet in the
Configuration Handbook.
When using enhanced configuration devices, nCONFIGof the FPGA can
be connected to nINIT_CONF, which allows the INIT_CONF JTAG
instruction to initiate FPGA configuration. The nINIT_CONFpin does
not need to be connected if its functionality is not used. If nINIT_CONFis
not used, nCONFIGmust be pulled to VCC either directly or through a
resistor. An internal pull-up on the nINIT_CONFpin is always active in
the enhanced configuration devices, which means an external pull-up is
not required if nCONFIGis tied to nINIT_CONF.
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August 2005
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Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 µs. During POR, the device resets and holds
nSTATUSlow, and tri-states all user I/O pins. The configuration device
also goes through a POR delay to allow the power supply to stabilize. The
POR time for enhanced configuration devices can be set to either 100 ms
or 2 ms, depending on its PORSELpin setting. If the PORSELpin is
connected to GND, the POR delay is 100 ms. During this time, the
configuration device drives its OEpin low. This low signal delays
configuration because the OEpin is connected to the target device’s
nSTATUSpin. When both devices complete POR, they release their open-
drain OEor nSTATUSpin, which is then pulled high by a pull-up resistor.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
APEX II devices have weak pull-up resistors on the user I/O pins which
are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the APEX II Programmable Logic Device Family Data Sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of 3
stages: reset, configuration, and initialization. While nCONFIGor
nSTATUSare low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIGor nSTATUSpin low.
1
VCCINTand VCCIOpins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIGgoes high, the device comes out of reset and releases the
nSTATUSpin, which is pulled high by a pull-up resistor. Enhanced
configuration devices have an optional internal pull-up on the OEpin.
This option is available in the Quartus II software from the General tab of
the Device & Pin Options dialog box. If this internal pull-up is not used,
an external 1-kΩpull-up on the OE/nSTATUSline is required. Once
nSTATUSis released the FPGA is ready to receive configuration data and
the configuration stage begins.
When nSTATUSis pulled high, OEof the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The APEX II device receives configuration
data on its DATA[7..0]pins and the clock is received on the DCLKpin.
A byte of data is latched into the FPGA on the rising edge of DCLK.
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August 2005
Configuring APEX II Devices
After the FPGA has received all configuration data successfully it releases
the open-drain CONF_DONEpin, which is pulled high by a pull-up
resistor. Since CONF_DONEis tied to the configuration device’s nCSpin,
the configuration device is disabled when CONF_DONEgoes high.
Enhanced configuration devices have an optional internal pull-up on the
nCSpin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal pull-
up is not used, an external 1kΩpull-up on the nCS/CONF_DONEline is
required. A low to high transition on CONF_DONEindicates configuration
is complete and initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSRpin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. You also have the
flexibility to synchronize initialization of multiple devices by using the
CLKUSRoption. The Enable user-supplied start-up clock (CLKUSR) option
can be turned on in the Quartus II software from the General tab of the
Device & Pin Options dialog box. Supplying a clock on CLKUSRwill not
affect the configuration process. After all configuration data has been
accepted and CONF_DONEgoes high, APEX II devices require 40 clock
cycles to initialize properly.
An optional INIT_DONEpin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONEpin is used it will be high due to an external 1-kΩpull-
up resistor when nCONFIGis low and during the beginning of
configuration. Once the option bit to enable INIT_DONEis programmed
into the device (during the first frame of configuration data), the
INIT_DONEpin will go low. When initialization is complete, the
INIT_DONEpin will be released and pulled high. In user-mode, the user
I/O pins will no longer have weak pull-ups and will function as assigned
in your design. The enhanced configuration device will drive DCLKlow
and DATA[7..0]high at the end of configuration.
If an error occurs during configuration, the FPGA drives its nSTATUSpin
low, resetting itself internally. Since the nSTATUSpin is tied to OE, the
configuration device will also be reset. If the Auto-Restart Configuration
After Error option-available in the Quartus II software from the General
tab of the Device & Pin Options dialog box-is turned on, the FPGA will
automatically initiate reconfiguration if an error occurs. The APEX II
device will release its nSTATUSpin after a reset time-out period
(maximum of 40 µs). When the nSTATUSpin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
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August 2005
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Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
this option is turned off, the external system must monitor nSTATUSfor
errors and then pulse nCONFIGlow for at least 8 µs to restart
configuration. The external system can pulse nCONFIG, if nCONFIGis
under system control rather than tied to VCC
.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONEhas not gone high, it recognizes that the FPGA
has not configured successfully. Enhanced configuration devices wait for
64 DCLKcycles after the last configuration bit was sent for CONF_DONEto
reach a high state. In this case, the configuration device pulls its OEpin
low, which in turn drives the target device’s nSTATUSpin low. If the Auto-
Restart Configuration After Error option is set in the software, the target
device resets and then release its nSTATUSpin after a reset time-out
period (maximum of 40 µs). When nSTATUSreturns high, the
configuration device will try to reconfigure the FPGA.
When CONF_DONEis sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully;
therefore, your system should not pull CONF_DONElow to delay
initialization. Instead, you should use the CLKUSR option to synchronize
the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain will
initialize together if their CONF_DONEpins are tied together.
If the optional CLKUSRpin is being used and nCONFIGis pulled low to
restart configuration during device initialization, you need to ensure
CLKUSRcontinues toggling during the time nSTATUSis low (maximum
of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIGpin low. The nCONFIGpin should be low for at least
8 µs. When nCONFIGis pulled low, the FPGA also pulls nSTATUSand
CONF_DONElow and all I/O pins are tri-stated. Since CONF_DONEis
pulled low, this will activate the configuration device since it will see its
nCSpin drive low. Once nCONFIGreturns to a logic high state and
nSTATUSis released by the FPGA, reconfiguration begins.
Figure 6–17 shows how to configure multiple APEX II devices with an
enhanced configuration device. This circuit is similar to the configuration
device circuit for a single device, except the APEX II devices are cascaded
for multi-device configuration.
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Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
Figure 6–17. Multi-Device FPP Configuration Using an Enhanced Configuration Device
V
(1)
CC
V
(1)
CC
1 kΩ
(3)
(3) 1 kΩ
Enhanced
APEX II Device 2
APEX II Device 1
Configuration Device
V
CC
V
CC
MSEL1
MSEL0
DCLK
DATA[7..0]
nSTATUS
MSEL1
MSEL0
DCLK
DATA[7..0]
nSTATUS
DCLK
DATA[7..0]
(3)
OE
GND
N.C.
GND
(3)
CONF_DONE
nCONFIG
CONF_DONE
nCONFIG
nCS
nINIT_CONF (2)
nCEO
nCE
nCEO
nCE
GND
Notes to Figure 6–17:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIGline. The
nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-up resistors on configuration device option when generating programming files.
1
Enhanced configuration devices (EPC4/8/16) cannot be
cascaded.
When performing multi-device configuration, you must generate the
configuration device’s POF from each project’s SOF. You can combine
multiple SOFs using the Quartus II software.
f
For more information on how to create configuration files for multi-
device configuration chains, refer to Software Settings, chapter 6 and 7 in
volume 2 of the Configuration Handbook.
In multi-device FPP configuration the first device’s nCEpin is connected
to GND while its nCEOpin is connected to nCEof the next device in the
chain. The last device’s nCEinput comes from the previous device, while
its nCEOpin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEOpin drives low to activate
the second device’s nCEpin, which prompts the second device to begin
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August 2005
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Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA[7..0], and CONF_DONE) are connected to every device in the
chain. You should pay special attention to the configuration signals
because they may require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLKand DATAlines
are buffered for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OEor nSTATUSpins. Similarly, since all device
CONF_DONEpins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUSand CONF_DONEpins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUSpin low. This low
signal drives the OEpin low on the enhanced configuration device and
drives nSTATUSlow on all FPGAs, which causes them to enter a reset
state. This behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
FPGAs will release their nSTATUSpins after a reset time-out period
(maximum of 40 µs). When all the nSTATUSpins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-Restart Configuration After Error option is turned off, the external
system must monitor nSTATUSfor errors and then pulse nCONFIGlow
for at least 8 µs to restart configuration. The external system can pulse
nCONFIGif nCONFIGis under system control rather than tied to VCC
.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEOpins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. You should pay
special attention to the configuration signals because they may require
buffering to ensure signal integrity and prevent clock skew problems.
Specifically, ensure that the DCLKand DATAlines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 6–18 shows
multi-device FPP configuration when both APEX II devices are receiving
the same configuration data.
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Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
Figure 6–18. Multiple-Device FPP Configuration Using an Enhanced Configuration Device When Both FPGAs
Receive the Same Data
V
(1)
CC
V
(1)
CC
1 kΩ
(3)
(3)
1 kΩ
Enhanced
APEX II Device
APEX II Device
Configuration Device
V
CC
V
CC
MSEL1
MSEL0
DCLK
DATA[7..0]
nSTATUS
MSEL1
MSEL0
DCLK
DATA[7..0]
nSTATUS
DCLK
DATA[7..0]
(3)
OE
GND
GND
(3)
CONF_DONE
nCONFIG
CONF_DONE
nCONFIG
nCS
nINIT_CONF (2)
(4) N.C.
(4) N.C.
nCEO
nCE
nCEO
nCE
GND
GND
Notes to Figure 6–18:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIGline. The
nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
(4) The nCEOpins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single enhanced configuration chain to configure multiple
APEX II devices with other Altera devices that support FPP
configuration, such as Stratix® and Stratix GX devices. To ensure that all
devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONEand nSTATUSpins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–19 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
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August 2005
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Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
Figure 6–19. APEX II FPP Configuration Using an Enhanced Configuration Device Timing Waveform
nINIT_CONF or
VCC/nCONFIG
tLOE
OE/nSTATUS
nCS/CONF_DONE
tHC
tLC
tCE
DCLK
DATA
bit/byte bit/byte
bit/byte
Driven High
1
n
2
tOE
User I/O
User Mode
Tri-State
Tri-State
INIT_DONE
(1)
Note to Figure 6–19:
(1) APEX II devices enter user mode 40 clock cycles after CONF_DONEgoes high. The initialization clock can come from
the APEX II internal oscillator or the CLKUSRpin.
f
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8, & EPC16) Data Sheet in the Configuration Handbook.
Device configuration options and how to create configuration files are
discussed further in Software Settings, chapter 6 and 7 in volume 2 of the
Configuration Handbook.
FPP Configuration Using a Microprocessor
In the FPP configuration scheme, an intelligent host, such as a
microprocessor or CPLD, can transfer configuration data from a storage
device, such as flash memory, to the target APEX II device. Configuration
data can be stored in RBF, HEX or TTF format. Figure 6–20 shows the
configuration interface connections between the APEX II device and a
microprocessor for single device configuration.
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Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
Figure 6–20. Single Device FPP Configuration Using a Microprocessor
Memory
V
CC
(1)
V
CC
(1)
ADDR DATA[7..0]
V
CC
APEX II Device
1 kΩ
1 kΩ
MSEL1
MSEL0
CONF_DONE
nSTATUS
GND
N.C.
nCE
nCEO
Microprocessor
GND
DATA[7..0]
nCONFIG
DCLK
Note to Figure 6–20:
(1) The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 µs. During POR, the device resets and holds
nSTATUSlow, and tri-states all user I/O pins. Once the FPGA
successfully exits POR, all user I/O pins are tri-stated. APEX II devices
have weak pull-up resistors on the user I/O pins which are on before and
during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the APEX II Programmable Logic Device Family Data Sheet.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIGor nSTATUSare low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIGpin.
1
VCCINTand VCCIOpins on the banks where the configuration,
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIGgoes high, the device comes out of reset and releases the
open-drain nSTATUSpin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUSis released, the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUSis
pulled high, the microprocessor should place the configuration data one
byte at a time on the DATA[7..0]pins.
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Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
The APEX II device receives configuration data on its DATA[7..0]pins
and the clock is received on the DCLKpin. Data is latched into the FPGA
on the rising edge of DCLK. Data is continuously clocked into the target
device until CONF_DONEgoes high. After the FPGA has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 1-kΩpull-up resistor. A low-to-
high transition on CONF_DONEindicates configuration is complete and
initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSRpin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device. Driving DCLKto the device after configuration is complete does
not affect device operation.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSRoption. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSRwill not affect the configuration process. After all
configuration data has been accepted and CONF_DONEgoes high,
APEX II devices require 40 clock cycles to initialize properly.
An optional INIT_DONEpin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONEpin is used it will be high due to an external 1-kΩpull-
up resistor when nCONFIGis low and during the beginning of
configuration. Once the option bit to enable INIT_DONEis programmed
into the device (during the first frame of configuration data), the
INIT_DONEpin will go low. When initialization is complete, the
INIT_DONEpin will be released and pulled high. The microprocessor
must be able to detect this low-to-high transition which signals the FPGA
has entered user mode. In user-mode, the user I/O pins will no longer
have weak pull-ups and will function as assigned in your design. When
initialization is complete, the FPGA enters user mode.
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August 2005
Configuring APEX II Devices
To ensure DCLKand DATA0are not left floating at the end of
configuration, the microprocessor must take care to drive them either
high or low, whichever is convenient on your board. The DATA[7..1]
pins are available as user I/O pins after configuration. When the FPP
scheme is chosen in the Quartus II software, as a default these I/O pins
are tri-stated in user mode and should be driven by the microprocessor.
To change this default option in the Quartus II software, select the Dual-
Purpose Pins tab of the Device & Pin Options dialog box.
Handshaking signals are not used in FPP configuration mode. Therefore,
the configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLKperiod
exists, which means you can pause configuration by halting DCLKfor an
indefinite amount of time.
If an error occurs during configuration, the FPGA drives its nSTATUSpin
low, resetting itself internally. The low signal on the nSTATUSpin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUSafter a reset time-out period (maximum of 40
µs). After nSTATUSis released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIGlow. If this option is turned off, the microprocessor
must generate a low-to-high transition (with a low pulse of at least 8 µs)
on nCONFIGto restart the configuration process.
The microprocessor can also monitor the CONF_DONEand INIT_DONE
pins to ensure successful configuration. The CONF_DONEpin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONEor INIT_DONEhave not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSRpin is being used and nCONFIGis pulled
low to restart configuration during device initialization, you
need to ensure CLKUSRcontinues toggling during the time
nSTATUSis low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIGpin low-to-high. The nCONFIGpin should be
low for at least 8 µs. When nCONFIGis pulled low, the FPGA also pulls
nSTATUSand CONF_DONElow and all I/O pins are tri-stated. Once
nCONFIGreturns to a logic high state and nSTATUSis released by the
FPGA, reconfiguration begins.
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Fast Passive Parallel Configuration
Figure 6–21 shows how to configure multiple devices using a
microprocessor. This circuit is similar to the FPP configuration circuit for
a single device, except the APEX II devices are cascaded for multi-device
configuration.
Figure 6–21. Multi-Device FPP Configuration Using a Microprocessor
Memory
V
CC
(1)
V
(1)
CC
ADDR DATA[7..0]
V
CC
V
CC
APEX II Device 1
MSEL1
APEX II Device 2
MSEL1
1 kΩ
1 kΩ
MSEL0
MSEL0
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
GND
GND
N.C.
nCE
nCEO
nCE
nCEO
Microprocessor
GND
DATA[7..0]
DATA[7..0]
nCONFIG
DCLK
nCONFIG
DCLK
Note to Figure 6–21:
(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device FPP configuration the first device’s nCEpin is connected
to GND while its nCEOpin is connected to nCEof the next device in the
chain. The last device’s nCEinput comes from the previous device, while
its nCEOpin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEOpin drives low to activate
the second device’s nCEpin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. You should pay special attention to the configuration signals
because they may require buffering to ensure signal integrity and prevent
clock skew problems. Specifically, ensure that the DCLKand DATAlines
are buffered for every fourth device. Because all device CONF_DONEpins
are tied together, all devices initialize and enter user mode at the same
time.
6–42
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August 2005
Configuration Handbook, Volume 1
Configuring APEX II Devices
Since all nSTATUSand CONF_DONEpins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUSpin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUSpins after a reset time-out period (maximum of 40
µs). After all nSTATUSpins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIGlow. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIGto restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEOpins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. You should pay
special attention to the configuration signals because they may require
buffering to ensure signal integrity and prevent clock skew problems.
Specifically, ensure that the DCLKand DATAlines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 6–22 shows
multi-device FPP configuration when both APEX II devices are receiving
the same configuration data.
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August 2005
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Configuration Handbook, Volume 1
Fast Passive Parallel Configuration
Figure 6–22. Multiple-Device FPP Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
Memory
V
CC
(1)
V
(1)
CC
ADDR DATA[7..0]
V
CC
V
CC
APEX II Device
MSEL1
APEX II Device
MSEL1
1 kΩ
1 kΩ
MSEL0
MSEL0
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
GND
N.C. (2)
GND
N.C. (2)
nCE
nCEO
nCE
nCEO
Microprocessor
GND
GND
DATA[7..0]
DATA[7..0]
nCONFIG
DCLK
nCONFIG
DCLK
Notes to Figure 6–22:
(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
(2) The nCEOpins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure APEX II devices
with other Altera devices that support FPP configuration, such as Stratix.
To ensure that all devices in the chain complete configuration at the same
time or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONEand nSTATUSpins must be tied
together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–23 shows the timing waveform for the FPP configuration
scheme using a microprocessor.
6–44
Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
Figure 6–23. APEX II FPP Configuration Using a Microprocessor Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS
(1)
tSTATUS
tCF2ST0
tCLK
(2)
CONF_DONE
t
CH tCL
tCF2CD
tST2CK
(3)
DCLK
DATA
tDH
(3)
Byte 0 Byte 1 Byte 2 Byte 3
Byte n
User Mode
User Mode
tDSU
High-Z
User I/O
INIT_DONE
tCD2UM
Notes to Figure 6–23:
(1) Upon power-up, the APEX II device holds nSTATUSlow for not more than 5 µs after VCC reaches its minimum
requirement.
(2) Upon power-up, before and during configuration, CONF_DONEis low.
(3) DATA0and DCLKshould not be left floating after configuration. It should be driven high or low, whichever is more
convenient. DATA[7..1]are available as user I/O pins after configuration and the state of theses pins depends on
the design programmed into the device.
Table 6–5 defines the timing parameters for APEX II devices for FPP
configuration.
Table 6–5. FPP Timing Parameters for APEX II Devices (Part 1 of 2)
Note (1)
Min
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
Max
200
200
Units
ns
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
ns
nCONFIGlow pulse width
8
µs
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
nSTATUSlow pulse width
10
40 (2)
1 (2)
µs
nCONFIGhigh to nSTATUShigh
µs
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge on DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
40
1
µs
µs
10
0
ns
tDH
ns
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August 2005
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Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
Table 6–5. FPP Timing Parameters for APEX II Devices (Part 2 of 2)
Note (1)
Min
Symbol
tCH
Parameter
Max
Units
ns
DCLKhigh time
DCLKlow time
DCLKperiod
7.5
7.5
15
tCL
ns
tCLK
ns
fMAX
DCLKfrequency
66
8
MHz
µs
tCD2UM
CONF_DONEhigh to user mode (3)
2
Notes to Table 6–5:
(1) This information is preliminary.
(2) This value is obtainable if users do not delay configuration by extending the nCONFIGor nSTATUSlow pulse
width.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in Software Settings, chapter 6 and 7 in volume 2 of the
Configuration Handbook.
Configuring Using the MicroBlaster Driver
The MicroBlasterTM software driver supports a RBF programming input
file and is targeted for embedded fast passive parallel configuration. The
source code is developed for the Windows NT operating system,
although you can customize it to run on other operating systems. For
more information on the MicroBlaster software driver, go to the Altera
web site (http://www.altera.com).
Passive Parallel Asynchronous (PPA) configuration uses an intelligent
host, such as a microprocessor, to transfer configuration data from a
storage device, such as flash memory, to the target APEX II device.
Configuration data can be stored in TTF, RBF or HEX format. The host
system outputs byte-wide data and the accompanying strobe signals to
the FPGA. When using PPA, you should pull the DCLKpin high through
a 1-kΩpull-up resistor to prevent unused configuration input pins from
floating.
Passive Parallel
Asynchronous
Configuration
Figure 6–24 shows the configuration interface connections between the
FPGA and a microprocessor for single device PPA configuration. The
microprocessor or an optional address decoder can control the device’s
chip select pins, nCSand CS. The address decoder allows the
microprocessor to select the APEX II device by accessing a particular
address, which simplifies the configuration process. The nCSand CSpins
must be held active during configuration and initialization.
6–46
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Configuration Handbook, Volume 1
August 2005
Configuring APEX II Devices
Figure 6–24. Single Device PPA Configuration Using a Microprocessor Note (1)
Address Decoder
ADDR
(2)
V
CC
(2)
Memory
V
CC
1 kΩ
ADDR DATA[7..0]
1 kΩ
VCC
APEX II Device
(1)
MSEL1
MSEL0
nCS
(1)
CS
CONF_DONE
nSTATUS
nCE
N.C.
nCEO
DCLK
Microprocessor
GND
(2)
V
CC
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
1 kΩ
Notes to Figure 6–24:
(1) If not used, the CS pin can be connected to VCC directly. If not used, the nCSpin can be connected to GND directly.
(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device.
During PPA configuration, it is only required to use either the nCSor CS
pin. Therefore, if only one chip-select input is used, the other must be tied
to the active state. For example, nCScan be tied to ground while CSis
toggled to control configuration. The device’s nCSor CSpins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Table 6–6.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5 μs. During POR, the device resets and holds
nSTATUSlow, and tri-states all user I/O pins. Once the FPGA
successfully exits POR, all user I/O pins are tri-stated. APEX II devices
have weak pull-up resistors on the user I/O pins which are on before and
during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the APEX II Programmable Logic Device Family Data Sheet.
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August 2005
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Configuration Handbook, Volume 1
Passive Parallel Asynchronous Configuration
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIGor nSTATUSare low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIGpin.
1
VCCINTand VCCIOpins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIGgoes high, the device comes out of reset and releases the
open-drain nSTATUSpin, which is then pulled high by an external 1-kΩ
pull-up resistor. Once nSTATUSis released the FPGA is ready to receive
configuration data and the configuration stage begins. When nSTATUSis
pulled high, the microprocessor should then assert the target device’s
nCSpin low and/or CSpin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0]pins
and pulses the nWSpin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSYsignal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the APEX II device is processing
the byte of configuration data.
During the time RDYnBSYis low, the APEX II device internally processes
the configuration data using its internal oscillator (typically 10 MHz).
When the device is ready for the next byte of configuration data, it will
drive RDYnBSYhigh. If the microprocessor senses a high signal when it
polls RDYnBSY, the microprocessor sends the next byte of configuration
data to the FPGA.
Alternatively, the nRSsignal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSYdoes not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Data should not be driven onto the data bus while nRSis low because it
will cause contention on the DATA7pin. If the nRSpin is not used to
monitor configuration, it should be tied high.
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of tBUSY(max) + tRDY2WS + tW2SB before sending the
next data byte. In this set-up, nRSshould be tied high and RDYnBSYdoes
not need to be connected to the microprocessor. The tBUSY, tRDY2WS and
tW2SB timing specifications are listed in Table 6–6.
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Configuring APEX II Devices
Next, the microprocessor checks nSTATUSand CONF_DONE. If nSTATUS
is not low and CONF_DONEis not high, the microprocessor sends the next
data byte. However, if nSTATUSis not low and all the configuration data
has been received, the device is ready for initialization. After the FPGA
has received all configuration data successfully, it releases the open-drain
CONF_DONEpin, which is pulled high by an external 1-kΩpull-up
resistor. A low-to-high transition on CONF_DONEindicates configuration
is complete and initialization of the device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional CLKUSRpin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will take care to provide
itself with enough clock cycles for proper initialization. Therefore, if the
internal oscillator is the initialization clock source, sending the entire
configuration file to the device is sufficient to configure and initialize the
device.
You also have the flexibility to synchronize initialization of multiple
devices by using the CLKUSRoption. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. Supplying a clock
on CLKUSRwill not affect the configuration process. After all
configuration data has been accepted and CONF_DONEgoes high, APEX
II devices require 40 clock cycles to initialize properly.
An optional INIT_DONEpin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONEpin is used it will be high due to an external 1-kΩpull-
up when nCONFIGis low and during the beginning of configuration.
Once the option bit to enable INIT_DONEis programmed into the device
(during the first frame of configuration data), the INIT_DONEpin will go
low. When initialization is complete, the INIT_DONEpin will be released
and pulled high. The microprocessor must be able to detect this low-to-
high transition which signals the FPGA has entered user mode. In user-
mode, the user I/O pins will no longer have weak pull-ups and will
function as assigned in your design. When initialization is complete, the
FPGA enters user mode.
To ensure DATA0is not left floating at the end of configuration, the
microprocessor must take care to drive them either high or low,
whichever is convenient on your board. After configuration, the nCS, CS,
nRS, nWS, RDYnBSY, and DATA[7..1]pins can be used as user I/O pins.
When the PPA scheme is chosen in the Quartus II software, as a default
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Passive Parallel Asynchronous Configuration
these I/O pins are tri-stated in user mode and should be driven by the
microprocessor. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
If an error occurs during configuration, the FPGA drives its nSTATUSpin
low, resetting itself internally. The low signal on the nSTATUSpin also
alerts the microprocessor that there is an error. If the Auto-Restart
Configuration After Error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
FPGA releases nSTATUSafter a reset time-out period (maximum of 40
µs). After nSTATUSis released and pulled high by a pull-up resistor, the
microprocessor can try to reconfigure the target device without needing
to pulse nCONFIGlow. If this option is turned off, the microprocessor
must generate a low-to-high transition (with a low pulse of at least 8 µs)
on nCONFIGto restart the configuration process.
The microprocessor can also monitor the CONF_DONEand INIT_DONE
pins to ensure successful configuration. The CONF_DONEpin must be
monitored by the microprocessor to detect errors and determine when
programming completes. If the microprocessor sends all configuration
data but CONF_DONEor INIT_DONEhas not gone high, the
microprocessor must reconfigure the target device.
1
If the optional CLKUSRpin is being used and nCONFIGis pulled
low to restart configuration during device initialization, you
need to ensure CLKUSRcontinues toggling during the time
nSTATUSis low (maximum of 40 µs).
When the FPGA is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIGpin low-to-high. The nCONFIGpin should be
low for at least 8 µs. When nCONFIGis pulled low, the FPGA also pulls
nSTATUSand CONF_DONElow and all I/O pins are tri-stated. Once
nCONFIGreturns to a logic high state and nSTATUSis released by the
FPGA, reconfiguration begins.
Figure 6–25 shows how to configure multiple APEX II devices using a
microprocessor. This circuit is similar to the PPA configuration circuit for
a single device, except the devices are cascaded for multi-device
configuration.
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Configuration Handbook, Volume 1
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August 2005
Configuring APEX II Devices
Figure 6–25. Multi-Device PPA Configuration Using a Microprocessor
V
CC
(2)
V
(2)
CC
1 kΩ
V
CC
(2)
1 kΩ
1 kΩ
Address Decoder
ADDR
V
CC (2)
Memory
1 kΩ
DATA[7..0]
ADDR
APEX II Device 1
DATA[7..0]
(1)
APEX II Device 2
DATA[7..0]
(1)
nCS
nCE
DCLK
nCS
GND
CS (1)
CS (1)
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
nCE
DCLK
Microprocessor
nCEO
N.C.
nCEO
nWS
nRS
nWS
nRS
V
CC
V
CC
MSEL1
MSEL0
MSEL1
MSEL0
nCONFIG
RDYnBSY
nCONFIG
RDYnBSY
Notes to Figure 6–25:
(1) If not used, the CSpin can be connected to VCC directly. If not used, the nCSpin can be connected to GND directly.
(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
In multi-device PPA configuration the first device’s nCEpin is connected
to GND while its nCEOpin is connected to nCEof the next device in the
chain. The last device’s nCEinput comes from the previous device, while
its nCEOpin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEOpin drives low to activate
the second device’s nCEpin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the microprocessor.
Each device’s RDYnBSYpin can have a separate input to the
microprocessor. Alternatively, if the microprocessor is pin limited, all the
RDYnBSYpins can feed an ANDgate and the output of the ANDgate can
feed the microprocessor. For example, if you have 2 devices in a PPA
configuration chain, the second device’s RDYnBSYpin will be high during
the time that the first device is being configured. When the first device has
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Passive Parallel Asynchronous Configuration
been successfully configured, it will driven nCEOlow to activate the next
device in the chain and drive its RDYnBSYpin high. Therefore, since
RDYnBSYsignal is driven high before configuration and after
configuration before entering user-mode, the device being configured
will govern the output of the ANDgate.
The nRSsignal can be used in multi-device PPA chain since the APEX II
device will tri-state its DATA[7..0]pins before configuration and after
configuration before entering user-mode to avoid contention. Therefore,
only the device that is currently being configured will respond to the nRS
strobe by asserting DATA7.
All other configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS,
CS, nWS, nRSand CONF_DONE) are connected to every device in the chain.
You should pay special attention to the configuration signals because
they may require buffering to ensure signal integrity and prevent clock
skew problems. Specifically, ensure that the DATAlines are buffered for
every fourth device. Because all device CONF_DONEpins are tied together,
all devices initialize and enter user mode at the same time.
Since all nSTATUSand CONF_DONEpins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first FPGA flags an error
on nSTATUS, it resets the chain by pulling its nSTATUSpin low. This
behavior is similar to a single FPGA detecting an error.
If the Auto-Restart Configuration After Error option is turned on, the FPGAs
release their nSTATUSpins after a reset time-out period (maximum of 40
µs). After all nSTATUSpins are released and pulled high, the
microprocessor can try to reconfigure the chain without needing to pulse
nCONFIGlow. If this option is turned off, the microprocessor must
generate a low-to-high transition (with a low pulse of at least 8 µs) on
nCONFIGto restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEOpins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DATA[7..1], nCS, CS, nWS,
nRSand CONF_DONE) are connected to every device in the chain. You
should pay special attention to the configuration signals because they
may require buffering to ensure signal integrity and prevent clock skew
problems. Specifically, ensure that the DATAlines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 6–26 shows
multi-device PPA configuration when both devices are receiving the same
configuration data.
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August 2005
Configuring APEX II Devices
Figure 6–26. Multiple-Device PPA Configuration Using a Microprocessor When Both FPGAs Receive the
Same Data
V
(2)
CC
V
(2)
CC
1 kΩ
(2)
V
1 kΩ
CC
1 kΩ
Address Decoder
ADDR
V
(2)
CC
Memory
1 kΩ
DATA[7..0]
ADDR
APEX II Device
DATA[7..0]
nCS (1)
APEX II Device
DATA[7..0]
nCE
DCLK
nCS (1)
CS (1)
GND
CS (1)
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
nCE
DCLK
nCEO
Microprocessor
nCEO
N.C. (3)
GND
N.C. (3)
nWS
nWS
V
CC
nRS
nCONFIG
RDYnBSY
nRS
nCONFIG
V
CC
MSEL1
MSEL0
RDYnBSY
MSEL1
MSEL0
Notes to Figure 6–26:
(1) If not used, the CSpin can be connected to VCC directly. If not used, the nCSpin can be connected to GND directly.
(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
(3) The nCEOpins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure APEX II devices
with other Altera devices that support PPA configuration, such as Stratix,
Mercury, APEX 20K, ACEX 1K, and FLEX 10KE devices. To ensure that all
devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONEand nSTATUSpins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
Figure 6–27 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
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Passive Parallel Asynchronous Configuration
Figure 6–27. APEX II PPA Configuration Timing Waveform
tCFG
tCF2ST1
nCONFIG
nSTATUS (1)
CONF_DONE (2)
DATA[7..0]
(3) CS
(4)
(4)
(4)
(4)
(4)
Byte 0
tDSU
Byte 1
Byte n
1
Byte n
tCSH
tCSSU
tDH
tCF2WS
(3) nCS
tWSP
nWS
tRDY2WS
RDYnBSY
tWS2B
tSTATUS
tCF2ST0
tCF2CD
tBUSY
tCD2UM
High-Z
User I/Os
High-Z
User-Mode
INIT_DONE
Notes to Figure 6–27:
(1) Upon power-up, the APEX II device holds nSTATUSlow for not more than 5 μs after VCCINT reaches its minimum
requirement.
(2) Upon power-up, before and during configuration, CONF_DONEis low.
(3) The user can toggle nCSor CSduring configuration if the design meets the specification for tCSSU, tWSP, and tCSH
.
(4) DATA0should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRSand RDYnBSYare available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Figure 6–28 shows the timing waveform for the PPA configuration
scheme when using a strobed nRSand nWSsignal.
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Configuration Handbook, Volume 1
Configuring APEX II Devices
Figure 6–28. APEX II PPA Configuration Timing Waveform Using nRS & nWS
t
CF2ST1
t
CFG
nCONFIG
(1) nSTATUS
t
STATUS
t
CF2SCD
(2) CONF_DONE
t
CSSU
(4)
(4)
(4)
(4)
(4)
nCS (3)
t
CSH
CS (3)
t
DH
Byte 0
Byte 1
Byte n
DATA[7..0]
nWS
t
DSU
t
t
WSP
t
RS2WS
nRS
WS2RS
t
t
CF2WS
WS2RS
tRSD7
INIT_DONE
User I/O
t
RDY2WS
High-Z
User-Mode
t
WS2B
(4)
DATA7/RDYnBSY (5)
t
CD2UM
t
BUSY
Notes to Figure 6–28:
(1) Upon power-up, the APEX II device holds nSTATUSlow for not more than 5 μs after VCCINT reaches its minimum
requirement.
(2) Upon power-up, before and during configuration, CONF_DONEis low.
(3) The user can toggle nCSor CSduring configuration if the design meets the specification for tCSSU, tWSP, and tCSH
.
(4) DATA0should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..1], CS, nCS, nWS, nRS, and RDYnBSYare available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
(5) DATA7is a bidirectional pin. It is an input for configuration data input, but it is an output to show the status of
RDYnBSY.
Table 6–6 defines the timing parameters for APEX II devices for PPA
configuration.
Table 6–6. PPA Timing Parameters for APEX II Devices (Part 1 of 2)
Note (1)
Symbol
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Min
Max
200
200
Units
ns
tCF2CD
tCF2ST0
tCFG
ns
8
µs
tSTATUS
nSTATUSlow pulse width
10
µs
40 (2)
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August 2005
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JTAG Configuration
Table 6–6. PPA Timing Parameters for APEX II Devices (Part 2 of 2)
Note (1)
Symbol
Parameter
Min
Max
Units
µs
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
tCF2ST1
tCSSU
tCSH
tCF2WS
tDSU
nCONFIGhigh to nSTATUShigh
1 (2)
Chip select setup time before rising edge on nWS
Chip select hold time after rising edge on nWS
nCONFIGhigh to first rising edge on nWS
Data setup time before rising edge on nWS
Data hold time after rising edge on nWS
nWSlow pulse width
10
0
40
10
0
tDH
tWSP
200
tWS2B
tBUSY
tRDY2WS
tWS2RS
tRS2WS
tRSD7
tCD2UM
nWSrising edge to RDYnBSYlow
50
RDYnBSYlow pulse width
0.1
50
1.6
RDYnBSYrising edge to nWSrising edge
nWSrising edge to nRSfalling edge
nRSrising edge to nWSrising edge
nRSfalling edge to DATA7valid with RDYnBSYsignal
CONF_DONEhigh to user mode (3)
200
200
50
8
2
Notes to Table 6–6:
(1) This information is preliminary.
(2) This value is obtainable if users do not delay configuration by extending the nCONFIGor nSTATUSlow pulse
width.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 40 for APEX II devices to obtain this value.
f
Device configuration options and how to create configuration files are
discussed further in Software Settings, chapter 6 and 7 in volume 2 of the
Configuration Handbook.
The Joint Test Action Group (JTAG) has developed a specification for
boundary-scan testing. This boundary-scan test (BST) architecture offers
the capability to efficiently test components on PCBs with tight lead
spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is
operating normally. The JTAG circuitry can also be used to shift
configuration data into the device.
JTAG
Configuration
f
For more information on JTAG boundary-scan testing, refer to
Application Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices.
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August 2005
Configuring APEX II Devices
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. All user I/O pins are tri-stated
during JTAG configuration. APEX II devices are designed such that JTAG
instructions have precedence over any device configuration modes. This
means that JTAG configuration can take place without waiting for other
configuration modes to complete. For example, if you attempt JTAG
configuration of APEX II FPGAs during PS configuration, PS
configuration will be terminated and JTAG configuration will begin.
Table 6–7 explains each JTAG pin’s function.
Table 6–7. JTAG Pin Descriptions
Pin Description
Function
TDI
Test data input
Serial input pin for instructions as well as test and programming data.
Data is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC
.
TDO
TMS
Test data output
Test mode select
Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of
the TAP controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore, TMSmust be set up before
the rising edge of TCK. TMSis evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to VCC
.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
TRST
Test reset input (optional) Active-low input to asynchronously reset the boundary-scan circuit. The
TRSTpin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can
be disabled by connecting this pin to GND.
1
If VCCIO of the bank where the JTAG pins reside, are tied to
3.3-V, both the I/O pins and JTAG TDOport will drive at 3.3-V
levels.
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August 2005
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JTAG Configuration
During JTAG configuration, data can be downloaded to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV header. Configuring devices through a cable is similar to
programming devices in-system, except the TRSTpin should be
connected to VCC. This ensures that the TAP controller is not reset.
Figure 6–29. shows JTAG configuration of a single APEX II device.
Figure 6–29. JTAG Configuration of a Single Device Using a Download Cable
VCC (1)
1 kΩ
(1)
VCC
1 kΩ
VCC (1)
1 kΩ
(1)VCC
1 kΩ
APEX II Device
nCE (4)
TCK
TDO
N.C.
nCE0
GND
TMS
TDI
Download Cable
10-Pin Male Header
(JTAG Mode)
nSTATUS
CONF_DONE
nCONFIG
MSEL0
VCC
(2)
(2)
(2)
(Top View)
TRST
Pin 1
VCC
MSEL1
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 6–29:
(1) The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIOpin),
ByteBlaster II, or ByteBlasterMV cable.
(2) The nCONFIG, MSEL0, and MSEL1pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIGto VCC, and MSEL0and MSEL1to ground.
(3) Pin 6 of the header is a VIOreference voltage for the MasterBlaster output driver. VIOshould match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the
ByteBlasterMV, this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCEwhen it
is used for Active Serial programming, otherwise it is a no connect.
(4) nCEmust be connected to GND or driven low for successful JTAG configuration.
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data from the TDIpin to the TDOpin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDOpin one
clock cycle later.
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Configuration Handbook, Volume 1
Configuring APEX II Devices
APEX II devices have dedicated JTAG pins that always function as JTAG
pins. JTAG testing can be performed on APEX II devices both before and
after configuration, but not during configuration. The chip-wide reset
(DEV_CLRn) and chip-wide output enable (DEV_OE) pins on APEX II
devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of APEX II devices, the
dedicated configuration pins should be considered. Table 6–8 shows how
these pins should be connected during JTAG configuration.
Table 6–8. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
On all APEX II devices in the chain, nCEshould be driven low by connecting it to ground, pulling
it low via a resistor, or driving it by some control circuitry. For devices that are also in multi-device
PS, FPP, or PPA configuration chains, the nCEpins should be connected to GND during JTAG
configuration or JTAG configured in the same order as the configuration chain.
nCEO
MSEL
On all APEX II devices in the chain, nCEOcan be left floating or connected to the nCEof the
next device. See nCEdescription above.
These pins must not be left floating. These pins support whichever non-JTAG configuration is
used in production. If only JTAG configuration is used, you should tie both pins to ground.
nCONFIG
nSTATUS
Driven high by connecting to VCC, pulling high via a resistor, or driven by some control circuitry.
Pull to VCC via a 1-kΩresistor. When configuring multiple devices in the same JTAG chain, each
nSTATUSpin should be pulled up to VCC individually. nSTATUSpulling low in the middle of JTAG
configuration indicates that an error has occurred.
CONF_DONE Pull to VCC via a 1-kΩresistor. When configuring multiple devices in the same JTAG chain, each
CONF_DONEpin should be pulled up to VCC individually. CONF_DONEgoing high at the end of
JTAG configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more convenient on your board.
Should not be left floating. Drive low or high, whichever is more convenient on your board.
DATA0
When programming a JTAG device chain, one JTAG-compatible header is
connected to several devices. The number of devices in the JTAG chain is
limited only by the drive capability of the download cable. When four or
more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMSpins with an on-board buffer.
JTAG-chain device programming is ideal when the system contains
multiple devices, or when testing your system using JTAG BST circuitry.
Figure 6–30 shows multi-device JTAG configuration.
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August 2005
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Configuration Handbook, Volume 1
JTAG Configuration
Figure 6–30. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
(1)
(1)
(1)
(1)
(1)
(1)
VCC
1 kΩ
VCC
1 kΩ
VCC
VCC
VCC
VCC
1 kΩ
(1) VCC
1 kΩ
APEX II Device
1 kΩ
1 kΩ
APEX II Device
APEX II Device
1 kΩ
Pin 1
VCC
(1) VCC
nSTATUS
nCONFIG
MSEL0
MSEL1
nCE (4)
nSTATUS
nCONFIG
MSEL0
MSEL1
nCE (4)
TRST
nSTATUS
nCONFIG
MSEL0
MSEL1
nCE (4)
TRST
TDI
TMS
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1 kΩ
CONF_DONE
CONF_DONE
CONF_DONE
VCC
VCC
VCC
TRST
TDI
TMS
VIO
TDI
TMS
TDO
TCK
TDO
TDO
TCK
(3)
TCK
1 kΩ
Notes to Figure 6–30:
(1) The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIOpin),
ByteBlaster II, or ByteBlasterMV cable.
(2) The nCONFIG, MSEL0, and MSEL1pins should be connected to support a non-JTAG configuration scheme. If only
JTAG configuration is used, connect nCONFIGto VCC, and MSEL0and MSEL1to ground.
(3) Pin 6 of the header is a VIOreference voltage for the MasterBlaster output driver. VIOshould match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV,
this pin is a no connect. In the USB Blaster and ByteBlaster II, this pin is connected to nCEwhen it is used for Active
Serial programming, otherwise it is a no connect.
(4) nCEmust be connected to GND or driven low for successful JTAG configuration.
The nCEpin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, FPP, and PPA configuration chains, the
first device’s nCEpin is connected to GND while its nCEOpin is
connected to nCEof the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEOpin is left floating.
After the first device completes configuration in a multi-device
configuration chain, its nCEOpin drives low to activate the second
device’s nCEpin, which prompts the second device to begin
configuration. Therefore, if these devices are also in a JTAG chain, you
should make sure the nCEpins are connected to GND during JTAG
configuration or that the devices are JTAG configured in the same order
as the configuration chain. As long as the devices are JTAG configured in
the same order as the multi-device configuration chain, the nCEOof the
previous device will drive nCEof the next device low when it has
successfully been JTAG configured.
Other Altera devices that have JTAG support can be placed in the same
JTAG chain for device programming and configuration.
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Configuration Handbook, Volume 1
Configuring APEX II Devices
f
For more information about configuring multiple Altera devices in the
same configuration chain, refer to Configuring Mixed Altera FPGA Chains
in the Configuration Handbook.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the state of
CONF_DONEthrough the JTAG port. If CONF_DONEis not high, the
Quartus II software indicates that configuration has failed. If CONF_DONE
is high, the software indicates that configuration was successful. When
Quartus II generates a JAM file for a multi-device chain, it contains
instructions so that all the devices in the chain will be initialized at the
same time.
Figure 6–31 shows JTAG configuration of an APEX II FPGA with a
microprocessor.
Figure 6–31. JTAG Configuration of a Single Device Using a Microprocessor
Memory
APEX II Device
(3)
DATA
ADDR
nCE
GND
N.C.
V
CC
nCEO
V
(1)
CC
TRST
TDI
TCK
TMS
TDO
V
(1)
CC
1 kΩ
(2)
(2)
(2)
nCONFIG
MSEL0
MSEL1
1 kΩ
Microprocessor
nSTATUS
CONF_DONE
Notes to Figure 6–31:
(1) The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain.
(2) Connect the nCONFIG, MSEL1, and MSEL0pins to support a non-JTAG configuration scheme. If your design only
uses JTAG configuration, connect the nCONFIGpin to VCC and the MSEL1and MSEL0pins to ground.
(3) nCEmust be connected to GND or driven low for successful JTAG configuration.
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-
system programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
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August 2005
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Device Configuration Pins
f
For more information on JTAG and Jam STAPL in embedded
environments, refer to AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the jam player, visit the Altera web site:
www.altera.com/support/software/download/programming/jam/
jam-index.jsp
Configuring APEX II FPGAs with JRunner
JRunner is a software driver that allows you to configure Altera FPGAs,
including APEX II FPGAs, through the ByteBlaster II or ByteBlasterMV
cables in JTAG mode. The programming input file supported is in RBF
format. JRunner also requires a Chain Description File (.cdf) generated by
the Quartus II software. JRunner is targeted for embedded JTAG
configuration. The source code has been developed for the Windows NT
operating system (OS). You can customize the code to make it run on
other platforms.
f
For more information on the JRunner software driver, refer to the
JRunner Software Driver: An Embedded Solution to the JTAG Configuration
White Paper and the source files.
The following tables describe the connections and functionality of all the
configuration related pins on the APEX II device. Table 6–9 describes the
dedicated configuration pins, which are required to be connected
properly on your board for successful configuration. Some of these pins
may not be required for your configuration schemes.
Device
Configuration
Pins
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 1 of 5)
User Configuration
Pin Name
Pin Type
Description
Mode
Scheme
MSEL0
MSEL1
N/A
All
Input
Two-bit configuration input that sets the APEX II device
configuration scheme. See Table 6–3 for the appropriate
connections. These pins must remain at a valid state
during power-up, before nCONFIGis pulled low to initiate
a reconfiguration and during configuration.
VCCSEL
N/A
All
Input
Dedicated input that ensures the configuration related
I/O banks have powered up to the appropriate 1.8-V or
2.5-V/3.3-V voltage levels before starting configuration.
A logic high (1.5 V, 1.8 V, 2.5 V, 3.3 V) means 1.8 V, and
a logic low means 2.5-V/3.3 V.
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Configuring APEX II Devices
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 2 of 5)
User Configuration
Pin Name
Pin Type
Description
Mode
Scheme
nCONFIG
N/A
All
Input
Configuration control input. Pulling this pin low during
user-mode will cause the FPGA to lose its configuration
data, enter a reset state, tri-state all I/O pins, and
returning this pin to a logic high level will initiate a
reconfiguration.
If your configuration scheme uses an enhanced
configuration device or EPC2 device, nCONFIGcan be
tied directly to VCC or to the configuration device’s
nINIT_CONFpin.
nSTATUS
N/A
All
Bidirectional The FPGA drives nSTATUSlow immediately after power-
open-drain up and releases it within 5 µs. (When using a
configuration device, the configuration device holds
nSTATUSlow for up to 200 ms.)
Status output. If an error occurs during configuration,
nSTATUSis pulled low by the target device.
Status input. If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
Driving nSTATUSlow after configuration and initialization
does not affect the configured device. If a configuration
device is used, driving nSTATUSlow will cause the
configuration device to attempt to configure the FPGA,
but since the FPGA ignores transitions on nSTATUSin
user-mode, the FPGA will not reconfigure. To initiate a
reconfiguration, nCONFIGmust be pulled low.
The enhanced configuration devices' and EPC2 devices'
OEand nCSpins have optional internal programmable
pull-up resistors. If internal pull-up resistors are used,
external 1-kΩ pull-up resistors should not be used on
these pins.
CONF_DON
E
N/A
All
Bidirectional Status output. The target FPGA drives the CONF_DONE
open-drain pin low before and during configuration. Once all
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and CONF_DONE
goes high, the target device initializes and enters user
mode.
Driving CONF_DONElow after configuration and
initialization does not affect the configured device.
The enhanced configuration devices' and EPC2 devices'
OEand nCSpins have optional internal programmable
pull-up resistors. If internal pull-up resistors are used,
external 1-kΩ pull-up resistors should not be used on
these pins.
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Device Configuration Pins
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 3 of 5)
User Configuration
Pin Name
Pin Type
Description
Mode
Scheme
nCE
N/A
All
Input
Active-low chip enable. The nCEpin activates the device
with a low signal to allow configuration. The nCEpin must
be held low during configuration, initialization, and user
mode. In single device configuration, it should be tied
low. In multi-device configuration, nCEof the first device
is tied low while its nCEOpin is connected to nCEof the
next device in the chain.
The nCEpin must also be held low for successful JTAG
programming of the FPGA.
nCEO
DCLK
N/A
All
Output
Input
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device's nCEpin. The nCEOof the last device in the
chain is left floating.
N/A Synchronous
configuration
schemes (PS
and FPP)
Clock input used to clock data from an external source
into the target device. Data is latched into the FPGA on
the rising edge of DCLK.
In PPA mode, DCLKshould be tied high to VCC to prevent
this pin from floating.
After configuration, this pin is tri-stated. In schemes that
use a configuration device, DCLKwill be driven low after
configuration is done. In schemes that use a control host,
DCLKshould be driven either high or low, whichever is
more convenient. Toggling this pin after configuration
does not affect the configured device.
DATA0
N/A
All
Input
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on
the DATA0pin.
After configuration, EPC1 and EPC1441 devices tri-state
this pin, while EPC2 devices drive this pin high. In
schemes that use a control host, DATA0should be
driven either high or low, whichever is more convenient.
Toggling this pin after configuration does not affect the
configured device.
DATA[7..1]
I/O
Parallel
configuration
schemes
(FPP and
PPA)
Inputs
Data inputs. Byte-wide configuration data is presented to
the target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tri-
stated.
After PPA or FPP configuration, DATA[7..1]are
available as a user I/O pins and the state of these pin
depends on the Dual-Purpose Pin settings.
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Configuring APEX II Devices
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 4 of 5)
User Configuration
Pin Name
Pin Type
Description
Mode
Scheme
DATA7
I/O
PPA
Bidirectional In the PPA configuration scheme, the DATA7pin
presents the RDYnBSYsignal after the nRSsignal has
been strobed low.
In serial configuration schemes, it functions as a user I/O
during configuration, which means it is tri-stated.
After PPA configuration, DATA7is available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
nWS
nRS
I/O
I/O
PPA
PPA
Input
Input
Write strobe input. A low-to-high transition causes the
device to latch a byte of data on the DATA[7..0]pins.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nWSis available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
Read strobe input. A low input directs the device to drive
the RDYnBSYsignal on the DATA7pin.
If the nRSpin is not used in PPA mode, it should be tied
high.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nRSis available as a user I/O
and the state of this pin depends on the Dual-Purpose
Pin settings.
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Device Configuration Pins
Table 6–9. Dedicated Configuration Pins on the APEX II Device (Part 5 of 5)
User Configuration
Pin Name
Pin Type
Description
Mode
Scheme
RDYnBSY
I/O
PPA
Output
Ready output. A high output indicates that the target
device is ready to accept another data byte. A low output
indicates that the target device is busy and not ready to
receive another data byte.
In PPA configuration schemes, this pin will drive out high
after power-up, before configuration and after
configuration before entering user-mode.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, RDYnBSYis available as a user
I/O and the state of this pin depends on the dual-purpose
pin settings.
nCS/CS
I/O
PPA
Input
Chip-select inputs. A low on nCSand a high on CSselect
the target device for configuration. The nCSand CSpins
must be held active during configuration and
initialization.
During the PPA configuration mode, it is only required to
use either the nCSor CSpin. Therefore, if only one chip-
select input is used, the other must be tied to the active
state. For example, nCScan be tied to ground while CS
is toggled to control configuration.
In non-PPA schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nCSand CSare available as a
user I/O pins and the state of these pins depends on the
dual-purpose pin settings.
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Configuring APEX II Devices
Table 6–10 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration they function as user I/O pins, which means they are tri-
stated with weak pull-up resistors.
Table 6–10. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is on. I/O if
option is off.
Input
Optional user-supplied clock input.
Synchronizes the initialization of one or
more devices. This pin is enabled by turning
on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software
INIT_DONE
N/A if option is on. I/O if
option is off.
Output open-drain Status pin. Can be used to indicate when
the device has initialized and is in user
mode. When nCONFIGis low and during the
beginning of configuration, the INIT_DONE
pin is tri-stated and pulled high due to an
external 1-kΩ pull-up resistor. Once the
option bit to enable INIT_DONEis
programmed into the device (during the first
frame of configuration data), the
INIT_DONEpin will go low. When
initialization is complete, the INIT_DONE
pin will be released and pulled high and the
FPGA enters user mode. Thus, the
monitoring circuitry must be able to detect a
low-to-high transition. This pin is enabled by
turning on the Enable INIT_DONE output
option in the Quartus II software.
DEV_OE
N/A if option is on. I/O if
option is off.
Input
Input
Optional pin that allows the user to override
all tri-states on the device. When this pin is
driven low, all I/O pins are tri-stated; when
this pin is driven high, all I/O pins behave as
programmed. This pin is enabled by turning
on the Enable device-wide output enable
(DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if option is on. I/O if
option is off.
Optional pin that allows you to override all
clears on all device registers. When this pin
is driven low, all registers are cleared; when
this pin is driven high, all registers behave
as programmed. This pin is enabled by
turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II
software.
Altera Corporation
August 2005
6–67
Configuration Handbook, Volume 1
Device Configuration Pins
JTAG pins must be kept stable before and during configuration. JTAG pin
stability prevents accidental loading of JTAG instructions. Table 6–11
describes the dedicated JTAG pins.
Table 6–11. Dedicated JTAG Pins
Pin Name User Mode Pin Type
Description
TDI
N/A
Input
Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to VCC
.
TDO
N/A
Output Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is
not being shifted out of the device.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. Transitions within the state machine occur on
the rising edge of TCK. Therefore, TMSmust be set up before the rising
edge of TCK. TMSis evaluated on the rising edge of TCK.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to VCC
.
TCK
N/A
N/A
Input
Input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to GND.
TRST
Active-low input to asynchronously reset the boundary-scan circuit. The
TRSTpin is optional according to IEEE Std. 1149.1.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting this pin to GND.
6–68
Altera Corporation
August 2005
Configuration Handbook, Volume 1
相关型号：
EP2A40F1020C7N
Loadable PLD, 1.55ns, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FINE LINE, BGA-1020
ALTERA
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