EP3C10F256A7 [INTEL]
Field Programmable Gate Array, 10320 CLBs, 10320-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256;
| 型号： | EP3C10F256A7 |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 10320 CLBs, 10320-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256 栅 |
| 文件： | 总348页 (文件大小：7163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Cyclone III Device Handbook Volume 1
Cyclone III Device Handbook
Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document last updated for Altera Complete Design Suite version:
Document publication date:
12.0
August 2012
CIII5V1-4.2
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
ISO
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Section I. Device Core
Chapter 1. Cyclone III Device Family Overview
Cyclone III Device Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Lowest Power FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Design Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Increased System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Cyclone III Device Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Logic Elements and Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Embedded Multipliers and Digital Signal Processing Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Clock Networks and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Support for Industry-Standard Embedded Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Hot Socketing and Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
SEU Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
JTAG Boundary Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Design Security (Cyclone III LS Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13
Chapter 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
LE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
LE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Chapter 3. Memory Blocks in the Cyclone III Device Family
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Mixed-Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
iv
Contents
Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Single-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Shift Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
FIFO Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
I/O Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Read or Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Single-Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Read-During-Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Chapter 4. Embedded Multipliers in the Cyclone III Device Family
Embedded Multiplier Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Multiplier Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
18-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
9-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Chapter 5. Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
GCLK Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
GCLK Network Clock Source Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
GCLK Network Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
clkena Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
PLLs in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Cyclone III Device Family PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
External Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Source-Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
No Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
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August 2012 Altera Corporation
Contents
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pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Manual Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21
Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
Phase Shift Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
PLL Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26
PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26
Post-Scale Counters (C0 to C4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28
Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29
Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
Bypassing PLL Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31
Dynamic Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31
Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34
Section II. I/O Interfaces
Chapter 6. I/O Features in the Cyclone III Device Family
Cyclone III Device Family I/O Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
I/O Element Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
PCI-Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
LVDS Transmitter Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
On-Chip Series Termination Without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Termination Scheme for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Voltage-Referenced I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Differential I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
External Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Pad Placement and DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Pad Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
vi
Contents
Chapter 7. High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
High-Speed I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
LVDS I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
Designing with LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
BLVDS I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
Designing with BLVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family . . . . . . . . . 7–10
Designing with RSDS, Mini-LVDS, and PPDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
LVPECL I/O Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
Differential SSTL I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . 7–13
Differential HSTL I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . 7–14
True Output Buffer Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15
Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15
High-Speed I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16
Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17
Differential Pad Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17
Board Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17
Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19
Chapter 8. External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Data and Data Clock/Strobe Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Optional Parity, DM, and Error Correction Coding Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Address and Control/Command Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Memory Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Cyclone III Device Family Memory Interfaces Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
DDR Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
DDR Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12
OCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
Section III. System Integration
Chapter 9. Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device
Family
Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
Configuration Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
Configuration File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
Configuration and JTAG Pin I/O Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9
Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
Configuration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
AS Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
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August 2012 Altera Corporation
Contents
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Single-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13
Multi-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
Configuring Multiple Cyclone III Device Family with the Same Design . . . . . . . . . . . . . . . . . . . 9–16
Guidelines for Connecting Serial Configuration Device to Cyclone III Device Family on AS
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20
Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21
AP Configuration (Supported Flash Memories) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23
AP Configuration Supported Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24
Single-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25
Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–27
Byte-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28
Word-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29
Guidelines for Connecting Parallel Flash to Cyclone III Devices for the AP Interface . . . . . . . . 9–30
Configuring With Multiple Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–30
Estimating the AP Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–32
Programming Parallel Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–33
PS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–34
PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–35
PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–38
PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–40
FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–42
FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–43
FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–47
JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–48
Configuring Cyclone III Device Family with Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–55
Configuring Cyclone III Device Family with the JRunner Software Driver . . . . . . . . . . . . . . . . . 9–56
Combining JTAG and AS Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–56
Programming Serial Configuration Devices In-System Using the JTAG Interface . . . . . . . . . . . 9–58
JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–60
Changing the Start Boot Address of the AP Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–64
Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–64
Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–70
Cyclone III LS Design Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–70
Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71
Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71
Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71
AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71
Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71
Cyclone III LS Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–72
Available Security Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–73
Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–73
No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–74
FACTORY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–74
Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–74
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–75
Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–76
Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–77
Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–77
Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–77
Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–80
Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–81
Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–84
User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–85
Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–86
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
viii
Contents
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–86
Chapter 10. Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
Devices Driven Before Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
I/O Pins Remain Tristated During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
Hot-Socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
POR Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4
Chapter 11. SEU Mitigation in the Cyclone III Device Family
Error Detection Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Automated SEU Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4
Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4
Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5
Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7
Accessing Error Detection Block Through User Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8
Recovering from CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10
Chapter 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
IEEE Std. 1149.1 BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1
IEEE Std. 1149.1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2
I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5
Guidelines for IEEE Std. 1149.1 BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6
Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
Chapter Revision Dates
The chapters in this document, Cyclone III Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1. Cyclone III Device Family Overview
Revised: July 2012
Part Number: CIII51001-2.4
Chapter 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51002-2.3
Chapter 3. Memory Blocks in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51004-2.3
Chapter 4. Embedded Multipliers in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51005-2.3
Chapter 5. Clock Networks and PLLs in the Cyclone III Device Family
Revised:
July 2012
Part Number: CIII51006-4.1
Chapter 6. I/O Features in the Cyclone III Device Family
Revised:
July 2012
Part Number: CIII51007-3.4
Chapter 7. High-Speed Differential Interfaces in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51008-4.0
Chapter 8. External Memory Interfaces in the Cyclone III Device Family
Revised:
July 2012
Part Number: CIII51009-3.1
Chapter 9. Configuration, Design Security, and Remote System Upgrades in the Cyclone III De-
vice Family
Revised:
August 2012
Part Number: CIII51016-2.2
Chapter 10. Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Revised:
July 2012
Part Number: CIII51011-3.4
Chapter 11. SEU Mitigation in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51013-2.3
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
x
Chapter Revision Dates
Chapter 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
Revised: December 2011
Part Number: CIII51014-2.3
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
Section I. Device Core
This section provides a complete overview of all features relating to the Cyclone® III
device family.
This section includes the following chapters:
■
Chapter 1, Cyclone III Device Family Overview
■
Chapter 2, Logic Elements and Logic Array Blocks in the Cyclone III Device
Family
■
■
■
Chapter 3, Memory Blocks in the Cyclone III Device Family
Chapter 4, Embedded Multipliers in the Cyclone III Device Family
Chapter 5, Clock Networks and PLLs in the Cyclone III Device Family
f
For information about the revision history for chapters in this section, refer to
“Document Revision History” in each individual chapter.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
I–2
Section I: Device Core
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
1. Cyclone III Device Family Overview
July 2012
CIII51001-2.4
CIII51001-2.4
Cyclone® III device family offers a unique combination of high functionality, low
power and low cost. Based on Taiwan Semiconductor Manufacturing Company
(TSMC) low-power (LP) process technology, silicon optimizations and software
features to minimize power consumption, Cyclone III device family provides the ideal
solution for your high-volume, low-power, and cost-sensitive applications. To address
the unique design needs, Cyclone III device family offers the following two variants:
■
Cyclone III—lowest power, high functionality with the lowest cost
Cyclone III LS—lowest power FPGAs with security
■
With densities ranging from about 5,000 to 200,000 logic elements (LEs) and
0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power
consumption, Cyclone III device family makes it easier for you to meet your power
budget. Cyclone III LS devices are the first to implement a suite of security features at
the silicon, software, and intellectual property (IP) level on a low-power and
high-functionality FPGA platform. This suite of security features protects the IP from
tampering, reverse engineering and cloning. In addition, Cyclone III LS devices
support design separation which enables you to introduce redundancy in a single
chip to reduce size, weight, and power of your application.
This chapter contains the following sections:
■
■
■
“Cyclone III Device Family Features” on page 1–1
“Cyclone III Device Family Architecture” on page 1–6
“Reference and Ordering Information” on page 1–12
Cyclone III Device Family Features
Cyclone III device family offers the following features:
Lowest Power FPGAs
■
Lowest power consumption with TSMC low-power process technology and
Altera® power-aware design flow
■
Low-power operation offers the following benefits:
■
■
■
Extended battery life for portable and handheld applications
Reduced or eliminated cooling system costs
Operation in thermally-challenged environments
■
Hot-socketing operation support
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
July 2012
Subscribe
1–2
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Design Security Feature
Cyclone III LS devices offer the following design security features:
■
Configuration security using advanced encryption standard (AES) with 256-bit
volatile key
■
Routing architecture optimized for design separation flow with the Quartus® II
software
■
Design separation flow achieves both physical and functional isolation
between design partitions
■
■
Ability to disable external JTAG port
Error Detection (ED) Cycle Indicator to core
■
Provides a pass or fail indicator at every ED cycle
■
Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
■
■
Ability to perform zeroization to clear contents of the FPGA logic, CRAM,
embedded memory, and AES key
Internal oscillator enables system monitor and health check capabilities
Increased System Integration
■
High memory-to-logic and multiplier-to-logic ratio
■
High I/O count, low-and mid-range density devices for user I/O constrained
applications
■
Adjustable I/O slew rates to improve signal integrity
■
Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,
LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
■
Supports the multi-value on-chip termination (OCT) calibration feature to
eliminate variations over process, voltage, and temperature (PVT)
■
Four phase-locked loops (PLLs) per device provide robust clock management and
synthesis for device clock management, external system clock management, and
I/O interfaces
■
■
■
Five outputs per PLL
Cascadable to save I/Os, ease PCB routing, and reduce jitter
Dynamically reconfigurable to change phase shift, frequency multiplication or
division, or both, and input frequency in the system without reconfiguring the
device
■
■
Remote system upgrade without the aid of an external controller
Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
■
Nios® II embedded processor for Cyclone III device family, offering low cost and
custom-fit embedded processing solutions
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
1–3
Cyclone III Device Family Features
■
■
Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
■
Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
Table 1–1 lists Cyclone III device family features.
Table 1–1. Cyclone III Device Family Features
Number of
Global
Clock
Networks
Logic
Elements
Total RAM
Bits
18 x 18
Multipliers
Maximum
User I/Os
Family
Device
M9K
PLLs
Blocks
EP3C5
EP3C10
5,136
10,320
15,408
24,624
39,600
55,856
81,264
119,088
70,208
100,448
150,848
198,464
46
46
423,936
423,936
23
23
2
2
4
4
4
4
4
4
4
4
4
4
10
10
20
20
20
20
20
20
20
20
20
20
182
182
346
215
535
377
429
531
429
429
429
429
EP3C16
56
516,096
56
EP3C25
66
608,256
66
Cyclone III
EP3C40
126
260
305
432
333
483
666
891
1,161,216
2,396,160
2,810,880
3,981,312
3,068,928
4,451,328
6,137,856
8,211,456
126
156
244
288
200
276
320
396
EP3C55
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III
LS
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
1–4
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Table 1–2 lists Cyclone III device family package options, I/O pins, and differential
channel counts.
(1), (2), (3), (4), (5)
Table 1–2. Cyclone III Device Family Package Options, I/O pin and Differential Channel Counts
(7)
Family
Package E144
M164
P240
—
F256
U256
F324
—
F484
—
U484
—
F780
—
EP3C5
EP3C10
94, 22 106, 28
94, 22 106, 28
182, 68 182, 68
182, 68 182, 68
—
—
—
—
—
EP3C16
84, 19 92, 23 160, 47 168, 55 168, 55
—
346, 140 346, 140
—
EP3C25
82, 18
—
—
—
—
—
—
—
—
—
—
148, 43 156, 54 156, 54 215, 83
—
—
—
Cyclone III
(8)
EP3C40
128, 26
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
195, 61 331, 127 331, 127 535, 227 (6)
EP3C55
—
—
—
—
—
—
—
—
327, 135 327, 135
295, 113 295, 113
377, 163
429, 181
531, 233
429, 181
429, 181
429, 181
429, 181
EP3C80
—
—
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
—
—
283, 106
—
—
—
294, 113 294, 113
294, 113 294, 113
—
—
Cyclone III
LS
—
—
226, 87
226, 87
—
—
—
—
Notes to Table 1–2:
(1) For each device package, the first number indicates the number of the I/O pin; the second number indicates the differential channel count.
(2) For more information about device packaging specifications, refer to the Cyclone III Package and Thermal Resistance webpage.
(3) The I/O pin numbers are the maximum I/O counts (including clock input pins) supported by the device package combination and can be affected
by the configuration scheme selected for the device.
(4) All packages are available in lead-free and leaded options.
(5) Vertical migration is not supported between Cyclone III and Cyclone III LS devices.
(6) The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/Os are restricted to 510 I/Os if you enable
migration to the EP3C120 and are using voltage referenced I/O standards. If you are not using voltage referenced I/O standards, you can increase
the maximum number of I/Os.
(7) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground
plane on your PCB. Use this exposed pad for electrical connectivity and not for thermal purposes.
(8) All Cyclone III device UBGA packages are supported by the Quartus II software version 7.1 SP1 and later, with the exception of the UBGA
packages of EP3C16, which are supported by the Quartus II software version 7.2.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
1–5
Cyclone III Device Family Features
Table 1–3 lists Cyclone III device family package sizes.
Table 1–3. Cyclone III Device Family Package Sizes
Family
Package
E144
M164
P240
F256
Pitch (mm)
0.5
Nominal Area (mm2) Length x Width (mm mm) Height (mm)
484
64
22 22
8 8
1.60
1.40
4.10
1.55
2.20
2.20
2.60
2.20
2.60
2.60
2.20
2.60
0.5
0.5
1197
289
196
361
529
361
841
529
361
841
34.6 34.6
17 17
14 14
19 19
23 23
19 19
29 29
23 23
19 19
29 29
1.0
Cyclone III
U256
F324
0.8
1.0
F484
1.0
U484
F780
0.8
1.0
F484
1.0
Cyclone III LS
U484
F780
0.8
1.0
Table 1–4 lists Cyclone III device family speed grades.
Table 1–4. Cyclone III Device Family Speed Grades (Part 1 of 2)
Family
Device
E144
C7,C8, C7, C8,
I7, A7 I7
C7,C8, C7, C8,
I7, A7 I7
C7,C8, C7, C8,
M164
P240
F256
U256
F324
F484
U484
F780
C6, C7,
C6, C7,
EP3C5
—
—
—
—
—
C8, I7, A7 C8, I7, A7
C6, C7, C6, C7,
C8, I7, A7 C8, I7, A7
C6, C7, C6, C7,
C8, I7, A7 C8, I7, A7
C6, C7, C6, C7,
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
—
C8
C8
C8
—
—
—
—
—
—
—
—
C6, C7,
C8, I7, A7 C8, I7, A7
C6, C7,
—
I7, A7
I7
C7,C8,
I7, A7
C6, C7,
—
—
—
—
C8, I7, A7 C8, I7, A7 C8, I7, A7
Cyclone III
C6, C7,
C6, C7,
C6, C7,
C6, C7,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C8, I7, A7 C8, I7, A7 C8, I7, A7 C8, I7
C6, C7,
C8, I7
C6, C7,
C8, I7
C6, C7,
C8, I7
—
—
—
C6, C7,
C8, I7
C6, C7,
C8, I7
C6, C7,
C8, I7
C7, C8,
I7
C7, C8, I7
—
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
1–6
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
Table 1–4. Cyclone III Device Family Speed Grades (Part 2 of 2)
Family
Device
E144
M164
P240
F256
U256
F324
F484
U484
F780
C7, C8,
I7
EP3CLS70
—
—
—
—
—
—
C7, C8, I7 C7, C8, I7
C7, C8, I7 C7, C8, I7
C7, C8,
I7
EP3CLS100
EP3CLS150
EP3CLS200
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cyclone III
LS
C7, C8,
I7
C7, C8, I7
C7, C8, I7
—
—
C7, C8,
I7
Table 1–5 lists Cyclone III device family configuration schemes.
Table 1–5. Cyclone III Device Family Configuration Schemes
Configuration Scheme
Active serial (AS)
Cyclone III
Cyclone III LS
v
v
v
v
v
v
—
v
v
v
Active parallel (AP)
Passive serial (PS)
Fast passive parallel (FPP)
Joint Test Action Group (JTAG)
Cyclone III Device Family Architecture
Cyclone III device family includes a customer-defined feature set that is optimized for
portable applications and offers a wide range of density, memory, embedded
multiplier, and I/O options. Cyclone III device family supports numerous external
memory interfaces and I/O protocols that are common in high-volume applications.
The Quartus II software features and parameterizable IP cores make it easier for you
to use the Cyclone III device family interfaces and protocols.
The following sections provide an overview of the Cyclone III device family features.
Logic Elements and Logic Array Blocks
The logic array block (LAB) consists of 16 logic elements and a LAB-wide control
block. An LE is the smallest unit of logic in the Cyclone III device family architecture.
Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic.
The four-input LUT is a function generator that can implement any function with four
variables.
f
For more information about LEs and LABs, refer to the Logic Elements and Logic Array
Blocks in the Cyclone III Device Family chapter.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
1–7
Cyclone III Device Family Architecture
Memory Blocks
Each M9K memory block of the Cyclone III device family provides nine Kbits of
on-chip memory capable of operating at up to 315 MHz for Cyclone III devices and up
to 274 MHz for Cyclone III LS devices. The embedded memory structure consists of
M9K memory blocks columns that you can configure as RAM, first-in first-out (FIFO)
buffers, or ROM. The Cyclone III device family memory blocks are optimized for
applications such as high throughout packet processing, embedded processor
program, and embedded data storage.
The Quartus II software allows you to take advantage of the M9K memory blocks by
instantiating memory using a dedicated megafunction wizard or by inferring memory
directly from the VHDL or Verilog source code.
M9K memory blocks support single-port, simple dual-port, and true dual-port
operation modes. Single-port mode and simple dual-port mode are supported for all
port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36. True
dual-port is supported in port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16,
and ×18.
f
For more information about memory blocks, refer to the Memory Blocks in the Cyclone
III Device Family chapter.
Embedded Multipliers and Digital Signal Processing Support
Cyclone III devices support up to 288 embedded multiplier blocks and Cyclone III LS
devices support up to 396 embedded multiplier blocks. Each block supports one
individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.
The Quartus II software includes megafunctions that are used to control the operation
mode of the embedded multiplier blocks based on user parameter settings.
Multipliers can also be inferred directly from the VHDL or Verilog source code. In
addition to embedded multipliers, Cyclone III device family includes a combination
of on-chip resources and external interfaces, making them ideal for increasing
performance, reducing system cost, and lowering the power consumption of digital
signal processing (DSP) systems. You can use Cyclone III device family alone or as
DSP device co-processors to improve price-to-performance ratios of DSP systems.
The Cyclone III device family DSP system design support includes the following
features:
■
DSP IP cores:
■
■
Common DSP processing functions such as finite impulse response (FIR), fast
Fourier transform (FFT), and numerically controlled oscillator (NCO) functions
Suites of common video and image processing functions
■
■
Complete reference designs for end-market applications
DSP Builder interface tool between the Quartus II software and the MathWorks
Simulink and MATLAB design environments
■
DSP development kits
f
For more information about embedded multipliers and digital signal processing
support, refer to the Embedded Multipliers in Cyclone III Devices chapter.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
1–8
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
Clock Networks and PLLs
Cyclone III device family includes 20 global clock networks. You can drive global
clock signals from dedicated clock pins, dual-purpose clock pins, user logic, and
PLLs. Cyclone III device family includes up to four PLLs with five outputs per PLL to
provide robust clock management and synthesis. You can use PLLs for device clock
management, external system clock management, and I/O interfaces.
You can dynamically reconfigure the Cyclone III device family PLLs to enable
auto-calibration of external memory interfaces while the device is in operation. This
feature enables the support of multiple input source frequencies and corresponding
multiplication, division, and phase shift requirements. PLLs in Cyclone III device
family may be cascaded to generate up to ten internal clocks and two external clocks
on output pins from a single external clock source.
f
For more PLL specifications and information, refer to the Cyclone III Device Data Sheet,
Cyclone III LS Device Data Sheet, and Clock Networks and PLLs in the Cyclone III Device
Family chapters.
I/O Features
Cyclone III device family has eight I/O banks. All I/O banks support single-ended
and differential I/O standards listed in Table 1–6.
Table 1–6. Cyclone III Device Family I/O Standards Support
Type
Single-Ended I/O
Differential I/O
I/O Standard
LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X
SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
The Cyclone III device family I/O also supports programmable bus hold,
programmable pull-up resistors, programmable delay, programmable drive strength,
programmable slew-rate control to optimize signal integrity, and hot socketing.
Cyclone III device family supports calibrated on-chip series termination (RS OCT) or
driver impedance matching (Rs) for single-ended I/O standards, with one OCT
calibration block per side.
f
For more information, refer to the I/O Features in the Cyclone III Device Family chapter.
High-Speed Differential Interfaces
Cyclone III device family supports high-speed differential interfaces such as BLVDS,
LVDS, mini-LVDS, RSDS, and PPDS. These high-speed I/O standards in Cyclone III
device family provide high data throughput using a relatively small number of I/O
pins and are ideal for low-cost applications. Dedicated differential output drivers on
the left and right I/O banks can send data rates at up to 875 Mbps for Cyclone III
devices and up to 740 Mbps for Cyclone III LS devices, without the need for external
resistors. This saves board space or simplifies PCB routing. Top and bottom I/O banks
support differential transmission (with the addition of an external resistor network)
data rates at up to 640 Mbps for both Cyclone III and Cyclone III LS devices.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
1–9
Cyclone III Device Family Architecture
f
For more information, refer to the High-Speed Differential Interfaces in the Cyclone III
Device Family chapter.
Auto-Calibrating External Memory Interfaces
Cyclone III device family supports common memory types such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM. DDR2 SDRAM memory interfaces support data
rates up to 400 Mbps for Cyclone III devices and 333 Mbps for Cyclone III LS devices.
Memory interfaces are supported on all sides of Cyclone III device family. Cyclone III
device family has the OCT, DDR output registers, and 8-to-36-bit programmable DQ
group widths features to enable rapid and robust implementation of different
memory standards.
An auto-calibrating megafunction is available in the Quartus II software for DDR and
QDR memory interface PHYs. This megafunction is optimized to take advantage of
the Cyclone III device family I/O structure, simplify timing closure requirements, and
take advantage of the Cyclone III device family PLL dynamic reconfiguration feature
to calibrate PVT changes.
f
For more information, refer to the External Memory Interfaces in the Cyclone III Device
Family chapter.
Support for Industry-Standard Embedded Processors
To quickly and easily create system-level designs using Cyclone III device family, you
can select among the ×32-bit soft processor cores: Freescale®V1 Coldfire, ARM®
Cortex M1, or Altera Nios® II, along with a library of 50 other IP blocks when using
the system-on-a-programmable-chip (SOPC) Builder tool. SOPC Builder is an Altera
Quartus II design tool that facilitates system-integration of IP blocks in an FPGA
design. The SOPC Builder automatically generates interconnect logic and creates a
testbench to verify functionality, saving valuable design time.
Cyclone III device family expands the peripheral set, memory, I/O, or performance of
legacy embedded processors. Single or multiple Nios II embedded processors are
designed into Cyclone III device family to provide additional co-processing power, or
even replace legacy embedded processors in your system. Using the Cyclone III
device family and Nios II together provide low-cost, high-performance embedded
processing solutions, which in turn allow you to extend the life cycle of your product
and improve time-to-market over standard product solutions.
1
Separate licensing of the Freescale and ARM embedded processors are required.
Hot Socketing and Power-On-Reset
Cyclone III device family features hot socketing (also known as hot plug-in or hot
swap) and power sequencing support without the use of external devices. You can
insert or remove a board populated with one or more Cyclone III device family
during a system operation without causing undesirable effects to the running system
bus or the board that was inserted into the system.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
1–10
Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
The hot socketing feature allows you to use FPGAs on PCBs that also contain a
mixture of 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. The Cyclone III device family
hot socketing feature eliminates power-up sequence requirements for other devices
on the board for proper FPGA operation.
f
For more information about hot socketing and power-on-reset, refer to the
Hot-Socketing and Power-on Reset in the Cyclone III Device Family chapter.
SEU Mitigation
Cyclone III LS devices offer built-in error detection circuitry to detect data corruption
due to soft errors in the CRAM cells. This feature allows CRAM contents to be read
and verified to match a configuration-computed CRC value. The Quartus II software
activates the built-in 32-bit CRC checker, which is part of the Cyclone III LS device.
f
For more information about SEU mitigation, refer to the SEU Mitigation in the
Cyclone III Device Family chapter.
JTAG Boundary Scan Testing
Cyclone III device family supports the JTAG IEEE Std. 1149.1 specification. The
boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and captures functional data while a device is
operating normally. Boundary-scan cells in the Cyclone III device family can force
signals onto pins or capture data from pins or from logic array signals. Forced test
data is serially shifted into the boundary-scan cells. Captured data is serially shifted
out and externally compared to expected results. In addition to BST, you can use the
IEEE Std. 1149.1 controller for the Cyclone III LS device in-circuit reconfiguration
(ICR).
f
For more information about JTAG boundary scan testing, refer to the IEEE 1149.1
(JTAG) Boundary-Scan Testing for the Cyclone III Device Family chapter.
Quartus II Software Support
The Quartus II software is the leading design software for performance and
productivity. It is the only complete design solution for CPLDs, FPGAs, and ASICs in
the industry. The Quartus II software includes an integrated development
environment to accelerate system-level design and seamless integration with leading
third-party software tools and flows.
The Cyclone III LS devices provide both physical and functional separation between
security critical design partitions. Cyclone III LS devices offer isolation between
design partitions. This ensures that device errors do not propagate from one partition
to another, whether unintentional or intentional. The Quartus II software design
separation flow facilitates the creation of separation regions in Cyclone III LS devices
by tightly controlling the routing in and between the LogicLock regions. For ease of
use, the separation flow integrates in the existing incremental compilation flow.
f
For more information about the Quartus II software features, refer to the Quartus II
Handbook.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
1–11
Cyclone III Device Family Architecture
Configuration
Cyclone III device family uses SRAM cells to store configuration data. Configuration
data is downloaded to Cyclone III device family each time the device powers up.
Low-cost configuration options include the Altera EPCS family serial flash devices as
well as commodity parallel flash configuration options. These options provide the
flexibility for general-purpose applications and the ability to meet specific
configuration and wake-up time requirements of the applications. Cyclone III device
family supports the AS, PS, FPP, and JTAG configuration schemes. The AP
configuration scheme is only supported in Cyclone III devices.
f
For more information about configuration, refer to the Configuration, Design Security,
and Remote System Upgrades in the Cyclone III Device Family chapter.
Remote System Upgrades
Cyclone III device family offers remote system upgrade without an external
controller. The remote system upgrade capability in Cyclone III device family allows
system upgrades from a remote location. Soft logic (either the Nios II embedded
processor or user logic) implemented in Cyclone III device family can download a
new configuration image from a remote location, store it in configuration memory,
and direct the dedicated remote system upgrade circuitry to start a reconfiguration
cycle. The dedicated circuitry performs error detection during and after the
configuration process, and can recover from an error condition by reverting to a safe
configuration image. The dedicated circuitry also provides error status information.
Cyclone III devices support remote system upgrade in the AS and AP configuration
scheme. Cyclone III LS devices support remote system upgrade in the AS
configuration scheme only.
f
For more information, refer to the Configuration, Design Security, and Remote System
Upgrades in the Cyclone III Device Family chapter.
Design Security (Cyclone III LS Devices Only)
Cyclone III LS devices offer design security features which play a vital role in the large
and critical designs in the competitive military and commercial environments.
Equipped with the configuration bit stream encryption and anti-tamper features,
Cyclone III LS devices protect your designs from copying, reverse engineering and
tampering. The configuration security of Cyclone III LS devices uses AES with 256-bit
security key.
f
For more information, refer to the Configuration, Design Security, and Remote System
Upgrades in Cyclone III Device Family chapter.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
1–12
Chapter 1: Cyclone III Device Family Overview
Reference and Ordering Information
Reference and Ordering Information
Figure 1–1 and Figure 1–2 show the ordering codes for Cyclone III and Cyclone III LS
devices.
Figure 1–1. Cyclone III Device Packaging Ordering Information
PackageType
E
Q
F
: Plastic Enhanced Quad Flat Pack (EQFP)
: Plastic Quad Flat Pack (PQFP)
OperatingTemperature
: FineLine Ball-Grid Array (FBGA)
: Ultra FineLine Ball-Grid Array (UBGA)
: Micro FineLine Ball-Grid Array (MBGA)
C
I
: Commercial temperature (TJ = 0° C to 85° C)
: Industrial temperature (TJ = -40° C to 100° C)
: Automotive temperature (TJ = -40° C to 125° C)
U
M
A
Family Signature
EP3C: Cyclone III
Optional Suffix
Indicates specific device
options or shipment method
EP3C 25
F
324
C
7
N
Package Code
Member Code
N
: Lead-free packaging
ES : Engineering sample
144 : 144 pins
164 : 164 pins
240 : 240 pins
256 : 256 pins
324 : 324 pins
484 : 484 pins
780 : 780 pins
5
: 5,136 logic elements
10 : 10,320 logic elements
16 : 15,408 logic elements
25 : 24,624 logic elements
25E : 24,624 logic elements
40 : 39,600 logic elements
55 : 55,856 logic elements
80 : 81,264 logic elements
120 : 119,088 logic elements
Speed Grade
6 (fastest)
7
8
Figure 1–2. Cyclone III LS Device Packaging Ordering Information
PackageType
OperatingTemperature
F
: FineLine Ball-Grid Array (FBGA)
: Ultra FineLine Ball-Grid Array (UBGA)
C
I
: Commercial temperature (TJ = 0° C to 85° C)
: Industrial temperature (TJ = -40° C to 100° C)
U
Family Signature
Optional Suffix
Indicates specific device
options or shipment method
EP3CLS
70
F
484
C
7
N
EP3CLS : Cyclone III LS
Package Code
Member Code
N
: Lead-free packaging
ES : Engineering sample
484 : 484 pins
780 : 780 pins
70 : 70,208 logic elements
100 : 100,448 logic elements
150 : 150,848 logic elements
200 : 198,464 logic elements
Speed Grade
7 (fastest)
8
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Family Overview
1–13
Document Revision History
Document Revision History
Table 1–7 lists the revision history for this document.
Table 1–7. Document Revision History
Date
July 2012
Version
Changes
Updated 484 pin package code in Figure 1–1.
2.4
■ Updated Table 1–1 and Table 1–2.
■ Updated Figure 1–1 and Figure 1–2.
■ Updated hyperlinks.
December 2011
2.3
■ Minor text edits.
December 2009
July 2009
2.2
2.1
Minor text edits.
Minor edit to the hyperlinks.
■ Added Table 1–5.
■ Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
■ Updated “Introduction”, “Cyclone III Device Family Architecture”, “Embedded Multipliers
and Digital Signal Processing Support ”, “Clock Networks and PLLs ”, “I/O Features ”,
“High-Speed Differential Interfaces ”, “Auto-Calibrating External Memory Interfaces ”,
“Quartus II Software Support”, “Configuration ”, and “Design Security (Cyclone III LS
Devices Only)”.
June 2009
2.0
■ Removed “Referenced Document” section.
■ Updated “Increased System Integration” section.
■ Updated “Memory Blocks” section.
October 2008
May 2008
1.3
1.2
■ Updated chapter to new template.
■ Added 164-pin Micro FineLine Ball-Grid Array (MBGA) details to Table 1–2, Table 1–3 and
Table 1–4.
■ Updated Figure 1–2 with automotive temperature information.
■ Updated “Increased System Integration” section, Table 1–6, and “High-Speed Differential
Interfaces” section with BLVDS information.
■ Removed the text “Spansion” in “Increased System.
■ Integration” and “Configuration” sections.
■ Removed trademark symbol from “MultiTrack” in “MultiTrack Interconnect”.
July 2007
1.1
1.0
■ Removed registered trademark symbol from “Simulink” and “MATLAB” from “Embedded
Multipliers and Digital.
■ Signal Processing Support” section.
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
1–14
Chapter 1: Cyclone III Device Family Overview
Document Revision History
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
2. Logic Elements and Logic Array Blocks
in the Cyclone III Device Family
December 2011
CIII51002-2.3
CIII51002-2.3
This chapter contains feature definitions for logic elements (LEs) and logic array
blocks (LABs). Details are provided on how LEs work, how LABs contain groups of
LEs, and how LABs interface with the other blocks in the Cyclone® III device family
(Cyclone III and Cyclone III LS devices).
Logic Elements
Logic elements (LEs) are the smallest units of logic in the Cyclone III device family
architecture. LEs are compact and provide advanced features with efficient logic
usage. Each LE has the following features:
■
A four-input look-up table (LUT), which can implement any function of four
variables
■
■
■
■
A programmable register
A carry chain connection
A register chain connection
The ability to drive the following interconnects:
■
■
■
■
■
Local
Row
Column
Register chain
Direct link
■
■
Register packing support
Register feedback support
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
December 2011
Subscribe
2–2
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Logic Elements
Figure 2–1 shows the LEs for the Cyclone III device family.
Figure 2–1. Cyclone III Device Family LEs
Register Chain
Routing from
previous LE
Register Bypass
LAB-Wide
Synchronous LAB-Wide
Programmable
Register
Load
Synchronous
Clear
LE Carry-In
data 1
data 2
Row, Column,
And Direct Link
Routing
Synchronous
Load and
Clear Logic
Carry
Chain
Look-Up Table
data 3
D
Q
(LUT)
data 4
ENA
CLRN
Row, Column,
And Direct Link
Routing
labclr1
labclr2
Asynchronous
Clear Logic
Chip-Wide
Reset
Local
Routing
Register Feedback
(DEV_CLRn)
Clock &
Clock Enable
Select
Register Chain
Output
labclk1
LE Carry-Out
labclk2
labclkena1
labclkena2
LE Features
You can configure the programmable register of each LE for D, T, JK, or SR flipflop
operation. Each register has data, clock, clock enable, and clear inputs. Signals that
use the global clock network, general-purpose I/O pins, or any internal logic can
drive the clock and clear control signals of the register. Either general-purpose I/O
pins or the internal logic can drive the clock enable. For combinational functions, the
LUT output bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources. The
LUT or register output independently drives these three outputs. Two LE outputs
drive the column or row and direct link routing connections, while one LE drives the
local interconnect resources. This allows the LUT to drive one output while the
register drives another output. This feature, called register packing, improves device
utilization because the device can use the register and the LUT for unrelated
functions. The LAB-wide synchronous load control signal is not available when using
register packing. For more information on the synchronous load control signal, refer
to “LAB Control Signals” on page 2–6.
The register feedback mode allows the register output to feed back into the LUT of the
same LE to ensure that the register is packed with its own fan-out LUT, providing
another mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
2–3
LE Operating Modes
In addition to the three general routing outputs, LEs in a LAB have register chain
outputs, which allows registers in the same LAB to cascade together. The register
chain output allows the LUTs to be used for combinational functions and the registers
to be used for an unrelated shift register implementation. These resources speed up
connections between LABs while saving local interconnect resources.
LE Operating Modes
Cyclone III device family LEs operate in the following modes:
■
■
Normal mode
Arithmetic mode
LE operating modes use LE resources differently. In each mode, there are six available
inputs to the LE. These inputs include the four data inputs from the LAB local
interconnect, the LE carry-in from the previous LE carry-chain, and the register chain
connection. Each input is directed to different destinations to implement the desired
logic function. LAB-wide signals provide clock, asynchronous clear, synchronous
clear, synchronous load, and clock enable control for the register. These LAB-wide
signals are available in all LE modes.
The Quartus® II software automatically chooses the appropriate mode for common
functions, such as counters, adders, subtractors, and arithmetic functions, in
conjunction with parameterized functions such as the library of parameterized
modules (LPM) functions. You can also create special-purpose functions that specify
which LE operating mode to use for optimal performance, if required.
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In normal mode, four data inputs from the LAB local interconnect are inputs to a
four-input LUT (Figure 2–2). The Quartus II Compiler automatically selects the
carry-in (cin) or the data3signal as one of the inputs to the LUT. LEs in normal mode
support packed registers and register feedback.
Figure 2–2 shows LEs in normal mode.
Figure 2–2. Cyclone III Device Family LEs in Normal Mode
Register Chain
Connection
sload
sclear
(LAB Wide) (LAB Wide)
Packed Register Input
Row, Column, and
Direct Link Routing
Q
D
data1
data2
Row, Column, and
Direct Link Routing
ENA
data3
cin (from cout
of previous LE)
CLRN
Four-Input
LUT
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
Local Routing
data4
Register
Chain Output
Register Bypass
Register Feedback
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
2–4
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Logic Array Blocks
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, and
comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry
chain (Figure 2–3). LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output. Register feedback and register packing are supported
when LEs are used in arithmetic mode.
Figure 2–3 shows LEs in arithmetic mode.
Figure 2–3. Cyclone III Device Family LEs in Arithmetic Mode
Register Chain
Connection
Packed Register Input
sload
(LAB Wide)
sclear
(LAB Wide)
data4
data1
data2
Three-Input
LUT
Row, Column, and
Direct link routing
Q
D
Row, Column, and
Direct link routing
data3
ENA
CLRN
Three-Input
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
cin (from cout
of previous LE)
LUT
Local Routing
cout
Register
Chain Output
Register Bypass
Register Feedback
The Quartus II Compiler automatically creates carry chain logic during design
processing. You can also manually create the carry chain logic during design entry.
Parameterized functions, such as LPM functions, automatically take advantage of
carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 LEs by automatically
linking LABs in the same column. For enhanced fitting, a long carry chain runs
vertically, which allows fast horizontal connections to M9K memory blocks or
embedded multipliers through direct link interconnects. For example, if a design has a
long carry chain in a LAB column next to a column of M9K memory blocks, any LE
output can feed an adjacent M9K memory block through the direct link interconnect.
If the carry chains run horizontally, any LAB which is not next to the column of M9K
memory blocks uses other row or column interconnects to drive a M9K memory
block. A carry chain continues as far as a full column.
Logic Array Blocks
Logic array blocks (LABs) contain groups of LEs.
Topology
Each LAB consists of the following features:
■
16 LEs
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December 2011 Altera Corporation
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
2–5
Logic Array Blocks
■
■
■
■
LAB control signals
LE carry chains
Register chains
Local interconnect
The local interconnect transfers signals between LEs in the same LAB. Register chain
connections transfer the output of one LE register to the adjacent LE register in a LAB.
The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing
the use of local and register chain connections for performance and area efficiency.
Figure 2–4 shows the LAB structure for the Cyclone III device family.
Figure 2–4. Cyclone III Device Family LAB Structure
Row Interconnect
Column
Interconnect
Direct link
interconnect
from adjacent
block
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Direct link
interconnect
to adjacent
block
Local Interconnect
LAB
LAB Interconnects
The LAB local interconnect is driven by column and row interconnects and LE
outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM
blocks, and embedded multipliers from the left and right can also drive the local
interconnect of a LAB through the direct link connection. The direct link connection
feature minimizes the use of row and column interconnects, providing higher
performance and flexibility. Each LE can drive up to 48 LEs through fast local and
direct link interconnects.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
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Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
LAB Control Signals
Figure 2–5 shows the direct link connection.
Figure 2–5. Cyclone III Device Family Direct Link Connection
Direct link interconnect from
left LAB, M9K memory
block, embedded multiplier,
PLL, or IOE output
Direct link interconnect from
right LAB, M9K memory
block, embedded multiplier,
PLL, or IOE output
Direct link
interconnect
to left
Direct link
interconnect
to right
Local
Interconnect
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs. The control
signals include:
■
■
■
■
■
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
You can use up to eight control signals at a time. Register packing and synchronous
load cannot be used simultaneously.
Each LAB can have up to four non-global control signals. You can use additional LAB
control signals as long as they are global signals.
Synchronous clear and load signals are useful for implementing counters and other
functions. The synchronous clear and synchronous load signals are LAB-wide signals
that affect all registers in the LAB.
Each LAB can use two clocks and two clock enable signals. The clock and clock enable
signals of each LAB are linked. For example, any LE in a particular LAB using the
labclk1signal also uses the labclkena1. If the LAB uses both the rising and falling
edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock
enable signal turns off the LAB-wide clock.
The LAB row clocks [5..0]and LAB local interconnect generate the LAB-wide
control signals. The MultiTrack interconnect inherent low skew allows clock and
control signal distribution in addition to data distribution.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
2–7
Document Revision History
Figure 2–6 shows the LAB control signal generation circuit.
Figure 2–6. Cyclone III Device Family LAB-Wide Control Signals
Dedicated
6
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena2
labclkena1
labclr1
synclr
labclk1
labclk2
syncload
labclr2
LAB-wide signals control the logic for the clear signal of the register. The LE directly
supports an asynchronous clear function. Each LAB supports up to two asynchronous
clear signals (labclr1and labclr2).
A LAB-wide asynchronous load signal to control the logic for the preset signal of the
register is not available. The register preset is achieved with a NOT gate push-back
technique. The Cyclone III device family only supports either a preset or
asynchronous clear signal.
In addition to the clear port, the Cyclone III device family provides a chip-wide reset
pin (DEV_CLRn) that resets all registers in the device. An option set before compilation
in the Quartus II software controls this pin. This chip-wide reset overrides all other
control signals.
Document Revision History
Table 2–1 lists the revision history for this document.
Table 2–1. Document Revision History (Part 1 of 2)
Date
Version
2.3
Changes
December 2011
December 2009
July 2009
Minor text edits.
2.2
Minor changes to the text.
Minor edit to the hyperlinks.
2.1
Updated to include Cyclone III LS information
■ Updated chapter part number.
June 2009
2.0
1.2
■ Updated “Introduction” on page 2–1.
■ Updated Figure 2–1 on page 2–2 and Figure 2–4 on page 2–5.
■ Updated “LAB Control Signals” on page 2–6.
Updated chapter to new template.
October 2008
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
2–8
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Document Revision History
Table 2–1. Document Revision History (Part 2 of 2)
Date
July 2007
March 2007
Version
1.1
Changes
Removed trademark symbol from “MultiTrack” in “LAB Control Signals” section.
Initial release.
1.0
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
3. Memory Blocks in the Cyclone III
Device Family
December 2011
CIII51004-2.3
CIII51004-2.3
The Cyclone® III device family (Cyclone III and Cyclone III LS devices) features
embedded memory structures to address the on-chip memory needs of Altera®
Cyclone III device family designs. The embedded memory structure consists of
columns of M9K memory blocks that you can configure to provide various memory
functions, such as RAM, shift registers, ROM, and FIFO buffers.
This chapter contains the following sections:
■
■
■
“Memory Modes” on page 3–7
“Clocking Modes” on page 3–14
“Design Considerations” on page 3–15
Overview
M9K blocks support the following features:
■
■
■
8,192 memory bits per block (9,216 bits per block including parity)
Independent read-enable (rden) and write-enable (wren) signals for each port
Packed mode in which the M9K memory block is split into two 4.5 K single-port
RAMs
■
■
■
■
■
■
Variable port configurations
Single-port and simple dual-port modes support for all port widths
True dual-port (one read and one write, two reads, or two writes) operation
Byte enables for data input masking during writes
Two clock-enable control signals for each port (port A and port B)
Initialization file to pre-load memory content in RAM and ROM modes
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
December 2011
Subscribe
3–2
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Table 3–1 lists the features supported by the M9K memory
Table 3–1. Summary of M9K Memory Features
Feature
M9K Blocks
8192 × 1
4096 × 2
2048 × 4
1024 × 8
Configurations (depth × width)
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
Parity bits
v
Byte enable
v
Packed mode
v
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
v
v
v
v
(1)
Embedded shift register mode
v
ROM mode
v
(1)
FIFO buffer
v
Simple dual-port mixed width support
v
(2)
True dual-port mixed width support
v
v
Memory initialization file (.mif)
Mixed-clock mode
v
Power-up condition
Outputs cleared
Register asynchronous clears
Latch asynchronous clears
Write or read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Notes to Table 3–1:
Read address registers and output registers only
Output latches only
Write and read: Rising clock edges
Outputs set to Old Data or New Data
Outputs set to Old Data or Don’t Care
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
logic.
(2) Width modes of ×32 and ×36 are not available.
f
For information about the number of M9K memory blocks for the Cyclone III device
family, refer to the Cyclone III Device Family Overview chapter.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–3
Overview
Control Signals
The clock-enable control signal controls the clock entering the input and output
registers and the entire M9K memory block. This signal disables the clock so that the
M9K memory block does not see any clock edges and does not perform any
operations.
The rdenand wrencontrol signals control the read and write operations for each port
of M9K memory blocks. You can disable the rdenor wrensignals independently to
save power whenever the operation is not required.
Figure 3–1 shows how the register clock, clear, and control signals are implemented in
the Cyclone III device family M9K memory block.
Figure 3–1. M9K Control Signal Selection
Dedicated
Row LAB
Clocks
6
Local
Interconnect
clocken_b
clock_b
rden_b
addressstall_b
wren_b
aclr_b
byteena_b
rden_a
wren_a
clock_a
clocken_a
aclr_a
addressstall_a
byteena_a
Parity Bit Support
Parity checking for error detection is possible with the parity bit along with internal
logic resources. The Cyclone III device family M9K memory blocks support a parity
bit for each storage byte. You can use this bit as either a parity bit or as an additional
data bit. No parity function is actually performed on this bit.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–4
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Byte Enable Support
The Cyclone III device family M9K memory blocks support byte enables that mask
the input data so that only specific bytes of data are written. The unwritten bytes
retain the previous written value. The wrensignals, along with the byte-enable
(byteena) signals, control the write operations of the RAM block. The default value of
the byteenasignals is high (enabled), in which case writing is controlled only by the
wrensignals. There is no clear port to the byteenaregisters. M9K blocks support byte
enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
Byte enables operate in one-hot manner, with the LSB of the byteenasignal
corresponding to the least significant byte of the data bus. For example, if
byteena = 01and you are using a RAM block in ×18 mode, data[8..0]is enabled
and data[17..9]is disabled. Similarly, if byteena = 11, both data[8..0]and
data[17..9]are enabled. Byte enables are active high.
Table 3–2 lists the byte selection.
(1)
Table 3–2. byteena for Cyclone III Device Family M9K Blocks
Affected Bytes
byteena[3..0]
datain × 16
[7..0]
[15..8]
—
datain × 18
[8..0]
[17..9]
—
datain × 32
datain × 36
[8..0]
[0] = 1
[1] = 1
[7..0]
[15..8]
[17..9]
[2] = 1
[23..16]
[31..24]
[26..18]
[35..27]
[3] = 1
—
—
Note to Table 3–2:
(1) Any combination of byte enables is possible.
Figure 3–2 shows how the wrenand byteenasignals control the RAM operations.
(1)
Figure 3–2. Cyclone III Device Family byteena Functional Waveform
inclock
wren
rden
an
XXXX
XX
a0
10
a1
ABCD
01
a2
a0
a1
a2
address
data
XXXX
XX
11
byteena
FFFF
ABFF
contents at a0
FFFF
FFCD
ABFF
contents at a1
FFFF
ABFF
ABCD
contents at a2
q (asynch)
doutn
FFCD
ABCD
FFCD
ABCD
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–5
Overview
(1)
Figure 3–2. Cyclone III Device Family byteena Functional Waveform
Note to Figure 3–2:
(1) For this functional waveform, New Data mode is selected.
When a byteenabit is deasserted during a write cycle, the old data in the memory
appears in the corresponding data-byte output. When a byteenabit is asserted during
a write cycle, the corresponding data-byte output depends on the setting chosen in
the Quartus® II software. The setting can either be the newly written data or the old
data at that location.
Packed Mode Support
Cyclone III device family M9K memory blocks support packed mode. You can
implement two single-port memory blocks in a single block under the following
conditions:
■
Each of the two independent block sizes is less than or equal to half of the M9K
block size. The maximum data width for each independent block is 18 bits wide.
■
Each of the single-port memory blocks is configured in single-clock mode. For
more information about packed mode support, refer to “Single-Port Mode” on
page 3–8 and “Single-Clock Mode” on page 3–15.
Address Clock Enable Support
Cyclone III device family M9K memory blocks support an active-low address clock
enable, which holds the previous address value for as long as the addressstallsignal
is high (addressstall='1'). When you configure M9K memory blocks in dual-port
mode, each port has its own independent address clock enable.
Figure 3–3 shows an address clock enable block diagram. The address register output
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
Figure 3–3. Cyclone III Device Family Address Clock Enable Block Diagram
address[0]
address[0]
address[0]
register
address[N]
register
address[N]
address[N]
addressstall
clock
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–6
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–4 and Figure 3–5 show the address clock enable waveform during read and
write cycles, respectively.
Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
rden
a0
a1
a2
a3
a4
a5
a6
addressstall
latched address
(inside memory)
a5
a1
a4
an
a0
q (synch)
dout0
dout1
dout4
doutn-1
doutn
doutn
dout1
dout1
dout1
dout1
dout0
dout4
dout1
q (asynch)
dout5
Figure 3–5. Cyclone III Device Family Address Clock Enable During Write Cycle Waveform
inclock
a0
00
a1
01
a2
02
a3
03
a4
04
a5
05
a6
06
wraddress
data
wren
addressstall
latched address
(inside memory)
a1
a4
03
a5
an
XX
a0
00
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
01
02
XX
XX
04
XX
XX
05
Mixed-Width Support
M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to “Memory Modes” on
page 3–7.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–7
Memory Modes
Asynchronous Clear
The Cyclone III device family supports asynchronous clears for read address registers,
output registers, and output latches only. Input registers other than read address
registers are not supported. When applied to output registers, the asynchronous clear
signal clears the output registers and the effects are immediately seen. If your RAM
does not use output registers, you can still clear the RAM outputs using the output
latch asynchronous clear feature.
1
Asserting asynchronous clear to the read address register during a read operation
might corrupt the memory content.
Figure 3–6 shows the functional waveform for the asynchronous clear feature.
Figure 3–6. Output Latch Asynchronous Clear Waveform
clk
aclr
aclr at latch
q
a1
a0
a1
a2
1
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard™ Plug-In Manager.
f
For more information, refer to the Internal Memory (RAM and ROM) User Guide.
There are three ways to reset registers in the M9K blocks:
■
■
■
Power up the device
Use the aclrsignal for output register only
Assert the device-wide reset signal using the DEV_CLRn option
Memory Modes
Cyclone III device family M9K memory blocks allow you to implement
fully-synchronous SRAM memory in multiple modes of operation. Cyclone III device
family M9K memory blocks do not support asynchronous (unregistered) memory
inputs.
M9K memory blocks support the following modes:
■
■
■
■
■
■
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–8
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
1
Violating the setup or hold time on the M9K memory block input registers may
corrupt memory contents. This applies to both read and write operations.
Single-Port Mode
Single-port mode supports non-simultaneous read and write operations from a single
address. Figure 3–7 shows the single-port memory configuration for Cyclone III
device family M9K memory blocks.
Figure 3–7. Single-Port Memory (1), (2)
data[]
address[]
wren
byteena[]
addressstall
inclock
inclocken
rden
q[]
outclock
outclocken
aclr
Notes to Figure 3–7:
(1) You can implement two single-port memory blocks in a single M9K block.
(2) For more information, refer to “Packed Mode Support” on page 3–5.
During a write operation, the behavior of the RAM outputs is configurable. If you
activate rdenduring a write operation, the RAM outputs show either the new data
being written or the old data at that address. If you perform a write operation with
rdendeactivated, the RAM outputs retain the values they held during the most recent
active rdensignal.
To choose the desired behavior, set the Read-During-Write option to either New Data
or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software. For
more information about read-during-write mode, refer to “Read-During-Write
Operations” on page 3–15.
The port width configurations for M9K blocks in single-port mode are as follow:
■
■
■
■
■
■
■
■
■
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–9
Memory Modes
Figure 3–8 shows timing waveforms for read and write operations in single-port
mode with unregistered outputs. Registering the outputs of the RAM simply delays
the output by one clock cycle.
q
Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms
clk_a
wren_a
rden_a
address_a
data_a
a0
B
a1
E
A
C
D
F
q_a (old data)
a0(old data)
A
B
B
C
a1(old data)
D
E
E
F
A
D
q_a (new data)
Simple Dual-Port Mode
Simple dual-port mode supports simultaneous read and write operations to different
locations. Figure 3–9 shows the simple dual-port memory configuration.
(1)
Figure 3–9. Cyclone III Device Family Simple Dual-Port Memory
data[]
rdaddress[]
rden
wraddress[]
wren
q[]
byteena[]
wr_addressstall
wrclock
rd_addressstall
rdclock
rdclocken
wrclocken
aclr
Note to Figure 3–9:
(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.
Cyclone III device family M9K memory blocks support mixed-width configurations,
allowing different read and write port widths.
Table 3–3 lists mixed-width configurations.
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Write Port
Read Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 256 × 32 1024 × 9 512 × 18 256 × 36
8192 × 1
4096 × 2
2048 × 4
1024 × 8
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
—
—
—
—
—
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–10
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Write Port
Read Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 256 × 32 1024 × 9 512 × 18 256 × 36
512 × 16
256 × 32
1024 × 9
512 × 18
256 × 36
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
v
v
—
—
—
—
—
v
v
v
—
—
v
v
v
—
—
v
v
v
In simple dual-port mode, M9K memory blocks support separate wrenand rden
signals. You can save power by keeping the rdensignal low (inactive) when not
reading. Read-during-write operations to the same address can either output “Don’t
Care” data at that location or output “Old Data”. To choose the desired behavior, set
the Read-During-Write option to either Don’t Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to “Read-During-Write Operations” on page 3–15.
Figure 3–10 shows the timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the
qoutput by one clock cycle.
Figure 3–10. Cyclone III Device Family Simple Dual-Port Timing Waveforms
wrclock
wren
a0
a1
a2
a3
a4
a5
an
din
an-1
a6
wraddress
data
din-1
din4
din5
din6
rdclock
rden
rdaddress
bn
doutn-1
b1
b2
b3
b0
q (asynch)
dout0
doutn
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–11
Memory Modes
True Dual-Port Mode
True dual-port mode supports any combination of two-port operations: two reads,
two writes, or one read and one write, at two different clock frequencies. Figure 3–11
shows the Cyclone III device family true dual-port memory configuration.
(1)
Figure 3–11. Cyclone III Device Family True Dual-Port Memory
data_a[]
address_a[]
wren_a
data_b[]
address_b[]
wren_b
byteena_a[]
addressstall_a
clock_a
byteena_b[]
addressstall_b
clock_b
clocken_a
rden_a
clocken_b
rden_b
aclr_a
aclr_b
q_a[]
q_b[]
Note to Figure 3–11:
(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.
1
The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit
(18-bit with parity).
Table 3–4 lists the possible M9K block mixed-port width configurations.
Table 3–4. Cyclone III Device Family M9K Block Mixed-Width Configurations (True Dual-Port
Mode)
Write Port
Read Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 1024 × 9 512 × 18
8192 × 1
4096 × 2
2048 × 4
1024 × 8
512 × 16
1024 × 9
512 × 18
v
v
v
v
v
—
—
v
v
v
v
v
—
—
v
v
v
v
v
—
—
v
v
v
v
v
—
—
v
v
v
v
v
—
—
—
—
—
—
—
v
v
—
—
—
—
—
v
v
In true dual-port mode, M9K memory blocks support separate wrenand rdensignals.
You can save power by keeping the rdensignal low (inactive) when not reading.
Read-during-write operations to the same address can either output “New Data” at
that location or “Old Data”. To choose the desired behavior, set the Read-During-
Write option to either New Data or Old Data in the RAM MegaWizard Plug-In
Manager in the Quartus II software. For more information about this behavior, refer to
“Read-During-Write Operations” on page 3–15.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–12
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
In true dual-port mode, you can access any memory location at any time from either
port A or port B. However, when accessing the same memory location from both
ports, you must avoid possible write conflicts. When you attempt to write to the same
address location from both ports at the same time, a write conflict happens. This
results in unknown data being stored to that address location. There is no conflict
resolution circuitry built into the Cyclone III device family M9K memory blocks. You
must handle address conflicts external to the RAM block.
Figure 3–12 shows true dual-port timing waveforms for the write operation at port A
and read operation at port B. Registering the outputs of the RAM simply delays the
outputs by one clock cycle.
q
Figure 3–12. Cyclone III Device Family True Dual-Port Timing Waveforms
clk_a
wren_a
an
a0
a1
a2
a3
a4
a5
address_a
an-1
a6
din-1
din
din4
din5
din6
data_a
rden_a
q_a (asynch)
clk_b
dout0
dout1
dout2
din5
dout3
din4
din
din-1
wren_b
address_b
rden_b
bn
b1
b2
b3
b0
q_b (asynch)
doutn
dout2
dout0
doutn-1
dout1
Shift Register Mode
Cyclone III device family M9K memory blocks can implement shift registers for
digital signal processing (DSP) applications, such as finite impulse response (FIR)
filters, pseudo-random number generators, multi-channel filtering, and
auto-correlation and cross-correlation functions. These and other DSP applications
require local data storage, traditionally implemented with standard flipflops that
quickly exhaust many logic cells for large shift registers. A more efficient alternative is
to use embedded memory as a shift register block, which saves logic cell and routing
resources.
The size of a (w × m × n) shift register is determined by the input data width (w), the
length of the taps (m), and the number of taps (n), and must be less than or equal to
the maximum number of memory bits, which is 9,216 bits. In addition, the size of
(w × n) must be less than or equal to the maximum width of the block, which is 36 bits.
If you need a larger shift register, you can cascade the M9K memory blocks.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–13
Memory Modes
Figure 3–13 shows the Cyclone III device family M9K memory block in the shift
register mode.
Figure 3–13. Cyclone III Device Family Shift Register Mode Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
W
m-Bit Shift Register
W
n Number of Taps
m-Bit Shift Register
W
W
W
m-Bit Shift Register
W
ROM Mode
Cyclone III device family M9K memory blocks support ROM mode. A .mif initializes
the ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
FIFO Buffer Mode
Cyclone III device family M9K memory blocks support single-clock or dual-clock
FIFO buffers. Dual clock FIFO buffers are useful when transferring data from one
clock domain to another clock domain. Cyclone III device family M9K memory blocks
do not support simultaneous read and write from an empty FIFO buffer.
f
For more information about FIFO buffers, refer to the SCFIFO and DCFIFO
Megafunctions user guide.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–14
Chapter 3: Memory Blocks in the Cyclone III Device Family
Clocking Modes
Clocking Modes
Cyclone III device family M9K memory blocks support the following clocking modes:
■
■
■
■
Independent
Input or output
Read or write
Single-clock
When using read or write clock mode, if you perform a simultaneous read or write to
the same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode or I/O clock mode and choose
the appropriate read-during-write behavior in the MegaWizard Plug-In Manager.
1
1
Violating the setup or hold time on the memory block input registers might corrupt
the memory contents. This applies to both read and write operations.
Asynchronous clears are available on read address registers, output registers, and
output latches only.
Table 3–5 lists the clocking mode versus memory mode support matrix.
Table 3–5. Cyclone III Device Family Memory Clock Modes
Simple
True Dual-Port
Mode
Single-Port
Mode
Clocking Mode
Dual-Port
Mode
ROM Mode
FIFO Mode
Independent
Input or output
Read or write
Single-clock
v
v
—
v
—
v
v
v
—
v
—
v
v
v
—
v
—
—
v
v
Independent Clock Mode
Cyclone III device family M9K memory blocks can implement independent clock
mode for true dual-port memories. In this mode, a separate clock is available for each
port (port A and port B). clock Acontrols all registers on the port A side, while clock
B
controls all registers on the port B side. Each port also supports independent clock
enables for port A and B registers.
I/O Clock Mode
Cyclone III device family M9K memory blocks can implement input or output clock
mode for FIFO, single-port, true, and simple dual-port memories. In this mode, an
input clock controls all input registers to the memory block, including data, address,
byteena, wren, and rdenregisters. An output clock controls the data-output registers.
Each memory block port also supports independent clock enables for input and
output registers.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–15
Design Considerations
Read or Write Clock Mode
Cyclone III device family M9K memory blocks can implement read or write clock
mode for FIFO and simple dual-port memories. In this mode, a write clock controls
the data inputs, write address, and wrenregisters. Similarly, a read clock controls the
data outputs, read address, and rdenregisters. M9K memory blocks support
independent clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Single-Clock Mode
Cyclone III device family M9K memory blocks can implement single-clock mode for
FIFO, ROM, true dual-port, simple dual-port, and single-port memories. In this mode,
you can control all registers of the M9K memory block with a single clock together
with clock enable.
Design Considerations
This section describes designing with M9K memory blocks.
Read-During-Write Operations
“Same-Port Read-During-Write Mode” on page 3–16 and “Mixed-Port Read-During-
Write Mode” on page 3–16 describe the functionality of the various RAM
configurations when reading from an address during a write operation at that same
address.
There are two read-during-write data flows: same-port and mixed-port. Figure 3–14
shows the difference between these flows.
Figure 3–14. Cyclone III Device Family Read-During-Write Data Flow
write_a
write_b
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
read_a
Port A
Port B
read_b
data out
data out
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–16
Chapter 3: Memory Blocks in the Cyclone III Device Family
Design Considerations
Same-Port Read-During-Write Mode
This mode applies to a single-port RAM or the same port of a true dual-port RAM. In
the same port read-during-write mode, there are two output choices: New Data mode
(or flow-through) and Old Data mode. In New Data mode, new data is available on
the rising edge of the same clock cycle on which it was written. In Old Data mode, the
RAM outputs reflect the old data at that address before the write operation proceeds.
When using New Data mode together with byteena, you can control the output of the
RAM. When byteenais high, the data written into the memory passes to the output
(flow-through). When byteenais low, the masked-off data is not written into the
memory and the old data in the memory appears on the outputs. Therefore, the
output can be a combination of new and old data determined by byteena
.
Figure 3–15 and Figure 3–16 show sample functional waveforms of same port
read-during-write behavior with both New Data and Old Data modes, respectively.
Figure 3–15. Same Port Read-During Write: New Data Mode
clk_a
wren_a
rden_a
address_a
a0
B
a1
E
data_a
A
C
D
F
q_a (asynch)
A
B
C
D
E
F
Figure 3–16. Same Port Read-During-Write: Old Data Mode
clk_a
wren_a
rden_a
address_a
a0
B
a1
E
data_a
A
C
D
F
q_a (asynch)
a0(old data)
A
B
a1(old data)
D
E
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode, which has one port
reading and the other port writing to the same address location with the same clock.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 3: Memory Blocks in the Cyclone III Device Family
3–17
Design Considerations
In this mode, you also have two output choices: Old Data mode or Don't Care mode.
In Old Data mode, a read-during-write operation to different ports causes the RAM
outputs to reflect the old data at that address location. In Don't Care mode, the same
operation results in a “Don't Care” or unknown value on the RAM outputs.
f
For more information about how to implement the desired behavior, refer to the
Internal Memory (RAM and ROM) User Guide.
Figure 3–17 shows a sample functional waveform of mixed port read-during-write
behavior for the Old Data mode. In Don't Care mode, the old data is replaced with
“Don't Care”.
Figure 3–17. Mixed Port Read-During-Write: Old Data Mode
clk_a&b
wren_a
address_a
a
b
A
B
C
D
E
F
data_a
rden_b
address_b
a
b
B
a (old data)
D
E
b (old data)
A
q_b (asynch)
1
For mixed-port read-during-write operation with dual clocks, the relationship
between the clocks determines the output behavior of the memory. If you use the
same clock for the two clocks, the output is the old data from the address location.
However, if you use different clocks, the output is unknown during the mixed-port
read-during-write operation. This unknown value may be the old or new data at the
address location, depending on whether the read happens before or after the write.
Conflict Resolution
When you are using M9K memory blocks in true dual-port mode, it is possible to
attempt two write operations to the same memory location (address). Because there is
no conflict resolution circuitry built into M9K memory blocks, this results in unknown
data being written to that location. Therefore, you must implement conflict-resolution
logic external to the M9K memory block.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
3–18
Chapter 3: Memory Blocks in the Cyclone III Device Family
Document Revision History
Power-Up Conditions and Memory Initialization
The M9K memory block outputs of the Cyclone III device family power up to zero
(cleared) regardless of whether the output registers are used or bypassed. All M9K
memory blocks support initialization using a .mif. You can create .mifs in the
Quartus II software and specify their use using the RAM MegaWizard Plug-In
Manager when instantiating memory in your design. Even if memory is
pre-initialized (for example, using a .mif), it still powers up with its outputs cleared.
Only the subsequent read after power up outputs the pre-initialized values.
f
For more information about .mifs, refer to the Internal Memory (RAM and ROM) User
Guide and the Quartus II Handbook.
Power Management
The M9K memory block clock enables of the Cyclone III device family allow you to
control clocking of each M9K memory block to reduce AC power consumption. Use
the rdensignal to ensure that read operations only occur when necessary. If your
design does not require read-during-write, reduce power consumption by deasserting
the rdensignal during write operations, or any period when there are no memory
operations. The Quartus II software automatically powers down any unused M9K
memory blocks to save static power.
Document Revision History
Table 3–6 lists the revision history for this document.
Table 3–6. Document Revision History
Date
Version
2.3
Changes
December 2011
December 2009
July 2009
Minor text edits.
2.2
Minor changes to the text.
2.1
Made minor correction to the part number.
Updated to include Cyclone III LS information
■ Updated chapter part number.
■ Updated “Introduction” on page 3–1.
■ Updated “Overview” on page 3–1.
June 2009
2.0
■ Updated Table 3–1 on page 3–2.
■ Updated “Control Signals” on page 3–3.
■ Updated “Memory Modes” on page 3–8.
■ Updated “Simple Dual-Port Mode” on page 3–10.
■ Updated “Read or Write Clock Mode” on page 3–16.
Updated chapter to new template.
October 2008
May 2008
1.3
1.2
■ Revised the maximum performance of the M9K blocks to 315 MHz in “Introduction” and
“Overview” sections, and in Table 3-1.
■ Updated “Address Clock Enable Support” section.
Added chapter TOC and “Referenced Documents” section.
Initial release.
July 2007
1.1
1.0
March 2007
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
4. Embedded Multipliers in the
Cyclone III Device Family
December 2011
CIII51005-2.3
CIII51005-2.3
The Cyclone® III device family (Cyclone III and Cyclone III LS devices) includes a
combination of on-chip resources and external interfaces that help to increase
performance, reduce system cost, and lower the power consumption of digital signal
processing (DSP) systems. The Cyclone III device family, either alone or as DSP device
co-processors, are used to improve price-to-performance ratios of DSP systems.
Particular focus is placed on optimizing Cyclone III and Cyclone III LS devices for
applications that benefit from an abundance of parallel processing resources, which
include video and image processing, intermediate frequency (IF) modems used in
wireless communications systems, and multi-channel communications and video
systems.
This chapter contains the following sections:
■
■
■
“Embedded Multiplier Block Overview” on page 4–2
“Architecture” on page 4–3
“Operational Modes” on page 4–5
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
December 2011
Subscribe
4–2
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Embedded Multiplier Block Overview
Embedded Multiplier Block Overview
Figure 4–1 shows one of the embedded multiplier columns with the surrounding logic
array blocks (LABs). The embedded multiplier is configured as either one 18 × 18
multiplier or two 9 × 9 multipliers. For multiplications greater than 18 × 18, the
Quartus® II software cascades multiple embedded multiplier blocks together. There
are no restrictions on the data width of the multiplier, but the greater the data width,
the slower the multiplication process.
Figure 4–1. Embedded Multipliers Arranged in Columns with Adjacent LABs
Embedded
Multiplier
Column
1 LAB
Row
Embedded
Multiplier
Table 4–1 lists the number of embedded multipliers and the multiplier modes that can
be implemented in the Cyclone III device family.
Table 4–1. Number of Embedded Multipliers in the Cyclone III Device Family
(1)
(1)
Device Family
Device
EP3C5
Embedded Multipliers 9 × 9 Multipliers
18 × 18 Multipliers
23
23
46
23
23
EP3C10
46
EP3C16
56
112
132
252
312
488
576
400
552
640
792
56
EP3C25
66
66
Cyclone III
EP3C40
126
156
244
288
200
276
320
396
126
156
244
288
200
276
320
396
EP3C55
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Note to Table 4–1:
(1) These columns show the number of 9 × 9 or 18 × 18 multipliers for each device. The total number of multipliers for each device is not the sum
of all the multipliers.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
4–3
Architecture
In addition to the embedded multipliers in the Cyclone III device family, you can
implement soft multipliers by using the M9K memory blocks as look-up tables
(LUTs). The LUTs contain partial results from the multiplication of input data with
coefficients that implement variable depth and width high-performance soft
multipliers for low-cost, high-volume DSP applications. The availability of soft
multipliers increases the number of available multipliers in the device.
Table 4–2 lists the total number of multipliers available in the Cyclone III device
family using embedded multipliers and soft multipliers.
Table 4–2. Number of Multipliers in the Cyclone III Device Family
Soft Multipliers
(2)
Device Family
Device
Embedded Multipliers
Total Multipliers
(1)
(16 × 16)
EP3C5
EP3C10
23
23
—
46
23
69
EP3C16
56
56
112
132
252
416
549
720
533
759
986
1287
EP3C25
66
66
Cyclone III
EP3C40
126
156
244
288
200
276
320
396
126
260
305
432
333
483
666
891
EP3C55
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Notes to Table 4–2:
(1) Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit
coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.
(2) The total number of multipliers may vary, depending on the multiplier mode you use.
f
f
For more information about M9K memory blocks of the Cyclone III device family,
refer to the Memory Blocks in the Cyclone III Device Family chapter.
For more information about soft multipliers, refer to the Implementing Multipliers in
FPGA Devices application note.
Architecture
Each embedded multiplier consists of the following elements:
■
■
■
Multiplier stage
Input and output registers
Input and output interfaces
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
4–4
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Architecture
Figure 4–2 shows the multiplier block architecture.
Figure 4–2. Multiplier Block Architecture
signa
signb
aclr
clock
ena
D
Q
Q
Data A
Data B
ENA
Data Out
D
Q
CLRN
ENA
CLRN
D
ENA
Output
Register
Input
Register
CLRN
Embedded Multiplier Block
Input Registers
You can send each multiplier input signal into an input register or directly into the
multiplier in 9- or 18-bit sections, depending on the operational mode of the
multiplier. Each multiplier input signal can be sent through a register independently
of other input signals. For example, you can send the multiplier Data Asignal through
a register and send the Data Bsignal directly to the multiplier.
The following control signals are available to each input register in the embedded
multiplier:
■
■
■
clock
clock enable
asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
Multiplier Stage
The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18
multipliers as well as other multipliers in between these configurations. Depending
on the data width or operational mode of the multiplier, a single embedded multiplier
can perform one or two multiplications in parallel. For multiplier information, refer to
“Operational Modes” on page 4–5.
Each multiplier operand is a unique signed or unsigned number. Two signals, signa
and signb, control an input of a multiplier and determine if the value is signed or
unsigned. If the signasignal is high, the Data Aoperand is a signed number. If the
signasignal is low, the Data Aoperand is an unsigned number.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
4–5
Operational Modes
Table 4–3 lists the sign of the multiplication results for the various operand sign
representations. The results of the multiplication are signed if any one of the operands
is a signed value.
Table 4–3. Multiplier Sign Representation
Data A
Data B
Result
signa Value
Unsigned
Unsigned
Signed
Logic Level
Low
signb Value
Unsigned
Signed
Logic Level
Low
Unsigned
Signed
Signed
Signed
Low
High
High
Unsigned
Signed
Low
Signed
High
High
Each embedded multiplier block has only one signaand one signbsignal to control
the sign representation of the input data to the block. If the embedded multiplier
block has two 9 × 9 multipliers, the Data Ainput of both multipliers share the same
signasignal, and the Data Binput of both multipliers share the same signbsignal.
You can dynamically change the signaand signbsignals to modify the sign
representation of the input operands at run time. You can send the signaand signb
signals through a dedicated input register. The multiplier offers full precision,
regardless of the sign representation.
1
When the signaand signbsignals are unused, the Quartus II software sets the
multiplier to perform unsigned multiplication by default.
Output Registers
You can register the embedded multiplier output using output registers in either
18- or 36-bit sections, depending on the operational mode of the multiplier. The
following control signals are available for each output register in the embedded
multiplier:
■
■
■
clock
clock enable
asynchronous clear
All input and output registers in a single embedded multiplier are fed by the same
clock, clock enable, and asynchronous clear signals.
Operational Modes
You can use an embedded multiplier block in one of two operational modes,
depending on the application needs:
■
One 18-bit × 18-bit multiplier
■
Up to two 9-bit × 9-bit independent multipliers
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
4–6
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Operational Modes
1
You can also use embedded multipliers of the Cyclone III device family to implement
multiplier adder and multiplier accumulator functions, in which the multiplier
portion of the function is implemented using embedded multipliers, and the adder or
accumulator function is implemented in logic elements (LEs).
18-Bit Multipliers
You can configure each embedded multiplier to support a single 18 × 18 multiplier for
input widths of 10 to 18 bits.
Figure 4–3 shows the embedded multiplier configured to support an 18-bit multiplier.
Figure 4–3. 18-Bit Multiplier Mode
signa
signb
aclr
clock
ena
D
Q
Data A [17..0]
Data B [17..0]
ENA
Data Out [35..0]
D
Q
CLRN
ENA
CLRN
D
Q
ENA
CLRN
18 × 18 Multiplier
Embedded Multiplier
All 18-bit multiplier inputs and results are independently sent through registers. The
multiplier inputs can accept signed integers, unsigned integers, or a combination of
both. Also, you can dynamically change the signaand signbsignals and send these
signals through dedicated input registers.
9-Bit Multipliers
You can configure each embedded multiplier to support two 9 × 9 independent
multipliers for input widths of up to 9 bits.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
4–7
Operational Modes
Figure 4–4 shows the embedded multiplier configured to support two 9-bit
multipliers.
Figure 4–4. 9-Bit Multiplier Mode
signa
signb
aclr
clock
ena
D
Q
Data A 0 [8..0]
Data B 0 [8..0]
ENA
Data Out 0 [17..0]
D
Q
CLRN
ENA
CLRN
D
Q
ENA
CLRN
9 × 9 Multiplier
D
Q
Data A 1 [8..0]
Data B 1 [8..0]
ENA
Data Out 1 [17..0]
D
Q
CLRN
ENA
CLRN
D
Q
ENA
CLRN
9 × 9 Multiplier
Embedded Multiplier
All 9-bit multiplier inputs and results are independently sent through registers. The
multiplier inputs can accept signed integers, unsigned integers, or a combination of
both. Two 9 × 9 multipliers in the same embedded multiplier block share the same
signaand signbsignal. Therefore, all the Data Ainputs feeding the same embedded
multiplier must have the same sign representation. Similarly, all the Data Binputs
feeding the same embedded multiplier must have the same sign representation.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
4–8
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Document Revision History
Document Revision History
Table 4–4 lists the revision history for this document.
Table 4–4. Document Revision History
Date
Version
2.3
Changes
December 2011
December 2009
July 2009
Minor text edits.
2.2
Minor changes to the text.
2.1
Made minor correction to the part number.
Updated to include Cyclone III LS information
■ Updated chapter part number.
■ Updated “Introduction” on page 4–1.
■ Updated “Embedded Multiplier Block Overview” on page 4–1.
■ Updated Table 4–1 on page 4–2 and Table 4–2 on page 4–2.
■ Updated “Input Registers” on page 4–4.
Updated chapter to new template.
June 2009
2.0
October 2008
July 2007
1.2
1.1
1.0
Added EP3C120 information.
■ Updated “Introduction” section.
■ Updated Table 4–1 and Table 4–2.
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
5. Clock Networks and PLLs in the
Cyclone III Device Family
July 2012
CIII51006-4.1
CIII51006-4.1
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
with advanced features in the Cyclone® III device family (Cyclone III and
Cyclone III LS devices).
This chapter includes the following sections:
■
■
■
■
■
■
■
■
■
■
■
“Clock Networks” on page 5–1
“PLLs in the Cyclone III Device Family” on page 5–9
“Cyclone III Device Family PLL Hardware Overview” on page 5–10
“Clock Feedback Modes” on page 5–11
“Hardware Features” on page 5–15
“Programmable Bandwidth” on page 5–22
“Phase Shift Implementation” on page 5–22
“PLL Cascading” on page 5–24
“PLL Reconfiguration” on page 5–26
“Spread-Spectrum Clocking” on page 5–33
“PLL Specifications” on page 5–33
Clock Networks
The Cyclone III device family provides up to 16 dedicated clock pins (CLK[15..0]
)
that can drive the global clocks (GCLKs). The Cyclone III device family supports four
dedicated clock pins on each side of the device except EP3C5 and EP3C10 devices.
EP3C5 and EP3C10 devices only support four dedicated clock pins on the left and
right sides of the device.
f
For more information about the number of GCLK networks in each device density,
refer to the Cyclone III Device Family Overview chapter.
GCLK Network
GCLKs drive throughout the entire device, feeding all device quadrants. All resources
in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,
and M9K memory blocks) can use GCLKs as clock sources. Use these clock network
resources for control signals, such as clock enables and clears fed by an external pin.
Internal logic can also drive GCLKs for internally generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
July 2012
Subscribe
5–2
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
Table 5–1 lists the connectivity of the clock sources to the GCLK networks.
Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 1 of 2)
(1)
GCLK Networks
GCLK Network Clock
Sources
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
/
/
/
/
/
/
/
/
/
/
DIFFCLK_0p
DIFFCLK_0n
DIFFCLK_1p
DIFFCLK_1n
DIFFCLK_2p
DIFFCLK_2n
DIFFCLK_3p
DIFFCLK_3n
DIFFCLK_5n
DIFFCLK_5p
v
—
—
v
—
—
—
—
—
—
—
v
v
—
—
—
—
—
—
—
v
v
—
—
—
—
—
—
—
—
—
—
v
v
—
—
—
—
—
—
v
—
v
—
—
—
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v
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v
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v
v
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v
v
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v
v
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v
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v
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v
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v
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v
v
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—
—
—
—
(2)
(2)
CLK10
(2)
/
/
/
/
/
/
DIFFCLK_4n
DIFFCLK_4p
DIFFCLK_7n
DIFFCLK_7p
DIFFCLK_6n
—
—
—
—
—
—
—
—
—
—
—
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—
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v
—
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v
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—
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—
—
v
v
—
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—
v
—
—
—
—
—
—
—
v
—
—
v
—
—
—
v
v
—
—
—
v
v
—
—
—
—
—
—
v
v
—
—
v
—
v
—
CLK11
(2)
CLK12
(2)
CLK13
(2)
CLK14
(2)
CLK15
(2)
DIFFCLK_6p
(3)
PLL1_C0
PLL1_C1
PLL1_C2
PLL1_C3
PLL1_C4
PLL2_C0
PLL2_C1
PLL2_C2
PLL2_C3
PLL2_C4
PLL3_C0
PLL3_C1
PLL3_C2
PLL3_C3
PLL3_C4
PLL4_C0
v
—
v
—
—
—
—
—
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—
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v
—
v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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v
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—
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–3
Clock Networks
Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 2 of 2)
(1)
GCLK Networks
GCLK Network Clock
Sources
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
PLL4_C1
PLL4_C2
PLL4_C3
PLL4_C4
DPCLK0
DPCLK1
DPCLK7
—
—
—
—
v
—
—
—
—
—
—
v
—
—
—
—
—
—
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—
—
—
—
—
—
—
—
v
—
—
—
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v
—
v
—
—
—
—
v
—
v
—
—
—
—
v
—
—
—
v
—
—
v
—
—
(4)
CDPCLK0, or
—
—
—
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2), (5)
CDPCLK7
DPCLK2
(4)
CDPCLK1, or
—
—
v
v
(2), (5)
CDPCLK2
DPCLK5
DPCLK7
DPCLK4
DPCLK6
DPCLK6
(4)
(2)
(4)
(2)
(4)
—
—
—
—
—
—
—
—
—
—
v
—
—
—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
CDPCLK5, or
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2), (5)
CDPCLK6
DPCLK3
(4)
CDPCLK4, or
—
v
v
(2), (5)
CDPCLK3
DPCLK8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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—
—
—
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—
—
—
—
—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
v
DPCLK11
DPCLK9
DPCLK10
DPCLK5
DPCLK2
DPCLK4
DPCLK3
Notes to Table 5–1:
(1) EP3C5 and EP3C10 devices only have GCLK networks 0 to 9.
(2) These pins apply to all devices in the Cyclone III device family except EP3C5 and EP3C10 devices.
(3) EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2.
(4) This pin applies only to EP3C5 and EP3C10 devices.
(5) Only one of the two CDPCLKpins can feed the clock control block. You can use the other pin as a regular I/O pin.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–4
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
If you do not use dedicated clock pins to feed the GCLKs, you can use them as
general-purpose input pins to feed the logic array. However, when using them as
general-purpose input pins, they do not have support for an I/O register and must
use LE-based registers in place of an I/O register.
f
For more information about how to connect the clock and PLL pins, refer to the
Cyclone III Device Family Pin Connection Guidelines on the Altera® website.
Clock Control Block
The clock control block drives GCLKs. Clock control blocks are located on each side of
the device, close to the dedicated clock input pins. GCLKs are optimized for
minimum clock skew and delay.
Table 5–2 lists the sources that can feed the clock control block, which in turn feeds the
GCLKs.
Table 5–2. Clock Control Block Inputs
Input
Description
Dedicated clock input pins can drive clocks or global signals, such as
synchronous and asynchronous clears, presets, or clock enables onto
given GCLKs.
Dedicated clock inputs
DPCLKand CDPCLKI/O pins are bidirectional dual function pins that
are used for high fan-out control signals, such as protocol signals,
TRDYand IRDYsignals for PCI, via the GCLK. Clock control blocks
that have inputs driven by dual-purpose clock I/O pins are not able to
drive PLL inputs.
Dual-purpose clock
(DPCLKand CDPCLK)
I/O input
PLL outputs
PLL counter outputs can drive the GCLK.
You can drive the GCLK through logic array routing to enable internal
logic elements (LEs) to drive a high fan-out, low-skew signal path.
Clock control blocks that have inputs driven by internal logic are not
able to drive PLL inputs.
Internal logic
In the Cyclone III device family, dedicated clock input pins, PLL counter outputs,
dual-purpose clock I/O inputs, and internal logic can all feed the clock control block
for each GCLK.
1
Normal I/O pins cannot drive the PLL input clock port.
The output from the clock control block in turn feeds the corresponding GCLK. The
GCLK can drive the PLL input if the clock control block inputs are outputs of another
PLL or dedicated clock input pins. The clock control blocks are at the device
periphery; there are a maximum of 20 clock control blocks available per Cyclone III
device family.
The control block has two functions:
■
■
Dynamic GCLK clock source selection (not applicable for DPCLKor CDPCLKand
internal logic input)
GCLK network power down (dynamic enable and disable)
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–5
Clock Networks
Figure 5–1 shows the clock control block.
Figure 5–1. Clock Control Block
Clock Control Block
Internal Logic
Enable/
Disable
Global
Clock
DPCLK or CDPCLK
Static Clock Select (3)
Static Clock
Select (3)
C0
C1
CLK[n + 3]
inclk1
inclk0
f
CLK[n + 2]
CLK[n + 1]
CLK[n]
IN
C2
PLL
C3
C4
CLKSWITCH (1)
CLKSELECT[1..0] (2)
Internal Logic (4)
Notes to Figure 5–1:
(1) The clkswitchsignal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
output of the multiplexer is the input clock (fIN) for the PLL.
(2) The clkselect[1..0]signals are fed by internal logic and is used to dynamically select the clock source for the GCLK when the device is in user
mode.
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) You can use internal logic to enable or disable the GCLK in user mode.
Each PLL generates five clock outputs through the c[4..0]counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in Figure 5–1.
f
For more information about how to use the clock control block in the Quartus® II
software, refer to the Clock Control Block (ALTCLKCTRL) Megafunction User Guide.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–6
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
GCLK Network Clock Source Generation
Figure 5–2 shows Cyclone III device family PLLs, clock inputs, and clock control
block location for different device densities.
(1)
Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family
DPCLK[11.10]
DPCLK[9..8]
CDPCLK7
CDPCLK6
CLK[11..8]
2
2
4
4
(3)
PLL
2
PLL
3
4
5
CDPCLK0
CDPCLK5
(3)
(2)
(2)
2
4
4
Clock Control
Block (1)
5
2
GCLK[19..0]
20
DPCLK0
DPCLK7
CLK[7..4]
DPCLK6
20
20
CLK[3..0]
DPCLK1
4
4
20
GCLK[19..0]
Clock Control
Block (1)
2
4
4
5
2
4
(2)
(2)
(3)
CDPCLK4
CDPCLK1
5
PLL
4
PLL
1
(3)
4
4
2
2
CDPCLK3
CDPCLK2
CLK[15..12]
DPCLK[3..2]
DPCLK[5..4]
Notes to Figure 5–2:
(1) There are five clock control blocks on each side.
(2) Only one of the corner CDPCLKpins in each corner can feed the clock control block at a time. You can use the other CDPCLKpins as
general-purpose I/O pins.
(3) Remote clock pins can feed PLLs over dedicated clock paths. However, these paths are not fully compensated.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–7
Clock Networks
The inputs to the five clock control blocks on each side must be chosen from among
the following clock sources:
■
■
■
Four clock input pins
Five PLL counter outputs
Two DPCLKpins and two CDPCLKpins from both the left and right sides, and four
DPCLKpins and two CDPCLKpins from both the top and bottom
■
Five signals from internal logic
From the clock sources listed above, only two clock input pins, two PLL clock outputs,
one DPCLKor CDPCLKpin, and one source from internal logic can drive into any given
clock control block, as shown in Figure 5–1 on page 5–5.
Out of these five inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–3 shows a simplified version of the five clock control blocks on each side of
the Cyclone III device family periphery.
(1)
Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family
4
Clock Input Pins
5
PLL Outputs
Clock
Control
Block
2
5
CDPCLK
GCLK
2 or 4
DPCLK
5
Internal Logic
Five Clock Control
Blocks on Each Side
of the Device
Note to Figure 5–3:
(1) The left and right sides of the device have two DPCLKpins; the top and bottom of the device have four DPCLKpins.
GCLK Network Power Down
You can disable the Cyclone III device family GCLK (power down) by using both
static and dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable of the GCLKs in the Cyclone III device family.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page 5–5.
You can set the input clock sources and the clkenasignals for the GCLK multiplexers
through the Quartus II software using the ALTCLKCTRL megafunction.
f
For more information, refer to the Clock Control Block (ALTCLKCTRL) Megafunction
User Guide.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–8
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
clkena Signals
The Cyclone III device family supports clkenasignals at the GCLK network level.
This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the
output clock, the PLL does not need a resynchronization or re-lock period because the
circuit gates off the clock at the clock network level. In addition, the PLL can remain
locked independent of the clkenasignals because the loop-related counters are not
affected.
Figure 5–4 shows how to implement the clkenasignal.
Figure 5–4. clkena Implementation
clkena
clkin
clkena_out
D
Q
clk_out
1
1
The clkenacircuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in Figure 5–4.
Figure 5–5 shows the waveform example for a clock output enable. The clkenasignal
is sampled on the falling edge of the clock (clkin).
This feature is useful for applications that require low power or sleep mode.
Figure 5–5. clkena Implementation: Output Enable
clkin
clkena
clk_out
The clkenasignal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–9
PLLs in the Cyclone III Device Family
Altera recommends using the clkenasignals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by deasserting the clkenasignal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the
clkenasignal. The exact number of clock cycles you must wait before enabling the
secondary clock is design-dependent. You can build custom logic to ensure glitch-
free transition when switching between different clock sources.
PLLs in the Cyclone III Device Family
The Cyclone III device family offers up to four PLLs that provide robust clock
management and synthesis for device clock management, external system clock
management, and high-speed I/O interfaces.
f
For more information about the number of PLLs in each device density, refer to the
Cyclone III Device Family Overview chapter.
The Cyclone III device family PLLs have the same core analog structure.
Table 5–3 lists the features available in the Cyclone III device family PLLs.
Table 5–3. Cyclone III Device Family PLL Hardware Features
Hardware Features
C (output counters)
Availability
5
(1)
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
1 to 512
1 single-ended or 1 differential pair
4 single-ended or 2 differential pairs
(2)
Spread-spectrum input clock tracking
PLL cascading
v
Through GCLK
Source-Synchronous Mode, No Compensation
Mode, Normal Mode, and Zero Delay Buffer Mode
Compensation modes
(3)
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
User mode reconfiguration
Loss of lock detection
Notes to Table 5–3:
Down to 96-ps increments
v
v
v
v
v
(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a
non-50% duty cycle, the post-scale counters range from 1 through 256.
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.
(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
degree increments, the Cyclone III device family can shift all output frequencies in increments of at least 45°.
Smaller degree increments are possible depending on the frequency and divide parameters.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–10
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Cyclone III Device Family PLL Hardware Overview
Cyclone III Device Family PLL Hardware Overview
This section gives a hardware overview of the Cyclone III device family PLL.
Figure 5–6 shows a simplified block diagram of the major components of the PLL of
the Cyclone III device family.
(1)
Figure 5–6. Cyclone III Device Family PLL Block Diagram
lock
LOCK
circuit
÷C0
÷C1
÷C2
Clock inputs
from pins
4
8
÷n
clkswitch
8
÷2 (2)
inclk0
inclk1
LF
VCO
PFD
CP
Clock
Switchover
Block
PLL
output
mux
clkbad0
GCLKs
÷C3
÷C4
GCLK(3)
clkbad1
VCO
Range
Detector
VCOOVRR
VCOUNDR
External clock
output
activeclock
pfdena
÷M
no compensation;
ZDB mode
GCLK
networks
source-synchronous;
normal mode
Notes to Figure 5–6:
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
1
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the fVCO specification specified in the Cyclone III Device Data Sheet and
Cyclone III LS Device Data Sheet chapters.
External Clock Outputs
Each PLL of the Cyclone III device family supports one single-ended clock output or
one differential clock output. Only the C0 output counter can feed the dedicated
external clock outputs, as shown in Figure 5–7, without going through the GCLK.
Other output counters can feed other I/O pins through the GCLK.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–11
Clock Feedback Modes
Figure 5–7 shows the external clock outputs for PLLs.
Figure 5–7. External Clock Outputs for PLLs
C0
C1
C2
C3
C4
PLL #
clkena 0 (1)
clkena 1 (1)
PLL #_CLKOUTp (2)
PLL #_CLKOUTn (2)
Notes to Figure 5–7:
(1) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
(2) PLL#_CLKOUTpand PLL#_CLKOUTnpins are dual-purpose I/O pins that you can use as one single-ended or one
differential clock output.
Each pin of a differential output pair is 180° out of phase. The Quartus II software
places the NOT gate in your design into the I/O element to implement 180° phase
with respect to the other pin in the pair. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as well as LVDS,
LVPECL, differential HSTL, and differential SSTL.
f
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the I/O Features in the Cyclone III Device Family chapter.
Cyclone III device family PLLs can drive out to any regular I/O pin through the
GCLK. You can also use the external clock output pins as general purpose I/O pins if
external PLL clocking is not required.
Clock Feedback Modes
Cyclone III device family PLLs support up to four different clock feedback modes.
Each mode allows clock multiplication and division, phase shifting, and
programmable duty cycle.
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Feedback Modes
1
Input and output delays are fully compensated by the PLL only when you are using
the dedicated clock input pins associated with a given PLL as the clock sources. For
example, when using PLL1 in normal mode, the clock delays from the input pin to the
PLL and the PLL clock output-to-destination register are fully compensated, provided
that the clock input pin is one of the following four pins:
■
■
■
■
CLK0
CLK1
CLK2
CLK3
When driving the PLL using the GCLK network, the input and output delays may not
be fully compensated in the Quartus II software.
Source-Synchronous Mode
If the data and clock arrive at the same time at the input pins, the phase relationship
between the data and clock remains the same at the data and clock ports of any I/O
element input register.
Figure 5–8 shows an example waveform of the data and clock in this mode. Use this
mode for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O standard is used.
Figure 5–8. Phase Relationship Between Data and Clock in Source-Synchronous Mode
Data pin
PLL reference
clock at input pin
Data at register
Clock at register
Source-synchronous mode compensates for delay of the clock network used,
including any difference in the delay between the following two paths:
■
Data pin to I/O element register input
■
Clock input pin to the PLL phase-frequency detector (PFD) input
1
Set the input pin to the register delay chain in the I/O element to zero in the
Quartus II software for all data pins clocked by a source-synchronous mode PLL.
Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II
software.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–13
Clock Feedback Modes
No Compensation Mode
In no compensation mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because clock feedback into the PFD does not pass
through as much circuitry. Both the PLL internal and external clock outputs are
phase-shifted with respect to the PLL clock input.
Figure 5–9 shows a waveform example of the phase relationship of the PLL clock in
this mode.
Figure 5–9. Phase Relationship Between PLL Clocks in No Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1), (2)
External PLL Clock
Outputs (2)
Notes to Figure 5–9:
(1) Internal clocks fed by the PLL are phase-aligned to each other.
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the PLL fully compensates the delay introduced by the
GCLK network.
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Feedback Modes
Figure 5–10 shows a waveform example of the phase relationship of the PLL clocks in
this mode.
Figure 5–10. Phase Relationship Between PLL Clocks in Normal Mode
Phase Aligned
PLL Reference
Clock at the Input pin
PLL Clock at the
Register Clock Port
External PLL Clock
Outputs (1)
Note to Figure 5–10:
(1) The external clock output can lead or lag the PLL internal clock signals.
Zero Delay Buffer Mode
In zero delay buffer (ZDB) mode, the external clock output pin is phase-aligned with
the clock input pin for zero delay through the device. When using this mode, use the
same I/O standard on the input clock and output clocks to guarantee clock alignment
at the input and output pins.
Figure 5–11 shows an example waveform of the phase relationship of the PLL clocks
in ZDB mode.
Figure 5–11. Phase Relationship Between PLL Clocks in ZDB Mode
Phase Aligned
PLL Reference Clock
at the Input Pin
PLL Clock
at the Register Clock Port
External PLL Clock Output
at the Output Pin
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–15
Hardware Features
Hardware Features
Cyclone III device family PLLs support several features for general-purpose clock
management. This section discusses clock multiplication and division
implementation, phase shifting implementations, and programmable duty cycles.
Clock Multiplication and Division
Each Cyclone III device family PLL provides clock synthesis for PLL output ports
using M/(N*post-scale counter) scaling factors. The input clock is divided by a
pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop
drives the VCO to match fIN (M/N). Each output port has a unique post-scale counter
that divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO value is the least common multiple of the output frequencies
that meets its frequency specifications. For example, if output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz in the VCO range). Then, the post-scale
counters scale down the VCO frequency for each output port.
There is one pre-scale counter, N, and one multiply counter, M, per PLL, with a range
of 1 to 512 for both M and N. The N counter does not use duty cycle control because
the purpose of this counter is only to calculate frequency division. There are five
generic post-scale counters per PLL that can feed GCLKs or external clock outputs.
These post-scale counters range from 1 to 512 with a 50% duty cycle setting. The
post-scale counters range from 1 to 256 with any non-50% duty cycle setting. The sum
of the high/low count values chosen for a design selects the divide value for a given
counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
ALTPLL megafunction.
1
Phase alignment between output counters are determined using the tPLL_PSERR
specification.
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
Post-Scale Counter Cascading
Cyclone III device family PLLs support post-scale counter cascading to create
counters larger than 512. This is implemented by feeding the output of one C counter
into the input of the next C counter, as shown in Figure 5–12.
Figure 5–12. Counter Cascading
VCO Output
C0
VCO Output
C1
VCO Output
C2
VCO Output
C3
VCO Output
C4
VCO Output
When cascading counters to implement a larger division of the high-frequency VCO
clock, the cascaded counters behave as one counter with the product of the individual
counter settings.
For example, if C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.
1
Post-scale counter cascading is automatically set by the Quartus II software in the
configuration file. Post-scale counter cascading cannot be performed using the PLL
reconfiguration.
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. You can achieve
the duty cycle setting by a low and high time count setting for the post-scale counters.
The Quartus II software uses the frequency input and the required multiply or divide
rate to determine the duty cycle choices. The post-scale counter value determines the
precision of the duty cycle. The precision is defined by 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty
cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift allows the
generation of precise non-overlapping clocks.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–17
Hardware Features
PLL Control Signals
You can use the following three signals to observe and control the PLL operation and
resynchronization.
pfdena
Use the pfdenasignal to maintain the last locked frequency so that your system has
time to store its current settings before shutting down. The pfdenasignal controls the
PFD output with a programmable gate. If you disable the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term drift to a lower
frequency.
areset
The aresetsignal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When driven high, the PLL
counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is
then set back to its nominal setting. When driven low again, the PLL resynchronizes
to its input as it re-locks.
You must include the aresetsignal in your designs if one of the following conditions
is true:
■
PLL reconfiguration or clock switchover enabled in your design
■
Phase relationships between the PLL input clock and output clocks must be
maintained after a loss-of-lock condition
1
1
If the input clock to the PLL is toggling or unstable upon power up, assert the areset
signal after the input clock is stable and within specifications.
locked
The lockedoutput indicates that the PLL has locked onto the reference clock and the
PLL clock outputs are operating at the desired phase and frequency set in the
Quartus II MegaWizard™ Plug-in Manager.
Altera recommends that you use the aresetand lockedsignals in your designs to
control and observe the status of your PLL.
This implementation is illustrated in Figure 5–13.
Figure 5–13. Locked Signal Implementation
locked
V
CC
OFF
D
Q
PLL
locked
areset
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Volume 1
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
If you use the SignalTap® II tool to probe the lockedsignal before the D flip-flop, the
lockedsignal goes low only when aresetis deasserted. If the aresetsignal is not
enabled, the extra logic is not implemented in the ALTPLL megafunction.
f
For more information about the PLL control signals, refer to the Phase-Locked Loop
(ALTPLL) Megafunction User Guide.
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops running.
Your design can automatically perform clock switchover when the clock is no longer
toggling, or based on the user control signal, clkswitch
.
Automatic Clock Switchover
Cyclone III device family PLLs support a fully configurable clock switchover
capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also sends
out three status signals—clkbad[0], clkbad[1], and activeclock—from the PLL to
implement a custom switchover circuit. You can select a clock source at the backup
clock by connecting it to the inclk1port of the PLL in your design.
Figure 5–14 shows the block diagram of the switchover circuit built into the PLL.
Figure 5–14. Automatic Clock Switchover Circuit
clkbad0
clkbad1
Activeclock
Switchover
State
Machine
Clock
Sense
clksw
clkswitch
(provides manual
switchover support)
inclk0
inclk1
n Counter
PFD
refclk
muxout
fbclk
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–19
Hardware Features
There are two ways to use the clock switchover feature:
Use the switchover circuitry for switching from inclk0to inclk1running at the
■
same frequency. For example, in applications that require a redundant clock with
the same frequency as the reference clock, the switchover state machine generates
a signal that controls the multiplexer select input shown in Figure 5–14. In this
case, inclk1becomes the reference clock for the PLL. This automatic switchover
can switch back and forth between the inclk0and inclk1clocks any number of
times, when one of the two clocks fails and the other clock is available.
■
Use the clkswitchinput for user- or system-controlled switch conditions. This is
possible for same-frequency switchover or to switch between inputs of different
frequencies. For example, if inclk0is 66 MHz and inclk1is 200 MHz, you must
control the switchover because the automatic clock-sense circuitry cannot monitor
primary and secondary clock frequencies with a frequency difference of more than
20%. This feature is useful when clock sources can originate from multiple cards
on the backplane, requiring a system-controlled switchover between frequencies
of operation. Choose the secondary clock frequency so the VCO operates in the
recommended frequency range. Also, set the M, N, and C counters accordingly to
keep the VCO operating frequency in the recommended range.
Figure 5–15 shows a waveform example of the switchover feature when using
automatic loss of clock detection. Here, the inclk0signal remains low. After the
inclk0signal remains low for approximately two clock cycles, the clock-sense
circuitry drives the clkbad[0]signal high. Also, because the reference clock signal is
not toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to inclk1
.
(1)
Figure 5–15. Automatic Switchover Upon Clock Loss Detection
inclk0
inclk1
(1)
muxout
clkbad0
clkbad1
activeclock
Note to Figure 5–15:
(1) Switchover is enabled on the falling edge of inclk0or inclk1, depending on which clock is available. In this figure,
switchover is enabled on the falling edge of inclk1
.
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
Manual Override
If you are using the automatic switchover, you must switch input clocks with the
manual override feature with the clkswitchinput.
Figure 5–16 shows an example of a waveform illustrating the switchover feature
when controlled by clkswitch. In this case, both clock sources are functional and
inclk0is selected as the reference clock. A low-to-high transition of the clkswitch
signal starts the switchover sequence. The clkswitchsignal must be high for at least
three clock cycles (at least three of the longer clock period if inclk0and inclk1have
different frequencies). On the falling edge of inclk0, the reference clock of the counter,
muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the
reference clock multiplexer switches from inclk0to inclk1as the PLL reference. On
the falling edge of inclk1, the reference clock multiplexer switches from inclk0to
inclk1as the PLL reference, and the activeclocksignal changes to indicate which
clock is currently feeding the PLL.
In this mode, the activeclocksignal mirrors the clkswitchsignal. As both blocks are
still functional during the manual switch, neither clkbadsignals go high. Because the
switchover circuit is positive edge-sensitive, the falling edge of the clkswitchsignal
does not cause the circuit to switch back from inclk1to inclk0. When the clkswitch
signal goes high again, the process repeats. The clkswitchsignal and the automatic
switch only works depending on the availability of the clock that is switched to. If the
clock is unavailable, the state machine waits until the clock is available.
1
If CLKSWITCH = 1, the automatic switchover function is overridden. While the
clkswitchsignal is high, further switchover action is blocked.
(1)
Figure 5–16. Clock Switchover Using the clkswitch Control
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
Note to Figure 5–16:
(1) Both inclk0and inclk1must be running when the clkswitchsignal goes high to start a manual clock switchover
event.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–21
Hardware Features
Manual Clock Switchover
Cyclone III device family PLLs support manual switchover, in which the clkswitch
signal controls whether inclk0or inclk1is the input clock to the PLL. The
characteristics of a manual switchover is similar to the manual override feature in an
automatic clock switchover, in which the switchover circuit is edge-sensitive. When
the clkswitchsignal goes high, the switchover sequence starts. The falling edge of the
clkswitchsignal does not cause the circuit to switch back to the previous input clock.
f
For more information about PLL software support in the Quartus II software, refer to
the Phase-Locked Loop (ALTPLL) Megafunction User Guide.
Guidelines
Use the following guidelines to design with clock switchover in PLLs:
■
Clock loss detection and automatic clock switchover requires that the inclk0and
inclk1frequencies be within 20% of each other. Failing to meet this requirement
causes the clkbad[0]and clkbad[1]signals to function improperly.
■
When using manual clock switchover, the difference between inclk0and inclk1
can be more than 20%. However, differences between the two clock sources
(frequency, phase, or both) can cause the PLL to lose lock. Resetting the PLL
ensures that the correct phase relationships are maintained between the input and
output clocks.
1
Both inclk0and inclk1must be running when the clkswitchsignal goes high to
start the manual clock switchover event. Failing to meet this requirement causes the
clock switchover to malfunction.
■
Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. When referencing input clock changes, the
low-bandwidth PLL reacts slower than a high-bandwidth PLL. When the
switchover happens, the low-bandwidth PLL propagates the stopping of the clock
to the output slower than the high-bandwidth PLL. The low-bandwidth PLL
filters out jitter on the reference clock. However, you must be aware that the
low-bandwidth PLL also increases lock time.
■
■
After a switchover occurs, there may be a finite resynchronization period for the
PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
re-lock is dependent on the PLL configuration.
If the phase relationship between the input clock to the PLL and output clock from
the PLL is important in your design, assert aresetfor 10 ns after performing a
clock switchover. Wait for the locked signal (or gated lock) to go high before
re-enabling the output clocks from the PLL.
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Programmable Bandwidth
■
Figure 5–17 shows how the VCO frequency gradually decreases when the primary
clock is lost and then increases as the VCO locks on to the secondary clock. After
the VCO locks on to the secondary clock, some overshoot can occur (an
over-frequency condition) in the VCO frequency.
Figure 5–17. VCO Switchover Operating Frequency
Primary Clock Stops Running
Frequency Overshoot
Switchover Occurs
VCO Tracks Secondary Clock
ΔF
vco
■
Disable the system during switchover if the system is not tolerant to frequency
variations during the PLL resynchronization period. You can use the clkbad[0]
and clkbad[1]status signals to turn off the PFD (pfdena
= 0) so the VCO
maintains its last frequency. You can also use the switchover state machine to
switch over to the secondary clock. Upon enabling the PFD, output clock enable
signals (clkena) can disable clock outputs during the switchover and
resynchronization period. After the lock indication is stable, the system can
re-enable the output clock or clocks.
Programmable Bandwidth
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. Cyclone III device family PLLs provide advanced control of the PLL
bandwidth using the programmable characteristics of the PLL loop, including loop
filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines
the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.
Phase Shift Implementation
Phase shift is used to implement a robust solution for clock delays in the Cyclone III
device family. Phase shift is implemented with a combination of the VCO phase
output and the counter starting time. The VCO phase output and counter starting
time are the most accurate methods of inserting delays, because they are purely based
on counter settings, which are independent of process, voltage, and temperature.
You can phase shift the output clocks from the Cyclone III device family PLLs in
either:
■
Fine resolution using VCO phase taps, or
Coarse resolution using counter starting time
■
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July 2012 Altera Corporation
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5–23
Phase Shift Implementation
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. Equation 5–1
shows the minimum delay time that you can insert using this method.
Equation 5–1. Fine Resolution Phase Shift
TVCO
fine = ------------- = --------------- = -------------------
8fVCO 8MfREF
1
N
8
Note to Equation 5–1:
(1) fREF is the input reference clock frequency
For example, if fREF is 100 MHz, N = 1, and M = 8, then fVCO = 800 MHz, and
fine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that
depends on reference clock frequency and counter settings.
Coarse resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks. Equation 5–2 shows the coarse phase
shift.
Equation 5–2. Coarse Resolution Phase Shift
C – 1
fVCO MfREF
C – 1N
coarse = ------------ = ----------------------
Note to Equation 5–2:
(1) C is the count value set for the counter delay time—the initial setting in the PLL usage section of the compilation
report in the Quartus II software. If the initial value is 1, C – 1 = 0° phase shift.
July 2012 Altera Corporation
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Cascading
Figure 5–18 shows an example of phase shift insertion using fine resolution through
VCO phase taps method. The eight phases from the VCO are shown and labeled for
reference. In this example, CLK0is based on 0° phase from the VCO and has the C
value for the counter set to one. The CLK1signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1is based on the 135° phase tap
from the VCO and has the C value for the counter set to one. The CLK1signal is also
divided by four. In this case, the two clocks are offset by 3 fine. CLK2is based on the
0° phase from the VCO but has the C value for the counter set to three. This creates a
delay of two coarse (two complete VCO periods).
Figure 5–18. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 t
t
VCO
VCO
0
45
90
135
180
225
270
315
CLK0
t
d0-1
CLK1
CLK2
t
d0-2
You can use the coarse and fine phase shifts to implement clock delays in the
Cyclone III device family.
The Cyclone III device family supports dynamic phase shifting of VCO phase taps
only. The phase shift is configurable for any number of times. Each phase shift takes
about one scanclkcycle, allowing you to implement large phase shifts quickly.
PLL Cascading
Two PLLs are cascaded to each other through the clock network. If your design
cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while
the destination (downstream) PLL must have a high-bandwidth setting.
Cyclone III Device Handbook
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–25
PLL Cascading
Figure 5–19 shows using GCLK while cascading PLLs.
Figure 5–19. PLL Cascading Using GCLK
Five Clock
Control Blocks
Output from PLL
Input to PLL
CLK[8..11]
4
2
PLL
3
PLL
2
2
5
1
20 GCLK[10..14]
GCLK[0:19]
Output from PLL
Remote clock
from two Clock
pins at adjacent
5
2
2
edge of device
1
Five Clock
Control Blocks
20
GCLK[0:19]
4
GCLK[0..4]
CLK[0..3]
CLK[4..7]
GCLK[5..9]
GCLK[0:19]
20
Five Clock
Control Blocks
1
2
2
5
GCLK[0:19]
20
Output from PLL
GCLK[15..19]
1
PLL
1
PLL
4
5
2
2
CLK[12..15]
Five Clock
Control Blocks
Output from PLL
Consider the following guidelines when cascading PLLs:
■
Set the primary PLL to low bandwidth to help filter jitter. Set the secondary PLL to
high bandwidth to be able to track the jitter from the primary PLL. You can view
the Quartus II software compilation report file to ensure the PLL bandwidth
ranges do not overlap. If the bandwidth ranges overlap, jitter peaking can occur in
the cascaded PLL scheme.
1
You can get an estimate of the PLL deterministic jitter and static phase error
(SPE) by using the TimeQuest Timing Analyzer in the Quartus II software.
Use the SDC command "derive_clock_uncertainty" to direct TimeQuest to
generate a report titled "PLLJ_PLLSPE_INFO.txt" in your project directory.
Then, use "set_clock_uncertainty" commands to add jitter and SPE values to
your clock constraints.
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
■
■
Keep the secondary PLL in a reset state until the primary PLL has locked to ensure
the phase settings are correct on the secondary PLL.
You cannot connect either of the inclkports of any PLLs in the cascaded scheme
to clock outputs from PLLs in the cascaded scheme.
PLL Reconfiguration
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In Cyclone III device family PLLs, you can reconfigure
both counter settings and phase shift the PLL output clock in real time. You can also
change the charge pump and loop filter components, which dynamically affects PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.
The ability to reconfigure the PLL in real time is useful in applications that might
operate at multiple frequencies. It is also useful in prototyping environments,
allowing you to sweep PLL output frequencies and adjust the output clock phase
dynamically. For instance, a system generating test patterns is required to generate
and send patterns at 75 or 150 MHz, depending on the requirements of the device
under test. Reconfiguring PLL components in real time allows you to switch between
two such output frequencies in a few microseconds.
You can also use this feature to adjust clock-to-out (tCO) delays in real time by
changing the PLL output clock phase shift. This approach eliminates the need to
regenerate a configuration file with the new PLL settings.
PLL Reconfiguration Hardware Implementation
The following PLL components are configurable in real time:
■
■
■
■
Pre-scale counter (N)
Feedback counter (M)
Post-scale output counters (C0-C4
)
Dynamically adjust the charge pump current (
ICP) and loop filter components
(R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth
Cyclone III Device Handbook
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–27
PLL Reconfiguration
Figure 5–20 shows how to adjust PLL counter settings dynamically by shifting their
new settings into a serial shift register chain or scan chain. Serial data shifts to the scan
chain via the scandataport, and shift registers are clocked by scanclk. The maximum
scanclkfrequency is 100 MHz. After shifting the last bit of data, asserting the
configupdatesignal for at least one scanclkclock cycle synchronously updates the
PLL configuration bits with the data in the scan registers.
Figure 5–20. PLL Reconfiguration Scan Chain
F
VCO
from M counter
from N counter
PFD
LF/K/CP
VCO
scandata
scanclkena
configupdate
inclk
/C4
/C3
/C2
/C1
/C0
/M
/N
scandataout
scandone
scanclk
1
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, not all counters update simultaneously.
To reconfigure the PLL counters, perform the following steps:
1. The scanclkenasignal is asserted at least one scanclkcycle prior to shifting in the
first bit of scandata Dn).
(
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
scanclk
.
3. After all 144 bits have been scanned into the scan chain, the scanclkenasignal is
deasserted to prevent inadvertent shifting of bits in the scan chain.
4. The configupdatesignal is asserted for one scanclkcycle to update the PLL
counters with the contents of the scan chain.
5. The scandonesignal goes high indicating that the PLL is being reconfigured. A
falling edge indicates that the PLL counters have been updated with new settings.
6. Reset the PLL using the aresetsignal if you make any changes to the M, N,
post-scale output C counters, or the
ICP , R, C settings.
7. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–28
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Figure 5–21 shows a functional simulation of the PLL reconfiguration feature.
Figure 5–21. PLL Reconfiguration Scan Chain
scandata
Dn
D0
LSB
scanclk
scanclkena
scandataout
Dn_old
D0_old
Dn
configupdate
scandone
areset
1
When reconfiguring the counter clock frequency, the corresponding counter phase
shift settings cannot be reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the same non-zero phase shift
setting (for example, 90°) on the clock output, you must reconfigure the phase shift
after reconfiguring the counter clock frequency.
Post-Scale Counters (C0 to C4)
You can configure multiply or divide values and duty cycle of post-scale counters in
real time. Each counter has an 8-bit high time setting and an 8-bit low time setting.
The duty cycle is the ratio of output high or low time to the total cycle time, which is
the sum of the two. Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty cycle.
When the rbypassbit is set to 1, it bypasses the counter, resulting in a divide by one.
When this bit is set to 0, the PLL computes the effective division of the VCO output
frequency based on the high and low time counters. For example, if the post-scale
divide factor is 10, the high and low count values is set to 5 and 5 respectively, to
achieve a 50–50% duty cycle. The PLL implements this duty cycle by transitioning the
output clock from high-to-low on the rising edge of the VCO output clock. However, a
4 and 6 setting for the high and low count values, respectively, would produce an
output clock with 40–60% duty cycle.
The rseloddbit indicates an odd divide factor for the VCO output frequency with a
50% duty cycle. For example, if the post-scale divide factor is three, the high and low
time count values are 2 and 1, respectively, to achieve this division. This implies a
67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd
control bit to 1 to achieve this duty cycle despite an odd division factor. The PLL
implements this duty cycle by transitioning the output clock from high-to-low on a
falling edge of the VCO output clock. When you set rselodd= 1, subtract 0.5 cycles
from the high time and add 0.5 cycles to the low time.
For example:
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–29
PLL Reconfiguration
■
■
■
High time count = 2 cycles
Low time count = 1 cycle
rselodd= 1 effectively equals:
■
■
■
High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Scan Chain Description
Cyclone III device family PLLs have a 144-bit scan chain.
Table 5–4 lists the number of bits for each component of the PLL.
Table 5–4. Cyclone III Device Family PLL Reprogramming Bits
Number of Bits
Block Name
Counter
Other
Total
18
18
18
18
18
18
18
9
(1)
(2)
C4
C3
C2
C1
C0
M
16
2
(2)
16
2
(2)
16
2
(2)
16
2
(2)
16
2
(2)
16
2
(2)
N
16
2
Charge Pump
9
0
0
(3)
Loop Filter
9
9
Total number of bits:
Notes to Table 5–4:
144
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
Figure 5–22 shows the scan chain order of the PLL components.
Figure 5–22. PLL Component Scan Chain Order
LF CP
N
M
C0
C1
DATAIN
MSB
LSB
C4
DATAOUT
C3
C2
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–30
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Figure 5–23 shows the scan chain bit order sequence for one PLL post-scale counter in
Cyclone III device family PLLs.
Figure 5–23. Scan Chain Bit Order
HB
8
HB
6
HB
5
HB
1
HB
3
HB
7
HB
9
HB
0
HB
2
HB
4
DATAIN
rbypass
rselodd
LB
5
LB
0
LB
1
LB
2
LB
3
LB
4
LB
6
LB
7
LB
8
LB
9
DATAOUT
f
For more information about the PLL scan chain, refer to the Implementing PLL
Reconfiguration in Cyclone III Devices application note.
Charge Pump and Loop Filter
You can reconfigure the charge pump and loop filter settings to update the PLL
bandwidth in real time. Table 5–5 through Table 5–7 list the possible settings for
charge pump (ICP), loop filter resistor (R), and capacitor (C) values for Cyclone III
device family PLLs.
Table 5–5. Charge Pump Bit Control
CP[2]
CP[1]
CP[0]
Setting (Decimal)
0
0
0
1
0
0
1
1
0
1
1
1
0
1
3
7
Table 5–6. Loop Filter Resistor Value Control
Setting
(Decimal)
LFR[4]
LFR[3]
LFR[2]
LFR[1]
LFR[0]
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
0
3
4
8
16
19
20
24
27
28
30
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–31
PLL Reconfiguration
Table 5–7. Loop Filter Control of High Frequency Capacitor
LFC[1]
LFC[0]
Setting (Decimal)
0
0
1
0
1
1
0
1
3
Bypassing PLL Counter
Bypassing a PLL counter results in a multiply (M counter) or a divide (N, C0 to C4
counters) factor of one.
Table 5–8 lists the settings for bypassing the counters in Cyclone III device family
PLLs.
Table 5–8. PLL Counter Settings
PLL Scan Chain Bits [0..8] Settings
Description
LSB
MSB
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
PLL counter bypassed
(1)
0
PLL counter not bypassed
Note to Table 5–8:
(1) Bypass bit.
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are then ignored.
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust tCO delays by
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
Table 5–9 lists the control signals that are used for dynamic phase shifting.
Table 5–9. Dynamic Phase Shifting Control Signals (Part 1 of 2)
Signal Name
Description
Source
Destination
PLL
reconfiguration
circuit
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to select
all C counters. This signal is registered in the
Logic array or I/O
pins
PHASECOUNTERSELECT[2:0]
PLL on the rising edge of SCANCLK
.
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
PLL
reconfiguration
circuit
Logic array or I/O
pins
PHASEUPDOWN
the rising edge of SCANCLK
.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–32
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Table 5–9. Dynamic Phase Shifting Control Signals (Part 2 of 2)
Signal Name
Description
Source
Destination
PLL
reconfiguration
circuit
Logic array or I/O
pins
PHASESTEP
SCANCLK
Logic high enables dynamic phase shifting.
Free running clock from core used in
combination with PHASESTEPto enable or
disable dynamic phase shifting. Shared with
SCANCLKfor dynamic reconfiguration.
PLL
reconfiguration
circuit
GCLK or I/O pins
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
PLL reconfiguration Logic array or
circuit I/O pins
PHASEDONE
Deasserts on rising edge of SCANCLK
.
Table 5–10 lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECTsetting.
Table 5–10. Phase Counter Select Mapping
PHASECOUNTERSELECT [2]
[1]
0
[0]
0
Selects
0
0
0
0
1
1
1
All Output Counters
M Counter
0
1
1
0
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
1
1
0
0
0
1
1
0
To perform one dynamic phase shift step, you must perform the following
procedures:
1. Set PHASEUPDOWNand PHASECOUNTERSELECTas required.
2. Assert PHASESTEPfor at least two SCANCLKcycles. Each PHASESTEPpulse allows one
phase shift.
3. Deassert PHASESTEPafter PHASEDONEgoes low.
4. Wait for PHASEDONEto go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple phase-
shifts.
PHASEUPDOWNand PHASECOUNTERSELECTsignals are synchronous to SCANCLKand must
meet the tsu and th requirements with respect to the SCANCLKedges.
1
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180, in other words, a phase shift of 5 ns.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–33
Spread-Spectrum Clocking
Figure 5–24 shows the dynamic phase shifting waveform.
Figure 5–24. Timing Diagram for Dynamic Phase Shift
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
a
b
c
d
PHASEDONE goes low
synchronous with SCANCLK
The PHASESTEPsignal is latched on the negative edge of SCANCLK(a,c) and must remain
asserted for at least two SCANCLKcycles. Deassert PHASESTEPafter PHASEDONEgoes low.
On the second SCANCLKrising edge (b,d) after PHASESTEPis latched, the values of
PHASEUPDOWNand PHASECOUNTERSELECTare latched and the PLL starts dynamic
phase-shifting for the specified counters, and in the indicated direction. PHASEDONEis
deasserted synchronous to SCANCLKat the second rising edge (b,d) and remains low
until the PLL finishes dynamic phase-shifting. Depending on the VCO and SCANCLK
frequencies, PHASEDONElow time may be greater than or less than one SCANCLKcycle.
You can perform another dynamic phase-shift after the PHASEDONEsignal goes from
low to high. Each PHASESTEPpulse enables one phase shift. PHASESTEPpulses must be
at least one SCANCLKcycle apart.
f
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer
to the Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction user
guide.
Spread-Spectrum Clocking
The Cyclone III device family can accept a spread-spectrum input with typical
modulation frequencies. However, the device cannot automatically detect that the
input is a spread-spectrum signal. Instead, the input signal looks like deterministic
jitter at the input of the PLL. Cyclone III device family PLLs can track a
spread-spectrum input clock as long as it is in the input jitter tolerance specifications
and the modulation frequency of the input clock is below the PLL bandwidth, which
is specified in the fitter report. The Cyclone III device family cannot generate
spread-spectrum signals internally.
PLL Specifications
f
For information about PLL specifications, refer to the Cyclone III Device Data Sheet and
Cyclone III LS Device Data Sheet chapters.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–34
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Document Revision History
Document Revision History
Table 5–11 lists the revision history for this document.
Table 5–11. Document Revision History (Part 1 of 2)
Date
July 2012
Version
Changes
4.1
Updated Figure 5–2.
■ Minor edits to Equation 5–1 and Equation 5–2.
■ Updated Table 5–5.
■ Updated Figure 5–6, Figure 5–13, Figure 5–19, and Figure 5–24.
November 2011
4.0
■ Updated “Clock Control Block” on page 5–4, “Manual Override” on page 5–20, “PLL
Cascading” on page 5–24, and “Dynamic Phase Shifting” on page 5–31.
■ Minor text edits.
December 2009
July 2009
3.2
3.1
Minor changes to the text.
Made minor correction to the part number.
■ Updated to include Cyclone III LS information.
■ Updated chapter part number.
■ Updated “Clock Networks” on page 5–1.
■ Updated Table 5–1 on page 5–2, Table 5–3 on page 5–9.
■ Updated “PLLs in the Cyclone III Device Family” on page 5–9.
■ Updated “PLL Reconfiguration Hardware Implementation” on page 5–25.
■ Updated “Spread-Spectrum Clocking” on page 5–32.
■ Updated the “Dynamic Phase Shifting” and “Introduction” sections.
■ Updated Figure 5–2, Figure 5–8, and Figure 5–24.
■ Updated chapter to new template.
June 2009
3.0
2.1
October 2008
■ Updated Figure 5–2 and added (Note 3).
■ Updated “clkena Signals” section.
■ Updated Figure 5–8 and added (Note 3).
■ Updated “PLL Control Signals” section.
■ Updated “PLL Cascading” section.
■ Updated “Cyclone III PLL Hardware Overview” section.
■ Updated Table 5–6, Table 5–3, Table 5–7.
■ Updated Figure 5–14.
May 2008
2.0
■ Updated “PLL Cascading” section.
■ Updated “Clock Multiplication and Division” section.
■ Updated Step 6–32 in “PLL Reconfiguration Hardware Implementation” section.
■ Updated “Spread-Spectrum Clocking” section.
■ Updated Figure 5–29.
■ Updated “VCCD and GND” section.
■ Added “Power Consumption” section.
September 2007
1.2
■ Updated “Board Layout” section and removed Figure 5-30.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–35
Document Revision History
Table 5–11. Document Revision History (Part 2 of 2)
Date
Version
Changes
■ Updated document with EP3C120 information.
■ Updated Table 5–1 and Table 5–4 with EP3C120 information.
■ Updated “Clock Control Block” section.
■ Updated locked signal information in “PLL Control Signals” section and added
Figure 5–16.
July 2007
1.1
■ Updated “Manual Override” section, updated “Manual Clock Switchover” section.
■ Added new “Programmable Bandwidth” section with Figure 5–21 and Figure 5–22.
■ Replaced Figure 5-30 with correct diagram.
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
1.0
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
5–36
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Document Revision History
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Section II. I/O Interfaces
This section provides information about Cyclone® III device family I/O features and
high-speed differential and external memory interfaces.
This section includes the following chapters:
■
■
■
Chapter 6, I/O Features in the Cyclone III Device Family
Chapter 7, High-Speed Differential Interfaces in the Cyclone III Device Family
Chapter 8, External Memory Interfaces in the Cyclone III Device Family
f
For information about the revision history for chapters in this section, refer to
“Document Revision History” in each individual chapter.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
II–2
Section II: I/O Interfaces
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
6. I/O Features in the Cyclone III
Device Family
July 2012
CIII51007-3.4
CIII51007-3.4
This chapter describes the I/O features offered in the Cyclone® III device family
(Cyclone III and Cyclone III LS devices).
The I/O capabilities of the Cyclone III device family are driven by the diversification
of I/O standards in many low-cost applications, and the significant increase in
required I/O performance. Altera’s objective is to create a device that accommodates
your key board design needs with ease and flexibility.
The I/O flexibility of the Cyclone III device family is increased from the previous
generation low-cost FPGAs by allowing all I/O standards to be selected on all I/O
banks. Improvements to on-chip termination (OCT) support and the addition of true
differential buffers have eliminated the need for external resistors in many
applications, such as display system interfaces. Altera’s Quartus® II software
completes the solution with powerful pin planning features that allow you to plan
and optimize I/O system designs even before the design files are available.
This chapter contains the following sections:
■
■
■
■
■
■
■
“Cyclone III Device Family I/O Elements” on page 6–1
“I/O Element Features” on page 6–2
“OCT Support” on page 6–7
“I/O Standards” on page 6–11
“Termination Scheme for I/O Standards” on page 6–13
“I/O Banks” on page 6–16
“Pad Placement and DC Guidelines” on page 6–21
Cyclone III Device Family I/O Elements
Cyclone III device family I/O elements (IOEs) contain a bidirectional I/O buffer and
five registers for registering input, output, output-enable signals, and complete
embedded bidirectional single-data rate transfer. I/O pins support various
single-ended and differential I/O standards.
The IOE contains one input register, two output registers, and two output-enable (OE)
registers. The two output registers and two OE registers are used for DDR
applications. You can use input registers for fast setup times and output registers for
fast clock-to-output times. Additionally, you can use OE registers for fast
clock-to-output enable timing. You can use IOEs for input, output, or bidirectional
data paths.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
July 2012
Subscribe
6–2
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Element Features
Figure 6–1 shows the Cyclone III device family IOE structure.
Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration
io_clk[5..0]
Column
or Row
Interconnect
OE
OE Register
V
CCIO
D
Q
Optional
PCI Clamp
clkout
ENA
ACLR
/PRN
V
CCIO
oe_out
Programmable
Pull-Up
aclr/prn
Resistor
Chip-Wide Reset
Output
Pin Delay
Output Register
D
Q
Current Strength Control
Open-Drain Out
Slew Rate Control
ENA
ACLR
sclr/
preset
/PRN
data_in1
data_in0
Bus Hold
Input Pin to
Input Register
Delay
or Input Pin to
Logic Array
Delay
D
Q
clkin
ENA
ACLR
/PRN
oe_in
Input Register
I/O Element Features
The Cyclone III device family IOE offers a range of programmable features for an I/O
pin. These features increase the flexibility of I/O utilization and provide an
alternative to reduce the usage of external discrete components to on-chip, such as a
pull-up resistor and a diode.
Programmable Current Strength
The output buffer for each Cyclone III device family I/O pin has a programmable
current strength control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and Class II, SSTL-18 Class I and Class II,
HSTL-18 Class I and Class II, HSTL-15 Class I and Class II, and HSTL-12 Class I
and Class II I/O standards have several levels of current strength that you can
control.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–3
I/O Element Features
Table 6–1 lists the possible settings for I/O standards with current strength control.
These programmable current strength settings are a valuable tool in helping decrease
the effects of simultaneously switching outputs (SSO) in conjunction with reducing
system noise. The supported settings ensure that the device driver meets the
specifications for IOHand IOLof the corresponding I/O standard.
1
When you use programmable current strength, on-chip series termination is not
available.
(1)
Table 6–1. Programmable Current Strength
IOH/IOL Current Strength Setting (mA)
I/O Standard
Top and Bottom I/O Pins
Left and Right I/O Pins
1.2-V LVCMOS
2, 4, 6, 8, 10,12
2, 4, 6, 8,10
1.5-V LVCMOS
2, 4, 6, 8, 10, 12,16
2, 4, 6, 8, 10, 12,16
1.8-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
3.0-V LVCMOS
2, 4, 6, 8, 10, 12,16
4, 8, 12,16
4, 8, 12,16
4, 8, 12,16
2
2, 4, 6, 8, 10, 12,16
4, 8, 12,16
4, 8, 12,16
4, 8, 12,16
2
3.0-V LVTTL
(2)
3.3-V LVCMOS
(2)
3.3-V LVTTL
4, 8
4, 8
HSTL-12 Class I
HSTL-12 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
BLVDS
8, 10,12
14
8, 10
—
8, 10, 12
16
8, 10, 12
16
8, 10, 12
16
8, 10, 12
16
8, 10, 12
12, 16
8, 10, 12
12, 16
8, 12
8, 12
16
16
8, 12, 16
8, 12, 16
Notes to Table 6–1:
(1) The default setting in the Quartus II software is 50- OCT without calibration for all non-voltage reference and
HSTL/SSTL Class I I/O standards. The default setting is 25- OCT without calibration for HSTL/SSTL Class II I/O
standards.
(2) The default current setting in the Quartus II software is highlighted in bold italic for 3.3-V LVTTL and 3.3-V LVCMOS
I/O standards.
f
For information about how to interface the Cyclone III device family with 3.3-, 3.0-, or
2.5-V systems, refer to the guidelines provided in AN 447: Interfacing Cyclone III and
Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–4
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Element Features
Slew Rate Control
The output buffer for each Cyclone III device family I/O pin provides optional
programmable output slew-rate control. The Quartus II software allows three settings
for programmable slew rate control—0, 1, and 2—where 0 is the slow slew rate and 2
is the fast slew rate. The default setting is 2. A faster slew rate provides high-speed
transitions for high-performance systems. However, these fast transitions may
introduce noise transients in the system. A slower slew rate reduces system noise, but
adds a nominal delay to rising and falling edges. Because each I/O pin has an
individual slew-rate control, you can specify the slew rate on a pin-by-pin basis. The
slew-rate control affects both the rising and falling edges. Slew rate control is available
for single-ended I/O standards with current strength of 8 mA or higher.
1
1
You cannot use the programmable slew rate feature when using OCT with or without
calibration.
You cannot use the programmable slew rate feature when using the 3.0-V PCI,
3.0-V PCI-X, 3.3-V LVTTL, and 3.3-V LVCMOS I/O standards. Only fast slew rate
(default) setting is available.
Open-Drain Output
The Cyclone III device family provides an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables the device to
provide system-level control signals (for example, interrupt and write enable signals)
that are asserted by multiple devices in your system.
Bus Hold
Each Cyclone III device family user I/O pin provides an optional bus-hold feature.
The bus-hold circuitry holds the signal on an I/O pin at its last-driven state. Because
the bus-hold feature holds the last-driven state of the pin until the next input signal is
present, an external pull-up or pull-down resistor is not necessary to hold a signal
level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input threshold
voltage in which noise can cause unintended high-frequency switching. You can select
this feature individually for each I/O pin. The bus-hold output drives no higher than
V
CCIO to prevent overdriving signals.
1
If you enable the bus-hold feature, the device cannot use the programmable pull-up
option. Disable the bus-hold feature when the I/O pin is configured for differential
signals. Bus-hold circuitry is not available on dedicated clock pins.
Bus-hold circuitry is only active after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
f
For the specific sustaining current for each VCCIO voltage level driven through the
resistor and for the overdrive current used to identify the next driven input level, refer
to the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–5
I/O Element Features
Programmable Pull-Up Resistor
Each Cyclone III device family I/O pin provides an optional programmable pull-up
resistor while in user mode. If you enable this feature for an I/O pin, the pull-up
resistor holds the output to the VCCIO level of the output pin’s bank.
1
1
If you enable the programmable pull-up, the device cannot use the bus-hold feature.
Programmable pull-up resistors are not supported on the dedicated configuration,
JTAG, and dedicated clock pins.
When the optional DEV_OEsignal drives low, all I/O pins remain tri-stated even if the
programmable pull-up option is enabled.
Programmable Delay
The Cyclone III device family IOE includes programmable delays to ensure zero hold
times, minimize setup times, increase clock-to-output times, or delay the clock input
signal.
A path in which a pin directly drives a register may require a programmable delay to
ensure zero hold time, whereas a path in which a pin drives a register through
combinational logic may not require the delay. Programmable delays minimize setup
time. The Quartus II Compiler can program these delays to automatically minimize
setup time while providing a zero hold time. Programmable delays can increase the
register-to-pin delays for output registers. Each dual-purpose clock input pin
provides a programmable delay to the global clock networks.
Table 6–2 lists the programmable delays for the Cyclone III device family.
Table 6–2. Cyclone III Device Family Programmable Delay Chain
Programmable Delays
Input pin-to-logic array delay
Input pin-to-input register delay
Output pin delay
Quartus II Logic Option
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Dual-purpose clock input pin
delay
Input delay from dual-purpose clock pin to fan-out destinations
There are two paths in the IOE for an input to reach the logic array. Each of the two
paths can have a different delay. This allows you to adjust delays from the pin to the
internal logic element (LE) registers that reside in two different areas of the device.
You must set the two combinational input delays with the input delay from pin to
internal cells logic option in the Quartus II software for each path. If the pin uses the
input register, one of the delays is disregarded and the delay is set with the input
delay from pin to input register logic option in the Quartus II software.
The IOE registers in each I/O block share the same source for the preset or clear
features. You can program preset or clear for each individual IOE, but you cannot use
both features simultaneously. You can also program the registers to power-up high or
low after configuration is complete. If programmed to power-up low, an
asynchronous clear can control the registers. If programmed to power-up high, an
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–6
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Element Features
asynchronous preset can control the registers. This feature prevents the inadvertent
activation of the active-low input of another device upon power up. If one register in
an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if
they require preset or clear. Additionally, a synchronous reset signal is available for
the IOE registers.
f
For more information about the input and output pin delay settings, refer to the Area
and Timing Optimization chapter in volume 2 of the Quartus II Handbook.
PCI-Clamp Diode
The Cyclone III device family provides an optional PCI-clamp diode enabled input
and output for each I/O pin. Dual-purpose configuration pins support the diode in
user mode if the specific pins are not used as configuration pins for the selected
configuration scheme. For example, if you are using the active serial (AS)
configuration scheme, you cannot use the clamp diode on the ASDOand nCSOpins in
user mode. Dedicated configuration pins do not support the on-chip diode.
The PCI-clamp diode is available for the following I/O standards:
■
■
■
■
■
■
■
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
PCI
PCI-X
If the input I/O standard is 3.3-V LVTTL, 3.3-V LVCMOS, 3.0-V LVTTL,
3.0-V LVCMOS, 2.5-V LVTTL/LVCMOS, PCI, or PCI-X, the PCI clamp diode is
enabled by default in the Quartus II software.
f
For more information about the Cyclone III device family PCI-clamp diode support,
refer to AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V
LVTTL/LVCMOS I/O Systems.
LVDS Transmitter Programmable Pre-Emphasis
The Cyclone III device family true LVDS transmitter supports programmable
pre-emphasis. Programmable pre-emphasis is used to compensate the
frequency-dependent attenuation of the transmission line. It increases the amplitude
of the high-frequency components of the output signal, which cancels out much of the
high-frequency loss of the transmission line.
The Quartus II software allows two settings for programmable pre-emphasis
control—0 and 1, in which 0 is pre-emphasis off and 1 is pre-emphasis on. The default
setting is 1. The amount of pre-emphasis needed depends on the amplification of the
high-frequency components along the transmission line. You must adjust the setting
to suit your designs, as pre-emphasis decreases the amplitude of the low-frequency
component of the output signal as well.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–7
OCT Support
f
For more information about the Cyclone III device family high-speed differential
interface support, refer to the High-Speed Differential Interfaces in the Cyclone III Device
Family chapter.
OCT Support
The Cyclone III device family features OCT to provide output impedance matching
and termination capabilities. OCT helps to prevent reflections and maintain signal
integrity while minimizing the need for external resistors in high pin-count ball grid
array (BGA) packages.
The Cyclone III device family provides output driver on-chip impedance matching
and on-chip series termination for single-ended outputs and bidirectional pins. For
bidirectional pins, OCT is active only for output.
1
When using on-chip series termination, programmable current strength is not
available.
There are two ways to implement OCT in the Cyclone III device family:
■
OCT with calibration
■
OCT without calibration
Table 6–3 lists the I/O standards that support output impedance matching and series
termination.
Table 6–3. Selectable I/O Drivers for On-Chip Series Termination with and Without Calibration Setting
On-Chip Series Termination with Calibration On-Chip Series Termination Without Calibration
Setting, in ohms ()
Setting, in ohms ()
I/O Standard
Row I/O
Column I/O
50, 25
50, 25
50, 25
50, 25
50, 25
50
Row I/O
Column I/O
50, 25
50, 25
50, 25
50, 25
50, 25
50
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
50, 25
50, 25
50, 25
50, 25
50
50, 25
50, 25
50, 25
50, 25
50
1.2-V LVCMOS
SSTL-2 Class I
50
50
SSTL-2 Class II
25
25
25
25
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
50
50
50
50
25
25
25
25
50
50
50
50
25
25
25
25
50
50
50
50
25
25
25
25
50
50
50
50
—
25
—
25
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–8
Chapter 6: I/O Features in the Cyclone III Device Family
OCT Support
On-Chip Series Termination with Calibration
The Cyclone III device family supports on-chip series termination with calibration in
all banks. The on-chip series termination calibration circuit compares the total
impedance of the output buffer to the external 25- 1% or 50- 1% resistors
connected to the RUPand RDNpins, and dynamically adjusts the output buffer
impedance until they match (as shown in Figure 6–2).
The RS shown in Figure 6–2 is the intrinsic impedance of the transistors that make up
the output buffer.
Figure 6–2. Cyclone III Device Family On-Chip Series Termination with Calibration
Cyclone III Device Family
Driver Series Termination
Receiving
Device
V
CCIO
R
S
S
Z
O
R
GND
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in banks 2, 4, 5, and 7. Each calibration block supports each
side of the I/O banks. Because there are two I/O banks sharing the same calibration
block, both banks must have the same VCCIO if both banks enable OCT calibration. If
two related banks have different VCCIOs, only the bank in which the calibration block
resides can enable OCT calibration.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–9
OCT Support
Figure 6–3 shows the top-level view of the OCT calibration blocks placement.
Figure 6–3. Cyclone III Device Family OCT Block Placement
I/O Bank 7
I/O Bank 8
I/O bank with
calibration block
I/O bank without
calibration block
Cyclone III Device Family
Calibration block
coverage
I/O Bank 4
I/O Bank 3
Each calibration block comes with a pair of RUPand RDNpins. When used for
calibration, the RUPpin is connected to VCCIO through an external 25- 1% or
50- 1% resistor for an on-chip series termination value of 25 or 50 ,
respectively. The RDNpin is connected to GND through an external 25- 1% or 50-
1% resistor for an on-chip series termination value of 25 or 50 , respectively. The
external resistors are compared with the internal resistance using comparators. The
resultant outputs of the comparators are used by the OCT calibration block to
dynamically adjust buffer impedance.
During calibration, the resistance of the RUPand RDNpins varies. For an estimate of the
maximum possible current through the external calibration resistors, assume a
minimum resistance of 0 on the RUPand RDNpins during calibration.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–10
Chapter 6: I/O Features in the Cyclone III Device Family
OCT Support
Figure 6–4 shows the external calibration resistors setup on the RUPand RDNpins and
the associated OCT calibration circuitry.
Figure 6–4. Cyclone III Device Family On-Chip Series Termination with Calibration Setup
Cyclone III Device Family OCT with
Calibration with RUP and RDN pins
V
CCIO
External
Calibration
Resistor
RUP
OCT
V
Calibration
Circuitry
CCIO
RDN
External
Calibration
Resistor
GND
RUPand RDNpins go to a tri-state condition when calibration is completed or not
running. These two pins are dual-purpose I/Os and function as regular I/Os if you
do not use the calibration circuit.
On-Chip Series Termination Without Calibration
The Cyclone III device family supports driver impedance matching to the impedance
of the transmission line, which is typically 25 or 50 . When used with the output
drivers, OCT sets the output driver impedance to 25 or 50 . The Cyclone III device
family also supports output driver series termination (RS = 50 ) for SSTL-2 and
SSTL-18.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–11
I/O Standards
Figure 6–5 shows the single-ended I/O standards for OCT without calibration. The RS
shown is the intrinsic transistor impedance.
Figure 6–5. Cyclone III Device Family On-Chip Series Termination Without Calibration
Cyclone III Device Family
Driver Series Termination
Receiving
Device
V
CCIO
R
S
S
Z
O
R
GND
All I/O banks and I/O pins support impedance matching and series termination.
Dedicated configuration pins and JTAG pins do not support impedance matching or
series termination.
On-chip series termination is supported on any I/O bank. VCCIO and VREF must be
compatible for all I/O pins to enable on-chip series termination in a given I/O bank.
I/O standards that support different RS values can reside in the same I/O bank as
long as their VCCIO and VREF are not conflicting.
Impedance matching is implemented using the capabilities of the output driver and is
subject to a certain degree of variation, depending on the process, voltage, and
temperature.
f
For more information about tolerance specification, refer to the Cyclone III Device Data
Sheet and Cyclone III LS Device Data Sheet chapters.
I/O Standards
The Cyclone III device family supports multiple single-ended and differential I/O
standards. Apart from 3.3-, 3.0-, 2.5-, 1.8-, and 1.5-V support, the Cyclone III device
family also supports 1.2-V I/O standards.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–12
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Standards
Table 6–4 lists I/O standards supported by the Cyclone III device family and which
I/O pins support them.
Table 6–4. Cyclone III Device Family Supported I/O Standards and Constraints (Part 1 of 2)
Left and Right
I/O Pins
V
CCIO Level (in V)
Top and Bottom I/O Pins
Standard
Support
I/O Standard
Type
User
CLK,
CLK, UserI/O
Input
Output
PLL_OUT
I/O
DQS
v
v
v
v
DQS
v
v
v
v
Pins
Pins
3.3-V LVTTL,
3.3-V LVCMOS
3.3/3.0/2.5
Single-ended
Single-ended
Single-ended
JESD8-B
JESD8-B
JESD8-5
3.3
3.0
2.5
1.8
v
v
v
v
v
v
v
v
v
(1)
(2)
3.0-V LVTTL,
3.0-V LVCMOS
3.3/3.0/2.5
v
(1)
(2)
2.5-V LVTTL /
LVCMOS
3.3/3.0/2.5
v
(2)
1.8-V LVTTL /
LVCMOS
Single-ended
Single-ended
JESD8-7
1.8/1.5 (2)
v
1.5-V LVCMOS
1.2-V LVCMOS
JESD8-11
1.8/1.5 (2)
1.2
1.5
1.2
v
v
v
v
v
v
v
v
v
v
Single-ended JESD8-12A
SSTL-2 Class I,
SSTL-2 Class II
Voltage
JESD8-9A
referenced
2.5
1.8
1.8
1.5
1.2
1.2
2.5
1.8
1.8
1.5
1.2
1.2
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
v
v
v
v
v
—
SSTL-18 Class I,
SSTL-18 Class II
Voltage
JESD815
referenced
HSTL-18 Class I,
HSTL-18 Class II
Voltage
JESD8-6
referenced
HSTL-15 Class I,
HSTL-15 Class II
Voltage
JESD8-6
referenced
Voltage
HSTL-12 Class I
JESD8-16A
referenced
Voltage
(7)
HSTL-12 Class II
PCI and PCI-X
JESD8-16A
referenced
Single-ended
—
3.0
—
3.0
2.5
—
v
—
v
—
v
v
—
v
—
v
—
v
—
v
—
v
v
—
—
—
v
—
v
—
v
—
—
—
Differential SSTL-2
Class I or Class II
Differential
JESD8-9A
(3)
2.5
—
Differential
SSTL-18 Class I or
Class II
1.8
Differential
JESD815
JESD8-6
JESD8-6
(3)
1.8
—
—
1.8
—
v
—
v
—
v
—
v
—
—
—
—
—
—
—
—
v
v
—
v
—
v
—
v
—
—
—
—
—
—
—
—
v
Differential
HSTL-18 Class I or
Class II
Differential
(3)
1.8
—
Differential
HSTL-15 Class I or
Class II
1.5
—
Differential
(3)
1.5
—
Differential
HSTL-12 Class I or
Class II
1.2
—
Differential
JESD8-16A
—
(3)
1.2
—
(4)
PPDS
Differential
2.5
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–13
Termination Scheme for I/O Standards
Table 6–4. Cyclone III Device Family Supported I/O Standards and Constraints (Part 2 of 2)
Left and Right
I/O Pins
V
CCIO Level (in V)
Top and Bottom I/O Pins
Standard
Support
I/O Standard
Type
User
CLK,
CLK, UserI/O
Input
Output
PLL_OUT
I/O
Pins
DQS
DQS
Pins
(8)
LVDS
Differential
Differential
—
—
2.5
—
2.5
2.5
v
v
v
v
v
v
v
RSDS and
mini-LVDS
—
—
v
(4)
(6)
BLVDS
Differential
Differential
—
—
2.5
2.5
2.5
—
—
—
—
v
—
v
(5)
LVPECL
v
—
v
—
Notes to Table 6–4:
(1) The PCI-clamp diode must be enabled for 3.3-V/3.0-V LVTTL/LVCMOS.
(2) The Cyclone III architecture supports the MultiVolt I/O interface feature that allows Cyclone III devices to interface with I/O systems that have
different supply voltages.
(3) Differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. Differential HSTL and SSTL
inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. Differential HSTL and SSTL are only
supported on CLKpins.
(4) PPDS, mini-LVDS, and RSDS are only supported on output pins.
(5) LVPECL is only supported on clock inputs.
(6) Bus LVDS (BLVDS) output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses LVDS input buffer.
(7) Class I and Class II refer to output termination and do not apply to input. 1.2-V HSTL input is supported at both column and row I/O regardless of
class.
(8) True differential LVDS, RSDS, and mini-LVDS I/O standards are supported in left and right I/O pins while emulated differential LVDS (LVDS_E_3R),
RSDS (RSDS_E_3R), and mini-LVDS (LVDS_E_3R) I/O standards are supported in both left and right, and top and bottom I/O pins.
The Cyclone III device family supports PCI and PCI-X I/O standards at 3.0-V VCCIO
.
The 3.0-V PCI and PCI-X I/O are fully compatible for direct interfacing with 3.3-V PCI
systems without requiring any additional components. The 3.0-V PCI and PCI-X
outputs meet the VIH and VIL requirements of 3.3-V PCI and PCI-X inputs with
sufficient noise margin.
f
For more information about the 3.3/3.0/2.5-V LVTTL and LVCMOS multivolt I/O
support, refer to AN 447: Interfacing Cyclone III and Cyclone IV Devices with 3.3/3.0/2.5-V
LVTTL/LVCMOS I/O Systems.
Termination Scheme for I/O Standards
This section describes recommended termination schemes for voltage-referenced and
differential I/O standards.
The 3.3-V LVTTL, 3.0-V LVTTL and LVCMOS, 2.5-V LVTTL and LVCMOS,
1.8-V LVTTL and LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, 3.0-V PCI, and PCI-X
I/O standards do not specify a recommended termination scheme per the JEDEC
standard.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–14
Chapter 6: I/O Features in the Cyclone III Device Family
Termination Scheme for I/O Standards
Voltage-Referenced I/O Standard Termination
Voltage-referenced I/O standards require an input reference voltage (VREF) and a
termination voltage (VTT). The reference voltage of the receiving device tracks the
termination voltage of the transmitting device, as shown in Figure 6–6 and Figure 6–7.
Figure 6–6. Cyclone III Device Family HSTL I/O Standard Termination
HSTL Class I
Termination
HSTL Class II
V
V
V
TT
TT
TT
50
50
50
50
External
On-Board
Termination
50
V
V
REF
REF
Transmitter
Receiver
Transmitter
Receiver
V
V
TT
V
TT
Cyclone III Device
Cyclone III Device
Family Series OCT
25
TT
Family Series OCT
50 50
50
50
50
OCT with
and without
Calibration
50
V
V
REF
REF
Transmitter
Receiver
Transmitter
Receiver
Figure 6–7. Cyclone III Device Family SSTL I/O Standard Termination
Termination
SSTL Class I
SSTL Class II
V
TT
V
TT
V
TT
50
50
50
25
50
50
External
On-Board
Termination
25
V
V
REF
REF
Transmitter
Receiver
Transmitter
Receiver
Cyclone III Device
Family Series OCT
50
Cyclone III Device
Family Series OCT
25
V
V
TT
V
TT
TT
50
50
50
50
50
OCT with
and without
Calibration
V
REF
V
REF
Transmitter
Receiver
Transmitter
Receiver
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–15
Termination Scheme for I/O Standards
Differential I/O Standard Termination
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the bus (Figure 6–8 and Figure 6–9).
The Cyclone III device family supports differential SSTL-2 and SSTL-18, differential
HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and
differential LVPECL.
Figure 6–8. Cyclone III Device Family Differential HSTL I/O Standard Termination
Termination
Differential HSTL
V
V
TT
TT
External
On-Board
Termination
Receiver
Transmitter
V
V
TT
TT
Cyclone III Device
Family Series OCT
50
OCT
Transmitter
Receiver
(1)
Figure 6–9. Cyclone III Device Family Differential SSTL I/O Standard Termination
Termination
Differential SSTL Class I
Differential SSTL Class II
V
V
V
V
TT TT
TT TT
V
V
TT
TT
50
25
50
50
50
50
50
50
25
25
50
External
On-Board
Termination
25
50
50
Transmitter
Receiver
Transmitter
Receiver
V
TT
V
V
V
V
V
TT
TT
TT
TT
TT
Cyclone III Device
Family Series OCT
50
Cyclone III Device
Family Series OCT
25
50 50 50 50
50
50
50
50
OCT
50
50
Transmitter
Receiver
Transmitter
Receiver
Note to Figure 6–9:
(1) Only Differential SSTL-2 I/O standard supports Class II output.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–16
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
f
For information about the Cyclone III device family differential PPDS, LVDS,
mini LVDS, RSDS I/O, and Bus LVDS (BLVDS) standard termination, refer to the
High-Speed Differential Interfaces in the Cyclone III Device Family chapter.
I/O Banks
I/O pins on the Cyclone III device family are grouped together into I/O banks, and
each bank has a separate power bus. Cyclone III and Cyclone III LS devices have eight
I/O banks, as shown in Figure 6–10. Each device I/O pin is associated with one I/O
bank. All single-ended I/O standards are supported in all banks except HSTL-12
Class II, which is only supported in column I/O banks. All differential I/O standards
are supported in all banks. The only exception is HSTL-12 Class II, which is only
supported in column I/O banks.
(1), (2)
Figure 6–10. Cyclone III Device Family I/O Banks
I/O Bank 8
I/O Bank 7
All I/O Banks Support:
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PPDS
LVDS
RSDS
mini-LVDS
Bus LVDS (7)
LVPECL (3)
SSTL-2 class I and II
SSTL-18 CLass I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II (4)
Differential SSTL-2 (5)
Differential SSTL-18 (5)
Differential HSTL-18 (5)
Differential HSTL-15 (5)
Differential HSTL-12 (6)
I/O Bank 3
I/O Bank 4
Notes to Figure 6–10:
(1) This is a top view of the silicon die. This is only a graphical representation. For exact pin locations, refer to the pin list and the Quartus II software.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks 1, 2, 5, and 6 only. External resistors
are needed for the differential outputs in column I/O banks.
(3) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output pins.
(4) The HSTL-12 Class II is supported in column I/O banks 3, 4, 7, and 8 only.
(5) The differential SSTL-18 and SSTL-2, differential HSTL-18, and HSTL-15 I/O standards are supported only on clock input pins and phase-locked
loops (PLLs) output clock pins. Differential SSTL-18, differential HSTL-18, and HSTL-15 I/O standards do not support Class II output.
(6) The differential HSTL-12 I/O standard is only supported on clock input pins and PLL output clock pins. Differential HSTL-12 Class II is supported
only in column I/O banks 3, 4, 7, and 8.
(7) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses the LVDS input buffer.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–17
I/O Banks
Table 6–5 lists the I/O standards supported when a pin is used as a regular I/O pin in
the I/O banks of the Cyclone III device family.
Table 6–5. Cyclone III Device Family I/O Standards Support
I/O Banks
I/O Standard
3.3-V LVTTL/LVCMOS,
1
2
3
4
5
6
7
8
3.0-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS,
1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS,
v
v
v
v
v
v
v
v
1.2V LVCMOS,
3.0-V PCI/PCI-X
SSTL-18 Class I/II,
SSTL-2 Class I/II,
HSTL-18 Class I/II,
HSTL-15 Class I/II,
HSTL-12 Class I
v
v
v
v
v
v
v
v
HSTL-12 Class II
—
—
v
v
—
—
v
v
Differential SSTL-2,
Differential SSTL-18,
Differential HSTL-18,
Differential HSTL-15,
Differential HSTL-12
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2), (3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
PPDS
(2)
LVDS
v
v
v
v
v
v
v
v
BLVDS
v
v
v
v
v
v
v
v
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
RSDS and mini-LVDS
Differential LVPECL
Notes to Table 6–5:
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(1) These differential I/O standards are supported only for clock inputs and dedicated PLL_OUToutputs.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks only. Differential outputs in
column I/O banks require an external resistors network.
(3) This I/O standard is supported for outputs only.
(4) This I/O standard is supported for clock inputs only.
Each I/O bank of the Cyclone III device family has a VREFbus to accommodate
voltage-referenced I/O standards. Each VREFpin is the reference source for its VREF
group. If you use a VREF group for voltage-referenced I/O standards, connect the VREF
pin for that group to the appropriate voltage level. If you do not use all the VREF
groups in the I/O bank for voltage referenced I/O standards, you can use the VREFpin
in the unused voltage referenced groups as regular I/O pins. For example, if you have
SSTL-2 Class I input pins in I/O bank 1 and they are all placed in the VREFB1N0
group, VREFB1N0must be powered with 1.25 V, and the remaining VREFB1N[1:3]pins
(if available) are used as I/O pins. If multiple VREF groups are used in the same I/O
bank, the VREFpins must all be powered by the same voltage level because the VREF
pins are shorted together within the same I/O bank.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–18
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
1
When VREFpins are used as regular I/Os, they have higher pin capacitance than
regular user I/O pins. This has an impact on the timing if the pins are used as inputs
and outputs.
f
f
For more information about VREFpin capacitance, refer to the pin capacitance section
in the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters.
For more information about how to identify VREF groups, refer to the Cyclone III
Device Family Pin-Out files or the Quartus II Pin Planner tool.
Table 6–6 lists the number of VREFpins in each I/O bank for Cyclone III and
Cyclone III LS devices.
Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices (Part 1 of 2)
I/O Banks
Family
Device
Package
Pin Count
1
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
2
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
3
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
4
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
5
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
6
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
7
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
8
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
4
4
4
4
2
2
3
3
3
3
EQFP
MBGA
FBGA
EQFP
MBGA
FBGA
EQFP
MBGA
PQFP
FBGA
FBGA
EQFP
PQFP
FBGA
FBGA
PQFP
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
144
164
256
144
164
256
144
164
240
256
484
144
240
256
324
240
324
484
780
484
780
484
780
484
780
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–19
I/O Banks
Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices (Part 2 of 2)
I/O Banks
Family
Device
Package
Pin Count
1
3
3
3
3
3
3
3
3
3
3
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
3
3
3
3
3
3
3
3
3
3
5
3
3
3
3
3
3
3
3
3
3
6
3
3
3
3
3
3
3
3
3
3
7
3
3
3
3
3
3
3
3
3
3
8
3
3
3
3
3
3
3
3
3
3
UBGA
FBGA
FBGA
UBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
278
278
413
278
278
413
210
413
210
413
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Each I/O bank of the Cyclone III device family has its own VCCIOpins. Each I/O bank
can support only one VCCIO setting from among 1.2, 1.5, 1.8, 3.0, or 3.3 V. Any number
of supported single-ended or differential standards can be simultaneously supported
in a single I/O bank, as long as they use the same VCCIO levels for input and output
pins.
When designing LVTTL/LVCMOS inputs with Cyclone III and Cyclone III LS
devices, refer to the following guidelines:
■
All pins accept input voltage (VI) up to a maximum limit (3.6 V), as stated in the
recommended operating conditions are provided in the Cyclone III Device Data
Sheet and Cyclone III LS Device Data Sheet chapters.
■
■
Whenever the input level is higher than the bank VCCIO, expect higher leakage
current.
The LVTTL/LVCMOS I/O standard input pins can only meet the VIH and VIL
levels according to bank voltage level.
Voltage-referenced standards are supported in an I/O bank using any number of
single-ended or differential standards, as long as they use the same VREF and VCCIO
values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your
Cyclone III and Cyclone III LS devices, I/O pins using these standards—because they
require different VREF values—must be in different banks from each other. However,
the same I/O bank can support SSTL-2 and 2.5-V LVCMOS with the VCCIO set to
2.5 V and the VREF set to 1.25 V.
1
1
When using Cyclone III and Cyclone III LS devices as a receiver in 3.3-, 3.0-, or 2.5-V
LVTTL/LVCMOS systems, you are responsible for managing overshoot or
undershoot to stay in the absolute maximum ratings and the recommended operating
conditions, provided in the Cyclone III Device Data Sheet and Cyclone III LS Device Data
Sheet chapters.
The PCI clamping diode is enabled by default in the Quartus II software for input
signals with bank VCCIO at 2.5, 3.0, or 3.3 V.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–20
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
f
For more information about the Cyclone III device family I/O interface with 3.3-, 3.0-,
or 2.5-V LVTTL/LVCMOS systems, refer to AN 447: Interfacing Cyclone III and
Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
High-Speed Differential Interfaces
The Cyclone III device family can send and receive data through LVDS signals. For
the LVDS transmitter and receiver, the input and output pins of the Cyclone III device
family support serialization and deserialization through internal logic.
The BLVDS extends the benefits of LVDS to multipoint applications such as in
bidirectional backplanes. The loading effect and the need to terminate the bus at both
ends for multipoint applications require BLVDS to drive out a higher current than
LVDS to produce a comparable voltage swing. All the I/O banks of the Cyclone III
device family support BLVDS for user I/O pins.
The reduced swing differential signaling (RSDS) and mini-LVDS standards are
derivatives of the LVDS standard. The RSDS and mini-LVDS I/O standards are
similar in electrical characteristics to LVDS, but have a smaller voltage swing and
therefore provide increased power benefits and reduced electromagnetic interference
(EMI).
The point-to-point differential signaling (PPDS) standard is the next generation of the
RSDS standard introduced by National Semiconductor Corporation. The Cyclone III
device family meets the National Semiconductor Corporation PPDS Interface
Specification and supports the PPDS standard for outputs only. All the I/O banks of
the Cyclone III device family support the PPDS standard for output pins only.
You can use I/O pins and internal logic to implement the LVDS I/O receiver and
transmitter in the Cyclone III device family. Cyclone III and Cyclone III LS devices do
not contain dedicated serialization or deserialization circuitry. Therefore, shift
registers, internal PLLs, and IOEs are used to perform serial-to-parallel conversions
on incoming data and parallel-to-serial conversion on outgoing data.
The LVDS standard does not require an input reference voltage, but it does require a
100- termination resistor between the two signals at the input buffer. An external
resistor network is required on the transmitter side for top and bottom I/O banks.
f
For more information about the Cyclone III device family high-speed differential
interface support, refer to the High-Speed Differential Interfaces in the Cyclone III Device
Family chapter.
External Memory Interfacing
The Cyclone III device family supports I/O standards required to interface with a
broad range of external memory interfaces, such as DDR SDRAM, DDR2 SDRAM,
and QDRII SRAM.
f
For more information about the Cyclone III device family external memory interface
support, refer to the External Memory Interfaces in the Cyclone III Device Family chapter.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–21
Pad Placement and DC Guidelines
Pad Placement and DC Guidelines
Pad Placement
Altera recommends that you create a Quartus II design, enter your device I/O
assignments, and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation. These rules are dependent on
device density, package, I/O assignments, voltage assignments, and other factors that
are not fully described in this chapter.
f
For more information about how the Quartus II software checks I/O restrictions, refer
to the I/O Management chapter in volume 2 of the Quartus II Handbook.
DC Guidelines
For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to Electromigration
Current assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.
Document Revision History
Table 6–7 lists the revision history for this document.
Table 6–7. Document Revision History (Part 1 of 3)
Date
July 2012
Version
Changes
Updated OCT with or without calibration note in “Slew Rate Control” section,
■ Updated Table 6–1 and Table 6–4.
3.4
■ Updated “Programmable Pull-Up Resistor” on page 6–5, “OCT Support” on page 6–7,
and “I/O Standards” on page 6–11.
December 2011
3.3
■ Updated hyperlinks.
■ Minor text edits.
December 2009
July 2009
3.2
3.1
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
■ Updated chapter part number.
■ Updated “Introduction” on page 6–1, “PCI-Clamp Diode” on page 6–6, “On-Chip Series
Termination Without Calibration” on page 6–10, “I/O Standards” on page 6–11, “I/O
Banks” on page 6–16, “High-Speed Differential Interfaces” on page 6–20, and “External
Memory Interfacing” on page 6–20.
June 2009
3.0
■ Updated Table 6–6 on page 6–18.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–22
Chapter 6: I/O Features in the Cyclone III Device Family
Document Revision History
Table 6–7. Document Revision History (Part 2 of 3)
Date
Version
Changes
■ Added (Note 6) to Table 6–5.
■ Updated the “I/O Banks” section.
■ Updated the “Differential Pad Placement Guidelines” section.
■ Updated the “VREF Pad Placement Guidelines” section.
October 2008
2.1
■ Removed any mention of “RSDS and PPDS are registered trademarks of National
Semiconductor” from chapter.
■ Updated chapter to new template.
Changes include addition of BLVDS information.
■ Added an introduction to “I/O Element Features” section.
■ Updated “Slew Rate Control” section.
■ Updated “Programmable Delay” section.
■ Updated Table 6–1 with BLVDS information.
■ Updated Table 6–2.
■ Updated “PCI-Clamp Diode” section.
■ Updated “LVDS Transmitter Programmable Pre-Emphasis” section.
■ Updated “On-Chip Termination with Calibration” section and added new Figure 6–9.
■ Updated Table 6–3 title.
■ Updated Table 6–4 unit.
■ Updated “I/O Standards” section and Table 6–5 with BLVDS information and added
(Note 5).
May 2008
2.0
■ Updated “Differential I/O Standard Termination” section with BLVDS information.
■ Updated “I/O Banks” section.
■ Updated (Note 2) and added (Note 7) and BLVDS information to Figure 6–15.
■ Updated (Note 2) and added BLVDS information to Table 6–6.
■ Added MBGA package information to Table 6–7.
■ Deleted Table 6-8.
■ Updated “High-Speed Differential Interfaces” section with BLVDS information.
■ Updated “Differential Pad Placement Guidelines” section and added new Figure 6–16.
■ Updated “VREF Pad Placement Guidelines” section and added new Figure 6–17.
■ Updated Table 6–11.
■ Added new “DCLK Pad Placement Guidelines” section.
■ Updated “DC Guidelines” section.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 6: I/O Features in the Cyclone III Device Family
6–23
Document Revision History
Table 6–7. Document Revision History (Part 3 of 3)
Date
Version
Changes
■ Updated feetpara note in “Programmable Current Strength” section.
■ Updated feetpara note in “Slew Rate Control” section.
■ Updated feetpara note in “Open-Drain Output” section.
■ Updated feetpara note in “Bus Hold” section.
■ Updated feetpara note in “Programmable Pull-Up Resistor” section.
■ Updated feetpara note in “PCI-Clamp Diode” section.
■ Updated Figure 6–13.
July 2007
1.1
■ Updated Figure 6–14 and added Note (1).
■ Updated “I/O Banks” section.
■ Updated Note (5) to Figure 6–15.
■ Updated “DDR/DDR2 and QDRII Pads” section and corrected ‘cms’ to ‘cmd’.
■ Updated Note 3 in Table 6-8.
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
1.0
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
6–24
Chapter 6: I/O Features in the Cyclone III Device Family
Document Revision History
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
7. High-Speed Differential Interfaces in
the Cyclone III Device Family
December 2011
CIII51008-4.0
CIII51008-4.0
This chapter describes the high-speed differential I/O features and resources in the
Cyclone III device family.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The Altera®
Cyclone® III device family (Cyclone III and Cyclone III LS devices) supports LVDS,
BLVDS, reduced swing differential signaling (RSDS), mini-LVDS, and point-to-point
differential signaling (PPDS).
This chapter contains the following sections:
■
■
■
■
■
■
“High-Speed I/O Interface” on page 7–1
“High-Speed I/O Standards Support” on page 7–7
“True Output Buffer Feature” on page 7–15
“High-Speed I/O Timing” on page 7–16
“Design Guidelines” on page 7–17
“Software Overview” on page 7–18
High-Speed I/O Interface
Cyclone III device family I/Os are separated into eight I/O banks, as shown in
Figure 7–1. Each bank has an independent power supply. True output drivers for
LVDS, RSDS, mini-LVDS, and PPDS are on the left and right I/O banks. These I/O
standards are also supported on the top and bottom I/O banks using external
resistors. On the left and right I/O banks, some of the differential pin pairs (
pins) of the true output drivers are not located on adjacent pins. In these cases, a
power pin is located between the and pins. These I/O standards are also
pand n
p
n
supported on all I/O banks using two single-ended output with the second output
programmed as inverted, and an external resistor network. True input buffers for
these I/O standards are supported on all I/O banks.
f
For more information about the location of Cyclone III device family true differential
pins, refer to the Pin-Out Files for Altera Devices webpage on the Altera website.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
December 2011
Subscribe
7–2
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface
Figure 7–1 shows the I/O banks of the Cyclone III device family.
Figure 7–1. Cyclone III Device Family I/O Banks
I/O banks 7 and 8 also support the
HSTL-12 Class II I/O standard
I/O Bank 8
I/O Bank 7
All I/O Banks Support:
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI/PCI-X (1)
LVDS
RSDS (2)
BLVDS (5)
mini-LVDS (2)
PPDS (2)
LVPECL (3)
SSTL-2 Class I and II
SSTL-18 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I
Differential SSTL-2 (4)
Differential SSTL-18 (4)
Differential HSTL-18 (4)
DIfferential HSTL-15 (4)
Differential HSTL-12 (4)
I/O Bank 3
I/O Bank 4
I/O banks 3 and 4 also support the
HSTL-12 Class II I/O standard
Notes to Figure 7–1:
(1) The PCI-X I/O standard does not meet the IV curve requirement at the linear region.
(2) The RSDS, mini-LVDS, and PPDS I/O standards are only supported on output pins. These I/O standards are not supported on input pins.
(3) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported on output pins.
(4) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on dedicated clock input pins and PLL
output clock pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O
standards.
(5) BLVDS output uses two single-ended outputs with the second output programmed as inverted. BLVDS input uses LVDS input buffer.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–3
High-Speed I/O Interface
Table 7–1 lists which I/O bank supports these I/O standards in the Cyclone III device
family.
Table 7–1. Differential I/O Standards Supported in Cyclone III Device Family I/O Banks
External Resistor
Network at
Differential I/O Standards
I/O Bank Location
Transmitter (TX) Receiver (RX)
Transmitter
1,2,5,6
All
Not Required
Three Resistors
Not Required
LVDS
Yes
Yes
Yes
Yes
1,2,5,6
3, 4, 7, 8
All
Not
Supported
RSDS
Three Resistors
Single Resistor
Not Required
1,2,5,6
All
Not
Supported
mini-LVDS
PPDS
Three Resistors
Not Required
1,2,5,6
All
Not
Supported
Yes
Yes
Three Resistors
Single Resistor
(1)
BLVDS
All
Yes
Yes
Not
Supported
(2)
LVPECL
All
NA
(3)
Differential SSTL-2
All
All
All
All
All
NA
NA
NA
NA
NA
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(3)
(3)
(3)
(3)
Differential SSTL-18
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
Notes to Table 7–1:
(1) Transmitter and Receiver FMAX depend on system topology and performance requirement.
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
You can use I/O pins and internal logic to implement a high-speed differential
interface in the Cyclone III device family. The Cyclone III device family does not
contain dedicated serialization or deserialization circuitry. Therefore, shift registers,
internal phase-locked loops (PLLs), and I/O cells are used to perform
serial-to-parallel conversions on incoming data and parallel-to-serial conversion on
outgoing data. The differential interface data serializers and deserializers (SERDES)
are automatically constructed in the core logic elements (LEs) with the Quartus® II
software ALTLVDS megafunction.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–4
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface
Table 7–2 lists the total number of supported row and column differential channels in
the Cyclone III device family.
Table 7–2. Cyclone III Device Family Differential Channels (Part 1 of 2)
(1), (2)
Number of Differential Channels
Clock
Cyclone III Device Family
Device
Package
User I/O
Clock Input
Total
Output
E144
F256
M164
U256
E144
F256
M164
U256
E144
E240
F256
F484
M164
U256
U484
E144
E240
F256
F324
U256
E240
F324
F484
F780
U484
F484
F780
U484
F484
F780
U484
F484
F780
16
62
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
22
68
EP3C5
22
28
62
68
16
22
62
68
EP3C10
EP3C16
22
28
62
68
7
19
35
47
43
55
128
11
140
23
43
55
128
6
140
18
Cyclone III Devices
31
43
EP3C25
42
54
71
83
42
54
14
26
49
61
EP3C40
EP3C55
115
215
115
123
151
123
101
169
101
94
127
227
127
135
163
135
113
181
113
106
233
EP3C80
EP3C120
221
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–5
High-Speed I/O Interface
Table 7–2. Cyclone III Device Family Differential Channels (Part 2 of 2)
(1), (2)
Number of Differential Channels
Clock
Cyclone III Device Family
Device
Package
User I/O
Clock Input
Total
Output
U484
F484
F780
U484
F484
F780
F484
F780
F484
F780
101
101
169
101
101
169
75
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
4
4
113
113
181
113
113
181
87
EP3CLS70
EP3CLS100
Cyclone III LS Devices
EP3CLS150
EP3CLS200
169
75
181
87
169
181
Notes to Table 7–2:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
(2) For differential pad placement guidelines, refer to the I/O Features in the Cyclone III Device Family chapter.
Table 7–3 lists the numbers of differential channels that can be migrated in
Cyclone III devices.
(1)
Table 7–3. Cyclone III Devices Migratable Differential Channels
(Part 1 of 2)
Migratable Channels
Package
Migration Between Devices
Type
User I/O
CLK
4
Total
20
9
EP3C5 and EP3C10
EP3C5 and EP3C16
EP3C5 and EP3C25
EP3C10 and EP3C16
EP3C10 and EP3C25
EP3C16 and EP3C25
EP3C5 and EP3C10
EP3C5 and EP3C16
EP3C10 and EP3C16
EP3C16 and EP3C25
EP3C16 and EP3C40
EP3C25 and EP3C40
EP3C5 and EP3C10
EP3C5 and EP3C16
EP3C5 and EP3C25
EP3C10 and EP3C16
EP3C10 and EP3C25
EP3C16 and EP3C25
16
5
4
6
4
10
9
E144
5
4
6
4
10
13
26
15
14
31
19
20
66
43
44
43
44
41
5
8
22
11
19
23
11
12
62
39
40
39
40
33
4
M164
Q240
4
4
8
8
8
4
4
4
F256
4
4
8
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–6
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface
(1)
Table 7–3. Cyclone III Devices Migratable Differential Channels
(Part 2 of 2)
Migratable Channels
Package
Type
Migration Between Devices
EP3C5 and EP3C10
User I/O
CLK
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Total
66
62
39
EP3C5 and EP3C16
EP3C5 and EP3C25
EP3C10 and EP3C16
EP3C10 and EP3C25
EP3C16 and EP3C25
EP3C25 and EP3C40
EP3C16 and EP3C40
EP3C16 and EP3C55
EP3C16 and EP3C80
EP3C16 and EP3C120
EP3C40 and EP3C55
EP3C40 and EP3C80
EP3C40 and EP3C120
EP3C55 and EP3C80
EP3C55 and EP3C120
EP3C80 and EP3C120
EP3C16 and EP3C40
EP3C16 and EP3C55
EP3C16 and EP3C80
EP3C40 and EP3C55
EP3C40 and EP3C80
EP3C55 and EP3C80
EP3C40 and EP3C55
EP3C40 and EP3C80
EP3C40 and EP3C120
EP3C55 and EP3C80
EP3C55 and EP3C120
EP3C80 and EP3C120
43
40
44
U256
F324
39
43
40
44
33
41
47
55
102
98
110
106
87
79
72
80
102
84
110
92
F484
74
82
98
106
93
85
88
96
102
98
110
106
87
79
U484
F780
102
84
110
92
98
106
54
46
51
59
54
62
144
142
160
152
150
168
Note to Table 7–3:
(1) The migratable differential channels for Cyclone III devices are not directly migratable to Cyclone III LS devices
and vice versa.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–7
High-Speed I/O Standards Support
Table 7–4 lists the numbers of differential channels that can be migrated in
Cyclone III LS devices.
(1)
Table 7–4. Cyclone III LS Devices Migratable Differential Channels
Migratable Channels
Package
Type
Migration between Devices
Clock
Input
Clock
Output
User I/O
Total
U484
EP3CLS70 and EP3CLS100
EP3CLS70 and EP3CLS100
EP3CLS70 and EP3CLS150
EP3CLS70 and EP3CLS200
EP3CLS100 and EP3CLS150
EP3CLS100 and EP3CLS200
EP3CLS150 and EP3CLS200
EP3CLS70 and EP3CLS100
EP3CLS70 and EP3CLS150
EP3CLS70 and EP3CLS200
EP3CLS100 and EP3CLS150
EP3CLS100 and EP3CLS200
EP3CLS150 and EP3CLS200
101
101
71
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
4
113
113
83
71
83
F484
71
83
71
83
75
87
169
169
169
169
169
169
181
181
181
181
181
181
F780
Note to Table 7–4:
(1) The migratable differential channels for Cyclone III devices are not directly migratable to Cyclone III LS devices
and vice versa.
High-Speed I/O Standards Support
This section provides information about the high-speed I/O standards supported in
the Cyclone III device family.
LVDS I/O Standard Support in the Cyclone III Device Family
The LVDS I/O standard is a high-speed, low-voltage swing, low power, and general
purpose I/O interface standard. The Cyclone III device family meets the
ANSI/TIA/EIA-644 standard with the following exceptions:
■
The maximum differential output voltage (VOD) is increased to 600 mV. The
maximum VOD for ANSI specification is 450 mV.
■
The input voltage range is reduced to the range of 1.0 V to 1.6 V, 0.5 V to 1.85 V, or
0 V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644
specification supports an input voltage range of 0 V to 2.4 V.
f
For more information about the LVDS I/O standard electrical specifications in the
Cyclone III device family, refer to the Cyclone III Device Data Sheet and Cyclone III LS
Device Data Sheet chapters.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–8
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Designing with LVDS
Cyclone III device family I/O banks support LVDS I/O standard. The left and right
I/O banks support true LVDS transmitters. On the top and bottom I/O banks, the
emulated LVDS transmitters are supported using two single-ended output buffers
with external resistors. One of the single-ended output buffers is programmed to have
opposite polarity. The LVDS receiver requires an external 100- termination resistor
between the two signals at the input buffer.
Figure 7–2 shows a point-to-point LVDS interface using Cyclone III device family true
LVDS output and input buffers.
Figure 7–2. Cyclone III Device Family LVDS Interface with True Output Buffer on the Left and Right I/O Banks
Cyclone III Device Family
Transmitting Device
Receiving Device
txout +
txout -
rxin +
rxin -
txout +
txout -
rxin +
50 Ω
50 Ω
Cyclone III
Device
Family Logic
Array
50 Ω
50 Ω
100 Ω
100 Ω
rxin -
Input Buffer
Output Buffer
Figure 7–3 shows a point-to-point LVDS interface with Cyclone III device family
LVDS using two single-ended output buffers and external resistors.
(1)
Figure 7–3. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks
Cyclone III Device Family
Emulated
LVDS Transmitter
Resistor Network
LVDS Receiver
R
S
50 Ω
50 Ω
100 Ω
R
P
R
S
Note to Figure 7–3:
(1) RS= 120 ; RP= 170
BLVDS I/O Standard Support in the Cyclone III Device Family
The BLVDS I/O standard is a high-speed differential data transmission technology
that extends the benefits of standard point-to-point LVDS to multipoint configuration
that supports bidirectional half-duplex communication. BLVDS differs from standard
LVDS by providing a higher drive to achieve similar signal swings at the receiver
while loaded with two terminations at both ends of the bus.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–9
High-Speed I/O Standards Support
Figure 7–4 shows a typical BLVDS topology with multiple transmitter and receiver
pairs.
Figure 7–4. BLVDS Topology with Cyclone III Device Family Transmitters and Receivers
V
V
CC
CC
100 kΩ
100 kΩ
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
R
T
R
T
50
Ω
100 kΩ
GND
100 k Ω
GND
Output
Data
Output
Data
Output
Data
Input
Data
Input
Data
Input
Data
The BLVDS I/O standard is supported on all I/O banks of the Cyclone III device
family. The BLVDS transmitter uses two single-ended output buffers with the second
output buffer programmed as inverted, while the BLVDS receiver uses a true LVDS
input buffer. The transmitter and receiver share the same pins. An output-enabled (OE
signal is required to tristate the output buffers when the LVDS input buffer receives a
signal.
)
f
f
For more information about BLVDS I/O features and electrical specifications, refer to
the I/O Features in the Cyclone III Device Family chapter in volume 1 of the Cyclone III
Device Handbook and the Cyclone III Device Data Sheet and Cyclone III LS Device Data
Sheet chapters.
For more information and design examples about implementing the BLVDS interfaces
in the Cyclone III device family, refer to AN 522: Implementing Bus LVDS Interface in
Supported Altera Device Families.
Designing with BLVDS
The BLVDS bidirectional communication requires termination at both ends of the bus
in BLVDS. The termination resistor (RT) must match the bus differential impedance,
which in turn depends on the loading on the bus. Increasing the load decreases the
bus differential impedance. With termination at both ends of the bus, termination is
not required between the two signals at the input buffer. A single series resistor (RS) is
required at the output buffer to match the output buffer impedance to the
transmission line impedance. However, this series resistor affects the voltage swing at
the input buffer. The maximum data rate achievable depends on many factors.
1
Altera recommends that you perform simulation using the IBIS model while
considering factors such as bus loading, termination values, and output and input
buffer location on the bus to ensure that the required performance is achieved.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–10
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device
Family
The RSDS, mini-LVDS, and PPDS I/O standards are used in chip-to-chip applications
between the timing controller and the column drivers on the display panels such as
LCD monitor panels and LCD televisions. The Cyclone III device family meets the
National Semiconductor Corporation RSDS Interface Specification, Texas Instruments
mini-LVDS Interface Specification, and National Semiconductor Corporation PPDS
Interface Specification to support RSDS, mini-LVDS and PPDS output standards,
respectively.
f
f
For more information about the Cyclone III device family RSDS, mini-LVDS, and
PPDS output electrical specifications, refer to the Cyclone III Device Data Sheet and
Cyclone III LS Device Data Sheet chapters.
For more information about the RSDS I/O standard, refer to the RSDS specification
from the National Semiconductor website (www.national.com).
Designing with RSDS, Mini-LVDS, and PPDS
Cyclone III device family I/O banks support RSDS, mini-LVDS, and PPDS output
standards. The left and right I/O banks support true RSDS, mini-LVDS, and PPDS
transmitters. On the top and bottom I/O banks, RSDS, mini-LVDS, and PPDS
transmitters are supported using two single-ended output buffers with external
resistors. The two-single ended output buffers are programmed to have opposite
polarity.
Figure 7–5 shows a RSDS, mini-LVDS, or PPDS interface with a true output buffer.
Figure 7–5. Cyclone III Device Family RSDS, Mini-LVDS, or PPDS Interface with True Output Buffer on the Left and Right
I/O Banks
Cyclone III Device Family
True RSDS, Mini-LVDS,
or PPDS Transmitter
RSDS, Mini-LVDS,
or PPDS Receiver
50
50
100
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–11
High-Speed I/O Standards Support
Figure 7–6 shows a RSDS, mini-LVDS, or PPDS interface with two singled-ended
output buffers and external resistors.
(1)
Figure 7–6. RSDS, Mini-LVDS, or PPDS Interface with External Resistor Network on the Top and Bottom I/O Banks
Cyclone III Device Family
Emulated RSDS,
Mini-LVDS, or PPDS
Transmitter
Resistor Network
RSDS, Mini-LVDS,
or PPDS Receiver
RS
50 Ω
50 Ω
RP
100 Ω
RS
Note to Figure 7–6:
(1) RS= 120 ; RP= 170
A resistor network is required to attenuate the output voltage swing to meet RSDS,
mini-LVDS, and PPDS specifications when using emulated transmitters. You can
modify the resistor network values to reduce power or improve the noise margin.
The resistor values chosen must satisfy Equation 7–1.
Equation 7–1.
RP
------
RS
2
------------------- = 50
RP
RS + ------
2
1
Altera recommends that you perform simulations using Cyclone III device family IBIS
models to validate that custom resistor values meet the RSDS, mini-LVDS, or PPDS
requirements.
You can use a single external resistor instead of using three resistors in the resistor
network for an RSDS interface, as shown in Figure 7–7. The external single-resistor
solution reduces the external resistor count while still achieving the required
signaling level for RSDS. However, the performance of the single-resistor solution is
lower than the performance with the three-resistor network.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–12
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–7 shows the RSDS interface with a single resistor network on the top and
bottom I/O banks.
Figure 7–7. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Cyclone III Device Family
Emulated
RSDS Transmitter
Single Resistor Network
RSDS Receiver
50 Ω
50 Ω
RP
100 Ω
Note to Figure 7–7:
(1) RP= 100
LVPECL I/O Support in the Cyclone III Device Family
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V
CCIO. This standard is used in applications involving video graphics,
telecommunications, data communications, and clock distribution. The Cyclone III
device family supports the LVPECL input standard at the dedicated clock input pins
only. The LVPECL receiver requires an external 100- termination resistor between
the two signals at the input buffer.
f
For more information about the LVPECL I/O standard electrical specification, refer to
the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters.
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone III device family LVPECL input common mode
voltage.
Figure 7–8 shows the AC-coupled termination scheme. The 50- resistors used at the
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone III device family LVPECL input buffer
specification (Figure 7–9).
Figure 7–8. LVPECL AC-Coupled Termination
LVPECL
Transmitter
Cyclone III Device Family
LVPECL Receiver
0.1 µF
0.1 µF
Z
= 50
= 50
0
50
50
V
ICM
Z
0
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–13
High-Speed I/O Standards Support
Figure 7–9 shows the LVPECL DC-coupled termination.
Figure 7–9. LVPECL DC-Coupled Termination
Cyclone III Device Family
LVPECL Receiver
LVPECL Transmitter
50
50
100
Differential SSTL I/O Standard Support in the Cyclone III Device Family
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. The Cyclone III device family supports
differential SSTL-2 and SSTL-18 I/O standards. The differential SSTL output standard
is only supported at PLL#_CLKOUTpins using two single-ended SSTL output buffers
(PLL#_CLKOUTpand PLL#_CLKOUTn), with the second output programmed to have
opposite polarity. The differential SSTL input standard is supported on the GCLK
pins only, treating differential inputs as two single-ended SSTL and only decoding
one of them.
The differential SSTL I/O standard requires two differential inputs with an external
reference voltage (VREF) as well as an external termination voltage (VTT) of 0.5 × VCCIO
to which termination resistors are connected.
f
For more information about the differential SSTL electrical specifications, refer to the
I/O Features in the Cyclone III Device Family chapter and the Cyclone III Device Data Sheet
and Cyclone III LS Device Data Sheet chapters.
Figure 7–10 shows the differential SSTL Class I interface.
Figure 7–10. Differential SSTL Class I Interface
VTT
VTT
Output Buffer
Receiver
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–14
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–11 shows the differential SSTL Class II interface.
Figure 7–11. Differential SSTL Class II Interface
VTT
VTT
VTT
VTT
Output Buffer (1)
Receiver
Note to Figure 7–11:
(1) PLL output clock pins do not support differential SSTL-18 Class II I/O standard.
Differential HSTL I/O Standard Support in the Cyclone III Device Family
The differential HSTL I/O standard is used for the applications designed to operate in
0 V to 1.2 V, 0 V to 1.5 V, or 0 V to 1.8 V HSTL logic switching range. The Cyclone III
device family supports differential HSTL-18, HSTL-15, and HSTL-12 I/O standards.
The differential HSTL input standard is available on GCLK pins only, treating the
differential inputs as two single-ended HSTL and only decoding one of them. The
differential HSTL output standard is only supported at the PLL#_CLKOUTpins using
two single-ended HSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with the
second output programmed to have opposite polarity.
The differential HSTL I/O standard requires two differential inputs with an external
reference voltage (VREF), as well as an external termination voltage (VTT) of 0.5 × VCCIO
to which termination resistors are connected.
f
For more information about the differential HSTL signaling characteristics, refer to the
I/O Features in the Cyclone III Device Family, Cyclone III Device Data Sheet, and Cyclone III
LS Device Data Sheet chapters.
Figure 7–12 shows the differential HSTL Class I interface.
Figure 7–12. Differential HSTL Class I Interface
VTT
VTT
50 Ω
50 Ω
Output Buffer
Receiver
Z
= 50 Ω
= 50 Ω
0
Z
0
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–15
True Output Buffer Feature
Figure 7–13 shows the differential HSTL Class II interface.
Figure 7–13. Differential HSTL Class II Interface
VTT
VTT
VTT
VTT
50 Ω
50 Ω
50 Ω
50 Ω
Output Buffer (1)
Receiver
Z
= 50 Ω
= 50 Ω
0
Z
0
Note to Figure 7–13:
(1) PLL output clock pins do not support differential HSTL Class II I/O standard.
True Output Buffer Feature
Cyclone III device family true differential transmitters offer programmable
pre-emphasis—you can choose to turn it on or off. The default setting is on.
Programmable Pre-Emphasis
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependent attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the VOD specification and the output impedance of the
transmitter. At high frequency, the slew rate may not be fast enough to reach full VOD
before the next edge; this may lead to pattern dependent jitter. With pre-emphasis, the
output current is momentarily boosted during switching to increase the output slew
rate. The overshoot produced by this extra switching current is different from the
overshoot caused by signal reflection. This overshoot happens only during switching,
and does not produce ringing.
Figure 7–14 shows the differential output signal with pre-emphasis.
Figure 7–14. The Output Signal with Pre-Emphasis
Overshoot
Positive channel (p)
Negative channel (n)
VOD
Undershoot
December 2011 Altera Corporation
Cyclone III Device Handbook
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7–16
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Timing
High-Speed I/O Timing
This section discusses the timing budget, waveforms, and specifications for
source-synchronous signaling in the Cyclone III device family. Timing for
source-synchronous signaling is based on skew between the data and clock signals.
High-speed differential data transmission requires timing parameters provided by IC
vendors and requires you to consider the board skew, cable skew, and clock jitter. This
section provides information about high-speed I/O standards timing parameters in
the Cyclone III device family.
Table 7–5 lists the parameters of the timing diagram as shown in Figure 7–15.
Table 7–5. High-Speed I/O Timing Definitions
Parameter
Symbol
Description
The timing difference between the fastest and slowest output
edges, including tCO variation and clock skew. The clock is
included in the TCCS measurement.
(1)
Transmitter channel-to-channel skew
TCCS
The period of time during which the data must be valid in order
for you to capture it correctly. The setup and hold times
determine the ideal strobe position in the sampling window.
TSW = TSU + Thd + PLL jitter.
Sampling window
SW
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS. The RSKM equation is:
Receiver input skew margin
RSKM
TUI – SW – TCCS
RSKM = --------------------------------------------------
2
Allowed input jitter on the input clock to the PLL that is tolerable
while maintaining PLL lock.
Input jitter tolerance (peak-to-peak)
—
—
Output jitter (peak-to-peak)
Peak-to-peak output jitter from the PLL.
Note to Table 7–5:
(1) The TCCS specification applies to the entire bank of differential I/O as long as the SERDES logic is placed in the logic array block (LAB) adjacent
to the output pins.
Figure 7–15. High-Speed I/O Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal Clock
TCCS
RSKM
RSKM
TCCS
Receiver
Input Data
Sampling Window (SW)
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–17
Design Guidelines
Figure 7–16 shows the Cyclone III device family high-speed I/O timing budget.
(1)
Figure 7–16. Cyclone III Device Family High-Speed I/O Timing Budget
Internal Clock Period
0.5 × TCCS
RSKM
SW
RSKM
0.5 × TCCS
Note to Figure 7–16:
(1) The equation for the high-speed I/O timing budget is:
eriod = 0.5 TCCS + RSKM + SW + RSKM + 0.5 TCCS
f
For more information, refer to the Cyclone III Device Data Sheet and Cyclone III LS
Device Data Sheet chapters in volume 2 of the Cyclone III Device Handbook.
Design Guidelines
This section provides guidelines for designing with the Cyclone III device family.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the VCCIO supply, you must observe some
restrictions on the placement of single-ended I/O pins in relation to differential pads.
Altera recommends that you create a Quartus II design, enter your device I/O
assignments, and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation.
f
For more information about how the Quartus II software checks I/O restrictions, refer
to the I/O Management chapter in volume 2 of the Quartus II Handbook.
Board Design Considerations
This section explains how to achieve the optimal performance from the Cyclone III
device family I/O interface and ensure first-time success in implementing a
functional design with optimal signal quality. You must consider the critical issues of
controlled impedance of traces and connectors, differential routing, and termination
techniques to get the best performance from the Cyclone III device family.
Use the following general guidelines for improved signal quality:
■
Base board designs on controlled differential impedance. Calculate and compare
all parameters, such as trace width, trace thickness, and the distance between two
differential traces.
■
Maintain equal distance between traces in differential I/O standard pairs as much
as possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–18
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Software Overview
■
Longer traces have more inductance and capacitance. These traces must be as
short as possible to limit signal integrity issues.
■
■
■
■
■
Place termination resistors as close to receiver input pins as possible.
Use surface mount components.
Avoid 90° corners on board traces.
Use high-performance connectors.
Design backplane and card traces so that trace impedance matches the impedance
of the connector and termination.
■
■
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal trace lengths
result in misplaced crossing points and decrease system margins as the
transmitter-channel-to-channel skew (TCCS) value increases.
■
■
Limit vias because they cause discontinuities.
Keep switching transistor-to-transistor logic (TTL) signals away from differential
signals to avoid possible noise coupling.
■
■
Do not route TTL clock signals to areas under or above the differential signals.
Analyze system-level signals.
f
For more information about PCB layout guidelines, refer to the High-Speed Board
Layout Guidelines and Guidelines for Designing High-Speed FPGA PCBs application
notes.
Software Overview
Cyclone III device family high-speed I/O system interfaces are created in core logic
by a Quartus II software megafunction because they do not have a dedicated circuit
for the SERDES. The Cyclone III device family uses the I/O registers and LE registers
to improve the timing performance and support the SERDES. Altera Quartus II
software allows you to design your high-speed interfaces using the ALTLVDS
megafunction. This megafunction implements either a high-speed deserializer
receiver or a high-speed serializer transmitter. There is a list of parameters in the
ALTLVDS megafunction that you can set to customize your SERDES based on your
design requirements. The megafunction is optimized to use Cyclone III device family
resources to create high-speed I/O interfaces in the most effective manner.
1
When you are using the Cyclone III device family with the ALTLVDS megafunction,
the interface always sends the MSB of your parallel data first.
f
For more information about designing your high-speed I/O systems interfaces using
the ALTLVDS megafunction, refer to the LVDS SERDES Transmitter/Receiver
(ALTLVDS_TX amd ALTLVDS_RX) Megafunction User Guide and the Quartus II
Handbook.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
7–19
Document Revision History
Document Revision History
Table 7–6 lists the revision history for this document.
Table 7–6. Document Revision History (Part 1 of 2)
Date
Version
Changes
■ Updated Table 7–2.
■ Updated “Differential SSTL I/O Standard Support in the Cyclone III Device Family” on
page 7–13, “Differential HSTL I/O Standard Support in the Cyclone III Device Family” on
page 7–14, and “Differential Pad Placement Guidelines” on page 7–17.
December 2011
4.0
■ Updated hyperlinks.
■ Minor text edits.
December 2009
July 2009
3.2
3.1
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
■ Updated chapter part number.
■ Updated “Introduction” on page 7–1, “High-Speed I/O Interface” on page 7–1, “High-
Speed I/O Standards Support” on page 7–7, “LVDS I/O Standard Support in Cyclone III
Family Devices” on page 7–7, “Designing with LVDS” on page 7–8, “BLVDS I/O Standard
Support in Cyclone III Family Devices” on page 7–8, “RSDS, Mini-LVDS, and PPDS I/O
Standard Support in Cyclone III Family Devices” on page 7–10, “LVPECL I/O Support in
Cyclone III Family Devices” on page 7–12, “Differential SSTL I/O Standard Support in
Cyclone III Family Devices” on page 7–13, and “Differential HSTL I/O Standard Support in
Cyclone III Family Devices” on page 7–14.
June 2009
3.0
■ Updated Figure 7–1 on page 7–2, Figure 7–4 on page 7–9, and Figure 7–5 on page 7–10.
■ Updated Table 7–1 on page 7–3, Table 7–2 on page 7–4, Table 7–3 on page 7–5, and
Table 7–4 on page 7–7.
■ Updated Table 7–2.
■ Updated Table 7–1.
■ Updated “BLVDS I/O Standard Support in Cyclone III Devices”.
■ Updated “Software Overview”.
October 2008
1.3
■ Removed registered trademark symbols for RSDS and PPDS.
■ Removed any mention of “RSDS and PPDS are registered trademarks of National
Semiconductor” in this chapter.
■ Updated chapter to new template.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
7–20
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Document Revision History
Table 7–6. Document Revision History (Part 2 of 2)
Date
Version
Changes
Changes include addition of BLVD information
■ Updated “Introduction” section with BLVDS information.
■ Updated Figure 7–1 with BLVDS information and added Note 5.
■ Updated Table 7–1 and added BLVDS information.
■ Updated “Cyclone III High-Speed I/O Banks” section with BLVDS information.
■ Updated Table 7–2 and 7–6.
■ Added new section “BLVDS I/O Standard Support in Cyclone III Devices”.
■ Updated Note 4 to Figure 7–4.
May 2008
1.2
■ Updated Note 1 to Figure 7–10.
■ Updated Note 1 to Figure 7–11.
■ Updated Note 1 to Figure 7–14.
■ Updated “Mini-LVDS I/O Standard Support in Cyclone III Devices” section.
■ Updated Note 1 to Figure 7–17.
■ Updated “LVPECL I/O Support in Cyclone III Devices” section.
■ Added new Figure 7–18.
■ Added note that PLL output clock pins do not support Class II type of selected differential
I/O standards.
■ Added Table 8–3 that lists the number of differential channels which are migratable
across densities and packages.
■ Updated (Note 4) to Figure 7–1.
■ Updated (Note 3) to Table 7–1.
■ Added new Table 7–3.
July 2007
1.1
1.0
■ Added (Note 1) to Figure 7–21.
■ Added (Note 1) to Figure 7–23.
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
8. External Memory Interfaces in the
Cyclone III Device Family
July 2012
CIII51009-3.1
CIII51009-3.1
In addition to an abundant supply of on-chip memory, Cyclone® III device family
(Cyclone III and Cyclone III LS devices) can easily interface to a broad range of
external memory, including DDR2 SDRAM, DDR SDRAM, and QDRII SRAM.
External memory devices are an important system component of a wide range of
image processing, storage, communications, and general embedded applications.
1
Altera® recommends that you construct all DDR2 or DDR SDRAM external memory
interfaces using the Altera ALTMEMPHY megafunction. You can implement the
controller function using the Altera DDR2 or DDR SDRAM memory controllers,
third-party controllers, or a custom controller for unique application needs.
Cyclone III device family supports QDR II interfaces electrically, but Altera does not
supply controller or physical layer (PHY) megafunctions for QDR II interfaces.
This chapter includes a description of the hardware interfaces for external memory
interfaces available in Cyclone III device family.
This chapter contains the following sections:
■
“Cyclone III Device Family Memory Interfaces Pin Support” on page 8–2
“Cyclone III Device Family Memory Interfaces Features” on page 8–11
■
f
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to the External Memory Interfaces page.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
July 2012
Subscribe
8–2
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Figure 8–1 shows the block diagram of a typical external memory interface data path
in Cyclone III device family.
(1)
Figure 8–1. Cyclone III Device Family External Memory Data Path
DQS/CQ/CQn
DQ
IOE
Register
OE
IOE
Register
OE
IOE
Register
IOE
Register
IOE
Register
V
IOE
Register
CC
DataA
DataB
LE
Register
IOE
Register
GND
IOE
Register
LE
Register
LE
Register
System Clock
PLL
-90° Shifted Clock
Capture Clock
Note to Figure 8–1:
(1) All clocks shown here are global clocks.
Cyclone III Device Family Memory Interfaces Pin Support
Cyclone III device family uses data (DQ), data strobe (DQS), clock, command, and
address pins to interface with external memory. Some memory interfaces use the data
mask (DM) or byte write select (BWS#) pins to enable data masking. This section
describes how Cyclone III device family supports all these different pins.
Data and Data Clock/Strobe Pins
Cyclone III device family data pins for external memory interfaces are called D for
write data, Q for read data, or DQfor shared read and write data pins. The read-data
strobes or read clocks are called DQSpins. Cyclone III device family supports both
bidirectional data strobes and unidirectional read clocks. Depending on the external
memory standard, the DQand DQSare bidirectional signals (in DDR2 and
DDR SDRAM) or unidirectional signals (in QDR II SRAM). Connect the bidirectional
DQdata signals to the same Cyclone III device family DQpins. For unidirectional Dor Q
signals, connect the read-data signals to a group of DQpins and the write-data signals
to a different group of DQpins.
1
In QDR II SRAM, the Q read-data group must be placed at a different VREF bank
location from the D write-data group, command, or address pins.
In Cyclone III device family, DQSis used only during write mode in DDR2 and
DDR SDRAM interfaces. Cyclone III device family ignores DQSas the read-data strobe
because the PHY internally generates the read capture clock for read mode. However,
you must connect the DQSpin to the DQSsignal in DDR2 and DDR SDRAM interfaces,
or to the CQsignal in QDR II SRAM interfaces.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–3
Cyclone III Device Family Memory Interfaces Pin Support
1
Cyclone III device family does not support differential strobe pins, which is an
optional feature in the DDR2 SDRAM device.
f
When you use the Altera Memory Controller MegaCore®, the PHY is instantiated for
you. For more information about the memory interface data path, refer to the External
Memory Interfaces page.
1
ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the
implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone III device family through the
ALTMEMPHY megafunction because you are not required to route the DQSsignals on
the global clock buses (because DQSis ignored for read capture). Resynchronization
issues do not arise because no transfer occurs from the memory domain clock (DQS) to
the system domain for capturing data DQ
.
All I/O banks in Cyclone III device family can support DQand DQSsignals with DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36. DDR2 and DDR SDRAM interfaces use ×8
mode DQSgroup regardless of the interface width. For wider interface, you can use
multiple ×8 DQgroups to achieve the desired width requirement.
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQpins, respectively, in the group, to support one, two, or four
parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support the
QDR II memory interface. CQ# is the inverted read-clock signal which is connected to
the complementary data strobe (DQSor CQ#)pin. You can use any unused DQpins as
regular user I/O pins if they are not used as memory interface signals.
Table 8–1 lists the number of DQSor DQgroups supported on each side of the
Cyclone III device only.
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)
Number Number Number Number Number Number
Device
Package
Side
×8
×9
×16
×18
×32
×36
Groups
Groups
Groups
Groups
Groups
Groups
Left
0
0
1
1
0
0
1
1
1
1
2
2
0
0
0
0
0
0
0
0
1
1
2
2
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Right
144-pin EQFP (1)
(2)
Top
(3), (4)
Bottom
Left
Right
(1)
EP3C5
164-pin MBGA
(2)
Top
(3), (4)
Bottom
(4), (5)
Left
256-pin FineLine
BGA/256-pin
Ultra FineLine
(4), (6)
Right
Top
(1)
BGA
Bottom
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
8–4
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 2 of 4)
Number Number Number Number Number Number
Device
Package
Side
×8
×9
×16
×18
×32
×36
Groups
Groups
Groups
Groups
Groups
Groups
Left
0
0
1
1
0
0
1
1
1
1
2
2
0
0
1
1
0
0
1
1
1
1
1
1
1
1
2
2
4
4
4
4
0
0
0
0
0
0
0
0
1
1
2
2
0
0
0
0
0
0
0
0
1
0
1
1
1
1
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
2
2
2
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
Right
(1)
144-pin EQFP
164-pin MBGA
(2)
Top
(3), (4)
Bottom
Left
Right
(1)
EP3C10
(2)
Top
(3), (4)
Bottom
(4), (5)
Left
256-pin FineLine
BGA/256-pin Ultra
(4), (6)
Right
Top
(1)
FineLine BGA
Bottom
Left
Right
(1)
144-pin EQFP
(2)
Top
(3), (4)
Bottom
Left
Right
(1)
164-pin MBGA
(2)
Top
(3), (4)
Bottom
(4), (7)
Left
(3), (4)
Right
Top
(1)
EP3C16
240-pin PQFP
Bottom
(4), (5)
Left
256-pin FineLine
BGA/256-pin
Ultra FineLine
(4), (6)
Right
Top
(1)
BGA
Bottom
Left
484-pin FineLine
BGA/484-pin
Ultra FineLine
BGA
Right
Top
1
1
1
1
Bottom
1
1
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–5
Cyclone III Device Family Memory Interfaces Pin Support
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 3 of 4)
Number Number Number Number Number Number
Device
Package
Side
×8
×9
×16
×18
×32
×36
Groups
Groups
Groups
Groups
Groups
Groups
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
Left
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
2
2
4
4
4
4
4
4
6
6
0
0
0
0
1
0
1
1
1
1
2
2
2
2
2
2
1
0
1
1
2
2
2
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
Right
(1)
144-pin EQFP
240-pin PQFP
(2)
Top
Bottom
(3), (4)
(4), (7)
Left
(3), (4)
Right
Top
(1)
Bottom
EP3C25
(4), (5)
Left
256-pin FineLine
BGA/256-pin
Ultra FineLine
(4), (6)
Right
Top
(1)
BGA
Bottom
Left
(8)
Right
Top
324-pin FineLine BGA
(1)
Bottom
(4), (7)
Left
(3), (4)
Right
Top
0
0
240-pin PQFP
0
0
Bottom
Left
0
0
0
0
(8)
Right
Top
0
0
324-pin FineLine BGA
0
0
Bottom
Left
0
0
EP3C40
1
1
484-pin FineLine
BGA/484-pin
Ultra FineLine
BGA
Right
Top
1
1
1
1
Bottom
Left
1
1
1
1
Right
Top
1
1
780-pin FineLine BGA
1
1
Bottom
1
1
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
8–6
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 4 of 4)
Number Number Number Number Number Number
Device
Package
Side
×8
×9
×16
×18
×32
×36
Groups
Groups
Groups
Groups
Groups
Groups
Left
4
4
4
4
4
4
6
6
4
4
4
4
4
4
6
6
4
4
4
4
4
4
6
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
484-pin FineLine
BGA/484-pin Ultra
FineLine BGA
Right
Top
Bottom
Left
EP3C55
Right
Top
780-pin FineLine BGA
Bottom
Left
484-pin FineLine
BGA/484-pin
Ultra FineLine
BGA
Right
Top
Bottom
Left
EP3C80
Right
Top
780-pin FineLine BGA
484-pin FineLine BGA
780-pin FineLine BGA
Bottom
Left
Right
Top
Bottom
Left
EP3C120
Right
Top
Bottom
Notes to Table 8–1:
(1) This device package does not support ×32 or ×36 mode.
(2) For the top side of the device, RUP, RDN, PLLCLKOUT3n, and PLLCLKOUT3p pins are shared with the DQ or DM pins to gain ×8 DQ group. You
cannot use these groups if you are using the RUP and RDN pins for on-chip termination (OCT) calibration or if you are using PLLCLKOUT3n
and PLLCLKOUT3p.
(3) There is no DM pin support for these groups.
(4) The RUP and RDN pins are shared with the DQ pins. You cannot use these groups if you are using the RUP and RDN pins for OCT calibration.
(5) The ×8 DQ group can be formed in Bank 2.
(6) The ×8 DQ group can be formed in Bank 5.
(7) There is no DM and BWS# pins support for these groups.
(8) The RUP pin is shared with the DQ pin to gain ×9 or ×18 DQ group. You cannot use these groups if you are using the RUP and RDN pins for
OCT calibration.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–7
Cyclone III Device Family Memory Interfaces Pin Support
Table 8–2 lists the numbers of DQS or DQ groups supported on each side of the
Cyclone III LS device only.
Table 8–2. Cyclone III LS Device DQS and DQ Bus Mode Support for Each Side of the Device
Number Number Number Number Number Number
Device
Package
Side
of ×8
of ×9
of ×16
Groups
of ×18
Groups
of ×32
Groups
of ×36
Groups
Groups
Groups
—
—
—
—
1
Left
Right
Top
2
2
2
2
4
4
6
6
2
2
2
2
4
4
6
6
2
2
2
2
4
4
6
6
2
2
2
2
4
4
6
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
—
—
—
—
1
484-pin FineLine
BGA/
484-pin Ultra FineLine
(1)
BGA
Bottom
Left
EP3CLS70
Right
Top
1
1
780-pin FineLine BGA
1
1
Bottom
Left
1
1
—
—
—
—
1
—
—
—
—
1
484-pin FineLine
BGA/
Right
Top
484-pin Ultra FineLine
(1)
BGA
Bottom
Left
EP3CLS100
Right
Top
1
1
780-pin FineLine BGA
1
1
Bottom
Left
1
1
—
—
—
—
1
—
—
—
—
1
484-pin FineLine BGA
Right
Top
(1)
Bottom
Left
EP3CLS150
Right
Top
1
1
780-pin FineLine BGA
1
1
Bottom
Left
1
1
—
—
—
—
1
—
—
—
—
1
484-pin FineLine BGA
Right
Top
(1)
Bottom
Left
EP3CLS200
Right
Top
1
1
780-pin FineLine BGA
1
1
Bottom
1
1
Note to Table 8–2:
(1) This device package does not support x32 or 36 mode.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
8–8
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
f
1
For more information about device package outline, refer to the Package and Thermal
Resistance page.
DQSpins are listed in the Cyclone III and Cyclone III LS pin tables as DQSXY, in which
indicates the DQSgrouping number and indicates whether the group is located on
the top ( ), bottom ( ), left ( ) or right ( ) side of the device. Similarly, the
corresponding DQpins are marked as DQXY, in which the denotes the DQ grouping
number and denotes whether the group is located on the top ( ), bottom ( ), left (
or right ( ) side of the device. For example, DQS2Tindicates a DQSpin belonging to
group , located on the top side of the device. Similarly, the DQpins belonging to that
group is shown as DQ2T
X
Y
T
B
L
R
X
Y
T
B
L
)
R
2
.
Each DQgroup is associated with its corresponding DQSpins, as defined in the Cyclone
III and Cyclone III LS pin tables; for example:
■
■
For DDR2 or DDR SDRAM, ×8 DQgroup DQ3B[7:0]pins are associated with
the DQS3Bpin (same 3B group index)
For QDR II SRAM, ×9 Q read-data group DQ3L[8..0]pins are associated with
DQS2L/CQ3Land DQS3L/CQ3L#pins (same 3L group index)
The Quartus® II software issues an error message if a DQgroup is not placed properly
with its associated DQS
.
Figure 8–2 shows the location and numbering of the DQS, DQ, or CQ# pins in the
Cyclone III device family I/O banks.
1
For maximum timing performance, Altera recommends that the data groups for
external memory interfaces must always be within the same side of a device.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–9
Cyclone III Device Family Memory Interfaces Pin Support
(1)
Figure 8–2. DQS, CQ, or CQ# Pins in Cyclone III Device Family I/O Banks
SD/CQT1#
3
DS4C5/QT
SD/CQT5#
SD2/C3QT
SD0/C1QT
I/O Bank 8
I/O Bank 7
/IOBank6
DQS2L/CQ3L
DQS0L/CQ1L
DQS2R/CQ3R
DQS0R/CQ1R
/IOBank1
Cyclone III Device Family
DQS1R/CQ1R#
DQS3R/CQ3R#
/IOBank5
DQS1L/CQ1L#
DQS3L/CQ3L#
/IOBank2
I/O Bank 3
I/O Bank 4
Q
DS2C3/QB
SD0/C1QB
SD/CQB3#
1
DS/QBC5#
Note to Figure 8–2:
(1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone III device family except devices in 144-pin EQFP and 164-pin
MBGA.
Figure 8–3 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O
banks of the Cyclone III device in the 144-pin EQFP and 164-pin MBGA packages
only.
Figure 8–3. DQS, CQ, or CQ# Pins for Devices in the 144-Pin EQFP and 164-Pin MBGA Packages
SD/CQT1#
SD0/C1QT
I/O Bank 8
I/O Bank 7
/IOBank6
DQS0R/CQ1R
DQS0L/CQ1L
/IOBank1
Cyclone III Devices
in 144-pin EQFP and
164-pin MBGA
/IOBank5
DQS1L/CQ1L#
DQS1R/CQ1R#
/IOBank2
I/O Bank 3
I/O Bank 4
SD0/C1QB
SD/CQB1#
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
8–10
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Pin Support
In Cyclone III device family, the ×9 mode uses the same DQand DQSpins as the ×8
mode, and one additional DQpin that serves as a regular I/O pin in the ×8 mode. The
×18 mode uses the same DQand DQSpins as ×16 mode, with two additional DQpins
that serve as regular I/O pins in the ×16 mode. Similarly, the ×36 mode uses the same
DQand DQSpins as the ×32 mode, with four additional DQpins that serve as regular
I/O pins in the ×32 mode. When not used as DQor DQSpins, the memory interface pins
are available as regular I/O pins.
Optional Parity, DM, and Error Correction Coding Pins
Cyclone III device family supports parity in ×9, ×18, and ×36 modes. One parity bit is
available per eight bits of data pins. You can use any of the DQpins for parity in
Cyclone III device family because the parity pins are treated and configured similar to
DQpins.
DM pins are only required when writing to DDR2 and DDR SDRAM devices.
QDR II SRAM devices use the BWS# signal to select the byte to be written into
memory. A low signal on the DM or BWS# pin indicates the write is valid. Driving the
DM or BWS# pin high causes the memory to mask the DQsignals. Each group of DQS
and DQsignals has one DM pin. Similar to the DQoutput signals, the DM signals are
clocked by the -90° shifted clock.
In Cyclone III device family, the DM pins are preassigned in the device pinouts. The
Quartus II Fitter treats the DQand DM pins in a DQSgroup equally for placement
purposes. The preassigned DQand DM pins are the preferred pins to use.
Some DDR2 SDRAM and DDR SDRAM devices support error correction coding
(ECC), a method of detecting and automatically correcting errors in data
transmission. In 72-bit DDR2 or DDR SDRAM, there are eight ECC pins and 64 data
pins. Connect the DDR2 and DDR SDRAM ECC pins to a separate DQSor DQgroup in
Cyclone III device family. The memory controller needs additional logic to encode
and decode the ECC data.
Address and Control/Command Pins
The address signals and the control or command signals are typically sent at a single
data rate. You can use any of the user I/O pins on all I/O banks of Cyclone III device
family to generate the address and control or command signals to the memory device.
1
Cyclone III device family does not support QDR II SRAM in the burst length of two.
Memory Clock Pins
In DDR2 and DDR SDRAM memory interfaces, the memory clock signals (CK and
CK#) are used to capture the address signals and the control or command signals.
Similarly, QDR II SRAM devices use the write clocks (K and K#) to capture the
address and command signals. The CK/CK# and K/K# signals are generated to
resemble the write-data strobe using the DDIO registers in Cyclone III device family.
f
For more information about CK/CK# pins placement, refer to the “Pin Connection
Guidelines Tables” section in the Planning Pin and FPGA Resources chapter of the
External Memory Interface Handbook.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–11
Cyclone III Device Family Memory Interfaces Features
Cyclone III Device Family Memory Interfaces Features
This section describes Cyclone III device family memory interfaces, including DDR
input registers, DDR output registers, OCT, and phase-lock loops (PLLs).
DDR Input Registers
The DDR input registers are implemented with three internal logic element (LE)
registers for every DQpin. These LE registers are located in the logic array block (LAB)
adjacent to the DDR input pin.
Figure 8–4 shows Cyclone III device family DDR input registers.
Figure 8–4. Cyclone III Device Family DDR Input Registers
DDR Input Registers in Cyclone III Device Family
DQ
LE
Register
dataout_h
Input Register AI
neg_reg_out
dataout_l
LE
Register
LE
Register
Register CI
Input Register BI
Capture Clock
PLL
The DDR data is first fed to two registers, input register AI and input register BI.
■
■
■
Input register AI captures the DDR data present during the rising edge of the clock
Input register BI captures the DDR data present during the falling edge of the clock
Register CI aligns the data before it is synchronized with the system clock
The data from the DDR input register is fed to two registers, sync_reg_hand
sync_reg_l, then the data is typically transferred to a FIFO block to synchronize the
two data streams to the rising edge of the system clock. Because the read-capture
clock is generated by the PLL, the read-data strobe signal (DQSor CQ) is not used
during read operation in Cyclone III device family; hence, postamble is not a concern
in this case.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
8–12
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
DDR Output Registers
A dedicated write DDIO block is implemented in the DDR output and output enable
paths. Figure 8–5 shows how Cyclone III device family dedicated write DDIO block is
implemented in the I/O element (IOE) registers.
Figure 8–5. Cyclone III Device Family Dedicated Write DDIO
DDR Output Enable Registers
Output Enable
IOE
Register
Output Enable
Register AOE
data1
data0
IOE
Register
Output Enable
Register BOE
DDR Output Registers
datain_l
IOE
Register
data0
data1
DQ or DQS
Output Register AO
datain_h
IOE
Register
-90° Shifted Clock
®
Output Register BO
The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through datain_land datain_h, are fed into two registers,
outputregister Aoand outputregister Bo, respectively, on the same clock edge.
The output from outputregisterAois captured on the falling edge of the clock, while
the output from outputregisterBois captured on the rising edge of the clock. The
registered outputs are multiplexed by the common clock to drive the DDR output pin
at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s DQSwrite preamble time specification.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–13
Cyclone III Device Family Memory Interfaces Features
f
For more information about Cyclone III device family IOE registers, refer to the
I/O Features in the Cyclone III Device Family chapter.
Figure 8–6 shows how the second output enable register extends the DQS
high-impedance state by half a clock cycle during a write operation.
(1)
Figure 8–6. Extending the OE Disable by Half a Clock Cycle for a Write Transaction
System clock
(outclock for DQS)
OE for DQS
Delay
90o
(from logic array)
by Half
a Clock
Cycle
Preamble
Postamble
DQS
Write Clock
(outclock for DQ,
o
-90 phase shifted
from System Clock)
datain_h
(from logic array)
D0
D2
D3
datain_I
(from logic array)
D1
OE for DQ
(from logic array)
DQ
D0
D1
D2
D3
Note to Figure 8–6:
(1) The waveform reflects the software simulation result. The OEsignal is an active low on the device. However, the Quartus II software implements
the signal as an active high and automatically adds an inverter before the AOE register D input.
OCT
Cyclone III device family supports calibrated on-chip series termination (RS OCT) in
both vertical and horizontal I/O banks. To use the calibrated OCT, you must use the
RUP and RDN pins for each RS OCT control block (one for each side). You can use
each OCT calibration block to calibrate one type of termination with the same VCCIO
for that given side.
f
For more information about Cyclone III device family OCT calibration block, refer to
the Cyclone III Device I/O Features chapter.
PLL
When interfacing with external memory, the PLL is used to generate the memory
system clock, the write clock, the capture clock and the logic-core clock. The system
clock generates the DQSwrite signals, commands, and addresses. The write-clock is
shifted by -90° from the system clock and generates the DQsignals during writes. You
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
8–14
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Document Revision History
1
The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are
used when the ALTMEMPHY megafunction is instantiated to interface with external
memories.
f
f
For more information about the usage of PLL outputs by the ALTMEMPHY
megafunction, refer to the External Memory Interfaces page.
For more information about Cyclone III device family PLL, refer to the Clock Networks
and PLLs in the Cyclone III Device Family chapter.
Document Revision History
Table 8–3 lists the revision history for this document.
Table 8–3. Document Revision History
Date
July 2012
Version
Changes
3.1
Finalized Table 8–2.
■ Updated “Data and Data Clock/Strobe Pins” on page 8–2 and “Memory Clock Pins” on
page 8–10.
December 2011
3.0
■ Updated hyperlinks.
■ Minor text edits.
■ Removed Tables 8-1, 8-2, 8-3, and 8-4.
■ Changed links to reference Literature: External Memory Interfaces.
Minor changes to the text.
January 2010
2.3
December 2009
July 2009
2.2
2.1
Made minor correction to the part number.
■ Updated chapter part number.
■ Updated “Introduction” on page 8–1.
■ Updated Table 8–1 on page 8–1, Table 8–2 on page 8–2, Table 8–3 on page 8–3,
Table 8–4 on page 8–4, and Table 8–5 on page 8–7. Updated notes to Table 8–6 on
page 8–10. Updated “Data and Data Clock/Strobe Pins” on page 8–5.
June 2009
2.0
■ Updated note to Figure 8–2 on page 8–12.
■ Updated “Optional Parity, DM, and Error Correction Coding Pins” on page 8–13.
■ Updated “Address and Control/Command Pins” on page 8–14.
■ Updated “Introduction”, “DDR Input Registers” and “Conclusion” sections.
■ Updated chapter to new template.
October 2008
May 2008
1.3
1.2
■ Added (Note 4) to Figure 8–3.
■ Updated Table 8–3 and Table 8-5. Added new Table 8–4.
■ Updated (Note 1) to Figure 8-4. Updated Figure 8–5 and 8–14.
■ Updated “Data and Data Clock/Strobe Pins” section.
■ Updated Table 8–5.
July 2007
1.1
1.0
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Section III. System Integration
This section includes the following chapters:
■
Chapter 9, Configuration, Design Security, and Remote System Upgrades in the
Cyclone III Device Family
■
■
■
Chapter 10, Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Chapter 11, SEU Mitigation in the Cyclone III Device Family
Chapter 12, IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device
Family
f
For information about the revision history for chapters in this section, refer to
“Document Revision History” in each individual chapter.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
III–2
Section III: System Integration
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
9. Configuration, Design Security, and
Remote System Upgrades in the
Cyclone III Device Family
August 2012
CIII51016-2.2
CIII51016-2.2
This chapter describes the configuration, design security, and remote system
upgrades in Cyclone® III devices. The Cyclone III device family (Cyclone III and
Cyclone III LS devices) uses SRAM cells to store configuration data. Configuration
data must be downloaded to Cyclone III device family each time the device powers
up because SRAM memory is volatile.
The Cyclone III device family is configured using one of the following configuration
schemes:
■
■
■
■
■
Fast Active serial (AS)
Active parallel (AP) for Cyclone III devices only
Passive serial (PS)
Fast passive parallel (FPP)
Joint Test Action Group (JTAG)
All configuration schemes use an external configuration controller (for example,
MAX® II devices or a microprocessor), a configuration device, or a download cable.
The Cyclone III device family offers the following configuration features:
■
■
■
Configuration data decompression
Design security (for Cyclone III LS devices only)
Remote system upgrade
As Cyclone III LS devices play a role in larger and more critical designs in competitive
commercial and military environments, it is increasingly important to protect your
designs from copying, reverse engineering, and tampering. Cyclone III LS devices
address these concerns with 256-bit advanced encryption standard (AES)
programming file encryption and anti-tamper feature support to prevent tampering.
For more information about the design security feature in Cyclone III LS devices, refer
to “Design Security” on page 9–70.
System designers face difficult challenges such as shortened design cycles, evolving
standards, and system deployments in remote locations. The Cyclone III device
family helps overcome these challenges with inherent re-programmability and
dedicated circuitry to perform remote system upgrades. Remote system upgrades
help deliver feature enhancements and bug fixes without costly recalls, reduce
time-to-market, and extend product life. Remote system upgrades can also be
implemented with the advanced Cyclone III device family features such as real-time
decompression of configuration data. For more information about the remote system
upgrade feature in Cyclone III device family, refer to “Remote System Upgrade” on
page 9–74.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
August 2012
Subscribe
9–2
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
This chapter describes the Cyclone III device family configuration features and
describes how to configure Cyclone III device family using the supported
configuration schemes. This chapter also includes configuration pin descriptions and
the Cyclone III device family configuration file formats. In this chapter, the generic
term “device” includes all Cyclone III device family.
This chapter contains the following sections:
■
■
■
“Configuration Features” on page 9–2
“Design Security” on page 9–70
“Remote System Upgrade” on page 9–74
Configuration Features
Cyclone III device family offers configuration data decompression to reduce
configuration file storage, provides design security feature to protect your
configuration data (for Cyclone III LS devices only), and provides remote system
upgrade to allow you to remotely update your Cyclone III device family designs.
Table 9–1 lists which configuration methods you can use in each configuration
scheme.
Table 9–1. Cyclone III Device Family Configuration Features (Part 1 of 2)
Remote
System
Design
Configuration
Method
Security
Configuration Scheme
Decompression
Upgrade (Cyclone III LS
(1)
Devices Only)
SerialConfiguration
Device
Fast Active Serial Standard (AS Standard POR)
Fast Active Serial Fast (AS Fast POR)
v
v
—
—
v
v
v
v
v
v
—
—
v
SerialConfiguration
Device
Active Parallel ×16 Standard (AP Standard POR, for
Cyclone III devices only)
Supported Flash
(2)
Memory
Active Parallel ×16 Fast (AP Fast POR, for Cyclone III
devices only)
Supported Flash
(2)
Memory
External Host with
Flash Memory
v
v
v
v
—
—
—
—
—
—
Passive Serial Standard (PS Standard POR)
(3)
Download Cable
v
External Host with
Flash Memory
v
Passive Serial Fast (PS Fast POR)
(3)
Download Cable
v
External Host with
Flash Memory
Fast Passive Parallel Fast (FPP Fast POR)
v
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–3
Configuration Features
Table 9–1. Cyclone III Device Family Configuration Features (Part 2 of 2)
Configuration
Remote
System
Design
Security
Configuration Scheme
Decompression
Method
Upgrade (Cyclone III LS
(1)
Devices Only)
External Host with
Flash Memory
—
—
—
—
—
—
JTAG based configuration
Download Cable
Notes to Table 9–1:
(1) Remote update mode is supported when using the remote system upgrade feature. You can enable or disable remote update mode with an option
setting in the Quartus® II software. For more information about the remote system upgrade feature, refer to “Remote System Upgrade” on
page 9–74.
(2) For more information about the supported families for the Micron commodity parallel flash, refer to Table 9–11 on page 9–24.
(3) The design security feature is not supported using a SRAM Object File (.sof).
1
1
1
The design security feature is for Cyclone III LS devices only and is available in all
configuration schemes except the JTAG-based configuration. The decompression
feature is not supported when you have enabled the design security feature.
When using a serial configuration scheme such as PS or fast AS, the configuration
time is the same whether or not you have enabled the design security feature. A ×4
DCLKis required if you use the FPP scheme with the design security feature.
Cyclone III devices support remote system upgrade in AS and AP configuration
schemes. Cyclone III LS devices only support remote system upgrade in the AS
configuration scheme.
This section only describes the decompression feature. For more information about
the design security and remote system upgrade, refer to “Design Security” on
page 9–70 and “Remote System Upgrade” on page 9–74.
Configuration Data Decompression
Cyclone III device family supports configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and send the
compressed bitstream to Cyclone III device family. During configuration, Cyclone III
device family decompress the bitstream in real time and program SRAM cells. The
decompression feature is not supported when you have enabled the design security
feature.
1
1
Compression may reduce the configuration bitstream size by 35 to 55%.
Cyclone III device family supports decompression in the AS and PS configuration
schemes. Decompression is not supported in the AP, FPP, or JTAG-based
configuration schemes. In PS mode, use the Cyclone III device family decompression
feature to reduce configuration time.
Altera recommends using the Cyclone III device family decompression feature during
AS configuration if you must save configuration memory space in the serial
configuration device.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
9–4
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
When you enable compression, the Quartus II software generates configuration files
with compressed configuration data. This compressed file reduces the storage
requirements in the configuration device or flash memory and decreases the time
needed to send the bitstream to the Cyclone III device family. The time needed by a
Cyclone III device family to decompress a configuration file is less than the time
needed to send the configuration data to the device. There are two methods for
enabling compression for Cyclone III device family bitstreams in the Quartus II
software:
■
Before design compilation (using the Compiler Settings menu).
■
After design compilation (use the Convert Programming Files dialog box).
To enable compression in the compiler settings of the project in the Quartus II
software, perform the following steps:
1. On the Assignments menu, click Device. The Settings dialog box appears.
2. Click Device and Pin Options. The Device and Pin Options dialog box appears.
3. Click the Configuration tab.
4. Turn on Generate compressed bitstreams (Figure 9–1).
5. Click OK.
6. In the Settings dialog box, click OK.
Figure 9–1. Enabling Compression for Cyclone III Device Family Bitstreams in Compiler Settings
To enable compression when creating programming files from the Convert
Programming Files window, follow these steps:
1. On the File menu, click Convert Programming Files.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–5
Configuration Features
2. Under Output programming file, from the pull-down menu, select your desired
file type.
3. If you select the Programmer Object File (.pof), you must specify a configuration
device, directly under the file type.
4. In the Input files to convert box, select SOF Data.
5. Click Add File to browse to the Cyclone III device family .sofs.
6. In the Convert Programming Files dialog box, select the .pof you added to SOF
Data and click Properties.
7. In the SOF File Properties dialog box, turn on the Compression option.
When multiple devices in Cyclone III device family are cascaded, you can selectively
enable the compression feature for each device in the chain. Figure 9–2 shows a chain
of two devices in Cyclone III device family. The first device has compression enabled
and receives compressed bitstream from the configuration device. The second device
has the compression feature disabled and receives uncompressed data. You can
generate programming files for this setup from the Convert Programming Files
dialog box from the File menu in the Quartus II software.
Figure 9–2. Compressed and Uncompressed Configuration Data in the Same Configuration File
Serial Data
Serial Configuration
Device
Compressed
Uncompressed
V
CC
Decompression
Controller
10 kΩ
Cyclone III
Device Family
Cyclone III
Device Family
nCE
nCEO
nCE
nCEO
N.C.
GND
Configuration Requirement
The following section describes power-on-reset (POR) for Cyclone III device family.
POR Circuit
The POR circuit keeps the device in the reset state until the power supply voltage
levels have stabilized after device power-up. After device power-up, the device does
not release nSTATUSuntil the required voltages listed in table Table 9–4 on page 9–8
are above the POR trip point of the device. VCCINT and VCCA are monitored for brown-
out conditions after device power-up.
1
VCCA is the analog power to the phase-locked loop (PLL).
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
In Cyclone III device family, you can select either a fast POR time or standard POR
time depending on the MSEL pin settings. The fast POR time is 3 ms < TPOR < 9 ms
for the fast configuration time. The standard POR time is 50 ms < TPOR < 200 ms,
which has a lower power-ramp rate.
Table 9–2 lists the supported POR times for each configuration scheme.
Table 9–2. Cyclone III Device Family Supported POR Times Across Configuration Schemes (1)
Configuration
Voltage
Fast POR Time
Standard POR Time
Configuration Scheme
(3 ms< TPOR < 9 ms) (50 ms< TPOR < 200 ms)
Standard (V) (2)
Fast Active Serial Standard (AS Standard POR)
Fast Active Serial Standard (AS Standard POR)
Fast Active Serial Fast (AS Fast POR)
—
—
v
v
v
v
—
—
3.3
3.0/2.5
3.3
Fast Active Serial Fast (AS Fast POR)
3.0/2.5
Active Parallel ×16 Standard (AP Standard POR, for
Cyclone III devices only)
—
—
—
v
v
v
v
v
—
—
3.3
3.0/2.5
1.8
Active Parallel ×16 Standard (AP Standard POR, for
Cyclone III devices only)
Active Parallel ×16 Standard (AP Standard POR, for
Cyclone III devices only)
Active Parallel ×16 Fast (AP Fast POR, for
Cyclone III devices only)
3.3
Active Parallel ×16 Fast (AP Fast POR, for
Cyclone III devices only)
1.8
Passive Serial Standard (PS Standard POR)
Passive Serial Fast (PS Fast POR)
Fast Passive Parallel Fast (FPP Fast POR)
Fast Passive Parallel Fast (FPP Fast POR)
JTAG-based configuration
—
v
v
v
—
—
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
1.8/1.5
v
—
(3)
(3)
—
Notes to Table 9–2:
(1) Altera recommends connecting the MSEL pins to VCCA or GND depending on the MSEL pin settings.
(2) The configuration voltage standard is applied to the VCCIO supply of the bank in which the configuration pins reside.
(3) JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. However, the
POR time is dependent on the MSEL pin settings.
In some applications, it is necessary for a device to wake up very quickly to begin
operation. The Cyclone III device family offers the fast POR time option to support
fast wake-up time applications. The fast POR time option has stricter power-up
requirements when compared with the standard POR time option. You can select
either the fast POR or standard POR options with the MSEL pin settings.
1
The automotive application is for Cyclone III devices only. The Cyclone III devices
fast wake-up time meets the requirement of common bus standards in automotive
applications, such as Media Orientated Systems Transport (MOST) and Controller
Area Network (CAN).
f
For more information about wake-up time and the POR circuit, refer to the
Hot-Socketing and Power-On Reset in Cyclone III Devices chapter.
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9–7
Configuration Features
Configuration File Size
Table 9–3 lists the uncompressed configuration file sizes for the Cyclone III device
family. To calculate the amount of storage space required for multiple device
configurations, add the file size of each device together.
.
Table 9–3. Cyclone III Device Family Uncompressed Raw Binary File (.rbf) Sizes
Device
Data Size (bits)
3,000,000
EP3C5
EP3C10
3,000,000
EP3C16
4,100,000
EP3C25
5,800,000
Cyclone III
EP3C40
9,600,000
EP3C55
14,900,000
20,000,000
28,600,000
26,766,760
26,766,760
50,610,728
50,610,728
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Use the data in Table 9–3 only to estimate the file size before design compilation.
Different configuration file formats, such as Hexadecimal (.hex) or Tabular Text
File (.ttf) formats, have different file sizes. However, for any specific version of the
Quartus II software, any design targeted for the same device has the same
uncompressed configuration file size. If you are using compression, the file size varies
after each compilation because the compression ratio is design dependent.
f
For more information about setting device configuration options or creating
configuration files, refer to the Software Settings section in volume 2 of the
Configuration Handbook.
Configuration and JTAG Pin I/O Requirements
Cyclone III devices are manufactured using the TSMC 65-nm low-k dielectric process;
Cyclone III LS devices are manufactured using the TSMC 60-nm low-k dielectric
process. Although Cyclone III device family uses TSMC 2.5-V transistor technology in
the I/O buffers, the devices are compatible and able to interface with 2.5-, 3.0-, 3.3-V
configuration voltage standards. However, you must follow specific requirements
when interfacing Cyclone III device family with 2.5-, 3.0-, 3.3-V configuration voltage
standards.
All I/O inputs must maintain a maximum AC voltage of 4.1 V. When using a JTAG
configuration scheme or a serial configuration device in an AS configuration scheme,
you must connect a 25- series resistor at the near end of the TDOand TDIpin or the
serial configuration device for the DATA[0]pin. When cascading Cyclone III device
family in a multi-device configuration, you must connect the repeater buffers between
the master and slave devices for DATAand DCLK
.
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Configuration Features
The output resistance of the repeater buffers must fit the maximum overshoot
equation shown in Equation 9–1:
(1)
Equation 9–1.
0.8Z R 1.8Z
O
E
O
Note to Equation 9–1:
(1) ZO is the transmission line impedance and RE is the equivalent resistance of the output buffer.
Configuration Process
This section describes the configuration process.
f
For more information about the configuration cycle state machine of Altera FPGAs,
refer to the Configuring Altera FPGAs chapter in volume 1 of the Configuration
Handbook.
Power Up
If the device is powered up from the power-down state, the VCCIO for all the I/O
banks must be powered up to the appropriate level for the device to exit POR.
To begin configuration, the required voltages listed in Table 9–4 must be powered up
to the appropriate voltage levels.
Table 9–4. Power-Up Voltage for Cyclone III Device Family Configuration
(1)
Device
Cyclone III
Voltage that must be Powered-Up
(2)
VCCINT, VCCA, VCCIO
(2)
Cyclone III LS
Notes to Table 9–4:
VCCBAT, VCCINT, VCCA, VCCIO
(1) Voltages must be powered up to the appropriate voltage levels to begin configuration.
(2) VCCIO is for banks in which the configuration and JTAG pins reside.
Reset
When nCONFIGor nSTATUSis low, the device is in reset. After power-up, the Cyclone III
device family goes through POR. POR delay depends on the MSEL pin settings,
which correspond to your configuration scheme.
Depending on the configuration scheme, a fast or standard POR time is available.
POR time for fast POR ranges between 3–9 ms. POR time for standard POR, which
has a lower power-ramp rate, ranges between 50–200 ms.
During POR, the device resets, holds nSTATUSand CONF_DONElow, and tri-states all
user I/O pins.
1
The configuration bus is not tri-stated in POR stage if the MSELpins are set to AS or AP
mode. To tri-state the configuration bus for AS and AP configuration schemes, you
must tie nCEhigh and nCONFIGlow. For more information about the hardware
implementation, refer to “Configuring With Multiple Bus Masters” on page 9–30.
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9–9
Configuration Features
When the device exits POR, all user I/O pins continue to tri-state. The user I/O pins
and dual-purpose I/O pins have weak pull-up resistors that are always enabled (after
POR) before and during configuration. After POR, the Cyclone III device family
releases nSTATUS, which is pulled high by an external 10-k pull-up resistor and
enters configuration mode.
When nCONFIGgoes high, the device exits reset and releases the open-drain nSTATUS
pin, which is then pulled high by an external 10-kpull-up resistor. After nSTATUSis
released, the device is ready to receive configuration data and the configuration stage
begins.
Cyclone III LS devices are accessible by limited JTAG instructions after POR. For more
information about enabling full JTAG instructions access, refer to “JTAG Instructions”
on page 9–60.
f
For more information about the value of weak pull-up resistors on the I/O pins that
are on before and during configuration, refer to the Cyclone III Device Data Sheet and
Cyclone III LS Device Data Sheet chapters.
Configuration
Configuration data is latched into the Cyclone III device family at each DCLKcycle.
However, the width of the data bus and the configuration time taken for each scheme
are different. After the device receives all the configuration data, the device releases
the open-drain CONF_DONEpin, which is pulled high by an external 10-kpull-up
resistor. A low-to-high transition on the CONF_DONEpin indicates that configuration is
complete and initialization of the device can begin. The CONF_DONEpin must have an
external 10-k pull-up resistor for the device to initialize.
You can begin reconfiguration by pulling the nCONFIGpin low. The nCONFIGpin must
be low for at least 500 ns. When nCONFIGis pulled low, the Cyclone III device family is
reset. The Cyclone III device family also pulls nSTATUSand CONF_DONElow and all I/O
pins are tri-stated. When nCONFIGreturns to a logic-high level and nSTATUSis released
by the Cyclone III device family, reconfiguration begins.
Configuration Error
If an error occurs during configuration, the Cyclone III device family asserts the
nSTATUSsignal low, indicating a data frame error, and the CONF_DONEsignal stays low.
If the Auto-restart configuration after error option (available in the Quartus II
software from the General tab of the Device and Pin Options dialog box) is turned
on, the Cyclone III device family releases nSTATUSafter a reset time-out period (a
maximum of 230 s), and retries configuration. If this option is turned off, the system
must monitor nSTATUSfor errors and then pulse nCONFIGlow for at least 500 ns to
restart configuration.
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Configuration Features
Initialization
In Cyclone III device family, the clock source for initialization is either a 10-MHz
(typical) internal oscillator (separate from the AS internal oscillator) or an optional
CLKUSRpin. By default, the internal oscillator is the clock source for initialization. If
you use the internal oscillator, the device provides itself with enough clock cycles for a
proper initialization. When using the internal oscillator, you do not need to send
additional clock cycles from an external source to the CLKUSRpin during the
initialization stage. Additionally, you can use the CLKUSRpin as a user I/O pin.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. The CLKUSRpin allows you to control
when your device enters user mode for an indefinite amount of time. You can turn on
the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software
from the General tab of the Device and Pin Options dialog box. When you turn on
the Enable user supplied start-up clock option (CLKUSR) option, the CLKUSRpin is
the initialization clock source. Supplying a clock on the CLKUSRpin does not affect the
configuration process. After the configuration data is accepted and CONF_DONEgoes
high, the Cyclone III device family requires a certain amount of clock cycles to
initialize and to enter user mode.
Table 9–5 lists the required clock cycles for proper initialization in Cyclone III device
family.
Table 9–5. Initialization Clock Cycles Required in Cyclone III Device Family
Device
Initialization Clock Cycles
Cyclone III
3,185
3,192
Cyclone III LS
Table 9–6 lists the maximum CLKUSR frequency (fMAX) for Cyclone III device family.
Table 9–6. Maximum CLKUSR Frequency for Cyclone III Device Family
Device
fMAX (MHz)
133
Cyclone III
Cyclone III LS
100
1
If you use the optional CLKUSRpin and the nCONFIGpin is pulled low to restart
configuration during device initialization, ensure that the CLKUSRpin continues to
toggle when nSTATUSis low (a maximum of 230 s).
User Mode
An optional INIT_DONEpin is available that signals the end of initialization and the
start of user mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONEpin, it is high due to an external
10-k pull-up resistor when nCONFIGis low and during the beginning of
configuration. After the option bit to enable INIT_DONEis programmed into the device
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Configuration Features
(during the first frame of configuration data), the INIT_DONEpin goes low. When
initialization is complete, the INIT_DONEpin is released and pulled high. This low-to-
high transition signals that the device has entered user mode. In user mode, the user
I/O pins function as assigned in your design and no longer have weak pull-up
resistors.
Configuration Scheme
A configuration scheme with different configuration voltage standards is selected by
driving the MSEL pins either high or low, as listed in Table 9–7.
The MSEL pins are powered by VCCINT. The MSEL[3..0]pins have 9-k internal
pull-down resistors that are always active.
1
Smaller Cyclone III devices or package options (E144, M164, Q240, F256, and U256
packages) do not have the MSEL[3]pin. The AS Fast POR configuration scheme at 3.0-
or 2.5-V configuration voltage standard and the AP configuration scheme are not
supported in Cyclone III devices without the MSEL[3] pin. To configure these devices
with other supported configuration schemes, select the MSEL[2..0]pins according to
the MSEL settings in Table 9–7.
1
1
Hardwire the MSEL pins to VCCA or GND without any pull-up or pull-down resistors
to avoid any problems detecting an incorrect configuration scheme. Do not drive the
MSEL pins with a microprocessor or another device.
The Quartus II software prohibits you from using the LVDS I/O standard in I/O
Bank 1 when the configuration device I/O voltage is not 2.5 V. If you need to assign
LVDS I/O standard in I/O Bank 1, navigate to
Assignments>Device>Settings>Device and Pin Option>Configuration to change the
Configuration Device I/O voltage to 2.5 V or Auto.
(1)
Table 9–7. Cyclone III Device Family Configuration Schemes
Configuration Scheme
(Part 1 of 2)
MSEL
Configuration Voltage Standard (V)
(2), (3)
3
2
1
0
Fast Active Serial Standard (AS Standard
POR)
0
0
1
0
3.3
Fast Active Serial Standard (AS Standard
POR)
0
0
1
1
3.0/2.5
Fast Active Serial Fast (AS Fast POR)
Fast Active Serial Fast (AS Fast POR)
1
0
1
1
0
0
1
0
3.3
3.0/2.5
Active Parallel ×16 Standard (AP Standard
POR, for Cyclone III devices only)
0
1
1
0
1
0
0
1
1
1
0
0
1
1
0
1
3.3
3.0/2.5
1.8
Active Parallel ×16 Standard (AP Standard
POR, for Cyclone III devices only)
Active Parallel ×16 Standard (AP Standard
POR, for Cyclone III devices only)
Active Parallel ×16 Fast (AP Fast POR, for
Cyclone III devices only)
3.3
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Configuration Features
(1)
Table 9–7. Cyclone III Device Family Configuration Schemes
Configuration Scheme
(Part 2 of 2)
MSEL
Configuration Voltage Standard (V)
(2), (3)
3
2
1
0
Active Parallel ×16 Fast (AP Fast POR, for
Cyclone III devices only)
0
1
1
0
1.8
Passive Serial Standard (PS Standard POR)
Passive Serial Fast (PS Fast POR)
0
1
1
0
1
1
0
0
1
0
0
0
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
(4)
Fast Passive Parallel Fast (FPP Fast POR)
Fast Passive Parallel Fast (FPP Fast POR)
(for Cyclone III devices only) (4)
1
0
1
0
1
0
1
1
1.8/1.5
1.8/1.5
Fast Passive Parallel Fast (FPP Fast POR)
(for Cyclone III LS devices only)
Fast Passive Parallel Fast (FPP Fast POR)
with Encryption (for Cyclone III LS
devices only)
0
1
0
1
3.3/3.0/2.5
Fast Passive Parallel Fast (FPP Fast POR)
with Encryption (for Cyclone III LS
devices only)
0
1
1
0
1.8/1.5
—
(5)
(6)
(6)
(6)
(6)
JTAG-based configuration
Notes to Table 9–7:
(1) Altera recommends connecting the MSEL pins to VCCA or GND depending on the MSEL pin settings.
(2) The configuration voltage standard is applied to the VCCIO supply of the bank in which the configuration pins reside.
(3) You must follow specific requirements when interfacing Cyclone III device family with 2.5-, 3.0-, and 3.3-V configuration voltage standards. For
more information about these requirements, refer to “Configuration and JTAG Pin I/O Requirements” on page 9–7.
(4) FPP configuration is not supported in the Cyclone III E144 device package of Cyclone III devices.
(5) The JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored.
(6) Do not leave the MSEL pins floating. Connect them to VCCA or GND. These pins support the non-JTAG configuration scheme used in production.
Altera recommends connecting the MSEL pins to GND if your device is only using the JTAG configuration.
AS Configuration (Serial Configuration Devices)
In the AS configuration scheme, Cyclone III device family is configured using a serial
configuration device. These configuration devices are low-cost devices with
non-volatile memories that feature a simple four-pin interface and a small form factor.
These features make serial configuration devices the ideal low-cost configuration
solution.
f
For more information about serial configuration devices, refer to the Serial
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
In Cyclone III device family, the active master clock frequency runs at a maximum of
40 MHz, and typically at 30 MHz. Cyclone III device family only work with serial
configuration devices that support up to 40 MHz.
Serial configuration devices provide a serial interface to access configuration data.
During device configuration, Cyclone III device family reads configuration data using
the serial interface, decompress data if necessary, and configure their SRAM cells. This
scheme is referred to as the AS configuration scheme because the device controls the
configuration interface.
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Configuration Features
1
If you want to gain control of the EPCS pins, hold the nCONFIGpin low and pull the
nCEpin high to cause the device to reset and tri-state the AS configuration pins.
Single-Device AS Configuration
The four-pin interface of serial configuration devices consists of the following pins:
■
■
■
■
Serial clock input (DCLK
Serial data output (DATA
AS data input (ASDI
Active-low chip select (nCS
)
)
)
)
This four-pin interface connects to Cyclone III device family pins, as shown in
Figure 9–3.
Figure 9–3. Single-Device AS Configuration
V
(1)
V
(1)
CCIO
CCIO
V
(1)
CCIO
10 kΩ
10 kΩ
Serial Configuration
10 kΩ
Cyclone III Device Family
Device
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
GND
25 Ω (6)
DATA
DCLK
nCS
DATA[0]
DCLK
nCSO (5)
ASDO (5)
ASDI
MSEL[3..0]
(4)
(2)
Notes to Figure 9–3:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Cyclone III device family uses the ASDO-to-ASDIpath to control the configuration device.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(5) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions
as the DATA[1]pin in other AP and FPP modes.
(6) Connect the series resistor at the near end of the serial configuration device.
1
1
To tri-state the configuration bus for AS configuration schemes, you must tie nCEhigh
and nCONFIGlow.
When connecting a serial configuration device to a Cyclone III device family in the
single-device AS configuration, you must connect a 25- series resistor at the near
end of the serial configuration device for DATA[0]. The 25- resistor in the series
works to minimize the driver impedance mismatch with the board trace and reduce
overshoot seen at the Cyclone III device family DATA[0]input pin.
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Configuration Features
In a single-device AS configuration, the maximum board loading and board trace
length between the supported serial configuration device and the Cyclone III device
family must follow the recommendations in Table 9–9 on page 9–20.
The DCLKgenerated by the Cyclone III device family controls the entire configuration
cycle and provides timing for the serial interface. Cyclone III device family uses a 40-
MHz internal oscillator to generate DCLK. There are some variations in the internal
oscillator frequency because of the process, voltage, and temperature conditions in
Cyclone III device family. The internal oscillator is designed to ensure that its
maximum frequency is guaranteed to meet the EPCS device specifications.
1
EPCS1 does not support Cyclone III device family because of its insufficient memory
capacity.
Table 9–8 lists the AS DCLKoutput frequency for Cyclone III device family.
Table 9–8. AS DCLK Output Frequency
Oscillator
Minimum
Typical
Maximum
Unit
40 MHz
20
30
40
MHz
In the AS configuration scheme, the serial configuration device latches input and
control signals on the rising edge of DCLKand drives out configuration data on the
falling edge. Cyclone III device family drives out control signals on the falling edge of
DCLKand latch configuration data on the falling edge of DCLK
.
In configuration mode, the Cyclone III device family enables the serial configuration
device by driving the nCSOoutput pin low, which connects to the nCSpin of the
configuration device. The Cyclone III device family uses the DCLKand DATA[1]pins to
send operation commands and read address signals to the serial configuration device.
The configuration device provides data on its DATApin, which connects to the DATA[0]
input of the Cyclone III device family.
After all the configuration bits are received by the Cyclone III device family, it releases
the open-drain CONF_DONEpin, which is pulled high by an external 10-k resistor.
Initialization begins only after the CONF_DONEsignal reaches a logic-high level. All AS
configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal pull-up
resistors that are always active. After configuration, these pins are set as input tri-
stated and are driven high by weak internal pull-up resistors. The CONF_DONEpin must
have an external 10-k pull-up resistor for the device to initialize.
The timing parameters for AS mode are not listed here because the tCF2CD, tCF2ST0, tCFG
STATUS, tCF2ST1, and tCD2UM timing parameters are identical to the timing parameters
,
t
for PS mode listed in Table 9–13 on page 9–39.
Multi-Device AS Configuration
You can configure multiple Cyclone III device family using a single serial
configuration device. You can cascade multiple Cyclone III device family using the
chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in the chain must
have its nCEpin connected to GND. You must connect its nCEOpin to the nCEpin of the
next device in the chain. Use an external 10-k pull-up resistor to pull the nCEOsignal
high to its VCCIO level to help the internal weak pull-up resistor. When the first device
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Configuration Features
captures all its configuration data from the bitstream, it drives the nCEOpin low,
enabling the next device in the chain. You can leave the nCEOpin of the last device
unconnected or use it as a user I/O pin after configuration if the last device in the
chain is a Cyclone III device family. The nCONFIG
,
nSTATUS
,
CONF_DONE
,
DCLK, and
DATA[0]pins of each device in the chain are connected (Figure 9–4).
Figure 9–4. Multi-device AS Configuration
V
(1)
V
(1)
V
(1)
CCIO
CCIO
CCIO
V
(2)
CCIO
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Serial Configuration
Master Device of the
Cyclone III Device Family
Device
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
nCEO
GND
25 Ω (6)
(6), (8)
DATA
DATA[0]
DATA[0]
DCLK
50 Ω
DCLK
DCLK
nCS
ASDI
nCSO (5)
ASDO (5)
MSEL[3..0]
(4)
MSEL[3..0]
(4)
(8)
50 Ω
Buffers (7)
Notes to Figure 9–4:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) You can leave the nCEOpin unconnected or use it as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device
family in AS mode and the slave devices in PS mode. To connect MSEL[3..0]for the master device in AS mode and slave devices in PS mode,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(5) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions as the DATA[1]pin in other
AP and FPP modes.
(6) Connect the series resistor at the near end of the serial configuration device.
(7) Connect the repeater buffers between the master and slave devices of the Cyclone III device family for DATA[0]and DCLK. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
“Configuration and JTAG Pin I/O Requirements” on page 9–7.
(8) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
The first Cyclone III device family in the chain is the configuration master and
controls the configuration of the entire chain. You must connect its MSEL pins to
select the AS configuration scheme. The remaining Cyclone III device family is
configuration slaves and you must connect their MSEL pins to select the PS
configuration scheme. Any other Altera device that supports PS configuration can
also be part of the chain as a configuration slave.
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Configuration Features
1
1
When connecting a serial configuration device to the Cyclone III device family in the
multi-device AS configuration, you must connect a 25- series resistor at the near end
of the serial configuration device for DATA[0]
.
In the multi-device AS configuration, the board trace length between the serial
configuration device to the master device of the Cyclone III device family must follow
the recommendations in Table 9–9 on page 9–20. You must also connect the repeater
buffers between the master and slave devices of the Cyclone III device family for
DATA[0]and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The
output resistance of the repeater buffers must fit the maximum overshoot equation
outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
As shown in Figure 9–4 on page 9–15, the nSTATUSand CONF_DONEpins on all target
devices are connected together with external pull-up resistors. These pins are
open-drain bidirectional pins on the devices. When the first device asserts nCEO(after
receiving all its configuration data), it releases its CONF_DONEpin. However, the
subsequent devices in the chain keep this shared CONF_DONEline low until they receive
their configuration data. When all target devices in the chain receive their
configuration data and release CONF_DONE, the pull-up resistor drives a high level on
this line and all devices simultaneously enter initialization mode.
1
Although you can cascade Cyclone III device family, serial configuration devices
cannot be cascaded or chained together.
If the configuration bitstream size exceeds the capacity of a serial configuration
device, you must select a larger configuration device, enable the compression feature,
or both. When configuring multiple devices, the size of the bitstream is the sum of the
individual devices configuration bitstreams.
Configuring Multiple Cyclone III Device Family with the Same Design
Certain designs require you to configure multiple Cyclone III device family with the
same design through a configuration bitstream or a .sof. You can do this using the
following methods:
■
Multiple SRAM Object Files
Single SRAM Object File
■
1
For both methods, the serial configuration devices cannot be cascaded or
chained together.
Multiple SRAM Object Files
Two copies of the .sof are stored in the serial configuration device. Use the first copy
to configure the master device of the Cyclone III device family and the second copy to
configure all the remaining slave devices concurrently. All slave devices must be of
the same density and package. The setup is similar to Figure 9–4 on page 9–15, in
which the master device is set up in AS mode and the slave devices are set up in PS
mode.
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Configuration Features
To configure four identical Cyclone III device family with the same .sof, you must set
up the chain similar to Figure 9–5. The first device is the master device and its MSEL
pins must be set to select the AS configuration. The other three slave devices are set
up for concurrent configuration and their MSEL pins must be set to select the PS
configuration. The nCEOpin from the master device drives the nCEinput pins on all
three slave devices, as well as the DATAand DCLKpins that connect in parallel to all
four devices. During the first configuration cycle, the master device reads its
configuration data from the serial configuration device while holding nCEOhigh. After
completing its configuration cycle, the master device drives nCElow and sends the
second copy of the configuration data to all three slave devices, configuring them
simultaneously.
The advantage of using the setup in Figure 9–5 is that you can have a different .sof for
the master device. However, all the slave devices must be configured with the same
.sof. In this configuration method, you can either compress or uncompress the .sofs.
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Configuration Features
1
You can still use this method if the master and slave devices use the same .sof.
Figure 9–5. Multi-Device AS Configuration where the Devices Receive the Same Data with Multiple SRAM Object Files
Slave Device of the Cyclone III Device Family
V
(1)
V
(1)
V
(1)
V
(2)
CCIO
CCIO
CCIO
CCIO
nSTATUS
CONF_DONE
nCONFIG
nCE
10 kΩ
10 kΩ
10 kΩ
10 kΩ
nCEO
N.C. (3)
DATA[0]
DCLK
MSEL[3..0]
(4)
Master Device of the
Cyclone III Device
Family
Serial Configuration
Slave Device of the Cyclone III Device Family
Device
nSTATUS
nSTATUS
CONF_DONE
nCONFIG
nCE
CONF_DONE
nCONFIG
nCE
nCEO
nCEO
N.C. (3)
GND
25 Ω (6)
(6),(8)
DATA
DATA[0]
DATA[0]
DCLK
50 Ω
DCLK
nCS
ASDI
DCLK
nCSO (5)
ASDO (5)
MSEL[3..0]
(4)
MSEL[3..0]
(4)
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
(8)
50 Ω
Buffers (7)
DATA[0]
DCLK
MSEL[3..0]
(4)
Notes to Figure 9–5:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AS mode and the slave
devices in PS mode. To connect MSEL[3..0]for the master device in AS mode and the slave devices in PS mode, refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to VCCA or GND.
(5) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions as the DATA[1]pin in other
AP and FPP modes.
(6) Connect the series resistor at the near end of the serial configuration device.
(7) Connect the repeater buffers between the master and slave devices for DATA[0]and DCLK. All I/O inputs must maintain a maximum AC voltage
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O
Requirements” on page 9–7.
(8) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
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Configuration Features
Single SRAM Object File
The second method configures both the master device and slave devices with the
same .sof. The serial configuration device stores one copy of the .sof. This setup is
shown in Figure 9–6 where the master is set up in AS mode and the slave devices are
set up in PS mode. You must set up one or more slave devices in the chain. All the
slave devices must be set up as shown in Figure 9–6.
Figure 9–6. Multi-Device AS Configuration where the Devices Receive the Same Data with a Single .sof
V
(1)
V
(1)
V
(1)
CCIO
CCIO
CCIO
10 kΩ
10 kΩ
10 kΩ
Slave Device 2 of the Cyclone III
Slave Device 1 of the Cyclone III
Master Device of the Cyclone III
Serial Configuration
Device Family
Device Family
Device
Device Family
nSTATUS
nSTATUS
nSTATUS
CONF_DONE
nCONFIG
CONF_DONE
nCONFIG
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (2)
GND
nCE
nCEO
N.C. (2)
nCE
nCEO
N.C. (2)
GND
GND
(5)
25 Ω
DATA[0]
DCLK
DATA[0]
DATA
DATA[0]
DCLK
(5),(7)
50 Ω
DCLK
nCS
ASDI
DCLK
nCSO (4)
ASDO (4)
MSEL[3..0]
(3)
MSEL[3..0]
(3)
MSEL[3..0]
(3)
50 Ω(7)
Buffers (6)
Notes to Figure 9–6:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device
family in AS mode and the slave devices in PS mode. To connect MSEL[3..0]for the master device in AS mode and slave devices in PS mode,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(4) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions as the DATA[1]pin in other
AP and FPP modes.
(5) Connect the series resistor at the near end of the serial configuration device.
(6) Connect the repeater buffers between the master and slave devices for DATA[0]and DCLK. All I/O inputs must maintain a maximum AC voltage
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O
Requirements” on page 9–7.
(7) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
In this setup, all the Cyclone III device family in the chain are connected for
concurrent configuration. This can reduce the AS configuration time because all the
Cyclone III device family is configured in one configuration cycle. Connect the nCE
input pins of all the Cyclone III device family to ground. You can either leave the nCEO
output pins on all the Cyclone III device family unconnected or use the nCEOoutput
pins as normal user I/O pins. The DATAand DCLKpins are connected in parallel to all
the Cyclone III device family.
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Configuration Features
Altera recommends putting a buffer before the DATAand DCLKoutput from the master
device to avoid signal strength and integrity issues. The buffer must not significantly
change the DATA-to-DCLKrelationships or delay them with respect to other AS signals
(ASDIand nCS). Also, the buffer must only drive the slave devices to ensure that the
timing between the master device and the serial configuration device is unaffected.
This configuration method supports both compressed and uncompressed .sofs.
Therefore, if the configuration bitstream size exceeds the capacity of a serial
configuration device, you can enable the compression feature in the .sof or you can
select a larger serial configuration device.
Guidelines for Connecting Serial Configuration Device to Cyclone III Device
Family on AS Interface
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and Cyclone III device family must
follow the recommendations listed in Table 9–9.
Table 9–9. Maximum Trace Length and Loading for the AS Configuration
Cyclone III
Device Family
AS Pins
Maximum Board Trace Length from the
Cyclone III Device Family to the Serial
Configuration Device (Inches)
Maximum Board Load (pF)
DCLK
DATA[0]
nCSO
10
10
10
10
15
30
30
30
ASDO
Estimating AS Configuration Time
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Cyclone III device family. This serial interface is clocked
by the Cyclone III device family DCLKoutput (generated from an internal oscillator).
Equation 9–2 and Equation 9–3 show the configuration time estimation for the
Cyclone III device family.
Equation 9–2.
maximum DCLK period
----------------------------------------------------------------
Size
= estimated maximum configuration ti
1 bit
Equation 9–3.
50 ns
1 bit
------------
3,500,000 bits
= 175 ms
To estimate the typical configuration time, use the typical DCLKperiod shown in
Figure 9–7 on page 9–22. With a typical DCLKperiod of 33.33 ns, the typical
configuration time is 116.7 ms. Enabling compression reduces the amount of
configuration data that is sent to the Cyclone III device family, which also reduces
configuration time. On average, compression reduces configuration time by 50%.
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Configuration Features
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash memory-based devices. You can
program these devices in-system using the USB-Blaster™ or ByteBlaster™ II
download cable. Alternatively, you can program them using the Altera Programming
Unit (APU), supported third-party programmers, or a microprocessor with the
SRunner software driver.
You can perform in-system programming of serial configuration devices using the AS
programming interface. During in-system programming, the download cable disables
device access to the AS interface by driving the nCEpin high. Cyclone III device family
is also held in reset by a low level on nCONFIG. After programming is complete, the
download cable releases nCEand nCONFIG, allowing the pull-down and pull-up
resistors to drive GND and VCC, respectively.
To perform in-system programming of a serial configuration device using the AS
programming interface, the diodes and capacitors must be placed as close as possible
to the Cyclone III device family. Ensure that the diodes and capacitors maintain a
maximum AC voltage of 4.1 V (Figure 9–7).
1
If you wish to use the same setup shown in Figure 9–7 to perform in-system
programming of a serial configuration device and single- or multi-device AS
configuration, you do not need a series resistor on the DATAline at the near end of the
serial configuration device. The existing diodes and capacitors are sufficient.
Altera has developed the Serial FlashLoader (SFL), a JTAG-based in-system
programming solution for Altera serial configuration devices. The SFL is a bridge
design for the Cyclone III device family that uses its JTAG interface to access the
EPCS JIC (JTAG Indirect Configuration Device Programming) file and then uses the
AS interface to program the EPCS device. Both the JTAG interface and AS interface
are bridged together inside the SFL design.
f
f
For more information about implementing the SFL with Cyclone III device family,
refer to AN 370: Using the Serial FlashLoader with the Quartus II Software.
For more information about the USB-Blaster download cable, refer to the USB-Blaster
Download Cable User Guide. For more information about the ByteBlaster II download
cable, refer to the ByteBlaster II Download Cable User Guide.
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Configuration Features
Figure 9–7 shows the download cable connections to the serial configuration device.
Figure 9–7. In-System Programming of Serial Configuration Devices
V
(1)
V
(1)
V
CCIO
(1)
CCIO
CCIO
10 kΩ
10 kΩ
10 kΩ
Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (2)
3.3 V
3.3 V
10 kΩ
3.3 V
Serial
Configuration Device
3.3 V
GND
(6)
DATA
DCLK
nCS
DATA[0] (7)
DCLK (7)
nCSO (5)
ASDI
ASDO (5)
MSEL[3..0]
(4)
Pin 1
3.3 V (3)
GND
GND
10 pf
10 pf
10 pf
ByteBlaster II or USB Blaster
10-Pin Male Header
GND
GND
GND
10 pf
(6)
GND
Notes to Figure 9–7:
(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) Power up the VCC of the ByteBlaster II or USB-Blaster download cable with the 3.3-V supply.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to VCCA or ground.
(5) These are dual-purpose I/O pins. This nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions as the DATA[1]pin in other
AP and FPP modes.
(6) The diodes and capacitors must be placed as close as possible to the Cyclone III device family. Ensure that the diodes and capacitors maintain a
maximum AC voltage of 4.1 V. The external diodes and capacitors are required to prevent damage to the Cyclone III device family AS configuration
input pins due to possible overshoot when programming the serial configuration device using a download cable. For effective voltage clamping,
Altera recommends using the Schottky diode, which has a relatively lower forward diode voltage (VF) than the switching and Zener diodes. For
more information about the interface guidelines using Schottky diodes, refer to AN 523: Cyclone III Configuration Interface Guidelines with EPCS
Devices.
(7) When cascading Cyclone III device family in a multi-device AS configuration, connect the repeater buffers between the master and slave devices
for DATA[0]and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the
maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
You can use the Quartus II software with the APU and the appropriate configuration
device programming adapter to program serial configuration devices. All serial
configuration devices are offered in an 8- or 16-pin small outline integrated circuit
(SOIC) package.
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Configuration Features
In production environments, serial configuration devices are programmed using
multiple methods. Altera programming hardware or other third-party programming
hardware is used to program blank serial configuration devices before they are
mounted onto PCBs. Alternatively, you can use an on-board microprocessor to
program the serial configuration device in-system by porting the reference C-based
SRunner software driver provided by Altera.
A serial configuration device is programmed in-system by an external microprocessor
using the SRunner software driver. The SRunner software driver is a software driver
developed for embedded serial configuration device programming, which is easily
customized to fit in different embedded systems. The SRunner software driver is able
to read a Raw Programming Data (.rpd) file and write to the serial configuration
devices. The serial configuration device programming time using the SRunner
software driver is comparable to the programming time with the Quartus II software.
f
For more information about the SRunner software driver, refer to AN 418: SRunner:
An Embedded Solution for Serial Configuration Device Programming and the source code
at the Altera website (www.altera.com).
AP Configuration (Supported Flash Memories)
The AP configuration scheme is for Cyclone III devices only. In the AP configuration
scheme, Cyclone III devices are configured using commodity 16-bit parallel flash
memory. These external non-volatile configuration devices are industry standard
microprocessor flash memories. The flash memories provide a fast interface to access
the configuration data. The speed-up in configuration time is mainly due to the 16-bit
wide parallel data bus, which is used to retrieve data from the flash memory.
Some of the smaller Cyclone III devices or package options do not support the AP
configuration scheme and do not have the MSEL[3]pin. Table 9–10 lists the supported
AP configuration scheme for each Cyclone III device.
Table 9–10. Supported AP Configuration Scheme for Cyclone III Devices
Package Options
Device
E144 M164 Q240
F256
—
F324
—
F484
—
F780
—
U256
—
U484
—
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
—
—
—
v
—
—
v
v
—
—
—
—
v
v
v
v
v
v
v
v
—
v
v
v
—
—
—
—
—
—
—
—
—
During device configuration, Cyclone III devices read configuration data using the
parallel interface and configure their SRAM cells. This scheme is referred to as the AP
configuration scheme because the device controls the configuration interface. This
scheme contrasts with the FPP configuration scheme, where an external host controls
the interface.
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Configuration Features
AP Configuration Supported Flash Memory
The AP configuration controller in Cyclone III devices is designed to interface with
the Micron P30 Parallel NOR flash family and the Micron P33 Parallel NOR flash
family, which are two industry standard flash families. Unlike serial configuration
devices, both of the flash families supported in the AP configuration scheme are
designed to interface with microprocessors. By configuring from an industry standard
microprocessor flash which allows access to the flash after entering user mode, the AP
configuration scheme allows you to combine configuration data and user data
(microprocessor boot code) on the same flash memory.
The Micron P30 and P33 flash families support a continuous synchronous burst read
mode at 40 MHz DCLKfrequency for reading data from the flash. Additionally, the
Micron P30 and P33 flash families have identical pin-out and adopt similar protocols
for data access.
1
Cyclone III devices use a 40-MHz oscillator for the AP configuration scheme.
Table 9–11 lists the supported families of the commodity parallel flash for the AP
configuration scheme.
Table 9–11. Supported Commodity Flash for the AP Configuration Scheme for Cyclone III
(1)
Devices
(2)
(3)
Flash Memory Density
64 Mbit
Micron P30 Flash Family
Micron P33 Flash Family
v
v
v
v
v
v
128 Mbit
256 Mbit
Notes to Table 9–11:
(1) The AP configuration scheme only supports flash memory speed grades of 40 MHz and above.
(2) 3.3- , 3.0-, 2.5-, and 1.8-V I/O options are supported for the Micron P30 flash family.
(3) 3.3-, 3.0- and 2.5-V I/O options are supported for the Micron P33 flash family.
The AP configuration scheme of Cyclone III devices supports the Micron P30 and P33
family 64-, 128-, and 256-Mbit flash memories. Configuring Cyclone III devices from
the Micron P30 and P33 family 512-Mbit flash memory is possible, but you must
properly drive the extra address and FLASH_nCEpins as required by these flash
memories.
1
You must refer to the respective flash data sheets to check for supported speed grades
and package options.
The AP configuration scheme in Cyclone III devices supports flash speed grades of
40 MHz and above. However, the AP configuration for all these speed grades must be
capped at 40 MHz. The advantage of faster speed grades is realized when your design
in the Cyclone III device accesses flash memory in user mode.
f
For more information about the operation of the Micron P30 Parallel NOR and P33
flash memories, search for the keyword “P30” or “P33” on the Micron website
(www.micron.com) to obtain the P30 or P33 family data sheet.
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Configuration Features
Single-Device AP Configuration
The following groups of interface pins are supported in Micron P30 and P33 flash
memories:
■
■
■
Control pins
Address pins
Data pins
Following are the control signals from the supported parallel flash memories:
■
■
■
■
■
■
CLK
active-low reset (RST#
)
active-low chip enable (CE#)
active-low output enable (OE#
)
active-low address valid (ADV#
)
active-low write enable (WE#
)
The supported parallel flash memories output a control signal (WAIT) to Cyclone III
devices to indicate when synchronous data is ready on the data bus. Cyclone III
devices have a 24-bit address bus connecting to the address bus (A[24:1]) of the flash
memory. A 16-bit bidirectional data bus (DATA[15..0]) provides data transfer between
the Cyclone III device and the flash memory.
The following are the control signals from the Cyclone III device to flash memory:
■
■
■
■
■
■
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
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Configuration Features
The interface for the Micron P30 flash memory and P33 flash memory connects to
Cyclone III device pins, as shown in Figure 9–8.
Figure 9–8. Single-Device AP Configuration Using Micron P30 and P33 Flash Memory
V
CCIO
(1) V
(1) V (1)
CCIO
CCIO
10k
10k
10k
UTS
A
SnT
CnONFGI
N.C. (2)
(3)
nCEO
FC_DOEN
nCE
GND
MSEL[3..0]
CLK
RST#
CE#
DCLK
nRESET
FLASH_nCE
nOE
OE#
ADV#
WE#
nAVD
nWE
WAIT
I/O (4)
DQ[15:0]
A[24:1]
DATA[15..0]
PADD[23..0]
Micron P30/P33 Flash
Cyclone III Device
Notes to Figure 9–8:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to VCCA or GND.
(4) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use a normal I/O to monitor the WAITsignal from the Micron P30 or P33 flash.
1
1
To tri-state the configuration bus for AP configuration schemes, you must tie nCEhigh
and nCONFIGlow.
In a single-device AP configuration, the maximum board loading and board trace
length between the supported parallel flash and Cyclone III devices must follow the
recommendations listed in Table 9–12 on page 9–30.
1
If you use the AP configuration scheme for Cyclone III devices, the VCCIO of I/O
banks 1, 6, 7, and 8 must be 3.3, 3.0, 2.5, or 1.8 V. Altera does not recommend using the
level shifter between the Micron P30/P33 flash and the Cyclone III device in the AP
configuration scheme.
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Configuration Features
1
There are no series resistors required in the AP configuration mode for Cyclone III
devices when using the Micron flash at 2.5-, 3.0-, and 3.3-V I/O standard. The output
buffer of the Micron P30 IBIS model does not overshoot above 4.1 V. Thus, series
resistors are not required for the 2.5-, 3.0-, and 3.3-V AP configuration option.
However, if there are any other devices sharing the same flash I/Os with Cyclone III
devices, all shared pins are still subject to the 4.1-V limit and may require series
resistors.
The default read mode of the supported parallel flash memory and all writes to the
parallel flash memory are asynchronous. Both the parallel flash families support a
synchronous read mode, with data supplied on the positive edge of DCLK
.
■
■
■
■
nRESETis an active-low hard reset
FLASH_nCEis an active-low chip enable
nOEis an active-low output enable for the DATA[15..0]bus and WAITpin
nAVDis an active-low address valid signal and is used to write addresses into the
flash
■
■
■
nWEis an active-low write enable and is used to write data into the flash
PADD[23..0]bus is the address bus supplied to the flash
DATA[15..0] bus is a bidirectional bus used to supply and read data to and from
the flash, with the flash output controlled by nOE
The serial clock (DCLK) generated by Cyclone III devices controls the entire
configuration cycle and provides timing for the parallel interface. Cyclone III devices
use a 40-Mhz internal oscillator to generate DCLK. The oscillator is the same oscillator
used in the AS configuration scheme. The active DCLKoutput frequency is listed in
Table 9–8 on page 9–14.
Multi-Device AP Configuration
You can cascade multiple Cyclone III devices using the chip-enable (nCE) and chip-
enable-out (nCEO) pins. The first device in the chain must have its nCEpin connected to
GND. Connect its nCEOpin to the nCEpin of the next device in the chain. Use an
external 10-k pull-up resistor to pull the nCEOsignal high to its VCCIO level to help
the internal weak pull-up resistor. When the first device captures all its configuration
data from the bitstream, it drives the nCEOpin low, enabling the next device in the
chain. You can leave the nCEOpin of the last device unconnected or use it as a user I/O
pin after configuration if the last device in the chain is a Cyclone III device. The
nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[15..8], and DATA[7..0]pins of each device
in the chain are connected (Figure 9–9 on page 9–28 and Figure 9–10 on page 9–29).
The first Cyclone III device in the chain, as shown in Figure 9–9 on page 9–28 and
Figure 9–10 on page 9–29, is the configuration master device and controls the
configuration of the entire chain. Connect its MSEL pins to select the AP configuration
scheme. The remaining Cyclone III devices are used as configuration slaves. Connect
their MSEL pins to select the FPP configuration scheme. Any other Altera device that
supports FPP configuration can also be part of the chain as a configuration slave.
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Configuration Features
The following are the configurations for the DATA[15..0]bus in a multi-device AP
configuration:
■
Byte-wide multi-device AP configuration
Word-wide multi-device AP configuration
■
Byte-Wide Multi-Device AP Configuration
The simpler method for multi-device AP configuration is the byte-wide multi-device
AP configuration. In the byte-wide multi-device AP configuration, the LSB of the
DATA[7..0]pin from the flash and master device (set to the AP configuration scheme)
is connected to the slave devices set to the FPP configuration scheme, as shown in
Figure 9–9.
Figure 9–9. Byte-Wide Multi-Device AP Configuration
V
(1)
V
CCIO
V
CCIO
(1)
V
CCIO
(1)
(2)
V
CCIO
(2)
10 k
Ω
CCIO
10 kΩ
10 kΩ
10 kΩ
10 kΩ
S
S
TUS
A
A
A
T
T
nST
F
F
nOCNFIG
O
O
C_FDONE
nCE
nCEO
nCE
nCEO
nCE
nCEO
N.C. (3)
GND
CLK
RST#
CE#
DCLK
nRESET
FLASH_nCE
nOE
nAVD
OE#
ADV#
WE#
WAIT
MSEL[3..0]
MSEL[3..0]
MSEL[3..0]
(4)
DQ[7..0]
(4)
DQ[7..0]
(4)
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
DATA[7..0]
DCLK
DATA[7..0]
DCLK
DQ[15:0]
A[24:1]
Micron P30/P33 Flash
Cyclone III Master Device
Cyclone III Slave Device
Cyclone III Slave Device
Buffers (6)
Notes to Figure 9–9:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
devices in FPP mode. To connect MSEL[3..0]for the master device in AP mode and the slave devices in FPP mode, refer to Table 9–7 on
page 9–11. Connect the MSEL pins directly to VCCA or GND.
(5) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the WAITsignal from the Micron P30 or P33 flash.
(6) Connect the repeater buffers between the master device and slave devices for DATA[15..0]and DCLK. All I/O inputs must maintain a maximum
AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG
Pin I/O Requirements” on page 9–7.
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Configuration Features
Word-Wide Multi-Device AP Configuration
The more efficient setup is one in which some of the slave devices are connected to the
LSB of DATA[7..0]and the remaining slave devices are connected to the MSB of
DATA[15..8]. In the word-wide multi-device AP configuration, the nCEOpin of the
master device enables two separate daisy-chains of slave devices, allowing both
chains to be programmed concurrently, as shown in Figure 9–10.
Figure 9–10. Word-Wide Multi-Device AP Configuration
V
(1)
CCIO
(1)
V
(1)
CCIO
V
CCIO
V
CCIO
(2)
V
CCIO
(2)
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
S
S
TUS
A
A
A
T
T
nST
F
F
nOCNFIG
O
O
C_FDONE
nCE
nCEO
nCE
nCEO
nCE
nCEO N.C. (3)
GND
CLK
RST#
CE#
DCLK
nRESET
FLASH_nCE
nOE
OE#
ADV#
WE#
WAIT
nAVD
nWE
MSEL[3..0]
MSEL[3..0]
MSEL[3..0]
(4)
(4)
DQ[7..0]
(4)
DQ[7..0]
I/O (5)
DATA[15..0]
PADD[23..0]
DATA[7..0]
DCLK
DATA[7..0]
DCLK
DQ[15:0]
A[24:1]
Micron P30/P33 Flash
Cyclone III Master Device
Cyclone III Slave Device
Cyclone III Slave Device
V
CCIO
(1)
Buffers (6)
10 kΩ
S
TUS
A
A
T
nST
F
nOCNFIG
O
C_FDONE
nCE
nCEO
nCE
nCEO
N.C. (3)
DQ[15..8]
MSEL[3..0]
MSEL[3..0]
(4)
(4)
DATA[7..0]
DCLK
DATA[7..0]
DCLK
DQ[15..8]
Cyclone III Slave Device
Cyclone III Slave Device
Notes to Figure 9–10:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
devices in FPP mode. To connect MSEL[3..0]for the master device in AP mode and the slave devices in FPP mode, refer to Table 9–7 on
page 9–11. Connect the MSEL pins directly to VCCA or GND.
(5) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O pin to monitor the WAITsignal from the Micron P30 or P33 flash.
(6) Connect the repeater buffers between the Cyclone III master device and slave devices for DATA[15..0]and DCLK. All I/O inputs must maintain a
maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration
and JTAG Pin I/O Requirements” on page 9–7.
1
In a multi-device AP configuration, the board trace length between the parallel flash
and the master device must follow the recommendations listed in Table 9–12.
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Configuration Features
As shown in Figure 9–9 and Figure 9–10, the nSTATUSand CONF_DONEpins on all target
devices are connected together with external pull-up resistors. These pins are open-
drain bidirectional pins on the devices. When the first device asserts nCEO(after
receiving all its configuration data), it releases its CONF_DONEpin. However, the
subsequent devices in the chain keep this shared CONF_DONEline low until they receive
their configuration data. When all target devices in the chain receive their
configuration data and release CONF_DONE, the pull-up resistor drives a high level on
this line and all devices simultaneously enter initialization mode.
Guidelines for Connecting Parallel Flash to Cyclone III Devices for the AP
Interface
For the single- and multi-device AP configuration, the board trace length and loading
between the supported parallel flash and Cyclone III devices must follow the
recommendations listed in Table 9–12. These recommendations also apply to an AP
configuration with multiple bus masters.
Table 9–12. Maximum Trace Length and Loading for the AP Configuration
Maximum Board Trace Length from the
Cyclone III AP Pins
Cyclone III Device to the Flash Device
(Inches)
Maximum Board Load (pF)
DCLK
6
6
6
6
6
6
6
6
6
15
30
30
30
30
30
30
30
30
DATA[15..0]
PADD[23..0]
nRESET
Flash_nCE
nOE
nAVD
nWE
(1)
I/O
Note to Table 9–12:
(1) The AP configuration ignores the WAITsignal from the flash during configuration mode. However, if you are
accessing flash during user mode with user logic, you can optionally use the normal I/O to monitor the WAITsignal
from the Micron P30 or P33 flash.
Configuring With Multiple Bus Masters
Similar to the AS configuration scheme, the AP configuration scheme supports
multiple bus masters for the parallel flash. For another master to take control of the
AP configuration bus, the master must assert nCONFIGlow for at least 500 ns to reset
the master Cyclone III device and override the weak 10 k pull-down resistor on the
nCEpin. This resets the master Cyclone III device and causes it to tri-state its AP
configuration bus. The other master then takes control of the AP configuration bus.
After the other master is done, it releases the AP configuration bus, then releases the
nCEpin, and finally pulses nCONFIGlow to restart the configuration.
In the AP configuration scheme, multiple masters share the parallel flash. Similar to
the AS configuration scheme, the bus control is negotiated by the nCEpin.
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Configuration Features
Figure 9–11 shows the AP configuration with multiple bus masters.
Figure 9–11. AP Configuration with Multiple Bus Masters
(6)
Other Master Device
V
CCIO
(1)
V
CCIO
(1) V
CCIO
(1)
#V
IAT
10 k
K
T
#
#
D
#
W
:
:
O
nOCNFIG
10 k
10 k
UTS
A
SnT
CnONFGI
nCE
FC_DOEN
10 k
nCEO
(2)
GND
CLK
RST#
CE#
DCLK (5)
nRESET
FLASH_nCE
nOE
nAVD
OE#
ADV#
WE#
WAIT
MSEL[3..0]
(3)
nWE
I/O (4)
DATA[15..0] (5)
PADD[23..0]
DQ[15:0]
A[24:1]
Micron P30/P33 Flash
Cyclone III Master Device
Notes to Figure 9–11:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to VCCA or GND.
(4) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the WAITsignal from the Micron P30 or P33 flash.
(5) When cascading Cyclone III devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave devices
for DATA[15..0]and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit
the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
(6) The other master device must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
(7) The other master device can control the AP configuration bus by driving the nCE pin to high with an output high on the I/O pin.
(8) The other master device can pulse nCONFIGif it is under system control rather than tied to VCCIO
.
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Configuration Features
Figure 9–12 shows the recommended balanced star routing for multiple bus master
interfaces to minimize signal integrity issue.
Figure 9–12. Balanced Star Routing
External
Master Device
N (2)
DCLK
M (1)
N (2)
Cyclone III
Master Device
Micron Flash
Notes to Figure 9–12:
(1) Altera does not recommend M to exceed six inches as listed in Table 9–12 on page 9–30.
(2) Altera recommends using a balanced star routing. Try to keep the N length equal and as short as possible to minimize
reflection noise from the transmission line. The M length is applicable for this setup.
Estimating the AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to the Cyclone III devices. This parallel interface is clocked by the
Cyclone III DCLKoutput (generated from an internal oscillator). As listed in Table 9–8
on page 9–14, the DCLKminimum frequency when using the 40-MHz oscillator is
20 MHz (50 ns). In word-wide cascade programming, the DATA[15..0]bus transfers a
16-bit word and essentially cuts configuration time to approximately 1/16 of the AS
configuration time. Therefore, the maximum configuration time estimation for an
EP3C40 device (9,600,000 bits of uncompressed data) is defined in Equation 9–4 and
Equation 9–5.
Equation 9–4.
maximum DCLK period
16 bits per DCLK cycle
----------------------------------------------------------------
Size
= estimated maximum configuration ti
Equation 9–5.
50 ns
16 bits
----------------
9,600,000 bits
= 30 ms
To estimate a typical configuration time, use the typical DCLKperiod listed in Table 9–8
on page 9–14. With a typical DCLKperiod of 33.33 ns, the typical configuration time is
20 ms.
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Configuration Features
Programming Parallel Flash Memories
Supported parallel flash memories are external non-volatile configuration devices.
They are industry standard microprocessor flash memories. For more information
about the supported families for the commodity parallel flash, refer to Table 9–11 on
page 9–24.
Cyclone III devices in a single- or multiple-device chains support in-system parallel
flash programming with the JTAG interface using the flash loader megafunction. For
Cyclone III devices, the board-intelligent host or download cable uses four JTAG pins
to program the parallel flash in system, even if the host or download cable cannot
access the configuration pins of the parallel flash.
f
1
For more information about using the JTAG pins on Cyclone III devices to program
the parallel flash in-system, refer to AN 478: Using FPGA-Based Parallel Flash Loader
(PFL) with the Quartus II Software.
In the AP configuration scheme, the default configuration boot address is 0×010000
when represented in 16-bit word addressing in the supported parallel flash memory
(Figure 9–13). In the Quartus II software, the default configuration boot address is
0x020000 because it is represented in 8-bit byte addressing. Cyclone III devices
configure from word address 0x010000, which is equivalent to byte address 0x020000.
The Quartus II software uses byte addressing for the default configuration boot
address. You must set the start address field to 0x020000.
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Configuration Features
The default configuration boot addressing allows the system to use special parameter
blocks in the flash memory map. Parameter blocks are at the top or bottom of the
memory map. The configuration boot address in the AP configuration scheme is
shown in Figure 9–13. You can change the default configuration default boot address
0x010000 to any desired address using the APFC_BOOT_ADDR JTAG instruction. For
more information about the APFC_BOOT_ADDR JTAG instruction, refer to “JTAG
Instructions” on page 9–60.
Figure 9–13. Configuration Boot Address in AP Flash Memory Map
Bottom Parameter Flash Memory
Top Parameter Flash Memory
128-Kb
parameter area
Other data/code
Other data/code
Cyclone III
Default
Boot
Cyclone III
Default
Boot
Address
Address
Configuration
Data
Configuration
Data
x010000 (1)
x00FFF
x010000 (1)
x00FFF
Other data/code
16-bit word
128-Kb
parameter area
16-bit word
x000000
x000000
bit[15]
bit[0]
bit[15]
bit[0]
Note to Figure 9–13:
(1) The default configuration boot address is x010000 when represented in 16-bit word addressing.
PS Configuration
You can perform PS configuration on Cyclone III device family with an external
intelligent host, such as a MAX II device, microprocessor with flash memory, or a
download cable. In the PS scheme, an external host controls the configuration.
Configuration data is clocked into the target Cyclone III device family using the
DATA[0]pin at each rising edge of DCLK
.
If your system already contains a common flash interface (CFI) flash memory, you can
use it for the Cyclone III device family configuration storage as well. The MAX II PFL
feature provides an efficient method to program CFI flash memory devices through
the JTAG interface and provides the logic to control the configuration from the flash
memory device to the Cyclone III device family. Both PS and FPP configuration
schemes are supported using the PFL feature.
f
1
For more information about the PFL, refer to Parallel Flash Loader Megafunction User
Guide.
Cyclone III device family does not support enhanced configuration devices for PS or
FPP configurations.
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Configuration Features
PS Configuration Using an External Host
In the PS configuration scheme, you can use an intelligent host such as MAX II or
microprocessor that controls the transfer of configuration data from a storage device,
such as flash memory, to the target Cyclone III device family. You can store the
configuration data in .rbf, .hex, or .ttf format.
Figure 9–14 shows the configuration interface connections between a Cyclone III
device family and an external host device for a single-device configuration.
Figure 9–14. Single-Device PS Configuration Using an External Host
Cyclone III
Device Family
Memory
V
V
CCIO(1)
CCIO(1)
ADDR DATA[0]
10 kΩ
10 kΩ
(3)
MSEL[3..0]
CONF_DONE
nSTATUS
nCE
nCEO N.C. (2)
External Host
(MAX II Device or
Microprocessor)
GND
DATA[0] (4)
nCONFIG
DCLK (4)
Notes to Figure 9–14:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC must be high
enough to meet the VIH specification of the I/O on the device and the external host.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or ground.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0]and DCLKmust fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
To begin configuration, the external host device must generate a low-to-high
transition on the nCONFIGpin. When nSTATUSis pulled high, the external host device
must place the configuration data one bit at a time on the DATA[0]pin. If you are using
configuration data in a .rbf, .ttf, or .hex file, you must first send the LSB of each data
byte. For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the serial
bitstream you must send to the device is:
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111
Cyclone III device family receives configuration data on the DATA[0]pin and the clock
is received on the DCLKpin. Data is latched into the device on the rising edge of DCLK
.
Data is continuously clocked into the target device until CONF_DONEgoes high and the
device enters the initialization state.
1
Two DCLKfalling edges are required after CONF_DONEgoes high to begin device
initialization.
The INIT_DONEpin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
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Configuration Features
To ensure DCLKand DATA[0]are not left floating at the end of configuration, the MAX
II device must drive them either high or low, whichever is convenient on your board.
The DATA[0]pin is available as a user I/O pin after configuration. In the PS scheme,
the DATA[0]pin is tri-stated by default in user mode and must be driven by the
external host device. To change this default option in the Quartus II software, select
the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified system frequency to
ensure correct configuration (Figure 9–19 on page 9–42). No maximum DCLKperiod
exists, which means you can pause configuration by halting DCLKfor an indefinite
amount of time.
If a configuration error occurs during configuration and the Auto-restart
configuration after error option is turned on, the Cyclone III device family releases
nSTATUSafter a reset time-out period (a maximum of 230 s). After nSTATUSis released
and pulled high by a pull-up resistor, the external host device tries to reconfigure the
target device without needing to pulse nCONFIGlow. If this option is turned off, the
external host device must generate a low-to-high transition (with a low pulse of at
least 500 ns) on nCONFIGto restart the configuration process.
The external host device can also monitor the CONF_DONEand INIT_DONEpins to ensure
successful configuration. The CONF_DONEpin must be monitored by the external device
to detect errors and to determine when the programming is complete. If all
configuration data is sent, but CONF_DONEor INIT_DONEhas not gone high, the external
device must reconfigure the target device.
Figure 9–15 shows how to configure multiple devices using an external host device.
This circuit is similar to the PS configuration circuit for a single device, except that the
Cyclone III device family is cascaded for multi-device configuration.
Figure 9–15. Multi-Device PS Configuration Using an External Host
Memory
V
CCIO (2)
Cyclone III Device Family 2
V
V
Cyclone III Device Family 1
CCIO (1) CCIO (1)
ADDR DATA[0]
10 k
10 k
10 k
(4)
(4)
MSEL[3..0]
MSEL[3..0]
CONF_DONE
CONF_DONE
nSTATUS
nSTATUS
nCE
nCE
nCEO
nCEO N.C. (3)
External Host
(MAX II Device or
Microprocessor)
GND
DATA[0] (5)
nCONFIG
DCLK (5)
DATA[0] (5)
nCONFIG
DCLK (5)
Buffers (5)
Notes to Figure 9–15:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or ground.
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0]and DCLK must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
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Configuration Features
In a multi-device PS configuration, the nCEpin of the first device is connected to GND
while its nCEOpin is connected to the nCEpin of the next device in the chain. The nCE
input of the last device comes from the previous device, while its nCEOpin is left
floating. After the first device completes configuration in a multi-device configuration
chain, its nCEOpin drives low to activate the nCEpin of the second device, which
prompts the second device to begin configuration. The second device in the chain
begins configuration in one clock cycle. Therefore, the transfer of data destinations is
transparent to the external host device. All other configuration pins (nCONFIG
,
nSTATUS, DCLK,
DATA[0], and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLKand DATAlines are buffered. Because all
device CONF_DONEpins are tied together, all devices initialize and enter user mode at
the same time.
If any device detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured because all nSTATUSand CONF_DONEpins are tied together.
For example, if the first device flags an error on nSTATUS, it resets the chain by pulling
its nSTATUSpin low. This behavior is similar to a single device detecting an error.
You can have multiple devices that contain the same configuration data in your
system. To support this configuration scheme, all device nCEinputs are tied to GND,
while the nCEOpins are left floating. All other configuration pins (nCONFIG
DATA[0], and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
, nSTATUS,
DCLK
,
clock skew problems. Ensure that the DCLKand DATAlines are buffered. Devices must
be of the same density and package. All devices start and complete configuration at
the same time.
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Configuration Features
Figure 9–16 shows a multi-device PS configuration when both Cyclone III device
family is receiving the same configuration data.
Figure 9–16. Multi-Device PS Configuration When Both Devices Receive the Same Data
Memory
V
(1)
V (1)
Cyclone III Device Family
CCIO
CCIO
Cyclone III Device Family
ADDR DATA[0]
10 k
10 k
(3)
(3)
MSEL[3..0]
MSEL[3..0]
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
nCE
nCEO
N.C. (2)
N.C. (2)
nCE
nCEO
External Host
(MAX II Device or
Microprocessor)
GND
GND
DATA[0] (4)
nCONFIG
DCLK (4)
DATA[0] (4)
nCONFIG
DCLK (4)
Buffers (4)
Notes to Figure 9–16:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.
(2) The nCEOpins of both devices are left unconnected or used as user I/O pins when configuring the same configuration
data into multiple devices.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or ground.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0]and DCLKmust fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
PS Configuration Timing
A PS configuration must meet the setup and hold timing parameters and the
maximum clock frequency. When using a microprocessor or another intelligent host
to control the PS interface, ensure that you meet these timing requirements.
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Configuration Features
Figure 9–17 shows the timing waveform for a PS configuration when using an
external host device as an external host.
(1)
Figure 9–17. PS Configuration Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
DCLK
(4)
tDH
DATA[0]
(5)
Bit 0 Bit 1 Bit 2 Bit 3
tDSU
Bit n
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
User Mode
tCD2UM
Notes to Figure 9–17:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONE
are at logic-high levels. When nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds nSTATUSlow during POR delay.
(3) After power-up, before and during configuration, CONF_DONEis low.
(4) In user mode, drive DCLKeither high or low when using the PS configuration scheme, whichever is more convenient.
When using the AS configuration scheme, DCLKis a Cyclone III device family output pin and must not be driven
externally.
(5) Do not leave the DATA[0]pin floating after configuration. Drive it high or low, whichever is more convenient.
Table 9–13 lists the PS configuration timing parameters for Cyclone III device family.
Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 1 of 2)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
500
Unit
ns
—
—
500
ns
500
45
—
ns
(1)
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
nSTATUSlow pulse width
800
s
s
s
s
ns
(2)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLKhigh time
—
800
(1)
800
—
—
—
—
—
—
—
2
5
tDH
0
ns
tCH
3.2
ns
tCL
DCLKlow time
3.2
ns
tCLK
DCLKperiod
7.5
ns
(4)
fMAX
DCLKfrequency
—
300
100
MHz
s
—
(3)
tCD2UM
tCD2CU
CONF_DONEhigh to user mode
650
—
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLKperiod
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 2 of 2)
Symbol
Parameter
Minimum
Maximum
Unit
t
CD2CU + (initialization clock
tCD2UMC CONF_DONEhigh to user mode with CLKUSR option on
—
—
(5)
cycles × CLKUSRperiod)
Notes to Table 9–13:
(1) This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(2) This value is applicable if you do not delay configuration by externally holding nSTATUSlow.
(3) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting the device.
(4) Cyclone III devices can support a DCLKfMAX of 133 MHz. Cyclone III LS devices can support a DCLKfMAX of 100 MHz.
(5) For more information about the initialization clock cycles required in Cyclone III device family, refer to Table 9–5 on page 9–10.
PS Configuration Using a Download Cable
In this section, the generic term "download cable" includes the Altera USB-Blaster
universal serial bus (USB) port download cable, MasterBlaster™ serial/USB
communications cable, ByteBlaster II parallel port download cable, the
ByteBlasterMV™ parallel port download cable, and the Ethernet-Blaster
communications cable.
In the PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the device using the download cable.
The programming hardware or download cable then places the configuration data
one bit at a time on the DATA[0]pin of the device. The configuration data is clocked
into the target device until CONF_DONEgoes high. The CONF_DONEpin must have an
external 10-k pull-up resistor for the device to initialize.
When you use a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no effect on the device
initialization because this option is disabled in the .sof when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you do not need to provide a clock on CLKUSRwhen you are
configuring the device with the Quartus II programmer and a download cable.
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Configuration Features
Figure 9–18 shows PS configuration for Cyclone III device family using a download
cable.
Figure 9–18. PS Configuration Using a USB-Blaster, MasterBlaster, ByteBlaster II,
ByteBlasterMV, or Ethernet Blaster Cable
V
(1)
CCA
10 kΩ
(2)
VCCA (1)
10kΩ
VCCA (1)
10kΩ
VCCA (1)
VCCA (1)
10kΩ
(2)
Cyclone III Device Family
10kΩ
CONF_DONE
nSTATUS
MSEL[3..0] (5)
nCE
Download Cable 10-Pin Male
Header (Top View)
nCEO N.C. (4)
GND
DCLK
DATA[0]
nCONFIG
Pin 1
VCCA (6)
GND
VIO (3)
Shield
GND
Notes to Figure 9–18:
(1) The pull-up resistor must be connected to the same supply voltage as the VCCA supply.
(2) You only need the pull-up resistors on DATA[0]and DCLKif the download cable is the only configuration scheme
used on your board. This is to ensure that DATA[0]and DCLKare not left floating after configuration. For example,
if you are also using a configuration device, you do not need the pull-up resistors on DATA[0]and DCLK
.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the
device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. For the USB Blaster,
ByteBlaster II, ByteBlaster MV, and Ethernet Blaster, this pin is a no connect.
(4) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(5) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11 for PS configuration schemes. Connect the MSEL pins directly to VCCA or GND.
(6) Power up the VCC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V supply from VCCA
.
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable.
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.
You can use a download cable to configure multiple Cyclone III device family by
connecting the nCEOpin of each device to the nCEpin of the subsequent device. The
nCEpin of the first device is connected to GND while its nCEOpin is connected to the
nCEpin of the next device in the chain. The nCEinput of the last device comes from the
previous device while its nCEOpin is left floating. All other configuration pins,
nCONFIG, nSTATUS, DCLK, DATA[0], and CONF_DONEare connected to every device in the
chain. Because all CONF_DONEpins are tied together, all devices in the chain initialize
and enter user mode at the same time.
In addition, the entire chain halts configuration if any device detects an error because
the nSTATUSpins are tied together. The Auto-restart configuration after error option
does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs.
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–19 shows PS configuration for multi Cyclone III device family using a
MasterBlaster, USB-Blaster, ByteBlaster II, or ByteBlasterMV cable.
Figure 9–19. Multi-Device PS Configuration Using a USB-Blaster, MasterBlaster, ByteBlaster II,
ByteBlasterMV, or Ethernet Blaster Cable
V
(1)
CCA
Download Cable
10-Pin Male Header
10 kΩ
(2)
V
(1)
CCA
V
(1)
V
(1)
CCA
CCA
10 kΩ
(Passive Serial Mode)
10 kΩ
10 kΩ
(2)
Cyclone III Device Family 1
Pin 1
V
(7)
CONF_DONE
nSTATUS
DCLK
CCA
V
(4)
CCIO
10 kΩ
MSEL[3..0] (6)
GND
VIO (3)
V
(1)
CCA
nCE
10 kΩ
GND
DATA[0]
nCONFIG
nCEO
GND
Cyclone III Device Family 2
CONF_DONE
nSTATUS
MSEL[3..0]
DCLK
(6)
nCEO N.C. (5)
nCE
DATA[0]
nCONFIG
Notes to Figure 9–19:
(1) The pull-up resistor must be connected to the same supply voltage as the VCCA supply.
(2) You only need the pull-up resistors on DATA[0]and DCLKif the download cable is the only configuration scheme
used on your board. This is to ensure that DATA[0] and DCLKare not left floating after configuration. For example, if
you are also using a configuration device, you do not need the pull-up resistors on DATA[0]and DCLK
.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the
device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In ByteBlasterMV,
this pin is a no connect. In USB-Blaster, ByteBlaster II, and Ethernet Blaster, this pin is connected to nCEwhen it is
used for AS programming. Otherwise, it is a no connect.
(4) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(5) The nCEOpin of the last device in the chain is left unconnected or used as a user I/O pin.
(6) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]for
PS configuration schemes, refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(7) Power up the VCC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V supply from VCCA
.
Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable.
The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from
the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.
FPP Configuration
The FPP configuration in Cyclone III device family is designed to meet the increasing
demand for faster configuration time. Cyclone III device family is designed with the
capability of receiving byte-wide configuration data per clock cycle.
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Configuration Features
You can perform the FPP configuration of Cyclone III device family with an intelligent
host, such as a MAX II device or microprocessor with flash memory. If your system
already contains a CFI flash memory, you can use it for the Cyclone III device family
configuration storage as well. The MAX II PFL feature in MAX II devices provides an
efficient method to program CFI flash memory devices through the JTAG interface
and the logic to control configuration from the flash memory device to the Cyclone III
device family. Both PS and FPP configuration schemes are supported using this PFL
feature.
f
1
1
For more information about the PFL, refer to Parallel Flash Loader Megafunction User
Guide.
Cyclone III device family does not support enhanced configuration devices for PS or
FPP configurations.
FPP configuration is not supported in the E144 package of Cyclone III devices.
FPP Configuration Using an External Host
The FPP configuration using an external host provides a fast method to configure
Cyclone III device family. In the FPP configuration scheme, you can use an external
host device to control the transfer of configuration data from a storage device, such as
flash memory, to the target Cyclone III device family. You can store configuration data
in either an .rbf, .hex, or .ttf format. When using the external host, a design that
controls the configuration process, such as fetching the data from flash memory and
sending it to the device, must be stored in the external host device. Figure 9–20 shows
the configuration interface connections between the Cyclone III device family and an
external device for single-device configuration.
Figure 9–20. Single-Device FPP Configuration Using an External Host
Memory
V (1) V (1)
CCIO CCIO
Cyclone III Device Family
ADDR DATA[7..0]
10 k
10 k
MSEL[3..0]
(3)
CONF_DONE
nSTATUS
nCEO N.C. (2)
nCE
External Host
(MAX II Device or
Microprocessor)
GND
(4)
DATA[7..0]
nCONFIG
(4)
DCLK
Notes to Figure 9–20:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC must be high
enough to meet the VIH specification of the I/O on the device and the external host.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0]and DCLKmust fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
After nSTATUSis released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUSis pulled high, the external host device
places the configuration data one byte at a time on the DATA[7..0]pins.
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Configuration Features
Cyclone III device family receives configuration data on the DATA[7..0]pins and the
clock is received on the DCLKpin. Data is latched into the device on the rising edge of
DCLK. Data is continuously clocked into the target device until CONF_DONEgoes high.
The CONF_DONEpin goes high one byte early in FPP configuration mode. The last byte
is required for serial configuration (AS and PS) modes.
1
Two DCLKfalling edges are required after CONF_DONEgoes high to begin the
initialization of the device.
Supplying a clock on CLKUSRdoes not affect the configuration process. After the
CONF_DONEpin goes high, CLKUSRis enabled after the time specified as tCD2CU. After
this time period elapses, Cyclone III device family requires certain amount of clock
cycles to initialize properly and enter user mode. For more information about the
initialization clock cycles required in the Cyclone III device family, refer to Table 9–5
on page 9–10. For more information about the supported CLKUSRfMAX value for
Cyclone III device family, refer to Table 9–14 on page 9–47.
The INIT_DONEpin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
To ensure that DCLKand DATA[0]are not left floating at the end of the configuration,
the MAX II device must drive them either high or low, whichever is convenient on
your board. The DATA[0]pin is available as a user I/O pin after configuration. When
you choose the FPP scheme in the Quartus II software, the DATA[0]pin is tri-stated by
default in user mode and must be driven by the external host device. To change this
default option in the Quartus II software, select the Dual-Purpose Pins tab of the
Device and Pin Options dialog box.
The DCLKspeed must be below the specified system frequency to ensure correct
configuration. No maximum DCLKperiod exists, which means you can pause
configuration by halting DCLKfor an indefinite amount of time.
If a configuration error occurs during configuration and the Auto-restart
configuration after error option is turned on, the Cyclone III device family releases
nSTATUSafter a reset time-out period (a maximum of 230 s). After nSTATUSis released
and pulled high by a pull-up resistor, the external host device can try to reconfigure
the target device without needing to pulse nCONFIGlow. If this option is turned off, the
external host device must generate a low-to-high transition (with a low pulse of at
least 500 ns) on nCONFIGto restart the configuration process.
The external host device can also monitor the CONF_DONEand INIT_DONEpins to ensure
successful configuration. The CONF_DONEpin must be monitored by the external device
to detect errors and to determine when programming is complete. If all configuration
data is sent but CONF_DONEor INIT_DONEhas not gone high, the external device must
reconfigure the target device.
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9–45
Configuration Features
Figure 9–21 shows how to configure multiple devices using a MAX II device. This
circuit is similar to the FPP configuration circuit for a single device, except the
Cyclone III device family is cascaded for a multi-device configuration.
Figure 9–21. Multi-Device FPP Configuration Using an External Host
Memory
V
CCIO (2)
Cyclone III Device Family 2
10 k
V
(1)
V
(1)
CCIO
CCIO
Cyclone III Device Family 1
ADDR DATA[7..0]
10 k
10 k
(4)
(4)
MSEL[3..0]
MSEL[3..0]
CONF_DONE
CONF_DONE
nSTATUS
nSTATUS
nCE
nCE
nCEO
nCEO N.C. (3)
External Host
(MAX II Device or
Microprocessor)
GND
DATA[7..0] (5)
nCONFIG
DCLK (5)
DATA[7..0] (5)
nCONFIG
DCLK (5)
Buffers (5)
Notes to Figure 9–21:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or ground.
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0]and DCLKmust fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
In a multi-device FPP configuration, the nCEpin of the first device is connected to
GND while its nCEOpin is connected to the nCEpin of the next device in the chain. The
nCEinput of the last device comes from the previous device while its nCEOpin is left
floating. After the first device completes configuration in a multi-device configuration
chain, its nCEOpin drives low to activate the nCEpin of the second device, which
prompts the second device to begin configuration. The second device in the chain
begins configuration in one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device. All other configuration pins (nCONFIG
, nSTATUS,
DCLK
,
DATA[7..0], and CONF_DONE) are connected to every device in the chain. The
configuration signals may require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLKand DATAlines are buffered. All devices
initialize and enter user mode at the same time because all device CONF_DONEpins are
tied together.
All nSTATUSand CONF_DONEpins are tied together and if any device detects an error,
configuration stops for the entire chain and the entire chain must be reconfigured. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUSpin low. This behavior is similar to a single device detecting an error.
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Configuration Features
If a system has multiple devices that contain the same configuration data, tie all
device nCEinputs to GND and leave nCEOpins floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLKand DATAlines are buffered.
Devices must be of the same density and package. All devices start and complete
configuration at the same time.
Figure 9–22 shows multi-device FPP configuration when both Cyclone III device
family is receiving the same configuration data.
Figure 9–22. Multi-Device FPP Configuration Using an External Host When Both Devices Receive
the Same Data
Memory
V
CCIO
(1)
V
CCIO
(1)
Cyclone III Device Family 1
Cyclone III Device Family 2
ADDR DATA[7..0]
10 k
10 k
(3)
(3)
MSEL[3..0]
MSEL[3..0]
CONF_DONE
nSTATUS
CONF_DONE
nSTATUS
nCE
nCEO
nCE
nCEO N.C. (2)
N.C. (2)
External Host
(MAX II Device or
Microprocessor)
GND
GND
DATA[7..0] (4)
nCONFIG
DCLK (4)
DATA[7..0] (4)
nCONFIG
DCLK (4)
Buffers (4)
Notes to Figure 9–22:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.
(2) The nCEOpins of both devices are left unconnected or used as user I/O pins when configuring the same configuration
data into multiple devices.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]
,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0]and DCLKmust fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
You can use a single configuration chain to configure Cyclone III device family with
other Altera devices that support the FPP configuration. To ensure that all devices in
the chain complete configuration at the same time or that an error flagged by one
device starts reconfiguration in all devices, tie all the device CONF_DONEand nSTATUS
pins together.
f
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in
volume 2 of the Configuration Handbook.
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Configuration Features
FPP Configuration Timing
Figure 9–23 shows the timing waveform for FPP configuration when using an
external host.
(1)
Figure 9–23. FPP Configuration Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
(5)
Byte 2
Byte 3
Byte n-1
Byte 0
Byte 1
Byte n
DATA[7..0]
User Mode
User Mode
tDSU
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
tCD2UM
Notes to Figure 9–23:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONE
are at logic-high levels. When nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds nSTATUSlow during POR delay.
(3) After power-up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0]is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
settings.
Table 9–14 lists the FPP configuration timing parameters for Cyclone III device family.
Table 9–14. FPP Timing Parameters for Cyclone III Device Family (Part 1 of 2)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
500
Unit
ns
—
—
500
ns
500
45
—
ns
(1)
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
nSTATUSlow pulse width
230
s
s
s
s
ns
(1)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATAsetup time before rising edge on DCLK
DATAhold time after rising edge on DCLK
DCLKhigh time
—
230
(1)
230
—
—
—
—
—
—
—
2
5
tDH
0
ns
tCH
3.2
3.2
7.5
—
300
ns
tCL
DCLKlow time
ns
tCLK
DCLKperiod
ns
(3)
fMAX
DCLKfrequency
100
MHz
s
(2)
tCD2UM
CONF_DONEhigh to user mode
650
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Configuration Features
Table 9–14. FPP Timing Parameters for Cyclone III Device Family (Part 2 of 2)
Symbol
tCD2CU
Parameter
Minimum
Maximum
Unit
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLKperiod
tCD2CU + (initialization clock
cycles × CLKUSRperiod)
—
—
CONF_DONEhigh to user mode with CLKUSR
tCD2UMC
—
—
(4)
option on
Notes to Table 9–14:
(1) This value is applicable if users do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(2) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting up the device.
(3) Cyclone III EP3C5, EP3C10, EP3C16, EP3C25, and EP3C40 devices support a DCLKfMAX of 133 MHz. Cyclone III EP3C55, EP3C80, EP3C120 and
all the Cyclone III LS devices support a DCLKfMAX of 100 MHz.
(4) For more information about the initialization clock cycles required in Cyclone III device family, refer to Table 9–5 on page 9–10.
JTAG Configuration
JTAG has developed a specification for boundary-scan testing. This boundary-scan
test (BST) architecture offers the capability to efficiently test components on PCBs
with tight lead spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is operating normally.
You can also use the JTAG circuitry to shift configuration data into the device. The
Quartus II software automatically generates .sofs that are used for JTAG
configuration with a download cable in the Quartus II software programmer.
f
1
For more information about JTAG boundary-scan testing, refer to the IEEE 1149.1
(JTAG) Boundary-Scan Testing for Cyclone III Devices chapter.
For the Cyclone III device, JTAG instructions have precedence over any other device
configuration modes. Therefore, JTAG configuration can take place without waiting
for other configuration modes to complete. For example, if you attempt JTAG
configuration of a Cyclone III device during PS configuration, PS configuration
terminates and JTAG configuration begins. If the Cyclone III device MSEL pins are set
to AS mode, the Cyclone III device does not output a DCLKsignal when JTAG
configuration takes place.
For the Cyclone III LS device, JTAG programming is disabled if the device was
already configured using the PS or AS mode. After POR, the Cyclone III LS device
allows only mandatory JTAG 1149.1 instructions (BYPASS
, SAMPLE/RELOAD, EXTEST, and
FACTORY). For more information, refer to “JTAG Instructions” on page 9–60.
The four required pins for a device operating in JTAG mode are TDI, TDO, TMS, and TCK.
The TCKpin has an internal weak pull-down resistor while the TDIand TMSpins have
weak internal pull-up resistors (typically 25 k). The TDOoutput pin is powered by
V
CCIO in I/O bank 1. All the JTAG input pins are powered by the VCCIO pin. All the
JTAG pins support only LVTTL I/O standard. All user I/O pins are tri-stated during
JTAG configuration. Table 9–15 lists the function of each JTAG pin.
1
The TDOoutput is powered by the VCCIO power supply of I/O bank 1.
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9–49
Configuration Features
f
For more information about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing
for Cyclone III Devices chapter.
Table 9–15. Dedicated JTAG Pins
Pin
Pin Type
Name
Description
Serial input pin for instructions as well as test and programming data. Data shifts in on the
rising edge of TCK. The TDIpin is powered by the VCCIO supply. If the JTAG interface is not
required on the board, the JTAG circuitry is disabled by connecting this pin to VCC.
TDI
TDO
Test data input
Serial data output pin for instructions as well as test and programming data. Data shifts out on
the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. The
TDOpin is powered by VCCIO in I/O bank 1. If the JTAG interface is not required on the board, the
JTAG circuitry is disabled by leaving this pin unconnected.
Test data output
Input pin that provides the control signal to determine the transitions of the TAP controller state
machine. Transitions in the state machine occur on the rising edge of TCK. Therefore, TMSmust
Test mode select be set up before the rising edge of TCK. TMSis evaluated on the rising edge of TCK. The TMSpin
TMS
TCK
is powered by the VCCIO supply. If the JTAG interface is not required on the board, the JTAG
circuitry is disabled by connecting this pin to VCC.
Clock input to the BST circuitry. Some operations occur at the rising edge while others occur at
the falling edge. The TCKpin is powered by the VCCIO supply. If the JTAG interface is not
required on the board, the JTAG circuitry is disabled by connecting this pin to GND.
Test clock input
You can download data to the device on the PCB through the USB-Blaster,
MasterBlaster, ByteBlaster II, ByteBlasterMV download cable, and Ethernet-Blaster
communications cable during JTAG configuration. Configuring devices using a cable
is similar to programming devices in-system. Figure 9–24 and Figure 9–25 show the
JTAG configuration of a single Cyclone III device family.
For device VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–24. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and
3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from
V
CCA, and you must pull TCKto ground.
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Configuration Features
For device VCCIO of 1.2, 1.5, and 1.8 V, refer to Figure 9–25. You can power up the VCC
of the download cabled with the supply from VCCIO
.
Figure 9–24. JTAG Configuration of a Single Device Using a Download Cable (2.5, 3.0, and 3.3-V
VCCIO Powering the JTAG Pins)
V
CCA
(1)
V
(2)
CCIO
V
CCA
V
(2)
10 kΩ
CCIO
(1)
Cyclone III Device Family
nCE (3)
10 kΩ
TCK
TDO
GND
N.C. (4) nCEO
TMS
TDI
Download Cable 10-Pin Male
Header (Top View)
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
(5)
(5)
Pin 1
V
(6)
CCA
(5)
(5)
DCLK
GND
(7)
V
IO
1 kΩ
GND
GND
Notes to Figure 9–24:
(1) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
(2) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(3) The nCE pin must be connected to GND or driven low for successful JTAG configuration.
(4) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(5) Connect the nCONFIGand MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the nCONFIGpin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLKand
DATA[0]either high or low, whichever is convenient on your board.
(6) Power up the VCC of the ByteBlaster II, USB-Blaster, ByteBlasterMV, or Ethernet Blaster cable with a 2.5- V supply
from VCCA. Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the
MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power
supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User
Guide.
(7) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the device's VCCA
For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In USB-Blaster,
ByteBlaster II, ByteBlasterMV, and Ethernet Blaster, this pin is a no connect.
.
Cyclone III Device Handbook
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August 2012 Altera Corporation
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
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Configuration Features
Figure 9–25. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V VCCIO
Powering the JTAG Pins)
V
CCIO
(1)
V
(2)
CCIO
V
CCIO
10 kΩ
V
(2)
CCIO
(1)
Cyclone III Device Family
10 kΩ
nCE (3)
TCK
TDO
GND
N.C. (4)
nCEO
TMS
TDI
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
Download Cable
10-Pin Male Header (Top View)
(5)
(5)
(5)
(5)
Pin 1
V
(6)
CCIO
DCLK
GND
(7)
V
IO
1 kΩ
GND
GND
Notes to Figure 9–25:
(1) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
(2) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(3) The nCEmust be connected to GND or driven low for successful JTAG configuration.
(4) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(5) Connect the nCONFIGand MSEL[3..0]pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the nCONFIGpin to logic-high and the MSEL[3..0]pins to ground. In addition, pull DCLKand
DATA[0]either high or low, whichever is convenient on your board.
(6) Power up the VCC of the ByteBlaster II, USB-Blaster, or Ethernet Blaster cable with supply from VCCIO. The
ByteBlaster II, USB-Blaster, and Ethernet Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the ByteBlaster II Download Cable User Guide, USB-Blaster Download Cable User Guide
and Ethernet Blaster Communications Cable User Guide.
(7) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCEwhen it is used for AS programming;
otherwise it is a no connect.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDIpin to the TDOpin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDOpin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONEthrough the JTAG
port. When the Quartus II software generates a .jam for a multi-device chain, it
contains instructions to have all devices in the chain initialize at the same time. If
CONF_DONEis not high, the Quartus II software indicates that configuration has failed.
If CONF_DONEis high, the software indicates that configuration was successful. After
the configuration bitstream is serially sent using the JTAG TDIport, the TCKport
clocks an additional clock cycle to perform device initialization.
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Configuration Features
Cyclone III device family has dedicated JTAG pins that function as JTAG pins. You
can perform JTAG testing on Cyclone III device family before, during, and after
configuration. Cyclone III device family supports the BYPASS, IDCODE, and SAMPLE
instructions during configuration without interrupting configuration. All other JTAG
instructions can only be issued by first interrupting configuration and
reprogramming I/O pins using the ACTIVE_DISENGAGEand CONFIG_IOinstructions.
The CONFIG_IOinstruction allows I/O buffers to be configured using the JTAG port
and when issued after the ACTIVE_DISENGAGEinstruction interrupts configuration.
This instruction allows you to perform board-level testing prior to configuring the
Cyclone III device family or waiting for a configuration device to complete
configuration. Prior to issuing the CONFIG_IOinstruction, you must issue the
ACTIVE_DISENGAGEinstruction. This is because in Cyclone III device family, the
CONFIG_IOinstruction does not hold nSTATUSlow until reconfiguration, so you must
disengage the active configuration mode controller when active configuration is
interrupted. The ACTIVE_DISENGAGEinstruction places the active configuration mode
controllers in an idle state prior to JTAG programming. Additionally, the
ACTIVE_ENGAGEinstruction allows you to re-engage a disengaged active configuration
mode controller.
1
You must follow a specific flow when executing the CONFIG_IO, ACTIVE_DISENGAGE,
and ACTIVE_ENGAGEJTAG instructions in Cyclone III device family. For more
information about the instruction flow, refer to “JTAG Instructions” on page 9–60.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Cyclone III device family do not affect JTAG boundary-scan or programming
operations. Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration, consider the dedicated configuration
pins. Table 9–16 lists how these pins must be connected during JTAG configuration.
Table 9–16. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
On all Cyclone III device family in the chain, nCEmust be driven low by connecting it to ground, pulling it
low using a resistor or driving it by some control circuitry. For devices that are also in multi-device AS, AP,
PS, or FPP configuration chains, the nCEpins must be connected to GND during JTAG configuration or
JTAG configured in the same order as the configuration chain.
nCE
On all Cyclone III device family in the chain, nCEOis left floating or connected to the nCEof the next
device.
nCEO
These pins must not be left floating. These pins support whichever non-JTAG configuration that is used in
production. If you only use JTAG configuration, tie these pins to GND.
MSEL[3..0]
nCONFIG
nSTATUS
Driven high by connecting to the VCCIO supply of the bank in which the pin resides and pulling up using a
resistor or driven high by some control circuitry.
Pull to the VCCIO supply of the bank in which the pin resides using a 10-k resistor. When configuring
multiple devices in the same JTAG chain, each nSTATUSpin must be pulled up to the VCCIO individually.
Pull to the VCCIO supply of the bank in which the pin resides using a 10-k resistor. When configuring
multiple devices in the same JTAG chain, each CONF_DONEpin must be pulled up to the VCCIO supply of
the bank in which the pin resides individually. CONF_DONEgoing high at the end of JTAG configuration
indicates successful configuration.
CONF_DONE
DCLK
Must not be left floating. Drive low or high, whichever is more convenient on your board.
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–53
Configuration Features
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMSpins with an on-board
buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system using JTAG BST circuitry. Figure 9–26 and Figure 9–27
show a multi-device JTAG configuration.
For the device VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–26. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and
3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from
VCCA
For device VCCIO of 1.2, 1.5, and 1.8 V, refer to Figure 9–27. You can power up the VCC
of the download cable with the supply from VCCIO
.
.
Figure 9–26. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V VCCIO Powering the
JTAG Pins)
Download Cable
10-Pin Male Header
(1)
(1)
(1)
(1)
V
CCIO
V
CCIO
(1)
(1)
V
CCIO
V
CCIO
V
CCA
V
CCIO
VCCIO
Cyclone III Device
Family
Cyclone III Device
Family
Cyclone III Device
Family
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
(6)
10 kΩ
Pin 1
VCCA (5)
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
V
CCA
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(6)
(2)
(2)
(2)
CONF_DONE
CONF_DONE
CONF_DONE
(2)
(2)
(2)
VIO
(3)
nCE (4)
nCE (4)
nCE (4)
TDI
TMS
TDI
TMS
TDO
TDO
TDI
TMS
TDO
TCK
TCK
TCK
1 kΩ
Notes to Figure 9–26:
(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIGand MSEL[3..0]pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
nCONFIGpin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLKand DATA[0]either high or low, whichever is convenient
on your board.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the device. For this value, refer to the
MasterBlaster Serial/USB Communications Cable User Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and
ByteBlaster II cables, this pin is connected to nCEwhen it is used for AS programming, otherwise it is a no connect.
(4) The nCEpin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the VCC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V supply from VCCA. Third-party programmers must switch
to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V
circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications User Guide.
(6) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your setup.
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Configuration Features
Figure 9–27. JTAG Configuration of Multiple Devices Using a Download Cable (1.2, 1.5, and 1.8-V VCCIO Powering the
JTAG Pins)
Download Cable
10-Pin Male Header
(1)
(1)
(1)
(1)
V
CCIO
V
CCIO
(1)
(1)
V
CCIO
V
CCIO
V
CCIO (1)
V
CCIO
V
CCIO
Cyclone III
Device Family
Cyclone III
Device Family
Cyclone III
Device Family
10 kΩ
10 kΩ
nST
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
10 kΩ
10 kΩ
10 kΩ
10 kΩ
(6)
Pin 1
VCCIO (5)
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
A
TUS
V
CCIO (1)
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(6)
CONF_DONE
CONF_DONE
CONF_DONE
(2)
(2)
(2)
VIO
(3)
nCE (4)
nCE (4)
nCE (4)
TDI
TMS
TDI
TMS
TDO
TDO
TDI
TMS
TDO
TCK
TCK
TCK
1 kΩ
Notes to Figure 9–27:
(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIGand MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
nCONFIGpin to logic high and the MSEL[3..0]pins to ground. In addition, pull DCLKand DATA[0] either high or low, whichever is convenient
on your board.
(3) In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCEwhen it is used for AS programming, otherwise it is a no connect.
(4) The nCEpin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the VCC of the ByteBlaster II or USB-Blaster cable with supply from VCCIO. The ByteBlaster II and USB-Blaster cables do not support a
target supply voltage of 1.2 V. For the target supply voltage value, refer to the ByteBlaster II Download Cable User Guide and the USB-Blaster
Download Cable User Guide.
(6) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your setup.
1
All I/O inputs must maintain a maximum AC voltage of 4.1 V. If a non-Cyclone III
device family is cascaded in the JTAG-chain, TDOof the non-Cyclone III device family
driving into TDIof the Cyclone III device family must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
The nCEpin must be connected to GND or driven low during JTAG configuration. In
multi-device AS, AP, PS, and FPP configuration chains, the nCEpin of the first device
is connected to GND while its nCEOpin is connected to the nCEpin of the next device
in the chain. The inputs of the nCEpin of the last device come from the previous device
while its nCEOpin is left floating. In addition, the CONF_DONEand nSTATUSsignals are
shared in multi-device AS, AP, PS, and FPP configuration chains to ensure that the
devices enter user mode at the same time after configuration is complete. When the
CONF_DONEand nSTATUSsignals are shared among all the devices, every device must
be configured when you perform JTAG configuration.
If you only use JTAG configuration, Altera recommends that you connect the circuitry
as shown in Figure 9–26 or Figure 9–27, in which each of the CONF_DONEand nSTATUS
signals are isolated so that each device can enter user mode individually.
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9–55
Configuration Features
After the first device completes configuration in a multi-device configuration chain,
its nCEOpin drives low to activate the nCEpin of the second device, which prompts the
second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, ensure that the nCEpins are connected to GND during JTAG configuration or
that the devices are JTAG configured in the same order as the configuration chain. As
long as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEOpin of the previous device drives the nCEpin of the next
device low when it has successfully been JTAG configured. You can place other Altera
devices that have JTAG support in the same JTAG chain for device programming and
configuration.
1
JTAG configuration allows an unlimited number of Cyclone III device family to be
cascaded in a JTAG chain.
f
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in
volume 2 of the Configuration Handbook.
Figure 9–28 shows JTAG configuration of a Cyclone III device family with a
microprocessor.
Figure 9–28. JTAG Configuration of a Single Device Using a Microprocessor
Cyclone III Device Family
Memory
(3)
nCE
ADDR
DATA
nCEO
N.C.
(2)
MSEL[3..0]
V
(1)
(2)
(2)
(2)
CCIO
nCONFIG
DATA[0]
DCLK
V
(1)
CCIO
10 kΩ
TDI (4)
10 kΩ
TCK (4)
TDO
nSTATUS
Microprocessor
TMS (4)
CONF_DONE
Notes to Figure 9–28:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain.
(2) Connect the nCONFIGand MSEL[3..0]pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the nCONFIGpin to logic high and the MSEL[3..0]pins to ground. In addition, pull DCLKand
DATA[0] either high or low, whichever is convenient on your board.
(3) The nCEpin must be connected to GND or driven low for successful JTAG configuration.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. Signals driving into TDI, TMS, and TCKmust fit the
maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
Configuring Cyclone III Device Family with Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard. The Jam Player
provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP state machine.
f
For more information about JTAG and Jam STAPL in embedded environments, refer
to AN 425: Using Command-Line Jam STAPL Solution for Device Programming. To
download the jam player, visit the Altera website (www.altera.com).
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Configuration Features
Configuring Cyclone III Device Family with the JRunner Software Driver
The JRunner software driver allows you to configure Cyclone III device family
through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The supported
programming input file is in .rbf format. The JRunner software driver also requires a
Chain Description File (.cdf) generated by the Quartus II software. The JRunner
software driver is targeted for embedded JTAG configuration. The source code is
developed for the Windows NT operating system (OS). You can customize the code to
make it run on your embedded platform.
1
The .rbf used by the JRunner software driver cannot be a compressed .rbf because the
JRunner software driver uses JTAG-based configuration. During JTAG-based
configuration, the real-time decompression feature is not available.
f
For more information about the JRunner software driver, refer to AN 414: JRunner
Software Driver: An Embedded Solution for PLD JTAG Configuration and the source files
on the Altera website at (www.altera.com).
Combining JTAG and AS Configuration Schemes
You can combine the AS configuration scheme with the JTAG-based configuration
(Figure 9–29). This setup uses two 10-pin download cable headers on the board. One
download cable is used in JTAG mode to configure the Cyclone III device family
directly using the JTAG interface. The other download cable is used in AS mode to
program the serial configuration device in-system using the AS programming
interface. The MSEL[3..0]pins must be set to select AS configuration mode (Table 9–7
on page 9–11). If you try configuring the device using both schemes simultaneously,
the JTAG configuration takes precedence and the AS configuration terminates.
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Configuration Features
Figure 9–29. Combining JTAG and AS Configuration Schemes
V
V
V
CCIO(1) CCIO(1) CCIO(1)
10 kΩ 10 kΩ
10 kΩ
Cyclone III Device Family
V
CCA
nSTATUS
N.C.
nCEO
CONF_DONE
nCONFIG
(8)
nCE
V
CCA
3.3 V
3.3 V
3.3 V
3.3 V
(4)
10kΩ
Serial
MSEL [3..0]
Configuration
Device
(8)
GND
(7)
Download Cable
(JTAG Mode)
10-Pin Male Header
(top view)
DATA[0]
DCLK
TCK
TDO
TMS
TDI
DATA
DCLK
nCS
nCSO (5)
ASDO (5)
Pin 1
ASDI
VCCA (6)
Pin 1
V
(3)
IO
3.3 V (2)
1 kΩ
10 pf
GND
10 pf
10 pf
Download Cable
(AS Mode)
10-Pin Male Header
GND
10 pf
GND
GND
(7)
GND
Notes to Figure 9–29:
(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Power up the VCC of the ByteBlaster II, USB-Blaster, or Ethernet Blaster cable with the 3.3-V supply.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the
device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In ByteBlasterMV,
this pin is a no connect. In USB-Blaster and ByteBlaster II, this pin is connected to nCEwhen it is used for AS
programming, otherwise it is a no connect.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]for
AS configuration schemes, refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(5) These are dual-purpose I/O pins. This nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions
as the DATA[1]pin in other AP and FPP modes.
(6) Power up VCC of the ByteBlaster II, USB-Blaster, ByteBlasterMV, or Ethernet Blaster cable with a 2.5- V supply from
V
CCA. Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster
cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V
from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.
(7) You must place the diodes and capacitors as close as possible to the Cyclone III device family. For effective voltage
clamping, Altera recommends using the Schottky diode, which has a relatively lower forward diode voltage (VF) than
the switching and Zener diodes. For more information about the interface guidelines using Schottky diodes, refer to
AN 523: Cyclone III Configuration Interface Guidelines with EPCS Devices.
(8) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
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Configuration Features
Programming Serial Configuration Devices In-System Using the JTAG
Interface
Cyclone III device family in a single-device or in a multiple-device chain supports
in-system programming of a serial configuration device with the JTAG interface using
the SFL design. The intelligent host or download cable of the board can use the four
JTAG pins on the Cyclone III device family to program the serial configuration device
in system, even if the host or download cable cannot access the configuration pins
(DCLK, DATA, ASDI, and nCSpins).
The SFL design is a JTAG-based in-system programming solution for Altera serial
configuration devices. The SFL is a bridge design for the Cyclone III device family
that uses its JTAG interface to access the EPCS JTAG Indirect Configuration Device
Programming (.jic) file and then uses the AS interface to program the EPCS device.
Both the JTAG interface and AS interface are bridged together inside the SFL design.
In a multiple device chain, you must only configure the master device that controls
the serial configuration device. When using this feature, the slave devices in the
multiple device chain which are configured by the serial configuration device do not
need to be configured. To use this feature successfully, set the MSEL[3..0]pins of the
master device to select the AS configuration scheme (Table 9–7 on page 9–11). The
serial configuration device in-system programming through the Cyclone III device
family JTAG interface has three stages, which are described in the following sections:
■
■
■
“Loading the SFL Design” on page 9–58
“ISP of the Configuration Device” on page 9–59
“Reconfiguration” on page 9–60
Loading the SFL Design
The SFL design is a design inside the Cyclone III device family that bridges the JTAG
interface and the AS interface with glue logic.
The intelligent host uses the JTAG interface to configure the master device with a SFL
design. The SFL design allows the master device to control the access of four serial
configuration device pins, also known as the Active Serial Memory Interface (ASMI)
pins, through the JTAG interface. The ASMI pins are serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and active-low chip select (nCS) pins.
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Configuration Features
If you configure a master device with a SFL design, the master device enters user
mode even though the slave devices in the multiple device chain are not being
configured. The master device enters user mode with a SFL design even though the
CONF_DONEsignal is externally held low by the other slave devices in chain.
Figure 9–30 shows the JTAG configuration of a single Cyclone III device family with a
SFL design.
Figure 9–30. Programming Serial Configuration Devices In-System Using the JTAG Interface
V
CCA
(9)
V
(1)
CCIO
V
CCA
10 kΩ
V
(1)
CCIO
Cyclone III Device Family
(9)
10 kΩ
Serial Configuration
nCE (4)
TCK
TDO
V
(1)
Device
CCIO
GND
N.C. (5)
nCEO
10 kΩ
TMS
TDI
Download Cable 10-Pin Male
Header (Top View)
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
Serial
Flash
Loader
(2)
25 Ω (7)
Pin 1
V
(6)
CCA
DATA
DCLK
nCS
DCLK
nCSO (8)
ASDO (8)
ASDI
GND
(3)
V
IO
1 kΩ
GND
GND
Notes to Figure 9–30:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0]for
AS configuration schemes, refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the
device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In ByteBlasterMV,
this pin is a no connect. In USB-Blaster, ByteBlaster II, and Ethernet Blaster, this pin is connected to nCEwhen it is
used for AS programming, otherwise it is a no connect.
(4) The nCEpin must be connected to GND or driven low for successful JTAG configuration.
(5) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(6) Power up the VCC of the ByteBlaster II, USB-Blaster, ByteBlasterMV, or Ethernet Blaster cable with a 2.5-V supply from
V
CCA. Third-party programmers must switch to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster
cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V
from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide.
(7) Connect the series resistor at the near end of the serial configuration device.
(8) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions
as the DATA[1]pin in other AP and FPP modes.
(9) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
ISP of the Configuration Device
In the second stage, the SFL design in the master device allows you to write the
configuration data for the device chain into the serial configuration device with the
Cyclone III device family JTAG interface. The JTAG interface sends the programming
data for the serial configuration device to the Cyclone III device family first. The
Cyclone III device family then uses the ASMI pins to send the data to the serial
configuration device.
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Configuration Features
Reconfiguration
After the configuration data is successfully written into the serial configuration
device, the Cyclone III device family does not reconfigure by itself. The intelligent
host issues the PULSE_NCONFIGJTAG instruction to initialize the reconfiguration
process. During reconfiguration, the master device is reset and the SFL design no
longer exists in the Cyclone III device family and the serial configuration device
configures all the devices in the chain with your user design.
f
For more information about SFL, refer to AN 370: Using the Serial FlashLoader with
Quartus II Software.
JTAG Instructions
This section describes the instructions that are necessary for JTAG configuration for
the Cyclone III device family. Table 9–17 lists the supported JTAG instructions.
Table 9–17. JTAG Instructions
JTAG Instruction
CONFIG_IO
Cyclone III Device
Cyclone III LS Device
v
v
v
v
v
v
—
—
—
v
v
v
—
—
—
v
v
v
ACTIVE_DISENGAGE
ACTIVE_ENGAGE
EN_ACTIVE_CLK
DIS_ACTIVE_CLK
APFC_BOOT_ADDR
(1)
FACTORY
(2)
KEY_PROG_VOL
(2)
KEY_CLR_VREG
Notes to Table 9–17:
(1) In Cyclone III LS devices, the CONFIG_IO
,
ACTIVE_DISENGAGE, PULSE_NCONFIG,and PROGRAMinstructions are
supported, provided that the FACTORYinstruction is executed. It is not necessary to execute the FACTORY
instruction prior to the JTAG configuration in Cyclone III devices because this instruction is used for Cyclone III LS
devices only.
(2) Use the KEY_PROG_VOL and KEY_CLR_VREGinstructions for the design security feature. For more information,
refer to “Design Security” on page 9–70.
f
For more information about the JTAG binary instruction code, refer to the IEEE 1149.1
(JTAG) Boundary-Scan Testing for Cyclone III Devices chapter.
For Cyclone III LS devices, the device can only allow mandatory JTAG 1149.1
instructions after POR. These instructions are BYPASS, SAMPLE/PRELOAD, EXTESTand
FACTORY. To enable the access of other JTAG instructions, issue the FACTORYinstruction.
The FACTORYinstruction puts the device in a state in which it is ready for in-house
testing and board-level testing and it must be executed before configuration starts.
When this instruction is executed, the CRAM bits content and volatile key are cleared
and the device is reset.
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Configuration Features
I/O Reconfiguration
Use the CONFIG_IOinstruction to reconfigure the I/O configuration shift register
(IOCSR) chain. This instruction allows you to perform board-level testing prior to
configuring the Cyclone III device family or waiting for a configuration device to
complete configuration. After the configuration is interrupted and JTAG testing is
complete, the part must be reconfigured using the PULSE_NCONFIG JTAG instruction
or by pulsing the nCONFIGpin low.
You can issue the CONFIG_IOinstruction any time during user mode. The CONFIG_IO
instruction cannot be issued when nCONFIGpin is asserted low (during power up) or
immediately after issuing a JTAG instruction that triggers reconfiguration. For more
information about the wait-time for issuing the CONFIG_IOinstruction, refer to
Table 9–18.
When using CONFIG_IOinstruction, you must meet the following timing restrictions:
■
■
CONFIG_IOinstruction cannot be issued during the nCONFIGpin low
Observe 230 s minimum wait time after any of the following conditions are met:
■
■
■
nCONFIGpin goes high
Issuing the PULSE_NCONFIGinstruction
Issuing the ACTIVE_ENGAGEinstruction, before issuing the CONFIG_IOinstruction
■
Wait 230 s after power up with nCONFIGpin high before issuing the CONFIG_IO
instruction (or wait for the nSTATUSpin to go high)
Table 9–18. Wait Time for Issuing the CONFIG_IO Instruction
Wait Time
Time
Wait time after the nCONFIG pin is released
230 s
Wait time after PULSE_NCONFIGor ACTIVE_ENGAGEis
issued
230 s
Use the ACTIVE_DISENGAGEinstruction with CONFIG_IOinstruction to interrupt
configuration. Table 9–19 lists the sequence of instructions to use for various
CONFIG_IOusage scenarios.
(1)
Table 9–19. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows
(Part 1 of 2)
Configuration Scheme and Current State of the Cyclone III Device Family
Prior to User Mode
(Interrupting
User Mode
Power Up
JTAG Instruction
Configuration)
AP
AP
AP
PS FPP
AS
PS
FPP
AS
PS FPP AS
(4)
(4)
(4)
FACTORY
NA
O
NA
O
NA
O
NA
O
NA
O
NA
O
NA
O
NA
O
R
R
R
NA
—
ACTIVE_DISENGAGE
—
—
—
CONFIG_IO
R
R
R
R
R
R
R
R
NA NA NA NA
JTAG Boundary Scan Instructions (no
O
O
O
O
O
O
O
O
—
—
—
—
JTAG_PROGRAM
)
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Configuration Features
(1)
Table 9–19. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows
(Part 2 of 2)
Configuration Scheme and Current State of the Cyclone III Device Family
Prior to User Mode
(Interrupting
User Mode
Power Up
JTAG Instruction
Configuration)
AP
AP
AP
PS FPP
AS
PS
FPP
AS
PS FPP AS
(4)
(4)
(4)
(2)
(2)
(2)
(2)
ACTIVE_ENGAGE
R
A
A
R
A
A
R
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
(3)
(3)
(3)
PULSE_NCONFIG
Pulse nCONFIGpin
JTAG TAP Reset
A
R
A
R
A
R
A
R
O
O
R
O
O
R
R
R
Notes to Table 9–19:
(1) “R” indicates that the instruction is to be executed before the next instruction, “O” indicates the optional instruction, “A” indicates that the
instruction must be executed, and “NA” indicates that the instruction is not allowed in this mode.
(2) Required if you use ACTIVE_DISENGAGE
.
(3) Neither of the instruction is required if you use ACTIVE_ENGAGE
.
(4) AP configuration is for Cyclone III devices only.
The CONFIG_IOinstruction does not hold the nSTATUSpin low until reconfiguration.
You must disengage the active configuration controllers (AS and AP) by issuing the
ACTIVE_DISENGAGEand ACTIVE_ENGAGEinstructions when the active configuration is
interrupted. You must issue the ACTIVE_DISENGAGEinstruction alone or prior to the
CONFIG_IOinstruction if the JTAG_PROGRAMinstruction is to be issued later (Table 9–20).
This puts the active configuration controllers into the idle state. The active
configuration controller is re-engaged after user mode is reached using JTAG
programming (Table 9–20).
1
While executing the CONFIG_IOinstruction, all user I/Os are tri-stated.
If reconfiguration after interruption is performed using configuration modes (rather
than using JTAG_PROGRAM), it is not necessary to issue the ACTIVE_DISENGAGE
instruction prior to CONFIG_IO. You can start reconfiguration by either pulling the
nCONFIGpin low for at least 500 ns, or issuing the PULSE_NCONFIGinstruction. If the
ACTIVE_DISENGAGEinstruction was issued and the JTAG_PROGRAMinstruction fails to
enter user mode, you must issue the ACTIVE_ENGAGEinstruction to reactivate the active
configuration controller. Issuing the ACTIVE_ENGAGEinstruction also triggers the
reconfiguration in configuration modes; therefore, it is not necessary to pull the
nCONFIGpin low or issue the PULSE_NCONFIGinstruction.
ACTIVE_DISENGAGE
The ACTIVE_DISENGAGEinstruction places the active configuration controller (AS and
AP) into an idle state prior to JTAG programming. The active configuration controller
is the AS controller when the MSEL pins are set to AS configuration scheme and the
AP controller when the MSEL pins are set to the AP configuration scheme. The two
purposes of placing the active controllers in an idle state are:
■
To ensure that they are not trying to configure the device in their respective
configuration modes during JTAG programming
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Configuration Features
■
To allow the controllers to properly recognize a successful JTAG programming
that results in the device reaching user mode
The ACTIVE_DISENGAGEinstruction is required before JTAG programming regardless
of the current state of the Cyclone III device family if the MSEL pins are set to an
active configuration scheme (AS or AP). If the ACTIVE_DISENGAGEinstruction is issued
during a passive configuration scheme (PS or FPP), it has no effect on the Cyclone III
device family. Similarly, the CONFIG_IOinstruction is issued after an
ACTIVE_DISENGAGEinstruction, but is no longer required to properly halt
configuration. Table 9–20 lists the required, recommended, and optional instructions
for each configuration mode. The ordering of the required instructions is a hard
requirement and must be met to ensure functionality.
(1)
Table 9–20. JTAG Programming Instruction Flows
Configuration Scheme and Current State of the Cyclone III Device
Prior to User Mode
(Interrupting
User Mode
Power Up
JTAG Instruction
Configuration)
AP
AP
AP
PS
FPP
AS
PS FPP AS
PS FPP AS
(2)
(2)
(2)
FACTORY
NA
O
NA
O
NA
R
NA NA NA NA NA
R
O
R
O
R
R
NA
R
ACTIVE_DISENGAGE
CONFIG_IO
R
O
O
R
O
O
O
R
O
O
O
R
O
O
O
R
R
O
O
R
Rc
O
Rc
O
O
NA NA NA NA
Other JTAG instructions
JTAG_PROGRAM
O
O
R
O
R
O
R
O
R
R
R
R
CHECK_STATUS
Rc
R
Rc
R
Rc
R
Rc Rc Rc Rc Rc Rc
Rc
R
Rc Rc
JTAG_STARTUP
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
JTAG TAP Reset/ other instruction
Notes to Table 9–20:
R
R
R
R
(1) “R” indicates that the instruction is required to be executed before the next instruction, “O” indicates the optional instruction, “Rc” indicates
the recommended instruction, and “NA” indicates that the instruction is not allowed to be executed in this mode.
(2) AP configuration is for Cyclone III devices only.
In AS or AP configuration schemes, the ACTIVE_DISENGAGEinstruction puts the active
configuration controllers into idle state. If a successful JTAG programming is
executed, the active controllers are automatically re-engaged after user mode is
reached using JTAG programming. This causes the active controllers to transition to
their respective user mode states.
If JTAG programming fails to get the Cyclone III device family to enter user mode and
re-engage active programming, there are available methods to achieve this for the AS
or AP configuration schemes:
■
When in the AS configuration scheme, you can re-engage the AS controller by
moving the JTAG TAP controller to the reset state or by issuing the ACTIVE_ENGAGE
instruction.
■
When in the AP configuration scheme, the only way to re-engage the AP controller
is to issue the ACTIVE_ENGAGEinstruction. In this case, asserting the nCONFIGpin
does not re-engage either active controller.
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Configuration Features
ACTIVE_ENGAGE
The ACTIVE_ENGAGEinstruction allows you to re-engage a disengaged active controller.
You can issue this instruction any time during configuration or user mode to re-
engage an already disengaged active controller as well as trigger reconfiguration of
the Cyclone III device family in the active configuration scheme specified by the
MSEL pin settings.
The ACTIVE_ENGAGEinstruction functions as the PULSE_NCONFIGinstruction when the
device is in passive configuration schemes (PS or FPP). The nCONFIGpin is disabled
when the ACTIVE_ENGAGEinstruction is issued.
1
Altera does not recommend using the ACTIVE_ENGAGEinstruction but it is provided as
a fail-safe instruction for re-engaging the active configuration (AS or AP) controllers.
Changing the Start Boot Address of the AP Flash
In the AP configuration scheme, for Cyclone III devices only, you can change the
default configuration boot address of the parallel flash memory to any desired
address using the APFC_BOOT_ADDR JTAG instruction.
APFC_BOOT_ADDR
The APFC_BOOT_ADDRinstruction is for Cyclone III devices only and allows you to
define a start boot address for the parallel flash memory in the AP configuration
scheme.
This instruction shifts in a start boot address for the AP flash. When this instruction
becomes the active instruction, the TDIand TDOpins are connected through a 22-bit
active boot address shift register. The shifted-in boot address bits get loaded into the
22-bit AP boot address update register, which feeds into the AP controller. The content
of the AP boot address update register can be captured and shifted-out of the active
boot address shift register from TDO
.
The boot address in the boot address shift register and update register are shifted to
the right (in the LSB direction) by two bits versus the intended boot address. The
reason for this is that the two LSB of the address are not accessible. When this boot
address is fed into the AP controller, two 0s are attached in the end as LSB, thereby
pushing the shifted-in boot address to the left by two bits, which become the actual
AP boot address the AP controller gets.
If you have enabled the remote update feature, the APFC_BOOT_ADDRinstruction sets
the boot address for the factory configuration only.
1
The APFC_BOOT_ADDRinstruction is retained after reconfiguration while the system
board is still powered on. However, you must reprogram the instruction whenever
you restart the system board.
Device Configuration Pins
Table 9–21 through Table 9–23 describe the connections and functionality of all the
configuration-related pins on Cyclone III device family.
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Configuration Features
Table 9–21 lists the Cyclone III device family pin configuration.
Table 9–21. Cyclone III Device Family Configuration Pin Summary
Bank
Description
FLASH_nCE, nCSO
CRC_ERROR
Input/Output
Output
Output
Input
Dedicated
Powered By
Configuration Mode
(2)
1
6
—
—
VCCIO
AS, AP
(1)
VCCIO/Pull-up
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
Pull-up
Pull-up
VCCIO
VCCIO
VCCIO
Pull-up
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCINT
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
Optional, all modes
PS, FPP, AS
1
1
8
DATA[0]
Yes
(2)
Bidirectional
Input
AP
FPP
AS
DATA[1], ASDO
DATA[7..2]
Output
Bidirectional
Input
—
(2)
AP
FPP
(2)
Bidirectional
Bidirectional
Output
Bidirectional
Input
—
AP
(2)
8
6
1
1
DATA[15..8]
INIT_DONE
nSTATUS
nCE
AP
—
Optional, all modes
All modes
Yes
Yes
All modes
Input
PS, FPP
1
DCLK
Yes
(2)
Output
Bidirectional
Input
AS, AP
6
1
1
1
1
6
6
6
1
7
8
6
1
6
6
6
5
5
CONF_DONE
TDI
Yes
Yes
Yes
Yes
Yes
—
All modes
JTAG
TMS
Input
JTAG
TCK
Input
JTAG
nCONFIG
CLKUSR
nCEO
Input
All modes
Optional
Input
Output
Input
—
Optional, all modes
All modes
JTAG
MSEL[3..0]
TDO
Yes
Yes
—
Output
Output
Output
Output
Output
Output
Output
Output
Input
(2)
PADD[14..0]
PADD[19..15]
PADD[23..20]
nRESET
nAVD
AP
(2)
—
AP
(2)
—
AP
(2)
—
AP
(2)
—
AP
(2)
nOE
—
AP
(2)
nWE
—
AP
(2)
DEV_OE
DEV_CLRn
—
Optional, AP
(2)
Input
—
Optional, AP
Notes to Table 9–21:
(1) In Cyclone III devices, the CRC_ERRORpin is a dedicated output by default. Optionally, you can enable the CRC_ERRORpin as an open-drain output
in the CRC Error Detection tab from the Device and Pin Options dialog box.
(2) AP configuration is for Cyclone III devices only.
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Configuration Features
Table 9–22 lists the dedicated configuration pins that must be connected properly on
your board for successful configuration. Some of these pins may not be required for
your configuration scheme.
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 1 of 4)
User
Mode
Configuration
Scheme
Pin Name
Pin Type
Description
4-bit configuration input that sets the Cyclone III device
family configuration scheme. These pins must be hardwired
to VCCA or GND. The MSEL[3..0]pins have internal 9-k
pull-down resistors that are always active.
MSEL [3..0]
N/A
N/A
All
All
Input
Some of the smaller devices or package options of
Cyclone III devices do not have the MSEL[3]pin; therefore,
the AP configuration scheme is not supported.
Configuration control input. Pulling this pin low with external
circuitry during user mode causes the Cyclone III device
family to lose its configuration data, enter a reset state, and
tri-state all I/O pins. Returning this pin to a logic-high level
starts a reconfiguration.
nCONFIG
Input
The Cyclone III device family drives nSTATUSlow
immediately after power-up and releases it after the POR
time.
■ Status output. If an error occurs during configuration,
nSTATUSis pulled low by the target device.
■ Status input. If an external source (for example, another
Cyclone III device family) drives the nSTATUSpin low
during configuration or initialization, the target device
enters an error state.
Bidirectional
open-drain
nSTATUS
N/A
All
Driving nSTATUSlow after configuration and initialization
does not affect the configured device. If you use a
configuration device, driving nSTATUSlow causes the
configuration device to attempt to configure the device, but
because the device ignores transitions on nSTATUSin user
mode, the device does not reconfigure. To start a
reconfiguration, nCONFIGmust be pulled low.
■ Status output. The target Cyclone III device family drives
the CONF_DONEpin low before and during configuration.
After all configuration data is received without error and
the initialization cycle starts, the target device releases
CONF_DONE.
Bidirectional ■ Status input. After all data is received and CONF_DONE
CONF_DONE
N/A
All
open-drain
goes high, the target device initializes and enters user
mode. The CONF_DONEpin must have an external 10-k
pull-up resistor in order for the device to initialize.
Driving CONF_DONElow after configuration and initialization
does not affect the configured device. Do not connect bus
holds or ADC to the CONF_DONEpin.
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Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 2 of 4)
User
Mode
Configuration
Scheme
Pin Name
Pin Type
Description
Active-low chip enable. The nCEpin activates the Cyclone III
device family with a low signal to allow configuration. The
nCEpin must be held low during configuration, initialization,
and user-mode. In a single-device configuration, it must be
tied low. In a multi-device configuration, nCEof the first
device is tied low while its nCEOpin is connected to the nCE
pin of the next device in the chain. The nCEpin must also be
held low for successful JTAG programming of the device.
nCE
N/A
All
Input
Output that drives low when configuration is complete. In a
single-device configuration, you can leave this pin floating or
use it as a user I/O pin after configuration. In a multi-device
configuration, this pin feeds the nCEpin of the next device.
The nCEOof the last device in the chain is left floating or is
used as a user I/O pin after configuration.
N/A if
option is
on. I/O if
option is
off.
Output open
drain
nCEO
All
If you use the nCEOpin to feed the nCEpin of the next device,
use an external 10-k pull-up resistor to pull the nCEOpin
high to the VCCIO voltage of its I/O bank to help the internal
weak pull-up resistor.
If you use the nCEOpin as a user I/O pin after configuration,
set the state of the pin on the Dual-Purpose Pin settings.
Output control signal from the Cyclone III device family to the
serial configuration device in AS mode that enables the
configuration device. This pin functions as the nCSOpin in AS
mode and the FLASH_NCEpin in AP mode.
FLASH_nCE
,
(3)
I/O
AS, AP
Output
(1), (2)
Output control signal from the Cyclone III device to the
parallel flash in AP mode that enables the flash. Connects to
nCSO
(3)
the CE#pin on the Micron P30 or P33 flash.
This pin has an internal pull-up resistor that is always active.
In PS and FPP configuration, DCLKis the clock input used to
clock data from an external source into the target Cyclone III
device family. Data is latched into the device on the rising
edge of DCLK.
In AS mode, DCLKis an output from the Cyclone III device
family that provides timing for the configuration interface, it
has an internal pull-up resistor (typically 25 k) that is
always active.
Input (PS,
PS, FPP, AS,
In AP mode, DCLKis an output from the Cyclone III device
(1), (2)
DCLK
N/A
FPP).Output
(3)
(3)
AP
that provides timing for the configuration interface.
(AS, AP (3)
)
In active configuration schemes (AS or AP), this pin will be
driven into an inactive state after configuration completes.
Alternatively, in active schemes, you can use this pin as a
user I/O during user mode. In passive schemes (PS or FPP)
that use a control host, DCLKmust be driven either high or
low, whichever is more convenient. In passive schemes, you
cannot use DCLKas a user I/O in user mode. Toggling this pin
after configuration does not affect the configured device
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Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 3 of 4)
User
Mode
Configuration
Scheme
Pin Name
Pin Type
Description
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target Cyclone III
device family on the DATA[0]pin.
In AS mode, DATA[0]has an internal pull-up resistor that is
always active. After AS configuration, DATA[0]is a dedicated
input pin with optional user control.
Input (PS,
FPP, AS).
Bidirectional
(AP) (3)
DATA[0]
(1), (2)
PS, FPP, AS,
I/O
(3)
AP
After PS or FPP configuration, DATA[0]is available as a user
I/O pin and the state of this pin depends on the Dual-Purpose
Pin settings.
After AP configuration, DATA[0]is a dedicated bidirectional
(3)
pin with optional user control.
Data input in non-AS mode. Control signal from the
Cyclone III device family to the serial configuration device in
AS mode used to read out configuration data. The DATA[1]
pin functions as the ASDOpin in AS mode.
In AS mode, DATA[1]has an internal pull-up resistor that is
always active. After AS configuration, DATA[1]is a dedicated
output pin with optional user control.
Input (FPP),
Output (AS).
Bidirectional
In PS configuration scheme, DATA[1]functions as user I/O
pin during configuration, which means it is tri-stated.
DATA[1]
ASDO
,
(3)
I/O
FPP, AS, AP
(1), (2)
(3)
After FPP configuration, DATA[1]is available as a user I/O
pin and the state of this pin depends on the Dual-Purpose
Pin settings.
(AP)
In AP configuration scheme, which is for Cyclone III devices
only, the byte-wide or word-wide configuration data is
presented to the target Cyclone III device on DATA[7..0]or
DATA[15..0], respectively. After AP configuration, DATA[1]
(3)
is a dedicated bidirectional pin with optional user control.
Data inputs.
In AS or PS configuration schemes, they function as user I/O
pins during configuration, which means they are tri-stated.
After FPP configuration, DATA[7..2]are available as user
I/O pins and the state of these pin depends on the
Dual-Purpose Pin settings.
Inputs
(FPP).
(3)
DATA[7..2]
I/O
FPP, AP
Bidirectional
The byte-wide or word-wide configuration data is presented
to the target Cyclone III device on DATA[7..0]or
(3)
(AP)
DATA[15..0], respectively, in the AP configuration scheme
(for Cyclone III devices only). After AP configuration,
DATA[7..2]are dedicated bidirectional pins with optional
(3)
user control.
Data inputs. Word-wide configuration data is presented to the
target Cyclone III device on DATA[15..0]
.
In PS, FPP, or AS configuration schemes, they function as
Bidirectional user I/O pins during configuration, which means they are
tri-stated.
(3)
DATA[15..8]
I/O
AP
After AP configuration, DATA[15:8]are dedicated
bidirectional pins with optional user control.
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Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 4 of 4)
User
Mode
Configuration
Scheme
Pin Name
Pin Type
Description
24-bit address bus from the Cyclone III device to the parallel
flash in AP mode. Connects to the A[24:1]bus on the
Micron P30 or P33 flash.
(3)
PADD[23..0]
I/O
I/O
AP
Output
Active-low reset output. Driving the nRESETpin low resets
the parallel flash. Connects to the RST#pin on the Micron
P30 or P33 flash.
(3)
nRESET
nAVD
AP
Output
Output
Active-low address valid output. Driving the nAVDpin low
during a read or write operation indicates to the parallel flash
that valid address is present on the PADD[23..0]address
bus. Connects to the ADV#pin on the Micron P30 or P33
flash.
(3)
I/O
AP
Active-low output enable to the parallel flash. Driving the nOE
pin low during a read operation enables the parallel flash
outputs (DATA[15..0]). Connects to the OE#pin on the
Micron P30 or P33 flash.
(3)
nOE
I/O
I/O
AP
Output
Output
Active-low write enable to the parallel flash. Driving the nWE
pin low during a write operation indicates to the parallel flash
that data on the DATA[15..0]bus is valid. Connects to the
WE#pin on the Micron P30 or P33 flash.
(3)
nWE
AP
Note to Table 9–22:
(1) If you are accessing the EPCS device with the ALTASMI_PARALLEL megafunction or your own user logic in user mode, in the Device and Pin
Options window of the Quartus II software, in the Dual-Purpose Pins category, select Use as regular I/O for this pin.
(2) To tri-state the AS configuration pins in user mode, turn on the Enable input tri-state on active configuration pins in user mode option from the
Device and Pin Options dialog box in the Configuration tab. This option tri-states the DCLK, DATA0, nCSO, and ASDOpins.
(3) AP configuration scheme is for Cyclone III devices only.
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Design Security
Table 9–23 lists the optional configuration pins. If these optional configuration pins
are not enabled in the Quartus II software, they are available as general-purpose user
I/O pins. Therefore, during configuration, these pins function as user I/O pins and
are tri-stated with weak pull-up resistors.
Table 9–23. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
Optional user-supplied clock input synchronizes the initialization
of one or more devices. This pin is enabled by turning on the
Enable user-supplied start-up clock (CLKUSR) option in the
Quartus II software.
N/A if option is on.
I/O if option is off.
CLKUSR
Input
Status pin used to indicate when the device has initialized and is
in user-mode. When nCONFIGis low and during the beginning
of configuration, the INIT_DONEpin is tri-stated and pulled high
due to an external 10-k pull-up resistor. After the option bit to
enable INIT_DONEis programmed into the device (during the
first frame of configuration data), the INIT_DONEpin goes low.
When initialization is complete, the INIT_DONEpin is released
and pulled high and the device enters user mode. Thus, the
monitoring circuitry must be able to detect a low-to-high
transition. This pin is enabled by turning on the Enable
INIT_DONE output option in the Quartus II software.
N/A if option is on.
I/O if option is off.
Output
open-drain
INIT_DONE
The functionality of this pin changes if the Enable OCT_DONE
option is enabled in the Quartus II software. This option
controls whether the INIT_DONEsignal is gated by the
OCT_DONEsignal, which indicates the Power-Up OCT calibration
is complete. If this option is turned off, the INIT_DONEsignal is
not gated by the OCT_DONEsignal
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are tri-stated;
when this pin is driven high, all I/O pins behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
N/A if option is on.
I/O if option is off.
DEV_OE
Input
Input
Optional pin that allows you to override all clears on all device
registers. When this pin is driven low, all registers are cleared;
when this pin is driven high, all registers behave as
programmed. This pin is enabled by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
N/A if option is on.
I/O if option is off.
DEV_CLRn
Design Security
The design security feature is for Cyclone III LS devices only. The design security
feature is not supported in Cyclone III devices.
Cyclone III LS Design Security Protection
Cyclone III LS device designs are protected from copying, reverse engineering, and
tampering using configuration bitstream encryption and anti-tamper features.
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Design Security
Security Against Copying
The volatile key is securely stored in the Cyclone III LS device and cannot be read out
through any interfaces. The information of your design cannot be copied because the
configuration file read-back feature is not supported in Cyclone III LS devices.
Security Against Reverse Engineering
Reverse engineering from an encrypted configuration file is very difficult and time
consuming because Cyclone III LS configuration file formats are proprietary and the
file contains million of bits which require specific decryption. Reverse engineering the
Cyclone III LS device is just as difficult because the device is manufactured on the
advanced 60-nm process technology.
Security Against Tampering
Cyclone III LS devices support the following anti-tamper features:
■
■
■
Ability to limit JTAG instruction set and provides protection against configuration
data readback over the JTAG port
Ability to clear contents of FPGA logic, configuration memory, user memory, and
volatile key
Error detection (ED) cycle indicator to core Cyclone III LS devices provide a pass
or fail indicator at every ED cycle and visibility over intentional or unintentional
change of CRAM bits.
f
f
For more information about anti-tamper protection for Cyclone III LS devices, refer to
AN 593: Anti-Tamper Protection for Cyclone III LS Devices.
For more information about the implementation of secure configuration flow in
Quartus II, refer to AN 589: Using Design Security Feature in Cyclone III LS Devices.
AES Decryption Block
The main purpose of the AES decryption block is to decrypt the configuration
bitstream prior to entering configuration. Prior to receiving encrypted data, you must
enter and store the 256-bit volatile key in the device with battery backup. The key is
scrambled prior to storing it in the key storage to make it more difficult for anyone to
retrieve the stored key using de-capsulation of the device.
Key Storage
Cyclone III LS devices support volatile key programming. Table 9–24 lists the volatile
key features.
Table 9–24. Security Key Features (Part 1 of 2)
Volatile Key Features
Key programmability
Description
Reprogrammable and erasable
Required
External battery
(1)
Key programming method
On-board
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Design Security
Table 9–24. Security Key Features (Part 2 of 2)
Volatile Key Features
Description
Secure against copying, reverse engineering, and
tampering
Design protection
Note to Table 9–24:
(1) Key programming is carried out using the JTAG interface.
AES volatile key zeroization is supported in Cyclone III LS devices. The volatile key
clear and key program JTAG instructions from the device core is supported to protect
Cyclone III LS devices against tampering. You can clear and reprogram the key from
the device core whenever tampering attempt is detected by executing the
KEY_CLR_VREG and KEY_PROG_VOLJTAG instructions to clear and reprogram the
volatile key, and then reset the Cyclone III LS device by pulling the nCONFIGpin low
for at least 500 ns. When nCONFIGreturns to a logic-high level and nSTATUSis released
by the Cyclone III LS device, reconfiguration begins to configure the Cyclone III LS
device with a benign or unencrypted configuration file. After configuration is
successfully completed, observe the cyclecompletesignal from error detection block
to ensure that reconfigured CRAM bits content is correct for at least one error
detection cycle. You can also observe the cyclecompleteand crcerrorsignals for any
unintentional CRAM bits change.
f
cyclecompleteis a signal that is routed from the error detection block to the core for
the purpose of every complete error detection cycle. You must include the
cycloneiiils_crcblockWYSIWYG atom in your design to use the cyclecomplete
signal. For more information about the SEU mitigation, refer to the SEU Mitigation in
Cyclone III Devices chapter.
V
CCBAT is a dedicated power supply for the volatile key storage and not shared with
other on-chip power supplies, such as VCCIO or VCC. VCCBAT continuously supplies
power to the volatile register regardless of the on-chip supply condition. The nominal
voltage for this supply is 3.0 V, while its valid operating range is from 1.2 to 3.3 V. If
you do not use the volatile security key, you may connect the VCCBAT to a 1.8-V, 2.5-V,
or 3.0-V power supply.
1
1
After power-up, wait for 200 ms (Standard POR) or 9 ms (Fast POR) before beginning
the key programming to ensure that VCCBAT is at its full rail.
As an example, BR1220 (-30°C to +80°C) and BR2477A (-40 C to +125°C) are lithium
coin-cell type batteries used for volatile key storage purposes.
f
For more information about the battery specifications, refer to the Cyclone III LS Device
Data Sheet chapter.
Cyclone III LS Design Security Solution
Cyclone III LS devices are SRAM-based devices. To provide design security,
Cyclone III LS devices require a 256-bit volatile key for configuration bitstream
encryption.
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Design Security
The Cyclone III LS design security feature provides routing architecture optimization
for design separation flow with the Quartus II software. Design separation flow
achieves both physical and functional isolation between design partitions.
f
For more information about the design separation flow, refer to AN 567: Quartus II
Design Separation Flow.
You can carry out secure configuration in Steps 1–3, as shown in Figure 9–31:
1. Generate the encryption key programming file and encrypt the configuration data.
The Quartus II configuration software uses the user-defined 256-bit volatile keys
to generate a key programming file and an encrypted configuration file. The
encrypted configuration file is stored in an external memory, such as a flash
memory or a configuration device.
2. Program the volatile key into the Cyclone III LS device.
Program the user-defined 256-bit volatile keys into the Cyclone III LS device
through the JTAG interface.
3. Configure the Cyclone III LS device.
At system power-up, the external memory device sends the encrypted
configuration file to the Cyclone III LS device.
(1)
Figure 9–31. Cyclone III LS Secure Configuration Flow
Step 1. Generate the Encryption Key Programming File
Encrypt Configuration Data and Store in External Memory
Step 3. Configure the Cyclone III LS Device
Using Encrypted Configuration Data
Encrypted
Configuration
Data
FPGA
Encrypted
Configuration
Data
AES
Decryptor
Quartus II
Memory
Storage
Configuration
Data
AES
Encrypted
Configuration
Data
Encryptor
Encryption Key
Programming File
Volatile
Key Storage
Volatile Key
Volatile Key
Step 2. Program Volatile Key into
Cyclone III LS Device
Note to Figure 9–31:
(1) Step 1, Step 2, and Step 3 correspond to the procedure detailed in “Cyclone III LS Design Security Solution”.
Available Security Modes
There are several security modes available on Cyclone III LS devices, they are:
Volatile Key
No Key Operation
FACTORYMode
■
■
■
Volatile Key
Secure operation with volatile key programmed and required external battery—this
mode accepts both encrypted and unencrypted configuration bitstreams. Use the
unencrypted configuration bitstream support for board-level testing only.
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Remote System Upgrade
No Key Operation
Only unencrypted configuration bitstreams are allowed to configure the device.
FACTORY Mode
After power up, Cyclone III LS devices must be in FACTORYmode to program the
volatile key. The FACTORYprivate JTAG instruction must be issued after the device
successfully exits from POR and before the device starts loading the core
configuration data to enable access to all other instructions from the JTAG pins. The
device configuration data and AES volatile key are cleared if the FACTORYinstruction
is executed.
Table 9–25 lists the configuration bitstream and the configuration mode supported for
each security mode.
Table 9–25. Security Modes Supported
Configuration
Mode
Function
Allowed Configuration Mode
File
PS with AES (without decompression).
FPP with AES (without decompression).
Secure
Encrypted
Remote update fast AS with AES
(without decompression).
Volatile Key
Fast AS (without decompression).
Board-Level
Testing
All configuration modes that do not
engage the design security feature.
Unencrypted
Unencrypted
—
All configuration modes that do not
engage the design security feature.
No Key
—
Volatile Key
Programming
FACTORY
—
Remote System Upgrade
Cyclone III devices support remote system upgrade in AS and AP configuration
schemes. Cyclone III LS devices support remote system upgrade in the AS
configuration scheme only. Remote system upgrade can also be implemented with
advanced Cyclone III features such as real-time decompression of configuration data
in the AS configuration scheme.
■
■
■
The serial configuration device uses the AS configuration scheme to configure
Cyclone III or Cyclone III LS devices
The supported parallel flash uses the AP configuration scheme to configure
Cyclone III devices
Remote system upgrade is not supported in the multi-device configuration chain
for any configuration scheme.
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Remote System Upgrade
Functional Description
The dedicated remote system upgrade circuitry in Cyclone III device family manages
remote configuration and provides error detection, recovery, and status information.
User logic or a Nios II processor implemented in the Cyclone III device family logic
array provides access to the remote configuration data source and an interface to the
configuration memory.
1
Configuration memory refers to serial configuration devices (EPCS) or supported
parallel flash memory, and depends on the configuration scheme that you use.
The remote system upgrade process of Cyclone III device family involves the
following steps:
1. A Nios II processor (or user logic) implemented in the Cyclone III device family
logic array receives new configuration data from a remote location. The connection
to the remote source is a communication protocol such as the transmission control
protocol/Internet protocol (TCP/IP), peripheral component interconnect (PCI),
user datagram protocol (UDP), universal asynchronous receiver/transmitter
(UART), or a proprietary interface.
2. The Nios II processor (or user logic) writes this new configuration data into a
configuration memory.
3. The Nios II processor (or user logic) starts a reconfiguration cycle with the new or
updated configuration data.
4. The dedicated remote system upgrade circuitry detects and recovers from any
error that might occur during or after the reconfiguration cycle, and provides error
status information to the user design.
Figure 9–32 shows the steps required for performing remote configuration updates
(the numbers in Figure 9–32 coincide with steps 1–4).
Figure 9–32. Functional Diagram of Cyclone III Device Family Remote System Upgrade
1
2
Data
Data
Configuration
Memory
Cyclone III
Device Family
Control Module
Development
Location
Data
Device Configuration
3
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Remote System Upgrade
Figure 9–33 shows the block diagrams to implement remote system upgrade with the
AS and AP configuration schemes.
Figure 9–33. Remote System Upgrade Block Diagrams for AS and AP Configuration Schemes
Serial Configuration Device
Parallel Flash Memory
Cyclone III or
Cyclone III LS
Device
Cyclone III Device
Nios Processor or User
Logic
Nios Processor or User
Logic
Serial Configuration Device
Supported Parallel Flash
1
Remote system upgrade only supports single-device configuration.
When using remote system upgrade in Cyclone III devices, you must set the mode
select pins (MSEL [3.0]) to the AS or AP configuration scheme. When using remote
system upgrade in Cyclone III LS devices, you must set MSEL [3..0]to the AS
configuration scheme. The MSEL pin setting in remote system upgrade mode is the
same as standard configuration mode. Standard configuration mode refers to normal
Cyclone III device family configuration mode with no support for remote system
upgrades, and the remote system upgrade circuitry is disabled. When using remote
system upgrade in Cyclone III device family, you must enable the remote update
mode option setting in the Quartus II software. For more information, refer to
“Enabling Remote Update” on page 9–76.
Enabling Remote Update
You can enable or disable remote update for Cyclone III device family in the
Quartus II software before design compilation (in the Compiler Settings menu). To
enable remote update in the compiler settings of the project, perform the following
steps in the Quartus II software:
1. On the Assignments menu, click Device. The Settings dialog box appears.
2. Click Device and Pin Options. The Device and Pin Options dialog box appears.
3. Click the Configuration tab.
4. From the Configuration Mode list, select Remote.
5. Click OK.
6. In the Settings dialog box, click OK.
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Remote System Upgrade
Configuration Image Types
When using remote system upgrade, Cyclone III device family configuration
bitstreams are classified as factory configuration images or application configuration
images. An image, also referred to as a configuration, is a design loaded into the
device that performs certain user-defined functions. Each device in your system
requires one factory image with the addition of one or more application images. The
factory image is a user-defined fall-back, or safe, configuration and is responsible for
administering remote updates with dedicated circuitry. Application images
implement user-defined functionality in the target Cyclone III device family. You can
include the default application image functionality in the factory image.
Remote System Upgrade Mode
In remote update mode, the Cyclone III device family loads the factory configuration
image after power-up. The user-defined factory configuration determines which
application configuration is to be loaded and triggers a reconfiguration cycle. The
factory configuration can also contain application logic.
When used with configuration memory, remote update mode allows an application
configuration to start at any flash sector boundary. Additionally, the remote update
mode features a user watchdog timer that can detect functional errors in an
application configuration.
Remote Update Mode
When a Cyclone III device family is first powered up in remote update in the AS
configuration scheme, it loads the factory configuration located at address
boot_address[23:0] = 24b'0. Altera recommends storing the factory configuration
image for your system at boot address 24b'0when using the AS configuration
scheme. A factory configuration image is a bitstream for Cyclone III device family in
your system that is programmed during production and is the fall-back image when
an error occurs. This image is stored in non-volatile memory and is never updated or
modified using remote access. This corresponds to the start address location 0x000000
in the serial configuration device.
When you use the AP configuration in Cyclone III devices, the Cyclone III device
loads the default factory configuration located at the following address after device
power-up in remote update mode:
boot_address[23:0] = 24'h010000 = 24'b1 0000 0000 0000 0000
You can change the default factory configuration address to any desired address using
the APFC_BOOT_ADDR JTAG instruction. The factory configuration image is stored in
non-volatile memory and is never updated or modified using remote access. This
corresponds to the default start address location 0x010000 represented in 16-bit word
addressing (or the updated address if the default address is changed) in the
supported parallel flash memory. For more information about the application of the
APFC_BOOT_ADDRJTAG instruction in AP configuration scheme, refer to “JTAG
Instructions” on page 9–60.
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Remote System Upgrade
The factory configuration image is user designed and contains soft logic (Nios II
processor or state machine and the remote communication interface) to:
■
■
■
Process any errors based on status information from the dedicated remote system
upgrade circuitry
Communicate with the remote host and receive new application configurations
and store the new configuration data in the local non-volatile memory device
Determine which application configuration is to be loaded into the Cyclone III
device family
■
■
Enable or disable the user watchdog timer and load its time-out value (optional)
Instruct the dedicated remote system upgrade circuitry to start a reconfiguration
cycle
Figure 9–34 shows the transitions between the factory and application configurations
in remote update mode.
Figure 9–34. Transitions Between Configurations in Remote Update Mode
Configuration Error
Application 1
Configuration
Power Up
Set Control Register
and Reconfigure
Factory
Reload a Different Application
Configuration
Configuration
Error
Reload a Different Application
Application n
Configuration
Set Control Register
and Reconfigure
Configuration Error
After power up or a configuration error, the factory configuration logic writes the
remote system upgrade control register to specify the address of the application
configuration to be loaded. The factory configuration also specifies whether or not to
enable the user watchdog timer for the application configuration and, if enabled,
specifies the timer setting.
1
Only valid application configurations designed for remote update mode include the
logic to reset the timer in user mode. For more information about the user watchdog
timer, refer to “User Watchdog Timer” on page 9–85.
If there is an error while loading the application configuration, the remote system
upgrade status register is written by the dedicated remote system upgrade circuitry of
the Cyclone III device family, specifying the cause of the reconfiguration.
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Remote System Upgrade
The following actions cause the remote system upgrade status register to be written:
nSTATUSdriven low externally
Internal CRC error
User watchdog timer time-out
A configuration reset (logic array nCONFIGsignal or external nCONFIGpin assertion)
■
■
■
■
Cyclone III device family automatically load the factory configuration located at
address boot_address[23:0] = 24'b0for the AS configuration scheme, and default
address boot_address[23:0] = 24'h010000(or the updated address if the default
address is changed) for the AP configuration scheme. This user-designed factory
configuration reads the remote system upgrade status register to determine the reason
for reconfiguration. Then the factory configuration takes the appropriate error
recovery steps and writes to the remote system upgrade control register to determine
the next application configuration to be loaded.
When Cyclone III device family successfully load the application configuration, the
devices enter user mode. In user mode, the soft logic (Nios II processor or state
machine and the remote communication interface) assists the Cyclone III device
family in determining when a remote system update is arriving. When a remote
system update arrives, the soft logic receives the incoming data, writes it to the
configuration memory device, and triggers the device to load the factory
configuration. The factory configuration reads the remote system upgrade status
register, determines the valid application configuration to load, writes the remote
system upgrade control register accordingly, and starts system reconfiguration.
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Remote System Upgrade
Dedicated Remote System Upgrade Circuitry
This section explains the implementation of the Cyclone III device family remote
system upgrade dedicated circuitry. The remote system upgrade circuitry is
implemented in hard logic. This dedicated circuitry interfaces to the user-defined
factory application configurations implemented in the Cyclone III device family logic
array to provide the complete remote configuration solution. The remote system
upgrade circuitry contains the remote system upgrade registers, a watchdog timer,
and state machines that control those components. Figure 9–35 shows the data path of
the remote system upgrade block.
(1)
Figure 9–35. Remote System Upgrade Circuit Data Path
Internal Oscillator
Status Register (SR)
Current
State
Logic
Previous
State
Register 2
Bit[30..0]
Previous
State
Register 1
Bit[30..0]
Control Register
Bit [38..0]
Bit[31..0]
Logic
Update Register
Bit [38..0]
update
RSU
Master
State
Machine
Logic
RSU
Reconfiguration
State
Shift Register
dout
User
Watchdog
Timer
timeout
din
din
dout
Machine
Bit [40..39]
Bit [38..0]
capture
clkout capture update
Logic
clkin
RU_nCONFIG
RU_nRSTIMER
RU_DIN
RU_CLK (2)
RU_DOUT
RU_SHIFTnLD
RU_CAPTnUPDT
Logic Array
Notes to Figure 9–35:
(1) RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN,RU_nCONFIG, and RU_nRSTIMERsignals
are internally controlled by the ALTREMOTE_UPDATE megafunction.
(2) RU_CLKrefers to ALTREMOTE_UPDATE megafunction block "clock" input. For more information, refer to the
Remote Update Circuitry (ALTREMOTE_UPDATE) Megafunction User Guide.
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9–81
Remote System Upgrade
Remote System Upgrade Registers
The remote system upgrade block contains a series of registers that stores the
configuration addresses, watchdog timer settings, and status information. These
registers are listed in Table 9–26.
Table 9–26. Remote System Upgrade Registers
Register
Description
This register is accessible by the logic array and allows the update, status, and control registers to be
written and sampled by user logic. Write access is enabled in remote update mode for factory
configurations to allow writes to the update register. Write access is disabled for all application
configurations in remote update mode.
Shift register
This register contains the current configuration address, the user watchdog timer settings, one option
bit for checking early CONF_DONE, and one option bit for selecting the internal oscillator as the startup
Control register state machine clock. During a read operation in an application configuration, this register is read into the
shift register. When a reconfiguration cycle is started, the contents of the update register are written into
the control register.
This register contains data similar to that in the control register. However, it can only be updated by the
factory configuration by shifting data into the shift register and issuing an update operation. When a
Update register reconfiguration cycle is triggered by the factory configuration, the control register is updated with the
contents of the update register. During a read in a factory configuration, this register is read into the shift
register.
This register is written to by the remote system upgrade circuitry on every reconfiguration to record the
cause of the reconfiguration. This information is used by the factory configuration to determine the
appropriate action following a reconfiguration. During a capture cycle, this register is read into the shift
Status register
register.
The control and status registers of the remote system upgrade are clocked by the
10-MHz internal oscillator (the same oscillator that controls the user watchdog timer).
However, the shift and update registers of the remote system upgrade are clocked by
the maximum frequency of 40-MHz user clock input (RU_CLK). There is no minimum
frequency for RU_CLK.
Remote System Upgrade Control Register
The remote system upgrade control register stores the application configuration
address, the user watchdog timer settings, and option bits for application
configuration. In remote update mode for the AS configuration scheme, the control
register address bits are set to all zeros (24'b0) at power up to load the AS factory
configuration. In remote update mode for the AP configuration scheme, the control
register address bits are set to 24'h010000 (24'b1 0000 0000 0000 0000) at power up to
load the AP default factory configuration. However, for the AP configuration scheme,
you can change the default factory configuration address to any desired address using
the APFC_BOOT_ADDR JTAG instruction. Additionally, a factory configuration in remote
update mode has write access to this register.
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Remote System Upgrade
The control register bit positions are shown in Figure 9–36 and listed in Table 9–27. In
the figure, the numbers show the bit position of a setting in a register. For example, bit
number 35 is the enable bit for the watchdog timer.
Figure 9–36. Remote System Upgrade Control Register
38
37
36
35
34 33
12 11
0
Rsv2 Cd_early Osc_int Wd_en Rsv1 Ru_address[21..0] Wd_timer[11..
When enabled, the early CONF_DONEcheck (Cd_early) option bit ensures that there is a
valid configuration at the boot address specified by the factory configuration and that
it is of the proper size. If an invalid configuration is detected or CONF_DONEpin is
asserted too early, the device resets and then reconfigures the factory configuration
image. The internal oscillator, as startup state machine clock (Osc_int) option bit,
ensures a functional startup clock to eliminate the hanging of startup when enabled.
When all option bits are turned on, they provide complete coverage for the
programming and startup portions of the application configuration. It is strongly
recommended that you turn on both the Cd_earlyand Osc_intoption bits.
1
The Cd_earlyand Osc_intoption bits for the application configuration must be
turned on by the factory configuration.
Table 9–27. Remote System Upgrade Control Register Contents
Control Register Bit
Value
Definition
User watchdog time-out value (most significant 12 bits of
29-bit count value:
Wd_timer[11..0]
12'b000000000000
{Wd_timer[11..0],17'b1000}
)
Configuration address (most significant 22 bits of 24-bit
22'b0000000000000000000000 boot address value:
Ru_address[21..0]
boot_address[23:0]
= {Ru_address[21..0],2'b0})
Rsv1
1'b0
1'b1
1’b1
1’b1
1'b1
Reserved bit
User watchdog timer enable bit
Wd_en
(1)
Osc_int
Internal oscillator as startup state machine clock enable bit
Early CONF_DONEcheck
(1)
Cd_early
Rsv2
Reserved bit
Note to Table 9–27:
(1) Option bit for the application configuration.
Remote System Upgrade Status Register
The remote system upgrade status register specifies the reconfiguration trigger
condition. The various trigger and error conditions include:
■
Cyclical redundancy check (CRC) error during application configuration
■
nSTATUSassertion by an external device due to an error
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Remote System Upgrade
■
Cyclone III device family logic array triggered a reconfiguration cycle, possibly
after downloading a new application configuration image
External configuration reset (nCONFIG) assertion
User watchdog timer time out
■
■
Table 9–28 lists the contents of the current state logic in the status register, when the
remote system upgrade master state machine is in factory configuration or
application configuration accessing the factory information or application
information respectively, and the MSEL pin setting is set to AS or AP configuration
scheme. The status register bit in Table 9–28 lists the bit positions in a 32-bit logic.
Table 9–28. Remote System Upgrade Current State Logic Contents In Status Register (1)
Current State Logic
Status Register Bit
31:30
Definition
Description
Master State Machine The current state of the RSU master
current state
Reserved bits
state machine
29:24
Padding bits that are set to all 0's
(2)
Factory information
The current 24-bit boot address that was
used by the configuration scheme as the
start address to load the current
configuration.
23:0
Boot address
Master State Machine The current state of the RSU master
31:30
29
current state
state machine
User watchdog timer
enable bit
The current state of the user watchdog
enable, which is active high
Application information
(3)
part 1
The current entire 29-bit
watchdog time-out value
User watchdog timer
time-out value
28:0
Master State Machine The current state of the RSU master
31:30
29:24
current state
state machine
Reserved bits
Padding bits that are set to all 0’s
Application information
part 2
(3)
The current 24-bit boot address that was
used by the configuration scheme as the
start address to load the current
configuration
23:0
Boot address
Notes to Table 9–28:
(1) The MSEL pin setting is in the AS or AP configuration scheme.
(2) The RSU master state machine is in factory configuration.
(3) The RSU master state machine is in application configuration.
The previous two application configurations are available in the previous state
registers (previous state register 1 and previous state register 2), but only for
debugging purposes.
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Remote System Upgrade
Table 9–29 lists the contents of the previous state register 1 and previous state register
2 in the status register when the MSEL pin setting is set to the AS or AP scheme. The
status register bit in Table 9–29 shows the bit positions in a 31-bit register. The
previous state register 1 and previous state register 2 have the same bit definitions.
The previous state register 1 reflects the current application configuration and the
previous state register 2 reflects the previous application configuration.
Table 9–29. Remote System Upgrade Previous State Register 1 and Previous State Register 2
(1)
Contents in Status Register
Status Register Bit
Definition
nCONFIGsource
Description
30
29
28
27
One-hot, active-high field that
describes the reconfiguration source
that caused the Cyclone III device
family to leave the previous application
configuration. If there is a tie, the
higher bit order indicates precedence.
For example, if nCONFIGand remote
system upgrade nCONFIGreach the
reconfiguration state machine at the
same time, the nCONFIGprecedes the
CRC error source
nSTATUSsource
User watchdog timer source
Remote system upgrade nCONFIG
source
26
remote system upgrade nCONFIG
.
The state of the master state machine
during reconfiguration causes the
Cyclone III device family to leave the
previous application configuration.
25:24
Master state machine current state
Boot address
The address used by the configuration
scheme to load the previous
application configuration.
23:0
Note to Table 9–29:
(1) The MSEL pin settings are in the AS configuration scheme.
If a capture is inappropriately done, for example, capturing a previous state before the
system has entered remote update application configuration for the first time, a value
will output from the shift register to indicate that the capture was incorrectly called.
Remote System Upgrade State Machine
The remote system upgrade control and update registers have identical bit
definitions, but serve different roles (Table 9–26 on page 9–81). While both registers
can only be updated when the device is loaded with a factory configuration image,
the update register writes are controlled by the user logic, and the control register
writes are controlled by the remote system upgrade state machine.
In factory configurations, the user logic should send the option bits (Cd_earlyand
Osc_int), the configuration address, and watchdog timer settings for the next
application configuration bit to the update register. When the logic array
configuration reset (RU_nCONFIG) goes high, the remote system upgrade state machine
updates the control register with the contents of the update register and starts system
reconfiguration from the new application page.
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9–85
Remote System Upgrade
1
To ensure the successful reconfiguration between the pages, assert RU_nCONFIGsignal
for a minimum of 250 ns. This is equivalent to strobing the reconfiginput of the
ALTREMOTE_UPDATE megafunction high for a minimum of 250 ns.
If there is an error or reconfiguration trigger condition, the remote system upgrade
state machine directs the system to load a factory or application configuration (based
on mode and error condition) by setting the control register accordingly.
Table 9–30 lists the contents of the control register after such an event occurs for all
possible error or trigger conditions.
The remote system upgrade status register is updated by the dedicated error
monitoring circuitry after an error condition but before the factory configuration is
loaded.
Table 9–30. Control Register Contents After an Error or Reconfiguration Trigger Condition
Reconfiguration
Error/Trigger
Control Register Setting In
Remote Update
nCONFIGreset
nSTATUSerror
All bits are 0
All bits are 0
Update register
All bits are 0
All bits are 0
CORE triggered reconfiguration
CRC error
Wd time out
User Watchdog Timer
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. The system uses the timer to detect functional errors after an
application configuration is successfully loaded into the Cyclone III device family.
The user watchdog timer is a counter that counts down from the initial value loaded
into the remote system upgrade control register by the factory configuration. The
counter is 29-bits wide and has a maximum count value of 229. When specifying the
user watchdog timer value, specify only the most significant 12 bits. Remote system
upgrade circuitry appends 17’b1000 to form the 29 bits value for the watchdog timer.
The granularity of the timer setting is 217 cycles. The cycle time is based on the
frequency of the 10-MHz internal oscillator.
Table 9–31 lists the operating range of the 10-MHz internal oscillator.
Table 9–31. 10-MHz Internal Oscillator Specifications
Minimum
Typical
Maximum
Unit
5
6.5
10
MHz
The user watchdog timer begins counting after the application configuration enters
device user mode. This timer must be periodically reloaded or reset by the application
configuration before the timer expires by asserting RU_nRSTIMER. If the application
configuration does not reload the user watchdog timer before the count expires, a
time-out signal is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user watchdog
timer status bit (Wd) in the remote system upgrade status register and reconfigures the
device by loading the factory configuration.
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Document Revision History
1
1
To allow remote system upgrade dedicated circuitry to reset the watchdog timer, you
must assert the RU_nRSTIMERsignal active for a minimum of 250 ns. This is equivalent
to strobing the reset_timerinput of the ALTREMOTE_UPDATE megafunction high
for a minimum of 250 ns.
The user watchdog timer is not enabled during the configuration cycle of the device.
Errors during configuration are detected by the CRC engine. Also, the timer is
disabled for factory configuration. Functional errors must not exist in the factory
configuration because it is stored and validated during production and is never
updated remotely.
By default, the user watchdog timer is disabled in factory configurations and enabled
in user-mode application configurations. If you do not want to use the watchdog
timer feature, disable this feature in the factory configuration.
Quartus II Software Support
Implementation in your design requires a remote system upgrade interface between
the Cyclone III device family logic array and the remote system upgrade circuitry. You
must also generate configuration files for production and remote programming of the
system configuration memory. The Quartus II software provides these features.
The two implementation options, the ALTREMOTE_UPDATE megafunction and the
remote system upgrade atom, are for the interface between the remote system
upgrade circuitry and the device logic array interface. Using the megafunction block
instead of creating your own logic saves design time and offers more efficient logic
synthesis and device implementation.
f
For more information about the ALTREMOTE_UPDATE megafunction, refer to the
Remote Update Circuitry (ALTREMOTE_UPDATE) Megafunction User Guide.
Document Revision History
Table 9–32 lists the revision history for this document.
Table 9–32. Document Revision History (Part 1 of 2)
Date
August 2012
July 2012
Version
2.2
Changes
Updated Micron P30 and P33 Parallel NOR flash devices.
Finalized Table 9–3, Table 9–13, and Table 9–14.
2.1
■ Updated “Configuration Features” on page 9–2, “Reset” on page 9–8,“AS Configuration
(Serial Configuration Devices)” on page 9–12, “Single-Device AS Configuration” on
page 9–13, “AP Configuration Supported Flash Memory” on page 9–24, “Single-Device
AP Configuration” on page 9–25, “JTAG Configuration” on page 9–48, and “User
Watchdog Timer” on page 9–85.
■ Removed the “Overriding the Internal Oscillator” section from “JTAG Configuration”.
December 2011
2.0
■ Updated Figure 9–11, Figure 9–24, Figure 9–25, Figure 9–26, Figure 9–27, Figure 9–29,
Figure 9–30.
■ Updated Table 9–13, Table 9–18, and Table 9–22.
■ Replaced links to AN 386: Using the Parallel Flash Loader with the Quartus II Software
links to Parallel Flash Loader Megafunction User Guide.
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Volume 1
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9–87
Document Revision History
Table 9–32. Document Revision History (Part 2 of 2)
Date
Version
Changes
■ Updated Table 9–7, Table 9–10, Table 9–22, and Table 9–28.
■ Updated Figure 9–23 and Figure 9–30.
December 2009
1.2
■ Updated the “Programming Serial Configuration Devices” and “Security Against
Tampering” sections.
■ Minor changes to the text.
Made a minor correction to the part number.
Initial release.
July 2009
June 2009
1.1
1.0
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Document Revision History
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
10. Hot-Socketing and Power-On Reset in
the Cyclone III Device Family
July 2012
CIII51011-3.4
CIII51011-3.4
The Cyclone® III device family (Cyclone III and Cyclone III LS devices) offers
hot-socketing, which is also known as hot plug-in or hot swap, and power sequencing
support without the use of any external devices. You can insert or remove Cyclone III
device family or a board in a system during system operation without causing
undesirable effects to the running system bus or the board that is inserted into the
system.
The hot-socketing feature removes some of the difficulties that you encounter when
you use Cyclone III device family on a PCB that contains a mixture of 3.3, 3.0, 2.5, 1.8,
1.5, and 1.2 V devices. With the hot-socketing feature of Cyclone III device family, you
no longer need to ensure a proper power up sequence for each device on the board.
Cyclone III device family hot-socketing feature provides:
■
Board or device insertion and removal without external components or board
manipulation
■
■
Support for any power-up sequence
Non-intrusive I/O buffers to system buses during hot insertion
This chapter also describes the power-on reset (POR) circuitry in Cyclone III device
family. The POR circuitry keeps the devices in the reset state until the power supplies
are in operating range.
This chapter contains the following sections:
■
■
■
“Hot-Socketing Specifications” on page 10–1
“Hot-Socketing Feature Implementation” on page 10–3
“POR Circuitry” on page 10–3
Hot-Socketing Specifications
Cyclone III device family is a hot-socketing compliant without the need for any
external components or special design requirements. Hot-socketing support in
Cyclone III device family has the following advantages:
■
You can drive the device before power-up without damaging the device.
■
I/O pins remain tristated during power-up. The device does not drive out before
or during power-up, therefore not affecting other buses in operation.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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Subscribe
10–2
Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Hot-Socketing Specifications
Devices Driven Before Power-Up
You can drive signals into I/O pins, dedicated input pins, and dedicated clock pins of
Cyclone III device family before or during power-up or power down without
damaging the device. The Cyclone III device family supports any power-up or
power down sequence (VCCIO, VCCINT) to simplify system level design.
I/O Pins Remain Tristated During Power-Up
The output buffers of Cyclone III device family are turned off during system
power up or power down. Cyclone III device family does not drive out until the
device is configured and working in recommended operating conditions. The I/O
pins are tristated until the device enters user mode with a weak pull-up resistor (R) to
VCCIO
.
You can power-up or power down the VCCIO, VCCA, and VCCINT pins in any sequence.
The VCCIO, VCCA, and VCCINT pins must have a monotonic rise to their steady state
levels. The maximum power ramp rate is 3 ms for fast POR time and 50 ms for
standard POR time. The minimum power ramp rate is 50 µs. VCCIO for all I/O banks
must be powered up during device operation. All VCCA pins must be powered to 2.5 V
(even when PLLs are not used), and must be powered up and powered down at the
same time. VCCD_PLL must always be connected to VCCINT through a decoupling
capacitor and ferrite bead. During hot-socketing, the I/O pin capacitance is less than
15 pF and the clock pin capacitance is less than 20 pF.
Cyclone III device family meets the following hot-socketing specification:
■
The hot-socketing DC specification is | IIOPIN | < 300 uA
■
The hot-socketing AC specification is | IIOPIN | < 8 mA for the ramp rate of 10 ns
or more
For ramp rates faster than 10 ns on I/O pins, |IIOPIN| is obtained with the equation
I = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. The
hot-socketing specification takes into account the pin capacitance but not board trace
and external loading capacitance. You must consider additional or separate
capacitance for trace, connector, and loading. IIOPIN is the current for any user I/O
pins on the device. The DC specification applies when all VCC supplied to the device is
stable in the powered-up or powered-down conditions.
A possible concern for semiconductor devices in general regarding hot-socketing is
the potential for latch up. Latch up can occur when electrical subsystems are
hot-socketed into an active system. During hot-socketing, the signal pins may be
connected and driven by the active system before the power supply can provide
current to the VCC of the device and ground planes. This condition can lead to latch up
and cause a low-impedance path from VCC to ground in the device. As a result, the
device extends a large amount of current, possibly causing electrical damage.
The design of the I/O buffers and hot-socketing circuitry ensures that Cyclone III
device family are immune to latch up during hot-socketing.
f
For more information about the hot-socketing specification, refer to the Cyclone III
Device Data Sheet and Cyclone III LS Device Data Sheet chapters and the Hot-Socketing
and Power-Sequencing Feature and Testing for Altera Devices white paper.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
10–3
Hot-Socketing Feature Implementation
Hot-Socketing Feature Implementation
Each I/O pin has the circuitry shown in Figure 10–1. The hot-socketing circuit does
not include CONF_DONE nCEO, and nSTATUSpins to ensure that they are able to operate
,
during configuration. Thus, it is expected behavior for these pins to drive out during
power up and power down sequences.
Figure 10–1 shows the hot-socketing circuit block diagram for Cyclone III device
family.
Figure 10–1. Hot-socketing Circuit Block Diagram for Cyclone III Device Family
Power On
Reset
Monitor
VCCIO
Weak
Pull-Up
Resistor
R
Output Enable
Voltage
Tolerance
Control
Hot Socket
PAD
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors the voltage level of power supplies and keeps the I/O pins
tristated until the device is in user mode. The weak pull-up resistor (R) in Cyclone III
device family I/O element (IOE) keeps the I/O pins from floating. The 3.3-V tolerance
control circuit permits the I/O pins to be driven by 3.3 V before VCCIO, VCC, and VCCA
supplies are powered up, and it prevents the I/O pins from driving out when the
device is not in user mode.
1
Altera uses GND as reference for hot-socketing operation and I/O buffer designs. To
ensure proper operation, Altera recommends connecting the GND between boards
before connecting the power supplies. This prevents the GND on your board from
being pulled up inadvertently by a path to power through other components on your
board. A pulled up GND can otherwise cause an out-of-specification I/O voltage or
current condition with the Altera® device.
POR Circuitry
Cyclone III device family contains POR circuitry to keep the device in a reset state
until the power supply voltage levels have stabilized during power up. During POR,
all user I/O pins are tristated until the VCC reaches the recommended operating
levels. In addition, the POR circuitry also ensures the VCCIO level of I/O banks 1, 6, 7,
and 8 that contains configuration pins reach an acceptable level before configuration
is triggered.
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Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Document Revision History
The POR circuit of the Cyclone III device monitors the VCCINT, VCCIO (banks 1, 6, 7,
and 8), and VCCA pins during power-on. The enhanced POR circuit of the Cyclone III
LS device includes monitoring VCCBAT to ensure that VCCBAT is always at the minimum
requirement voltage level.
1
The VCCBAT power supply is the new design security feature power supply introduced
for Cyclone III LS devices only. Cyclone III devices do not have VCCBAT power supply.
After Cyclone III device family enters user mode, the POR circuit continues to
monitor the VCCINT or VCCA pins so that a brown-out condition during user mode is
detected. If the VCCINT or VCCA voltage sags below the POR trip point during user
mode, the POR circuit resets the device. If the VCCIO voltage sags during user mode,
the POR circuit does not reset the device.
In some applications, it is necessary for a device to wake up very quickly to begin
operation. Cyclone III device family offers the Fast-On feature to support fast
wake-up time applications. For Cyclone III device family, the MSEL[3..0]pin settings
determine the POR time (tPOR) of the device. Fast POR ranges from 3 ms to 9 ms, while
standard POR ranges from 50 ms to 200 ms.
If you cannot meet the maximum VCC ramp time requirement, use an external
component to hold nCONFIGlow until the power supplies have reached their
minimum recommend operating levels. Otherwise, the device may not properly
configure and enter user mode.
f
f
For more information about the MSEL[3..0]pin settings, refer to the Configuration,
Design Security, and Remote System Upgrades in the Cyclone III Device Family chapter.
For more information about the VCCBAT pin connection, refer to the Cyclone III Device
Family Pin Connection Guidelines.
Document Revision History
Table 10–1 lists the revision history for this document.
Table 10–1. Document Revision History (Part 1 of 2)
Date
July 2012
Version
Changes
Updated tolerance control circuit voltage level in the “Hot-Socketing Feature
Implementation” section.
3.4
■ Updated “POR Circuitry” on page 10–3.
■ Updated hyperlinks.
December 2011
3.3
■ Minor text edits.
December 2009
July 2009
3.2
3.1
Minor changes to the text.
Made minor correction to the part number.
■ Updated chapter part number.
■ Updated “I/O Pins Remain Tristated During Power-Up” on page 10–2.
■ Updated “Hot-Socketing Feature Implementation” on page 10–3.
■ Updated “POR Circuitry” on page 10–4.
June 2009
3.0
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
10–5
Document Revision History
Table 10–1. Document Revision History (Part 2 of 2)
Date
Version
Changes
■ Updated chapter to new template.
October 2008
1.2
■ Added handnote to the “Cyclone III Hot-Socketing Specifications” section.
■ Updated “I/O Pins Remain Tri-stated During Power-Up” section.
■ Updated Figure 10–3.
July 2007
1.1
1.0
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
10–6
Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Document Revision History
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
11. SEU Mitigation in the Cyclone III
Device Family
December 2011
CIII51013-2.3
CIII51013-2.3
Dedicated circuitry built into the Cyclone® III device family (Cyclone III and
Cyclone III LS devices) consists of a cyclical redundancy check (CRC) error detection
feature that can optionally check for a single-event upset (SEU) continuously and
automatically.
In critical applications used in the fields of avionics, telecommunications, system
control, medical, and military applications, it is important to be able to:
■
Confirm the accuracy of the configuration data stored in an FPGA device
Alert the system to an occurrence of a configuration error
■
This chapter describes how to activate and use the error detection CRC feature in user
mode and describes how to recover from configuration errors caused by CRC error.
Using the CRC error detection feature for Cyclone III device family does not impact
fitting or performance.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
■
■
“Error Detection Fundamentals” on page 11–1
“Configuration Error Detection” on page 11–2
“User Mode Error Detection” on page 11–2
“Automated SEU Detection” on page 11–3
“CRC_ERROR Pin” on page 11–3
“Table 11–2 lists the CRC_ERRORpin.” on page 11–4
“Error Detection Block” on page 11–4
“Error Detection Timing” on page 11–5
“Software Support” on page 11–7
“Recovering from CRC Errors” on page 11–10
Error Detection Fundamentals
Error detection determines if the data received through an input device is corrupted
during transmission. In validating the data, the transmitter uses a function to
calculate a checksum value for the data and appends the checksum to the original
data frame. The receiver uses the same calculation methodology to generate a
checksum for the received data frame and compares the received checksum to the
transmitted checksum. If the two checksum values are equal, the received data frame
is correct and no data corruption has occurred during transmission or storage.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
December 2011
Subscribe
11–2
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Configuration Error Detection
The error detection CRC feature in Cyclone III device family puts theory into practice.
In user mode, the error detection CRC feature in Cyclone III device family ensures the
integrity of the configuration data.
Configuration Error Detection
In configuration mode, a frame-based CRC is stored in the configuration data and
contains the CRC value for each data frame.
During configuration, Cyclone III device family calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until either the device detects an error or all the
values are calculated.
For Cyclone III device family, the CRC is computed by the Quartus® II software and
downloaded into the device as part of the configuration bit stream. These devices
store the CRC in the 32-bit storage register at the end of the configuration mode.
User Mode Error Detection
Soft errors are changes in a configuration random-access memory (CRAM) bit state
due to an ionizing particle. Cyclone III device family has built-in error detection
circuitry to detect data corruption by soft errors in the CRAM cells.
This error detection capability continuously computes the CRC of the configured
CRAM bits based on the contents of the device and compares it with the
pre-calculated CRC value obtained at the end of the configuration. If the CRCs match,
there is no error in the current configuration CRAM bits. The process of error
detection continues until the device is reset (by setting nCONFIGto low).
The Cyclone III device family error detection feature does not check memory blocks
and I/O buffers. These device memory blocks support parity bits that are used to
check the contents of memory blocks for any error. The I/O buffers are not verified
during error detection because the configuration data uses flip-flops as storage
elements that are more resistant to soft errors. Similar flip-flops are used to store the
pre-calculated CRC and other error detection circuitry option bits.
The error detection circuitry in Cyclone III device family uses a 32-bit CRC IEEE 802
standard and a 32-bit polynomial as the CRC generator. Therefore, a single 32-bit CRC
calculation is performed by the device. If a soft error does not occur, the resulting
32-bit signature value is 0x000000, which results in a
If a soft error occurs in the device, the resulting signature value is non-zero and the
CRC_ERRORoutput signal is
0on the output signal CRC_ERROR.
1
.
You can inject a soft error by changing the 32-bit CRC storage register in the CRC
circuitry. After verifying the failure induced, you can restore the 32-bit CRC value to
the correct CRC value using the same instruction and inserting the correct value.
1
Be sure to read out the correct value before updating it with a known bad value.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 11: SEU Mitigation in the Cyclone III Device Family
11–3
Automated SEU Detection
In user mode, Cyclone III device family supports the CHANGE_EDREGJTAG instruction,
which allows you to write to the 32-bit storage register. You can use Jam™ STAPL files
(.jam) to automate the testing and verification process. This instruction can only be
executed when the device is in user mode, and it is a powerful design feature that
enables you to dynamically verify the CRC functionality in-system without having to
reconfigure the device. You can then switch to use the CRC circuit to check for real
errors induced by an SEU.
Table 11–1 lists the CHANGE_EDREGJTAG instructions.
Table 11–1. CHANGE_EDREG JTAG Instruction
JTAG Instruction Instruction Code
Description
This instruction connects the 32-bit CRC storage register between TDIand TDO
Any precomputed CRC is loaded into the CRC storage register to test the operation
.
CHANGE_EDREG
00 0001 0101
of the error detection CRC circuitry at the CRC_ERRORpin.
1
After the test completes, to clear the CRC error and restore the original CRC value,
power cycle the device or perform the following procedure:
1. After the configuration completes, use JTAG instruction CHANGE_EDREGto shift out
the correct precomputed CRC value and load the wrong CRC value to the CRC
storage register. The CRC_ERRORpin will be asserted and shows that a CRC error is
detected.
2. Use JTAG instruction CHANGE_EDREGto shift in the correct precomputed CRC value.
The CRC_ERRORpin is deasserted and shows that the error detection CRC circuitry
is working.
Automated SEU Detection
Cyclone III device family offers on-chip circuitry for automated checking of SEU
detection. Applications that require the device to operate error-free at high elevations
or in close proximity to earth’s North or South Pole require periodic checks to ensure
continued data integrity. The error detection cyclic redundancy code feature
controlled by the Device and Pin Options dialog box in the Quartus II software uses a
32-bit CRC circuit to ensure data reliability and is one of the best options for
mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in
Cyclone III device family, eliminating the need for external logic. The CRC is
computed by the device during configuration and checked against an automatically
computed CRC during normal operation. The CRC_ERRORpin reports a soft error when
configuration CRAM data is corrupted, and you must decide whether to reconfigure
the FPGA by strobing the nCONFIGpin low or ignore the error.
CRC_ERROR Pin
A specific error detection pin, CRC_ERROR, is required to monitor the results of the error
detection circuitry during user mode.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
11–4
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection Block
Table 11–2 lists the CRC_ERRORpin.
Table 11–2. CRC_ERROR Pin Description
CRC_ERROR
Device
Description
Pin Type
By default, the Quartus II software sets the CRC_ERRORpin as a dedicated output. If the
CRC_ERRORpin is used as a dedicated output, you must ensure that the VCCIO of the bank in
Dedicated which the pin resides meets the input voltage specification of the system receiving the signal.
Output or
Open Drain Quartus II software from the Error Detection CRC tab of the Device and Pin Options dialog
Output box. Using the pin as an open-drain provides an advantage on the voltage leveling. To use this
Optionally, you can set this pin to be an open-drain output by enabling the option in the
Cyclone III
(Optional) pin as open-drain, you can tie this pin to VCCIO of Bank 1 through a 10-k pull-resistor.
Alternatively, depending on the voltage input specification of the system receiving the signal,
you can tie the pull-up resistor to a different pull-up voltage.
To use the CRC_ERRORpin, you can either tie this pin to VCCIO through a 10-kpull-up
resistor, or depending on input voltage specification of the system receiving the signal, you
can tie this pin to a different pull-up voltage.
Open Drain
Output
Cyclone III LS
f
For more information about the CRC_ERRORpin information for Cyclone III device
family, refer to the Cyclone III Pin-Out Files for Altera Devices page on the Altera®
website.
1
WYSIWYG is an optimization technique that performs optimization on VQM (Verilog
Quartus Mapping) netlist in the Quartus II software.
Error Detection Block
Table 11–3 lists the types of CRC detection to check the configuration bits.
Table 11–3. Types of CRC Detection to Check the Configuration Bits
First Type of CRC Detection
Second Type of CRC Detection
■ CRAM error checking ability (32-bit CRC) ■ 16-bit CRC embedded in every configuration data frame.
during user mode, for use by the
CRC_ERRORpin.
■ During configuration, after a frame of data is loaded into the device, the
pre-computed CRC is shifted into the CRC circuitry.
■ There is only one 32-bit CRC value, and
■ Simultaneously, the CRC value for the data frame shifted-in is calculated.
this value covers all the CRAM data.
If the pre-computed CRC and calculated CRC values do not match,
nSTATUSis set low.
■ Every data frame has a 16-bit CRC. Therefore, there are many 16-bit CRC
values for the whole configuration bit stream.
■ Every device has a different length of configuration data frame.
This section focuses on the first type—the 32-bit CRC when the device is in user
mode.
Error Detection Registers
There are two sets of 32-bit registers in the error detection circuitry that store the
computed CRC signature and pre-calculated CRC value. A non-zero value on the
signature register causes the CRC_ERRORpin to set high.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 11: SEU Mitigation in the Cyclone III Device Family
11–5
Error Detection Timing
Figure 11–1 shows the block diagram of the error detection block and the two related
32-bit registers: the signature register and the storage register.
Figure 11–1. Error Detection Block Diagram
Control Signals
Error Detection
State Machine
Compute & Compare
CRC
32
32
32-bit Storage
Register
32-bit Signature
Register
32
Table 11–4 lists the registers shown in Figure 11–1.
Table 11–4. Error Detection Registers
Register
Function
This register contains the CRC signature. The signature register contains the result of the user
mode calculated CRC value compared against the pre-calculated CRC value. If no errors are
detected, the signature register is all zeros. A non-zero signature register indicates an error in the
configuration CRAM contents.
32-bit signature
register
The CRC_ERRORsignal is derived from the contents of this register.
This register is loaded with the 32-bit pre-computed CRC signature at the end of the configuration
stage. The signature is then loaded into the 32-bit CRC circuit (called the Compute and Compare
CRC block, as shown in Figure 11–1) during user mode to calculate the CRC error. This register
forms a 32-bit scan chain during execution of the CHANGE_EDREGJTAG instruction. The
CHANGE_EDREGJTAG instruction can change the content of the storage register. Therefore, the
functionality of the error detection CRC circuitry is checked in-system by executing the instruction
to inject an error during the operation. The operation of the device is not halted when issuing the
CHANGE_EDREGinstruction.
32-bit storage register
Error Detection Timing
When the error detection CRC feature is enabled through the Quartus II software, the
device automatically activates the CRC process upon entering user mode after
configuration and initialization is complete.
The CRC_ERRORpin is driven low until the error detection circuitry has detected a
corrupted bit in the previous CRC calculation. After the pin goes high, it remains high
during the next CRC calculation. This pin does not log the previous CRC calculation.
If the new CRC calculation does not contain any corrupted bits, the CRC_ERRORpin is
driven low. The error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
11–6
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection Timing
Table 11–5 lists the minimum and maximum error detection frequencies.
Table 11–5. Minimum and Maximum Error Detection Frequencies
Error
Detection
Frequency
Maximum Error
Detection
Frequency
Minimum Error
Detection
Frequency
Device Type
Valid Divisors (2 )
Cyclone III
device family
80 MHz/2n
80 MHz
312.5 kHz
0, 1, 2, 3, 4, 5, 6, 7, 8
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to “Software Support” on page 11–7). The
divisor is a power of two (2), where n is between 0 and 8. The divisor ranges from one
through 256. Refer to Equation 11–1.
Equation 11–1. Error Detection Frequency
80 MHz
Error detection frequency = --------------------
2n
CRC calculation time depends on the device and the error detection clock frequency.
Table 11–6 lists the estimated time for each CRC calculation with minimum and
maximum clock frequencies for Cyclone III device family.
Table 11–6. CRC Calculation Time
Maximum Time (s)
(1)
Device
Minimum Time (ms)
(2)
EP3C5
EP3C10
5
2.29
2.29
5
EP3C16
7
3.17
EP3C25
9
4.51
Cyclone III
EP3C40
15
23
31
45
42
42
79
79
7.48
EP3C55
11.77
15.81
22.67
21.24
21.24
40.27
40.27
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Notes to Table 11–6:
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different
processes, voltages, and temperatures (PVT).
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 11: SEU Mitigation in the Cyclone III Device Family
11–7
Software Support
Software Support
Enabling the CRC error detection feature in the Quartus II software generates the
ERRORoutput to the optional dual purpose CRC ERRORpin.
CRC_
_
To enable the error detection feature using CRC, perform the following steps:
1. Open the Quartus II software and load a project using Cyclone III device family.
2. On the Assignments menu, click Settings. The Settings dialog box appears.
3. In the Category list, select Device. The Device page appears.
4. Click Device and Pin Options, as shown in Figure 11–2.
5. In the Device and Pin Options dialog box, click the Error Detection CRC tab.
6. Turn on Enable error detection CRC.
7. In the Divide error check frequency by box, enter a valid divisor as documented
in Table 11–5 on page 11–6.
1
The divisor value divides down the frequency of the configuration
oscillator output clock. This output clock is used as the clock source for the
error detection process.
8. Click OK.
Figure 11–2. Enabling the Error Detection CRC Feature in the Quartus II Software
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
11–8
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Software Support
1
For Cyclone III LS devices, the “Enable Open Drain on CRC Error Pin” option is not
available because the Quartus II software sets the CRC_ERRORpin for the Cyclone III LS
device as open drain output by default.
Accessing Error Detection Block Through User Logic
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register. This signature is read out by user logic from the core. The
<device>_crcblockprimitive is a WYSIWYG component used to establish the
interface from user logic to the error detection circuit. The <device>_crcblock
primitive atom contains the input and output ports that must be included in the atom.
To access the logic array, the <device>_crcblock WYSIWYG atom must be
inserted into your design.
Figure 11–3 shows the error detection block diagram in FPGA devices and shows the
interface that the WYSIWYG atom enables in your design.
Figure 11–3. Error Detection Block Diagram
80MHz Internal Chip Oscillator
Clock Divider
(1 to 256 Factor)
VCC
CRC_ERROR
(Shown in BIDIR Mode)
Pre-Computed CRC
(Saved in the Option Register)
Error Detection
Logic
SRAM
Bits
CRC
Computation
cyclecomplete
Logic Array
1
The user logic is affected by the soft error failure, thus reading out the 32-bit CRC
signature through the regoutshould not be relied upon to detect a soft error. You
should rely on the CRC_ERRORoutput signal itself, because this CRC_ERRORoutput
signal cannot be affected by a soft error.
To enable the <device>_crcblockWYSIWYG atom, you must name the atom for each
Cyclone III device family accordingly.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 11: SEU Mitigation in the Cyclone III Device Family
11–9
Software Support
Table 11–7 lists the name of the WYSIWYG atom for Cyclone III device family.
Table 11–7. WYSIWYG Atoms
Device
Cyclone III
WYSIWYG Atom
cycloneiii_crcblock
cycloneiiils_crcblock
Cyclone III LS
1
To enable the cycloneiii_crcblockprimitive in version 8.0 SP1 or earlier of the
Quartus II software, turn on the error detection CRC feature in the Device and Pins
Options dialog box. This is not required when you are using version 8.1 and later of
the Quartus II software.
Example 11–1 shows an example of how to define the input and output ports of a
WYSIWYG atom in a Cyclone III LS device.
Example 11–1. Error Detection Block Diagram
cycloneiiils_crcblock<crcblock_name>
(
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.ldsrc(<ldsrc source>),
.crcerror(<crcerror out destination>),
.regout(<output destination>),
.cyclecomplete(<cyclecomplete destination>),
);
Table 11–8 lists the input and output ports that must be included in the atom. The
input and output ports of the atoms for Cyclone III device family are similar, except
for the cyclecompleteport which is for Cyclone III LS devices only.
Table 11–8. CRC Block Input and Output Ports (Part 1 of 2)
Port
Input/Output
Definition
Unique identifier for the CRC block, and represents any identifier name that is
legal for the given description language (For example Verilog HDL, VHDL,
AHDL). This field is required.
<crcblock_name>
Input
This signal designates the clock input of this cell. All operations of this cell are
with respect to the rising edge of the clock. Whether it is the loading of the
data into the cell or data out of the cell, it always occurs on the rising edge.
This port is required.
.clk(<clock source>
Input
Input
This signal is an input into the error detection block. If shiftnld=1, the
data is shifted from the internal shift register to the regoutat each rising edge
of clk. If shiftnld=0, the shift register parallel loads either the
pre-calculated CRC value or the update register contents depending on the
ldsrcport input. This port is required.
.shiftnld (<shiftnld
source>)
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
11–10
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Recovering from CRC Errors
Table 11–8. CRC Block Input and Output Ports (Part 2 of 2)
Port
Input/Output
Definition
This signal is an input into the error detection block. If ldsrc=0, the
pre-computed CRC register is selected for loading into the 32-bit shift register
at the rising edge of clkwhen shiftnld=0. If ldsrc=1, the signature
register (result of the CRC calculation) is selected for loading into the shift
register at the rising edge of clkwhen shiftnld=0. This port is ignored
when shiftnld=1. This port is required.
.ldsrc (<ldsrc
source>)
Input
This signal is the output of the cell that is synchronized to the internal
oscillator of the device (80-MHz internal oscillator) and not to the clkport. It
asserts high if the error block detects that a SRAM bit has flipped and the
internal CRC computation has shown a difference with respect to the pre-
computed value. This signal must be connected either to an output pin or a
bidirectional pin. If it is connected to an output pin, you can only monitor the
CRC_ERROR pin(the core cannot access this output). If the CRC_ERROR
signal is used by core logic to read error detection logic, this signal must be
connected to a BIDIRpin. The signal is fed to the core indirectly by feeding a
BIDIRpin that has its output enable port connected to VCC (Figure 11–3 on
page 11–8).
.crcerror (<crcerror
indicator
Output
output>)
This signal is the output of the error detection shift register synchronized to
the clkport, to be read by core logic. It shifts one bit at each cycle, so you
should clock the clksignal 31 cycles to read out the 32 bits of the shift
register.
.regout (<registered
output>)
Output
Output
This signal is for cycloneiiils_crcblockonly. This output signal is
synchronized to the internal oscillator of the device (80-MHz internal
oscillator), and not to the clkport. The signal asserts high for one clock
cyclone every time an error detection cyclone completes.
.cyclecomplete (<cyclone
complete indicator
output>)
Recovering from CRC Errors
The system that the Altera FPGA resides in must control device reconfiguration. After
detecting an error on the CRC_ERRORpin, strobing the nCONFIGlow directs the system
to perform the reconfiguration at a time when it is safe for the system to reconfigure
the FPGA.
When the data bit is rewritten with the correct value by reconfiguring the device, the
device functions correctly.
While soft errors are uncommon in Altera devices, certain high-reliability applications
might require a design to account for these errors.
Document Revision History
Table 11–9 lists the revision history for this document.
Table 11–9. Document Revision History (Part 1 of 2)
Date
Version
2.3
Changes
■ Updated “User Mode Error Detection” on page 11–2.
■ Update hyperlinks.
December 2011
December 2009
■ Minor text edits.
2.2
Minor changes to the text.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 11: SEU Mitigation in the Cyclone III Device Family
11–11
Document Revision History
Table 11–9. Document Revision History (Part 2 of 2)
Date
July 2009
Version
Changes
Made minor correction to the part number.
2.1
■ Updated chapter part number.
■ Updated “Introduction” on page 11–1.
June 2009
2.0
■ Updated Table 11–6 on page 11–6 and Table 11–8 on page 11–9.
■ Updated Figure 11–2 on page 11–7.
■ Updated “Accessing Error Detection Block Through User Logic” on page 11–8.
■ Added chapter “Accessing Error Detection Block through User Logic” to document.
■ Updated chapter to new template.
October 2008
1.3
May 2008
July 2007
March 2007
1.2
1.1
1.0
■ Updated Table 11-2.
■ Added chapter TOC to document.
Initial release.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
11–12
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Document Revision History
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
12. IEEE 1149.1 (JTAG) Boundary-Scan
Testing for the Cyclone III Device Family
December 2011
CIII51014-2.3
CIII51014-2.3
This chapter provides guidelines on using the IEEE Std. 1149.1 boundary-scan test
(BST) circuitry in Cyclone® III device family (Cyclone III and Cyclone III LS devices).
BST architecture tests pin connections without using physical test probes, and
captures functional data while a device is operating normally. Boundary-scan cells
(BSCs) in a device can force signals onto pins or capture data from pin or logic array
signals. Forced test data is serially shifted into the boundary-scan cells. Captured data
is serially shifted out and externally compared to expected results.
This chapter contains the following sections:
■
■
■
■
■
“IEEE Std. 1149.1 BST Architecture” on page 12–1
“IEEE Std. 1149.1 BST Operation Control” on page 12–2
“I/O Voltage Support in a JTAG Chain” on page 12–5
“Guidelines for IEEE Std. 1149.1 BST” on page 12–6
“Boundary-Scan Description Language Support” on page 12–7
IEEE Std. 1149.1 BST Architecture
Cyclone III device family operating in the IEEE Std. 1149.1 BST mode use four
required pins:
■
■
■
■
TDI
TDO
TMS
TCK
The TCKpin has an internal weak pull-down resistor, while the TDIand TMSpins have
weak internal pull-up resistors. The TDOoutput pin and all the JTAG input pins are
powered by the VCCIO supply of bank 1A. All user I/O pins are tri-stated during JTAG
configuration.
1
For recommendations on how to connect a JTAG chain with multiple voltages across
the devices in the chain, refer to “I/O Voltage Support in a JTAG Chain” on page 12–5.
f
For more information about the description and functionality of all JTAG pins,
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)
controller, refer to AN39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 1
December 2011
Subscribe
12–2
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
IEEE Std. 1149.1 BST Operation Control
IEEE Std. 1149.1 BST Operation Control
Table 12–1 lists the boundary-scan register length for devices in Cyclone III device
family.
Table 12–1. Boundary-Scan Register Length for Cyclone III Device Family
Boundary-Scan Register
Length
Family
Device
EP3C5
EP3C10
603
603
EP3C16
1,080
732
EP3C25
Cyclone III
EP3C40
1,632
1,164
1,314
1,620
1,314
1,314
1,314
1,314
EP3C55
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Table 12–2 lists the IDCODEinformation for devices in Cyclone III device family.
Table 12–2. Device IDCODE for Cyclone III Device Family
(1)
IDCODE (32 Bits)
Family
Device
ManufacturerIdentity
(11 Bits)
(2)
Version (4 Bits) Part Number (16 Bits)
LSB (1 Bit)
EP3C5
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010 0000 1111 0001
0010 0000 1111 0001
0010 0000 1111 0010
0010 0000 1111 0011
0010 0000 1111 0100
0010 0000 1111 0101
0010 0000 1111 0110
0010 0000 1111 0111
0010 0111 0000 0001
0010 0111 0000 0000
0010 0111 0000 0011
0010 0111 0000 0010
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
1
1
1
1
1
1
1
1
1
1
1
1
EP3C10
EP3C16
EP3C25
Cyclone III
EP3C40
EP3C55
EP3C80
EP3C120
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
Cyclone III LS
Notes to Table 12–2:
(1) The MSB is on the left.
(2) The LSB of the IDCODEis always 1.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
12–3
IEEE Std. 1149.1 BST Operation Control
Cyclone III device family supports the IEEE Std. 1149.1 (JTAG) instructions as listed in
Table 12–3.
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern to be output at the device pins. Also used by the SignalTap® II
embedded logic analyzer.
SAMPLE/PRELOAD
00 0000 0101
Allows the external circuitry and board-level interconnects to be tested
by forcing a test pattern at the output pins and capturing test results at
the input pins.
(1)
EXTEST
BYPASS
00 0000 1111
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation.
11 1111 1111
00 0000 0111
00 000 0110
Selects the 32-bit USERCODEregister and places it between the TDIand
USERCODE
IDCODE
TDOpins, allowing the USERCODEto be serially shifted out of TDO
Selects the IDCODEregister and places it between TDIand TDO
allowing the IDCODEto be serially shifted out of TDO IDCODEis the
.
,
.
default instruction at power up and in TAP RESETstate.
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation, while tri-stating all of
the I/O pins.
HIGHZ
CLAMP
00 0000 1011
00 0000 1010
—
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through selected devices to
adjacent devices during normal device operation while holding I/O pins
to a state defined by the data in the boundary scan register.
Used when configuring Cyclone III device family using the JTAG port
with a USB-Blaster™ ByteBlaster™ II, MasterBlaster™ or ByteBlasterMV™
download cable, or when using a Jam File, or JBC File via an embedded
processor.
ICR Instructions
PULSE_NCONFIG
Emulates pulsing the nCONFIGpin low to trigger reconfiguration even
though the physical pin is unaffected.
00 0000 0001
00 0000 1101
Allows I/O reconfiguration through JTAG ports using the IOCSRfor
JTAG testing. This is executed after or during configurations. nSTATUS
pin must go high before you can issue the CONFIG_IOinstruction.
(2)
CONFIG_IO
Allows CLKUSRpin signal to replace the internal oscillator as the
configuration clock source.
(2)
EN_ACTIVE_CLK
01 1110 1110
10 1110 1110
10 1101 0000
10 1011 0000
Allows you to revert the configuration clock source from CLKUSRpin
signal set by EN_ACTIVE_CLKback to the internal oscillator.
(2)
DIS_ACTIVE_CLK
Places the active configuration mode controllers into idle state prior to
CONFIG_IOto configure the IOCSRor perform board level testing.
(2)
ACTIVE_DISENGAGE
This instruction might be used in AS and AP configuration schemes to
re-engage the active controller.
(2)
ACTIVE_ENGAGE
Places the 22-bit active boot address register between the TDIand TDO
pins, allowing a new active boot address to be serially shifted into TDI
and into the active parallel (AP) flash controller. In remote system
upgrade, the PFC_BOOT_ADDRinstruction sets the boot address for the
factory configuration.
(2), (3)
APFC_BOOT_ADDR
10 0111 0000
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
12–4
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
IEEE Std. 1149.1 BST Operation Control
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 2 of 2)
JTAG Instruction
Instruction Code
Description
Enables access to all other JTAG instructions (other than BYPASS
,
SAMPLE/PRELOADand EXTESTinstructions, which are supported upon
power up). This instruction also clears the device configuration data
and advanced encryption standard (AES) volatile key.
(4)
FACTORY
10 1000 0001
Used to enter and store the security key into volatile registers. When
this instruction is executed, TDIis connected to a 512-bit volatile key
scan chain. TDOis not connected to the end of this scan chain.
(4)
(4)
KEY_PROG_VOL
KEY_CLR_VREG
01 1010 1101
00 0010 1001
Clears the volatile verify register which signifies the validity of the
volatile keys stored in the registers. You must clear the volatile verify
register by issuing this command whenever you attempt to program a
new volatile key. This instruction must be asserted for at least 10 TCK
cycles.
Notes to Table 12–3:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ
(2) For more information about how to use CONFIG_IO
,
CLAMP, and EXTEST
.
,
EN_ACTIVE_CLK
,
DIS_ACTIVE_CLK
,
ACTIVE_DISENGAGE, ACTIVE_ENGAGEand
APFC_BOOT_ADDRinstructions for Cyclone III device family, refer to the Configuration, Design Security, and Remote System Upgrades in
Cyclone III Devices chapter.
(3) APFC_BOOT_ADDRinstruction is not supported in Cyclone III LS devices.
(4) For Cyclone III LS devices only. For more information about how to program the security key into the volatile registers, refer to the
Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices chapter.
The IEEE Std. 1149.1 BST circuitry is enabled upon device power-up. You can perform
BST on Cyclone III device family before, after, and during configuration. Cyclone III
device family supports the BYPASS, IDCODEand SAMPLEinstructions during
configuration without interrupting configuration. To send all other JTAG instructions,
interrupt the configuration using the CONFIG_IOinstruction except for active
configuration schemes in which the ACTIVE_DISENGAGEinstruction is used instead.
The CONFIG_IOinstruction allows you to configure I/O buffers via the JTAG port, and
when issued, interrupts configuration. This instruction allows you to perform board-
level testing prior to configuring Cyclone III device family. Alternatively, you can wait
for the configuration device to complete configuration. After configuration is
interrupted and JTAG BST is complete, you must reconfigure the part via JTAG
(PULSE_NCONFIGinstruction) or by pulsing nCONFIGlow.
1
When you perform JTAG boundary-scan testing before configuration, the nCONFIGpin
must be held low.
f
For more information about the following topics, refer to AN39: IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices:
■
■
■
■
■
TAP controller state-machine
Timing requirements for IEEE Std. 1149.1 signals
Instruction mode
Mandatory JTAG instructions (SAMPLE
/
PRELOAD
, EXTESTand BYPASS)
Optional JTAG instructions (IDCODE
,
USERCODE CLAMPand HIGHZ)
,
The following information is only applicable to Cyclone III LS devices:
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
12–5
I/O Voltage Support in a JTAG Chain
■
Only the three mandatory JTAG 1149.1 JTAG instructions (BYPASS
,
SAMPLE/PRELOAD
,
EXTEST) and the FACTORYprivate instruction are supported from
the JTAG pins upon power up. The FACTORYinstruction (instruction code:
10 1000 0001) must be issued before the device starts loading the core
configuration data to enable access to all other JTAG instructions. This instruction
also clears the device configuration data and AES volatile key.
■
■
IDCODEinstruction is not supported upon power-up, prior to issuing the FACTORY
instruction. However, it is the default instruction when the TAP controller is in the
reset state. Without loading any instructions, you can go to the Shift_DRstate and
shift out the JTAG Device ID.
IDCODE, CONFIG_IO, ACTIVE_DISENGAGE, HIGHZ, CLAMP, USERCODEand PULSE_NCONFIG
instructions are supported, provided that the FACTORYinstruction is executed.
I/O Voltage Support in a JTAG Chain
A JTAG chain can contain several different devices. However, you must be cautious if
the chain contains devices that have different VCCIO levels. The output voltage level of
the TDOpin must meet the specifications of the TDIpin it drives. For Cyclone III device
family, the TDOpin is powered by the VCCIO power supply. Because the VCCIO supply is
3.3 V, the TDOpin drives out 3.3 V.
Devices can interface with each other although they might have different VCCIO levels.
For example, a device with a 3.3-V TDOpin can drive to a device with a 5.0-V TDIpin
because 3.3 V meets the minimum TTL-level VIH for the 5.0-V TDIpin. JTAG pins on
Cyclone III device family can support the input levels of VCCIO of bank 1A.
1
For multiple devices in a JTAG chain with 3.0-V or 3.3-V I/O standard, you must
connect a 25- series resistor on a TDOpin driving a TDIpin.
You can also interface the TDIand TDOlines of the devices that have different VCCIO
levels by inserting a level shifter between the devices. If possible, the JTAG chain must
be built in such a way that a device with a higher VCCIO level drives to a device with
an equal or lower VCCIO level. This way, a level shifter may be required only to shift
the TDOlevel to a level acceptable to the JTAG tester.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
12–6
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
Guidelines for IEEE Std. 1149.1 BST
Figure 12–1 shows the JTAG chain of mixed voltages and how a level shifter is
inserted in the chain.
Figure 12–1. JTAG Chain of Mixed Voltages
Must be
3.3 V
tolerant
TDI
3.3 V
2.5 V
V
CCIO
V
CCIO
Tester
TDO
1.5 V
1.8 V
V
CCIO
Level
Shifter
V
CCIO
Shift TDO to
level accepted by
tester if necessary
Must be
1.8 V
tolerant
Must be
2.5 V
tolerant
Guidelines for IEEE Std. 1149.1 BST
Use the following guidelines when performing BST with IEEE Std. 1149.1 devices:
■
If the 10 bit checkerboard pattern (1010101010) does not shift out of the instruction
register via the TDOpin during the first clock cycle of the SHIFT_IRstate, the TAP
controller did not reach the proper state. To solve this problem, try one of the
following procedures:
■
Verify that the TAP controller has reached the SHIFT_IRstate correctly. To
advance the TAP controller to the SHIFT_IRstate, return to the RESETstate and
send the code 01100to the TMSpin.
■
Check the connections to the VCC, GND, JTAG, and dedicated configuration pins
on the device.
■
Perform a SAMPLE/PRELOADtest cycle prior to the first EXTESTtest cycle to ensure
that known data is present at the device pins when you enter the EXTESTmode. If
the OEJupdate register contains a 0, the data in the OUTJupdate register is driven
out. The state must be known and correct to avoid contention with other devices in
the system.
■
■
Do not perform EXTESTtesting during ICR. This instruction is supported before or
after ICR, but not during ICR. Use the CONFIG_IOinstruction to interrupt
configuration and then perform testing, or wait for configuration to complete.
If testing is performed before configuration, hold the nCONFIGpin low.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
12–7
Boundary-Scan Description Language Support
c
You must not invoke the following private instructions at any instance because these
instructions can potentially damage the device, rendering the device useless:
■
■
■
1000010000
1001000000
1011100000
Boundary-Scan Description Language Support
The boundary-scan description language (BSDL), a subset of VHDL, provides a
syntax that allows you to describe the features of an IEEE Std. 1149.1 BST-capable
device that can be tested. To download BSDL files for IEEE Std. 1149.1-compliant
Cyclone III device family, visit the Altera Download Center.
1
BSDL files for IEEE std. 1149.1-compliant Cyclone III LS devices can also be generated
using version 9.0 and later of the Quartus II software.
To perform BST on a configured device, a post configuration BSDL file that is
customized to your design is required. Post configuration BSDL file generation with
BSDL Customizer script (available on the Altera Download Center) is for Cyclone III
devices only.
Use version 9.0 and later of the Quartus II software to create a post configuration
BSDL file for Cyclone III LS devices.
f
For information on the procedures to generate the generic and post configuration
BSDL files with Quartus II software, visit the Altera Download Center.
Document Revision History
Table 12–4 lists the revision history for this document.
Table 12–4. Document Revision History (Part 1 of 2)
Date
Version
Changes
■ Updated “IEEE Std. 1149.1 BST Architecture” on page 12–1 and “I/O Voltage Support in a
JTAG Chain” on page 12–5.
December 2011
2.3
■ Minor text edits.
December 2009
July 2009
2.2
2.1
Minor changes to the text.
Made minor correction to the part number.
■ Updated “Introduction” on page 12–1, “IEEE Std. 1149.1 BST Architecture” on
page 12–1, “IEEE Std. 1149.1 BST Operation Control” on page 12–2, “Guidelines for IEEE
Std. 1149.1 BST” on page 12–6, and “Boundary-Scan Description Language Support” on
page 12–7.
June 2009
2.0
■ Updated Table 12–1 on page 12–2, Table 12–2 on page 12–2, and Table 12–3 on
page 12–3.
October 2008
May 2008
1.3
1.2
Updated chapter to new template.
Minor textual changes.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
12–8
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
Document Revision History
Table 12–4. Document Revision History (Part 2 of 2)
Date
Version
Changes
■ Updated “IEEE Std.1149.1 Boundary-Scan Register” section.
■ Updated IDCODE information and removed SignalTap II instructions in Table 12-4.
■ Updated “BST for Configured Devices” section.
July 2007
1.1
■ Added a guideline to “Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing” section.
■ Added chapter TOC and “Referenced Documents” section.
Initial release.
March 2007
1.0
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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This chapter provides additional information about the document and Altera.
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Initial Capital Letters
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Quotation marks indicate references to sections in a document and titles of
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Meaning
Indicates signal, port, register, bit, block, and primitive names. For example, data1
tdi, and input. The suffix denotes an active-low signal. For example, resetn
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,
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.
Courier type
.
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r
An angled arrow instructs you to press the Enter key.
1., 2., 3., and
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such as the steps listed in a procedure.
a., b., c., and so on
■
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The hand points to information that requires special attention.
1
h
The question mark directs you to a software help system with related information.
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f
m
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The envelope links to the Email Subscription Management Center page of the Altera
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Document last updated for Altera Complete Design Suite version:
Document publication date:
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Cyclone III Device Handbook
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Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Chapter 1. Cyclone III Device Datasheet
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Embedded Multiplier Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Configuration and JTAG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
High-Speed I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–22
Duty Cycle Distortion Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25
OCT Calibration Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25
IOE Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32
Chapter 2. Cyclone III LS Device Datasheet
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Embedded Multiplier Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Configuration and JTAG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Duty Cycle Distortion Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
OCT Calibration Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
IOE Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
iv
Contents
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter Revision Dates
The chapters in this document, Cyclone III Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1. Cyclone III Device Datasheet
Revised: July 2012
Part Number: CIII52001-3.5
Chapter 2. Cyclone III LS Device Datasheet
Revised:
July 2012
Part Number: CIII52002-1.4
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
vi
Chapter Revision Dates
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
1. Cyclone III Device Datasheet
July 2012
CIII52001-3.5
CIII52001-3.5
This chapter describes the electric characteristics, switching characteristics, and I/O
timing for Cyclone® III devices. A glossary is also included for your reference.
Electrical Characteristics
The following sections provide information about the absolute maximum ratings,
recommended operating conditions, DC characteristics, and other specifications for
Cyclone III devices.
Operating Conditions
When Cyclone III devices are implemented in a system, they are rated according to a
set of defined parameters. To maintain the highest possible performance and
reliability of Cyclone III devices, system designers must consider the operating
requirements in this document. Cyclone III devices are offered in commercial,
industrial, and automotive grades. Commercial devices are offered in –6 (fastest), –7,
and –8 speed grades. Industrial and automotive devices are offered only in –7 speed
grade.
1
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with “C” prefix, industrial with “I” prefix, and
automotive with “A” prefix. Commercial devices are therefore indicated as C6, C7,
and C8 per respective speed grades. Industrial and automotive devices are indicated
as I7 and A7, respectively.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Cyclone III
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Table 1–1 lists the absolute
maximum ratings for Cyclone III devices.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 2
July 2012
Subscribe
1–2
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
1
Conditions beyond those listed in Table 1–1 cause permanent damage to the device.
Additionally, device operation at the absolute maximum ratings for extended periods
of time has adverse effects on the device.
(1)
Table 1–1. Cyclone III Devices Absolute Maximum Ratings
Symbol
VCCINT
Parameter
Supply voltage for internal logic
Supply voltage for output buffers
Min
–0.5
–0.5
Max
1.8
Unit
V
VCCIO
3.9
V
Supply voltage (analog) for phase-locked loop
(PLL) regulator
VCCA
–0.5
3.75
V
VCCD_PLL
VI
Supply voltage (digital) for PLL
DC input voltage
–0.5
–0.5
–25
1.8
3.95
40
V
V
IOUT
DC output current, per pin
mA
Electrostatic discharge voltage using the human
body model
VESDHBM
VESDCDM
—
—
2000
500
V
V
Electrostatic discharge voltage using the
charged device model
TSTG
TJ
Storage temperature
–65
–40
150
125
°C
°C
Operating junction temperature
Note to Table 1–1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the
power supply.
Maximum Allowed Overshoot or Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 1–2 and
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods
shorter than 20 ns. Table 1–2 lists the maximum allowed input overshoot voltage and
the duration of the overshoot voltage as a percentage over the lifetime of the device.
The maximum allowed overshoot duration is specified as percentage of high-time
over the lifetime of the device.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–3
Electrical Characteristics
1
A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to
4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for device lifetime
of 10 years, this amounts to 10.74/10ths of a year.
Table 1–2. Cyclone III Devices Maximum Allowed Overshoot During Transitions over a 10-Year
(1)
Time Frame
Symbol
Parameter
Condition
VI = 3.95 V
VI = 4.0 V
Overshoot Duration as % of High Time
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
%
100
95.67
55.24
31.97
18.52
10.74
6.23
VI = 4.05 V
VI = 4.10 V
VI = 4.15 V
VI = 4.20 V
VI = 4.25 V
VI = 4.30 V
VI = 4.35 V
VI = 4.40 V
VI = 4.45 V
VI = 4.50 V
VI = 4.60 V
VI = 4.70 V
AC Input
Voltage
Vi
3.62
2.1
1.22
0.71
0.41
0.14
0.047
Note to Table 1–2:
(1) Figure 1–1 shows the methodology to determine the overshoot duration. In the example in Figure 1–1, overshoot
voltage is shown in red and is present on the input pin of the Cyclone III device at over 4.1 V but below 4.2 V. From
Table 1–1, for an overshoot of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over
a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes the
device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and
situations in which the device is in an idle state, lifetimes are increased.
Figure 1–1 shows the methodology to determine the overshoot duration.
Figure 1–1. Cyclone III Devices Overshoot Duration
4.2 V
4.1 V
3.3 V
ΔT
T
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–4
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone III devices. The steady-state voltage and current values expected from
Cyclone III devices are provided in Table 1–3. All supplies must be strictly monotonic
without plateaus.
(1), (2)
Table 1–3. Cyclone III Devices Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(3)
VCCINT
Supply voltage for internal logic
—
1.15
1.2
1.25
V
Supply voltage for output buffers, 3.3-V
operation
—
—
—
—
—
—
—
3.135
2.85
3.3
3
3.465
3.15
V
V
V
V
V
V
V
Supply voltage for output buffers, 3.0-V
operation
Supply voltage for output buffers, 2.5-V
operation
2.375
1.71
2.5
1.8
1.5
1.2
2.5
2.625
1.89
(3), (4)
VCCIO
Supply voltage for output buffers, 1.8-V
operation
Supply voltage for output buffers, 1.5-V
operation
1.425
1.14
1.575
1.26
Supply voltage for output buffers, 1.2-V
operation
Supply (analog) voltage for PLL
regulator
(3)
VCCA
2.375
2.625
(3)
VCCD_PLL
Supply (digital) voltage for PLL
Input voltage
—
1.15
–0.5
0
1.2
—
—
—
—
—
—
1.25
3.6
V
V
VI
—
VO
Output voltage
—
VCCIO
85
V
For commercial use
For industrial use
For extended temperature
For automotive use
Standard power-on reset
0
°C
°C
°C
°C
–40
–40
–40
100
125
125
TJ
Operating junction temperature
50 µs
50 µs
—
—
—
—
50 ms
3 ms
10
—
—
(5)
(POR)
tRAMP
Power supply ramp time
(6)
Fast POR
Magnitude of DC current across
PCI-clamp diode when enabled
IDiode
—
mA
Notes to Table 1–3:
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and
must be powered up and powered down at the same time.
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.
(3) The VCC must rise monotonically.
(4) All input buffers are powered by the VCCIO supply.
(5) POR time for Standard POR ranges between 50–200 ms. Each individual power supply should reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges between 3–9 ms. Each individual power supply should reach the recommended operating range within 3 ms.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–5
Electrical Characteristics
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone III devices.
Supply Current
Standby current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Use the Excel-based early
power estimator (EPE) to get the supply current estimates for your design because
these currents vary largely with the resources used. Table 1–4 lists I/O pin leakage
current for Cyclone III devices.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Table 1–4. Cyclone III Devices I/O Pin Leakage Current (1), (2)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
II
Input pin leakage current
VI = 0 V to VCCIOMAX
–10
—
10
A
Tristated I/O pin leakage
current
IOZ
VO = 0 V to VCCIOMAX
–10
—
10
A
Notes to Table 1–4:
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all
CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
V
(2) 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the
observed when the diode is on.
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–5 lists bus hold specifications for Cyclone III devices.
(1)
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 1 of 2)
V
CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min
Max Min Max Min Max Min Max Min Max
Bus-hold
low,
sustaining
current
VIN > VIL
(maximum)
8
—
—
12
—
—
30
—
—
50
—
—
70
—
—
70
—
—
A
A
Bus-hold
high,
sustaining
current
VIN < VIL
(minimum)
–8
–12
–30
–50
–70
–70
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–6
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
(1)
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 2 of 2)
V
CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min
Max Min Max Min Max Min Max Min Max
Bus-hold
low,
overdrive
current
0 V < VIN < VCCIO
—
125
—
—
175
—
—
200
—
—
300
—
500
—
500
A
Bus-hold
high,
overdrive
current
0 V < VIN < VCCIO
—
–125
–175
–200
–300
1.7
—
–500
2
—
–500 A
Bus-holdtrip
point
—
0.3
0.9 0.375 1.125 0.68 1.07 0.7
0.8
0.8
2
V
Note to Table 1–5:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
OCT Specifications
Table 1–6 lists the variation of OCT without calibration across process, temperature,
and voltage.
Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description
V
CCIO (V)
Unit
Commercial
Max
Industrial and Automotive
Max
3.0
2.5
1.8
1.5
1.2
30
30
40
40
50
50
50
%
%
%
%
%
Series OCT without
calibration
+40
+50
+50
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
Table 1–7 lists the OCT calibration accuracy at device power-up.
Table 1–7. Cyclone III Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description
VCCIO (V)
Unit
Industrial and Automotive
Max
Commercial Max
3.0
2.5
1.8
1.5
1.2
10
10
10
10
10
10
10
10
10
10
%
%
%
%
%
Series OCT with
calibration at device
power-up
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–7
Electrical Characteristics
The OCT resistance may vary with the variation of temperature and voltage after
calibration at device power-up. Use Table 1–8 and Equation 1–1 to determine the final
OCT resistance considering the variations after calibration at device power-up.
Table 1–8 lists the change percentage of the OCT resistance with voltage and
temperature.
Table 1–8. Cyclone III Devices OCT Variation After Calibration at Device Power-Up
Nominal Voltage
dR/dT (%/°C)
0.262
dR/dV (%/mV)
–0.026
3.0
2.5
1.8
1.5
1.2
0.234
–0.039
0.219
–0.086
0.199
–0.136
0.161
–0.288
(1), (2), (3), (4), (5), (6)
Equation 1–1.
(7)
RV = (V2 – V1) × 1000 × dR/dV
(8)
RT = (T2 – T1) × dR/dT
(9)
For Rx < 0; MFx = 1/ (|Rx|/100 + 1)
(10)
For Rx > 0; MFx = Rx/100 + 1
(11)
MF = MFV × MFT
(12)
Rfinal = Rinitial × MF
Notes to Equation 1–1:
(1) T2 is the final temperature.
(2) T1 is the initial temperature.
(3) MF is multiplication factor.
(4) Rfinal is final resistance.
(5) Rinitial is initial resistance.
(6) Subscript × refers to both V and T.
(7) RV is variation of resistance with voltage.
(8) RT is variation of resistance with temperature.
(9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
(10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
(11) V2 is final voltage.
(12) V1 is the initial voltage.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–8
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Example 1–1 shows you the example to calculate the change of 50 I/O impedance
from 25°C at 3.0 V to 85°C at 3.15 V:
Example 1–1.
RV = (3.15 – 3) × 1000 × –0.026 = –3.83
RT = (85 – 25) × 0.262 = 15.72
Because RV is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because RT is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
R
final = 50 × 1.114 = 55.71
Pin Capacitance
Table 1–9 lists the pin capacitance for Cyclone III devices.
Table 1–9. Cyclone III Devices Pin Capacitance
Typical – Typical –
Symbol
Parameter
Unit
QFP
FBGA
CIOTB
CIOLR
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
7
6
5
pF
pF
7
Input capacitance on left/right I/O pins with dedicated
LVDS output
CLVDSLR
8
7
pF
pF
pF
CVREFLR
Input capacitance on left/right dual-purpose VREFpin
when used as VREF or user I/O pin
21
21
(1)
CVREFTB
Input capacitance on top/bottom dual-purpose VREFpin
when used as VREF or user I/O pin
(2)
(2)
23
23
(1)
Input capacitance on top/bottom dedicated clock input
pins
CCLKTB
CCLKLR
7
6
6
5
pF
pF
Input capacitance on left/right dedicated clock input pins
Notes to Table 1–9:
(1) When VREFpin is used as regular input or output, a reduced performance of toggle rate and tCO is expected due to
higher pin capacitance.
(2) CVREFTB for EP3C25 is 30 pF.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–9
Electrical Characteristics
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 1–10 lists the weak pull-up and pull-down resistor values for Cyclone III
devices.
(1)
Table 1–10. Cyclone III Devices Internal Weak Pull-Up and Weak Pull-Down Resistor
Symbol
Parameter
Conditions
Min
7
Typ
25
28
35
57
82
143
19
22
25
35
50
Max
41
Unit
(2), (3)
VCCIO = 3.3 V 5%
k
k
k
k
k
k
k
k
k
k
k
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(4)
V
V
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
7
47
Value of I/O pin pull-up resistor before
and during configuration, as well as
user mode if the programmable
pull-up resistor option is enabled
8
61
R_PU
VCCIO = 1.8 V 5%
10
13
19
6
108
163
351
30
V
V
V
V
V
V
V
CCIO = 1.5 V 5%
CCIO = 1.2 V 5%
CCIO = 3.3 V 5%
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
CCIO = 1.8 V 5%
CCIO = 1.5 V 5%
(4)
6
36
Value of I/O pin pull-down resistor
before and during configuration
(4)
R_PD
6
43
(4)
7
71
(4)
8
112
Notes to Table 1–10:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pin. Weak pull-down feature is only available for JTAG
TCK.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(3) R_PU = (VCCIO – VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC – 5%;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Hot Socketing
Table 1–11 lists the hot-socketing specifications for Cyclone III devices.
Table 1–11. Cyclone III Devices Hot-Socketing Specifications
Symbol
IIOPIN(DC)
Parameter
Maximum
DC current per I/O pin
AC current per I/O pin
300 A
(1)
IIOPIN(AC)
8 mA
Note to Table 1–11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C
dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–10
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,
nCE
,
CONF_DONE, and DCLKpins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate.
Table 1–12 lists the hysteresis specifications across supported VCCIO range for Schmitt
trigger inputs in Cyclone III devices.
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices
Symbol
Parameter
Conditions
Minimum
200
Typical
—
Maximum
Unit
mV
mV
mV
mV
VCCIO = 3.3 V
—
—
—
—
V
V
CCIO = 2.5 V
CCIO = 1.8 V
200
—
Hysteresis for Schmitt trigger
input
VSCHMITT
140
—
VCCIO = 1.5 V
110
—
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O
standard specifications for Cyclone III devices.
(1), (2)
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications
VCCIO (V)
VIL (V)
VIH (V)
Max
VOL (V)
VOH (V)
IOL
IOH
I/O Standard
(mA)
(mA)
Min
3.135
3.135
2.85
Typ
3.3
3.3
3.0
3.0
Max
3.465
3.465
Min
Max
0.8
0.8
0.8
0.8
Min
1.7
1.7
1.7
1.7
Max
0.45
0.2
Min
2.4
(3)
3.3-V LVTTL
—
—
3.6
4
2
–4
–2
(3)
(3)
3.3-V LVCMOS
3.6
VCCIO – 0.2
2.4
(3)
3.0-V LVTTL
3.15 –0.3
3.15 –0.3
VCCIO + 0.3
VCCIO + 0.3
0.45
0.2
4
–4
3.0-V LVCMOS
2.85
VCCIO – 0.2
0.1
–0.1
2.5-V LVTTL and
LVCMOS
2.375
1.71
1.425
1.14
2.85
2.85
2.5
1.8
1.5
1.2
3.0
3.0
2.625 –0.3
1.89 –0.3
1.575 –0.3
1.26 –0.3
0.7
1.7
3.6
0.4
2.0
1
2
–1
–2
(3)
1.8-V LVTTL and
LVCMOS
0.35 * 0.65 *
VCCIO VCCIO
VCCIO
0.45
–
2.25
0.45
0.35 * 0.65 *
VCCIO VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI
VCCIO + 0.3
VCCIO + 0.3
2
–2
0.35 * 0.65 *
VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
VCCIO
0.3 *
VCCIO
0.5 *
VCCIO
3.15
3.15
—
—
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO
1.5
1.5
–0.5
–0.5
0.35*
VCCIO
0.5 *
VCCIO
3.0-V PCI-X
Notes to Table 1–13:
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/O Standard”
in “Glossary” on page 1–27.
(2) AC load CL = 10 pF.
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
1–11
Max
(1)
Table 1–14. Cyclone III Devices Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
(2)
V
CCIO (V)
Typ
VREF (V)
Typ
VTT (V)
I/O
Standard
Min
Max
Min
Max
Min
Typ
SSTL-2
Class I, II
VREF
0.04
–
VREF
0.04
+
2.375 2.5 2.625
1.19
1.25
0.9
1.31
VREF
SSTL-18
Class I, II
VREF
0.04
–
VREF
0.04
+
1.7
1.8
1.8
1.9
0.833
0.85
0.71
0.969
0.95
0.79
VREF
0.9
HSTL-18
Class I, II
1.71
1.89
0.9
0.85
0.71
0.95
0.79
HSTL-15
Class I, II
1.425 1.5 1.575
0.75
0.75
(3)
(4)
(3)
(4)
(3)
(4)
0.48 * VCCIO
0.47 * VCCIO
0.5 * VCCIO
0.5 * VCCIO
0.52 * VCCIO
0.53 * VCCIO
HSTL-12
Class I, II
0.5 *
VCCIO
1.14
1.2
1.26
—
—
Notes to Table 1–14:
(1) For an explanation of terms used in Table 1–14, refer to “Glossary” on page 1–27.
(2) VTT of transmitting device must track VREF of the receiving device.
(3) Value shown refers to DC input reference voltage, VREF(DC)
(4) Value shown refers to AC input reference voltage, VREF(AC)
.
.
Table 1–15. Cyclone III Devices Single-Ended SSTL and HSTL I/O Standards Signal Specifications
VIL(DC) (V)
Min Max
VREF
VIH(DC) (V)
Max
VIL(AC) (V)
Min Max
VREF
VIH(AC) (V)
Min Max
VOL (V)
Max
VOH (V)
Min
I/O
IOL
IOH
Standard
(mA) (mA)
Min
SSTL-2
Class I
–
VREF
0.18
+
–
VREF
0.35
+
VTT
–
VTT +
0.57
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.1
16.4 –16.4
6.7 –6.7
13.4 –13.4
–8.1
0.18
0.35
0.57
SSTL-2
Class II
VREF
0.18
–
VREF
0.18
+
VREF
–
VREF
0.35
+
VTT
–
VTT +
0.76
—
0.35
0.76
SSTL-18
Class I
VREF
0.125
–
VREF
+
VREF
–
VREF
0.25
+
VTT
–
VTT
+
—
0.125
0.25
0.475
0.475
SSTL-18
Class II
VREF
0.125
–
VREF
+
VREF
–
VREF
0.25
+
VCCIO
–
—
0.28
0.4
0.4
0.4
0.4
0.125
0.25
0.28
HSTL-18
Class I
VREF
0.1
–
–
–
–
–
VREF
0.1
+
+
+
+
+
VREF
0.2
–
VREF
0.2
+
VCCIO
0.4
–
—
8
16
8
–8
–16
–8
HSTL-18
Class II
VREF
0.1
VREF
0.1
VREF
0.2
–
–
–
–
VREF
0.2
+
+
+
+
VCCIO
0.4
–
–
–
—
HSTL-15
Class I
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
16
8
–16
–8
HSTL-12
Class I
VREF
0.08
VREF
0.08
VREF
VREF
VCCIO
+
+
0.25 ×
VCCIO
0.75 ×
VCCIO
–0.15
–0.15
V
V
CCIO + 0.15 –0.24
CCIO + 0.15 –0.24
0.15
0.15
0.24
HSTL-12
Class II
VREF
0.08
–
VREF
0.08
+
VREF
–
VREF
+
VCCIO
0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
14
–14
0.15
0.15
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–12
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
f
For more illustrations of receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the High-Speed Differential Interfaces in
Cyclone III Devices chapter.
Table 1–16. Cyclone III Devices Differential SSTL I/O Standard Specifications (1)
VSwing(AC)
(V)
VCCIO (V)
VSwing(DC) (V)
VX(AC) (V)
Typ
VOX(AC) (V)
Typ
I/O Standard
Min Typ Max Min Max
Min
Max
Min Max
Min
Max
SSTL-2
Class I, II
V
+ 0.2
CCIO/2
VCCI
0.7
VCCIO/2 –
0.125
V
CCIO/2
2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2
VCCIO/2 –
—
—
—
—
+ 0.125
O
SSTL-18
Class I, II
V
CCIO/2
VCCI
0.5
VCCIO/2 –
0.125
VCCIO/2
+ 0.125
1.7
1.8 1.90 0.25 VCCIO
0.175
+ 0.175
O
Note to Table 1–16:
(1) Differential SSTL requires a VREF input.
Table 1–17. Cyclone III Devices Differential HSTL I/O Standard Specifications (1)
V
CCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
I/O Standard
Mi
Min Typ Max Min Max
Min
0.85
0.71
Max
0.95
0.79
Min
0.85
0.71
Max
0.95
0.79
Max
—
n
HSTL-18
Class I, II
1.71 1.8 1.89 0.2
1.425 1.5 1.575 0.2
—
—
—
—
—
—
—
0.4
HSTL-15
Class I, II
0.4
0.3
—
HSTL-12
Class I, II
0.52 *
VCCIO
0.48 *
VCCIO
0.52 *
VCCIO
0.48 *
VCCIO
1.14 1.2 1.26 0.16 VCCIO 0.48 * VCCIO
—
Note to Table 1–17:
(1) Differential HSTL requires a VREF input.
(1)
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
(Part 1 of 2)
VOD (mV)
Max Min Typ Max Min Typ Max
(2)
(3)
(3)
V
CCIO (V)
VID (mV)
VIcM (V)
VOS (V)
I/O
Standard
Min Typ Max
Min Max Min
Condition
0.05
DMAX500 Mbps 1.80
LVPECL
500 Mbps DMAX
700 Mbps
(Row I/Os) 2.375 2.5 2.625 100
—
—
—
0.55
1.80
1.55
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
1.05 DMAX > 700 Mbps
0.05
DMAX 500 Mbps 1.80
LVPECL
500 Mbps DMAX
700 Mbps
(Column
2.375 2.5 2.625 100
2.375 2.5 2.625 100
0.55
1.80
(4)
I/Os)
1.05
0.05
DMAX > 700 Mbps
1.55
DMAX 500 Mbps 1.80
LVDS (Row
I/Os)
500 Mbps DMAX
700 Mbps
0.55
1.05
1.80 247
1.55
600 1.125 1.25 1.375
DMAX > 700 Mbps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–13
Electrical Characteristics
(1)
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
(Part 2 of 2)
VOD (mV)
(2)
(3)
(3)
VCCIO (V)
VID (mV)
VIcM (V)
VOS (V)
I/O
Standard
Min Typ Max
Min Max Min
Condition
Max Min Typ Max Min Typ Max
0.05
DMAX 500 Mbps 1.80
LVDS
(Column
I/Os)
500 Mbps DMAX
700 Mbps
2.375 2.5 2.625 100
—
0.55
1.05
1.80 247
1.55
—
600 1.125 1.25 1.375
DMAX > 700 Mbps
BLVDS
(Row I/Os) 2.375 2.5 2.625 100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(5)
BLVDS
(Column
2.375 2.5 2.625 100
—
—
—
—
—
—
—
—
(5)
I/Os)
mini-LVDS
(Row I/Os) 2.375 2.5 2.625
—
—
—
—
—
—
—
300
300
600
600
1.0
1.0
0.5
0.5
0.5
0.5
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.5
1.5
1.4
1.4
(6)
mini-LVDS
(Column
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
—
—
—
—
—
(6)
I/Os)
RSDS®
(Row
100 200 600
100 200 600
100 200 600
100 200 600
I/Os) (6)
RSDS
(Column
(6)
I/Os)
PPDS®
(Row I/Os) 2.375 2.5 2.625
(6)
PPDS
(Column
2.375 2.5 2.625
(6)
I/Os)
Notes to Table 1–18:
(1) For an explanation of terms used in Table 1–18, refer to “Transmitter Output Waveform” in “Glossary” on page 1–27.
(2) VIN range: 0 V VIN 1.85 V.
(3) RL range: 90 RL 110 .
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.
(5) No fixed VIN, VOD, and VOS specifications for BLVDS. They are dependent on the system topology.
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–14
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Power Consumption
You can use the following methods to estimate power for a design:
■
the Excel-based EPE.
■
the Quartus II PowerPlay power analyzer feature.
The interactive Excel-based EPE is used prior to designing the device to get a
magnitude estimate of the device power. The Quartus II PowerPlay power analyzer
provides better quality estimates based on the specifics of the design after place-and-
route is complete. The PowerPlay power analyzer can apply a combination of user-
entered, simulation-derived, and estimated signal activities which, combined with
detailed circuit models, can yield very accurate power estimates.
f
For more information about power estimation tools, refer to the Early Power Estimator
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook.
Switching Characteristics
This section provides the performance characteristics of the core and periphery blocks
for Cyclone III devices. All data is final and is based on actual silicon characterization
and testing. These numbers reflect the actual performance of the device under
worst-case silicon process, voltage, and junction temperature conditions.
Core Performance Specifications
Clock Tree Specifications
Table 1–19 lists the clock tree specifications for Cyclone III devices.
Table 1–19. Cyclone III Devices Clock Tree Performance
Performance
Device
Unit
C6
C7
C8
EP3C5
500
500
500
500
500
500
437.5
437.5
437.5
437.5
437.5
437.5
437.5
437.5
402
402
402
402
402
402
402
402
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
500
(1)
EP3C120
Note to Table 1–19:
(1) EP3C120 offered in C7, C8, and I7 grades only.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–15
Switching Characteristics
PLL Specifications
Table 1–20 describes the PLL specifications for Cyclone III devices when operating in
the commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), and the automotive junction temperature range
(–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in
“Glossary” on page 1–27.
Table 1–20. Cyclone III Devices PLL Specifications (1)
(Part 1 of 2)
Parameter
Symbol
Min
5
Typ
—
—
—
—
—
—
Max
472.5
325
Unit
MHz
MHz
MHz
%
(2)
fIN
fINPFD
Input clock frequency
PFD input frequency
5
(3)
fVCO
PLL internal VCO operating range
600
40
—
—
1300
60
fINDUTY
Input clock duty cycle
Input clock cycle-to-cycle jitter for FINPFD 100 MHz
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz
0.15
750
UI
(4)
tINJITTER_CCJ
ps
f
OUT_EXT (external clock output)
PLL output frequency
—
—
472.5
MHz
(2)
PLL output frequency (–6 speed grade)
—
—
—
45
—
—
—
—
50
—
472.5
450
402.5
55
MHz
MHz
MHz
%
fOUT (to global clock)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
tOUTDUTY
tLOCK
Duty cycle for external clock output (when set to 50%)
Time required to lock from end of device configuration
1
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
tDLOCK
—
—
1
ms
Dedicated clock output period jitter
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
30
ps
mUI
ps
(5)
F
OUT 100 MHz
tOUTJITTER_PERIOD_DEDCLK
F
OUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
300
30
(5)
F
OUT 100 MHz
tOUTJITTER_CCJ_DEDCLK
F
OUT < 100 MHz
mUI
ps
Regular I/O period jitter
650
75
(5)
F
OUT 100 MHz
tOUTJITTER_PERIOD_IO
F
OUT < 100 MHz
mUI
ps
Regular I/O cycle-to-cycle jitter
650
(5)
F
OUT 100 MHz
tOUTJITTER_CCJ_IO
F
OUT < 100 MHz
—
—
10
—
—
—
75
50
—
mUI
ps
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
ns
SCANCLK
cycles
(6)
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
3.5
—
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–16
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–20. Cyclone III Devices PLL Specifications (1)
Symbol
(Part 2 of 2)
Parameter
Min
Typ
Max
Unit
fSCANCLK
scanclkfrequency
—
—
100
MHz
Notes to Table 1–20:
(1) VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
jitter of the PLL, when an input jitter of 30 ps is applied.
(6) With 100 MHz scanclkfrequency.
Embedded Multiplier Specifications
Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications
Resources Used
Performance
C7, I7, A7
Mode
9 × 9-bit
Unit
Number of Multipliers
C6
C8
1
1
340
300
250
260
MHz
MHz
multiplier
18 × 18-bit
multiplier
287
200
Memory Block Specifications
Table 1–22 describes the M9K memory block specifications for Cyclone III devices.
Table 1–22. Cyclone III Devices Memory Block Performance Specifications
Resources Used
Performance
Memory
Mode
M9K
LEs
C6
C7, I7, A7
C8
Unit
Memory
FIFO 256 × 36
47
0
1
1
1
1
315
315
315
315
274
274
274
274
238
238
238
238
MHz
MHz
MHz
MHz
Single-port 256 × 36
M9K Block
Simple dual-port 256 × 36 CLK
True dual port 512 × 18 single CLK
0
0
Configuration and JTAG Specifications
Table 1–23 lists the configuration mode specifications for Cyclone III devices.
Table 1–23. Cyclone III Devices Configuration Mode Specifications
Programming Mode
Passive Serial (PS)
DCLK Fmax
133
Unit
MHz
MHz
(1)
Fast Passive Parallel (FPP)
100
Note to Table 1–23:
(1) EP3C40 and smaller density members support 133 MHz.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–17
Switching Characteristics
Table 1–24 lists the active configuration mode specifications for Cyclone III devices.
Table 1–24. Cyclone III Devices Active Configuration Mode Specifications
Programming Mode
Active Parallel (AP)
Active Serial (AS)
DCLK Range
20 – 40
Unit
MHz
MHz
20 – 40
Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.
(1)
Table 1–25. Cyclone III Devices JTAG Timing Parameters
Symbol
tJCP
Parameter
Min
40
20
20
1
Max
—
—
—
—
—
—
15
15
15
—
—
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock period
tJCH
TCK clock high time
TCK clock low time
tJCL
tJPSU_TDI JTAG port setup time for TDI
tJPSU_TMS JTAG port setup time for TMS
3
tJPH
JTAG port hold time
10
—
—
—
5
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
Capture register hold time
10
—
—
—
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Notes to Table 1–25:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several system interfacing, for example, the high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using
the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds with typical DDR SDRAM memory interface setup. I/O using
general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are
capable of a typical 200 MHz interfacing frequency with a 10 pF load.
1
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–18
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
High-Speed I/O Specifications
Table 1–26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27.
(1), (2)
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
C6
C7, I7
C8, A7
Min Typ Max
Symbol
Modes
Unit
Min Typ Max Min Typ
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
180
180
180
180
180
360
360
360
360
360
360
360
55
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
fHSCLK
(input clock
frequency)
5
5
5
5
5
5
5
5
5
5
5
5
311
MHz
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
311
100
80
70
40
20
10
45
—
311 Mbps
311 Mbps
311 Mbps
311 Mbps
311 Mbps
311 Mbps
311
311
Device operation in
Mbps
311
311
311
tDUTY
55
55
%
TCCS
200
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%, CLOAD
5 pF
=
=
tRISE
tFALL
500
500
500
20 – 80%, CLOAD
5 pF
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
(3)
tLOCK
—
ms
Notes to Table 1–26:
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output
pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 1 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
Max
85
Min
5
Typ
—
—
—
—
—
—
Max
85
Min
5
Typ
—
—
—
—
—
—
Max
85
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
5
85
5
85
5
85
fHSCLK (input
clock
frequency)
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
170
5
170
5
170
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–19
Switching Characteristics
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 2 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
55
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
55
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
55
×10
×8
×7
×4
×2
×1
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
Device
operation in
Mbps
70
70
70
40
40
40
20
20
20
10
10
10
tDUTY
45
45
45
TCCS
—
200
—
200
—
200
ps
Output jitter
(peak to
peak)
—
—
—
—
500
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
tRISE
500
500
500
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(2)
tLOCK
ms
Notes to Table 1–27:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 1 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
200
200
200
200
200
400
400
400
400
400
400
400
55
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
f
HSCLK (input
clock
frequency)
5
5
5
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
311
100
80
70
40
20
10
45
—
311
311
311
Device
operation in
Mbps
311
311
311
311
311
311
311
311
tDUTY
55
55
TCCS
200
200
200
ps
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–20
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 2 of 2)
C6
C7, I7
Typ
C8, A7
Typ
Symbol
Modes
Unit
Min
Typ
Max
Min
Max
Min
Max
Output jitter
(peak to
peak)
—
—
—
500
—
—
500
—
—
550
ps
ps
20 – 80%,
tRISE
—
500
—
—
500
—
—
500
—
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(3)
tLOCK
ms
Notes to Table 1–28:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–21
Switching Characteristics
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications (1)
C6
C7, I7
Min
C8, A7
Min
Symbol
Modes
Unit
Min
5
Max
420
420
420
420
420
420
840
840
840
840
840
420
55
Max
370
370
370
370
370
402.5
740
740
740
740
740
402.5
55
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
5
5
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
HSIODR
tDUTY
TCCS
200
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
1
—
—
500
1
—
—
550
1
ps
(2)
tLOCK
ms
Notes to Table 1–29:
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 1 of 2)
C6
C7, I7
Min
C8, A7
Min
Symbol
Modes
Unit
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
Max
275
275
275
275
275
402.5
550
550
550
550
550
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
5
5
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
HSIODR
tDUTY
TCCS
200
200
200
ps
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–22
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 2 of 2)
C6
C7, I7
Min
C8, A7
Min
Symbol
Modes
Unit
Min
—
Max
500
1
Max
500
1
Max
550
1
Output jitter
(peak to peak)
—
—
—
—
—
—
ps
(2)
tLOCK
—
ms
Notes to Table 1–30:
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
(1)
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications
C6
C7, I7
Min
C8, A7
Symbol
Modes
Unit
Min
5
Max
437.5
437.5
437.5
437.5
437.5
437.5
875
Max
370
370
370
370
370
402.5
740
740
740
740
740
402.5
400
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
400
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
5
5
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
5
5
5
5
5
fHSCLK (input
clock frequency)
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
—
100
80
70
40
20
10
—
100
80
70
40
20
10
—
875
875
HSIODR
SW
875
875
437.5
400
Input jitter
tolerance
—
—
—
—
500
1
—
—
500
1
—
—
550
1
ps
(2)
tLOCK
ms
Notes to Table 1–31:
(1) LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
External Memory Interface Specifications
Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
f
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–23
Switching Characteristics
Table 1–32 lists the FPGA sampling window specifications for Cyclone III devices.
Table 1–32. Cyclone III Devices FPGA Sampling Window (SW) Requirement – Read Side (1)
Column I/Os Row I/Os
Wraparound Mode
Memory Standard
Setup
Hold
Setup
Hold
Setup
Hold
C6
C7
C8
I7
DDR2 SDRAM
580
585
785
550
535
735
690
700
805
640
650
755
850
870
905
800
820
855
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
705
675
900
650
620
845
770
795
910
715
740
855
985
970
930
915
1085
1030
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
785
800
720
740
990
930
915
870
855
1115
1185
1210
1055
1125
1150
1050
1065
1005
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
765
745
945
710
690
890
855
880
955
800
825
900
1040
1000
1130
985
945
1075
A7
DDR2 SDRAM
DDR SDRAM
805
880
745
820
1020
955
960
935
1145
1220
1250
1085
1160
1190
QDRII SRAM
1090
1030
1105
1045
Note to Table 1–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 1–33 lists the transmitter channel-to-channel skew specifications for Cyclone III
devices.
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1)
(Part 1 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory
Standard
I/O Standard
Lead
Lag
C6
Lead
Lag
Lead
Lag
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
790
870
750
860
780
830
380
490
320
350
410
510
790
870
750
860
780
830
380
490
320
350
410
510
890
970
850
960
880
930
480
590
420
450
510
610
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
C7
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–24
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1)
(Part 2 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory
I/O Standard
Standard
Lead
915
Lag
410
545
340
380
450
570
Lead
Lag
410
545
340
380
450
570
Lead
1015
1125
980
Lag
510
645
440
480
550
670
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
915
1025
880
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
1025
880
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1010
910
1010
910
1110
1010
1110
1010
1010
C8
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
I7
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
1140
1280
1110
1260
1140
1290
540
700
460
510
590
730
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
961
1076
924
431
572
357
399
473
599
A7
961
1076
924
431
572
357
399
473
599
1061
1176
1024
1161
1056
1161
531
672
457
499
573
699
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1061
956
1061
956
1061
1061
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
1092
1239
1061
1218
1092
1250
462
630
378
431
515
662
1092
1239
1061
1218
1092
1250
462
630
378
431
515
662
1192
1339
1161
1318
1192
1350
562
730
478
531
615
762
DDR2 SDRAM
(2)
DDR SDRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
QDRII SRAM
Notes to Table 1–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 1 of 2)
Parameter
Clock period jitter
Symbol
tJIT(per)
tJIT(cc)
Min
-125
-200
Max
125
200
Unit
ps
Cycle-to-cycle period jitter
ps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–25
Switching Characteristics
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 2 of 2)
Parameter
Duty cycle jitter
Symbol
Min
Max
Unit
tJIT(duty)
-150
150
ps
Notes to Table 1–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specifications
Table 1–35 lists the worst case duty cycle distortion for Cyclone III devices.
(1), (2)
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins
C6
C7, I7
Max
55
C8, A7
Symbol
Unit
Min
Max
Min
Min
45
Max
Output Duty Cycle
45
55
45
55
%
Notes to Table 1–35:
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
and general purpose I/O pins.
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
I/O standard and current strength.
OCT Calibration Timing Specification
Table 1–36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III devices.
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
(1)
Power-Up
Symbol
Description
Maximum
Unit
Duration of series OCT with
calibration at device power-up
tOCTCAL
20
µs
Notes to Table 1–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
Table 1–37 and Table 1–38 list IOE programmable delay for Cyclone III devices.
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 1 of 2)
Max Offset
Number
Paths
Affected
Min
Offset
Parameter
of
Fast Corner
A7, I7 C6
Slow Corner
C8
Unit
Settings
C6
C7
I7
A7
Pad to I/O
dataout to
core
Input delay from pin to
internal cells
7
8
0
0
1.211 1.314 2.175
2.32
2.386 2.366
2.49
ns
ns
Input delay from pin to Pad to I/O
1.203 1.307
2.19
2.387
2.54
2.43
2.545
input register
input register
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–26
Chapter 1: Cyclone III Device Datasheet
I/O Timing
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 2 of 2)
Max Offset
Number
Paths
Affected
Min
Offset
Parameter
of
Fast Corner
A7, I7 C6
Slow Corner
C8
Unit
Settings
C6
C7
I7
A7
I/O output
register to
pad
Delay from output
register to output pin
2
0
0
0.479 0.504 0.915 1.011 1.107 1.018 1.048
0.664 0.694 1.199 1.378 1.532 1.392 1.441
ns
ns
Input delay from
Pad to global
dual-purpose clock pin clock
to fan-out destinations network
12
Notes to Table 1–37:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.
(1), (2)
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins
Max Offset
Number
Paths
Affected
Min
Offset
Parameter
of
Fast Corner
A7, I7 C6
Slow Corner
C8
Unit
Settings
C6
C7
I7
A7
Pad to I/O
dataout to
core
Input delay from pin to
internal cells
7
8
2
0
0
0
1.209 1.314 2.174 2.335 2.406 2.381 2.505
1.207 1.312 2.202 2.402 2.558 2.447 2.557
ns
ns
ns
Input delay from pin to Pad to I/O
input register
input register
I/O output
register to
pad
Delay from output
register to output pin
0.51
0.537 0.962 1.072 1.167 1.074 1.101
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to global
clock network
12
0
0.669 0.698 1.207 1.388 1.542 1.403
1.45
ns
Notes to Table 1–38:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software
I/O Timing
You can use the following methods to determine the I/O timing:
■
the Excel-based I/O Timing.
the Quartus II timing analyzer.
■
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–27
Glossary
f
The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices
Literature website.
Glossary
Table 1–39 lists the glossary for this chapter.
Table 1–39. Glossary (Part 1 of 5)
Letter
Term
—
Definitions
A
B
C
D
E
—
—
—
—
—
—
—
—
—
F
fHSCLK
GCLK
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
G
H
GCLK PLL
HSIODR
Input pin to Global Clock network through PLL.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
VIH
Input Waveforms
for the SSTL
Differential I/O
Standard
I
VSWING
VREF
VIL
TMS
TDI
tJCP
tJPSU_TDI
tJPSU_TMS
tJCH
t JCL
tJPH
TCK
TDO
J
JTAG Waveform
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
K
L
—
—
—
—
—
—
M
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–28
Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 2 of 5)
Letter
Term
—
Definitions
N
O
—
—
—
The following block diagram highlights the PLL Specification parameters.
CLKOUT Pins
fOUT_EXT
Switchover
CLK
fIN
fINPFD
N
fVCO
VCO
PFD
CP
LF
fOUT
GCLK
Counters
Core Clock
C0..C4
P
Q
PLL Block
Phase tap
M
Key
Reconfigurable in User Mode
—
—
RL
Receiver differential input discrete resistor (external to Cyclone III devices).
Receiver Input Waveform for LVDS and LVPECL Differential Standards.
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
Ground
VCM
Receiver Input
Waveform
R
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VID
0 V
VID
p - n
RSKM (Receiver
input skew
margin)
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–29
Glossary
Table 1–39. Glossary (Part 3 of 5)
Letter
Term
Definitions
VCCIO
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
Single-ended
Voltage
referenced I/O
Standard
VOL
S
VSS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
tC
High-speed receiver/transmitter input and output clock period.
TCCS (Channel-
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
to-channel-skew) including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
tCO
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
tcout
tDUTY
tFALL
tH
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal High-to-low transition time (80–20%).
Input register hold time.
T
Timing Unit
Interval (TUI)
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on PLL clock input.
tOUTJITTER_DEDCLK
tOUTJITTER_IO
tpllcin
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
tpllcout
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–30
Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 4 of 5)
Letter
Term
Definitions
Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
V
os
Ground
Transmitter
Output Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VOD
0 V
VOD
p - n
tRISE
tSU
Signal Low-to-high transition time (20–80%).
Input register setup time.
—
U
—
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–31
Glossary
Table 1–39. Glossary (Part 5 of 5)
Letter
Term
VCM(DC)
Definitions
DC Common Mode Input Voltage.
VDIF(AC)
VDIF(DC)
VICM
AC differential Input Voltage: The minimum AC input differential voltage required for switching.
DC differential Input Voltage: The minimum DC input differential voltage required for switching.
Input Common Mode Voltage: The common mode of the differential signal at the receiver.
Input differential Voltage Swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VIH
Voltage Input High: The minimum positive voltage applied to the input which is accepted by the
device as a logic high.
VIH(AC)
VIH(DC)
High-level AC input voltage.
High-level DC input voltage.
Voltage Input Low: The maximum positive voltage applied to the input which is accepted by the
device as a logic low.
VIL
VIL (AC)
VIL (DC)
VIN
Low-level AC input voltage.
Low-level DC input voltage.
DC input voltage.
VOCM
Output Common Mode Voltage: The common mode of the differential signal at the transmitter.
Output differential Voltage Swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.
VOD
VOH
V
Voltage Output High: The maximum positive voltage from an output which the device considers is
accepted as the minimum positive high level.
Voltage Output Low: The maximum positive voltage from an output which the device considers is
accepted as the maximum positive low level.
VOL
VOS
Output offset voltage: VOS = (VOH + VOL) / 2.
AC differential Output cross point voltage: The voltage at which the differential output signals must
cross.
VOX (AC)
VREF
Reference voltage for SSTL, HSTL I/O Standards.
AC input reference voltage for SSTL, HSTL I/O Standards. VREF(AC) = VREF(DC) + noise. The
VREF (AC)
VREF (DC)
VSWING (AC)
peak-to-peak AC noise on VREF should not exceed 2% of VREF(DC)
.
DC input reference voltage for SSTL, HSTL I/O Standards.
AC differential Input Voltage: AC Input differential voltage required for switching. For the SSTL
Differential I/O Standard, refer to Input Waveforms.
DC differential Input Voltage: DC Input differential voltage required for switching. For the SSTL
Differential I/O Standard, refer to Input Waveforms.
VSWING (DC)
VTT
Termination voltage for SSTL, HSTL I/O Standards.
AC differential Input cross point Voltage: The voltage at which the differential input signals must
cross.
VX (AC)
W
X
Y
Z
—
—
—
—
—
—
—
—
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–32
Chapter 1: Cyclone III Device Datasheet
Document Revision History
Document Revision History
Table 1–40 lists the revision history for this document.
Table 1–40. Document Revision History (Part 1 of 3)
Date
July 2012
Version
Changes
3.5
Updated minimum fHSCLK value to 5 MHz.
■ Updated “Supply Current” on page 1–5 and “Periphery Performance” on page 1–17.
December 2011
3.4
■ Updated Table 1–3, Table 1–4, Table 1–13, Table 1–16, Table 1–17, Table 1–20, and
Table 1–25.
■ Removed Table 1-32 and Table 1-33.
■ Added Literature: External Memory Interfaces reference.
Minor changes to the text.
January 2010
3.3
December 2009
July 2009
3.2
3.1
Minor edit to the hyperlinks.
■ Changed chapter title from DC and Switching Characteristics to “Cyclone III Device Data
Sheet” on page 1–1.
■ Updated (Note 1) to Table 1–23 on page 1–17.
■ Updated “External Memory Interface Specifications” on page 1–23.
■ Replaced Table 1–32 on page 1–23.
June 2009
3.0
■ Replaced Table 1–33 on page 1–23.
■ Added Table 1–36 on page 1–26.
■ Updated “I/O Timing” on page 1–28.
■ Removed “Typical Design Performance” section.
■ Removed “I/O Timing” subsections.
■ Updated chapter to new template.
■ Updated Table 1–1, Table 1–3, and Table 1–18.
■ Added (Note 7) to Table 1–3.
October 2008
2.2
2.1
■ Added the “OCT Calibration Timing Specification” section.
■ Updated “Glossary” section.
■ Updated Table 1–38.
■ Added BLVDS information (I/O standard) into Table 1–39, Table 1–40, Table 1–41,
Table 1–42.
■ Updated Table 1–43, Table 1–46, Table 1–47, Table 1–48, Table 1–49, Table 1–50,
Table 1–51, Table 1–52, Table 1–53, Table 1–54, Table 1–55, Table 1–56, Table 1–57,
Table 1–58, Table 1–59, Table 1–60, Table 1–61, Table 1–62, Table 1–63, Table 1–68,
Table 1–69, Table 1–74, Table 1–75, Table 1–80, Table 1–81, Table 1–86, Table 1–87,
Table 1–92, Table 1–93, Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and
Table 1–99.
July 2008
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 1: Cyclone III Device Datasheet
1–33
Document Revision History
Table 1–40. Document Revision History (Part 2 of 3)
Date
Version
Changes
■ Updated “Operating Conditions” section and included information on automotive device.
■ Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive information.
■ Under “Pin Capacitance” section, updated Table 1–9 and Table 1–10.
■ Added new “Schmitt Trigger Input” section with Table 1–12.
■ Under “I/O Standard Specifications” section, updated Table 1–13, 1–12 and 1–12.
May 2008
2.0
■ Under “Switching Characteristics” section, updated Table 1–19, 1–15, 1–16, 1–16, 1–17,
1–18, 1–19, 1–20, 1–21, 1–21, 1–23, 1–23, 1–23, 1–24, and 1–25.
■ Updated Figure 1–5 and 1–29.
■ Deleted previous Table 1-35 “DDIO Outputs Half-Period Jitter”.
■ Under “I/O Timing” section, updated Table 1–38, 1–29, 1–32, 1–33, 1–26, and 1–26.
■ Under “Typical Design Performance” section updated Table 1–46 through 1–145.
■ Under “Core Performance Specifications”, updated Tables 1-18 and 1-19.
■ Under “Preliminary, Correlated, and Final Timing”, updated Table 1-37.
December 2007
1.5
■ Under “Typical Design Performance”, updated Tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58,
Tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, Tables 1-87 through 1-92,
Tables 1-99, 1-100, 1-107, and 1-108.
■ Updated the CVREFTB value in Table 1-9.
■ Updated Table 1-21.
■ Under “High-Speed I/O Specification” section, updated Tables 1-25 through 1-30.
■ Updated Tables 1-31 through 1-38.
■ Added new Table 1-32.
October 2007
1.4
■ Under “Maximum Input and Output Clock Toggle Rate” section, updated Tables 1-40
through 1-42.
■ Under “IOE Programmable Delay” section, updated Tables 1-43 through 1-44.
■ Under “User I/O Pin Timing Parameters” section, updated Tables 1-45 through 1-92.
■ Under “Dedicated Clock Pin Timing Parameters” section, updated Tables 1-93 through 1-
108.
■ Updated Table 1-1 with VESDHBM and VESDCDM information.
■ Updated RCONF_PD information in Tables 1-10.
■ Added Note (3) to Table 1-12.
July 2007
June 2007
1.3
1.2
■ Updated tDLOCK information in Table 1-19.
■ Updated Table 1-43 and Table 1-44.
■ Added “Document Revision History” section.
Updated Cyclone III graphic in cover page.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
1–34
Chapter 1: Cyclone III Device Datasheet
Document Revision History
Table 1–40. Document Revision History (Part 3 of 3)
Date
Version
Changes
■ Corrected current unit in Tables 1-1, 1-12, and 1-14.
■ Added Note (3) to Table 1-3.
■ Updated Table 1-4 with ICCINT0, ICCA0, ICCD_PLL0, and ICCIO0 information.
■ Updated Table 1-9 and added Note (2).
■ Updated Table 1-19.
■ Updated Table 1-22 and added Note (1).
May 2007
1.1
■ Changed I/O standard from 1.5-V LVTTL/LVCMOS and 1.2-V LVTTL/LVCMOS to 1.5-V
LVCMOS and 1.2-V LVCMOS in Tables 1-41, 1-42, 1-43, 1-44, and 1-45.
■ Updated Table 1-43 with changes to LVPEC and LVDS and added Note (5).
■ Updated Tables 1-46, 1-47, Tables 1-54 through 1-95, and Tables 1-98 through 1-111.
■ Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1-110 through
1-111.
■ Added a waveform (Receiver Input Waveform) in glossary under letter “R” (Table 1-112).
March 2007
1.0
Initial release.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
2. Cyclone III LS Device Datasheet
July 2012
CIII52002-1.4
CIII52002-1.4
This chapter describes the electric characteristics, switching characteristics, and I/O
timing for Cyclone® III LS devices. A glossary is also included for your reference.
Electrical Characteristics
The following sections provide information about the absolute maximum ratings,
recommended operating conditions, DC characteristics, and other specifications for
Cyclone III LS devices.
Operating Conditions
When Cyclone III LS devices are implemented in a system, they are rated according to
a set of defined parameters. To maintain the highest possible performance and
reliability of Cyclone III LS devices, you must consider the operating requirements in
this chapter. Cyclone III LS devices are offered in commercial and industrial grades.
Commercial devices are offered in –7 (fastest) and –8 speed grades. Industrial devices
are offered only in –7 speed grade.
1
1
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades—commercial with a “C” prefix; industrial with an “I” prefix. For
example, commercial devices are described as C7 and C8 per respective speed grades.
Industrial devices are described as I7.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for
Cyclone III LS devices. The values are based on experiments conducted with the
device and theoretical modeling of breakdown and damage mechanisms. The
functional operation of the device is not implied at these conditions. Table 2–1 lists the
absolute maximum ratings for Cyclone III LS devices.
Conditions beyond those listed in Table 2–1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device. All parameters representing
voltages are measured with respect to ground.
Table 2–1. Cyclone III LS Devices Absolute Maximum Ratings (1) (Part 1 of 2)
Symbol
VCCINT
Parameter
Supply voltage for internal logic
Supply voltage for output buffers
Min
–0.5
–0.5
Max
1.8
Unit
V
VCCIO
3.9
V
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 2
July 2012
Subscribe
2–2
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Table 2–1. Cyclone III LS Devices Absolute Maximum Ratings (1) (Part 2 of 2)
Symbol
VCCA
VCCD_PLL
Parameter
Min
–0.5
–0.5
Max
3.75
1.8
Unit
V
Supply (analog) voltage for PLL regulator
Supply (digital) voltage for PLL
V
Battery back-up power supply for design
security volatile key register
(2)
VCCBAT
–0.5
3.75
V
VI
DC input voltage
–0.5
–25
3.95
40
V
IOUT
DC output current, per pin
mA
Electrostatic discharge voltage using the human
body model
VESDHBM
VESDCDM
—
—
2000
500
V
V
Electrostatic discharge voltage using the
charged device model
TSTG
TJ
Storage temperature
–65
–40
150
125
°C
°C
Operating junction temperature
Notes to Table 2–1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the
power supply.
(2) VCCBAT is tied to Power-on reset (POR). If the VCCBAT is below 1.2 V, the device will not power up.
Maximum Allowed Overshoot or Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2–2 and
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods
shorter than 20 ns.
Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage over the lifetime of the device. The maximum
allowed overshoot duration is specified as percentage of high-time over the lifetime of
the device.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–3
Electrical Characteristics
1
A DC signal is equivalent to 100% of the duty cycle. For example, a signal that
overshoots to 4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for a
device lifetime of 10 years, this is equivalent to 10.74% of ten years, which is 12.89
months.
Table 2–2. Cyclone III LS Devices Maximum Allowed Overshoot During Transitions over a 10-Year
Time Frame
Symbol
Parameter
Condition
VI = 3.95 V
VI = 4.0 V
Overshoot Duration as % of High Time
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
%
100
95.67
55.24
31.97
18.52
10.74
6.23
VI = 4.05 V
VI = 4.10 V
VI = 4.15 V
VI = 4.20 V
VI = 4.25 V
VI = 4.30 V
VI = 4.35 V
VI = 4.40 V
VI = 4.45 V
VI = 4.50 V
VI = 4.60 V
VI = 4.70 V
AC Input
Voltage
Vi
3.62
2.1
1.22
0.71
0.41
0.14
0.047
Figure 2–1 shows the methodology to determine the overshoot duration. In this
example, overshoot voltage is shown in red and is present on the input pin of the
Cyclone III LS device at over 4.1 V but below 4.2 V. From Table 2–1, for an overshoot
of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over a
10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This
10-year period assumes the device is always turned on with 100% I/O toggle rate and
50% duty cycle signal. For lower I/O toggle rates and situations in which the device is
in an idle state, lifetimes are increased.
Figure 2–1. Cyclone III LS Devices Overshoot Duration
4.2 V
4.1 V
3.3 V
ΔT
T
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–4
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone III LS devices.
The steady-state voltage and current values expected from Cyclone III LS devices are
provided in Table 2–3. All supplies must be strictly monotonic without plateaus.
Table 2–3. Cyclone III LS Devices Recommended Operating Conditions (1), (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(3)
VCCINT
Supply voltage for internal logic
—
1.15
1.2
1.25
V
Supply voltage for output buffers, 3.3-V
operation
—
—
—
—
—
—
3.135
2.85
3.3
3.0
2.5
1.8
1.5
1.2
3.465
3.15
V
V
V
V
V
V
Supply voltage for output buffers, 3.0-V
operation
Supply voltage for output buffers, 2.5-V
operation
2.375
1.71
2.625
1.89
(3), (7)
VCCIO
Supply voltage for output buffers, 1.8-V
operation
Supply voltage for output buffers, 1.5-V
operation
1.425
1.14
1.575
1.26
Supply voltage for output buffers, 1.2-V
operation
(3)
VCCA
Supply (analog) voltage for PLL regulator
Supply (digital) voltage for PLL
—
—
2.375
1.15
2.5
1.2
2.625
1.25
V
V
(3)
VCCD_PLL
Battery back-up power supply for design
security volatile key register
(4)
VCCBAT
—
1.2
3.0
3.3
V
VI
Input voltage
—
–0.5
0
—
—
—
—
—
—
3.6
VCCIO
85
V
VO
Output voltage
—
V
For commercial use
0
°C
°C
—
—
TJ
Operating junction temperature
Power supply ramptime
For industrial use
–40
50 µs
50 µs
100
(5)
Standard POR
50 ms
3 ms
tRAMP
IDiode
(6)
Fast POR
Magnitude of DC current across
PCI-clamp diode when enabled
—
—
—
10
mA
Notes to Table 2–3:
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when you do not use phase
locked-loops [PLLs}), and must be powered up and powered down at the same time.
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.
(3) VCC must rise monotonically.
(4) VCCBAT is tied to POR. If the VCCBAT is below 1.2 V, the device will not power up.
(5) POR time for Standard POR ranges from 50 to 200 ms. Each individual power supply must reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges from 3 to 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.
(7) All input buffers are powered by the VCCIO supply.
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone III LS devices.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–5
Electrical Characteristics
Supply Current
Supply current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Use the Excel-based Early
Power Estimator (EPE) to get the supply current estimates for your design because
these currents vary largely with the resources you use. Table 2–4 lists the I/O pin
leakage current for Cyclone III LS devices.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Table 2–4. Cyclone III LS Devices I/O Pin Leakage Current (1), (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
II
Input Pin Leakage Current VI = VCCIOMAX to 0 V
Tri-stated I/O Pin Leakage VO = VCCIOMAX to 0
–10
—
10
A
IOZ
–10
—
10
A
Current
V
Notes to Table 2–4:
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all
CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
V
(2) The 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be
observed when the diode is on.
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 2–5 lists the bus hold specifications for Cyclone III LS devices. Also listed are the
input pin capacitances and OCT tolerance specifications.
Table 2–5. Cyclone III LS Devices Bus Hold Parameters (1)
V
CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min
Max Min Max Min Max Min Max Min Max
Bus-hold
low,
sustaining
current
VIN > VIL
(maximum)
8
—
—
12
–12
—
—
—
30
–30
—
—
—
50
–50
—
—
—
70
–70
—
—
—
70
–70
—
—
—
A
A
Bus-hold
high,
sustaining
current
VIN < VIL
(minimum)
–8
—
Bus-hold
low,
overdrive
current
0 V < VIN <
VCCIO
125
175
200
300
500
500 A
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–6
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Table 2–5. Cyclone III LS Devices Bus Hold Parameters (1)
V
CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min
Max Min Max Min Max Min Max Min Max
Bus-hold
high,
overdrive
current
0 V < VIN <
VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
—
–500 A
Bus-hold
trip point
—
0.3
0.9 0.375 1.125 0.68 1.07 0.7
1.7 0.8 2.0 0.8 2.0
V
Note to Table 2–5:
(1) Bus-hold trip points are based on calculated input voltages from the JEDEC standard.
OCT Specifications
Table 2–6 lists the variation of OCT without calibration across process, temperature,
and voltage (PVT).
Table 2–6. Cyclone III LS Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description
V
CCIO (V)
Unit
Commercial Max
Industrial Max
3.0
2.5
1.8
1.5
1.2
30
30
40
50
50
40
40
50
50
50
%
%
%
%
%
Series OCT without
calibration
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
Table 2–7 lists the OCT calibration accuracy at device power-up.
Table 2–7. Cyclone III LS Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description
V
CCIO (V)
Unit
Commercial Max
Industrial Max
3.0
2.5
1.8
1.5
1.2
10
10
10
10
10
10
10
10
10
10
%
%
%
%
%
Series Termination with
power-up calibration
OCT resistance may vary with the variation of temperature and voltage after
power-up calibration. Use Table 2–8 and Equation 2–1 to determine the final OCT
resistance considering the variations after power-up calibration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–7
Electrical Characteristics
Table 2–8 lists the percentage change of the OCT resistance with voltage and
temperature.
Table 2–8. Cyclone III LS Devices OCT Variation After Calibration at Device Power-Up (1)
Nominal Voltage
dR/dT (%/°C)
0.262
dR/dV (%/mV)
–0.026
3.0
2.5
1.8
1.5
1.2
0.234
–0.039
0.219
–0.086
0.199
–0.136
0.161
–0.288
Note to Table 2–8:
(1) Use this table to calculate the final OCT resistance with the variation of temperature and voltage.
(1), (2), (3), (4), (5), (6)
Equation 2–1.
(7)
RV = (V2 – V1) × 1000 × dR/dV –––––
(8)
RT = (T2 – T1) × dR/dT –––––
(9)
For Rx < 0; MFx = 1/ (|Rx|/100 + 1) –––––
(10)
For Rx > 0; MFx = Rx/100 + 1 –––––
(11)
MF = MFV × MFT –––––
(12)
Rfinal = Rinitial × MF –––––
Notes to Equation 2–1:
(1) T2 is the final temperature.
(2) T1 is the initial temperature.
(3) MF is multiplication factor.
(4) Rfinal is final resistance.
(5) Rinitial is initial resistance.
(6) Subscript × refers to both V and T.
(7) RV is variation of resistance with voltage.
(8) RT is variation of resistance with temperature.
(9) dR/dT is the percentage change of resistance with temperature.
(10) dR/dV is the percentage change of resistance with voltage.
(11) V2 is final voltage.
(12) V1 is the initial voltage.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–8
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Example 2–1 shows you how to calculate the change of 50 I/O impedance from
25°C at 3.0 V to 85°C at 3.15 V.
Example 2–1.
RV = (3.15 – 3) × 1000 × –0.026 = –3.83
RT = (85 – 25) × 0.262 = 15.72
Because RV is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because RT is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
R
final = 50 × 1.114 = 55.71
Pin Capacitance
Table 2–9 lists the pin capacitance for Cyclone III LS devices.
Table 2–9. Cyclone III LS Devices Pin Capacitance
Typical – Typical –
Symbol
Parameter
Unit
QFP
FBGA
CIOTB
CIOLR
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
7
6
5
pF
pF
7
Input capacitance on left/right I/O pins with true LVDS
output
CLVDSLR
8
21
23
7
7
21
23
6
pF
pF
pF
pF
pF
CVREFLR
Input capacitance on left/right dual-purpose VREFpin
when used as VREF or user I/O pin
(1)
CVREFTB
Input capacitance on top/bottom dual-purpose VREF
pin when used as VREF or user I/O pin
(1)
Input capacitance on top/bottom dedicated clock input
pins
CCLKTB
CCLKLR
Input capacitance on left/right dedicated clock input
pins
6
5
Note to Table 2–9:
(1) When you use the VREFpin as a regular input or output, you can expect a reduced performance of toggle rate and
CO due to higher pin capacitance.
t
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–9
Electrical Characteristics
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 2–10 lists the weak pull-up and pull-down resistor values for Cyclone III LS
devices.
Table 2–10. Cyclone III LS Devices Internal Weak Pull-Up Weak and Pull-Down Resistor (1)
Symbol
Parameter
Conditions
Min
7
Typ
25
28
35
57
82
143
19
22
25
35
50
Max
41
Unit
(2), (3)
VCCIO = 3.3 V 5%
k
k
k
k
k
k
k
k
k
k
k
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(4)
V
V
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
7
47
Value of I/O pin pull-up resistor before
and during configuration, as well as
user mode if the programmable
pull-up resistor option is enabled
8
61
R_PU
VCCIO = 1.8 V 5%
10
13
19
6
108
163
351
30
V
V
V
V
V
V
V
CCIO = 1.5 V 5%
CCIO = 1.2 V 5%
CCIO = 3.3 V 5%
CCIO = 3.0 V 5%
CCIO = 2.5 V 5%
CCIO = 1.8 V 5%
CCIO = 1.5 V 5%
(4)
6
36
Value of I/O pin pull-down resistor
before and during configuration
(4)
R_PD
6
43
(4)
7
71
(4)
8
112
Notes to Table 2–10:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG TCK.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(3) R_PU = (VCCIO – VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC – 5%;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Hot Socketing
Table 2–11 lists the hot-socketing specifications for Cyclone III LS devices.
Table 2–11. Cyclone III Devices LS Hot-Socketing Specifications
Symbol
Parameter
DC current per I/O pin
AC current per I/O pin
Maximum
IIOPIN(DC)
IIOPIN(AC)
300 A
(1)
8 mA
Note to Table 2–11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin
capacitance and dv/dt is the slew rate.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–10
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III LS devices support Schmitt trigger input on TDI
CONF_DONE, and DCLKpins. A Schmitt trigger feature introduces
,
TMS, TCK, nSTATUS,
nCONFIG, nCE,
hysteresis to the input signal for improved noise immunity, especially for signals with
a slow edge rate. Table 2–12 lists the hysteresis specifications across supported VCCIO
range for Schmitt trigger inputs in Cyclone III LS devices.
Table 2–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III LS Devices
Symbol
Parameter
Conditions
Minimum
200
Typical
—
Maximum
Unit
mV
mV
mV
mV
VCCIO = 3.3 V
—
—
—
—
V
V
CCIO = 2.5 V
CCIO = 1.8 V
200
—
Hysteresis for Schmitt trigger
input
VSCHMITT
140
—
VCCIO = 1.5 V
110
—
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Cyclone III LS devices.
Table 2–13 through Table 2–18 provide Cyclone III LS devices I/O standard
specifications.
Table 2–13. Cyclone III LS Devices Single-Ended I/O Standard Specifications (1)
VCCIO (V)
Typ
VIL (V)
Max Min Max
VIH (V)
Max
VOL (V)
VOH (V)
IOL
IOH
I/O Standard
(mA) (mA)
Min
Min
1.7
1.7
1.7
1.7
Max
0.45
0.2
Min
2.4
(2)
3.3-V LVTTL
3.135 3.3 3.465
3.135 3.3 3.465
—
—
0.8
0.8
0.8
0.8
3.6
4
2
4
–4
–2
(2)
(2)
3.3-V LVCMOS
3.6
VCCIO – 0.2
2.4
(2)
3.0-V LVTTL
2.85
2.85
3.0
3.0
3.15 –0.3
3.15 –0.3
VCCIO + 0.3
VCCIO + 0.3
0.45
0.2
–4
3.0-V LVCMOS
VCCIO – 0.2 0.1
–0.1
2.5-V LVTTL and
LVCMOS
2.375 2.5 2.625 –0.3
1.71 1.8 1.89 –0.3
1.425 1.5 1.575 –0.3
0.7
1.7
3.6
0.4
2.0
1
2
2
2
–1
–2
(2)
1.8-V LVTTL and
LVCMOS
0.35* 0.65*
VCCIO VCCIO
VCCIO
0.45
–
2.25
0.45
0.35* 0.65*
VCCIO VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
1.5-V LVCMOS
1.2-V LVCMOS
PCI
VCCIO + 0.3
VCCIO + 0.3
–2
0.35* 0.65*
VCCIO VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
1.14
2.85
2.85
1.2
3.0
3.0
1.26 –0.3
–2
0.30* 0.50*
VCCIO VCCIO
3.15
3.15
—
—
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO 1.5
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO 1.5
–0.5
–0.5
0.35* 0.50*
VCCIO VCCIO
PCI-X
Notes to Table 2–13:
(1) AC load CL = 10 pF.
(2) For more information about interfacing Cyclone III LS devices with 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS I/O standards,
refer to AN 447: Interfacing Cyclone III and Cyclone iV Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–11
Electrical Characteristics
Table 2–14. Cyclone III LS Devices Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (4)
(3)
V
CCIO (V)
VREF (V)
Typ
VTT (V)
Typ
I/O
Standard
Min
Typ Max
Min
Max
Min
Max
SSTL-2
Class I, II
VREF
0.04
–
VREF
0.04
+
2.375 2.5 2.625
1.7 1.8 1.9
1.19
1.25
0.9
1.31
VREF
VREF
0.9
SSTL-18
Class I, II
VREF
0.04
–
VREF
0.04
+
0.833
0.85
0.71
0.969
0.95
HSTL-18
Class I, II
1.71 1.8 1.89
1.425 1.5 1.575
0.9
0.85
0.71
0.95
0.79
HSTL-15
Class I, II
0.75
0.79
0.75
0.48 * VCCIO
(1)
(2)
(1)
(2)
0.5 * VCCIO
0.5 * VCCIO
0.52 * VCCIO
0.53 * VCCIO
(1)
HSTL-12
Class I, II
0.5 *
VCCIO
1.14 1.2 1.26
—
—
0.47 * VCCIO
(2)
Notes to Table 2–14:
(1) The value shown refers to the DC input reference voltage, VREF(DC)
(2) The value shown refers to the AC input reference voltage, VREF(AC)
(3) VTT of the transmitting device must track VREF of the receiving device.
(4) For an explanation of the terms used in Table 2–14, refer to “Glossary” on page 2–26.
.
.
Table 2–15. Cyclone III LS Devices Single-Ended SSTL and HSTL I/O Standards Signal Specifications
VIL(DC) (V)
Min Max
VREF
VIH(DC) (V)
Max
VIL(AC) (V)
Min Max
VREF
VIH(AC) (V)
Min Max
VOL (V) VOH (V)
Max Min
I/O
IOL
IOH
Standard
(mA) (mA)
Min
SSTL-2
Class I
–
VREF
0.18
+
–
VREF
0.35
+
VTT
0.57
–
VTT +
0.57
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.1
16.4 –16.4
6.7 –6.7
13.4 –13.4
–8.1
0.18
0.35
SSTL-2
Class II
VREF
0.18
–
VREF
0.18
+
VREF
–
VREF
0.35
+
VTT
0.76
–
VTT +
0.76
—
0.35
SSTL-18
Class I
VREF
0.125
–
VREF
+
VREF
–
VREF
0.25
+
VTT
0.475
–
VTT
0.475
+
—
0.125
0.25
SSTL-18
Class II
VREF
0.125
–
VREF
+
VREF
–
VREF
0.25
+
VCCIO
0.28
–
—
0.28
0.4
0.4
0.4
0.4
0.125
0.25
HSTL-18
Class I
VREF
0.1
–
–
–
–
–
VREF
0.1
+
+
+
+
+
VREF
0.2
–
VREF
0.2
+
VCCIO
0.4
–
—
8
16
8
–8
–16
–8
HSTL-18
Class II
VREF
0.1
VREF
0.1
VREF
0.2
–
–
–
–
VREF
0.2
+
+
+
+
VCCIO
0.4
–
–
–
—
HSTL-15
Class I
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
16
8
–16
–8
HSTL-12
Class I
VREF
0.08
VREF
VREF
VREF
VCCIO
+
+
0.25 × 0.75 ×
VCCIO VCCIO
–0.15
–0.15
VCCIO + 0.15 –0.24
VCCIO + 0.15 –0.24
0.08
VREF
0.08
0.15
0.15
0.24
HSTL-12
Class II
VREF
0.08
–
+
VREF
–
VREF
+
VCCIO
0.24
0.25 × 0.75 ×
VCCIO VCCIO
14
–14
0.15
0.15
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–12
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
f
For more information about receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the High-Speed Differential Interfaces in
Cyclone III Devices chapter.
Table 2–16. Cyclone III LS Devices Differential SSTL I/O Standard Specifications (1)
VSwing(DC)
(V)
VSwing(AC)
VCCIO (V)
VX(AC) (V)
Typ
VOX(AC) (V)
Typ Max
(V)
I/O Standard
Min Typ Max Min Max
Min
Max
Min Max
Min
SSTL-2
Class I, II
V
+ 0.2
CCIO/2
VCCI VCCIO/2 –
V
CCIO/2
2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2
VCCIO/2 –
—
—
0.7
0.5
—
—
0.125
+ 0.125
O
SSTL-18
Class I, II
V
CCIO/2
VCCI VCCIO/2 –
V
CCIO/2
1.7
1.8 1.90 0.25 VCCIO
0.175
+ 0.175
0.125
+ 0.125
O
Note to Table 2–16:
(1) Differential SSTL requires a VREF input.
Table 2–17. Cyclone III LS Devices Differential HSTL I/O Standard Specifications (1)
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
VDIF(AC) (V)
I/O Standard
Min Typ Max Min Max
Min
Max
Min
Typ
Max
Min Max
HSTL-18
Class I, II
1.71 1.8 1.89 0.2
1.425 1.5 1.575 0.2
—
—
0.85
—
—
—
0.95
0.85
—
0.95
0.4
0.4
0.3
—
—
HSTL-15
Class I, II
0.71
0.79
0.71
—
—
0.79
HSTL-12
Class I, II
0.48 *
VCCIO
0.52 * 0.48 *
VCCIO VCCIO
0.52 *
VCCIO
0.48 *
VCCIO
1.14 1.2 1.26 0.16 VCCIO
Note to Table 2–17:
(1) Differential HSTL requires a VREF input.
Table 2–18. Differential I/O Standard Specifications (1) (Part 1 of 2)
(2)
(2)
V
CCIO (V)
VID (mV)
VICM (V)
VOD (mV)
VOS (V)
I/O
Standard
Min Typ Max Min Max Min
Condition
Max Min Typ Max Min Typ Max
0
DMAX500 Mbps 1.85
LVPECL
(Row
I/Os)
500 Mbps DMAX
700 Mbps
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 100
—
—
—
0.5
1.85
1.6
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
1
0
DMAX > 700 Mbps
D
MAX 500 Mbps 1.85
LVPECL
(Column
500 Mbps DMAX
700 Mbps
0.5
1.85
1.6
(3)
I/Os)
1
0
D
D
MAX > 700 Mbps
MAX 500 Mbps 1.85
LVDS
(Row
I/Os)
500 Mbps DMAX
700 Mbps
0.5
1
1.85 247
1.6
600 1.125 1.25 1.375
D
MAX > 700 Mbps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–13
Electrical Characteristics
Table 2–18. Differential I/O Standard Specifications (1) (Part 2 of 2)
(2)
(2)
VCCIO (V)
VID (mV)
VICM (V)
VOD (mV)
VOS (V)
I/O
Standard
Min Typ Max Min Max Min
Condition
Max Min Typ Max Min Typ Max
0
DMAX 500 Mbps 1.85
LVDS
(Column
I/Os)
500 Mbps DMAX
700 Mbps
2.375 2.5 2.625 100
—
0.5
1
1.85 247
1.6
—
600 1.125 1.25 1.35
D
MAX > 700 Mbps
BLVDS
(Row
I/Os)
2.375 2.5 2.625 100
2.375 2.5 2.625 100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
BLVDS
(Column
—
—
—
—
—
—
—
—
(4)
I/Os)
mini-LVDS
(Row
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
2.375 2.5 2.625
—
—
—
—
—
—
—
300
300
600
600
1.0
1.0
0.5
0.5
0.5
0.5
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.5
1.5
1.4
1.4
(5)
I/Os)
mini-LVDS
(Column
—
—
—
—
—
(5)
I/Os)
RSDS
(Row
I/Os)
100 200 600
100 200 600
100 200 600
100 200 600
(5)
RSDS
(Column
(5)
I/Os)
PPDS
(Row
I/Os)
(5)
PPDS
(Column
(5)
I/Os)
Notes to Table 2–18:
(1) For an explanation of the terms used in Table 2–18, refer to “Transmitter Output Waveform” in “Glossary” on page 2–26.
(2) RL range: 90 RL 110 .
(3) The LVPECL input standard is only supported at clock input. The output standard is not supported.
(4) There is no fixed VICM, VOD, and VOS specification for BLVDS. They are dependent on the system topology.
(5) Mini-LVDS, RSDS, and PPDS standards are only supported at output pins of Cyclone III LS devices.
Power Consumption
Use the following methods to estimate power for your design:
■
The Excel-based EPE
■
The Quartus II® PowerPlay power analyzer feature
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–14
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Use the interactive Excel-based EPE before designing your device to get a magnitude
estimate of the device power. The Quartus II PowerPlay power analyzer provides
better quality estimates based on the specifics of the design after place-and-route is
complete. The PowerPlay power analyzer can apply a combination of user-entered,
simulation-derived, and estimated signal activities which, combined with detailed
circuit models, can yield very accurate power estimates.
f
For more information about power estimation tools, refer to the Early Power Estimator
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook.
Switching Characteristics
This section describes performance characteristics of the core and periphery blocks for
Cyclone III LS devices.
Core Performance Specifications
Table 2–19 through Table 2–25 describe the core performance specifications for
Cyclone III LS devices.
Clock Tree Specifications
Table 2–19 lists the clock tree specifications for Cyclone III LS devices.
Table 2–19. Cyclone III LS Devices Clock Tree Performance
Performance
Device
Unit
C7
C8
I7
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
437.5
437.5
437.5
437.5
402
402
402
402
437.5
437.5
437.5
437.5
MHz
MHz
MHz
MHz
PLL Specifications
Table 2–20 lists the PLL specifications for Cyclone III LS devices when operating in
the commercial junction temperature range (0°C to 85°C) and the industrial junction
temperature range (-40°C to 100°C). For more information about the PLL block, refer
to “PLL Block” in “Glossary” on page 2–26.
Table 2–20. Cyclone III LS Devices PLL Specifications (4) (Part 1 of 2)
Symbol
Parameter
Min
5
Typ
—
—
—
—
—
—
Max
450
325
1300
60
Unit
MHz
MHz
MHz
%
(1)
fIN
fINPFD
Input clock frequency
PFD input frequency
5
(6)
fVCO
PLL internal VCO operating range
600
40
—
—
fINDUTY
Input clock duty cycle
Input clock cycle-to-cycle jitter for FINPFD 100 MHz
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz
0.15
750
UI
(5)
tINJITTER_CCJ
ps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–15
Switching Characteristics
Table 2–20. Cyclone III LS Devices PLL Specifications (4) (Part 2 of 2)
Symbol
Parameter
PLL output frequency
Min
Typ
Max
Unit
fOUT_EXT (external clock
—
—
450
MHz
(1)
output)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
—
—
—
—
450
MHz
MHz
fOUT (to global clock)
402.5
Duty cycle for external clock output (when set to
50%)
tOUTDUTY
tLOCK
45
—
50
—
55
1
%
Time required to lock from end of device
configuration
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
tDLOCK
—
—
1
ms
Dedicated clock output period jitter FOUT 100 MHz
—
—
—
—
300
30
ps
(3)
tOUTJITTER_PERIOD_DEDCLK
FOUT < 100 MHz
mUI
Dedicated clock output cycle-to-cycle jitter
—
—
300
ps
(3)
FOUT 100 MHz
tOUTJITTER_CCJ_DEDCLK
F
OUT < 100 MHz
—
—
—
—
—
—
10
—
—
—
—
—
—
—
30
650
75
mUI
ps
Regular I/O period jitter FOUT 100 MHz
OUT < 100 MHz
Regular I/O cycle-to-cycle jitter FOUT 100 MHz
OUT < 100 MHz
(3)
tOUTJITTER_PERIOD_IO
F
mUI
ps
650
75
(3)
tOUTJITTER_CCJ_IO
F
mUI
ps
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
50
Minimum pulse width on areset signal.
—
ns
scanclk
cycles
(2)
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
—
3.5
—
fSCANCLK
scanclkfrequency
—
100
MHz
Notes to Table 2–20:
(1) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) With 100-MHz scanclkfrequency.
(3) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
(4) VCCD_PLL must be connected to VCCINT through the decoupling capacitor and ferrite bead.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
than 200 ps.
(6) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–16
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Embedded Multiplier Specifications
Table 2–21 lists the embedded multiplier specifications for Cyclone III LS devices.
Table 2–21. Cyclone III LS Devices Embedded Multiplier Specifications
EP3CLS70, EP3CLS100,
Resources Used
EP3CLS150, and EP3CLS200
Performance
Mode
Unit
Number of Multipliers
C7 and I7
300
C8
9 × 9-bit multiplier
1
1
260
200
MHz
MHz
18 × 18-bit multiplier
250
Memory Block Specifications
Table 2–22 lists the M9K memory block and logic element (LE) specifications for
Cyclone III LS devices.
Table 2–22. Cyclone III LS Devices Memory Block Performance Specifications
EP3CLS70, EP3CLS100,
EP3CLS150, and EP3CLS200
Performance
Resources Used
Memory
Mode
Unit
M9K
Memory
LEs
C7 and I7
C8
FIFO 256 × 36
47
0
1
1
1
1
274
274
274
274
238
238
238
238
MHz
MHz
MHz
MHz
Single-port 256 × 36
M9K Block
Simple dual-port 256 × 36 CLK
True dual port 512 × 18 single CLK
0
0
Configuration and JTAG Specifications
Table 2–23 lists the configuration mode specifications for Cyclone III LS devices.
Table 2–23. Cyclone III LS Devices Configuration Mode Specifications
Programming Mode
Passive Serial (PS)
Fast Passive Parallel (FPP)
DCLK fMAX
133
Unit
MHz
MHz
100
Table 2–24 lists the active configuration mode specifications for Cyclone III LS
devices.
Table 2–24. Cyclone III LS Devices Active Configuration Mode Specifications
Programming Mode
Active Serial (AS)
DCLK Range
Unit
20 to 40
MHz
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–17
Switching Characteristics
Table 2–25 lists the JTAG timing parameters and values for Cyclone III LS devices.
Table 2–25. Cyclone III LS Devices JTAG Timing Parameters (1)
Symbol
tJCP
Parameter
Min
40
20
20
2
Max
—
—
—
—
—
—
16
15
15
—
—
25
25
25
Unit
TCK clock period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCK clock high time
TCK clock low time
tJCL
tJPSU_TDI JTAG port setup time for TDI
tJPSU_TMS JTAG port setup time for TMS
3
tJPH
JTAG port hold time
10
—
—
—
5
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
Capture register hold time
10
—
—
—
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Notes to Table 2–25:
(1) For more information, refer to “JTAG Waveform” in “Glossary” on page 2–26.
(2) The specification shown is for the 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For the 1.8-V
LVTTL/LVCMOS and the 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several systems interfacing, for example, the high-speed
I/O interface, external memory interface, and PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are
capable of typical 200 MHz interfacing frequency with 10 pF load.
1
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–18
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
High-Speed I/O Specification
Table 2–26 through Table 2–31 list the high-speed I/O timing for Cyclone III LS
devices. For more information about the definitions of high-speed timing
specifications, refer to “Glossary” on page 2–26.
Table 2–26. Cyclone III LS Devices RSDS Transmitter Timing Specification (1), (2)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
fHSCLK
(input clock
frequency)
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
311
100
80
70
40
20
10
45
—
311
311
311
311
311
Device operation
in Mbps
311
311
311
311
311
311
tDUTY
55
55
TCCS
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
tRISE
500
500
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
ps
CLOAD = 5 pF
(3)
tLOCK
—
ms
Notes to Table 2–26:
(1) Applicable for true RSDS and Emulated RSDS with three-resistor network transmitters.
(2) True RSDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS with three-resistor network
transmitter is supported at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–19
Switching Characteristics
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications (1)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
85
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
85
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
85
5
85
f
HSCLK (input
clock
frequency)
5
85
5
85
5
85
5
85
5
85
5
85
5
170
170
170
170
170
170
170
55
5
170
170
170
170
170
170
170
55
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
Device
operation in
Mbps
tDUTY
TCCS
200
200
ps
Output jitter
(peak to
peak)
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
tRISE
500
500
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(2)
tLOCK
ms
Notes to Table 2–27:
(1) Emulated RSDS with one-resistor network transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification (1), (2) (Part 1 of 2)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
Min
5
Typ
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
5
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–20
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification (1), (2) (Part 2 of 2)
C7 and I7
C8
Symbol
Modes
Unit
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
311
311
311
311
311
311
55
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
311
311
311
311
311
311
55
×10
×8
×7
×4
×2
×1
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
70
70
Device operation
in Mbps
40
40
20
20
10
10
tDUTY
45
45
TCCS
—
200
—
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
LOAD = 5 pF
20 – 80%,
tRISE
500
500
C
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(3)
tLOCK
ms
Notes to Table 2–28:
(1) Applicable for true and emulated mini-LVDS with three-resistor network transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS with three-resistor
network transmitter is supported at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–21
Switching Characteristics
Table 2–29. Cyclone III LS Devices True LVDS Transmitter Timing Specifications (1)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Max
370
370
370
370
370
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
402.5
740
740
740
740
740
402.5
55
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
HSIODR
tDUTY
TCCS
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
1
—
—
550
1
ps
(2)
tLOCK
ms
Notes to Table 2–29:
(1) True LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications (1) (Part 1 of 2)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Max
320
320
320
320
320
Min
5
Max
275
275
275
275
275
402.5
550
550
550
550
550
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
402.5
640
640
640
640
640
402.5
55
5
100
80
70
40
20
10
45
100
80
70
40
20
10
45
HSIODR
tDUTY
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–22
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications (1) (Part 2 of 2)
C7 and I7
C8
Symbol
TCCS
Modes
Unit
Min
Max
Min
Max
—
—
—
—
200
—
200
ps
ps
Output jitter
(peak to peak)
—
—
500
1
—
—
550
1
(2)
tLOCK
ms
Notes to Table 2–30:
(1) Emulated LVDS with three-resistor network transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications (1)
C7 and I7
C8
Symbol
Modes
Unit
Min
5
Max
370
370
370
370
370
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
400
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
402.5
740
5
100
80
70
40
20
10
—
100
80
70
40
20
10
—
740
740
HSIODR
SW
740
740
402.5
400
Input jitter
tolerance
—
—
—
—
500
1
—
—
550
1
ps
ps
(2)
tLOCK
Notes to Table 2–31:
(1) True LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
External Memory Interface Specifications
Cyclone III LS devices support external memory interfaces up to 200 MHz. The
external memory interfaces for Cyclone III LS devices are auto-calibrating and easy to
implement.
Table 2–32 and Table 2–33 list the external memory interface specifications for
Cyclone III LS devices and are useful when performing memory interface timing
analysis.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–23
Switching Characteristics
f
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Table 2–32. FPGA Sampling Window (SW) Requirement—Read Side (1)
Column I/Os (ps)
Memory Standard
Row I/Os (ps)
Wraparound Mode (ps)
Setup
Hold
Setup
Hold
Setup
Hold
C7
C8
I7
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
705
675
900
650
620
845
770
795
910
715
740
855
985
970
930
915
1085
1030
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
785
800
720
740
990
930
915
870
855
1115
1185
1210
1055
1125
1150
1050
1065
1005
DDR2 SDRAM
DDR SDRAM
765
745
945
710
690
890
855
880
955
800
825
900
1040
1000
1130
985
945
QDRII SRAM
1075
Note to Table 2–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side (1) (Part 1 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory Standard
I/O Standard
Lead
Lag
Lead
Lag
Lead
Lag
C7
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
915
1025
880
410
545
340
380
450
570
915
1025
880
410
545
340
380
450
570
1015
1125
980
510
645
440
480
550
670
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1010
910
1010
910
1010
1010
1110
1010
1010
C8
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
1140
1280
1110
1260
1140
1290
540
700
460
510
590
730
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–24
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side (1) (Part 2 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory Standard
I/O Standard
Lead
Lag
Lead
Lag
Lead
Lag
I7
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
961
1076
924
431
572
357
399
473
599
961
1076
924
431
572
357
399
473
599
1061
1176
1024
1161
1056
1161
531
672
457
499
573
699
DDR2 SDRAM
DDR SDRAM
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1061
956
1061
956
QDRII SRAM
1061
1061
Note to Table 2–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
Table 2–34 lists the Cyclone III LS devices memory ouput clock jitter specifications.
Table 2–34. Cyclone III LS Devices Memory Output Clock Jitter Specifications (1), (2)
Parameter
Clock period jitter
Symbol
tJIT (per)
Min
–125
–200
–150
Max
125
200
150
Unit
ps
Cycle-to-cycle period jitter
Duty cycle jitter
t
JIT (cc)
JIT (duty)
ps
t
ps
Notes to Table 2–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specification
Table 2–35 lists the worst case duty cycle distortion for Cyclone III LS devices.
Table 2–35. Duty Cycle Distortion on Cyclone III LS Devices I/O Pins (1), (2)
C7, I7
C8
Symbol
Output Duty Cycle
Unit
Min
Max
Min
Max
45
55
45
55
%
Notes to Table 2–35:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and I/O element
(IOE) driving the dedicated and general purpose I/O pins.
(2) Cyclone III LS devices meet the DCD specifications at the maximum output toggle rate for each combination of
the I/O standard and current strength.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–25
Switching Characteristics
OCT Calibration Timing Specification
Table 2–36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III LS devices.
Table 2–36. Cyclone III LS Devices Timing Specification for Series OCT with Calibration at Device
(1)
Power-Up
Symbol
Description
Maximum
Unit
Duration of series OCT with
calibration at device power-up
tOCTCAL
20
µs
Note to Table 2–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
Table 2–37 and Table 2–38 list the IOE programmable delay for Cyclone III LS devices.
(1), (2)
Table 2–37. Cyclone III LS Devices IOE Programmable Delay on the Column Pins
Max Offset
Slow Corner
C8
Number
of
setting
Min
Offset
Parameter
Paths Affected
Fast Corner
I7 C7
Unit
C7
I7
Input delay from the pin to the
internal cells
Pad to I/O
dataout to core
7
8
2
0
0
0
1.211 1.314 2.339 2.416 2.397
1.203 1.307 2.387 2.540 2.430
0.518 0.559 1.065 1.151 1.082
ns
ns
ns
Input delay from the pin to the
input register
Pad to I/O input
register
Delay from the output register to I/O output
the output pin
register to pad
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Pad to global
clock network
12
0
0.533 0.56 1.077 1.182 1.087
ns
Notes to Table 2–37:
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins (1), (2)
Max Offset
Number
Min
Offset
Parameter
Paths Affected
of
Fast Corner
I7 C7
Slow Corner
C8
Unit
setting
C7
I7
Input delay from the pin to the
internal cells
Pad to I/O
dataout to core
7
8
2
0
0
0
1.209 1.314 2.352 2.514 2.432
1.207 1.312 2.402 2.558 2.447
0.549 0.595 1.135 1.226 1.151
ns
ns
ns
Input delay from the pin to the
input register
Pad to I/O input
register
Delay from the output register to I/O output
the output pin
register to pad
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–26
Chapter 2: Cyclone III LS Device Datasheet
I/O Timing
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins (1), (2)
Max Offset
Number
Min
Parameter
Paths Affected
of
Fast Corner
I7 C7
Slow Corner
C8
Unit
Offset
setting
C7
I7
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Pad to global
clock network
12
0
0.52 0.54 1.052 1.16 1.061
ns
Notes to Table 2–38:
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
I/O Timing
DirectDrive technology and MultiTrack interconnect ensure predictable performance,
accurate simulation, and accurate timing analysis across all Cyclone III LS device
densities and speed grades.
Use the following methods to determine I/O timing:
■
The Excel-based I/O timing
■
The Quartus II Timing Analyzer
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used before designing the FPGA to get a timing
budget estimation as part of the link timing analysis. The Quartus II Timing Analyzer
provides a more accurate and precise I/O timing data based on the specifics of the
design after place-and-route is complete.
f
f
For more information about the Excel-based I/O timing spreadsheet, refer to the
Cyclone III Devices Literature page on the Altera website.
All specifications are representative of worst-case supply voltage and junction
temperature conditions. Altera characterizes timing delays at the worst-case process,
minimum voltage, and maximum temperature for input register setup time (tSU) and
hold time (tH).
For more information about timing delay from the FPGA output to the receiving
device for system-timing analysis, refer to AN 366: Understanding I/O Output Timing
for Altera Devices.
Glossary
Table 2–39 lists the glossary for this chapter.
Table 2–39. Glossary (Part 1 of 6)
Letter
Term
—
Definitions
A
B
C
—
—
—
—
—
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–27
Glossary
Table 2–39. Glossary (Part 2 of 6)
Letter
Term
—
Definitions
D
E
F
—
—
—
fHSCLK
GCLK
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
Input pin directly to the global clock network.
G
H
GCLK PLL
HSIODR
Input pin to the global clock network through the PLL.
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
VIH
Input Waveforms
for the SSTL
Differential I/O
Standard
I
VSWING
VREF
VIL
TMS
TDI
tJCP
tJPSU_TDI
tJPSU_TMS
tJCH
t JCL
tJPH
TCK
TDO
J
JTAG Waveform
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
K
L
—
—
—
—
—
—
—
—
—
—
M
N
O
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–28
Chapter 2: Cyclone III LS Device Datasheet
Glossary
Table 2–39. Glossary (Part 3 of 6)
Letter
Term
Definitions
The following block diagram highlights the PLL specification parameters.
CLKOUT Pins
fOUT_EXT
Switchover
CLK
fIN
fINPFD
N
fVCO
VCO
PFD
CP
LF
fOUT
GCLK
Counters
Core Clock
C0..C4
P
Q
PLL Block
Phase tap
M
Key
Reconfigurable in User Mode
—
—
RL
Receiver differential input discrete resistor (external to the Cyclone III LS device)
Receiver Input Waveform for LVDS and LVPECL Differential Standards
Single-Ended Waveform
Positive Channel (p) = V
IH
VID
Negative Channel (n) = V
Ground
IL
V
CM
Receiver Input
Waveform
R
Differential Input Waveform
VID
0 V
VID
p - n
RSKM (Receiver
input skew
margin)
High-speed I/O Block: The total margin left after accounting for the sampling window and
TCCS. RSKM = (TUI – SW – TCCS) / 2
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–29
Glossary
Table 2–39. Glossary (Part 4 of 6)
Letter
Term
Definitions
VCCIO
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
Single-ended
Voltage
referenced I/O
Standard
VOL
VSS
S
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■ The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
■ The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
SW (Sampling
Window)
tC
High-speed receiver and transmitter input and output clock period.
TCCS (Channel-
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
to-channel-skew) including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
tCO
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
tcout
tDUTY
tFALL
tH
Delay from the clock pad to the I/O output register.
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
Signal high-to-low transition time (80 to 20%).
Input register hold time.
T
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK
tOUTJITTER_IO
tpllcin
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
tpllcout
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–30
Chapter 2: Cyclone III LS Device Datasheet
Glossary
Table 2–39. Glossary (Part 5 of 6)
Letter
Term
Definitions
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS, and RSDS differential I/O
standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
V
os
Transmitter
Ground
Output Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VOD
0 V
VOD
p − n (1)
tRISE
tSU
Signal low-to-high transition time (20–80%).
Input register setup time.
—
U
—
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
2–31
Glossary
Table 2–39. Glossary (Part 6 of 6)
Letter
Term
VCM(DC)
Definitions
DC common mode input voltage.
AC differential Input Voltage—The minimum AC input differential voltage required for
switching.
VDIF(AC)
DC differential Input Voltage—The minimum DC input differential voltage required for
switching.
VDIF(DC)
VICM
Input Common Mode Voltage—The common mode of the differential signal at the receiver.
Input differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
Voltage Input High—The minimum positive voltage applied to the input that is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage.
High-level DC input voltage.
Voltage Input Low—The maximum positive voltage applied to the input that is accepted by
the device as a logic low.
VIL
VIL (AC)
VIL (DC)
VIN
Low-level AC input voltage.
Low-level DC input voltage.
DC input voltage.
Output Common Mode Voltage—The common mode of the differential signal at the
transmitter.
VOCM
VOD
V
Output differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.
Voltage Output High—The maximum positive voltage from an output that the device
considers will be accepted as the minimum positive high level.
VOH
Voltage Output Low—The maximum positive voltage from an output that the device considers
will be accepted as the maximum positive low level.
VOL
VOS
Output offset voltage—VOS = (VOH + VOL) / 2.
AC differential Output cross point voltage—The voltage at which the differential output signals
must cross.
VOX (AC)
VREF
Reference voltage for the SSTL and HSTL I/O standards.
AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise.
VREF (AC)
VREF (DC)
VSWING (AC)
The peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC)
.
DC input reference voltage for the SSTL and HSTL I/O standards.
AC differential Input Voltage—AC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
DC differential Input Voltage—DC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
VSWING (DC)
VTT
Termination voltage for the SSTL and HSTL I/O standards.
AC differential Input cross point Voltage—The voltage at which the differential input signals
must cross.
VX (AC)
W
X
Y
Z
—
—
—
—
—
—
—
—
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
2–32
Chapter 2: Cyclone III LS Device Datasheet
Document Revision History
Document Revision History
Table 2–40 lists the revision history for this document.
Table 2–40. Document Revision History
Date
Version
Changes
■ Updated minimum fHSCLK value to 5 MHz.
July 2012
1.4
■ Updated absolute maximum TJ to 125 °C in Table 2–1.
■ Finalized all preliminary information.
■ Updated “Supply Current” on page 2–5, “Periphery Performance” on page 2–17, and
“External Memory Interface Specifications” on page 2–22.
December 2011
1.3
■ Updated Table 2–1, Table 2–3, Table 2–13, Table 2–16, Table 2–17, Table 2–20, and
Table 2–25.
■ Updated Table 2–19 through Table 2–34, Table 2–37, and Table 2–38.
■ Updated the “Periphery Performance” on page 2–17 section.
■ Minor changes to the text.
December 2009
1.2
July 2009
June 2009
1.1
1.0
Minor edit to the hyperlinks.
Initial release.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Additional Information
This chapter provides additional information about the document and Altera.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Technical support
Contact Method
Website
Website
Email
Address
www.altera.com/support
www.altera.com/training
custrain@altera.com
Technical training
Product literature
Website
Email
www.altera.com/literature
nacomp@altera.com
Nontechnical support (general)
(software licensing)
Note to Table:
Email
authorization@altera.com
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Meaning
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
Bold Type with Initial Capital
Letters
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
bold type
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.
Indicates variables. For example, n + 1.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Initial Capital Letters
“Subheading Title”
Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
Info–2
Additional Information
Typographic Conventions
Visual Cue
Meaning
Indicates signal, port, register, bit, block, and primitive names. For example, data1
tdi, and input. The suffix denotes an active-low signal. For example, resetn
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf
,
n
.
Courier type
.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
r
An angled arrow instructs you to press the Enter key.
1., 2., 3., and
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
a., b., c., and so on
■
■
■
Bullets indicate a list of items when the sequence of the items is not important.
The hand points to information that requires special attention.
1
h
The question mark directs you to a software help system with related information.
The feet direct you to another document or website with related information.
The multimedia icon directs you to a related multimedia presentation.
f
m
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
c
A warning calls attention to a condition or possible situation that can cause you
injury.
w
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
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