EP3C55U484C8N

更新时间:2024-10-30 00:38:32
品牌:INTEL
描述:Field Programmable Gate Array, 55856 CLBs, 472.5MHz, 55856-Cell, CMOS, PBGA484, 19 X 19 MM, 2.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, UFBGA-484

EP3C55U484C8N 概述

Field Programmable Gate Array, 55856 CLBs, 472.5MHz, 55856-Cell, CMOS, PBGA484, 19 X 19 MM, 2.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, UFBGA-484

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1. Cyclone III Device Datasheet  
July 2012  
CIII52001-3.5  
CIII52001-3.5  
This chapter describes the electric characteristics, switching characteristics, and I/O  
timing for Cyclone® III devices. A glossary is also included for your reference.  
Electrical Characteristics  
The following sections provide information about the absolute maximum ratings,  
recommended operating conditions, DC characteristics, and other specifications for  
Cyclone III devices.  
Operating Conditions  
When Cyclone III devices are implemented in a system, they are rated according to a  
set of defined parameters. To maintain the highest possible performance and  
reliability of Cyclone III devices, system designers must consider the operating  
requirements in this document. Cyclone III devices are offered in commercial,  
industrial, and automotive grades. Commercial devices are offered in –6 (fastest), –7,  
and –8 speed grades. Industrial and automotive devices are offered only in –7 speed  
grade.  
1
In this chapter, a prefix associated with the operating temperature range is attached to  
the speed grades; commercial with “C” prefix, industrial with “I” prefix, and  
automotive with “A” prefix. Commercial devices are therefore indicated as C6, C7,  
and C8 per respective speed grades. Industrial and automotive devices are indicated  
as I7 and A7, respectively.  
Absolute Maximum Ratings  
Absolute maximum ratings define the maximum operating conditions for Cyclone III  
devices. The values are based on experiments conducted with the device and  
theoretical modeling of breakdown and damage mechanisms. The functional  
operation of the device is not implied at these conditions. Table 1–1 lists the absolute  
maximum ratings for Cyclone III devices.  
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos  
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as  
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its  
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and  
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service  
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying  
on any published information and before placing orders for products or services.  
ISO  
9001:2008  
Registered  
Cyclone III Device Handbook  
Volume 2  
July 2012  
Subscribe  
1–2  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
1
Conditions beyond those listed in Table 1–1 cause permanent damage to the device.  
Additionally, device operation at the absolute maximum ratings for extended periods  
of time has adverse effects on the device.  
(1)  
Table 1–1. Cyclone III Devices Absolute Maximum Ratings  
Symbol  
VCCINT  
Parameter  
Supply voltage for internal logic  
Supply voltage for output buffers  
Min  
–0.5  
–0.5  
Max  
1.8  
Unit  
V
VCCIO  
3.9  
V
Supply voltage (analog) for phase-locked loop  
(PLL) regulator  
VCCA  
–0.5  
3.75  
V
VCCD_PLL  
VI  
Supply voltage (digital) for PLL  
DC input voltage  
–0.5  
–0.5  
–25  
1.8  
3.95  
40  
V
V
IOUT  
DC output current, per pin  
mA  
Electrostatic discharge voltage using the human  
body model  
VESDHBM  
VESDCDM  
2000  
500  
V
V
Electrostatic discharge voltage using the  
charged device model  
TSTG  
TJ  
Storage temperature  
–65  
–40  
150  
125  
°C  
°C  
Operating junction temperature  
Note to Table 1–1:  
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the  
power supply.  
Maximum Allowed Overshoot or Undershoot Voltage  
During transitions, input signals may overshoot to the voltage listed in Table 1–2 and  
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods  
shorter than 20 ns. Table 1–2 lists the maximum allowed input overshoot voltage and  
the duration of the overshoot voltage as a percentage over the lifetime of the device.  
The maximum allowed overshoot duration is specified as percentage of high-time  
over the lifetime of the device.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–3  
Electrical Characteristics  
1
A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to  
4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for device lifetime  
of 10 years, this amounts to 10.74/10ths of a year.  
Table 1–2. Cyclone III Devices Maximum Allowed Overshoot During Transitions over a 10-Year  
(1)  
Time Frame  
Symbol  
Parameter  
Condition  
VI = 3.95 V  
VI = 4.0 V  
Overshoot Duration as % of High Time  
Unit  
%
%
%
%
%
%
%
%
%
%
%
%
%
%
100  
95.67  
55.24  
31.97  
18.52  
10.74  
6.23  
VI = 4.05 V  
VI = 4.10 V  
VI = 4.15 V  
VI = 4.20 V  
VI = 4.25 V  
VI = 4.30 V  
VI = 4.35 V  
VI = 4.40 V  
VI = 4.45 V  
VI = 4.50 V  
VI = 4.60 V  
VI = 4.70 V  
AC Input  
Voltage  
Vi  
3.62  
2.1  
1.22  
0.71  
0.41  
0.14  
0.047  
Note to Table 1–2:  
(1) Figure 1–1 shows the methodology to determine the overshoot duration. In the example in Figure 1–1, overshoot  
voltage is shown in red and is present on the input pin of the Cyclone III device at over 4.1 V but below 4.2 V. From  
Table 1–1, for an overshoot of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over  
a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes the  
device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and  
situations in which the device is in an idle state, lifetimes are increased.  
Figure 1–1 shows the methodology to determine the overshoot duration.  
Figure 1–1. Cyclone III Devices Overshoot Duration  
4.2 V  
4.1 V  
3.3 V  
ΔT  
T
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–4  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
Recommended Operating Conditions  
This section lists the functional operation limits for AC and DC parameters for  
Cyclone III devices. The steady-state voltage and current values expected from  
Cyclone III devices are provided in Table 1–3. All supplies must be strictly monotonic  
without plateaus.  
(1), (2)  
Table 1–3. Cyclone III Devices Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
(3)  
VCCINT  
Supply voltage for internal logic  
1.15  
1.2  
1.25  
V
Supply voltage for output buffers, 3.3-V  
operation  
3.135  
2.85  
3.3  
3
3.465  
3.15  
V
V
V
V
V
V
V
Supply voltage for output buffers, 3.0-V  
operation  
Supply voltage for output buffers, 2.5-V  
operation  
2.375  
1.71  
2.5  
1.8  
1.5  
1.2  
2.5  
2.625  
1.89  
(3), (4)  
VCCIO  
Supply voltage for output buffers, 1.8-V  
operation  
Supply voltage for output buffers, 1.5-V  
operation  
1.425  
1.14  
1.575  
1.26  
Supply voltage for output buffers, 1.2-V  
operation  
Supply (analog) voltage for PLL  
regulator  
(3)  
VCCA  
2.375  
2.625  
(3)  
VCCD_PLL  
Supply (digital) voltage for PLL  
Input voltage  
1.15  
–0.5  
0
1.2  
1.25  
3.6  
V
V
VI  
VO  
Output voltage  
VCCIO  
85  
V
For commercial use  
For industrial use  
For extended temperature  
For automotive use  
Standard power-on reset  
0
°C  
°C  
°C  
°C  
–40  
–40  
–40  
100  
125  
125  
TJ  
Operating junction temperature  
50 µs  
50 µs  
50 ms  
3 ms  
10  
(5)  
(POR)  
tRAMP  
Power supply ramp time  
(6)  
Fast POR  
Magnitude of DC current across  
PCI-clamp diode when enabled  
IDiode  
mA  
Notes to Table 1–3:  
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and  
must be powered up and powered down at the same time.  
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.  
(3) The VCC must rise monotonically.  
(4) All input buffers are powered by the VCCIO supply.  
(5) POR time for Standard POR ranges between 50–200 ms. Each individual power supply should reach the recommended operating range within  
50 ms.  
(6) POR time for Fast POR ranges between 3–9 ms. Each individual power supply should reach the recommended operating range within 3 ms.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–5  
Electrical Characteristics  
DC Characteristics  
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)  
tolerance, and bus hold specifications for Cyclone III devices.  
Supply Current  
Standby current is the current the device draws after the device is configured with no  
inputs or outputs toggling and no activity in the device. Use the Excel-based early  
power estimator (EPE) to get the supply current estimates for your design because  
these currents vary largely with the resources used. Table 1–4 lists I/O pin leakage  
current for Cyclone III devices.  
f
For more information about power estimation tools, refer to the PowerPlay Early Power  
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II  
Handbook.  
Table 1–4. Cyclone III Devices I/O Pin Leakage Current (1), (2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
II  
Input pin leakage current  
VI = 0 V to VCCIOMAX  
–10  
10  
A  
Tristated I/O pin leakage  
current  
IOZ  
VO = 0 V to VCCIOMAX  
–10  
10  
A  
Notes to Table 1–4:  
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all  
CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).  
V
(2) 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the  
observed when the diode is on.  
Bus Hold  
Bus hold retains the last valid logic state after the source driving it either enters the  
high impedance state or is removed. Each I/O pin has an option to enable bus hold in  
user mode. Bus hold is always disabled in configuration mode.  
Table 1–5 lists bus hold specifications for Cyclone III devices.  
(1)  
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 1 of 2)  
V
CCIO (V)  
Parameter  
Condition  
1.2  
1.5  
1.8  
2.5  
3.0  
3.3  
Unit  
Min Max Min  
Max Min Max Min Max Min Max Min Max  
Bus-hold  
low,  
sustaining  
current  
VIN > VIL  
(maximum)  
8
12  
30  
50  
70  
70  
A  
A  
Bus-hold  
high,  
sustaining  
current  
VIN < VIL  
(minimum)  
–8  
–12  
–30  
–50  
–70  
–70  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–6  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
(1)  
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 2 of 2)  
V
CCIO (V)  
Parameter  
Condition  
1.2  
1.5  
1.8  
2.5  
3.0  
3.3  
Unit  
Min Max Min  
Max Min Max Min Max Min Max Min Max  
Bus-hold  
low,  
overdrive  
current  
0 V < VIN < VCCIO  
125  
175  
200  
300  
500  
500  
A  
Bus-hold  
high,  
overdrive  
current  
0 V < VIN < VCCIO  
–125  
–175  
–200  
–300  
1.7  
–500  
2
–500 A  
Bus-holdtrip  
point  
0.3  
0.9 0.375 1.125 0.68 1.07 0.7  
0.8  
0.8  
2
V
Note to Table 1–5:  
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.  
OCT Specifications  
Table 1–6 lists the variation of OCT without calibration across process, temperature,  
and voltage.  
Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications  
Resistance Tolerance  
Description  
V
CCIO (V)  
Unit  
Commercial  
Max  
Industrial and Automotive  
Max  
3.0  
2.5  
1.8  
1.5  
1.2  
30  
30  
40  
40  
50  
50  
50  
%
%
%
%
%
Series OCT without  
calibration  
+40  
+50  
+50  
OCT calibration is automatically performed at device power-up for OCT enabled  
I/Os.  
Table 1–7 lists the OCT calibration accuracy at device power-up.  
Table 1–7. Cyclone III Devices Series OCT with Calibration at Device Power-Up Specifications  
Calibration Accuracy  
Description  
VCCIO (V)  
Unit  
Industrial and Automotive  
Max  
Commercial Max  
3.0  
2.5  
1.8  
1.5  
1.2  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
%
%
%
%
%
Series OCT with  
calibration at device  
power-up  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–7  
Electrical Characteristics  
The OCT resistance may vary with the variation of temperature and voltage after  
calibration at device power-up. Use Table 1–8 and Equation 1–1 to determine the final  
OCT resistance considering the variations after calibration at device power-up.  
Table 1–8 lists the change percentage of the OCT resistance with voltage and  
temperature.  
Table 1–8. Cyclone III Devices OCT Variation After Calibration at Device Power-Up  
Nominal Voltage  
dR/dT (%/°C)  
0.262  
dR/dV (%/mV)  
–0.026  
3.0  
2.5  
1.8  
1.5  
1.2  
0.234  
–0.039  
0.219  
–0.086  
0.199  
–0.136  
0.161  
–0.288  
(1), (2), (3), (4), (5), (6)  
Equation 1–1.  
(7)  
RV = (V2 – V1) × 1000 × dR/dV  
(8)  
RT = (T2 – T1) × dR/dT  
(9)  
For Rx < 0; MFx = 1/ (|Rx|/100 + 1)  
(10)  
For Rx > 0; MFx = Rx/100 + 1  
(11)  
MF = MFV × MFT  
(12)  
Rfinal = Rinitial × MF  
Notes to Equation 1–1:  
(1) T2 is the final temperature.  
(2) T1 is the initial temperature.  
(3) MF is multiplication factor.  
(4) Rfinal is final resistance.  
(5) Rinitial is initial resistance.  
(6) Subscript × refers to both V and T.  
(7) RV is variation of resistance with voltage.  
(8) RT is variation of resistance with temperature.  
(9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up.  
(10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up.  
(11) V2 is final voltage.  
(12) V1 is the initial voltage.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–8  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
Example 1–1 shows you the example to calculate the change of 50 I/O impedance  
from 25°C at 3.0 V to 85°C at 3.15 V:  
Example 1–1.  
RV = (3.15 – 3) × 1000 × –0.026 = –3.83  
RT = (85 – 25) × 0.262 = 15.72  
Because RV is negative,  
MFV = 1 / (3.83/100 + 1) = 0.963  
Because RT is positive,  
MFT = 15.72/100 + 1 = 1.157  
MF = 0.963 × 1.157 = 1.114  
R
final = 50 × 1.114 = 55.71   
Pin Capacitance  
Table 1–9 lists the pin capacitance for Cyclone III devices.  
Table 1–9. Cyclone III Devices Pin Capacitance  
Typical – Typical –  
Symbol  
Parameter  
Unit  
QFP  
FBGA  
CIOTB  
CIOLR  
Input capacitance on top/bottom I/O pins  
Input capacitance on left/right I/O pins  
7
6
5
pF  
pF  
7
Input capacitance on left/right I/O pins with dedicated  
LVDS output  
CLVDSLR  
8
7
pF  
pF  
pF  
CVREFLR  
Input capacitance on left/right dual-purpose VREF pin  
when used as VREF or user I/O pin  
21  
21  
(1)  
CVREFTB  
Input capacitance on top/bottom dual-purpose VREF pin  
when used as VREF or user I/O pin  
(2)  
(2)  
23  
23  
(1)  
Input capacitance on top/bottom dedicated clock input  
pins  
CCLKTB  
CCLKLR  
7
6
6
5
pF  
pF  
Input capacitance on left/right dedicated clock input pins  
Notes to Table 1–9:  
(1) When VREF pin is used as regular input or output, a reduced performance of toggle rate and tCO is expected due to  
higher pin capacitance.  
(2) CVREFTB for EP3C25 is 30 pF.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–9  
Electrical Characteristics  
Internal Weak Pull-Up and Weak Pull-Down Resistor  
Table 1–10 lists the weak pull-up and pull-down resistor values for Cyclone III  
devices.  
(1)  
Table 1–10. Cyclone III Devices Internal Weak Pull-Up and Weak Pull-Down Resistor  
Symbol  
Parameter  
Conditions  
Min  
7
Typ  
25  
28  
35  
57  
82  
143  
19  
22  
25  
35  
50  
Max  
41  
Unit  
(2), (3)  
VCCIO = 3.3 V 5%  
k  
k  
k  
k  
k  
k  
k  
k  
k  
k  
k  
(2), (3)  
(2), (3)  
(2), (3)  
(2), (3)  
(2), (3)  
(4)  
V
V
CCIO = 3.0 V 5%  
CCIO = 2.5 V 5%  
7
47  
Value of I/O pin pull-up resistor before  
and during configuration, as well as  
user mode if the programmable  
pull-up resistor option is enabled  
8
61  
R_PU  
VCCIO = 1.8 V 5%  
10  
13  
19  
6
108  
163  
351  
30  
V
V
V
V
V
V
V
CCIO = 1.5 V 5%  
CCIO = 1.2 V 5%  
CCIO = 3.3 V 5%  
CCIO = 3.0 V 5%  
CCIO = 2.5 V 5%  
CCIO = 1.8 V 5%  
CCIO = 1.5 V 5%  
(4)  
6
36  
Value of I/O pin pull-down resistor  
before and during configuration  
(4)  
R_PD  
6
43  
(4)  
7
71  
(4)  
8
112  
Notes to Table 1–10:  
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pin. Weak pull-down feature is only available for JTAG  
TCK.  
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO  
.
(3) R_PU = (VCCIO – VI)/IR_PU  
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;  
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;  
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.  
(4) R_PD = VI/IR_PD  
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;  
Typical condition: 25°C; VCCIO = VCC, VI = VCC – 5%;  
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.  
Hot Socketing  
Table 1–11 lists the hot-socketing specifications for Cyclone III devices.  
Table 1–11. Cyclone III Devices Hot-Socketing Specifications  
Symbol  
IIOPIN(DC)  
Parameter  
Maximum  
DC current per I/O pin  
AC current per I/O pin  
300 A  
(1)  
IIOPIN(AC)  
8 mA  
Note to Table 1–11:  
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C  
dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–10  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
Schmitt Trigger Input  
Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,  
nCE  
,
CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the  
input signal for improved noise immunity, especially for signal with slow edge rate.  
Table 1–12 lists the hysteresis specifications across supported VCCIO range for Schmitt  
trigger inputs in Cyclone III devices.  
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices  
Symbol  
Parameter  
Conditions  
Minimum  
200  
Typical  
Maximum  
Unit  
mV  
mV  
mV  
mV  
VCCIO = 3.3 V  
V
V
CCIO = 2.5 V  
CCIO = 1.8 V  
200  
Hysteresis for Schmitt trigger  
input  
VSCHMITT  
140  
VCCIO = 1.5 V  
110  
I/O Standard Specifications  
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH  
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards  
supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O  
standard specifications for Cyclone III devices.  
(1), (2)  
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications  
VCCIO (V)  
VIL (V)  
VIH (V)  
Max  
VOL (V)  
VOH (V)  
IOL  
IOH  
I/O Standard  
(mA)  
(mA)  
Min  
3.135  
3.135  
2.85  
Typ  
3.3  
3.3  
3.0  
3.0  
Max  
3.465  
3.465  
Min  
Max  
0.8  
0.8  
0.8  
0.8  
Min  
1.7  
1.7  
1.7  
1.7  
Max  
0.45  
0.2  
Min  
2.4  
(3)  
3.3-V LVTTL  
3.6  
4
2
–4  
–2  
(3)  
(3)  
3.3-V LVCMOS  
3.6  
VCCIO – 0.2  
2.4  
(3)  
3.0-V LVTTL  
3.15 –0.3  
3.15 –0.3  
VCCIO + 0.3  
VCCIO + 0.3  
0.45  
0.2  
4
–4  
3.0-V LVCMOS  
2.85  
VCCIO – 0.2  
0.1  
–0.1  
2.5-V LVTTL and  
LVCMOS  
2.375  
1.71  
1.425  
1.14  
2.85  
2.85  
2.5  
1.8  
1.5  
1.2  
3.0  
3.0  
2.625 –0.3  
1.89 –0.3  
1.575 –0.3  
1.26 –0.3  
0.7  
1.7  
3.6  
0.4  
2.0  
1
2
–1  
–2  
(3)  
1.8-V LVTTL and  
LVCMOS  
0.35 * 0.65 *  
VCCIO VCCIO  
VCCIO  
0.45  
2.25  
0.45  
0.35 * 0.65 *  
VCCIO VCCIO  
0.25 *  
VCCIO  
0.75 *  
VCCIO  
1.5-V LVCMOS  
1.2-V LVCMOS  
3.0-V PCI  
VCCIO + 0.3  
VCCIO + 0.3  
2
–2  
0.35 * 0.65 *  
VCCIO  
0.25 *  
VCCIO  
0.75 *  
VCCIO  
2
–2  
VCCIO  
0.3 *  
VCCIO  
0.5 *  
VCCIO  
3.15  
3.15  
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO  
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO  
1.5  
1.5  
–0.5  
–0.5  
0.35*  
VCCIO  
0.5 *  
VCCIO  
3.0-V PCI-X  
Notes to Table 1–13:  
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/O Standard”  
in “Glossary” on page 1–27.  
(2) AC load CL = 10 pF.  
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III  
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
1–11  
Max  
(1)  
Table 1–14. Cyclone III Devices Single-Ended SSTL and HSTL I/O Reference Voltage Specifications  
(2)  
V
CCIO (V)  
Typ  
VREF (V)  
Typ  
VTT (V)  
I/O  
Standard  
Min  
Max  
Min  
Max  
Min  
Typ  
SSTL-2  
Class I, II  
VREF  
0.04  
VREF  
0.04  
+
2.375 2.5 2.625  
1.19  
1.25  
0.9  
1.31  
VREF  
SSTL-18  
Class I, II  
VREF  
0.04  
VREF  
0.04  
+
1.7  
1.8  
1.8  
1.9  
0.833  
0.85  
0.71  
0.969  
0.95  
0.79  
VREF  
0.9  
HSTL-18  
Class I, II  
1.71  
1.89  
0.9  
0.85  
0.71  
0.95  
0.79  
HSTL-15  
Class I, II  
1.425 1.5 1.575  
0.75  
0.75  
(3)  
(4)  
(3)  
(4)  
(3)  
(4)  
0.48 * VCCIO  
0.47 * VCCIO  
0.5 * VCCIO  
0.5 * VCCIO  
0.52 * VCCIO  
0.53 * VCCIO  
HSTL-12  
Class I, II  
0.5 *  
VCCIO  
1.14  
1.2  
1.26  
Notes to Table 1–14:  
(1) For an explanation of terms used in Table 1–14, refer to “Glossary” on page 1–27.  
(2) VTT of transmitting device must track VREF of the receiving device.  
(3) Value shown refers to DC input reference voltage, VREF(DC)  
(4) Value shown refers to AC input reference voltage, VREF(AC)  
.
.
Table 1–15. Cyclone III Devices Single-Ended SSTL and HSTL I/O Standards Signal Specifications  
VIL(DC) (V)  
Min Max  
VREF  
VIH(DC) (V)  
Max  
VIL(AC) (V)  
Min Max  
VREF  
VIH(AC) (V)  
Min Max  
VOL (V)  
Max  
VOH (V)  
Min  
I/O  
IOL  
IOH  
Standard  
(mA) (mA)  
Min  
SSTL-2  
Class I  
VREF  
0.18  
+
VREF  
0.35  
+
VTT  
VTT  
+
8.1  
16.4 –16.4  
6.7 –6.7  
13.4 –13.4  
–8.1  
0.18  
0.35  
0.57  
0.57  
SSTL-2  
Class II  
VREF  
0.18  
VREF  
0.18  
+
VREF  
VREF  
0.35  
+
VTT  
VTT  
+
0.35  
0.76  
0.76  
SSTL-18  
Class I  
VREF  
0.125  
VREF  
+
VREF  
VREF  
0.25  
+
VTT  
VTT +  
0.475  
0.125  
0.25  
0.475  
SSTL-18  
Class II  
VREF  
0.125  
VREF  
+
VREF  
VREF  
0.25  
+
VCCIO  
0.28  
0.4  
0.4  
0.4  
0.4  
0.125  
0.25  
0.28  
HSTL-18  
Class I  
VREF  
0.1  
VREF  
0.1  
+
+
+
+
+
VREF  
0.2  
VREF  
0.2  
+
VCCIO  
0.4  
8
16  
8
–8  
–16  
–8  
HSTL-18  
Class II  
VREF  
0.1  
VREF  
0.1  
VREF  
0.2  
VREF  
0.2  
+
+
+
+
VCCIO  
0.4  
HSTL-15  
Class I  
VREF  
0.1  
VREF  
0.1  
VREF  
0.2  
VREF  
0.2  
VCCIO  
0.4  
HSTL-15  
Class II  
VREF  
0.1  
VREF  
0.1  
VREF  
0.2  
VREF  
0.2  
VCCIO  
0.4  
16  
8
–16  
–8  
HSTL-12  
Class I  
VREF  
0.08  
VREF  
0.08  
VREF  
VREF  
VCCIO  
+
+
0.25 ×  
VCCIO  
0.75 ×  
VCCIO  
–0.15  
–0.15  
V
V
CCIO + 0.15 –0.24  
CCIO + 0.15 –0.24  
0.15  
0.15  
0.24  
HSTL-12  
Class II  
VREF  
0.08  
VREF  
0.08  
+
VREF  
VREF  
+
VCCIO  
0.24  
0.25 ×  
VCCIO  
0.75 ×  
VCCIO  
14  
–14  
0.15  
0.15  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–12  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
f
For more illustrations of receiver input and transmitter output waveforms, and for  
other differential I/O standards, refer to the High-Speed Differential Interfaces in  
Cyclone III Devices chapter.  
Table 1–16. Cyclone III Devices Differential SSTL I/O Standard Specifications (1)  
VSwing(AC)  
(V)  
VCCIO (V)  
VSwing(DC) (V)  
VX(AC) (V)  
Typ  
VOX(AC) (V)  
Typ  
I/O Standard  
Min Typ Max Min Max  
Min  
Max  
Min Max  
Min  
Max  
SSTL-2  
Class I, II  
V
+ 0.2  
CCIO/2  
VCCI  
0.7  
VCCIO/2 –  
0.125  
V
CCIO/2  
2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2  
VCCIO/2 –  
+ 0.125  
O
SSTL-18  
Class I, II  
V
CCIO/2  
VCCI  
0.5  
VCCIO/2 –  
0.125  
VCCIO/2  
+ 0.125  
1.7  
1.8 1.90 0.25 VCCIO  
0.175  
+ 0.175  
O
Note to Table 1–16:  
(1) Differential SSTL requires a VREF input.  
Table 1–17. Cyclone III Devices Differential HSTL I/O Standard Specifications (1)  
V
CCIO (V)  
VDIF(DC) (V)  
VX(AC) (V)  
Typ  
VCM(DC) (V)  
Typ  
VDIF(AC) (V)  
I/O Standard  
Mi  
Min Typ Max Min Max  
Min  
0.85  
0.71  
Max  
0.95  
0.79  
Min  
0.85  
0.71  
Max  
0.95  
0.79  
Max  
n
HSTL-18  
Class I, II  
1.71 1.8 1.89 0.2  
1.425 1.5 1.575 0.2  
0.4  
HSTL-15  
Class I, II  
0.4  
0.3  
HSTL-12  
Class I, II  
0.52 *  
VCCIO  
0.48 *  
VCCIO  
0.52 *  
VCCIO  
0.48 *  
VCCIO  
1.14 1.2 1.26 0.16 VCCIO 0.48 * VCCIO  
Note to Table 1–17:  
(1) Differential HSTL requires a VREF input.  
(1)  
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications  
(Part 1 of 2)  
VOD (mV)  
Max Min Typ Max Min Typ Max  
(2)  
(3)  
(3)  
V
CCIO (V)  
VID (mV)  
VIcM (V)  
VOS (V)  
I/O  
Standard  
Min Typ Max  
Min Max Min  
Condition  
0.05  
DMAX500 Mbps 1.80  
LVPECL  
500 Mbps DMAX  
700 Mbps  
(Row I/Os) 2.375 2.5 2.625 100  
0.55  
1.80  
1.55  
(4)  
1.05 DMAX > 700 Mbps  
0.05  
DMAX 500 Mbps 1.80  
LVPECL  
500 Mbps DMAX  
700 Mbps  
(Column  
2.375 2.5 2.625 100  
2.375 2.5 2.625 100  
0.55  
1.80  
(4)  
I/Os)  
1.05  
0.05  
DMAX > 700 Mbps  
1.55  
DMAX 500 Mbps 1.80  
LVDS (Row  
I/Os)  
500 Mbps DMAX  
700 Mbps  
0.55  
1.05  
1.80 247  
1.55  
600 1.125 1.25 1.375  
DMAX > 700 Mbps  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–13  
Electrical Characteristics  
(1)  
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications  
(Part 2 of 2)  
VOD (mV)  
(2)  
(3)  
(3)  
VCCIO (V)  
VID (mV)  
VIcM (V)  
VOS (V)  
I/O  
Standard  
Min Typ Max  
Min Max Min  
Condition  
Max Min Typ Max Min Typ Max  
0.05  
DMAX 500 Mbps 1.80  
LVDS  
(Column  
I/Os)  
500 Mbps DMAX  
700 Mbps  
2.375 2.5 2.625 100  
0.55  
1.05  
1.80 247  
1.55  
600 1.125 1.25 1.375  
DMAX > 700 Mbps  
BLVDS  
(Row I/Os) 2.375 2.5 2.625 100  
(5)  
BLVDS  
(Column  
2.375 2.5 2.625 100  
(5)  
I/Os)  
mini-LVDS  
(Row I/Os) 2.375 2.5 2.625  
300  
300  
600  
600  
1.0  
1.0  
0.5  
0.5  
0.5  
0.5  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.5  
1.5  
1.4  
1.4  
(6)  
mini-LVDS  
(Column  
2.375 2.5 2.625  
2.375 2.5 2.625  
2.375 2.5 2.625  
(6)  
I/Os)  
RSDS®  
(Row  
100 200 600  
100 200 600  
100 200 600  
100 200 600  
I/Os) (6)  
RSDS  
(Column  
(6)  
I/Os)  
PPDS®  
(Row I/Os) 2.375 2.5 2.625  
(6)  
PPDS  
(Column  
2.375 2.5 2.625  
(6)  
I/Os)  
Notes to Table 1–18:  
(1) For an explanation of terms used in Table 1–18, refer to “Transmitter Output Waveform” in “Glossary” on page 1–27.  
(2) VIN range: 0 V VIN 1.85 V.  
(3) RL range: 90 RL 110 .  
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.  
(5) No fixed VIN, VOD, and VOS specifications for BLVDS. They are dependent on the system topology.  
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–14  
Chapter 1: Cyclone III Device Datasheet  
Switching Characteristics  
Power Consumption  
You can use the following methods to estimate power for a design:  
the Excel-based EPE.  
the Quartus II PowerPlay power analyzer feature.  
The interactive Excel-based EPE is used prior to designing the device to get a  
magnitude estimate of the device power. The Quartus II PowerPlay power analyzer  
provides better quality estimates based on the specifics of the design after place-and-  
route is complete. The PowerPlay power analyzer can apply a combination of user-  
entered, simulation-derived, and estimated signal activities which, combined with  
detailed circuit models, can yield very accurate power estimates.  
f
For more information about power estimation tools, refer to the Early Power Estimator  
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II  
Handbook.  
Switching Characteristics  
This section provides the performance characteristics of the core and periphery blocks  
for Cyclone III devices. All data is final and is based on actual silicon characterization  
and testing. These numbers reflect the actual performance of the device under  
worst-case silicon process, voltage, and junction temperature conditions.  
Core Performance Specifications  
Clock Tree Specifications  
Table 1–19 lists the clock tree specifications for Cyclone III devices.  
Table 1–19. Cyclone III Devices Clock Tree Performance  
Performance  
Device  
Unit  
C6  
C7  
C8  
EP3C5  
500  
500  
500  
500  
500  
500  
437.5  
437.5  
437.5  
437.5  
437.5  
437.5  
437.5  
437.5  
402  
402  
402  
402  
402  
402  
402  
402  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
EP3C10  
EP3C16  
EP3C25  
EP3C40  
EP3C55  
EP3C80  
500  
(1)  
EP3C120  
Note to Table 1–19:  
(1) EP3C120 offered in C7, C8, and I7 grades only.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–15  
Switching Characteristics  
PLL Specifications  
Table 1–20 describes the PLL specifications for Cyclone III devices when operating in  
the commercial junction temperature range (0°C to 85°C), the industrial junction  
temperature range (–40°C to 100°C), and the automotive junction temperature range  
(–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in  
“Glossary” on page 1–27.  
Table 1–20. Cyclone III Devices PLL Specifications (1)  
(Part 1 of 2)  
Parameter  
Symbol  
Min  
5
Typ  
Max  
472.5  
325  
Unit  
MHz  
MHz  
MHz  
%
(2)  
fIN  
fINPFD  
Input clock frequency  
PFD input frequency  
5
(3)  
fVCO  
PLL internal VCO operating range  
600  
40  
1300  
60  
fINDUTY  
Input clock duty cycle  
Input clock cycle-to-cycle jitter for FINPFD 100 MHz  
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz  
0.15  
750  
UI  
(4)  
tINJITTER_CCJ  
ps  
f
OUT_EXT (external clock output)  
PLL output frequency  
472.5  
MHz  
(2)  
PLL output frequency (–6 speed grade)  
45  
50  
472.5  
450  
402.5  
55  
MHz  
MHz  
MHz  
%
fOUT (to global clock)  
PLL output frequency (–7 speed grade)  
PLL output frequency (–8 speed grade)  
tOUTDUTY  
tLOCK  
Duty cycle for external clock output (when set to 50%)  
Time required to lock from end of device configuration  
1
ms  
Time required to lock dynamically (after switchover,  
reconfiguring any non-post-scale counters/delays or  
areset is deasserted)  
tDLOCK  
1
ms  
Dedicated clock output period jitter  
300  
30  
ps  
mUI  
ps  
(5)  
F
OUT 100 MHz  
tOUTJITTER_PERIOD_DEDCLK  
F
OUT < 100 MHz  
Dedicated clock output cycle-to-cycle jitter  
300  
30  
(5)  
F
OUT 100 MHz  
tOUTJITTER_CCJ_DEDCLK  
F
OUT < 100 MHz  
mUI  
ps  
Regular I/O period jitter  
650  
75  
(5)  
F
OUT 100 MHz  
tOUTJITTER_PERIOD_IO  
F
OUT < 100 MHz  
mUI  
ps  
Regular I/O cycle-to-cycle jitter  
650  
(5)  
F
OUT 100 MHz  
tOUTJITTER_CCJ_IO  
F
OUT < 100 MHz  
10  
75  
50  
mUI  
ps  
tPLL_PSERR  
tARESET  
Accuracy of PLL phase shift  
Minimum pulse width on areset signal.  
ns  
SCANCLK  
cycles  
(6)  
tCONFIGPLL  
Time required to reconfigure scan chains for PLLs  
3.5  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–16  
Chapter 1: Cyclone III Device Datasheet  
Switching Characteristics  
Table 1–20. Cyclone III Devices PLL Specifications (1)  
Symbol  
(Part 2 of 2)  
Parameter  
Min  
Typ  
Max  
Unit  
fSCANCLK  
scanclk frequency  
100  
MHz  
Notes to Table 1–20:  
(1) VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.  
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.  
(3) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale  
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.  
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.  
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic  
jitter of the PLL, when an input jitter of 30 ps is applied.  
(6) With 100 MHz scanclk frequency.  
Embedded Multiplier Specifications  
Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.  
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications  
Resources Used  
Performance  
C7, I7, A7  
Mode  
9 × 9-bit  
Unit  
Number of Multipliers  
C6  
C8  
1
1
340  
300  
250  
260  
MHz  
MHz  
multiplier  
18 × 18-bit  
multiplier  
287  
200  
Memory Block Specifications  
Table 1–22 describes the M9K memory block specifications for Cyclone III devices.  
Table 1–22. Cyclone III Devices Memory Block Performance Specifications  
Resources Used  
Performance  
Memory  
Mode  
M9K  
LEs  
C6  
C7, I7, A7  
C8  
Unit  
Memory  
FIFO 256 × 36  
47  
0
1
1
1
1
315  
315  
315  
315  
274  
274  
274  
274  
238  
238  
238  
238  
MHz  
MHz  
MHz  
MHz  
Single-port 256 × 36  
M9K Block  
Simple dual-port 256 × 36 CLK  
True dual port 512 × 18 single CLK  
0
0
Configuration and JTAG Specifications  
Table 1–23 lists the configuration mode specifications for Cyclone III devices.  
Table 1–23. Cyclone III Devices Configuration Mode Specifications  
Programming Mode  
Passive Serial (PS)  
DCLK Fmax  
133  
Unit  
MHz  
MHz  
(1)  
Fast Passive Parallel (FPP)  
100  
Note to Table 1–23:  
(1) EP3C40 and smaller density members support 133 MHz.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–17  
Switching Characteristics  
Table 1–24 lists the active configuration mode specifications for Cyclone III devices.  
Table 1–24. Cyclone III Devices Active Configuration Mode Specifications  
Programming Mode  
Active Parallel (AP)  
Active Serial (AS)  
DCLK Range  
20 – 40  
Unit  
MHz  
MHz  
20 – 40  
Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.  
(1)  
Table 1–25. Cyclone III Devices JTAG Timing Parameters  
Symbol  
tJCP  
Parameter  
Min  
40  
20  
20  
1
Max  
15  
15  
15  
25  
25  
25  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCK clock period  
tJCH  
TCK clock high time  
TCK clock low time  
tJCL  
tJPSU_TDI JTAG port setup time for TDI  
tJPSU_TMS JTAG port setup time for TMS  
3
tJPH  
JTAG port hold time  
10  
5
tJPCO  
tJPZX  
tJPXZ  
tJSSU  
tJSH  
JTAG port clock to output (2)  
JTAG port high impedance to valid output (2)  
JTAG port valid output to high impedance (2)  
Capture register setup time  
Capture register hold time  
10  
tJSCO  
tJSZX  
tJSXZ  
Update register clock to output  
Update register high impedance to valid output  
Update register valid output to high impedance  
Notes to Table 1–25:  
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27.  
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS  
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.  
Periphery Performance  
This section describes periphery performance, including high-speed I/O, external  
memory interface, and IOE programmable delay.  
I/O performance supports several system interfacing, for example, the high-speed  
I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using  
the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM  
interfacing speeds with typical DDR SDRAM memory interface setup. I/O using  
general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are  
capable of a typical 200 MHz interfacing frequency with a 10 pF load.  
1
Actual achievable frequency depends on design- and system-specific factors. Perform  
HSPICE/IBIS simulations based on your specific design and system setup to  
determine the maximum achievable frequency in your system.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–18  
Chapter 1: Cyclone III Device Datasheet  
Switching Characteristics  
High-Speed I/O Specifications  
Table 1–26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.  
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27.  
(1), (2)  
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications  
C6  
C7, I7  
C8, A7  
Min Typ Max  
Symbol  
Modes  
Unit  
Min Typ Max Min Typ  
Max  
155.5  
155.5  
155.5  
155.5  
155.5  
311  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
5
5
180  
180  
180  
180  
180  
360  
360  
360  
360  
360  
360  
360  
55  
5
5
5
5
155.5 MHz  
155.5 MHz  
155.5 MHz  
155.5 MHz  
155.5 MHz  
fHSCLK  
(input clock  
frequency)  
5
5
5
5
5
5
5
5
5
5
5
5
311  
MHz  
100  
80  
70  
40  
20  
10  
45  
100  
80  
70  
40  
20  
10  
45  
311  
100  
80  
70  
40  
20  
10  
45  
311 Mbps  
311 Mbps  
311 Mbps  
311 Mbps  
311 Mbps  
311 Mbps  
311  
311  
Device operation in  
Mbps  
311  
311  
311  
tDUTY  
55  
55  
%
TCCS  
200  
200  
200  
ps  
Output jitter  
(peak to peak)  
500  
500  
550  
ps  
ps  
20 – 80%, CLOAD  
5 pF  
=
=
tRISE  
tFALL  
500  
500  
500  
20 – 80%, CLOAD  
5 pF  
500  
1
500  
1
500  
1
ps  
(3)  
tLOCK  
ms  
Notes to Table 1–26:  
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.  
(2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output  
pin of all I/O banks.  
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.  
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 1 of 2)  
C6  
C7, I7  
C8, A7  
Symbol  
Modes  
Unit  
Min  
5
Typ  
Max  
85  
Min  
5
Typ  
Max  
85  
Min  
5
Typ  
Max  
85  
×10  
×8  
×7  
×4  
×2  
×1  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
5
85  
5
85  
5
85  
fHSCLK (input  
clock  
frequency)  
5
85  
5
85  
5
85  
5
85  
5
85  
5
85  
5
85  
5
85  
5
85  
5
170  
5
170  
5
170  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–19  
Switching Characteristics  
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 2 of 2)  
C6  
C7, I7  
C8, A7  
Symbol  
Modes  
Unit  
Min  
100  
80  
Typ  
Max  
170  
170  
170  
170  
170  
170  
55  
Min  
100  
80  
Typ  
Max  
170  
170  
170  
170  
170  
170  
55  
Min  
100  
80  
Typ  
Max  
170  
170  
170  
170  
170  
170  
55  
×10  
×8  
×7  
×4  
×2  
×1  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
Device  
operation in  
Mbps  
70  
70  
70  
40  
40  
40  
20  
20  
20  
10  
10  
10  
tDUTY  
45  
45  
45  
TCCS  
200  
200  
200  
ps  
Output jitter  
(peak to  
peak)  
500  
500  
550  
ps  
ps  
20 – 80%,  
tRISE  
500  
500  
500  
C
LOAD = 5 pF  
20 – 80%,  
tFALL  
500  
1
500  
1
500  
1
ps  
C
LOAD = 5 pF  
(2)  
tLOCK  
ms  
Notes to Table 1–27:  
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.  
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.  
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 1 of 2)  
C6  
C7, I7  
C8, A7  
Symbol  
Modes  
Unit  
Min  
5
Typ  
Max  
200  
200  
200  
200  
200  
400  
400  
400  
400  
400  
400  
400  
55  
Min  
5
Typ  
Max  
155.5  
155.5  
155.5  
155.5  
155.5  
311  
Min  
5
Typ  
Max  
155.5  
155.5  
155.5  
155.5  
155.5  
311  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
5
5
5
f
HSCLK (input  
clock  
frequency)  
5
5
5
5
5
5
5
5
5
5
5
5
100  
80  
70  
40  
20  
10  
45  
100  
80  
70  
40  
20  
10  
45  
311  
100  
80  
70  
40  
20  
10  
45  
311  
311  
311  
Device  
operation in  
Mbps  
311  
311  
311  
311  
311  
311  
311  
311  
tDUTY  
55  
55  
TCCS  
200  
200  
200  
ps  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–20  
Chapter 1: Cyclone III Device Datasheet  
Switching Characteristics  
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 2 of 2)  
C6  
C7, I7  
Typ  
C8, A7  
Typ  
Symbol  
Modes  
Unit  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
Output jitter  
(peak to  
peak)  
500  
500  
550  
ps  
ps  
20 – 80%,  
tRISE  
500  
500  
500  
C
LOAD = 5 pF  
20 – 80%,  
tFALL  
500  
1
500  
1
500  
1
ps  
C
LOAD = 5 pF  
(3)  
tLOCK  
ms  
Notes to Table 1–28:  
(1) Applicable for true and emulated mini-LVDS transmitter.  
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported  
at the output pin of all I/O banks.  
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–21  
Switching Characteristics  
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications (1)  
C6  
C7, I7  
Min  
C8, A7  
Min  
Symbol  
Modes  
Unit  
Min  
5
Max  
420  
420  
420  
420  
420  
420  
840  
840  
840  
840  
840  
420  
55  
Max  
370  
370  
370  
370  
370  
402.5  
740  
740  
740  
740  
740  
402.5  
55  
Max  
320  
320  
320  
320  
320  
402.5  
640  
640  
640  
640  
640  
402.5  
55  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
5
5
5
5
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
5
5
5
5
f
HSCLK (input  
clock frequency)  
5
5
5
5
5
5
5
5
5
100  
80  
70  
40  
20  
10  
45  
100  
80  
70  
40  
20  
10  
45  
100  
80  
70  
40  
20  
10  
45  
HSIODR  
tDUTY  
TCCS  
200  
200  
200  
ps  
Output jitter  
(peak to peak)  
500  
1
500  
1
550  
1
ps  
(2)  
tLOCK  
ms  
Notes to Table 1–29:  
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).  
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.  
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 1 of 2)  
C6  
C7, I7  
Min  
C8, A7  
Min  
Symbol  
Modes  
Unit  
Min  
5
Max  
320  
320  
320  
320  
320  
402.5  
640  
640  
640  
640  
640  
402.5  
55  
Max  
320  
320  
320  
320  
320  
402.5  
640  
640  
640  
640  
640  
402.5  
55  
Max  
275  
275  
275  
275  
275  
402.5  
550  
550  
550  
550  
550  
402.5  
55  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
5
5
5
5
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
5
5
5
5
f
HSCLK (input  
clock frequency)  
5
5
5
5
5
5
5
5
5
100  
80  
70  
40  
20  
10  
45  
100  
80  
70  
40  
20  
10  
45  
100  
80  
70  
40  
20  
10  
45  
HSIODR  
tDUTY  
TCCS  
200  
200  
200  
ps  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–22  
Chapter 1: Cyclone III Device Datasheet  
Switching Characteristics  
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 2 of 2)  
C6  
C7, I7  
Min  
C8, A7  
Min  
Symbol  
Modes  
Unit  
Min  
Max  
500  
1
Max  
500  
1
Max  
550  
1
Output jitter  
(peak to peak)  
ps  
(2)  
tLOCK  
ms  
Notes to Table 1–30:  
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.  
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.  
(1)  
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications  
C6  
C7, I7  
Min  
C8, A7  
Symbol  
Modes  
Unit  
Min  
5
Max  
437.5  
437.5  
437.5  
437.5  
437.5  
437.5  
875  
Max  
370  
370  
370  
370  
370  
402.5  
740  
740  
740  
740  
740  
402.5  
400  
Min  
5
Max  
320  
320  
320  
320  
320  
402.5  
640  
640  
640  
640  
640  
402.5  
400  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
5
5
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
ps  
5
5
5
5
5
fHSCLK (input  
clock frequency)  
5
5
5
5
5
5
5
5
5
100  
80  
70  
40  
20  
10  
100  
80  
70  
40  
20  
10  
100  
80  
70  
40  
20  
10  
875  
875  
HSIODR  
SW  
875  
875  
437.5  
400  
Input jitter  
tolerance  
500  
1
500  
1
550  
1
ps  
(2)  
tLOCK  
ms  
Notes to Table 1–31:  
(1) LVDS receiver is supported at all banks.  
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.  
External Memory Interface Specifications  
Cyclone III devices support external memory interfaces up to 200 MHz. The external  
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.  
f
For more information about external memory system performance specifications,  
board design guidelines, timing analysis, simulation, and debugging information,  
refer to Literature: External Memory Interfaces.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–23  
Switching Characteristics  
Table 1–32 lists the FPGA sampling window specifications for Cyclone III devices.  
Table 1–32. Cyclone III Devices FPGA Sampling Window (SW) Requirement – Read Side (1)  
Column I/Os Row I/Os  
Wraparound Mode  
Memory Standard  
Setup  
Hold  
Setup  
Hold  
Setup  
Hold  
C6  
C7  
C8  
I7  
DDR2 SDRAM  
580  
585  
785  
550  
535  
735  
690  
700  
805  
640  
650  
755  
850  
870  
905  
800  
820  
855  
DDR SDRAM  
QDRII SRAM  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
705  
675  
900  
650  
620  
845  
770  
795  
910  
715  
740  
855  
985  
970  
930  
915  
1085  
1030  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
785  
800  
720  
740  
990  
930  
915  
870  
855  
1115  
1185  
1210  
1055  
1125  
1150  
1050  
1065  
1005  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
765  
745  
945  
710  
690  
890  
855  
880  
955  
800  
825  
900  
1040  
1000  
1130  
985  
945  
1075  
A7  
DDR2 SDRAM  
DDR SDRAM  
805  
880  
745  
820  
1020  
955  
960  
935  
1145  
1220  
1250  
1085  
1160  
1190  
QDRII SRAM  
1090  
1030  
1105  
1045  
Note to Table 1–32:  
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row  
I/Os.  
Table 1–33 lists the transmitter channel-to-channel skew specifications for Cyclone III  
devices.  
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1)  
(Part 1 of 2)  
Column I/Os (ps)  
Row I/Os (ps)  
Wraparound Mode (ps)  
Memory  
Standard  
I/O Standard  
Lead  
Lag  
C6  
Lead  
Lag  
Lead  
Lag  
SSTL-18 Class I  
SSTL-18 Class II  
SSTL-2 Class I  
790  
870  
750  
860  
780  
830  
380  
490  
320  
350  
410  
510  
790  
870  
750  
860  
780  
830  
380  
490  
320  
350  
410  
510  
890  
970  
850  
960  
880  
930  
480  
590  
420  
450  
510  
610  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
SSTL-2 Class II  
1.8 V HSTL Class I  
1.8 V HSTL Class II  
C7  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–24  
Chapter 1: Cyclone III Device Datasheet  
Switching Characteristics  
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1)  
(Part 2 of 2)  
Column I/Os (ps)  
Row I/Os (ps)  
Wraparound Mode (ps)  
Memory  
I/O Standard  
Standard  
Lead  
915  
Lag  
410  
545  
340  
380  
450  
570  
Lead  
Lag  
410  
545  
340  
380  
450  
570  
Lead  
1015  
1125  
980  
Lag  
510  
645  
440  
480  
550  
670  
SSTL-18 Class I  
SSTL-18 Class II  
SSTL-2 Class I  
915  
1025  
880  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
1025  
880  
SSTL-2 Class II  
1.8 V HSTL Class I  
1.8 V HSTL Class II  
1010  
910  
1010  
910  
1110  
1010  
1110  
1010  
1010  
C8  
SSTL-18 Class I  
SSTL-18 Class II  
SSTL-2 Class I  
1040  
1180  
1010  
1160  
1040  
1190  
440  
600  
360  
410  
490  
630  
I7  
1040  
1180  
1010  
1160  
1040  
1190  
440  
600  
360  
410  
490  
630  
1140  
1280  
1110  
1260  
1140  
1290  
540  
700  
460  
510  
590  
730  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
SSTL-2 Class II  
1.8 V HSTL Class I  
1.8 V HSTL Class II  
SSTL-18 Class I  
SSTL-18 Class II  
SSTL-2 Class I  
961  
1076  
924  
431  
572  
357  
399  
473  
599  
A7  
961  
1076  
924  
431  
572  
357  
399  
473  
599  
1061  
1176  
1024  
1161  
1056  
1161  
531  
672  
457  
499  
573  
699  
DDR2 SDRAM  
DDR SDRAM  
QDRII SRAM  
SSTL-2 Class II  
1.8 V HSTL Class I  
1.8 V HSTL Class II  
1061  
956  
1061  
956  
1061  
1061  
SSTL-18 Class I  
SSTL-18 Class II  
SSTL-2 Class I  
1092  
1239  
1061  
1218  
1092  
1250  
462  
630  
378  
431  
515  
662  
1092  
1239  
1061  
1218  
1092  
1250  
462  
630  
378  
431  
515  
662  
1192  
1339  
1161  
1318  
1192  
1350  
562  
730  
478  
531  
615  
762  
DDR2 SDRAM  
(2)  
DDR SDRAM  
SSTL-2 Class II  
1.8 V HSTL Class I  
1.8 V HSTL Class II  
QDRII SRAM  
Notes to Table 1–33:  
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column  
and row I/Os.  
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.  
Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.  
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 1 of 2)  
Parameter  
Clock period jitter  
Symbol  
tJIT(per)  
tJIT(cc)  
Min  
-125  
-200  
Max  
125  
200  
Unit  
ps  
Cycle-to-cycle period jitter  
ps  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–25  
Switching Characteristics  
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 2 of 2)  
Parameter  
Duty cycle jitter  
Symbol  
Min  
Max  
Unit  
tJIT(duty)  
-150  
150  
ps  
Notes to Table 1–34:  
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.  
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global  
clock network.  
Duty Cycle Distortion Specifications  
Table 1–35 lists the worst case duty cycle distortion for Cyclone III devices.  
(1), (2)  
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins  
C6  
C7, I7  
Max  
55  
C8, A7  
Symbol  
Unit  
Min  
Max  
Min  
Min  
45  
Max  
Output Duty Cycle  
45  
55  
45  
55  
%
Notes to Table 1–35:  
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated  
and general purpose I/O pins.  
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of  
I/O standard and current strength.  
OCT Calibration Timing Specification  
Table 1–36 lists the duration of calibration for series OCT with calibration at device  
power-up for Cyclone III devices.  
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device  
(1)  
Power-Up  
Symbol  
Description  
Maximum  
Unit  
Duration of series OCT with  
calibration at device power-up  
tOCTCAL  
20  
µs  
Notes to Table 1–36:  
(1) OCT calibration takes place after device configuration, before entering user mode.  
IOE Programmable Delay  
Table 1–37 and Table 1–38 list IOE programmable delay for Cyclone III devices.  
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 1 of 2)  
Max Offset  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Slow Corner  
C8  
Unit  
Settings  
C6  
C7  
I7  
A7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
0
0
1.211 1.314 2.175  
2.32  
2.386 2.366  
2.49  
ns  
ns  
Input delay from pin to Pad to I/O  
1.203 1.307  
2.19  
2.387  
2.54  
2.43  
2.545  
input register  
input register  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–26  
Chapter 1: Cyclone III Device Datasheet  
I/O Timing  
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2) (Part 2 of 2)  
Max Offset  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Slow Corner  
C8  
Unit  
Settings  
C6  
C7  
I7  
A7  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
2
0
0
0.479 0.504 0.915 1.011 1.107 1.018 1.048  
0.664 0.694 1.199 1.378 1.532 1.392 1.441  
ns  
ns  
Input delay from  
Pad to global  
dual-purpose clock pin clock  
to fan-out destinations network  
12  
Notes to Table 1–37:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.  
(1), (2)  
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins  
Max Offset  
Number  
Paths  
Affected  
Min  
Offset  
Parameter  
of  
Fast Corner  
A7, I7 C6  
Slow Corner  
C8  
Unit  
Settings  
C6  
C7  
I7  
A7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
2
0
0
0
1.209 1.314 2.174 2.335 2.406 2.381 2.505  
1.207 1.312 2.202 2.402 2.558 2.447 2.557  
ns  
ns  
ns  
Input delay from pin to Pad to I/O  
input register  
input register  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
0.51  
0.537 0.962 1.072 1.167 1.074 1.101  
Input delay from  
dual-purpose clock pin  
to fan-out destinations  
Pad to global  
clock network  
12  
0
0.669 0.698 1.207 1.388 1.542 1.403  
1.45  
ns  
Notes to Table 1–38:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software  
I/O Timing  
You can use the following methods to determine the I/O timing:  
the Excel-based I/O Timing.  
the Quartus II timing analyzer.  
The Excel-based I/O Timing provides pin timing performance for each device density  
and speed grade. The data is typically used prior to designing the FPGA to get a  
timing budget estimation as part of the link timing analysis. The Quartus II timing  
analyzer provides a more accurate and precise I/O timing data based on the specifics  
of the design after place-and-route is complete.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–27  
Glossary  
f
The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices  
Literature website.  
Glossary  
Table 1–39 lists the glossary for this chapter.  
Table 1–39. Glossary (Part 1 of 5)  
Letter  
Term  
Definitions  
A
B
C
D
E
F
fHSCLK  
GCLK  
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.  
Input pin directly to Global Clock network.  
G
H
GCLK PLL  
HSIODR  
Input pin to Global Clock network through PLL.  
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).  
VIH  
Input Waveforms  
for the SSTL  
Differential I/O  
Standard  
I
VSWING  
VREF  
VIL  
TMS  
TDI  
tJCP  
tJPSU_TDI  
tJPSU_TMS  
tJCH  
t JCL  
tJPH  
TCK  
TDO  
J
JTAG Waveform  
tJPXZ  
tJPZX  
tJPCO  
tJSSU  
tJSH  
Signal  
to be  
Captured  
tJSZX  
tJSCO  
tJSXZ  
Signal  
to be  
Driven  
K
L
M
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–28  
Chapter 1: Cyclone III Device Datasheet  
Glossary  
Table 1–39. Glossary (Part 2 of 5)  
Letter  
Term  
Definitions  
N
O
The following block diagram highlights the PLL Specification parameters.  
CLKOUT Pins  
fOUT_EXT  
Switchover  
CLK  
fIN  
fINPFD  
N
fVCO  
VCO  
PFD  
CP  
LF  
fOUT  
GCLK  
Counters  
Core Clock  
C0..C4  
P
Q
PLL Block  
Phase tap  
M
Key  
Reconfigurable in User Mode  
RL  
Receiver differential input discrete resistor (external to Cyclone III devices).  
Receiver Input Waveform for LVDS and LVPECL Differential Standards.  
Single-Ended Waveform  
Positive Channel (p) = VIH  
VID  
Negative Channel (n) = VIL  
Ground  
VCM  
Receiver Input  
Waveform  
R
Differential Waveform (Mathematical Function of Positive & Negative Channel)  
VID  
0 V  
VID  
p - n  
RSKM (Receiver  
input skew  
margin)  
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.  
RSKM = (TUI – SW – TCCS) / 2.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–29  
Glossary  
Table 1–39. Glossary (Part 3 of 5)  
Letter  
Term  
Definitions  
VCCIO  
VOH  
VIH AC  
(
)
VIH(DC)  
VREF  
VIL(DC)  
VIL(AC  
)
Single-ended  
Voltage  
referenced I/O  
Standard  
VOL  
S
VSS  
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal  
values. The AC values indicate the voltage levels at which the receiver must meet its timing  
specifications. The DC values indicate the voltage levels at which the final logic state of the  
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver  
changes to the new logic state. The new logic state is then maintained as long as the input stays  
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the  
presence of input waveform ringing.  
SW (Sampling  
Window)  
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it  
correctly. The setup and hold times determine the ideal strobe position in the sampling window.  
tC  
High-speed receiver/transmitter input and output clock period.  
TCCS (Channel-  
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,  
to-channel-skew) including tCO variation and clock skew. The clock is included in the TCCS measurement.  
tcin  
tCO  
Delay from clock pad to I/O input register.  
Delay from clock pad to I/O output.  
tcout  
tDUTY  
tFALL  
tH  
Delay from clock pad to I/O output register.  
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.  
Signal High-to-low transition time (80–20%).  
Input register hold time.  
T
Timing Unit  
Interval (TUI)  
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data  
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).  
tINJITTER  
Period jitter on PLL clock input.  
tOUTJITTER_DEDCLK  
tOUTJITTER_IO  
tpllcin  
Period jitter on dedicated clock output driven by a PLL.  
Period jitter on general purpose I/O driven by a PLL.  
Delay from PLL inclk pad to I/O input register.  
Delay from PLL inclk pad to I/O output register.  
tpllcout  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–30  
Chapter 1: Cyclone III Device Datasheet  
Glossary  
Table 1–39. Glossary (Part 4 of 5)  
Letter  
Term  
Definitions  
Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O  
Standards  
Single-Ended Waveform  
Positive Channel (p) = VOH  
VOD  
Negative Channel (n) = VOL  
V
os  
Ground  
Transmitter  
Output Waveform  
Differential Waveform (Mathematical Function of Positive & Negative Channel)  
VOD  
0 V  
VOD  
p - n  
tRISE  
tSU  
Signal Low-to-high transition time (20–80%).  
Input register setup time.  
U
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–31  
Glossary  
Table 1–39. Glossary (Part 5 of 5)  
Letter  
Term  
VCM(DC)  
Definitions  
DC Common Mode Input Voltage.  
VDIF(AC)  
VDIF(DC)  
VICM  
AC differential Input Voltage: The minimum AC input differential voltage required for switching.  
DC differential Input Voltage: The minimum DC input differential voltage required for switching.  
Input Common Mode Voltage: The common mode of the differential signal at the receiver.  
Input differential Voltage Swing: The difference in voltage between the positive and  
complementary conductors of a differential transmission at the receiver.  
VID  
VIH  
Voltage Input High: The minimum positive voltage applied to the input which is accepted by the  
device as a logic high.  
VIH(AC)  
VIH(DC)  
High-level AC input voltage.  
High-level DC input voltage.  
Voltage Input Low: The maximum positive voltage applied to the input which is accepted by the  
device as a logic low.  
VIL  
VIL (AC)  
VIL (DC)  
VIN  
Low-level AC input voltage.  
Low-level DC input voltage.  
DC input voltage.  
VOCM  
Output Common Mode Voltage: The common mode of the differential signal at the transmitter.  
Output differential Voltage Swing: The difference in voltage between the positive and  
complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.  
VOD  
VOH  
V
Voltage Output High: The maximum positive voltage from an output which the device considers is  
accepted as the minimum positive high level.  
Voltage Output Low: The maximum positive voltage from an output which the device considers is  
accepted as the maximum positive low level.  
VOL  
VOS  
Output offset voltage: VOS = (VOH + VOL) / 2.  
AC differential Output cross point voltage: The voltage at which the differential output signals must  
cross.  
VOX (AC)  
VREF  
Reference voltage for SSTL, HSTL I/O Standards.  
AC input reference voltage for SSTL, HSTL I/O Standards. VREF(AC) = VREF(DC) + noise. The  
VREF (AC)  
VREF (DC)  
VSWING (AC)  
peak-to-peak AC noise on VREF should not exceed 2% of VREF(DC)  
.
DC input reference voltage for SSTL, HSTL I/O Standards.  
AC differential Input Voltage: AC Input differential voltage required for switching. For the SSTL  
Differential I/O Standard, refer to Input Waveforms.  
DC differential Input Voltage: DC Input differential voltage required for switching. For the SSTL  
Differential I/O Standard, refer to Input Waveforms.  
VSWING (DC)  
VTT  
Termination voltage for SSTL, HSTL I/O Standards.  
AC differential Input cross point Voltage: The voltage at which the differential input signals must  
cross.  
VX (AC)  
W
X
Y
Z
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–32  
Chapter 1: Cyclone III Device Datasheet  
Document Revision History  
Document Revision History  
Table 1–40 lists the revision history for this document.  
Table 1–40. Document Revision History (Part 1 of 3)  
Date  
July 2012  
Version  
Changes  
3.5  
Updated minimum fHSCLK value to 5 MHz.  
Updated “Supply Current” on page 1–5 and “Periphery Performance” on page 1–17.  
December 2011  
3.4  
Updated Table 1–3, Table 1–4, Table 1–13, Table 1–16, Table 1–17, Table 1–20, and  
Table 1–25.  
Removed Table 1-32 and Table 1-33.  
Added Literature: External Memory Interfaces reference.  
Minor changes to the text.  
January 2010  
3.3  
December 2009  
July 2009  
3.2  
3.1  
Minor edit to the hyperlinks.  
Changed chapter title from DC and Switching Characteristics to “Cyclone III Device Data  
Sheet” on page 1–1.  
Updated (Note 1) to Table 1–23 on page 1–17.  
Updated “External Memory Interface Specifications” on page 1–23.  
Replaced Table 1–32 on page 1–23.  
June 2009  
3.0  
Replaced Table 1–33 on page 1–23.  
Added Table 1–36 on page 1–26.  
Updated “I/O Timing” on page 1–28.  
Removed “Typical Design Performance” section.  
Removed “I/O Timing” subsections.  
Updated chapter to new template.  
Updated Table 1–1, Table 1–3, and Table 1–18.  
Added (Note 7) to Table 1–3.  
October 2008  
2.2  
2.1  
Added the “OCT Calibration Timing Specification” section.  
Updated “Glossary” section.  
Updated Table 1–38.  
Added BLVDS information (I/O standard) into Table 1–39, Table 1–40, Table 1–41,  
Table 1–42.  
Updated Table 1–43, Table 1–46, Table 1–47, Table 1–48, Table 1–49, Table 1–50,  
Table 1–51, Table 1–52, Table 1–53, Table 1–54, Table 1–55, Table 1–56, Table 1–57,  
Table 1–58, Table 1–59, Table 1–60, Table 1–61, Table 1–62, Table 1–63, Table 1–68,  
Table 1–69, Table 1–74, Table 1–75, Table 1–80, Table 1–81, Table 1–86, Table 1–87,  
Table 1–92, Table 1–93, Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and  
Table 1–99.  
July 2008  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
Chapter 1: Cyclone III Device Datasheet  
1–33  
Document Revision History  
Table 1–40. Document Revision History (Part 2 of 3)  
Date  
Version  
Changes  
Updated “Operating Conditions” section and included information on automotive device.  
Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive information.  
Under “Pin Capacitance” section, updated Table 1–9 and Table 1–10.  
Added new “Schmitt Trigger Input” section with Table 1–12.  
Under “I/O Standard Specifications” section, updated Table 1–13, 1–12 and 1–12.  
May 2008  
2.0  
Under “Switching Characteristics” section, updated Table 1–19, 1–15, 1–16, 1–16, 1–17,  
1–18, 1–19, 1–20, 1–21, 1–21, 1–23, 1–23, 1–23, 1–24, and 1–25.  
Updated Figure 1–5 and 1–29.  
Deleted previous Table 1-35 “DDIO Outputs Half-Period Jitter”.  
Under “I/O Timing” section, updated Table 1–38, 1–29, 1–32, 1–33, 1–26, and 1–26.  
Under “Typical Design Performance” section updated Table 1–46 through 1–145.  
Under “Core Performance Specifications”, updated Tables 1-18 and 1-19.  
Under “Preliminary, Correlated, and Final Timing”, updated Table 1-37.  
December 2007  
1.5  
Under “Typical Design Performance”, updated Tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58,  
Tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, Tables 1-87 through 1-92,  
Tables 1-99, 1-100, 1-107, and 1-108.  
Updated the CVREFTB value in Table 1-9.  
Updated Table 1-21.  
Under “High-Speed I/O Specification” section, updated Tables 1-25 through 1-30.  
Updated Tables 1-31 through 1-38.  
Added new Table 1-32.  
October 2007  
1.4  
Under “Maximum Input and Output Clock Toggle Rate” section, updated Tables 1-40  
through 1-42.  
Under “IOE Programmable Delay” section, updated Tables 1-43 through 1-44.  
Under “User I/O Pin Timing Parameters” section, updated Tables 1-45 through 1-92.  
Under “Dedicated Clock Pin Timing Parameters” section, updated Tables 1-93 through 1-  
108.  
Updated Table 1-1 with VESDHBM and VESDCDM information.  
Updated RCONF_PD information in Tables 1-10.  
Added Note (3) to Table 1-12.  
July 2007  
June 2007  
1.3  
1.2  
Updated tDLOCK information in Table 1-19.  
Updated Table 1-43 and Table 1-44.  
Added “Document Revision History” section.  
Updated Cyclone III graphic in cover page.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
1–34  
Chapter 1: Cyclone III Device Datasheet  
Document Revision History  
Table 1–40. Document Revision History (Part 3 of 3)  
Date  
Version  
Changes  
Corrected current unit in Tables 1-1, 1-12, and 1-14.  
Added Note (3) to Table 1-3.  
Updated Table 1-4 with ICCINT0, ICCA0, ICCD_PLL0, and ICCIO0 information.  
Updated Table 1-9 and added Note (2).  
Updated Table 1-19.  
Updated Table 1-22 and added Note (1).  
May 2007  
1.1  
Changed I/O standard from 1.5-V LVTTL/LVCMOS and 1.2-V LVTTL/LVCMOS to 1.5-V  
LVCMOS and 1.2-V LVCMOS in Tables 1-41, 1-42, 1-43, 1-44, and 1-45.  
Updated Table 1-43 with changes to LVPEC and LVDS and added Note (5).  
Updated Tables 1-46, 1-47, Tables 1-54 through 1-95, and Tables 1-98 through 1-111.  
Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1-110 through  
1-111.  
Added a waveform (Receiver Input Waveform) in glossary under letter “R” (Table 1-112).  
March 2007  
1.0  
Initial release.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  

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