EP4CE40F29I7N_技术文档

1. Cyclone IV Device Datasheet

March 2016

CYIV-53001-2.0

This chapter describes the electrical and switching characteristics for Cyclone^IV

devices. Electrical characteristics include operating conditions and power

consumption. Switching characteristics include transceiver specifications, core, and

periphery performance. This chapter also describes I/O timing, including

programmable I/O element (IOE) delay and programmable output buffer delay.

This chapter includes the following sections:

■

“Operating Conditions” on page 1–1

“Power Consumption” on page 1–16

“Switching Characteristics” on page 1–16

“I/O Timing” on page 1–37

“Glossary” on page 1–37

Operating Conditions

When Cyclone IV devices are implemented in a system, they are rated according to a

set of defined parameters. To maintain the highest possible performance and

reliability of Cyclone IV devices, you must consider the operating requirements

described in this chapter.

Cyclone IV devices are offered in commercial, industrial, extended industrial and,

automotive grades. Cyclone IV E devices offer –6 (fastest), –7, –8, –8L, and –9L speed

grades for commercial devices, –8L speed grades for industrial devices, and –7 speed

grade for extended industrial and automotive devices. Cyclone IV GX devices offer

–6 (fastest), –7, and –8 speed grades for commercial devices and –7 speed grade for

industrial devices.

f

1

For more information about the supported speed grades for respective Cyclone IV

devices, refer to the Cyclone IV FPGA Device Family Overview chapter.

Cyclone IV E devices are offered in core voltages of 1.0 and 1.2 V. Cyclone IV E

devices with a core voltage of 1.0 V have an ‘L’ prefix attached to the speed grade.

In this chapter, a prefix associated with the operating temperature range is attached to

the speed grades; commercial with a “C” prefix, industrial with an “I” prefix, and

automotive with an “A” prefix. Therefore, commercial devices are indicated as C6, C7,

C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8,

or I8L. Automotive devices are indicated as A7.

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Cyclone IV Device Handbook,

Volume 3

March 2016

Feedback Subscribe

1–2

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

1

Cyclone IV E industrial devices I7 are offered with extended operating temperature

range.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for Cyclone IV

devices. The values are based on experiments conducted with the device and

theoretical modeling of breakdown and damage mechanisms. The functional

operation of the device is not implied at these conditions. Table 1–1 lists the absolute

maximum ratings for Cyclone IV devices.

c

Conditions beyond those listed in Table 1–1 cause permanent damage to the device.

Additionally, device operation at the absolute maximum ratings for extended periods

of time have adverse effects on the device.

Table 1–1. Absolute Maximum Ratings for Cyclone IV Devices ⁽¹⁾

Symbol

V_CCINT

V_CCA

Parameter

Min

Max

Unit

Core voltage, PCI Express^(PCIe^) hard IP

block, and transceiver physical coding sublayer

(PCS) power supply

–0.5

1.8

V

Phase-locked loop (PLL) analog power supply

–0.5

3.75

1.8

V

V_{CCD_PLL}PLL digital power supply

V_CCIOI/O banks power supply

3.75

4.5

V_{CC_CLKIN}Differential clock input pins power supply

V_{CCH_GXB}Transceiver output buffer power supply

3.75

Transceiver physical medium attachment (PMA)

and auxiliary power supply

V_{CCA_GXB}

–0.5

3.75

V

V_{CCL_GXB}Transceiver PMA and auxiliary power supply

–0.5

–25

–65

–40

1.8

4.2

40

V

V_I

DC input voltage

I_OUT

T_STG

T_J

DC output current, per pin

Storage temperature

mA

°C

150

125

Operating junction temperature

Note to Table 1–1:

(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the

power supply.

Maximum Allowed Overshoot or Undershoot Voltage

During transitions, input signals may overshoot to the voltage shown in Table 1–2 and

undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods

shorter than 20 ns. Table 1–2 lists the maximum allowed input overshoot voltage and

the duration of the overshoot voltage as a percentage over the lifetime of the device.

The maximum allowed overshoot duration is specified as a percentage of high-time

over the lifetime of the device.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–3

Operating Conditions

1

A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to

4.3 V can only be at 4.3 V for 65% over the lifetime of the device; for a device lifetime

of 10 years, this amounts to 65/10ths of a year.

Table 1–2. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for

Cyclone IV Devices

Symbol

Parameter

Condition (V)

V_I= 4.20

V_I= 4.25

V_I= 4.30

V_I= 4.35

V_I= 4.40

V_I= 4.45

V_I= 4.50

V_I= 4.55

V_I= 4.60

Overshoot Duration as % of High Time

Unit

%

100

98

65

43

29

20

13

9

%

AC Input

Voltage

V_i

%

6

%

Figure 1–1 shows the methodology to determine the overshoot duration. The

overshoot voltage is shown in red and is present on the input pin of the Cyclone IV

device at over 4.3 V but below 4.4 V. From Table 1–2, for an overshoot of 4.3 V, the

percentage of high time for the overshoot can be as high as 65% over a 10-year period.

Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period

assumes that the device is always turned on with 100% I/O toggle rate and 50% duty

cycle signal. For lower I/O toggle rates and situations in which the device is in an idle

state, lifetimes are increased.

Figure 1–1. Cyclone IV Devices Overshoot Duration

4.4 V

4.3 V

3.3 V

DT

T

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–4

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

Recommended Operating Conditions

This section lists the functional operation limits for AC and DC parameters for

Cyclone IV devices. Table 1–3 and Table 1–4 list the steady-state voltage and current

values expected from Cyclone IV E and Cyclone IV GX devices. All supplies must be

strictly monotonic without plateaus.

Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices ^{(1), (2)}(Part 1 of 2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply voltage for internal logic,

1.2-V operation

—

1.15

1.2

1.25

V

(3)

V_CCINT

Supply voltage for internal logic,

1.0-V operation

—

0.97

3.135

2.85

1.0

3.3

3

1.03

3.465

3.15

V

Supply voltage for output buffers,

3.3-V operation

Supply voltage for output buffers,

3.0-V operation

Supply voltage for output buffers,

2.5-V operation

2.375

1.71

2.5

1.8

1.5

1.2

2.5

1.2

1.0

2.625

1.89

(3), (4)

V_CCIO

Supply voltage for output buffers,

1.8-V operation

Supply voltage for output buffers,

1.5-V operation

1.425

1.14

1.575

1.26

Supply voltage for output buffers,

1.2-V operation

Supply (analog) voltage for PLL

regulator

(3)

V_CCA

2.375

1.15

2.625

1.25

Supply (digital) voltage for PLL,

1.2-V operation

(3)

V_{CCD_PLL}

Supply (digital) voltage for PLL,

1.0-V operation

0.97

1.03

V_I

Input voltage

—

–0.5

0

—

3.6

V_CCIO

85

V

V_O

Output voltage

—

V

For commercial use

For industrial use

For extended temperature

For automotive use

Standard power-on reset

0

°C

–40

100

125

T_J

Operating junction temperature

Power supply ramp time

50 µs

—

50 ms

3 ms

—

(5)

(POR)

t_RAMP

(6)

Fast POR

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–5

Operating Conditions

Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices ^{(1), (2)}(Part 2 of 2)

Symbol

I_Diode

Parameter

Conditions

Min

Typ

Max

Unit

mA

Magnitude of DC current across

PCI-clamp diode when enable

—

10

Notes to Table 1–3:

(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support

C6, C7, C8, I7, and A7 speed grades.

(2) V_CCIOfor all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used)

and must be powered up and powered down at the same time.

(3) V_CCmust rise monotonically.

(4) V_CCIOpowers all input buffers.

(5) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range

within 50 ms.

(6) The POR time for Fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within

3 ms.

Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 1 of 2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Core voltage, PCIe hard IP block, and

transceiver PCS power supply

(3)

V_CCINT

—

1.16

1.2

1.24

V

(1), (3)

V_CCA

V_{CCD_PLL}

PLL analog power supply

PLL digital power supply

—

2.375

1.16

2.5

1.2

2.625

1.24

V

(2)

I/O banks power supply for 3.3-V

operation

—

3.135

2.85

3.3

3

3.465

3.15

V

I/O banks power supply for 3.0-V

operation

I/O banks power supply for 2.5-V

operation

2.375

1.71

2.5

1.8

1.5

1.2

3.3

3

2.625

1.89

(3), (4)

V_CCIO

I/O banks power supply for 1.8-V

operation

I/O banks power supply for 1.5-V

operation

1.425

1.14

1.575

1.26

I/O banks power supply for 1.2-V

operation

Differential clock input pins power

supply for 3.3-V operation

3.135

2.85

3.465

3.15

Differential clock input pins power

supply for 3.0-V operation

Differential clock input pins power

supply for 2.5-V operation

2.375

1.71

2.5

1.8

1.5

2.625

1.89

V_{CC_CLKIN}

(3), (5), (6)

Differential clock input pins power

supply for 1.8-V operation

Differential clock input pins power

supply for 1.5-V operation

1.425

1.575

Differential clock input pins power

supply for 1.2-V operation

—

1.14

1.2

2.5

1.26

V

V_{CCH_GXB}

Transceiver output buffer power supply

2.375

2.625

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–6

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2)

Symbol

V_{CCA_GXB}

Parameter

Conditions

Min

Typ

Max

Unit

Transceiver PMA and auxiliary power

supply

—

2.375

2.5

2.625

V

Transceiver PMA and auxiliary power

supply

V_{CCL_GXB}

—

1.16

1.2

1.24

V

V_I

DC input voltage

DC output voltage

—

–0.5

0

—

3.6

V_CCIO

85

V

V_O

—

For commercial use

For industrial use

Standard power-on reset

0

°C

T_J

Operating junction temperature

–40

100

50 µs

—

50 ms

3 ms

10

—

(7)

(POR)

t_RAMP

Power supply ramp time

(8)

Fast POR

Magnitude of DC current across

PCI-clamp diode when enabled

I_Diode

—

mA

Notes to Table 1–4:

(1) All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time.

(2) You must connect V_{CCD_PLL}to V_CCINTthrough a decoupling capacitor and ferrite bead.

(3) Power supplies must rise monotonically.

(4) V_CCIOfor all I/O banks must be powered up during device operation. Configurations pins are powered up by V_CCIOof I/O Banks 3, 8, and 9 where

I/O Banks 3 and 9 only support V_CCIOof 1.5, 1.8, 2.5, 3.0, and 3.3 V. For fast passive parallel (FPP) configuration mode, the V_CCIOlevel of I/O

Bank 8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 V.

(5) You must set V_{CC_CLKIN}to 2.5 V if you use CLKIN as a high-speed serial interface (HSSI) refclk or as a DIFFCLK input.

(6) The CLKIN pins in I/O Banks 3B and 8B can support single-ended I/O standard when the pins are used to clock left PLLs in non-transceiver

applications.

(7) The POR time for Standard POR ranges between 50 and 200 ms. V_CCINT, V_CCA, and V_CCIOof I/O Banks 3, 8, and 9 must reach the recommended

operating range within 50 ms.

(8) The POR time for Fast POR ranges between 3 and 9 ms. V_CCINT, V_CCA, and V_CCIOof I/O Banks 3, 8, and 9 must reach the recommended operating

range within 3 ms.

ESD Performance

This section lists the electrostatic discharge (ESD) voltages using the human body

model (HBM) and charged device model (CDM) for Cyclone IV devices general

purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table 1–5 lists the

ESD for Cyclone IV devices GPIOs and HSSI I/Os.

Table 1–5. ESD for Cyclone IV Devices GPIOs and HSSI I/Os

Symbol

V_ESDHBM

Parameter

ESD voltage using the HBM (GPIOs) ⁽¹⁾

Passing Voltage

Unit

V

2000

1000

500

(2)

ESD using the HBM (HSSI I/Os)

V

ESD using the CDM (GPIOs)

V

V_ESDCDM

(2)

ESD using the CDM (HSSI I/Os)

250

V

Notes to Table 1–5:

(1) The passing voltage for EP4CGX15 and EP4CGX30 row I/Os is 1000V.

(2) This value is applicable only to Cyclone IV GX devices.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–7

Operating Conditions

DC Characteristics

This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)

tolerance, and bus hold specifications for Cyclone IV devices.

Supply Current

The device supply current requirement is the minimum current drawn from the

power supply pins that can be used as a reference for power size planning. Use the

Excel-based early power estimator (EPE) to get the supply current estimates for your

design because these currents vary greatly with the resources used. Table 1–6 lists the

I/O pin leakage current for Cyclone IV devices.

Table 1–6. I/O Pin Leakage Current for Cyclone IV Devices ^{(1), (2)}

Symbol

Parameter

Conditions

Device

Min

Typ

Max

Unit

I_I

Input pin leakage current

V_I= 0 V to V_CCIOMAX

—

–10

—

10

A

Tristated I/O pin leakage

current

I_OZ

V_O= 0 V to V_CCIOMAX

—

–10

—

10

A

Notes to Table 1–6:

(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all V_CCIOsettings (3.3, 3.0, 2.5,

1.8, 1.5, and 1.2 V).

(2) The 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on.

Bus Hold

The bus hold retains the last valid logic state after the source driving it either enters

the high impedance state or is removed. Each I/O pin has an option to enable bus

hold in user mode. Bus hold is always disabled in configuration mode.

Table 1–7 lists bus hold specifications for Cyclone IV devices.

Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 1 of 2) ⁽¹⁾

V

_CCIO(V)

Parameter

Condition

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max Min

Max Min Max Min Max Min Max Min Max

Bus hold

low,

sustaining

current

V_IN> V_IL

(maximum)

8

—

12

–12

—

30

–30

—

50

–50

—

70

–70

—

70

–70

—

A

Bus hold

high,

sustaining

current

V_IN< V_IL

(minimum)

–8

—

Bus hold

low,

overdrive

current

0 V < V_IN< V_CCIO

125

–125

175

200

–200

300

–300

500

–500

500 A

–500 A

Bus hold

high,

overdrive

current

0 V < V_IN< V_CCIO

—

–175

—

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–8

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 2 of 2) ⁽¹⁾

V

_CCIO(V)

Parameter

Condition

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max Min

Max Min Max Min Max Min Max Min Max

Bus hold trip

point

—

0.3

0.9 0.375 1.125 0.68 1.07 0.7

1.7

0.8

2

0.8

2

V

Note to Table 1–7:

(1) Bus hold trip points are based on the calculated input voltages from the JEDEC standard.

OCT Specifications

Table 1–8 lists the variation of OCT without calibration across process, temperature,

and voltage (PVT).

Table 1–8. Series OCT Without Calibration Specifications for Cyclone IV Devices

Resistance Tolerance

Industrial, Extended

industrial, and

Automotive Maximum

Description

V

_CCIO(V)

Unit

Commercial Maximum

3.0

2.5

1.8

1.5

1.2

30

40

50

40

50

%

Series OCT without

calibration

OCT calibration is automatically performed at device power-up for OCT-enabled

I/Os.

Table 1–9 lists the OCT calibration accuracy at device power-up.

Table 1–9. Series OCT with Calibration at Device Power-Up Specifications for Cyclone IV Devices

Calibration Accuracy

Industrial, Extended

industrial, and

Automotive Maximum

Description

V_CCIO(V)

Unit

Commercial Maximum

3.0

2.5

1.8

1.5

1.2

10

%

Series OCT with

calibration at device

power-up

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–9

Operating Conditions

The OCT resistance may vary with the variation of temperature and voltage after

calibration at device power-up. Use Table 1–10 and Equation 1–1 to determine the

final OCT resistance considering the variations after calibration at device power-up.

Table 1–10 lists the change percentage of the OCT resistance with voltage and

temperature.

Table 1–10. OCT Variation After Calibration at Device Power-Up for Cyclone IV Devices

Nominal Voltage

dR/dT (%/°C)

0.262

dR/dV (%/mV)

–0.026

3.0

2.5

1.8

1.5

1.2

0.234

–0.039

0.219

–0.086

0.199

–0.136

0.161

–0.288

Equation 1–1. Final OCT Resistance ^{(1), (2), (3), (4), (5), (6)}

(7)

R_V= (V₂– V₁) × 1000 × dR/dV –––––

(8)

R_T= (T₂– T₁) × dR/dT –––––

(9)

For R_x< 0; MF_x= 1/ (|R_x|/100 + 1) –––––

(10)

For R_x> 0; MF_x= R_x/100 + 1 –––––

(11)

MF = MF_V× MF_T–––––

(12)

R_final= R_initial× MF –––––

Notes to Equation 1–1:

(1) T₂is the final temperature.

(2) T₁is the initial temperature.

(3) MF is multiplication factor.

(4) R_finalis final resistance.

(5) R_initialis initial resistance.

(6) Subscript _xrefers to both _Vand _T.

(7) R_Vis a variation of resistance with voltage.

(8) R_Tis a variation of resistance with temperature.

(9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up.

(10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up.

(11) V₂is final voltage.

(12) V₁is the initial voltage.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–10

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

Example 1–1 shows how to calculate the change of 50-I/O impedance from 25°C at

3.0 V to 85°C at 3.15 V.

Example 1–1. Impedance Change

R_V= (3.15 – 3) × 1000 × –0.026 = –3.83

R_T= (85 – 25) × 0.262 = 15.72

Because R_Vis negative,

MF_V= 1 / (3.83/100 + 1) = 0.963

Because R_Tis positive,

MF_T= 15.72/100 + 1 = 1.157

MF = 0.963 × 1.157 = 1.114

R

_final= 50 × 1.114 = 55.71 

Pin Capacitance

Table 1–11 lists the pin capacitance for Cyclone IV devices.

(1)

Table 1–11. Pin Capacitance for Cyclone IV Devices

Typical – Typical – Typical –

Quad Flat Quad Flat Ball-Grid

Symbol

Parameter

Unit

Pack

(QFP)

No Leads

(QFN)

Array

(BGA)

C_IOTB

Input capacitance on top and bottom I/O pins

Input capacitance on right I/O pins

7

8

7

8

6

5

7

pF

C_IOLR

C_LVDSLR

Input capacitance on right I/O pins with dedicated LVDS output

C_VREFLR

Input capacitance on right dual-purpose VREF pin when used as

21

23

21

23

pF

(2)

V_REFor user I/O pin

C_VREFTB

Input capacitance on top and bottom dual-purpose VREF pin when

used as V_REFor user I/O pin

(3)

23

(2)

C_CLKTB

C_CLKLR

Input capacitance on top and bottom dedicated clock input pins

Input capacitance on right dedicated clock input pins

7

6

7

6

5

pF

Notes to Table 1–11:

(1) The pin capacitance applies to FBGA, UBGA, and MBGA packages.

(2) When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and t_CObecause of higher pin

capacitance.

(3) C_VREFTBfor the EP4CE22 device is 30 pF.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–11

Operating Conditions

Internal Weak Pull-Up and Weak Pull-Down Resistor

Table 1–12 lists the weak pull-up and pull-down resistor values for Cyclone IV

devices.

Table 1–12. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices ⁽¹⁾

Symbol

Parameter

Conditions

Min

7

Typ

25

28

35

57

82

143

19

22

25

35

50

Max

41

Unit

(2), (3)

V_CCIO= 3.3 V 5%

k

(2), (3)

(4)

V

_CCIO= 3.0 V 5%

7

47

Value of the I/O pin pull-up resistor

before and during configuration, as

well as user mode if you enable the

programmable pull-up resistor option

V_CCIO= 2.5 V 5%

8

61

R_{_PU}

V

_CCIO= 1.8 V 5%

_CCIO= 1.5 V 5%

10

13

19

6

108

163

351

30

V_CCIO= 1.2 V 5%

V_CCIO= 3.3 V 5%

(4)

V

_CCIO= 3.0 V 5%

_CCIO= 2.5 V 5%

_CCIO= 1.8 V 5%

_CCIO= 1.5 V 5%

6

36

Value of the I/O pin pull-down resistor

before and during configuration

(4)

R_{_PD}

6

43

(4)

7

71

(4)

8

112

Notes to Table 1–12:

(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available

for JTAG TCK

.

(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO

.

(3) R_{_PU}= (V_CCIO– V_I)/I_{R_PU}

Minimum condition: –40°C; V_CCIO= V_CC+ 5%, V_I= V_CC+ 5% – 50 mV;

Typical condition: 25°C; V_CCIO= V_CC, V_I= 0 V;

Maximum condition: 100°C; V_CCIO= V_CC– 5%, V_I= 0 V; in which V_Irefers to the input voltage at the I/O pin.

(4) R_{_PD}= V_I/I_{R_PD}

Minimum condition: –40°C; V_CCIO= V_CC+ 5%, V_I= 50 mV;

Typical condition: 25°C; V_CCIO= V_CC, V_I= V_CC– 5%;

Maximum condition: 100°C; V_CCIO= V_CC– 5%, V_I= V_CC– 5%; in which V_Irefers to the input voltage at the I/O pin.

Hot-Socketing

Table 1–13 lists the hot-socketing specifications for Cyclone IV devices.

Table 1–13. Hot-Socketing Specifications for Cyclone IV Devices

Symbol

I_IOPIN(DC)

Parameter

DC current per I/O pin

Maximum

300 A

(1)

I_IOPIN(AC)

AC current per I/O pin

8 mA

I_XCVRTX(DC)

DC current per transceiver TX pin

DC current per transceiver RX pin

100 mA

50 mA

I_XCVRRX(DC)

Note to Table 1–13:

(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin

capacitance and dv/dt is the slew rate.

1

During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin

capacitance is less than 20 pF.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–12

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

Schmitt Trigger Input

Cyclone IV devices support Schmitt trigger input on the TDI

, TMS, TCK, nSTATUS,

nCONFIG, nCE,

CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces

hysteresis to the input signal for improved noise immunity, especially for signals with

slow edge rate. Table 1–14 lists the hysteresis specifications across the supported

V

_CCIOrange for Schmitt trigger inputs in Cyclone IV devices.

Table 1–14. Hysteresis Specifications for Schmitt Trigger Input in Cyclone IV Devices

Symbol

Parameter

Conditions (V)

Minimum

200

Unit

mV

V

_CCIO= 3.3

_CCIO= 2.5

200

Hysteresis for Schmitt trigger

input

V_SCHMITT

V_CCIO= 1.8

_CCIO= 1.5

140

V

110

I/O Standard Specifications

The following tables list input voltage sensitivities (V_IHand V_IL), output voltage (V_OH

and V_OL), and current drive characteristics (I_OHand I_OL), for various I/O standards

supported by Cyclone IV devices. Table 1–15 through Table 1–20 provide the I/O

standard specifications for Cyclone IV devices.

(2)

Table 1–15. Single-Ended I/O Standard Specifications for Cyclone IV Devices ^(1),

V_CCIO(V)

Typ

V_IL(V)

V_IH(V)

Max

V_OL(V)

Max

V_OH(V)

Min

I_OL

I_OH

I/O Standard

(mA)

(4)

Min

Max

Min

Max

Min

(3)

3.3-V LVTTL

3.135

2.85

3.3

3.0

2.5

3.465

—

0.8

0.7

1.7

3.6

0.45

0.2

2.4

V_CCIO– 0.2

2.4

4

2

–4

–2

(3)

3.3-V LVCMOS

3.6

(3)

3.0-V LVTTL

3.15 –0.3

2.625 –0.3

V_CCIO+ 0.3

0.45

0.2

4

–4

3.0-V LVCMOS

2.85

V_CCIO– 0.2

2.0

0.1

1

–0.1

–1

(3)

2.5 V

2.375

0.4

0.35 x 0.65 x

V_CCIOV_CCIO

V_CCIO

0.45

–

1.8 V

1.71

1.425

1.14

2.85

1.8

1.5

1.2

3.0

1.89 –0.3

1.575 –0.3

1.26 –0.3

2.25

0.45

2

–2

0.35 x 0.65 x

V_CCIOV_CCIO

0.25 x

V_CCIO

0.75 x

V_CCIO

1.5 V

V_CCIO+ 0.3

0.35 x 0.65 x

0.25 x

V_CCIO

0.75 x

V_CCIO

1.2 V

2

–2

V_CCIO

0.3 x

V_CCIO

0.5 x

V_CCIO

3.0-V PCI

3.0-V PCI-X

3.15

—

V_CCIO+ 0.3 0.1 x V_CCIO0.9 x V_CCIO

1.5

–0.5

0.35 x

V_CCIO

0.5 x

V_CCIO

Notes to Table 1–15:

(1) For voltage-referenced receiver input waveform and explanation of terms used in Table 1–15, refer to “Glossary” on page 1–37.

(2) AC load CL = 10 pF

(3) For more information about interfacing Cyclone IV devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III

and Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

(4) To meet the I^OLand IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4

mA), set the current strength settings to 4 mA or higher. Setting at lower current strength may not meet the I^OLand IOH specifications in the handbook.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

1–13

Max

Table 1–16. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Cyclone IV Devices ⁽¹⁾

(2)

V

_CCIO(V)

Typ

V_REF(V)

Typ

V_TT(V)

Typ

I/O

Standard

Min

Max

Min

Max

Min

SSTL-2

V_REF

0.04

–

V_REF

0.04

+

2.375 2.5 2.625

1.19

1.25

0.9

1.31

V_REF

0.9

Class I, II

SSTL-18

Class I, II

V_REF

0.04

–

V_REF

0.04

+

1.7

1.8

1.9

0.833

0.85

0.71

0.969

0.95

0.79

HSTL-18

Class I, II

1.71

1.89

0.9

0.85

0.71

0.95

0.79

HSTL-15

Class I, II

1.425 1.5 1.575

0.75

(3)

(4)

(3)

(4)

(3)

(4)

0.48 x V_CCIO

0.47 x V_CCIO

0.5 x V_CCIO

0.52 x V_CCIO

0.53 x V_CCIO

HSTL-12

Class I, II

0.5 x

V_CCIO

1.14

1.2

1.26

—

Notes to Table 1–16:

(1) For an explanation of terms used in Table 1–16, refer to “Glossary” on page 1–37.

(2) V_TTof the transmitting device must track V_REFof the receiving device.

(3) Value shown refers to DC input reference voltage, V_REF(DC)

(4) Value shown refers to AC input reference voltage, V_REF(AC)

.

Table 1–17. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone IV Devices

V_IL(DC)(V)

Min Max

V_REF

V_IH(DC)(V)

Max

V_IL(AC)(V)

Min Max

V_REF

V_IH(AC)(V)

Min Max

V_OL(V)

Max

V_OH(V)

Min

I/O

I_OL

I_OH

Standard

(mA) (mA)

Min

SSTL-2

Class I

–

V_REF

0.18

+

–

V_REF

0.35

+

V_TT

–

V_TT+

0.57

—

8.1

16.4 –16.4

6.7 –6.7

13.4 –13.4

–8.1

0.18

0.35

0.57

SSTL-2

Class II

V_REF

0.18

–

V_REF

0.18

+

V_REF

–

V_REF

0.35

+

V_TT

–

V_TT+

0.76

—

0.35

0.76

SSTL-18

Class I

V_REF

0.125

–

V_REF

+

V_REF

–

V_REF

0.25

+

V_TT

–

V_TT

+

—

0.125

0.25

0.475

SSTL-18

Class II

V_REF

0.125

–

V_REF

+

V_REF

–

V_REF

0.25

+

V_CCIO

–

—

0.28

0.4

0.125

0.25

0.28

HSTL-18

Class I

V_REF

0.1

–

V_REF

0.1

+

V_REF

0.2

–

V_REF

0.2

+

V_CCIO

0.4

–

—

8

16

8

–8

–16

–8

HSTL-18

Class II

V_REF

0.1

V_REF

0.1

V_REF

0.2

–

V_REF

0.2

+

V_CCIO

0.4

–

—

HSTL-15

Class I

V_REF

0.1

V_REF

0.1

V_REF

0.2

V_REF

0.2

V_CCIO

0.4

—

HSTL-15

Class II

V_REF

0.1

V_REF

0.1

V_REF

0.2

V_REF

0.2

V_CCIO

0.4

—

16

8

–16

–8

HSTL-12

Class I

V_REF

0.08

V_REF

0.08

V_REF

V_CCIO

+

0.25 ×

V_CCIO

0.75 ×

V_CCIO

–0.15

V

_CCIO+ 0.15 –0.24

0.15

0.24

HSTL-12

Class II

V_REF

0.08

–

V_REF

0.08

+

V_REF

–

V_REF

+

V_CCIO

0.24

0.25 ×

V_CCIO

0.75 ×

V_CCIO

14

–14

0.15

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–14

Chapter 1: Cyclone IV Device Datasheet

Operating Conditions

f

For more information about receiver input and transmitter output waveforms, and for

other differential I/O standards, refer to the I/O Features in Cyclone IV Devices chapter.

Table 1–18. Differential SSTL I/O Standard Specifications for Cyclone IV Devices ⁽¹⁾

V_Swing(AC)

(V)

V_CCIO(V)

V_Swing(DC)(V)

V_X(AC)(V)

Typ

V_OX(AC)(V)

Typ

I/O Standard

Min Typ Max Min Max

Min

Max

Min Max

Min

Max

SSTL-2

Class I, II

V_CCIO/2

+ 0.2

V_CCI

0.7

V_CCIO/2 –

0.125

V

_CCIO/2

2.375 2.5 2.625 0.36 V_CCIOV_CCIO/2 – 0.2

V_CCIO/2 –

—

+ 0.125

O

SSTL-18

Class I, II

V

_CCIO/2

V_CCI

0.5

V_CCIO/2 –

0.125

V_CCIO/2

+ 0.125

1.7

1.8 1.90 0.25 V_CCIO

0.175

+ 0.175

O

Note to Table 1–18:

(1) Differential SSTL requires a V_REFinput.

Table 1–19. Differential HSTL I/O Standard Specifications for Cyclone IV Devices ⁽¹⁾

V

_CCIO(V)

V_DIF(DC)(V)

V_X(AC)(V)

Typ

V_CM(DC)(V)

V_DIF(AC)(V)

I/O Standard

Mi

Min Typ Max Min Max

Min

0.85

0.71

Max

0.95

0.79

Min

0.85

0.71

Typ

—

Max

0.95

0.79

Max

—

n

HSTL-18

Class I, II

1.71 1.8 1.89 0.2

1.425 1.5 1.575 0.2

—

0.4

HSTL-15

Class I, II

0.4

0.3

—

HSTL-12

Class I, II

0.52 x

V_CCIO

0.48 x

V_CCIO

0.52 x

V_CCIO

0.48 x

V_CCIO

1.14 1.2 1.26 0.16 V_CCIO0.48 x V_CCIO

—

Note to Table 1–19:

(1) Differential HSTL requires a V_REFinput.

(1)

Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices

(Part 1 of 2)

(2)

(3)

V_CCIO(V)

Typ

V_ID(mV)

V_IcM(V)

V_OD(mV)

V_OS(V)

I/O Standard

Min

Max Min Max Min

Condition

Max Min Typ Max Min

Typ

Max

0.05

D

_MAX500 Mbps

1.80

LVPECL

500 Mbps  D_MAX

 700 Mbps

(Row I/Os)

2.375

2.5

2.625 100

—

0.55

1.80

1.55

—

(6)

1.05

0.05

D

_MAX> 700 Mbps

_MAX 500 Mbps 1.80

LVPECL

(Column

500 Mbps  D_MAX

700 Mbps

2.375

0.55

1.80

1.55

—

(6)

I/Os)

1.05

0.05

D

_MAX> 700 Mbps

_MAX 500 Mbps 1.80

LVDS (Row

I/Os)

500 Mbps  D_MAX

 700 Mbps

0.55

1.80 247

1.55

600 1.125 1.25 1.375

1.05 D_MAX> 700 Mbps

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–15

Operating Conditions

(1)

Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices

(Part 2 of 2)

(2)

(3)

V_CCIO(V)

Typ

V_ID(mV)

V_IcM(V)

V_OD(mV)

Max Min Typ Max Min

V_OS(V)

Typ

I/O Standard

Min

Max Min Max Min

Condition

Max

0.05

D_MAX 500 Mbps 1.80

LVDS

(Column

I/Os)

500 Mbps  D_MAX

 700 Mbps

2.375

2.5

2.625 100

—

0.55

1.05

—

1.80 247

1.55

—

600 1.125 1.25 1.375

D

_MAX> 700 Mbps

BLVDS (Row

I/Os)

2.375

2.5

2.625 100

—

(4)

BLVDS

(Column

I/Os)

—

(4)

mini-LVDS

(Row I/Os)

2.375

2.5

2.625

—

300

—

600

1.0

1.2

1.4

(5)

mini-LVDS

(Column

I/Os)

2.375

2.5

2.625

—

1.0

0.5

1.2

1.4

1.5

1.4

(5)

RSDS^®(Row

100 200 600

I/Os) ⁽⁵⁾

RSDS

(Column

I/Os)

(5)

PPDS (Row

I/Os)

(5)

PPDS

(Column

I/Os)

(5)

Notes to Table 1–20:

(1) For an explanation of terms used in Table 1–20, refer to “Glossary” on page 1–37.

(2) V_INrange: 0 V  V_IN 1.85 V.

(3) R_Lrange: 90  R_L 110  .

(4) There are no fixed V_IN, V_OD, and V_OSspecifications for BLVDS. They depend on the system topology.

(5) The Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins.

(6) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–16

Chapter 1: Cyclone IV Device Datasheet

Power Consumption

Use the following methods to estimate power for a design:

■

the Excel-based EPE

the Quartus^II PowerPlay power analyzer feature

The interactive Excel-based EPE is used prior to designing the device to get a

magnitude estimate of the device power. The Quartus II PowerPlay power analyzer

provides better quality estimates based on the specifics of the design after

place-and-route is complete. The PowerPlay power analyzer can apply a combination

of user-entered, simulation-derived, and estimated signal activities that, combined

with detailed circuit models, can yield very accurate power estimates.

f

For more information about power estimation tools, refer to the Early Power Estimator

User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II

Handbook.

Switching Characteristics

This section provides performance characteristics of Cyclone IV core and periphery

blocks for commercial grade devices.

These characteristics can be designated as Preliminary or Final.

■

Preliminary characteristics are created using simulation results, process data, and

other known parameters. The upper-right hand corner of these tables show the

designation as “Preliminary”.

Final numbers are based on actual silicon characterization and testing. The

numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. There are no designations

on finalized tables.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–17

Switching Characteristics

Transceiver Performance Specifications

Table 1–21 lists the Cyclone IV GX transceiver specifications.

Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)

C6

Typ

C7, I7

Typ

C8

Symbol/

Description

Conditions

Unit

Min

Max

Min

Max

Min

Typ

Max

Reference Clock

Supported I/O

Standards

1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL

Input frequency

from REFCLK input

pins

—

50

—

156.25

50

—

156.25

50

—

156.25

MHz

Spread-spectrum

modulating clock

frequency

Physical interface

for PCI Express

(PIPE) mode

30

—

33

—

30

—

33

—

30

—

33

—

kHz

—

Spread-spectrum

downspread

0 to

–0.5%

0 to

–0.5%

0 to

–0.5%

PIPE mode

Peak-to-peak

differential input

voltage

—

0.1

—

1.6

0.1

—

1100 5%

—

1.6

0.1

—

1.6

V

V_ICM(AC coupled)

1100 5%

—

1100 5%

—

mV

HCSL I/O

standard for PCIe

reference clock

V_ICM(DC coupled)

250

550

250

550

250

550

Transmitter REFCLK

Phase Noise ⁽¹⁾

—

–123

42.3

—

–123

42.3

—

–123

42.3

—

dBc/Hz

ps

Frequency offset

= 1 MHz – 8 MHZ

Transmitter REFCLK

Total Jitter ⁽¹⁾

2000

1%

2000

1%

2000

1%

R_ref

—



Transceiver Clock

cal_blk_clk clock

frequency

—

10

—

125

—

10

—

125

—

10

—

125

—

MHz

fixedclk clock

frequency

PCIe Receiver

Detect

—

125

—

125

—

125

Dynamic

reconfiguration

clock frequency

2.5/

reconfig_clk

clock frequency

37.5

—

50

2

37.5

—

50

2

37.5

—

50

2

MHz

ms

(2)

Delta time between

reconfig_clk

—

Transceiver block

minimum

power-down pulse

width

—

1

—

1

—

1

—

µs

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–18

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 2 of 4)

C6

C7, I7

Typ

C8

Symbol/

Conditions

Description

Unit

Min

Typ

Max

Min

Max

Min

Typ

Max

Receiver

1.4 V PCML,

1.5 V PCML,

2.5 V PCML,

LVPECL, LVDS

Supported I/O

Standards

Data rate (F324 and

smaller package) ⁽¹⁵⁾

—

600

—

2500

3125

1.6

600

—

2500

3125

1.6

600

—

2500

1.6

Mbps

Data rate (F484 and

larger package) ⁽¹⁵⁾

Mbps

Absolute V_MAXfor a

V

(3)

receiver pin

Operational V_MAXfor

a receiver pin

—

1.5

—

1.5

—

1.5

Absolute V_MINfor a

receiver pin

–0.4

—

–0.4

—

–0.4

—

V_ICM= 0.82 V

setting, Data Rate

= 600 Mbps to

3.125 Gbps

Peak-to-peak

differential input

voltage V_ID(diff p-p)

0.1

—

2.7

—

0.1

—

2.7

—

0.1

—

2.7

—

V

_ICM= 0.82 V

820

10%

820

10%

820

10%

V_ICM

—

mV

setting

100 setting

150 setting

—

100

150

—

100

150

—

100

150

—



Differential on-chip

termination resistors

PIPE, Serial

Rapid I/O SR,

SATA, CPRI LV,

SDI, XAUI

Differential and

common mode

return loss

Compliant

—

Programmable ppm

detector

62.5, 100, 125, 200,

250, 300

—

ppm

(4)

Clock data recovery

(CDR) ppm

tolerance (without

spread-spectrum

clocking enabled)

300

,

(5),

300

(5),

(5)

—

350

—

ppm

350

(6), (7)

CDR ppm tolerance

(with synchronous

spread-spectrum

350 to

—

–5350

—

–5350

ppm

(7), (9)

clocking enabled) ⁽⁸⁾

Run length

—

80

—

1.5

4.5

5.5

7

—

80

—

1.5

4.5

5.5

7

—

80

—

1.5

4.5

5.5

7

UI

dB

No Equalization

Medium Low

Medium High

High

Programmable

equalization

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–19

Switching Characteristics

Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 3 of 4)

C6

C7, I7

Typ

C8

Symbol/

Conditions

Description

Unit

Min

Typ

Max

Min

Max

Min

Typ

Max

Signal detect/loss

threshold

PIPE mode

65

—

175

65

—

175

65

—

175

mV

(10)

t_LTR

—

15

0

—

75

—

15

0

—

75

—

15

0

—

75

µs

ns

(11)

t_{LTR-LTD_Manual}

—

(12)

t_LTD

100

—

4000

100

—

4000

100

—

4000

(13)

t_{LTD_Manual}

—

(14)

t_{LTD_Auto}

—

Receiver buffer and

CDR offset

cancellation time

(per channel)

recon

fig_c

lk

—

17000

—

17000

—

17000

cycles

DC Gain Setting =

0

—

0

3

6

—

0

3

6

—

0

3

6

—

dB

Programmable DC

gain

DC Gain Setting =

1

DC Gain Setting =

2

Transmitter

Supported I/O

Standards

1.5 V PCML

Data rate (F324 and

smaller package)

—

600

—

2500

3125

600

—

2500

3125

600

—

2500

Mbps

Data rate (F484 and

larger package)

V_OCM

0.65 V setting

100 setting

150 setting

—

650

100

150

—

650

100

150

—

650

100

150

—

mV



Differential on-chip

termination resistors



PIPE, CPRI LV,

Serial Rapid I/O

SR, SDI, XAUI,

SATA

Differential and

common mode

return loss

Compliant

—

Rise time

Fall time

—

50

—

200

50

—

200

50

—

200

ps

Intra-differential pair

skew

—

15

—

15

—

15

ps

Intra-transceiver

block skew

120

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–20

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 4 of 4)

C6

C7, I7

Typ

C8

Symbol/

Conditions

Description

Unit

Min

Typ

Max

Min

Max

Min

Typ

Max

PLD-Transceiver Interface

Interface speed

(F324 and smaller

package)

—

25

—

125

25

—

125

25

—

125

MHz

Interface speed

(F484 and larger

package)

—

156.25

Digital reset pulse

width

Minimum is 2 parallel clock cycles

Notes to Table 1–21:

(1) This specification is valid for transmitter output jitter specification with a maximum total jitter value of 112 ps, typically for 3.125 Gbps SRIO and XAUI

protocols.

(2) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk frequency

is 37.5 MHz if the transceiver channel is configured in Receiver Only or Receiver and Transmitter mode.

(3) The device cannot tolerate prolonged operation at this absolute maximum.

(4) The rate matcher supports only up to 300 parts per million (ppm).

(5) Supported for the F169 and F324 device packages only.

(6) Supported for the F484, F672, and F896 device packages only. Pending device characterization.

(7) To support CDR ppm tolerance greater than 300 ppm, implement ppm detector in user logic and configure CDR to Manual Lock Mode.

(8) Asynchronous spread-spectrum clocking is not supported.

(9) For the EP4CGX30 (F484 package only), EP4CGX50, and EP4CGX75 devices, the CDR ppl tolerance is 200 ppm.

(10) Time taken until pll_locked goes high after pll_powerdown deasserts.

(11) Time that the CDR must be kept in lock-to-reference mode after rx_analogreset deasserts and before rx_locktodata is asserted in manual mode.

(12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode (Figure 1–2), or after rx_freqlocked signal goes high in

automatic mode (Figure 1–3).

(13) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode.

(14) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode.

(15) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–21

Switching Characteristics

Figure 1–2 shows the lock time parameters in manual mode.

LTD = lock-to-data. LTR = lock-to-reference.

1

Figure 1–2. Lock Time Parameters for Manual Mode

Reset Signals

2

rx _analogreset

4

rx _ digitalreset

t_{LTD_Manual (2)}

CDR Control Signals

rx _ locktorefclk

3

t_{LTR_LTD_Manual (1)}

3

rx _ locktodata

Two parallel clock cycles

Output Status Signals

1

busy

Figure 1–3 shows the lock time parameters in automatic mode.

Figure 1–3. Lock Time Parameters for Automatic Mode

Reset Signals

2

rx _analogreset

rx _ digitalreset

4

Two parallel clock cycles

Output Status Signals

busy

1

3

rx _ freqlocked

t_{LTD_Auto (1)}

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–22

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Figure 1–4 shows the differential receiver input waveform.

Figure 1–4. Receiver Input Waveform

Single-Ended Waveform

Positive Channel (p)

V

ID

Negative Channel (n)

V

CM

Ground

Differential Waveform

V

(diff peak-peak) = 2 x V (single-ended)

ID

V

ID

p − n = 0 V

V

ID

Figure 1–5 shows the transmitter output waveform.

Figure 1–5. Transmitter Output Waveform

Single-Ended Waveform

Positive Channel (p)

V

OD

Negative Channel (n)

V

CM

Ground

Differential Waveform

V

(diff peak-peak) = 2 x V

OD

(single-ended)

OD

V

OD

p − n = 0 V

V

OD

Table 1–22 lists the typical V_ODfor Tx term that equals 100 .

Table 1–22. Typical V_ODSetting, Tx Term = 100 

V_ODSetting (mV)

Symbol

(1)

1

2

3

4

5

6

V

_ODdifferential peak

400

600

800

900

1000

1200

to peak typical (mV)

Note to Table 1–22:

(1) This setting is required for compliance with the PCIe protocol.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–23

Switching Characteristics

Table 1–23 lists the Cyclone IV GX transceiver block AC specifications.

Table 1–23. Transceiver Block AC Specification for Cyclone IV GX Devices ^{(1), (2)}

C6

C7, I7

Min Typ

C8

Symbol/

Description

Conditions

Unit

Min Typ Max

Max Min Typ Max

(3)

PCIe Transmit Jitter Generation

Total jitter at 2.5 Gbps

(Gen1)

Compliance pattern

—

0.25

—

0.25

—

0.25

UI

(3)

PCIe Receiver Jitter Tolerance

Total jitter at 2.5 Gbps

(Gen1)

Compliance pattern

> 0.6

(4)

GIGE Transmit Jitter Generation

Deterministic jitter

Pattern = CRPAT

—

0.14

—

0.14

—

0.14

UI

(peak-to-peak)

Total jitter (peak-to-peak) Pattern = CRPAT

0.279

0.279 UI

(4)

GIGE Receiver Jitter Tolerance

Deterministic jitter

Pattern = CJPAT

> 0.4

UI

tolerance (peak-to-peak)

Combined deterministic

and random jitter

Pattern = CJPAT

> 0.66

tolerance (peak-to-peak)

Notes to Table 1–23:

(1) Dedicated refclk pins were used to drive the input reference clocks.

(2) The jitter numbers specified are valid for the stated conditions only.

(3) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.

(4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

Core Performance Specifications

The following sections describe the clock tree specifications, PLLs, embedded

multiplier, memory block, and configuration specifications for Cyclone IV Devices.

Clock Tree Specifications

Table 1–24 lists the clock tree specifications for Cyclone IV devices.

Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 1 of 2)

Performance

Device

EP4CE6

Unit

(1)

C6

C7

C8

C8L

C9L

265

I7

I8L

362

A7

500

437.5

402

362

437.5

402

MHz

EP4CE10

EP4CE15

EP4CE22

EP4CE30

EP4CE40

265

362

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–24

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 2 of 2)

Performance

Device

Unit

(1)

C6

C7

C8

C8L

362

C9L

265

I7

I8L

A7

—

EP4CE55

500

—

437.5

402

437.5

362

MHz

EP4CE75

362

—

265

—

362

—

EP4CE115

EP4CGX15

EP4CGX22

EP4CGX30

EP4CGX50

EP4CGX75

EP4CGX110

EP4CGX150

Note to Table 1–24:

500

—

(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades.

PLL Specifications

Table 1–25 lists the PLL specifications for Cyclone IV devices when operating in the

commercial junction temperature range (0°C to 85°C), the industrial junction

temperature range (–40°C to 100°C), the extended industrial junction temperature

range (–40°C to 125°C), and the automotive junction temperature range (–40°C to

125°C). For more information about the PLL block, refer to “Glossary” on page 1–37.

Table 1–25. PLL Specifications for Cyclone IV Devices ^{(1), (2)}(Part 1 of 2)

Symbol

Parameter

Input clock frequency (–6, –7, –8 speed grades)

Input clock frequency (–8L speed grade)

Input clock frequency (–9L speed grade)

PFD input frequency

Min

5

Typ

—

Max

472.5

362

Unit

MHz

%

(3)

f_IN

5

265

f_INPFD

5

325

(4)

f_VCO

PLL internal VCO operating range

Input clock duty cycle

600

40

1300

60

f_INDUTY

Input clock cycle-to-cycle jitter

—

0.15

750

UI

ps

(5)

F_REF 100 MHz

t_{INJITTER_CCJ}

F_REF< 100 MHz

f_{OUT_EXT}(external clock

PLL output frequency

472.5

MHz

(3)

output)

PLL output frequency (–6 speed grade)

—

45

—

50

—

472.5

450

402.5

362

265

55

MHz

%

PLL output frequency (–7 speed grade)

f_OUT(to global clock)

PLL output frequency (–8 speed grade)

PLL output frequency (–8L speed grade)

PLL output frequency (–9L speed grade)

Duty cycle for external clock output (when set to 50%)

Time required to lock from end of device configuration

t_OUTDUTY

t_LOCK

1

ms

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–25

Switching Characteristics

Table 1–25. PLL Specifications for Cyclone IV Devices ^{(1), (2)}(Part 2 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Time required to lock dynamically (after switchover,

reconfiguring any non-post-scale counters/delays or

areset is deasserted)

t_DLOCK

—

1

ms

Dedicated clock output period jitter

—

300

30

ps

mUI

ps

(6)

F_OUT 100 MHz

t_{OUTJITTER_PERIOD_DEDCLK}

F_OUT< 100 MHz

Dedicated clock output cycle-to-cycle jitter

300

30

(6)

F_OUT 100 MHz

t_{OUTJITTER_CCJ_DEDCLK}

F_OUT< 100 MHz

mUI

ps

Regular I/O period jitter

_OUT 100 MHz

650

75

(6)

F

t_{OUTJITTER_PERIOD_IO}

F_OUT< 100 MHz

mUI

ps

Regular I/O cycle-to-cycle jitter

650

(6)

F_OUT 100 MHz

t_{OUTJITTER_CCJ_IO}

F

_OUT< 100 MHz

—

10

—

75

50

—

mUI

ps

t_{PLL_PSERR}

t_ARESET

Accuracy of PLL phase shift

Minimum pulse width on areset signal.

ns

SCANCLK

cycles

(7)

t_CONFIGPLL

f_SCANCLK

Time required to reconfigure scan chains for PLLs

—

3.5

—

scanclk frequency

—

100

425

MHz

Period jitter for dedicated clock output in cascaded

PLLs (F_OUT 100 MHz)

ps

t_{CASC_OUTJITTER_PERIOD_DEDCLK}

(8), (9)

Period jitter for dedicated clock output in cascaded

PLLs (F_OUT 100 MHz)

—

42.5

mUI

Notes to Table 1–25:

(1) This table is applicable for general purpose PLLs and multipurpose PLLs.

(2) You must connect V_{CCD_PLL}to V_CCINTthrough the decoupling capacitor and ferrite bead.

(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O

standard.

(4) The V_COfrequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the V_CO

post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCOspecification.

(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less

than 200 ps.

(6) Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies

to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.

(7) With 100-MHz scanclk frequency.

(8) The cascaded PLLs specification is applicable only with the following conditions:

■

Upstream PLL—0.59 MHz  Upstream PLL bandwidth < 1 MHz

■

Downstream PLL—Downstream PLL bandwidth > 2 MHz

(9) PLL cascading is not supported for transceiver applications.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–26

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Embedded Multiplier Specifications

Table 1–26 lists the embedded multiplier specifications for Cyclone IV devices.

Table 1–26. Embedded Multiplier Specifications for Cyclone IV Devices

Resources Used

Mode

Performance

Unit

Number of Multipliers

C6

C7, I7, A7

300

C8

C8L, I8L

240

C9L

175

135

9 × 9-bit multiplier

1

340

287

260

200

MHz

18 × 18-bit multiplier

250

185

Memory Block Specifications

Table 1–27 lists the M9K memory block specifications for Cyclone IV devices.

Table 1–27. Memory Block Performance Specifications for Cyclone IV Devices

Resources Used

Performance

Memory

Mode

Unit

M9K

Memory

LEs

C6 C7, I7, A7 C8 C8L,I8L C9L

FIFO 256 × 36

47

0

1

315

274

238

200

157 MHz

Single-port 256 × 36

M9K Block

Simple dual-port 256 × 36 CLK

True dual port 512 × 18 single CLK

0

Configuration and JTAG Specifications

Table 1–28 lists the configuration mode specifications for Cyclone IV devices.

Table 1–28. Passive Configuration Mode Specifications for Cyclone IV Devices ⁽¹⁾

Programming Mode

Passive Serial (PS)

V_CCINTVoltage Level (V)

DCLK f_MAX

66

Unit

MHz

(3)

1.0

1.2

133

(3)

1.0

66

(2)

Fast Passive Parallel (FPP)

(4)

1.2

100

Notes to Table 1–28:

(1) For more information about PS and FPP configuration timing parameters, refer to the Configuration and Remote

System Upgrades in Cyclone IV Devices chapter.

(2) FPP configuration mode supports all Cyclone IV E devices (except for E144 package devices) and EP4CGX50,

EP4CGX75, EP4CGX110, and EP4CGX150 only.

(3) V_CCINT= 1.0 V is only supported for Cyclone IV E 1.0 V core voltage devices.

(4) Cyclone IV E devices support 1.2 V V_CCINT. Cyclone IV E 1.2 V core voltage devices support 133 MHz DCLK f_MAXfor

EP4CE6, EP4CE10, EP4CE15, EP4CE22, EP4CE30, and EP4CE40 only.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–27

Switching Characteristics

Table 1–29 lists the active configuration mode specifications for Cyclone IV devices.

Table 1–29. Active Configuration Mode Specifications for Cyclone IV Devices

Programming Mode

DCLK Range

20 to 40

Typical DCLK

Unit

MHz

(1)

Active Parallel (AP)

33

Active Serial (AS)

20 to 40

Note to Table 1–29:

(1) AP configuration mode is only supported for Cyclone IV E devices.

Table 1–30 lists the JTAG timing parameters and values for Cyclone IV devices.

Table 1–30. JTAG Timing Parameters for Cyclone IV Devices ⁽¹⁾

Symbol

t_JCP

Parameter

Min

40

19

1

Max

—

15

—

25

Unit

ns

TCK clock period

t_JCH

TCK clock high time

TCK clock low time

t_JCL

t_{JPSU_TDI}JTAG port setup time for TDI

t_{JPSU_TMS}JTAG port setup time for TMS

3

t_JPH

JTAG port hold time

10

—

5

(2), (3)

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock to output

(2), (3)

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

10

—

t_JSCO

t_JSZX

t_JSXZ

Update register clock to output

Update register high impedance to valid output

Update register valid output to high impedance

Notes to Table 1–30:

(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–37.

(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V

LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.

(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time

specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS

and 1.5-V LVCMOS, the output time specification is 18 ns.

Periphery Performance

This section describes periphery performance, including high-speed I/O and external

memory interface.

I/O performance supports several system interfaces, such as the high-speed I/O

interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the

SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM

interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,

1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency

with a 10 pF load.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–28

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

f

1

For more information about the supported maximum clock rate, device and pin

planning, IP implementation, and device termination, refer to Section III: System

Performance Specifications of the External Memory Interfaces Handbook.

Actual achievable frequency depends on design- and system-specific factors. Perform

HSPICE/IBIS simulations based on your specific design and system setup to

determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

Table 1–31 through Table 1–36 list the high-speed I/O timing for Cyclone IV devices.

For definitions of high-speed timing specifications, refer to “Glossary” on page 1–37.

Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (2), (4)}(Part 1 of 2)

C6

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ

Max Min Typ Max Min Typ Max

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

5

—

180

360

5

—

155.5

311

5

—

155.5

311

5

—

155.5

311

5

—

132.5 MHz

265 MHz

265 Mbps

f_HSCLK

(input clock

frequency)

5

100

80

70

40

20

10

45

360 100

360 80

360 70

360 40

360 20

360 10

311 100

311

55

80

70

40

20

10

45

311

55

80

70

40

20

10

45

311

55

80

70

40

20

10

45

Device

operation in

Mbps

t_DUTY

55

45

55

%

Transmitter

channel-to-

channel skew

(TCCS)

—

200

—

200

—

200

—

200

—

200

ps

Output jitter

(peak to peak)

—

500

—

500

—

550

—

600

—

700

—

ps

20 – 80%,

t_RISE

C_LOAD

5 pF

=

500

20 – 80%,

t_FALL

C_LOAD

5 pF

=

—

500

—

500

—

500

—

500

—

500

—

ps

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

1–29

C9L

Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (2), (4)}(Part 2 of 2)

C6

C7, I7

C8, A7

C8L, I8L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ

Max Min Typ Max Min Typ Max

(3)

t_LOCK

—

1

—

1

—

1

—

1

—

1

ms

Notes to Table 1–31:

(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.

(2) Cyclone IV E devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the

output pin of all I/O Banks.

Cyclone IV GX devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated RSDS transmitter is supported at the output

pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.

(3) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7

speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (3)}(Part 1 of 2)

C6

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

5

—

85

5

—

85

5

—

85

5

—

85

5

—

72.5 MHz

145 MHz

145 Mbps

f

_HSCLK(input

5

85

clock

frequency)

5

85

5

85

5

170

100

80

70

40

20

10

45

—

170 100

170 80

170 70

170 40

170 20

170 10

170 100

170 80

170 70

170 40

170 20

170 10

170 100

170 80

170 70

170 40

170 20

170 10

170 100

170 80

170 70

170 40

170 20

170 10

Device

operation in

Mbps

t_DUTY

55

45

—

55

45

—

55

45

—

55

45

—

55

%

TCCS

200

ps

Output jitter

(peak to peak)

—

500

—

500

—

550

—

600

—

700

ps

20 – 80%,

t_RISE

—

500

—

500

—

500

—

500

—

500

—

ps

C_LOAD

5 pF

=

20 – 80%,

t_FALL

—

500

—

500

—

500

—

500

—

500

—

ps

C_LOAD

5 pF

=

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–30

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (3)}(Part 2 of 2)

C6

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max

(2)

t_LOCK

—

1

—

1

—

1

—

1

—

1

ms

Notes to Table 1–32:

(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks of Cyclone IV E devices and I/O Banks 3, 4, 5, 6, 7, 8, and 9 of Cyclone IV GX

devices.

(2) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and

A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Table 1–33. Mini-LVDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (2), (4)}

C6

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

5

—

200

400

5

—

155.5

311

5

—

155.5

311

5

—

155.5

311

5

—

132.5 MHz

265 MHz

265 Mbps

f_HSCLK(input

clock

frequency)

5

100

80

70

40

20

10

45

—

400 100

400 80

400 70

400 40

400 20

400 10

311 100

311

55

80

70

40

20

10

45

—

311

55

80

70

40

20

10

45

—

311

55

80

70

40

20

10

45

—

Device

operation in

Mbps

t_DUTY

55

45

—

55

%

TCCS

200

ps

Output jitter

(peak to peak)

—

500

—

500

—

550

—

600

—

700

ps

20 – 80%,

t_RISE

C_LOAD

5 pF

=

—

500

—

500

—

500

—

500

—

500

—

ps

20 – 80%,

t_FALL

C_LOAD

5 pF

=

—

500

—

1

—

500

—

1

—

500

—

1

—

500

—

1

—

500

—

1

ps

(3)

t_LOCK

—

ms

Notes to Table 1–33:

(1) Applicable for true and emulated mini-LVDS transmitter.

(2) Cyclone IV E—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at

the output pin of all I/O banks.

Cyclone IV GX—true mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated mini-LVDS transmitter is supported at the

output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.

(3) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and

A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–31

Switching Characteristics

Table 1–34. True LVDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (3)}

C6

C7, I7

Min

C8, A7

Min

C8L, I8L

Min

C9L

Symbol

Modes

Unit

Min

5

Max

420

840

420

55

Max

370

402.5

740

402.5

55

Max

320

402.5

640

402.5

55

Max

320

362

640

362

55

Min

5

Max

250

265

500

265

55

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

5

MHz

Mbps

%

5

f

_HSCLK(input

clock

frequency)

5

100

80

70

40

20

10

45

—

100

80

70

40

20

10

45

—

100

80

70

40

20

10

45

—

100

80

70

40

20

10

45

—

100

80

70

40

20

10

45

—

HSIODR

t_DUTY

TCCS

200

ps

Output jitter

(peak to peak)

—

500

1

—

500

1

—

550

1

—

600

1

—

700

1

ps

(2)

t_LOCK

—

ms

Notes to Table 1–34:

(1) Cyclone IV E—true LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6.

Cyclone IV GX—true LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6.

(2) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support

C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (3)}(Part 1 of 2)

C6

C7, I7

C8, A7

C8L, I8L

Min

C9L

Symbol

Modes

Unit

Min

5

Max

320

Min

Max

320

Min

Max

275

Max

275

362

550

362

Min

5

Max

250

265

500

265

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

5

MHz

5

320

275

5

f

_HSCLK(input

clock

frequency)

5

320

5

320

5

275

5

MHz

5

320

5

320

5

275

5

MHz

5

320

5

320

5

275

5

MHz

5

402.5

640

5

402.5

640

5

402.5

550

5

MHz

100

80

70

40

20

10

100

80

70

40

20

10

100

80

70

40

20

10

100

80

70

40

20

10

100

80

70

40

20

10

Mbps

640

550

640

550

HSIODR

640

550

640

550

402.5

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–32

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (3)}(Part 2 of 2)

C6

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

t_DUTY

Modes

Unit

Min

45

Max

55

Min

Max

55

Min

Max

55

Min

Max

55

Min

45

Max

55

—

45

—

45

—

45

—

%

TCCS

—

200

—

200

ps

Output jitter

(peak to peak)

—

500

—

500

—

550

—

600

1

—

700

1

ps

(2)

t_LOCK

—

1

—

1

—

1

ms

Notes to Table 1–35:

(1) Cyclone IV E—emulated LVDS transmitter is supported at the output pin of all I/O Banks.

Cyclone IV GX—emulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.

(2) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support

C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices ^{(1), (3)}

C6

C7, I7

Min

C8, A7

Min

C8L, I8L

Min

C9L

Symbol

Modes

Unit

Min

10

100

80

70

40

20

10

—

Max

437.5

875

Max

370

402.5

740

402.5

400

Max

320

402.5

640

402.5

400

Max

320

362

640

362

550

Min

10

100

80

70

40

20

10

—

Max

250

265

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

10

100

80

70

40

20

10

—

10

100

80

70

40

20

10

—

10

100

80

70

40

20

10

—

MHz

f

_HSCLK(input

clock

frequency)

500 Mbps

265 Mbps

875

HSIODR

SW

875

437.5

400

640

700

1

ps

Input jitter

tolerance

—

500

—

500

—

550

—

600

1

—

ps

(2)

t_LOCK

—

1

—

1

—

1

ms

Notes to Table 1–36:

(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.

Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.

(2) t_LOCKis the time required for the PLL to lock from the end-of-device configuration.

(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support

C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

External Memory Interface Specifications

The external memory interfaces for Cyclone IV devices are auto-calibrating and easy

to implement.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–33

Switching Characteristics

f

For more information about the supported maximum clock rate, device and pin

planning, IP implementation, and device termination, refer to Section III: System

Performance Specifications of the External Memory Interface Handbook.

Table 1–37 lists the memory output clock jitter specifications for Cyclone IV devices.

Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices ^{(1), (2)}

Parameter

Clock period jitter

Symbol

t_JIT(per)

t_JIT(cc)

Min

–125

–200

–150

Max

125

200

150

Unit

ps

Cycle-to-cycle period jitter

Duty cycle jitter

ps

t_JIT(duty)

ps

Notes to Table 1–37:

(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2

standard.

(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL

output routed on a global clock (GCLK) network.

Duty Cycle Distortion Specifications

Table 1–38 lists the worst case duty cycle distortion for Cyclone IV devices.

(1), (2), (3)

Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins

C6

C7, I7

C8, I8L, A7

C9L

Symbol

Unit

Min

Max

Min

Max

Min

45

Max

Min

Max

Output Duty Cycle

45

55

45

55

45

55

%

Notes to Table 1–38:

(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general

purpose I/O pins.

(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current

strength.

(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support

C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.

OCT Calibration Timing Specification

Table 1–39 lists the duration of calibration for series OCT with calibration at device

power-up for Cyclone IV devices.

Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for

(1)

Cyclone IV Devices

Symbol

Description

Maximum

Units

Duration of series OCT with

calibration at device power-up

t_OCTCAL

20

µs

Note to Table 1–39:

(1) OCT calibration takes place after device configuration and before entering user mode.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–34

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

IOE Programmable Delay

Table 1–40 and Table 1–41 list the IOE programmable delay for Cyclone IV E 1.0 V

core voltage devices.

Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices ^{(1), (2)}

Max Offset

Number

Min

Parameter

Paths Affected

of

Fast Corner

C8L I8L

Slow Corner

C9L

Unit

Offset

Setting

C8L

I8L

Input delay from pin to

internal cells

Pad to I/O

dataout to core

7

8

2

0

2.054 1.924 3.387 4.017 3.411

2.010 1.875 3.341 4.252 3.367

0.641 0.631 1.111 1.377 1.124

ns

Input delay from pin to

input register

Pad to I/O input

register

Delay from output register

to output pin

I/O output

register to pad

Input delay from

dual-purpose clock pin to

fan-out destinations

Pad to global

clock network

12

0

0.971 0.931 1.684 2.298 1.684

ns

Notes to Table 1–40:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

(2)

Table 1–41. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices ^(1),

Max Offset

Number

Min

Parameter

Paths Affected

of

Fast Corner

C8L I8L

Slow Corner

C9L

Unit

Offset

Setting

C8L

I8L

Input delay from pin to

internal cells

Pad to I/O

dataout to core

7

8

2

0

2.057 1.921 3.389 4.146 3.412

2.059 1.919 3.420 4.374 3.441

0.670 0.623 1.160 1.420 1.168

ns

Input delay from pin to

input register

Pad to I/O input

register

Delay from output register

to output pin

I/O output

register to pad

Input delay from

dual-purpose clock pin to

fan-out destinations

Pad to global

clock network

12

0

0.960 0.919 1.656 2.258 1.656

ns

Notes to Table 1–41:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–35

Switching Characteristics

Table 1–42 and Table 1–43 list the IOE programmable delay for Cyclone IV E 1.2 V

core voltage devices.

Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices ^{(1), (2)}

Max Offset

Number

Paths

Affected

Min

Offset

Parameter

of

Fast Corner

I7

Slow Corner

C8

Unit

Setting

C6

A7

C6

C7

I7

A7

Pad to I/O

dataout to

core

Input delay from pin to

internal cells

7

8

2

0

1.314 1.211 1.211 2.177 2.340 2.433 2.388 2.508 ns

1.307 1.203 1.203 2.19 2.387 2.540 2.430 2.545 ns

0.437 0.402 0.402 0.747 0.820 0.880 0.834 0.873 ns

Input delay from pin to Pad to I/O

input register

I/O output

register to

pad

Delay from output

register to output pin

Input delay from

dual-purpose clock pin clock

to fan-out destinations network

Pad to global

12

0

0.693 0.665 0.665 1.200 1.379 1.532 1.393 1.441 ns

Notes to Table 1–42:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Table 1–43. IOE Programmable Delay on Row Pins for Cyclone IV E 1.2 V Core Voltage Devices ^{(1), (2)}

Max Offset

Number

Paths

Affected

Min

Offset

Parameter

of

Fast Corner

I7

Slow Corner

C8

Unit

Setting

C6

A7

C6

C7

I7

A7

Pad to I/O

dataout to

core

Input delay from pin to

internal cells

7

8

2

0

1.314 1.209 1.209 2.201 2.386 2.510 2.429 2.548 ns

1.312 1.207 1.207 2.202 2.402 2.558 2.447 2.557 ns

0.458 0.419 0.419 0.783 0.861 0.924 0.875 0.915 ns

Input delay from pin to Pad to I/O

input register

I/O output

register to

pad

Delay from output

register to output pin

Input delay from

dual-purpose clock pin clock

to fan-out destinations network

Pad to global

12

0

0.686 0.657 0.657 1.185 1.360 1.506 1.376 1.422 ns

Notes to Table 1–43:

(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–36

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–44 and Table 1–45 list the IOE programmable delay for Cyclone IV GX

devices.

Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices ^{(1), (2)}

Max Offset

Slow Corner

C7 C8

Number

of

Settings

Paths

Affected

Min

Offset

Parameter

Fast Corner

C6 I7

Unit

C6

I7

Pad to I/O

dataout to

core

Input delay from pin to

internal cells

7

8

2

0

1.313 1.209 2.184 2.336 2.451 2.387

1.312 1.208 2.200 2.399 2.554 2.446

0.438 0.404 0.751 0.825 0.886 0.839

ns

Input delay from pin to Pad to I/O

input register

I/O output

register to

pad

Delay from output

register to output pin

Input delay from

dual-purpose clock pin clock

to fan-out destinations network

Pad to global

12

0

0.713 0.682 1.228

1.41

1.566 1.424

ns

Notes to Table 1–44:

(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.

Table 1–45. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices ^{(1), (2)}

Max Offset

Number

Paths

Affected

Min

Parameter

of

Fast Corner

Slow Corner

Unit

Offset

Settings

C6 I7

C6

C7 C8

I7

Pad to I/O

dataout to

core

Input delay from pin to

internal cells

7

8

2

0

1.314 1.210 2.209 2.398 2.526 2.443

1.313 1.208 2.205 2.406 2.563 2.450

0.461 0.421 0.789 0.869 0.933 0.884

ns

Input delay from pin to Pad to I/O

input register

I/O output

register to

pad

Delay from output

register to output pin

Input delay from

dual-purpose clock pin

to fan-out destinations

Pad to global

clock network

12

0

0.712 0.682 1.225 1.407 1.562 1.421

ns

Notes to Table 1–45:

(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–37

I/O Timing

Use the following methods to determine I/O timing:

■

the Excel-based I/O Timing

the Quartus II timing analyzer

■

The Excel-based I/O timing provides pin timing performance for each device density

and speed grade. The data is typically used prior to designing the FPGA to get a

timing budget estimation as part of the link timing analysis. The Quartus II timing

analyzer provides a more accurate and precise I/O timing data based on the specifics

of the design after place-and-route is complete.

f

The Excel-based I/O Timing spreadsheet is downloadable from Cyclone IV Devices

Literature website.

Glossary

Table 1–46 lists the glossary for this chapter.

Table 1–46. Glossary (Part 1 of 5)

Letter

Term

—

Definitions

A

B

C

D

E

—

F

f_HSCLK

GCLK

High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.

Input pin directly to Global Clock network.

G

H

GCLK PLL

HSIODR

Input pin to Global Clock network through the PLL.

High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).

V_IH

Input Waveforms

for the SSTL

Differential I/O

Standard

I

VSWING

V_REF

V_IL

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–38

Chapter 1: Cyclone IV Device Datasheet

Glossary

Table 1–46. Glossary (Part 2 of 5)

Letter

Term

Definitions

TMS

TDI

t_JCP

t_{JPSU_TDI}

t_{JPSU_TMS}

t_JCH

t _JCL

t_JPH

TCK

TDO

J

JTAG Waveform

t_JPXZ

t_JPZX

t_JPCO

t_JSSU

t_JSH

Signal

to be

Captured

t_JSZX

t_JSCO

t_JSXZ

Signal

to be

Driven

K

L

—

M

N

O

The following highlights the PLL specification parameters:

CLKOUT Pins

f_{OUT_EXT}

Switchover

CLK

f_IN

f_INPFD

N

f_VCO

VCO

PFD

CP

LF

f_OUT

GCLK

Counters

C0..C4

Core Clock

P

Q

PLL Block

Phase tap

M

Key

Reconfigurable in User Mode

—

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–39

Glossary

Table 1–46. Glossary (Part 3 of 5)

Letter

Term

Definitions

R_L

Receiver differential input discrete resistor (external to Cyclone IV devices).

Receiver input waveform for LVDS and LVPECL differential standards:

Single-Ended Waveform

Positive Channel (p) = V_IH

V_ID

Negative Channel (n) = V_IL

V_CM

Ground

Receiver Input

Waveform

R

Differential Waveform (Mathematical Function of Positive & Negative Channel)

V_ID

0 V

V_ID

p - n

Receiver input

skew margin

(RSKM)

High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.

RSKM = (TUI – SW – TCCS) / 2.

V_CCIO

V_OH

V_{IH AC}

(

)

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

Single-ended

voltage-

referenced I/O

Standard

V_OL

S

V_SS

The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal

values. The AC values indicate the voltage levels at which the receiver must meet its timing

specifications. The DC values indicate the voltage levels at which the final logic state of the

receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver

changes to the new logic state. The new logic state is then maintained as long as the input stays

beyond the DC threshold. This approach is intended to provide predictable receiver timing in the

presence of input waveform ringing.

SW (Sampling

Window)

High-speed I/O block: The period of time during which the data must be valid to capture it

correctly. The setup and hold times determine the ideal strobe position in the sampling window.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–40

Chapter 1: Cyclone IV Device Datasheet

Glossary

Table 1–46. Glossary (Part 4 of 5)

Letter

Term

Definitions

t_C

High-speed receiver and transmitter input and output clock period.

Channel-to-

channel-skew

(TCCS)

High-speed I/O block: The timing difference between the fastest and slowest output edges,

including t_COvariation and clock skew. The clock is included in the TCCS measurement.

t_cin

Delay from the clock pad to the I/O input register.

Delay from the clock pad to the I/O output.

t_CO

t_cout

t_DUTY

t_FALL

t_H

Delay from the clock pad to the I/O output register.

High-speed I/O block: Duty cycle on high-speed transmitter output clock.

Signal high-to-low transition time (80–20%).

Input register hold time.

Timing Unit

Interval (TUI)

High-speed I/O block: The timing budget allowed for skew, propagation delays, and data

sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).

t_INJITTER

Period jitter on the PLL clock input.

t_{OUTJITTER_DEDCLK}

t_{OUTJITTER_IO}

t_pllcin

Period jitter on the dedicated clock output driven by a PLL.

Period jitter on the general purpose I/O driven by a PLL.

Delay from the PLL inclk pad to the I/O input register.

Delay from the PLL inclk pad to the I/O output register.

t_pllcout

T

Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O

Standards:

Single-Ended Waveform

Positive Channel (p) = V_OH

V_OD

Negative Channel (n) = V_OL

V

os

Transmitter

Output

Ground

Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

V_OD

0 V

V_OD

p - n

t_RISE

t_SU

Signal low-to-high transition time (20–80%).

Input register setup time.

—

U

—

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–41

Glossary

Table 1–46. Glossary (Part 5 of 5)

Letter

Term

V_CM(DC)

Definitions

DC common mode input voltage.

V_DIF(AC)

V_DIF(DC)

V_ICM

AC differential input voltage: The minimum AC input differential voltage required for switching.

DC differential input voltage: The minimum DC input differential voltage required for switching.

Input common mode voltage: The common mode of the differential signal at the receiver.

Input differential voltage swing: The difference in voltage between the positive and

complementary conductors of a differential transmission at the receiver.

V_ID

V_IH

Voltage input high: The minimum positive voltage applied to the input that is accepted by the

device as a logic high.

V_IH(AC)

V_IH(DC)

High-level AC input voltage.

High-level DC input voltage.

Voltage input low: The maximum positive voltage applied to the input that is accepted by the

device as a logic low.

V_IL

V_{IL (AC)}

V_{IL (DC)}

V_IN

Low-level AC input voltage.

Low-level DC input voltage.

DC input voltage.

V_OCM

Output common mode voltage: The common mode of the differential signal at the transmitter.

Output differential voltage swing: The difference in voltage between the positive and

complementary conductors of a differential transmission at the transmitter. V_OD= V_OH– V_OL.

V_OD

V_OH

V

Voltage output high: The maximum positive voltage from an output that the device considers is

accepted as the minimum positive high level.

Voltage output low: The maximum positive voltage from an output that the device considers is

accepted as the maximum positive low level.

V_OL

V_OS

Output offset voltage: V_OS= (V_OH+ V_OL) / 2.

AC differential output cross point voltage: the voltage at which the differential output signals

must cross.

V_{OX (AC)}

V_REF

Reference voltage for the SSTL and HSTL I/O standards.

AC input reference voltage for the SSTL and HSTL I/O standards. V_REF(AC)= V_REF(DC)+ noise. The

V_{REF (AC)}

V_{REF (DC)}

V_{SWING (AC)}

peak-to-peak AC noise on V_REFmust not exceed 2% of V_REF(DC)

.

DC input reference voltage for the SSTL and HSTL I/O standards.

AC differential input voltage: AC input differential voltage required for switching. For the SSTL

differential I/O standard, refer to Input Waveforms.

DC differential input voltage: DC input differential voltage required for switching. For the SSTL

differential I/O standard, refer to Input Waveforms.

V_{SWING (DC)}

V_TT

Termination voltage for the SSTL and HSTL I/O standards.

AC differential input cross point voltage: The voltage at which the differential input signals must

cross.

V_{X (AC)}

W

X

Y

Z

—

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–42

Chapter 1: Cyclone IV Device Datasheet

Document Revision History

Table 1–47 lists the revision history for this chapter.

Table 1–47. Document Revision History

Date

Version

Changes

March 2016

2.0

Updated note (5) in Table 1–21 to remove support for the N148 package.

Updated maximum value for V_{CCD_PLL}in Table 1–1.

Removed extended temperature note in Table 1–3.

Updated Table 1–21 by adding Note (15).

October 2014

1.9

December 2013

May 2013

1.8

1.7

Updated Table 1–15 by adding Note (4).

■ Updated the maximum value for V_I, V_{CCD_PLL}, V_CCIO, V_{CC_CLKIN}, V_{CCH_GXB}, and V_{CCA_GXB}

Table 1–1.

■ Updated Table 1–11 and Table 1–22.

■ Updated Table 1–21 to include peak-to-peak differential input voltage for the

October 2012

1.6

Cyclone IV GX transceiver input reference clock.

■ Updated Table 1–29 to include the typical DCLK value.

■ Updated the minimum f_HSCLKvalue in Table 1–31, Table 1–32, Table 1–33,

Table 1–34, and Table 1–35.

■ Updated “Maximum Allowed Overshoot or Undershoot Voltage”, “Operating

Conditions”, and “PLL Specifications” sections.

November 2011

December 2010

1.5

1.4

■ Updated Table 1–2, Table 1–3, Table 1–4, Table 1–5, Table 1–8, Table 1–9,

Table 1–15, Table 1–18, Table 1–19, and Table 1–21.

■ Updated Figure 1–1.

■ Updated for the Quartus II software version 10.1 release.

■ Updated Table 1–21 and Table 1–25.

■ Minor text edits.

Updated for the Quartus II software version 10.0 release:

■ Updated Table 1–3, Table 1–4, Table 1–21, Table 1–25, Table 1–28, Table 1–30,

Table 1–40, Table 1–41, Table 1–42, Table 1–43, Table 1–44, and Table 1–45.

July 2010

1.3

■ Updated Figure 1–2 and Figure 1–3.

■ Removed SW Requirement and TCCS for Cyclone IV Devices tables.

■ Minor text edits.

Updated to include automotive devices:

■ Updated the “Operating Conditions” and “PLL Specifications” sections.

■ Updated Table 1–1, Table 1–8, Table 1–9, Table 1–21, Table 1–26, Table 1–27,

Table 1–31, Table 1–32, Table 1–33, Table 1–34, Table 1–35, Table 1–36,

Table 1–37, Table 1–38, Table 1–40, Table 1–42, and Table 1–43.

March 2010

1.2

■ Added Table 1–5 to include ESD for Cyclone IV devices GPIOs and HSSI I/Os.

■ Added Table 1–44 and Table 1–45 to include IOE programmable delay for

Cyclone IV E 1.2 V core voltage devices.

■ Minor text edits.

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

Chapter 1: Cyclone IV Device Datasheet

1–43

Document Revision History

Table 1–47. Document Revision History

Date

Version

Changes

■ Updated Table 1–3 through Table 1–44 to include information for Cyclone IV E

devices and Cyclone IV GX devices for Quartus II software version 9.1 SP1 release.

February 2010

November 2009

1.1

■ Minor text edits.

1.0

Initial release.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

1–44

Chapter 1: Cyclone IV Device Datasheet

Document Revision History

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation


型号：	EP4CE40F29I7N
厂家：	INTEL
描述：	Field Programmable Gate Array, 2475 CLBs, 472.5MHz, 39600-Cell, PBGA780, 29 X 29 MM, 1 MM PITCH, LEAD FREE, FBGA-780 时钟 LTE 栅可编程逻辑
文件：	总44页 (文件大小：663K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EP4CE40F29I7N [INTEL]

相关型号：

EP4CE40F29I8L

EP4CE40F29I8L

EP4CE40F29I8LN

EP4CE40U19I7N

EP4CE55

EP4CE55F17C8

EP4CE55F23C6

EP4CE55F23C6N

EP4CE55F23C6N

EP4CE55F23C7

EP4CE55F23C7N

EP4CE55F23C7N