EP4CGX30CF14C7N [INTEL]

Field Programmable Gate Array, PBGA169, LEAD FREE, FBGA-169;


型号：	EP4CGX30CF14C7N
厂家：	INTEL
描述：	Field Programmable Gate Array, PBGA169, LEAD FREE, FBGA-169 栅
文件：	总14页 (文件大小：382K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1. Cyclone IV FPGA Device Family

Overview

May 2013

CYIV-51001-1.8

Altera’s new Cyclone^®IV FPGA device family extends the Cyclone FPGA series

leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a

transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive

applications, enabling system designers to meet increasing bandwidth requirements

while lowering costs.

Built on an optimized low-power process, the Cyclone IV device family offers the

following two variants:

■

Cyclone IV E—lowest power, high functionality with the lowest cost

■

Cyclone IV GX—lowest power and lowest cost FPGAs with 3.125 Gbps

transceivers

Cyclone IV E devices are offered in core voltage of 1.0 V and 1.2 V.

f For more information, refer to the Power Requirements for Cyclone IV Devices

chapter.

Providing power and cost savings without sacrificing performance, along with a

low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost,

small-form-factor applications in the wireless, wireline, broadcast, industrial,

consumer, and communications industries.

Cyclone IV Device Family Features

The Cyclone IV device family offers the following features:

Low-cost, low-power FPGA fabric:

6K to 150K logic elements

Up to 6.3 Mb of embedded memory

■

Up to 360 18 × 18 multipliers for DSP processing intensive applications

Protocol bridging applications for under 1.5 W total power

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Cyclone IV Device Handbook,

Volume 1

May 2013

Feedback Subscribe

1–2

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Features

■

Cyclone IV GX devices offer up to eight high-speed transceivers that provide:

■

Data rates up to 3.125 Gbps

8B/10B encoder/decoder

8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer

(PCS) interface

■

Byte serializer/deserializer (SERDES)

Word aligner

Rate matching FIFO

TX bit slipper for Common Public Radio Interface (CPRI)

Electrical idle

Dynamic channel reconfiguration allowing you to change data rates and

protocols on-the-fly

■

Static equalization and pre-emphasis for superior signal integrity

150 mW per channel power consumption

Flexible clocking structure to support multiple protocols in a single transceiver

block

■

Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)

Gen 1:

■

×1, ×2, and ×4 lane configurations

End-point and root-port configurations

Up to 256-byte payload

One virtual channel

2 KB retry buffer

4 KB receiver (Rx) buffer

■

Cyclone IV GX devices offer a wide range of protocol support:

■

PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)

Gigabit Ethernet (1.25 Gbps)

CPRI (up to 3.072 Gbps)

XAUI (3.125 Gbps)

Triple rate serial digital interface (SDI) (up to 2.97 Gbps)

Serial RapidIO (3.125 Gbps)

Basic mode (up to 3.125 Gbps)

V-by-One (up to 3.0 Gbps)

DisplayPort (2.7 Gbps)

Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)

OBSAI (up to 3.072 Gbps)

Cyclone IV Device Handbook,

Volume 1

May 2013 Altera Corporation

Chapter 1: Cyclone IV FPGA Device Family Overview

1–3

Device Resources

■

Up to 532 user I/Os

■

LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx

Support for DDR2 SDRAM interfaces up to 200 MHz

Support for QDRII SRAM and DDR SDRAM up to 167 MHz

■

Up to eight phase-locked loops (PLLs) per device

Offered in commercial and industrial temperature grades

Device Resources

Table 1–1 lists Cyclone IV E device resources.

Table 1–1. Resources for the Cyclone IV E Device Family

Resources

Logic elements (LEs)

6,272

270

10,320

414

15,408

504

22,320

594

28,848

594

39,600

1,134

55,856

2,340

75,408

2,745

114,480

Embedded memory

(Kbits)

3,888

266

Embedded 18 × 18

multipliers

116

154

200

General-purpose PLLs

Global Clock Networks

User I/O Banks

(1)

Maximum user I/O

179

343

153

532

374

426

528

Note to Table 1–1:

(1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver

pins and dedicated configuration pins are not included in the pin count.

May 2013 Altera Corporation

Cyclone IV Device Handbook,

Volume 1

1–4

Chapter 1: Cyclone IV FPGA Device Family Overview

Device Resources

Table 1–2 lists Cyclone IV GX device resources.

Table 1–2. Resources for the Cyclone IV GX Device Family

Resources

Logic elements (LEs)

14,400

21,280

756

29,440

1,080

29,440

1,080

49,888

2,502

140

73,920

4,158

198

109,424 149,760

Embedded memory (Kbits)

Embedded 18 × 18 multipliers

General purpose PLLs

Multipurpose PLLs

540

5,490

280

6,480

360

(4)

(5)

Global clock networks

(6)

High-speed transceivers

Transceiver maximum data rate

(Gbps)

2.5

3.125

PCIe (PIPE) hard IP blocks

User I/O banks

(7)

(8)

(9)

Maximum user I/O

150

290

310

475

Notes to Table 1–2:

(1) Applicable for the F169 and F324 packages.

(2) Applicable for the F484 package.

(3) Only two multipurpose PLLs for F484 package.

(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the Clock Networks and PLLs in

Cyclone IV Devices chapter.

(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer

to the Clock Networks and PLLs in Cyclone IV Devices chapter.

(6) If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.

(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.

(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.

(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver

pins and dedicated configuration pins are not included in the pin count.

Cyclone IV Device Handbook,

Volume 1

May 2013 Altera Corporation

Package Matrix

Table 1–3 lists Cyclone IV E device package offerings.

(2)

Table 1–3. Package Offerings for the Cyclone IV E Device Family ^(1),

Package

Size (mm)

Pitch (mm)

E144

22 × 22

0.5

M164

8 × 8

0.5

M256

9 x 9

0.5

U256

F256

17 × 17

1.0

F324

19 x 19

1.0

U484

19 × 19

0.8

F484

23 × 23

1.0

F780

29 × 29

1.0

14 × 14

0.8

Device

EP4CE6

EP4CE10

EP4CE15

EP4CE22

EP4CE30

EP4CE40

EP4CE55

EP4CE75

EP4CE115

—

179

—

179

—

179

165

153

—

179

165

153

—

165

—

343

—

137

—

193

—

328

324

292

280

124

132

110

103

532

374

426

528

224

160

178

230

—

328

324

292

—

124

132

110

—

Notes to Table 1–3:

(1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical

connectivity and not for thermal purposes.

(2) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the I/O

Management chapter in volume 2 of the Quartus II Handbook.

(3) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter.

Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts.

Table 1–4. Package Offerings for the Cyclone IV GX Device Family ⁽¹⁾

Package

Size (mm)

Pitch (mm)

N148

11 × 11

0.5

F169

14 × 14

1.0

F324

19 × 19

1.0

F484

23 × 23

1.0

F672

27 × 27

1.0

F896

31 × 31

1.0

Device

EP4CGX15

EP4CGX22

—

150

—

EP4CGX30

290

270

130

120

—

EP4CGX50

—

310

393

140

181

—

EP4CGX75

—

EP4CGX110

EP4CGX150

Note to Table 1–4:

—

475

220

—

(1) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the I/O

Management chapter in volume 2 of the Quartus II Handbook.

(2) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter.

Chapter 1: Cyclone IV FPGA Device Family Overview

1–7

Cyclone IV Device Family Speed Grades

Table 1–5 lists the Cyclone IV GX devices speed grades.

Table 1–5. Speed Grades for the Cyclone IV GX Device Family

Device

EP4CGX15

EP4CGX22

EP4CGX30

EP4CGX50

EP4CGX75

EP4CGX110

EP4CGX150

N148

F169

F324

F484

—

F672

—

F896

—

C7, C8, I7

C6, C7, C8, I7

—

C6, C7, C8, I7

—

C6, C7, C8, I7

C7, C8, I7

—

C6, C7, C8, I7

C7, C8, I7

—

C7, C8, I7

Table 1–6 lists the Cyclone IV E devices speed grades.

Table 1–6. Speed Grades for the Cyclone IV E Device Family ^{(1), (2)}

Device

E144

M164

M256

U256

F256

F324 U484

F484

F780

C8L, C9L, I8L

C6, C7, C8, I7,

C8L, C9L, I8L

I7N C6, C7, C8, I7,

EP4CE6

—

C8L, C9L, I8L

EP4CE10 C6, C7, C8, I7,

C8L, C9L, I8L

I7N C6, C7, C8, I7,

—

C8L, C9L, I8L

I7N C7N, I7N I7N C6, C7, C8, I7,

C8L, C9L, I8L

C6, C7, C8, I7,

C8L, C9L, I8L

EP4CE15

—

C6, C7, C8, I7

C8L, C9L, I8L

EP4CE22 C6, C7, C8, I7,

C8L, C9L, I8L

I7N C6, C7, C8, I7,

—

C8L, C9L, I8L

C6, C7, C8, I7,

C8L, C9L, I8L

C6, C7, C8, I7

EP4CE30

EP4CE40

—

A7N

C8L, C9L, I8L

C6, C7, C8, I7

I7N C6, C7, C8, I7,

C8L, C9L, I8L C8L, C9L, I8L

C6, C7, C8, I7 C6, C7, C8, I7

EP4CE55

EP4CE75

—

I7N

—

C8L, C9L, I8L C8L, C9L, I8L

C6, C7, C8, I7 C6, C7, C8, I7

C8L, C9L, I8L C8L, C9L, I8L

EP4CE115

C7, C8, I7

Notes to Table 1–6:

(1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage.

(2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage.

May 2013 Altera Corporation

Cyclone IV Device Handbook,

Volume 1

1–8

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

This section describes Cyclone IV device architecture and contains the following

topics:

■

“FPGA Core Fabric”

“I/O Features”

“Clock Management”

“External Memory Interfaces”

“Configuration”

“High-Speed Transceivers (Cyclone IV GX Devices Only)”

“Hard IP for PCI Express (Cyclone IV GX Devices Only)”

FPGA Core Fabric

Cyclone IV devices leverage the same core fabric as the very successful Cyclone series

devices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memory

blocks, and multipliers.

Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM

memory. You can configure the M9K blocks as single port, simple dual port, or true

dual port RAM, as well as FIFO buffers or ROM. They can also be configured to

implement any of the data widths in Table 1–7.

Table 1–7. M9K Block Data Widths for Cyclone IV Device Family

Mode

Single port or simple dual port

True dual port

Data Width Configurations

×1, ×2, ×4, ×8/9, ×16/18, and ×32/36

×1, ×2, ×4, ×8/9, and ×16/18

The multiplier architecture in Cyclone IV devices is the same as in the existing

Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or

two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP

including finite impulse response (FIR), fast Fourier transform (FFT), and numerically

controlled oscillator (NCO) functions for use with the multiplier blocks. The

Quartus^®II design software’s DSP Builder tool integrates MathWorks Simulink and

MATLAB design environments for a streamlined DSP design flow.

For more information, refer to the Logic Elements and Logic Array Blocks in Cyclone IV

Devices, Memory Blocks in Cyclone IV Devices, and Embedded Multipliers in Cyclone IV

Devices chapters.

Cyclone IV Device Handbook,

Volume 1

May 2013 Altera Corporation

Chapter 1: Cyclone IV FPGA Device Family Overview

1–9

Cyclone IV Device Family Architecture

I/O Features

Cyclone IV device I/O supports programmable bus hold, programmable pull-up

resistors, programmable delay, programmable drive strength, programmable

slew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices

support calibrated on-chip series termination (Rs OCT) or driver impedance matching

(Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speed

transceiver I/Os are located on the left side of the device. The top, bottom, and right

sides can implement general-purpose user I/Os.

Table 1–8 lists the I/O standards that Cyclone IV devices support.

Table 1–8. I/O Standards Support for the Cyclone IV Device Family

Type

Single-Ended I/O

Differential I/O

I/O Standard

LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X

SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS

The LVDS SERDES is implemented in the core of the device using logic elements.

For more information, refer to the I/O Features in Cyclone IV Devices chapter.

Clock Management

Cyclone IV devices include up to 30 global clock (GCLK) networks and up to eight

PLLs with five outputs per PLL to provide robust clock management and synthesis.

You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the

clock frequency or phase.

Cyclone IV GX devices support two types of PLLs: multipurpose PLLs and general-

purpose PLLs:

■

Use multipurpose PLLs for clocking the transceiver blocks. You can also use them

for general-purpose clocking when they are not used for transceiver clocking.

■

Use general purpose PLLs for general-purpose applications in the fabric and

periphery, such as external memory interfaces. Some of the general purpose PLLs

can support transceiver clocking.

For more information, refer to the Clock Networks and PLLs in Cyclone IV Devices

chapter.

External Memory Interfaces

Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces

on the top, bottom, and right sides of the device. Cyclone IV E devices also support

these interfaces on the left side of the device. Interfaces may span two or more sides of

the device to allow more flexible board design. The Altera^®DDR SDRAM memory

interface solution consists of a PHY interface and a memory controller. Altera supplies

the PHY IP and you can use it in conjunction with your own custom memory

controller or an Altera-provided memory controller. Cyclone IV devices support the

use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces.

May 2013 Altera Corporation

Cyclone IV Device Handbook,

Volume 1

1–10

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

For more information, refer to the External Memory Interfaces in Cyclone IV Devices

chapter.

Configuration

Cyclone IV devices use SRAM cells to store configuration data. Configuration data is

downloaded to the Cyclone IV device each time the device powers up. Low-cost

configuration options include the Altera EPCS family serial flash devices and

commodity parallel flash configuration options. These options provide the flexibility

for general-purpose applications and the ability to meet specific configuration and

wake-up time requirements of the applications.

Table 1–9 lists which configuration schemes are supported by Cyclone IV devices.

Table 1–9. Configuration Schemes for Cyclone IV Device Family

Devices

Cyclone IV GX

Supported Configuration Scheme

(1)

AS, PS, JTAG, and FPP

Cyclone IV E

AS, AP, PS, FPP, and JTAG

Note to Table 1–9:

(1) The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.

IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins

support IEEE 1149.1 (JTAG) for boundary scan testing.

For more information, refer to the JTAG Boundary-Scan Testing for Cyclone IV Devices

chapter.

For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you

must use passive serial (PS) configuration mode for the EP4CGX15/22/30 devices

and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 and

EP4CGX50/75/110/150 devices.

For more information, refer to the Configuration and Remote System Upgrades in

Cyclone IV Devices chapter.

The cyclical redundancy check (CRC) error detection feature during user mode is

supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only

supported for the devices with the core voltage of 1.2 V.

For more information about CRC error detection, refer to the SEU Mitigation in

Cyclone IV Devices chapter.

High-Speed Transceivers (Cyclone IV GX Devices Only)

Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that

can operate independently. These blocks support multiple industry-standard

communication protocols, as well as Basic mode, which you can use to implement

your own proprietary protocols. Each transceiver channel has its own pre-emphasis

and equalization circuitry, which you can set at compile time to optimize signal

integrity and reduce bit error rates. Transceiver blocks also support dynamic

reconfiguration, allowing you to change data rates and protocols on-the-fly.

Cyclone IV Device Handbook,

Volume 1

May 2013 Altera Corporation

Chapter 1: Cyclone IV FPGA Device Family Overview

1–11

Cyclone IV Device Family Architecture

Figure 1–1 shows the structure of the Cyclone IV GX transceiver.

Figure 1–1. Transceiver Channel for the Cyclone IV GX Device

Transmitter Channel PCS

Transceiver Channel

PMA

FPGA

Fabric

TX Phase

Compensation

FIFO

Byte Serializer

8B10B Encoder

Receiver Channel PCS

Receiver Channel

PMA

For more information, refer to the Cyclone IV Transceivers Architecture chapter.

Hard IP for PCI Express (Cyclone IV GX Devices Only)

Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)

in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that

implements the PHY-MAC layer, Data Link Layer, and Transaction Layer

functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point

configurations. This pre-verified hard IP block reduces risk, design time, timing

closure, and verification. You can configure the block with the Quartus II software’s

PCI Express Compiler, which guides you through the process step by step.

For more information, refer to the PCI Express Compiler User Guide.

May 2013 Altera Corporation

Cyclone IV Device Handbook,

Volume 1

1–12

Chapter 1: Cyclone IV FPGA Device Family Overview

Reference and Ordering Information

Figure 1–2 shows the ordering codes for Cyclone IV GX devices.

Figure 1–2. Packaging Ordering Information for the Cyclone IV GX Device

Member Code

PackageType

15 : 14,400 logic elements

22 : 21,280 logic elements

30 : 29,440 logic elements

50 : 49,888 logic elements

75 : 73,920 logic elements

110: 109,424 logic elements

150: 149,760 logic elements

: FineLine BGA (FBGA)

: Quad Flat Pack No Lead (QFN)

OperatingTemperature

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

Family Signature

Optional Suffix

Indicates specific device

options or shipment method

EP4C GX

EP4C: Cyclone IV

Family Variant

Package Code

: Lead-free packaging

ES : Engineering sample

GX : 3-Gbps transceivers

Transceiver Count

FBGA PackageType

14 : 169 pins

19 : 324 pins

23 : 484 pins

27 : 672 pins

31 : 896 pins

Speed Grade

: 2

: 4

: 8

6 (fastest)

QFN PackageType

11 : 148 pins

Figure 1–3 shows the ordering codes for Cyclone IV E devices.

Figure 1–3. Packaging Ordering Information for the Cyclone IV E Device

: Enhanced Thin Quad Flat Pack (EQFP)

: Ultra FineLine BGA (UBGA)

OperatingTemperature

: Commercial temperature (T_J= 0° C to 85° C)

: Industrial temperature (T_J= -40° C to 100° C)

Extended industrial temperature (T_J= -40° C to 125° C)

: Automotive temperature (T_J= -40° C to 125° C)

M : Micro FineLine BGA (MBGA)

Family Variant

: Enhanced logic/memory

Family Signature

Optional Suffix

Indicates specific device

options or shipment method

EP4C

EP4C: Cyclone IV

Package Code

: Lead-free packaging

ES : Engineering sample

Member Code

: 6,272 logic elements

FBGA PackageType

17 : 256 pins

19 : 324 pins

23 : 484 pins

29 : 780 pins

: Low-voltage device

10 : 10,320 logic elements

15 : 15,408 logic elements

22 : 22,320 logic elements

30 : 28,848 logic elements

40 : 39,600 logic elements

55 : 55,856 logic elements

75 : 75,408 logic elements

115: 114,480 logic elements

Speed Grade

6 (fastest)

EQFP PackageType

22 : 144 pins

UBGA PackageType

14 : 256 pins

19 : 484 pins

MBGA PackageType

: 164 pins

: 256 pins

Cyclone IV Device Handbook,

Volume 1

May 2013 Altera Corporation

Chapter 1: Cyclone IV FPGA Device Family Overview

1–13

Document Revision History

Table 1–10 lists the revision history for this chapter.

Table 1–10. Document Revision History

Date

May 2013

Version

Changes

Updated Table 1–3, Table 1–6 and Figure 1–3 to add new device options and

packages.

1.8

Updated Table 1–3, Table 1–6 and Figure 1–3 to add new device options and

packages.

February 2013

October 2012

1.7

1.6

Updated Table 1–3 and Table 1–4.

■ Updated “Cyclone IV Device Family Features” section.

■ Updated Figure 1–2 and Figure 1–3.

■ Updated for the Quartus II software version 10.1 release.

■ Added Cyclone IV E new device package information.

■ Updated Table 1–1, Table 1–2, Table 1–3, Table 1–5, and Table 1–6.

■ Updated Figure 1–3.

November 2011

1.5

December 2010

1.4

■ Minor text edits.

July 2010

1.3

1.2

Updated Table 1–2 to include F484 package information.

■ Updated Table 1–3 and Table 1–6.

March 2010

■ Updated Figure 1–3.

■ Minor text edits.

■ Added Cyclone IV E devices in Table 1–1, Table 1–3, and Table 1–6 for the

Quartus II software version 9.1 SP1 release.

■ Added the “Cyclone IV Device Family Speed Grades” and “Configuration”

sections.

February 2010

1.1

1.0

■ Added Figure 1–3 to include Cyclone IV E Device Packaging Ordering

Information.

■ Updated Table 1–2, Table 1–4, and Table 1–5 for Cyclone IV GX devices.

■ Minor text edits.

November 2009

Initial release.

May 2013 Altera Corporation

Cyclone IV Device Handbook,

Volume 1

1–14

Chapter 1: Cyclone IV FPGA Device Family Overview

Document Revision History

Cyclone IV Device Handbook,

Volume 1

May 2013 Altera Corporation

EP4CGX30CF14C7N [INTEL]

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