EPF10K30ABC356-2N [INTEL]

Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356;


型号：	EPF10K30ABC356-2N
厂家：	INTEL
描述：	Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356
文件：	总143页 (文件大小：1990K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Includes

FLEX 10KA

FLEX 10K

Embedded Programmable

Logic Device Family

March 2001, ver. 4.1

Data Sheet

ꢀ

The industry’s first embedded programmable logic device (PLD)

family, providing System-on-a-Programmable-Chip (SOPC)

integration

Features...

–

Embedded array for implementing megafunctions, such as

efficient memory and specialized logic functions

Logic array for general logic functions

–

ꢀ

High density

–

10,000 to 250,000 typical gates (see Tables 1 and 2)

Up to 40,960 RAM bits; 2,048 bits per embedded array block

(EAB), all of which can be used without reducing logic capacity

System-level features

–

MultiVolt^TMI/ O interface support

5.0-V tolerant input pins in FLEX^®10KA devices

Low power consumption (typical specification less than 0.5 mA

in standby mode for most devices)

–

FLEX 10K and FLEX 10KA devices support peripheral

component interconnect Special Interest Group (PCI SIG) PCI

Local Bus Specification, Revision 2.2

–

FLEX 10KA devices include pull-up clamping diode, selectable

on a pin-by-pin basis for 3.3-V PCI compliance

Select FLEX 10KA devices support 5.0-V PCI buses with eight or

fewer loads

Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming any device logic

Table 1. FLEX 10K Device Features

Feature

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K10A

EPF10K30A

EPF10K50V

Typical gates (logic and RAM) (1)

Maximum system gates

Logic elements (LEs)

10,000

31,000

576

20,000

63,000

1,152

144

30,000

69,000

1,728

216

40,000

93,000

2,304

288

50,000

116,000

2,880

360

Logic array blocks (LABs)

Embedded array blocks (EABs)

Total RAM bits

6,144

150

12,288

189

12,288

246

16,384

189

20,480

310

Maximum user I/O pins

Altera Corporation

A-DS-F10K-04.1

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 2. FLEX 10K Device Features

Feature

EPF10K70

EPF10K100

EPF10K130V

EPF10K250A

EPF10K100A

Typical gates (logic and

70,000

100,000

130,000

250,000

RAM) (1)

Maximum system gates

118,000

3,744

468

158,000

4,992

624

211,000

6,656

832

310,000

12,160

1,520

LEs

LABs

EABs

Total RAM bits

Maximum user I/O pins

18,432

358

24,576

406

32,768

470

40,960

470

Note to tables:

(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum

system gates.

–

Devices are fabricated on advanced processes and operate with

a 3.3-V or 5.0-V supply voltage (see Table 3

In-circuit reconfigurability (ICR) via external configuration

device, intelligent controller, or JTAG port

...and More

Features

ClockLock^TMand ClockBoost^TMoptions for reduced clock

delay/ skew and clock multiplication

–

Built-in low-skew clock distribution trees

100% functional testing of all devices; test vectors or scan chains

are not required

Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices

5.0-V Devices

3.3-V Devices

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K70

EPF10K100

EPF10K10A

EPF10K30A

EPF10K50V

EPF10K100A

EPF10K130V

EPF10K250A

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

ꢀ

Flexible interconnect

–

FastTrack^®Interconnect continuous routing structure for fast,

predictable interconnect delays

–

Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

–

Dedicated cascade chain that implements high-speed,

high-fan-in logic functions (automatically used by software tools

and megafunctions)

–

Tri-state emulation that implements internal tri-state buses

Up to six global clock signals and four global clear signals

ꢀ

Powerful I/ O pins

–

Individual tri-state output enable control for each pin

Open-drain option on each I/ O pin

Programmable output slew-rate control to reduce switching

noise

–

FLEX 10KA devices support hot-socketing

ꢀ

Peripheral register for fast setup and clock-to-output delay

Flexible package options

–

Available in a variety of packages with 84 to 600 pins (see

Tables 4 and 5)

Pin-compatibility with other FLEX 10K devices in the same

package

FineLine BGA^TMpackages maximize board space efficiency

ꢀ

Software design support and automatic place-and-route provided by

Altera development systems for Windows-based PCs and Sun

SPARCstation, HP 9000 Series 700/ 800 workstations

Additional design entry and simulation support provided by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

DesignWare components, Verilog HDL, VHDL, and other interfaces

to popular EDA tools from manufacturers such as Cadence,

Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,

VeriBest, and Viewlogic

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 4. FLEX 10K Package Options & I/O Pin Count Note (1)

Device

84-Pin

PLCC

100-Pin

TQFP

144-Pin TQFP

208-Pin

PQFP

240-Pin

PQFP

RQFP

EPF10K10

102

134

147

EPF10K10A

EPF10K20

189

EPF10K30

EPF10K30A

EPF10K40

102

EPF10K50

EPF10K50V

EPF10K70

EPF10K100

EPF10K100A

EPF10K130V

EPF10K250A

189

Table 5. FLEX 10K Package Options & I/O Pin Count (Continued)

Note (1)

Device

503-Pin 599-Pin

256-Pin

FineLine BGA

356-Pin

BGA

484-Pin

FineLine BGA

600-Pin

BGA

403-Pin

PGA

EPF10K10

EPF10K10A

EPF10K20

EPF10K30

EPF10K30A

EPF10K40

EPF10K50

EPF10K50V

EPF10K70

EPF10K100

EPF10K100A

EPF10K130V

EPF10K250A

150

191

150 (2)

246

369

274

310

358

406

274

406

470

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack

(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),

and FineLine BGA^TMpackages.

(2) This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine

BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin

FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.

Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based

on reconfigurable CMOS SRAM elements, the Flexible Logic Element

General

Description

MatriX (FLEX) architecture incorporates all features necessary to

implement common gate array megafunctions. With up to 250,000 gates,

the FLEX 10K family provides the density, speed, and features to integrate

entire systems, including multiple 32-bit buses, into a single device.

FLEX 10K devices are reconfigurable, which allows 100% testing prior to

shipment. As a result, the designer is not required to generate test vectors

for fault coverage purposes. Additionally, the designer does not need to

manage inventories of different ASIC designs; FLEX 10K devices can be

configured on the board for the specific functionality required.

Table 6 shows FLEX 10K performance for some common designs. All

performance values were obtained with Synopsys DesignWare or LPM

functions. No special design technique was required to implement the

applications; the designer simply inferred or instantiated a function in a

Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or

schematic design file.

Table 6. FLEX 10K & FLEX 10KA Performance

Application

Resources

Used

Performance

Units

LEs EABs

-1 Speed

Grade

-2 Speed

Grade

-3 Speed

Grade

-4 Speed

Grade

16-bit loadable

204

166

125

MHz

counter (1)

16-bit accumulator (1) 16

16-to-1 multiplexer (2) 10

204

4.2

166

5.8

125

6.0

7.0

MHz

256 × 8 RAM read

cycle speed (3)

172

145

108

MHz

256 × 8 RAM write

cycle speed (3)

106

MHz

Notes:

(1) The speed grade of this application is limited because of clock high and low specifications.

(2) This application uses combinatorial inputs and outputs.

(3) This application uses registered inputs and outputs.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The FLEX 10K architecture is similar to that of embedded gate arrays, the

fastest-growing segment of the gate array market. As with standard gate

arrays, embedded gate arrays implement general logic in a conventional

“sea-of-gates” architecture. In addition, embedded gate arrays have

dedicated die areas for implementing large, specialized functions. By

embedding functions in silicon, embedded gate arrays provide reduced

die area and increased speed compared to standard gate arrays. However,

embedded megafunctions typically cannot be customized, limiting the

designer’s options. In contrast, FLEX 10K devices are programmable,

providing the designer with full control over embedded megafunctions

and general logic while facilitating iterative design changes during

debugging.

Each FLEX 10K device contains an embedded array and a logic array. The

embedded array is used to implement a variety of memory functions or

complex logic functions, such as digital signal processing (DSP),

microcontroller, wide-data-path manipulation, and data-transformation

functions. The logic array performs the same function as the sea-of-gates

in the gate array: it is used to implement general logic, such as counters,

adders, state machines, and multiplexers. The combination of embedded

and logic arrays provides the high performance and high density of

embedded gate arrays, enabling designers to implement an entire system

on a single device.

FLEX 10K devices are configured at system power-up with data stored in

an Altera serial configuration device or provided by a system controller.

Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices,

which configure FLEX 10K devices via a serial data stream. Configuration

data can also be downloaded from system RAM or from Altera’s

BitBlaster^TMserial download cable or ByteBlasterMV^TMparallel port

download cable. After a FLEX 10K device has been configured, it can be

reconfigured in-circuit by resetting the device and loading new data.

Because reconfiguration requires less than 320 ms, real-time changes can

be made during system operation.

FLEX 10K devices contain an optimized interface that permits

microprocessors to configure FLEX 10K devices serially or in parallel, and

synchronously or asynchronously. The interface also enables

microprocessors to treat a FLEX 10K device as memory and configure the

device by writing to a virtual memory location, making it very easy for the

designer to reconfigure the device.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For more information, see the following documents:

ꢀ

Configuration Devices for APEX & FLEX Devices Data Sheet

BitBlaster Serial Download Cable Data Sheet

ByteBlasterMV Parallel Port Download Cable Data Sheet

Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000

Devices)

FLEX 10K devices are supported by Altera development systems; single,

integrated packages that offer schematic, text (including AHDL), and

waveform design entry, compilation and logic synthesis, full simulation

and worst-case timing analysis, and device configuration. The Altera

software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and

other interfaces for additional design entry and simulation support from

other industry-standard PC- and UNIX workstation-based EDA tools.

The Altera software works easily with common gate array EDA tools for

synthesis and simulation. For example, the Altera software can generate

Verilog HDL files for simulation with tools such as Cadence Verilog-XL.

Additionally, the Altera software contains EDA libraries that use device-

specific features such as carry chains which are used for fast counter and

arithmetic functions. For instance, the Synopsys Design Compiler library

supplied with the Altera development systems include DesignWare

functions that are optimized for the FLEX 10K architecture.

The Altera development systems run on Windows-based PCs and Sun

SPARCstation, and HP 9000 Series 700/ 800 workstations.

See the MAX+PLUS II Programmable Logic Development System & Software

Data Sheet for more information.

Functional

Each FLEX 10K device contains an embedded array to implement

memory and specialized logic functions, and a logic array to implement

general logic.

Description

The embedded array consists of a series of EABs. When implementing

memory functions, each EAB provides 2,048 bits, which can be used to

create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.

When implementing logic, each EAB can contribute 100 to 600 gates

towards complex logic functions, such as multipliers, microcontrollers,

state machines, and DSP functions. EABs can be used independently, or

multiple EABs can be combined to implement larger functions.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The logic array consists of logic array blocks (LABs). Each LAB contains

eight LEs and a local interconnect. An LE consists of a 4-input look-up

table (LUT), a programmable flipflop, and dedicated signal paths for carry

and cascade functions. The eight LEs can be used to create medium-sized

blocks of logic—8-bit counters, address decoders, or state machines—or

combined across LABs to create larger logic blocks. Each LAB represents

about 96 usable gates of logic.

Signal interconnections within FLEX 10K devices and to and from device

pins are provided by the FastTrack Interconnect, a series of fast,

continuous row and column channels that run the entire length and width

of the device.

Each I/ O pin is fed by an I/ O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bidirectional I/ O buffer and a flipflop that can be used as either an output

or input register to feed input, output, or bidirectional signals. When used

with a dedicated clock pin, these registers provide exceptional

performance. As inputs, they provide setup times as low as 1.6 ns and

hold times of 0 ns; as outputs, these registers provide clock-to-output

times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG

BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Figure 1 shows a block diagram of the FLEX 10K architecture. Each group

of LEs is combined into an LAB; LABs are arranged into rows and

columns. Each row also contains a single EAB. The LABs and EABs are

interconnected by the FastTrack Interconnect. IOEs are located at the end

of each row and column of the FastTrack Interconnect.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 1. FLEX 10K Device Block Diagram

Embedded Array Block (EAB)

IOE IOE IOE IOE

I/O Element

(IOE)

IOE

IOE IOE

IOE

Column

Interconnect

Logic Array

EAB

Logic Array

Block (LAB)

IOE

Logic Element (LE)

Row

Interconnect

EAB

Local Interconnect

Logic

Array

IOE

IOE IOE

IOE

Embedded Array

FLEX 10K devices provide six dedicated inputs that drive the flipflops’

control inputs to ensure the efficient distribution of high-speed, low-skew

(less than 1.5 ns) control signals. These signals use dedicated routing

channels that provide shorter delays and lower skews than the FastTrack

Interconnect. Four of the dedicated inputs drive four global signals. These

four global signals can also be driven by internal logic, providing an ideal

solution for a clock divider or an internally generated asynchronous clear

signal that clears many registers in the device.

Embedded Array Block

The EAB is a flexible block of RAM with registers on the input and output

ports, and is used to implement common gate array megafunctions. The

EAB is also suitable for functions such as multipliers, vector scalars, and

error correction circuits, because it is large and flexible. These functions

can be combined in applications such as digital filters and

microcontrollers.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Logic functions are implemented by programming the EAB with a read-

only pattern during configuration, creating a large LUT. With LUTs,

combinatorial functions are implemented by looking up the results, rather

than by computing them. This implementation of combinatorial functions

can be faster than using algorithms implemented in general logic, a

performance advantage that is further enhanced by the fast access times

of EABs. The large capacity of EABs enables designers to implement

complex functions in one logic level without the routing delays associated

with linked LEs or field-programmable gate array (FPGA) RAM blocks.

For example, a single EAB can implement a 4 × 4 multiplier with eight

inputs and eight outputs. Parameterized functions such as LPM functions

can automatically take advantage of the EAB.

The EAB provides advantages over FPGAs, which implement on-board

RAM as arrays of small, distributed RAM blocks. These FPGA RAM

blocks contain delays that are less predictable as the size of the RAM

increases. In addition, FPGA RAM blocks are prone to routing problems

because small blocks of RAM must be connected together to make larger

blocks. In contrast, EABs can be used to implement large, dedicated

blocks of RAM that eliminate these timing and routing concerns.

EABs can be used to implement synchronous RAM, which is easier to use

than asynchronous RAM. A circuit using asynchronous RAM must

generate the RAM write enable (WE) signal, while ensuring that its data

and address signals meet setup and hold time specifications relative to the

WEsignal. In contrast, the EAB’s synchronous RAM generates its own WE

signal and is self-timed with respect to the global clock. A circuit using the

EAB’s self-timed RAM need only meet the setup and hold time

specifications of the global clock.

When used as RAM, each EAB can be configured in any of the following

sizes: 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1. See Figure 2.

Figure 2. EAB Memory Conﬁgurations

2,048 × 1

256 × 8

512 × 4

1,024 × 2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Larger blocks of RAM are created by combining multiple EABs. For

example, two 256 × 8 RAM blocks can be combined to form a

256 × 16 RAM block; two 512 × 4 blocks of RAM can be combined to form

a 512 × 8 RAM block. See Figure 3.

Figure 3. Examples of Combining EABs

256 × 16

512 × 8

256 × 8

512 × 4

256 × 8

512 × 4

If necessary, all EABs in a device can be cascaded to form a single RAM

block. EABs can be cascaded to form RAM blocks of up to 2,048 words

without impacting timing. Altera’s software automatically combines

EABs to meet a designer’s RAM specifications.

EABs provide flexible options for driving and controlling clock signals.

Different clocks can be used for the EAB inputs and outputs. Registers can

be independently inserted on the data input, EAB output, or the address

and WEinputs. The global signals and the EAB local interconnect can drive

the WEsignal. The global signals, dedicated clock pins, and EAB local

interconnect can drive the EAB clock signals. Because the LEs drive the

EAB local interconnect, the LEs can control the WEsignal or the EAB clock

signals.

Each EAB is fed by a row interconnect and can drive out to row and

column interconnects. Each EAB output can drive up to two row channels

and up to two column channels; the unused row channel can be driven by

other LEs. This feature increases the routing resources available for EAB

outputs. See Figure 4.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 4. FLEX 10K Embedded Array Block

Chip-Wide

Reset

Dedicated Inputs &

Global Signals

Row Interconnect

(1)

2, 4, 8, 16

Data

Out

8, 4, 2, 1

2, 4, 8, 16

Address

8, 9, 10, 11

RAM/ROM

256 × 8

512 × 4

1,024 × 2

2,048 × 1

Column

Interconnect

EAB Local Interconnect (1)

Note:

(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have

22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices

have 26.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Logic Array Block

Each LAB consists of eight LEs, their associated carry and cascade chains,

LAB control signals, and the LAB local interconnect. The LAB provides

the coarse-grained structure to the FLEX 10K architecture, facilitating

efficient routing with optimum device utilization and high performance.

See Figure 5.

Figure 5. FLEX 10K LAB

Dedicated Inputs &

Global Signals

Row Interconnect

(1)

LAB Local

Interconnect (2)

See Figure 11

for details.

Carry-In &

Cascade-In

LAB Control

Signals

Column-to-Row

Interconnect

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

Column

Interconnect

Carry-Out &

Cascade-Out

Notes:

(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have

22 inputs to the LAB local interconnect channel from the row; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V,

and EPF10K250A devices have 26.

(2) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have

30 LAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices

have 34 LABs.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each LAB provides four control signals with programmable inversion

that can be used in all eight LEs. Two of these signals can be used as

clocks; the other two can be used for clear/ preset control. The LAB clocks

can be driven by the dedicated clock input pins, global signals, I/ O

signals, or internal signals via the LAB local interconnect. The LAB preset

and clear control signals can be driven by the global signals, I/ O signals,

or internal signals via the LAB local interconnect. The global control

signals are typically used for global clock, clear, or preset signals because

they provide asynchronous control with very low skew across the device.

If logic is required on a control signal, it can be generated in one or more

LEs in any LAB and driven into the local interconnect of the target LAB.

In addition, the global control signals can be generated from LE outputs.

Logic Element

The LE, the smallest unit of logic in the FLEX 10K architecture, has a

compact size that provides efficient logic utilization. Each LE contains a

four-input LUT, which is a function generator that can quickly compute

any function of four variables. In addition, each LE contains a

programmable flipflop with a synchronous enable, a carry chain, and a

cascade chain. Each LE drives both the local and the FastTrack

Interconnect. See Figure 6.

Figure 6. FLEX 10K Logic Element

Carry-In

Cascade-In

Programmable

data1

data2

data3

data4

Look-Up

Table

(LUT)

To FastTrack

Interconnect

Carry

Chain

Cascade

Chain

PRN

ENA

CLRN

To LAB Local

Interconnect

labctrl1

labctrl2

Clear/

Preset

Logic

Chip-Wide

Reset

Clock

Select

labctrl3

labctrl4

Carry-Out Cascade-Out

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The programmable flipflop in the LE can be configured for D, T, JK, or SR

operation. The clock, clear, and preset control signals on the flipflop can

be driven by global signals, general-purpose I/ O pins, or any internal

logic. For combinatorial functions, the flipflop is bypassed and the output

of the LUT drives the output of the LE.

The LE has two outputs that drive the interconnect; one drives the local

interconnect and the other drives either the row or column FastTrack

Interconnect. The two outputs can be controlled independently. For

example, the LUT can drive one output while the register drives the other

output. This feature, called register packing, can improve LE utilization

because the register and the LUT can be used for unrelated functions.

The FLEX 10K architecture provides two types of dedicated high-speed

data paths that connect adjacent LEs without using local interconnect

paths: carry chains and cascade chains. The carry chain supports high-

speed counters and adders; the cascade chain implements wide-input

functions with minimum delay. Carry and cascade chains connect all LEs

in an LAB and all LABs in the same row. Intensive use of carry and

cascade chains can reduce routing flexibility. Therefore, the use of these

chains should be limited to speed-critical portions of a design.

Carry Chain

The carry chain provides a very fast (as low as 0.2 ns) carry-forward

function between LEs. The carry-in signal from a lower-order bit drives

forward into the higher-order bit via the carry chain, and feeds into both

the LUT and the next portion of the carry chain. This feature allows the

FLEX 10K architecture to implement high-speed counters, adders, and

comparators of arbitrary width efficiently. Carry chain logic can be

created automatically by the Compiler during design processing, or

manually by the designer during design entry. Parameterized functions

such as LPM and DesignWare functions automatically take advantage of

carry chains.

Carry chains longer than eight LEs are automatically implemented by

linking LABs together. For enhanced fitting, a long carry chain skips

alternate LABs in a row. A carry chain longer than one LAB skips either

from even-numbered LAB to even-numbered LAB, or from odd-

numbered LAB to odd-numbered LAB. For example, the last LE of the

first LAB in a row carries to the first LE of the third LAB in the row. The

carry chain does not cross the EAB at the middle of the row. For instance,

in the EPF10K50 device, the carry chain stops at the eighteenth LAB and a

new one begins at the nineteenth LAB.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 7 shows how an n-bit full adder can be implemented in n + 1 LEs

with the carry chain. One portion of the LUT generates the sum of two bits

using the input signals and the carry-in signal; the sum is routed to the

output of the LE. The register can either be bypassed for simple adders or

be used for an accumulator function. The carry chain logic generates the

carry-out signal, which is routed directly to the carry-in signal of the next-

higher-order bit. The final carry-out signal is routed to an LE, where it can

be used as a general-purpose signal.

Figure 7. Carry Chain Operation (n-bit Full Adder)

Carry-In

LUT

Carry Chain

LE1

LUT

Carry Chain

LE2

LUT

Carry Chain

LEn

Carry-Out

LUT

Carry Chain

LEn + 1

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Cascade Chain

With the cascade chain, the FLEX 10K architecture can implement

functions that have a very wide fan-in. Adjacent LUTs can be used to

compute portions of the function in parallel; the cascade chain serially

connects the intermediate values. The cascade chain can use a logical AND

or logical OR(via De Morgan’s inversion) to connect the outputs of

adjacent LEs. Each additional LE provides four more inputs to the

effective width of a function, with a delay as low as 0.7 ns per LE. Cascade

chain logic can be created automatically by the Compiler during design

processing, or manually by the designer during design entry.

Cascade chains longer than eight bits are implemented automatically by

linking several LABs together. For easier routing, a long cascade chain

skips every other LAB in a row. A cascade chain longer than one LAB

skips either from even-numbered LAB to even-numbered LAB, or from

odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first

LAB in a row cascades to the first LE of the third LAB). The cascade chain

does not cross the center of the row (e.g., in the EPF10K50 device, the

cascade chain stops at the eighteenth LAB and a new one begins at the

nineteenth LAB). This break is due to the EAB’s placement in the middle

of the row.

Figure 8 shows how the cascade function can connect adjacent LEs to form

functions with a wide fan-in. These examples show functions of 4n

variables implemented with n LEs. The LE delay is as low as 1.6 ns; the

cascade chain delay is as low as 0.7 ns. With the cascade chain, 3.7 ns is

needed to decode a 16-bit address.

Figure 8. Cascade Chain Operation

AND Cascade Chain

OR Cascade Chain

d[3..0]

LUT

LE1

LE2

LE1

LE2

d[7..4]

d[(4n-1)..(4n-4)]

LUT

LEn

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

LE Operating Modes

The FLEX 10K LE can operate in the following four modes:

ꢀ

Normal mode

Arithmetic mode

ꢀ

Up/ down counter mode

Clearable counter mode

Each of these modes uses LE resources differently. In each mode, seven

available inputs to the LE—the four data inputs from the LAB local

interconnect, the feedback from the programmable register, and the

carry-in and cascade-in from the previous LE—are directed to different

destinations to implement the desired logic function. Three inputs to the

LE provide clock, clear, and preset control for the register. The Altera

software, in conjunction with parameterized functions such as LPM and

DesignWare functions, automatically chooses the appropriate mode for

common functions such as counters, adders, and multipliers. If required,

the designer can also create special-purpose functions which use a specific

LE operating mode for optimal performance.

The architecture provides a synchronous clock enable to the register in all

four modes. The Altera software can set DATA1to enable the register

synchronously, providing easy implementation of fully synchronous

designs.

Figure 9 shows the LE operating modes.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 9. FLEX 10K LE Operating Modes

Normal Mode

Cascade-In (1)

Carry-In

LE-Out to FastTrack

Interconnect

data1

data2

PRN

4-Input

LUT

data3

LE-Out to Local

Interconnect

ENA

CLRN

data4

Cascade-Out

Arithmetic Mode

Carry-In

Cascade-In

LE-Out

PRN

data1

data2

3-Input

LUT

ENA

CLRN

3-Input

LUT

Cascade-Out

Carry-Out

Up/Down Counter Mode

Cascade-In

Carry-In

data1 (ena)

data2 (u/d)

PRN

3-Input

LUT

LE-Out

data3 (data)

ENA

CLRN

3-Input

LUT

data4 (nload)

Carry-Out

Cascade-Out

Clearable Counter Mode

Carry-In

data1 (ena)

data2 (nclr)

PRN

3-Input

LUT

LE-Out

data3 (data)

ENA

CLRN

3-Input

LUT

Carry-Out

Cascade-Out

data4 (nload)

Note:

(1) Packed registers cannot be used with the cascade chain.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Normal Mode

The normal mode is suitable for general logic applications and wide

decoding functions that can take advantage of a cascade chain. In normal

mode, four data inputs from the LAB local interconnect and the carry-in

are inputs to a four-input LUT. The Compiler automatically selects the

carry-in or the DATA3signal as one of the inputs to the LUT. The LUT

output can be combined with the cascade-in signal to form a cascade chain

through the cascade-out signal. Either the register or the LUT can be used

to drive both the local interconnect and the FastTrack Interconnect at the

same time.

The LUT and the register in the LE can be used independently; this feature

is known as register packing. To support register packing, the LE has two

outputs; one drives the local interconnect and the other drives the

FastTrack Interconnect. The DATA4signal can drive the register directly,

allowing the LUT to compute a function that is independent of the

registered signal; a three-input function can be computed in the LUT, and

a fourth independent signal can be registered. Alternatively, a four-input

function can be generated, and one of the inputs to this function can be

used to drive the register. The register in a packed LE can still use the

clock enable, clear, and preset signals in the LE. In a packed LE, the

local interconnect, or vice versa.

Arithmetic Mode

The arithmetic mode offers 2 three-input LUTs that are ideal for

implementing adders, accumulators, and comparators. One LUT

computes a three-input function, and the other generates a carry output.

As shown in Figure 9 on page 19, the first LUT uses the carry-in signal and

two data inputs from the LAB local interconnect to generate a

combinatorial or registered output. For example, in an adder, this output

is the sum of three signals: a, b, and carry-in. The second LUT uses the

same three signals to generate a carry-out signal, thereby creating a carry

chain. The arithmetic mode also supports simultaneous use of the cascade

chain.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Up/Down Counter Mode

The up/ down counter mode offers counter enable, clock enable,

synchronous up/ down control, and data loading options. These control

signals are generated by the data inputs from the LAB local interconnect,

the carry-in signal, and output feedback from the programmable register.

The Up/ down counter mode uses 2 three-input LUTs: one generates the

counter data, and the other generates the fast carry bit. A 2-to-1

multiplexer provides synchronous loading. Data can also be loaded

asynchronously with the clear and preset register control signals, without

using the LUT resources.

Clearable Counter Mode

The clearable counter mode is similar to the up/ down counter mode, but

supports a synchronous clear instead of the up/ down control. The clear

function is substituted for the cascade-in signal in the up/ down counter

mode. Clearable counter mode uses 2 three-input LUTs: one generates the

counter data, and the other generates the fast carry bit. Synchronous

loading is provided by a 2-to-1 multiplexer. The output of this multiplexer

is ANDed with a synchronous clear signal.

Internal Tri-State Emulation

Internal tri-state emulation provides internal tri-stating without the

limitations of a physical tri-state bus. In a physical tri-state bus, the

tri-state buffers’ output enable (OE) signals select which signal drives the

bus. However, if multiple OEsignals are active, contending signals can be

driven onto the bus. Conversely, if no OEsignals are active, the bus will

float. Internal tri-state emulation resolves contending tri-state buffers to a

low value and floating buses to a high value, thereby eliminating these

problems. The Altera software automatically implements tri-state bus

functionality with a multiplexer.

Clear & Preset Logic Control

Logic for the programmable register’s clear and preset functions is

controlled by the DATA3, LABCTRL1, and LABCTRL2inputs to the LE. The

clear and preset control structure of the LE asynchronously loads signals

into a register. Either LABCTRL1or LABCTRL2can control the

asynchronous clear. Alternatively, the register can be set up so that

LABCTRL1implements an asynchronous load. The data to be loaded is

driven to DATA3; when LABCTRL1is asserted, DATA3is loaded into the

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

During compilation, the Compiler automatically selects the best control

signal implementation. Because the clear and preset functions are active-

low, the Compiler automatically assigns a logic high to an unused clear or

preset.

The clear and preset logic is implemented in one of the following six

modes chosen during design entry:

ꢀ

Asynchronous clear

Asynchronous preset

Asynchronous clear and preset

Asynchronous load with clear

Asynchronous load with preset

Asynchronous load without clear or preset

In addition to the six clear and preset modes, FLEX 10K devices provide a

chip-wide reset pin that can reset all registers in the device. Use of this

feature is set during design entry. In any of the clear and preset modes, the

chip-wide reset overrides all other signals. Registers with asynchronous

presets may be preset when the chip-wide reset is asserted. Inversion can

be used to implement the asynchronous preset. Figure 10 shows examples

of how to enter a section of a design for the desired functionality.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 10. LE Clear & Preset Modes

Asynchronous Clear

Asynchronous Preset

Asynchronous Clear & Preset

labctrl1

VCC

Chip-Wide Reset

labctrl1 or

PRN

labctrl2

PRN

CLRN

labctrl1 or

labctrl2

Chip-Wide Reset

CLRN

Chip-Wide Reset

VCC

Asynchronous Load without Clear or Preset

Asynchronous Load with Clear

NOT

labctrl1

(Asynchronous

Load)

labctrl1

(Asynchronous

Load)

PRN

data3

(Data)

data3

(Data)

NOT

CLRN

labctrl2

(Clear)

NOT

Chip-Wide Reset

Chip-WideReset

Asynchronous Load with Preset

NOT

labctrl1

(Asynchronous

Load)

labctrl2

(Preset)

PRN

data3

(Data)

CLRN

NOT

Chip-Wide Reset

Asynchronous Clear

The flipflop can be cleared by either LABCTRL1or LABCTRL2. In this mode,

the preset signal is tied to V to deactivate it.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Asynchronous Preset

An asynchronous preset is implemented as either an asynchronous load,

or with an asynchronous clear. If DATA3is tied to V , asserting LABCTRL1

asynchronously loads a one into the register. Alternatively, the Altera

software can provide preset control by using the clear and inverting the

input and output of the register. Inversion control is available for the

inputs to both LEs and IOEs. Therefore, if a register is preset by only one

of the two LABCTRLsignals, the DATA3input is not needed and can be used

for one of the LE operating modes.

Asynchronous Preset & Clear

When implementing asynchronous clear and preset, LABCTRL1controls

the preset and LABCTRL2controls the clear. DATA3is tied to V , therefore,

asserting LABCTRL1asynchronously loads a one into the register,

effectively presetting the register. Asserting LABCTRL2clears the register.

Asynchronous Load with Clear

When implementing an asynchronous load in conjunction with the clear,

LABCTRL1implements the asynchronous load of DATA3by controlling the

the register clear; LABCTRL2does not have to feed the preset circuits.

Asynchronous Load with Preset

When implementing an asynchronous load in conjunction with preset, the

Altera software provides preset control by using the clear and inverting

the input and output of the register. Asserting LABCTRL2presets the

inverts the signal that drives DATA3to account for the inversion of the

Asynchronous Load without Preset or Clear

When implementing an asynchronous load without preset or clear,

LABCTRL1implements the asynchronous load of DATA3by controlling the

FastTrack Interconnect

In the FLEX 10K architecture, connections between LEs and device I/ O

pins are provided by the FastTrack Interconnect, which is a series of

continuous horizontal and vertical routing channels that traverse the

device. This global routing structure provides predictable performance,

even in complex designs. In contrast, the segmented routing in FPGAs

requires switch matrices to connect a variable number of routing paths,

increasing the delays between logic resources and reducing performance.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The FastTrack Interconnect consists of row and column interconnect

channels that span the entire device. Each row of LABs is served by a

dedicated row interconnect. The row interconnect can drive I/ O pins and

feed other LABs in the device. The column interconnect routes signals

between rows and can drive I/ O pins.

A row channel can be driven by an LE or by one of three column channels.

These four signals feed dual 4-to-1 multiplexers that connect to two

specific row channels. These multiplexers, which are connected to each

LE, allow column channels to drive row channels even when all eight LEs

in an LAB drive the row interconnect.

Each column of LABs is served by a dedicated column interconnect. The

column interconnect can then drive I/ O pins or another row’s

interconnect to route the signals to other LABs in the device. A signal from

the column interconnect, which can be either the output of an LE or an

input from an I/ O pin, must be routed to the row interconnect before it

can enter an LAB or EAB. Each row channel that is driven by an IOE or

EAB can drive one specific column channel.

Access to row and column channels can be switched between LEs in

adjacent pairs of LABs. For example, an LE in one LAB can drive the row

and column channels normally driven by a particular LE in the adjacent

LAB in the same row, and vice versa. This routing flexibility enables

routing resources to be used more efficiently. See Figure 11.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 11. LAB Connections to Row & Column Interconnect

Column

Channels

To Other

Columns

Row Channels

At each intersection,

four row channels can

drive column channels.

Each LE can drive two

row channels.

From Adjacent LAB

To Adjacent LAB

LE 1

Each LE can switch

interconnect access

with an LE in the

LE 2

adjacent LAB.

LE 8

To LAB Local

Interconnect

To Other Rows

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For improved routing, the row interconnect is comprised of a combination

of full-length and half-length channels. The full-length channels connect

to all LABs in a row; the half-length channels connect to the LABs in half

of the row. The EAB can be driven by the half-length channels in the left

half of the row and by the full-length channels. The EAB drives out to the

full-length channels. In addition to providing a predictable, row-wide

interconnect, this architecture provides increased routing resources. Two

neighboring LABs can be connected using a half-row channel, thereby

saving the other half of the channel for the other half of the row.

Table 7 summarizes the FastTrack Interconnect resources available in

each FLEX 10K device.

Table 7. FLEX 10K FastTrack Interconnect Resources

Device

Rows

Channels per

Row

Columns

Channels per

Column

EPF10K10

144

EPF10K10A

EPF10K20

144

216

EPF10K30

EPF10K30A

EPF10K40

216

EPF10K50

EPF10K50V

EPF10K70

312

EPF10K100

EPF10K100A

EPF10K130V

EPF10K250A

312

456

In addition to general-purpose I/ O pins, FLEX 10K devices have six

dedicated input pins that provide low-skew signal distribution across the

device. These six inputs can be used for global clock, clear, preset, and

peripheral output enable and clock enable control signals. These signals

are available as control signals for all LABs and IOEs in the device.

The dedicated inputs can also be used as general-purpose data inputs

because they can feed the local interconnect of each LAB in the device.

However, the use of dedicated inputs as data inputs can introduce

additional delay into the control signal network.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 12 shows the interconnection of adjacent LABs and EABs with

row, column, and local interconnects, as well as the associated cascade

and carry chains. Each LAB is labeled according to its location: a letter

represents the row and a number represents the column. For example,

LAB B3 is in row B, column 3.

Figure 12. Interconnect Resources

See Figure 15

for details.

I/O Element (IOE)

IOE

Row

Interconnect

LAB

See Figure 14

for details.

Column

Interconnect

To LAB A5

To LAB A4

IOE

LAB

Cascade &

Carry Chains

To LAB B5

To LAB B4

IOE

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

I/O Element

An I/ O element (IOE) contains a bidirectional I/ O buffer and a register

that can be used either as an input register for external data that requires

a fast setup time, or as an output register for data that requires fast clock-

to-output performance. In some cases, using an LE register for an input

can be used as input, output, or bidirectional pins. For bidirectional

registered I/ O implementation, the output register should be in the IOE

and, the data input and output enable register should be LE registers

placed adjacent to the bidirectional pin. The Compiler uses the

programmable inversion option to invert signals from the row and

column interconnect automatically where appropriate. Figure 13 shows

the bidirectional I/ O registers.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 13. Bidirectional I/O Registers

Row and Column

Interconnect

2 Dedicated

Clock Inputs

Peripheral

4 Dedicated

Control Bus

Inputs

OE Register

ENA

VCC

CLRN

Chip-Wide

Reset

VCC

Chip-Wide

Output Enable

OE[7..0]

VCC

Output Register

CLK[1..0]

CLK[3..2]

ENA

CLRN

Open-Drain

Output

VCC

ENA[5..0]

Slew-Rate

Control

VCC

CLRN[1..0]

Chip-Wide

Reset

Input Register

VCC

ENA

CLRN

Chip-Wide

Reset

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each IOE selects the clock, clear, clock enable, and output enable controls

from a network of I/ O control signals called the peripheral control bus.

The peripheral control bus uses high-speed drivers to minimize signal

skew across devices; it provides up to 12 peripheral control signals that

can be allocated as follows:

ꢀ

Up to eight output enable signals

Up to six clock enable signals

Up to two clock signals

Up to two clear signals

If more than six clock enable or eight output enable signals are required,

each IOE on the device can be controlled by clock enable and output

enable signals driven by specific LEs. In addition to the two clock signals

available on the peripheral control bus, each IOE can use one of two

dedicated clock pins. Each peripheral control signal can be driven by any

of the dedicated input pins or the first LE of each LAB in a particular row.

In addition, an LE in a different row can drive a column interconnect,

which causes a row interconnect to drive the peripheral control signal.

The chip-wide reset signal will reset all IOE registers, overriding any

other control signals.

Tables 8 and 9 list the sources for each peripheral control signal, and the

rows that can drive global signals. These tables also show how the output

enable, clock enable, clock, and clear signals share 12 peripheral control

signals.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 8. EPF10K10, EPF10K20, EPF10K30, EPF10K40 & EPF10K50 Peripheral Bus Sources

Peripheral

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

Control Signal

EPF10K10A

EPF10K30A

EPF10K50V

OE0

OE1

OE2

OE3

OE4

OE5

Row A

Row B

Row C

Row A

Row B

Row C

Row A

Row B

Row C

Row D

Row E

Row F

Row A

Row B

Row C

Row D

Row E

Row F

Row A

Row B

Row C

Row D

Row E

Row F

Row A

Row B

Row C

Row D

Row E

Row F

Row A

Row C

Row D

Row E

Row F

Row G

Row B

Row C

Row D

Row E

Row F

Row H

Row A

Row B

Row D

Row F

Row H

Row J

Row A

Row C

Row E

Row G

Row I

CLKENA0/CLK0/GLOBAL0

CLKENA1/OE6/GLOBAL1

CLKENA2/CLR0

CLKENA3/OE7/GLOBAL2

CLKENA4/CLR1

CLKENA5/CLK1/GLOBAL3

Row J

Table 9. EPF10K70, EPF10K100, EPF10K130V & EPF10K250A Peripheral Bus Sources

Peripheral

EPF10K70

EPF10K100

EPF10K130V

EPF10K250A

Control Signal

EPF10K100A

OE0

OE1

OE2

OE3

OE4

OE5

Row A

Row B

Row D

Row I

Row A

Row C

Row E

Row L

Row I

Row C

Row E

Row G

Row N

Row K

Row M

Row H

Row F

Row D

Row J

Row L

Row I

Row E

Row G

Row I

Row P

Row M

Row O

Row J

Row H

Row F

Row L

Row N

Row K

Row G

Row H

Row E

Row C

Row B

Row F

Row H

Row E

Row K

Row F

Row D

Row B

Row H

Row J

Row G

CLKENA0/CLK0/GLOBAL0

CLKENA1/OE6/GLOBAL1

CLKENA2/CLR0

CLKENA3/OE7/GLOBAL2

CLKENA4/CLR1

CLKENA5/CLK1/GLOBAL3

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Signals on the peripheral control bus can also drive the four global signals,

referred to as GLOBAL0through GLOBAL3in Tables 8 and 9. The internally

generated signal can drive the global signal, providing the same

low-skew, low-delay characteristics for an internally generated signal as

for a signal driven by an input. This feature is ideal for internally

generated clear or clock signals with high fan-out. When a global signal is

driven by internal logic, the dedicated input pin that drives that global

signal cannot be used. The dedicated input pin should be driven to a

known logic state (such as ground) and not be allowed to float.

When the chip-wide output enable pin is held low, it will tri-state all pins

on the device. This option can be set in the Global Project Device Options

menu. Additionally, the registers in the IOE can be reset by holding the

chip-wide reset pin low.

Row-to-IOE Connections

When an IOE is used as an input signal, it can drive two separate row

channels. The signal is accessible by all LEs within that row. When an IOE

is used as an output, the signal is driven by a multiplexer that selects a

signal from the row channels. Up to eight IOEs connect to each side of

each row channel. See Figure 14.

Figure 14. FLEX 10K Row-to-IOE Connections

The values for m and n are provided in Table 10.

IOE1

Row FastTrack

Interconnect

IOE8

Each IOE is driven by an

m-to-1 multiplexer.

Each IOE can drive up to two

row channels.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 10 lists the FLEX 10K row-to-IOE interconnect resources.

Table 10. FLEX 10K Row-to-IOE Interconnect Resources

Device

Channels per Row (n)

Row Channels per Pin (m)

EPF10K10

144

EPF10K10A

EPF10K20

144

216

EPF10K30

EPF10K30A

EPF10K40

216

EPF10K50

EPF10K50V

EPF10K70

312

EPF10K100

EPF10K100A

EPF10K130V

EPF10K250A

312

456

Column-to-IOE Connections

When an IOE is used as an input, it can drive up to two separate column

channels. When an IOE is used as an output, the signal is driven by a

multiplexer that selects a signal from the column channels. Two IOEs

connect to each side of the column channels. Each IOE can be driven by

column channels via a multiplexer. The set of column channels that each

IOE can access is different for each IOE. See Figure 15.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 15. FLEX 10K Column-to-IOE Connections

The values for m and n are provided in Table 11.

Each IOE is driven by

an m-to-1 multiplexer.

IOE1

Column

Interconnect

IOE1

Each IOE can drive up to

two column channels.

Table 11 lists the FLEX 10K column-to-IOE interconnect resources.

Table 11. FLEX 10K Column-to-IOE Interconnect Resources

Device

Channels per Column (n) Column Channel per Pin (m)

EPF10K10

EPF10K10A

EPF10K20

EPF10K30

EPF10K30A

EPF10K40

EPF10K50

EPF10K50V

EPF10K70

EPF10K100

EPF10K100A

EPF10K130V

EPF10K250A

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

FLEX 10KE devices support the SameFrame pin-out feature for

SameFrame

Pin-Outs

FineLine BGA packages. The SameFrame pin-out feature is the

arrangement of balls on FineLine BGA packages such that the lower-ball-

count packages form a subset of the higher-ball-count packages.

SameFrame pin-outs provide the flexibility to migrate not only from

device to device within the same package, but also from one package to

another. A given printed circuit board (PCB) layout can support multiple

device density/ package combinations. For example, a single board layout

can support a range of devices from an EPF10K10A device in a 256-pin

FineLine BGA package to an EPF10K100A device in a 484-pin

FineLine BGA package.

The Altera software provides support to design PCBs with SameFrame

pin-out devices. Devices can be defined for present and future use. The

Altera software generates pin-outs describing how to lay out a board to

take advantage of this migration (see Figure 16).

Figure 16. SameFrame Pin-Out Example

Printed Circuit Board

Designed for 484-PinFineLine BGA Package

256-Pin

FineLine

BGA

484-Pin

FineLine

BGA

256-Pin FineLine BGA Package

(Reduced I/O Count or

484-Pin FineLine BGA Package

(Increased I/O Count or

Logic Requirements)

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

To support high-speed designs, selected FLEX 10K devices offer optional

ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)

that is used to increase design speed and reduce resource usage. The

ClockLock circuitry uses a synchronizing PLL that reduces the clock delay

and skew within a device. This reduction minimizes clock-to-output and

setup times while maintaining zero hold times. The ClockBoost circuitry,

which provides a clock multiplier, allows the designer to enhance device

area efficiency by sharing resources within the device. The ClockBoost

feature allows the designer to distribute a low-speed clock and multiply

that clock on-device. Combined, the ClockLock and ClockBoost features

provide significant improvements in system performance and

bandwidth.

ClockLock &

ClockBoost

Features

The ClockLock and ClockBoost features in FLEX 10K devices are enabled

through the Altera software. External devices are not required to use these

features. The output of the ClockLock and ClockBoost circuits is not

available at any of the device pins.

The ClockLock and ClockBoost circuitry locks onto the rising edge of the

incoming clock. The circuit output can only drive the clock inputs of

registers; the generated clock cannot be gated or inverted.

The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and

ClockBoost circuitry. When the dedicated clock pin is driving the

ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the

device.

In designs that require both a multiplied and non-multiplied clock, the

clock trace on the board can be connected to GCLK1. With the Altera

software, GCLK1can feed both the ClockLock and ClockBoost circuitry in

the FLEX 10K device. However, when both circuits are used, the other

clock pin (GCLK0) cannot be used. Figure 17 shows a block diagram of how

to enable both the ClockLock and ClockBoost circuits in the Altera

software. The example shown is a schematic, but a similar approach

applies for designs created in AHDL, VHDL, and Verilog HDL. When the

ClockLock and ClockBoost circuits are used simultaneously, the input

frequency parameter must be the same for both circuits. In Figure 17, the

input frequency must meet the requirements specified when the

ClockBoost multiplication factor is two.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 17. Enabling ClockLock & ClockBoost in the Same Design

CLOCKBOOST=1

INPUT_FREQUENCY=50

CLKLOCK

aout

gclk1

CLOCKBOOST=2

INPUT_FREQUENCY=50

CLKLOCK

bout

To use both the ClockLock and ClockBoost circuits in the same design,

designers must use Revision C EPF10K100GC503-3DX devices and

MAX+PLUS II software versions 7.2 or higher. The die revision is

indicated by the third digit of the nine-digit code on the top side of the

device.

This section discusses the peripheral component interconnect (PCI)

pull-up clamping diode option, slew-rate control, open-drain output

option, MultiVolt I/ O interface, and power sequencing for FLEX 10K

devices. The PCI pull-up clamping diode, slew-rate control, and

open-drain output options are controlled pin-by-pin via Altera logic

Output

Conﬁguration

options. The MultiVolt I/ O interface is controlled by connecting V

CCIO

a different voltage than V

. Its effect can be simulated in the Altera

CCINT

software via the Global Project Device Options dialog box (Assign

menu).

PCI Clamping Diodes

The EPF10K10A and EPF10K30A devices have a pull-up clamping diode

on every I/ O, dedicated input, and dedicated clock pin. PCI clamping

diodes clamp the transient overshoot caused by reflected waves to the

value and are required for 3.3-V PCI compliance. Clamping diodes

CCIO

can also be used to limit overshoot in other systems.

Clamping diodes are controlled on a pin-by-pin basis via a logic option in

the Altera software. When V

is 3.3 V, a pin that has the clamping

CCIO

diode turned on can be driven by a 2.5-V or 3.3-V signal, but not a 5.0-V

signal. When V is 2.5 V, a pin that has the clamping diode turned on

CCIO

can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal. However,

a clamping diode can be turned on for a subset of pins, which allows

devices to bridge between a 3.3-V PCI bus and a 5.0-V device.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Slew-Rate Control

The output buffer in each IOE has an adjustable output slew rate that can

be configured for low-noise or high-speed performance. A slower slew

rate reduces system noise and adds a maximum delay of approximately

2.9 ns. The fast slew rate should be used for speed-critical outputs in

systems that are adequately protected against noise. Designers can specify

the slew rate on a pin-by-pin basis during design entry or assign a default

slew rate to all pins on a device-wide basis. The slow slew rate setting

affects only the falling edge of the output.

Open-Drain Output Option

FLEX 10K devices provide an optional open-drain (electrically equivalent

to an open-collector) output for each I/ O pin. This open-drain output

enables the device to provide system-level control signals (e.g., interrupt

and write enable signals) that can be asserted by any of several devices. It

can also provide an additional wired-ORplane. Additionally, the Altera

software can convert tri-state buffers with grounded data inputs to open-

drain pins automatically.

Open-drain output pins on FLEX 10K devices (with a pull-up resistor to

the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V of

3.5 V. When the open-drain pin is active, it will drive low. When the pin

is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-

drain pin will only drive low or tri-state; it will never drive high. The rise

time is dependent on the value of the pull-up resistor and load

impedance. The I current specification should be considered when

selecting a pull-up resistor.

Output pins on 5.0-V FLEX 10K devices with V

= 3.3 V or 5.0 V (with

CCIO

a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input

pins. In this case, the pull-up transistor will turn off when the pin voltage

exceeds 3.3 V. Therefore, the pin does not have to be open-drain.

MultiVolt I/O Interface

The FLEX 10K device architecture supports the MultiVolt I/ O interface

feature, which allows FLEX 10K devices to interface with systems of

differing supply voltages. These devices have one set of V pins for

internal operation and input buffers (VCCINT) and another set for I/ O

output drivers (VCCIO).

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 12 describes the FLEX 10K device supply voltages and MultiVolt

I/ O support levels.

Table 12. Supply Voltages & MultiVolt I/O Support Levels

Devices

Supply Voltage (V)

MultiVolt I/O Support Levels (V)

Input

Output

CCINT

CCIO

FLEX 10K (1)

5.0

3.3

5.0

3.3

2.5

3.3 or 5.0

5.0

3.3 or 5.0

2.5

EPF10K50V (1)

EPF10K130V

FLEX 10KA (1)

3.3 or 5.0

2.5, 3.3, or 5.0

Note

(1) 240-pin QFP packages do not support the MultiVolt I/ O features, so they do not have separate V_CCIOpins.

Power Sequencing & Hot-Socketing

Because FLEX 10K devices can be used in a multi-voltage environment,

they have been designed specifically to tolerate any possible power-up

sequence. The V

order.

and V

power supplies can be powered in any

CCIO

CCINT

Signals can be driven into FLEX 10KA devices before and during power

up without damaging the device. Additionally, FLEX 10KA devices do

not drive out during power up. Once operating conditions are reached,

FLEX 10KA devices operate as specified by the user.

All FLEX 10K devices provide JTAG BST circuitry that complies with the

IEEE Std. 1149.1-1990 specification. All FLEX 10K devices can also be

configured using the JTAG pins through the BitBlaster serial download

cable, or ByteBlasterMV parallel port download cable, or via hardware

that uses the Jam^TMprogramming and test language. JTAG BST can be

performed before or after configuration, but not during configuration.

FLEX 10K devices support the JTAG instructions shown in Table 13.

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 13. FLEX 10K JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern output at the device pins.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST

data to pass synchronously through a selected device to adjacent devices during normal

device operation.

USERCODE

IDCODE

Selects the user electronic signature (USERCODE) register and places it between the

TDIand TDOpins, allowing the USERCODE to be serially shifted out of TDO.

Selects the IDCODE register and places it between TDIand TDO, allowing the IDCODE

to be serially shifted out of TDO.

ICR Instructions

These instructions are used when configuring a FLEX 10K device via JTAG ports with a

BitBlaster, or ByteBlasterMV or MasterBlaster download cable, or using a Jam File

(.jam) or Jam Byte-Code File (.jbc) via an embedded processor.

The instruction register length of FLEX 10K devices is 10 bits. The

USERCODE register length in FLEX 10K devices is 32 bits; 7 bits are

determined by the user, and 25 bits are predetermined. Tables 14 and 15

show the boundary-scan register length and device IDCODE information

for FLEX 10K devices.

Table 14. FLEX 10K Boundary-Scan Register Length

Device

Boundary-Scan

EPF10K10, EPF10K10A

EPF10K20

480

624

EPF10K30, EPF10K30A

EPF10K40

768

864

EPF10K50, EPF10K50V

EPF10K70

960

1,104

1,248

1,440

EPF10K100, EPF10K100A

EPF10K130V

EPF10K250A

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 15. 32-Bit FLEX 10K Device IDCODE

Note (1)

Device

IDCODE (32 Bits)

Part Number Manufacturer’s Identity 1 (1 Bit)

Version

(4 Bits)

(16 Bits)

(11 Bits)

(2)

EPF10K10, EPF10K10A

EPF10K20

0000

0001 0000 0001 0000

0001 0000 0010 0000

0001 0000 0011 0000

0001 0000 0100 0000

0001 0000 0101 0000

0001 0000 0111 0000

0000 0001 0000 0000

0000 0001 0011 0000

0000 0010 0101 0000

00001101110

EPF10K30, EPF10K30A

EPF10K40

EPF10K50, EPF10K50V

EPF10K70

EPF10K100, EPF10K100A

EPF10K130V

EPF10K250A

Notes:

(1) The most significant bit (MSB) is on the left.

(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.

FLEX 10K devices include weak pull-ups on JTAG pins.

For more information, see the following documents:

ꢀ

Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in

Altera Devices)

ꢀ

BitBlaster Serial Download Cable Data Sheet

ByteBlasterMV Parallel Port Download Cable Data Sheet

Jam Programming & Test Language Specification

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 18 shows the timing requirements for the JTAG signals.

Figure 18. JTAG Waveforms

TMS

TDI

t_JCP

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

t_JSSU

t_JSH

Signal

to Be

Captured

t_JSCO

t_JSZX

t_JSXZ

Signal

to Be

Driven

Table 16 shows the timing parameters and values for FLEX 10K devices.

Table 16. JTAG Timing Parameters & Values

Symbol

Parameter

Min Max Unit

TCKclock period

TCKclock high time

TCKclock low time

100

JCP

JCH

JCL

JTAG port setup time

JPSU

JPH

JTAG port hold time

JTAG port clock to output

JPCO

JPZX

JPXZ

JSSU

JSH

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

Update register clock to output

Update register high-impedance to valid output

Update register valid output to high impedance

JSCO

JSZX

JSXZ

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Each FLEX 10K device is functionally tested. Complete testing of each

Generic Testing

configurable SRAM bit and all logic functionality ensures 100% yield.

AC test measurements for FLEX 10K devices are made under conditions

equivalent to those shown in Figure 19. Multiple test patterns can be used

to configure devices during all stages of the production flow.

Figure 19. FLEX 10K AC Test Conditions

Power supply transients can affect AC

measurements. Simultaneous transitions of

multiple outputs should be avoided for

accurate measurement. Threshold tests must

not be performed under AC conditions.

VCC

464 Ω

(703 Ω)

[521 Ω]

Large-amplitude, fast-ground-current

To Test

System

Device

Output

transients normally occur as the device

outputs discharge the load capacitances.

When these transients ﬂow through the

parasitic inductance between the device

ground pin and the test system ground,

signiﬁcant reductions in observable noise

immunity can result. Numbers without

parentheses are for 5.0-V devices or outputs.

Numbers in parentheses are for 3.3-V devices

or outputs. Numbers in brackets are for

2.5-V devices or outputs.

250 Ω

(8.06 kΩ)

[481 Ω]

C1 (includes

JIG capacitance)

Device input

rise and fall

times < 3 ns

Tables 17 through 21 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for 5.0-V FLEX 10K devices.

Operating

Conditions

Table 17. FLEX 10K 5.0-V Device Absolute Maximum Ratings

Note (1)

Symbol

Parameter

Conditions

Min

Max

Unit

Supply voltage

With respect to ground (2)

–2.0

–25

–65

7.0

DC input voltage

DC output current, per pin

Storage temperature

Ambient temperature

Junction temperature

° C

OUT

No bias

150

135

150

135

STG

AMB

Under bias

Ceramic packages, under bias

PQFP, TQFP, RQFP, and BGA

packages, under bias

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 18. FLEX 10K 5.0-V Device Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

Supply voltage for internal logic (3), (4)

4.75 (4.50) 5.25 (5.50)

3.00 (3.00) 3.60 (3.60)

CCINT

and input buffers

Supply voltage for output

buffers, 5.0-V operation

(3), (4)

CCIO

Supply voltage for output

buffers, 3.3-V operation

Input voltage

–0.5

+ 0.5

CCINT

Output voltage

CCIO

Ambient temperature

For commercial use

For industrial use

For commercial use

For industrial use

° C

–40

Operating temperature

–40

100

Input rise time

Input fall time

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 19. FLEX 10K 5.0-V Device DC Operating Conditions

Notes (5), (6)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High-level input

voltage

2.0

+ 0.5

CCINT

Low-level input voltage

–0.5

0.8

5.0-V high-level TTL

output voltage

= –4 mA DC, V

= 4.75 V

= 3.00 V

2.4

CCIO

(7)

3.3-V high-level TTL

output voltage

= –4 mA DC, V

2.4

(7)

3.3-V high-level CMOS I = –0.1 mA DC, V

= 3.00 V

– 0.2

CCIO

output voltage

(7)

5.0-V low-level TTL

output voltage

= 12 mA DC, V

= 4.75 V

= 3.00 V

0.45

0.2

CCIO

(8)

3.3-V low-level TTL

output voltage

(8)

3.3-V low-level CMOS

output voltage

= 0.1 mA DC, V

CCIO

(8)

Input pin leakage

current

V = V

or ground

–10

–40

µA

(9)

Tri-stated I/O pin

leakage current

= V or ground

(9)

V = ground, no load

supply current

0.5

CC0

(standby)

Table 20. 5.0-V Device Capacitance of EPF10K10, EPF10K20 & EPF10K30 Devices

Note (10)

Symbol

Parameter

Input capacitance

Conditions

Min

Max

Unit

= 0 V, f = 1.0 MHz

Input capacitance on dedicated

clock pin

INCLK

Output capacitance

= 0 V, f = 1.0 MHz

OUT

Table 21. 5.0-V Device Capacitance of EPF10K40, EPF10K50, EPF10K70 & EPF10K100 Devices Note (10)

Symbol

Parameter

Input capacitance

Conditions

Min

Max

Unit

= 0 V, f = 1.0 MHz

Input capacitance on dedicated

clock pin

INCLK

Output capacitance

= 0 V, f = 1.0 MHz

OUT

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents

less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum V_CCrise time is 100 ms. V_CCmust rise monotonically.

(5) Typical values are for T_A= 25° C and V_CC= 5.0 V.

(6) These values are specified under the Recommended Operation Condition shown in Table 18 on page 45.

(7) The I_OHparameter refers to high-level TTL or CMOS output current.

(8) The I_OLparameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as

well as output pins.

(9) This value is specified for normal device operation. The value may vary during power-up.

(10) Capacitance is sample-tested only.

Figure 20 shows the typical output drive characteristics of FLEX 10K

devices with 5.0-V and 3.3-V V

. The output driver is compliant with

CCIO

the 5.0-V PCI Local Bus Specification, Revision 2.2 (for 5.0-V V

CCIO

Figure 20. Output Drive Characteristics of FLEX 10K Devices

5.0-V

3.3-V

150

120

150

120

I_OL

V_CCINT= 5.0 V

V_CCIO= 5.0 V

Room Temperature

V_CCINT= 5.0 V

V_CCIO= 3.3 V

Room Temperature

Typical I

Output

Typical I

Output

Current (mA)

I_OH

3.3

V_OOutput Voltage (V)

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 22 through 25 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for EPF10K50V and EPF10K130V devices.

Table 22. EPF10K50V & EPF10K130V Device Absolute Maximum Ratings

Note (1)

Symbol

Parameter

Conditions

Min

Max

Unit

Supply voltage

With respect to ground (2)

–0.5

–2.0

–25

–65

4.6

5.75

DC input voltage

DC output current, per pin

Storage temperature

Ambient temperature

Junction temperature

° C

OUT

No bias

150

135

150

135

STG

AMB

Under bias

Ceramic packages, under bias

RQFP and BGA packages, under

bias

Table 23. EPF10K50V & EPF10K130V Device Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

Supply voltage for internal logic (3), (4)

3.00 (3.00) 3.60 (3.60)

CCINT

and input buffers

Supply voltage for output

buffers

(3), (4)

3.00 (3.00) 3.60 (3.60)

CCIO

Input voltage

(5)

-0.5

5.75

Output voltage

CCIO

Ambient temperature

For commercial use

For industrial use

For commercial use

For industrial use

° C

–40

Operating temperature

–40

100

Input rise time

Input fall time

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 24. EPF10K50V & EPF10K130V Device DC Operating Conditions

Notes (6), (7)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High-level input voltage

Low-level input voltage

2.0

5.75

0.8

–0.5

3.3-V high-level TTL output

voltage

= –8 mA DC (8)

= –0.1 mA DC (8)

= 8 mA DC (9)

2.4

3.3-V high-level CMOS output

voltage

– 0.2

CCIO

3.3-V low-level TTL output

voltage

0.45

0.2

3.3-V low-level CMOS output

voltage

= 0.1 mA DC (9)

Input pin leakage current

V = 5.3 V to –0.3 V (10)

–10

µA

Tri-stated I/O pin leakage

current

V = 5.3 V to –0.3 V (10)

supply current (standby)

V = ground, no load

0.3

CC0

V = ground, no load (11)

Table 25. EPF10K50V & EPF10K130V Device Capacitance

(12)

Symbol

Parameter

Conditions

Min

Max

Unit

Input capacitance

= 0 V, f = 1.0 MHz

Input capacitance on dedicated

clock pin

INCLK

Output capacitance

= 0 V, f = 1.0 MHz

OUT

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V

for input currents less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum V_CCrise time is 100 ms. V_CCmust rise monotonically.

(5) EPF10K50V and EPF10K130V device inputs may be driven before V_CCINTand V_CCIOare powered.

(6) Typical values are for T_A= 25° C and V_CC= 3.3 V.

(7) These values are specified under the EPF10K50V and EPF10K130V device Recommended Operating Conditions in

Table 23 on page 48.

(8) The I_OHparameter refers to high-level TTL or CMOS output current.

(9) The I_OLparameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as

well as output pins.

(10) This value is specified for normal device operation. The value may vary during power-up.

(11) This parameter applies to -1 speed grade EPF10K50V devices, -2 speed grade EPF10K50V industrial temperature

devices, and -2 speed grade EPF10K130V devices.

(12) Capacitance is sample-tested only.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 21 shows the typical output drive characteristics of EPF10K50V

and EPF10K130V devices.

Figure 21. Output Drive Characteristics of EPF10K50V & EPF10K130V Devices

Typical I

Output

Current (mA)

I_OL

= 3.3 V

Room Temperature

I_OH

V_OOutput Voltage (V)

Tables 26 through 31 provide information on absolute maximum ratings,

recommended operating conditions, DC operating conditions, and

capacitance for 3.3-V FLEX 10K devices.

Table 26. FLEX 10KA 3.3-V Device Absolute Maximum Ratings

Note (1)

Symbol

Parameter

Conditions

Min

Max

Unit

Supply voltage

With respect to ground (2)

–0.5

–2.0

–25

–65

4.6

5.75

DC input voltage

DC output current, per pin

Storage temperature

Ambient temperature

Junction temperature

° C

OUT

No bias

150

135

150

135

STG

AMB

Under bias

Ceramic packages, under bias

PQFP, TQFP, RQFP, and BGA

packages, under bias

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 27. FLEX 10KA 3.3-V Device Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

Supply voltage for internal logic (3), (4)

3.00 (3.00) 3.60 (3.60)

2.30 (2.30) 2.70 (2.70)

CCINT

and input buffers

Supply voltage for output

buffers, 3.3-V operation

(3), (4)

(5)

CCIO

Supply voltage for output

buffers, 2.5-V operation

Input voltage

–0.5

5.75

Output voltage

CCIO

Ambient temperature

For commercial use

For industrial use

For commercial use

For industrial use

° C

–40

Operating temperature

–40

100

Input rise time

Input fall time

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 28. FLEX 10KA 3.3-V Device DC Operating Conditions

Notes (6), (7)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High-level input voltage

1.7 or

5.75

0.5 × V

CCINT

whichever is

lower

Low-level input voltage

–0.5

0.3 × V

CCINT

3.3-V high-level TTL output

voltage

= –11 mA DC,

2.4

= 3.00 V (8)

CCIO

3.3-V high-level CMOS output

voltage

= –0.1 mA DC,

– 0.2

CCIO

= 3.00 V (8)

CCIO

3.3-V high-level PCI output

voltage

= –0.5 mA DC,

0.9 × V

CCIO

= 3.00 to 3.60 V (8)

CCIO

2.5-V high-level output voltage I

= –0.1 mA DC,

2.1

2.0

1.7

= 2.30 V (8)

CCIO

= –1 mA DC,

= 2.30 V (8)

CCIO

= –2 mA DC,

= 2.30 V (8)

CCIO

3.3-V low-level TTL output

voltage

= 9 mA DC,

0.45

0.2

= 3.00 V (9)

CCIO

3.3-V low-level CMOS output

voltage

= 0.1 mA DC,

= 3.00 V (9)

CCIO

3.3-V low-level PCI output

voltage

= 1.5 mA DC,

0.1 × V

CCIO

= 3.00 to 3.60 V (9)

CCIO

2.5-V low-level output voltage

= 0.1 mA DC,

0.2

0.4

0.7

= 2.30 V (9)

CCIO

= 1 mA DC,

= 2.30 V (9)

= 2 mA DC,

= 2.30 V (9)

Input pin leakage current

V = 5.3 V to –0.3 V (10)

–10

µA

Tri-stated I/O pin leakage

current

V = 5.3 V to –0.3 V (10)

supply current (standby) V = ground, no load

0.3

CC0

V = ground, no load (11)

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 29. 3.3-V Device Capacitance of EPF10K10A & EPF10K30A Devices

Note (12)

Symbol

Parameter

Conditions

Min

Max

Unit

Input capacitance

= 0 V, f = 1.0 MHz

Input capacitance on dedicated

clock pin

INCLK

Output capacitance

= 0 V, f = 1.0 MHz

OUT

Table 30. 3.3-V Device Capacitance of EPF10K100A Devices

Symbol

Note (12)

Parameter

Conditions

Min

Max

Unit

Input capacitance

= 0 V, f = 1.0 MHz

Input capacitance on dedicated

clock pin

= 0 V, f = 1.0 MHz

INCLK

Output capacitance

= 0 V, f = 1.0 MHz

OUT

Table 31. 3.3-V Device Capacitance of EPF10K250A Devices

Symbol

Note (12)

Parameter

Conditions

Min

Max

Unit

Input capacitance

= 0 V, f = 1.0 MHz

Input capacitance on dedicated

clock pin

= 0 V, f = 1.0 MHz

INCLK

Output capacitance

= 0 V, f = 1.0 MHz

OUT

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC voltage input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to

5.75 V for input currents less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum V_CCrise time is 100 ms, and V_CCmust rise monotonically.

(5) FLEX 10KA device inputs may be driven before V_CCINTand V_CCIOare powered.

(6) Typical values are for T_A= 25° C and V_CC= 3.3 V.

(7) These values are specified under the Recommended Operating Conditions shown in Table 27 on page 51.

(8) The I_OHparameter refers to high-level TTL, PCI, or CMOS output current.

(9) The I_OLparameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins

as well as output pins.

(10) This value is specified for normal device operation. The value may vary during power-up.

(11) This parameter applies to all -1 speed grade commercial temperature devices and all -2 speed grade

industrial-temperature devices.

(12) Capacitance is sample-tested only.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 22 shows the typical output drive characteristics of EPF10K10A,

EPF10K30A, EPF10K100A, and EPF10K250A devices with 3.3-V and 2.5-V

. The output driver is compliant with the 3.3-V PCI Local Bus

CCIO

Specification, Revision 2.2 (with 3.3-V V

). Moreover, device analysis

CCIO

shows that the EPF10K10A, EPF10K30A, and EPF 10K100A devices can

drive a 5.0-V PCI bus with eight or fewer loads.

Figure 22. Output Drive Characteristics for EPF10K10A, EPF10K30A & EPF10K100A Devices

I_OL

V_CCINT= 3.3 V

_CCIO= 2.5 V

Room Temperature

V_CCINT= 3.3 V

V_CCIO= 3.3 V

Room Temperature

Typical I

Output

Current (mA)

Typical I

Output

Current (mA)

I_OH

V_OOutput Voltage (V)

Figure 23 shows the typical output drive characteristics of the

EPF10K250A device with 3.3-V and 2.5-V V

CCIO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 23. Output Drive Characteristics for EPF10K250A Device

I_OL

V_CCINT= 3.3 V

V_CCIO= 3.3 V

Room Temperature

V_CCINT= 3.3 V

V_CCIO= 2.5 V

Room Temperature

Typical I

Output

Current (mA)

Typical I

Output

Current (mA)

I_OH

V_OOutput Voltage (V)

The continuous, high-performance FastTrack Interconnect routing

resources ensure predictable performance and accurate simulation and

timing analysis. This predictable performance contrasts with that of

FPGAs, which use a segmented connection scheme and therefore have

unpredictable performance.

Timing Model

Device performance can be estimated by following the signal path from a

source, through the interconnect, to the destination. For example, the

registered performance between two LEs on the same row can be

calculated by adding the following parameters:

ꢀ

LE register clock-to-output delay (t

)

Interconnect delay (t

)

SAMEROW

LE look-up table delay (t

)

LUT

LE register setup time (t

)

The routing delay depends on the placement of the source and destination

LEs. A more complex registered path may involve multiple combinatorial

LEs between the source and destination LEs.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Timing simulation and delay prediction are available with the

MAX+PLUS II Simulator and Timing Analyzer, or with industry-

standard EDA tools. The Simulator offers both pre-synthesis functional

simulation to evaluate logic design accuracy and post-synthesis timing

simulation with 0.1-ns resolution. The Timing Analyzer provides point-

to-point timing delay information, setup and hold time analysis, and

device-wide performance analysis.

Figure 24 shows the overall timing model, which maps the possible paths

to and from the various elements of the FLEX 10K device.

Figure 24. FLEX 10K Device Timing Model

Dedicated

Clock/Input

Interconnect

I/O Element

Logic

Element

Embedded Array

Block

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figures 25 through 27 show the delays that correspond to various paths

and functions within the LE, IOE, and EAB timing models.

Figure 25. FLEX 10K Device LE Timing Model

Carry-In

Cascade-In

Delays

LUT Delay

t_LUT

Data-In

t_RLUT

Data-Out

t_CO

t_COMB

t_SU

t_CLUT

Packed Register

Delay

t_H

t_PRE

t_CLR

t_PACKED

Delay

t_C

t_EN

Control-In

Carry Chain

Delay

t_CGENR

t_CGEN

t_CICO

t_CASC

t_LABCARRY

t_LABCASC

Carry-Out

Cascade-Out

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 26. FLEX 10K Device IOE Timing Model

Output Data

Delay

I/O Register

Delays

Output

Delays

t_IOD

t_IOCO

t_IOCOMB

t_IOSU

t_IOH

t_IOCLR

Data-In

t_OD1

t_OD2

t_OD3

t_XZ

I/O Element

Control Delay

t_ZX1

t_ZX2

t_ZX3

Clock Enable

Clear

t_IOC

Clock

t_INREG

Output Enable

Input Register Delay

I/O Register

Feedback Delay

Data Feedback

into FastTrack

Interconnect

t_IOFD

Input Delay

t_INCOMB

Figure 27. FLEX 10K Device EAB Timing Model

Input Register

Delays

RAM/ROM

Block Delays

Output Register

Delays

EAB Output

Delay

EAB Data Input

Delays

Data-In

Data-Out

t_EABDATA1

t_EABDATA2

t_EABCO

t_EABBYPASS

t_EABSU

t_EABH

t_AA

t_EABCO

t_EABBYPASS

t_EABSU

t_EABH

t_EABOUT

t_DD

Address

t_WP

t_WDSU

t_WDH

t_WASU

t_WAH

t_WO

Write Enable

Input Delays

t_EABCH

t_EABCL

t_EABCH

t_EABCL

t_EABWE1

t_EABWE2

EAB Clock

Delay

Input Register

Clock

t_EABCLK

Output Register

Clock

Figures 28 shows the timing model for bidirectional I/ O pin timing.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 28. Synchronous Bidirectional Pin External Timing Model

OE Register

PRN

Dedicated

Clock

XZBIDIR

ZXBIDIR

CLRN

OUTCOBIDIR

Output Register

PRN

Bidirectional

INSUBIDIR

CLRN

INHBIDIR

Input Register

PRN

CLRN

Tables 32 through 36 describe the FLEX 10K device internal timing

parameters. These internal timing parameters are expressed as worst-case

values. Using hand calculations, these parameters can be used to estimate

design performance. However, before committing designs to silicon,

actual worst-case performance should be modeled using timing

simulation and analysis. Tables 37 through 38 describe FLEX 10K external

timing parameters.

Table 32. LE Timing Microparameters (Part 1 of 2)

Note (1)

Symbol Parameter

Conditions

LUT delay for data-in

LUT delay for carry-in

LUT

CLUT

RLUT

PACKED

LUT delay for LE register feedback

Data-in to packed register delay

LE register enable delay

Carry-in to carry-out delay

CICO

CGEN

CGENR

CASC

Data-in to carry-out delay

LE register feedback to carry-out delay

Cascade-in to cascade-out delay

LE register control signal delay

LE register clock-to-output delay

Combinatorial delay

COMB

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 32. LE Timing Microparameters (Part 2 of 2)

Symbol

Note (1)

Parameter

Conditions

LE register setup time for data and enable signals before clock; LE register

recovery time after asynchronous clear, preset, or load

LE register hold time for data and enable signals after clock

LE register preset delay

PRE

CLR

LE register clear delay

Minimum clock high time from clock pin

Minimum clock low time from clock pin

Table 33. IOE Timing Microparameters

Note (1)

Parameter

Symbol

Conditions

IOE data delay

IOE register control signal delay

IOD

IOC

IOE register clock-to-output delay

IOE combinatorial delay

IOCO

IOCOMB

IOSU

IOE register setup time for data and enable signals before clock; IOE register

recovery time after asynchronous clear

IOE register hold time for data and enable signals after clock

IOE register clear time

IOH

IOCLR

OD1

Output buffer and pad delay, slow slew rate = off, V

Output buffer and pad delay, slow slew rate = on

IOE output buffer disable delay

= V

C1 = 35 pF (2)

C1 = 35 pF (3)

C1 = 35 pF (4)

CCIO

CCINT

= low voltage

OD2

OD3

IOE output buffer enable delay, slow slew rate = off, V

IOE output buffer enable delay, slow slew rate = on

IOE input pad and buffer to IOE register delay

IOE register feedback delay

= V

CCINT

C1 = 35 pF (2)

C1 = 35 pF (3)

C1 = 35 pF (4)

ZX1

CCIO

= low voltage

ZX2

ZX3

INREG

IOFD

INCOMB

IOE input pad and buffer to FastTrack Interconnect delay

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 34. EAB Timing Microparameters

Note (1)

Symbol

Parameter

Conditions

Data or address delay to EAB for combinatorial input

Data or address delay to EAB for registered input

Write enable delay to EAB for combinatorial input

Write enable delay to EAB for registered input

EAB register clock delay

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

EAB register clock-to-output delay

Bypass register delay

EAB register setup time before clock

EAB register hold time after clock

Address access delay

Write pulse width

Data setup time before falling edge of write pulse

Data hold time after falling edge of write pulse

Address setup time before rising edge of write pulse

Address hold time after falling edge of write pulse

Write enable to data output valid delay

Data-in to data-out valid delay

(5)

WDSU

WDH

WASU

WAH

Data-out delay

EABOUT

EABCH

EABCL

Clock high time

Clock low time

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 35. EAB Timing Macroparameters

Notes (1), (6)

Symbol

Parameter

Conditions

EAB address access delay

EABAA

EAB asynchronous read cycle time

EABRCCOMB

EABRCREG

EABWP

EAB synchronous read cycle time

EAB write pulse width

EAB asynchronous write cycle time

EABWCCOMB

EABWCREG

EABDD

EAB synchronous write cycle time

EAB data-in to data-out valid delay

EAB clock-to-output delay when using output registers

EAB data/address setup time before clock when using input register

EAB data/address hold time after clock when using input register

EAB WEsetup time before clock when using input register

EAB WEhold time after clock when using input register

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

EAB data setup time before falling edge of write pulse when not using input

registers

EABWDSU

EAB data hold time after falling edge of write pulse when not using input

registers

EABWDH

EABWASU

EABWAH

EABWO

EAB address setup time before rising edge of write pulse when not using

input registers

EAB address hold time after falling edge of write pulse when not using input

registers

EAB write enable to data output valid delay

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 36. Interconnect Timing Microparameters

Note (1)

Symbol Parameter

Conditions

Delay from dedicated input pin to IOE control input

Delay from dedicated clock pin to LE or EAB clock

Delay from dedicated input or clock to LE or EAB data

Delay from dedicated clock pin to IOE clock

(7)

DIN2IOE

DCLK2LE

DIN2DATA

DCLK2IOE

DIN2LE

Delay from dedicated input pin to LE or EAB control input

Routing delay for an LE driving another LE in the same LAB

SAMELAB

SAMEROW

Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7)

same row

Routing delay for an LE driving an IOE in the same column

(7)

SAMECOLUMN

Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7)

DIFFROW

row

Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7)

TWOROWS

Routing delay for an LE driving a control signal of an IOE via the peripheral (7)

LEPERIPH

control bus

Routing delay for the carry-out signal of an LE driving the carry-in signal of a

different LE in a different LAB

LABCARRY

LABCASC

Routing delay for the cascade-out signal of an LE driving the cascade-in

signal of a different LE in a different LAB

Table 37. External Timing Parameters

Notes (8), (10)

Symbol

Parameter

Conditions

DRR

interconnects

Setup time with global clock at IOE register

Hold time with global clock at IOE register

INSU

INH

Clock-to-output delay with global clock at IOE register

OUTCO

Table 38. External Bidirectional Timing Parameters

Note (10)

Symbol

Parameter

Condition

Setup time for bidirectional pins with global clock at adjacent LE register

Hold time for bidirectional pins with global clock at adjacent LE register

Clock-to-output delay for bidirectional pins with global clock at IOE register

Synchronous IOE output buffer disable delay

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

Synchronous IOE output buffer enable delay, slow slew rate = off

ZXBIDIR

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be

measured explicitly.

(2) Operating conditions: V_CCIO= 5.0 V 5% for commercial use in FLEX 10K devices.

V_CCIO= 5.0 V 10% for industrial use in FLEX 10K devices.

V_CCIO= 3.3 V 10% for commercial or industrial use in FLEX 10KA devices.

(3) Operating conditions: V_CCIO= 3.3 V 10% for commercial or industrial use in FLEX 10K devices.

V_CCIO= 2.5 V 0.2 V for commercial or industrial use in FLEX 10KA devices.

(4) Operating conditions: V_CCIO= 2.5 V, 3.3 V, or 5.0 V.

(5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WEsignal is registered.

(6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;

these parameters are calculated by summing selected microparameters.

(7) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing

analysis are required to determine actual worst-case performance.

(8) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative

subset of signal paths is tested to approximate typical device applications.

(9) Contact Altera Applications for test circuit specifications and test conditions.

(10) These timing parameters are sample-tested only.

Figures 29 and 30 show the asynchronous and synchronous timing

waveforms, respectively, for the EAB macroparameters in Table 34.

Figure 29. EAB Asynchronous Timing Waveforms

EAB Asynchronous Read

Address

t_EABAA

t_EABRCCOMB

Data-Out

EAB Asynchronous Write

t_EABWP

t_EABWDSU

t_EABWDH

din0

din1

Data-In

t_EABWASU

t_EABWAH

t_EABWCCOMB

Address

t_EABDD

Data-Out

din0

din1

dout2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 30. EAB Synchronous Timing Waveforms

EAB Synchronous Read

Address

CLK

t_EABDATASU

t_EABDATAH

t_EABRCREG

t_EABDATACO

Data-Out

EAB Synchronous Write (EAB Output Registers Used)

din1

din2

din3

Data-In

Address

t_EABWESU

t_EABDATAH

t_EABWEH

t_EABDATASU

CLK

t_EABDATACO

t_EABWCREG

dout0

dout1

din1

din2

din3

din2

Data-Out

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 39 through 47 show EPF10K10 and EPF10K20 device internal and

external timing parameters.

Table 39. EPF10K10 & EPF10K20 Device LE Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

1.4

0.6

1.5

0.6

1.0

0.2

0.9

0.8

1.3

0.9

0.5

1.7

0.7

1.9

0.9

1.2

0.3

1.2

0.9

1.5

1.1

0.6

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

1.3

1.4

2.5

1.6

1.0

1.2

PRE

CLR

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 40. EPF10K10 & EPF10K20 Device IOE Timing Microparameters

Symbol -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

1.3

0.5

0.2

0.0

1.6

0.7

0.2

0.0

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

2.8

1.0

3.2

1.2

1.0

2.6

4.9

6.3

4.5

6.8

8.2

6.0

3.1

1.2

3.5

6.4

8.2

5.4

8.3

10.1

7.5

3.5

IOCLR

OD1

OD2

OD3

ZX1

ZX2

ZX3

INREG

IOFD

INCOMB

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 41. EPF10K10 & EPF10K20 Device EAB Internal Microparameters

Note (1)

Symbol

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

1.5

4.8

1.0

5.0

1.0

0.5

1.5

1.9

6.0

1.2

6.2

2.2

0.6

1.9

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.5

2.0

1.8

2.5

8.7

10.7

5.8

1.6

0.3

0.5

1.0

7.2

2.0

0.4

0.6

1.2

WDSU

WDH

WASU

WAH

5.0

0.5

6.2

0.6

EABOUT

EABCH

EABCL

4.0

5.8

4.0

7.2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 42. EPF10K10 & EPF10K20 Device EAB Internal Timing Macroparameters

Note (1)

Symbol -3 Speed Grade -4 Speed Grade

Unit

Min

Max

Min

Max

13.7

17.0

EABAA

13.7

9.7

17.0

11.9

7.2

EABRCCOMB

EABRCREG

EABWP

5.8

7.3

9.0

EABWCCOMB

EABWCREG

EABDD

13.0

16.0

10.0

2.0

12.5

3.4

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

5.3

0.0

5.5

0.0

5.5

0.0

2.1

0.0

5.6

0.0

5.8

0.0

5.8

0.0

2.7

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

9.5

11.8

EABWO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 43. EPF10K10 Device Interconnect Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

Min Max

-4 Speed Grade

Min Max

Unit

4.8

2.6

4.3

3.4

2.6

0.6

3.6

0.9

4.5

8.1

3.3

0.5

2.7

6.2

3.8

5.2

4.0

3.8

0.6

3.8

1.1

4.9

8.7

3.9

0.8

3.0

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 44. EPF10K20 Device Interconnect Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

Min Max

-4 Speed Grade

Min Max

Unit

5.2

2.6

4.3

2.6

0.6

3.7

1.4

5.1

8.8

4.7

0.5

2.7

6.6

3.8

5.2

4.0

3.8

0.6

3.9

1.6

5.5

9.4

5.6

0.8

3.0

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 45. EPF10K10 & EPF10K20 Device External Timing Parameters

Symbol -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

16.1

20.0

DRR

(2), (3)

5.5

0.0

2.0

6.0

0.0

2.0

INSU

(3)

INH

(3)

6.7

8.4

OUTCO

Table 46. EPF10K10 Device External Bidirectional Timing Parameters

Note (1)

Symbol -3 Speed Grade -4 Speed Grade

Unit

Min

Max

Min

Max

4.5

0.0

2.0

5.6

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

6.7

10.5

8.4

13.4

ZXBIDIR

Table 47. EPF10K20 Device External Bidirectional Timing Parameters

Note (1)

Symbol -3 Speed Grade -4 Speed Grade

Unit

Min

Max

Min

Max

4.6

0.0

2.0

5.7

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

6.7

10.5

8.4

13.4

ZXBIDIR

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 48 through 56 show EPF10K30, EPF10K40, and EPF10K50 device

internal and external timing parameters.

Table 48. EPF10K30, EPF10K40 & EPF10K50 Device LE Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

1.3

0.6

1.5

0.5

0.9

0.2

0.9

1.0

1.3

0.9

0.6

1.8

0.6

2.0

0.8

1.5

0.4

1.4

1.2

1.6

1.2

0.6

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

1.4

0.9

1.4

1.3

0.9

1.2

PRE

CLR

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 49. EPF10K30, EPF10K40 & EPF10K50 Device IOE Timing Microparameters

Symbol -3 Speed Grade -4 Speed Grade

Note (1)

Unit

Min

Max

Min

Max

0.4

0.5

0.4

0.0

0.6

0.9

0.5

0.0

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

3.1

1.0

3.5

1.9

1.0

3.3

5.6

7.0

5.2

7.5

8.9

7.7

3.3

1.2

3.6

IOCLR

OD1

6.5

OD2

8.3

OD3

5.5

ZX1

8.4

ZX2

10.2

10.0

4.0

ZX3

INREG

IOFD

INCOMB

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 50. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Microparameters

Note (1)

Symbol

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

1.5

4.8

1.0

5.0

1.0

0.5

1.5

1.9

6.0

1.2

6.2

2.2

0.6

1.9

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.5

2.0

1.8

2.5

8.7

10.7

5.8

1.6

0.3

0.5

1.0

7.2

2.0

0.4

0.6

1.2

WDSU

WDH

WASU

WAH

5.0

0.5

6.2

0.6

EABOUT

EABCH

EABCL

4.0

5.8

4.0

7.2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 51. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Timing Macroparameters

Symbol -3 Speed Grade -4 Speed Grade

Note (1)

Unit

Min

Max

Min

Max

13.7

17.0

EABAA

13.7

9.7

17.0

11.9

7.2

EABRCCOMB

EABRCREG

EABWP

5.8

7.3

9.0

EABWCCOMB

EABWCREG

EABDD

13.0

16.0

10.0

2.0

12.5

3.4

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

5.3

0.0

5.5

0.0

5.5

0.0

2.1

0.0

5.6

0.0

5.8

0.0

5.8

0.0

2.7

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

9.5

11.8

EABWO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 52. EPF10K30 Device Interconnect Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

Min Max

-4 Speed Grade

Min Max

Unit

6.9

3.6

5.5

4.6

3.6

0.3

3.3

2.5

5.8

9.1

6.2

0.4

2.4

8.7

4.8

7.2

6.2

4.8

0.3

3.7

2.7

6.4

10.1

7.1

0.6

3.0

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 53. EPF10K40 Device Interconnect Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

Min Max

-4 Speed Grade

Min Max

Unit

7.6

3.6

5.5

4.6

3.6

0.3

3.3

3.1

6.4

9.7

6.4

0.4

2.4

9.4

4.8

7.2

6.2

4.8

0.3

3.7

3.2

6.4

10.6

7.1

0.6

3.0

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 54. EPF10K50 Device Interconnect Timing Microparameters

Note (1)

Symbol

-3 Speed Grade

Min Max

-4 Speed Grade

Unit

Min

Max

8.4

3.6

5.5

4.6

3.6

0.3

3.3

3.9

7.2

10.5

7.5

0.4

2.4

10.2

4.8

7.2

6.2

4.8

0.3

3.7

4.1

7.8

11.5

8.2

0.6

3.0

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 55. EPF10K30, EPF10K40 & EPF10K50 Device External Timing Parameters

Note (1)

Symbol

-3 Speed Grade

Min Max

-4 Speed Grade

Unit

Min

Max

17.2

21.1

DRR

(2), (3)

5.7

0.0

2.0

6.4

0.0

2.0

INSU

(3)

INH

(3)

8.8

11.2

OUTCO

Table 56. EPF10K30, EPF10K40 & EPF10K50 Device External Bidirectional Timing Parameters

Symbol -3 Speed Grade -4 Speed Grade

Note (1)

Unit

Min

Max

Min

Max

4.1

0.0

2.0

4.6

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

8.8

12.3

11.2

15.0

ZXBIDIR

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 57 through 63 show EPF10K70 device internal and external timing

parameters.

Table 57. EPF10K70 Device LE Timing Microparameters

Note (1)

Symbol

-2 Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.3

0.4

1.5

0.8

0.2

1.0

1.1

1.0

0.7

0.9

0.4

1.5

0.4

1.6

0.9

0.2

1.1

1.2

1.1

0.8

1.0

0.5

2.0

0.5

2.0

1.3

1.2

0.3

1.4

1.5

1.3

1.0

1.4

0.7

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

1.9

2.1

2.3

2.6

3.1

0.9

1.0

1.4

PRE

CLR

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 58. EPF10K70 Device IOE Timing Microparameters

Note (1)

Symbol

-2 Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.0

0.4

0.0

0.5

0.4

0.0

0.7

0.9

0.0

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

4.5

0.4

5.0

0.5

6.2

0.7

0.6

3.6

5.6

6.9

5.5

7.5

8.8

8.0

7.2

0.7

4.0

6.3

7.7

6.2

8.5

9.9

9.0

8.1

1.6

5.0

IOCLR

OD1

7.3

OD2

8.7

OD3

6.8

ZX1

9.1

ZX2

10.5

10.2

10.3

ZX3

INREG

IOFD

INCOMB

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 59. EPF10K70 Device EAB Internal Microparameters

Note (1)

Symbol -2 Speed Grade -3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.3

4.3

0.9

4.5

0.9

0.4

1.3

1.5

4.8

1.0

5.0

1.0

0.5

1.5

1.9

6.0

1.2

6.2

2.2

0.6

1.9

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.3

1.8

1.5

2.0

1.8

2.5

7.8

8.7

10.7

5.2

1.4

0.3

0.4

0.9

5.8

1.6

0.3

0.5

1.0

7.2

2.0

0.4

0.6

1.2

WDSU

WDH

WASU

WAH

4.5

0.4

5.0

0.5

6.2

0.6

EABOUT

EABCH

EABCL

4.0

5.2

4.0

5.8

4.0

7.2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 60. EPF10K70 Device EAB Internal Timing Macroparameters

Symbol -2 Speed Grade -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

12.1

13.7

17.0

EABAA

12.1

8.6

13.7

9.7

17.0

11.9

7.2

EABRCCOMB

EABRCREG

EABWP

5.2

5.8

6.5

7.3

9.0

EABWCCOMB

EABWCREG

EABDD

11.6

13.0

16.0

8.8

1.7

10.0

2.0

12.5

3.4

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

4.7

0.0

4.9

0.0

1.8

0.0

4.1

0.0

5.3

0.0

5.5

0.0

2.1

0.0

4.7

0.0

5.6

0.0

5.8

0.0

2.7

0.0

5.8

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

8.4

9.5

11.8

EABWO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 61. EPF10K70 Device Interconnect Timing Microparameters

Note (1)

-4 Speed Grade

Symbol

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

6.6

4.2

6.5

5.5

4.2

0.4

4.8

3.3

8.1

12.9

5.5

0.8

2.7

7.3

4.8

7.1

6.2

4.8

0.4

4.9

3.4

8.3

13.2

5.7

0.9

3.0

8.8

6.0

10.8

7.7

6.0

0.5

5.5

3.7

9.2

14.7

6.5

1.1

3.2

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 62. EPF10K70 Device External Timing Parameters

Symbol -2 Speed Grade

Note (1)

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

17.2

19.1

24.2

DRR

(2), (3)

6.6

0.0

2.0

7.3

0.0

2.0

8.0

0.0

2.0

INSU

(3)

INH

(3)

9.9

11.1

14.3

OUTCO

Table 63. EPF10K70 Device External Bidirectional Timing Parameters

Symbol -2 Speed Grade -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

7.4

0.0

2.0

8.1

0.0

2.0

10.4

0.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

9.9

13.7

11.1

15.4

2.0

14.3

18.5

ZXBIDIR

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 64 through 70 show EPF10K100 device internal and external

timing parameters.

Table 64. EPF10K100 Device LE Timing Microparameters

Note (1)

Symbol

-3DX Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.5

0.4

1.6

0.9

0.2

1.1

1.2

1.1

0.8

1.0

0.5

1.5

0.4

1.6

0.9

0.2

1.1

1.2

1.1

0.8

1.0

0.5

2.0

0.5

2.0

1.3

1.2

0.3

1.4

1.5

1.3

1.0

1.4

0.7

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

2.1

2.3

2.1

2.3

2.6

3.1

1.0

1.4

PRE

CLR

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 65. EPF10K100 Device IOE Timing Microparameters

Note (1)

Symbol -3DX Speed Grade -3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.0

0.5

0.4

0.0

0.5

0.4

0.0

0.7

0.9

0.0

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

5.5

0.5

5.5

0.5

6.7

0.7

4.0

6.3

7.7

6.2

8.5

9.9

9.0

0.7

4.0

6.3

7.7

6.2

8.5

9.9

9.0

1.6

5.0

IOCLR

OD1

OD2

OD3

7.3

8.7

6.8

ZX1

9.1

ZX2

10.5

ZX3

without ClockLock or

INREG

ClockBoost circuitry

with ClockLock or

3.0

–

INREG

ClockBoost circuitry

8.1

10.3

IOFD

INCOMB

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 66. EPF10K100 Device EAB Internal Microparameters

Note (1)

Symbol -3DX Speed Grade -3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.5

4.8

1.0

5.0

1.0

0.5

1.5

4.8

1.0

5.0

1.0

0.5

1.5

1.9

6.0

1.2

6.2

2.2

0.6

1.9

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.5

2.0

1.5

2.0

1.8

2.5

8.7

10.7

5.8

1.6

0.3

0.5

1.0

5.8

1.6

0.3

0.5

1.0

7.2

2.0

0.4

0.6

1.2

WDSU

WDH

WASU

WAH

5.0

0.5

5.0

0.5

6.2

0.6

EABOUT

EABCH

EABCL

4.0

5.8

4.0

5.8

4.0

7.2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 67. EPF10K100 Device EAB Internal Timing Macroparameters

Note (1)

-4 Speed Grade

Symbol

-3DX Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

13.7

17.0

EABAA

13.7

9.7

13.7

9.7

17.0

11.9

7.2

EABRCCOMB

EABRCREG

EABWP

5.8

7.3

9.0

EABWCCOMB

EABWCREG

EABDD

13.0

16.0

10.0

2.0

10.0

2.0

12.5

3.4

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

5.3

0.0

5.5

0.0

5.5

0.0

2.1

0.0

5.3

0.0

5.5

0.0

5.5

0.0

2.1

0.0

5.6

0.0

5.8

0.0

5.8

0.0

2.7

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

9.5

11.8

EABWO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 68. EPF10K100 Device Interconnect Timing Microparameters

Note (1)

Symbol

-3DX Speed Grade -3 Speed Grade -4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

10.3

4.8

7.3

6.2

10.3

4.8

7.3

6.2

12.2

6.0

DIN2IOE

DIN2LE

11.0

7.7

DIN2DATA

DCLK2IOE

without ClockLock or

ClockBoost circuitry

with ClockLock or ClockBoost

2.3

4.8

2.3

–

4.8

–

6.0

–

DCLK2IOE

circuitry

without ClockLock or

DCLK2LE

ClockBoost circuitry

with ClockLock or ClockBoost

DCLK2LE

circuitry

0.4

4.9

0.4

4.9

0.5

5.5

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

5.1

5.4

10.0

14.9

6.9

10.0

14.9

6.9

10.9

16.4

8.1

TWOROWS

LEPERIPH

LABCARRY

LABCASC

0.9

1.1

3.0

3.2

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 69. EPF10K100 Device External Timing Parameters

Note (1)

Symbol

-3DX Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

19.1

24.2

DRR

(2), (3), (4)

7.8

2.0

0.0

6.2

2.0

7.8

2.0

0.0

–

8.5

2.0

0.0

–

INSU

(3), (4)

11.1

6.7

11.1

14.3

OUTCO

(3)

INH

(2), (3), (5)

INSU

OUTCO

(3), (5)

–

Table 70. EPF10K100 Device External Bidirectional Timing Parameters

Symbol -3DX Speed Grade -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

(4)

8.1

0.0

2.0

8.1

0.0

2.0

10.4

0.0

INSUBIDIR

(4)

INHBIDIR

OUTCOBIDIR

(4)

11.1

15.3

11.1

15.3

2.0

14.3

18.4

(4)

XZBIDIR

ZXBIDIR

(5)

9.1

0.0

2.0

–

INSUBIDIR

(5)

INHBIDIR

(5)

7.2

14.3

–

OUTCOBIDIR

(5)

XZBIDIR

ZXBIDIR

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

(4) This parameter is measured without the use of the ClockLock or ClockBoost circuits.

(5) This parameter is measured with the use of the ClockLock or ClockBoost circuits.

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Tables 71 through 77 show EPF10K50V device internal and external

timing parameters.

Table 71. EPF10K50V Device LE Timing Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Min

Max

0.9

0.1

0.5

0.4

0.7

0.2

0.8

0.4

0.7

0.3

0.5

0.4

1.0

0.5

0.8

0.4

0.9

0.2

0.7

0.3

0.7

1.0

0.7

0.4

1.3

0.6

0.9

0.5

1.1

0.2

0.8

0.3

0.8

1.3

0.9

0.5

1.6

0.6

1.0

0.7

1.4

0.3

1.2

0.4

0.9

1.5

1.0

0.6

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

0.8

0.5

1.6

0.8

2.2

1.0

2.5

1.4

0.8

0.4

0.5

PRE

CLR

2.0

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 72. EPF10K50V Device IOE Timing Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Min

Max

1.2

0.3

0.0

1.6

0.4

0.3

0.0

1.9

0.5

0.4

0.0

2.1

0.5

0.4

0.0

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

2.8

0.7

2.8

0.8

3.4

1.0

3.9

1.4

0.5

2.8

–

0.6

3.2

–

0.7

3.9

–

0.7

4.7

–

IOCLR

OD1

OD2

6.5

2.8

–

6.9

3.1

–

7.6

3.8

–

8.4

4.6

–

OD3

ZX1

ZX2

6.5

5.0

1.5

6.8

5.7

1.9

7.5

7.0

2.3

8.3

9.0

2.7

ZX3

INREG

IOFD

INCOMB

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 73. EPF10K50V Device EAB Internal Microparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Min

Max

1.7

4.9

0.0

4.0

0.4

0.1

0.9

2.8

3.9

2.5

4.1

0.8

0.2

1.1

3.4

4.8

3.0

5.0

1.0

0.3

1.3

4.6

5.9

3.7

6.2

1.2

0.4

1.6

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

0.8

1.5

1.6

1.8

2.0

2.2

2.5

5.5

8.2

10.0

12.4

6.0

0.1

4.9

0.8

0.2

0.4

0.8

6.0

1.0

0.3

0.5

1.0

7.4

1.2

0.4

0.6

1.2

WDSU

WDH

WASU

WAH

2.8

0.5

4.3

0.4

5.3

0.5

6.5

0.6

EABOUT

EABCH

EABCL

2.0

6.0

4.0

4.9

4.0

6.0

4.0

7.4

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 74. EPF10K50V Device EAB Internal Timing Macroparameters

Note (1)

-4 Speed Grade

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Min

Max

9.5

13.6

16.5

20.8

EABAA

9.5

6.1

13.6

8.8

16.5

10.8

6.0

20.8

13.4

7.4

EABRCCOMB

EABRCREG

EABWP

6.0

4.9

6.2

6.1

7.5

9.2

EABWCCOMB

EABWCREG

EABDD

12.0

11.6

14.2

17.4

6.8

1.0

9.7

1.4

11.8

1.8

14.9

2.2

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

5.3

0.0

4.4

0.0

1.8

0.0

4.5

0.0

4.6

0.0

4.8

0.0

1.1

0.0

4.6

0.0

5.6

0.0

5.8

0.0

1.4

0.0

5.6

0.0

6.9

0.0

7.2

0.0

2.1

0.0

7.4

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

5.1

9.4

11.4

14.0

EABWO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 75. EPF10K50V Device Interconnect Timing Microparameters

Note (1)

-4 Speed Grade

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Min Max

Unit

Min

Max

Min

Max

Min

Max

4.7

2.5

4.4

2.5

0.2

2.8

3.0

5.8

8.6

4.5

0.3

0.0

6.0

2.6

5.9

3.9

2.6

0.2

3.0

3.2

6.2

9.2

5.5

0.4

1.3

7.1

3.1

6.8

4.7

3.1

0.3

3.2

3.4

6.6

9.8

6.1

0.5

1.6

8.2

3.9

7.7

5.5

3.9

0.3

3.4

3.6

7.0

10.4

7.0

0.7

2.0

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 76. EPF10K50V Device External Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Min

Max

11.2

14.0

17.2

21.1

DRR

(2), (3)

5.5

0.0

2.0

4.2

0.0

2.0

5.2

0.0

2.0

6.9

0.0

2.0

INSU

(3)

INH

(3)

5.9

7.8

9.5

11.1

OUTCO

Table 77. EPF10K50V Device External Bidirectional Timing Parameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Min

Max

2.0

0.0

2.0

2.8

0.0

2.0

3.5

0.0

2.0

4.1

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

5.9

8.0

7.8

9.8

9.5

11.8

11.1

14.3

ZXBIDIR

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 78 through 84 show EPF10K130V device internal and external

timing parameters.

Table 78. EPF10K130V Device LE Timing Microparameters

Note (1)

Symbol

-2 Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.3

0.5

1.2

0.5

0.6

0.2

0.3

0.7

0.9

1.9

0.6

0.5

1.8

0.7

1.7

0.6

0.8

0.3

0.4

1.0

1.2

2.4

0.9

0.7

2.3

0.9

2.2

0.7

1.0

0.4

0.5

1.3

1.5

3.0

1.1

0.9

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

0.2

0.0

0.2

0.0

0.3

0.0

2.4

3.1

3.9

PRE

CLR

4.0

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 79. EPF10K130V Device IOE Timing Microparameters

Note (1)

Symbol

-2 Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.3

0.4

0.3

0.0

1.6

0.5

0.4

0.0

2.0

0.7

0.5

0.0

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

2.6

0.0

3.3

0.0

3.8

0.0

1.7

3.5

–

2.2

4.4

–

2.7

5.0

–

IOCLR

OD1

OD2

8.2

4.9

–

8.1

6.3

–

9.7

7.4

–

OD3

ZX1

ZX2

9.6

7.9

6.2

10.0

7.9

12.1

12.6

9.9

ZX3

INREG

IOFD

INCOMB

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 80. EPF10K130V Device EAB Internal Microparameters

Note (1)

Symbol -2 Speed Grade -3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.9

3.7

1.9

3.7

0.7

0.5

0.6

2.4

4.7

2.4

4.7

0.9

0.6

0.8

2.4

4.7

2.4

4.7

0.9

0.6

0.8

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.4

0.0

1.8

0.0

1.8

0.0

5.6

7.1

3.7

4.6

0.0

3.9

0.0

4.7

5.9

0.0

5.0

0.0

4.7

5.9

0.0

5.0

0.0

WDSU

WDH

WASU

WAH

5.6

2.4

7.1

3.1

7.1

3.1

EABOUT

EABCH

EABCL

4.0

4.7

4.0

4.7

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 81. EPF10K130V Device EAB Internal Timing Macroparameters

Symbol -2 Speed Grade -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

11.2

14.2

EABAA

11.1

8.5

14.2

10.8

4.7

14.2

10.8

4.7

EABRCCOMB

EABRCREG

EABWP

3.7

7.6

9.7

EABWCCOMB

EABWCREG

EABDD

14.0

17.8

11.1

3.6

14.2

4.6

14.2

4.6

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

4.4

0.0

4.4

0.0

4.6

0.0

3.9

0.0

5.6

0.0

5.6

0.0

5.9

0.0

5.0

0.0

5.6

0.0

5.6

0.0

5.9

0.0

5.0

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

11.1

14.2

EABWO

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 82. EPF10K130V Device Interconnect Timing Microparameters

Note (1)

-4 Speed Grade

Symbol

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

8.0

2.4

5.0

3.6

2.4

0.4

4.5

9.0

13.5

18.0

8.1

0.6

0.8

9.0

3.0

6.3

4.6

3.0

0.6

5.3

9.5

14.8

20.1

8.6

0.8

1.0

9.5

3.1

7.4

5.1

3.1

0.8

6.5

9.7

16.2

22.7

9.5

1.0

1.2

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 83. EPF10K130V Device External Timing Parameters

Symbol -2 Speed Grade

Note (1)

-3 Speed Grade

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

15.0

19.1

24.2

DRR

(2), (3)

6.9

0.0

2.0

8.6

0.0

2.0

11.0

0.0

INSU

(3)

INH

(3)

7.8

9.9

2.0

11.3

OUTCO

Table 84. EPF10K130V Device External Bidirectional Timing Parameters

Symbol -2 Speed Grade -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

6.7

0.0

2.0

8.5

0.0

2.0

10.8

0.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

6.9

12.9

8.8

16.4

2.0

10.2

19.3

ZXBIDIR

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 85 through 91 show EPF10K10A device internal and external

timing parameters.

Table 85. EPF10K10A Device LE Timing Microparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.9

1.2

1.9

0.6

0.5

1.2

1.4

2.3

0.7

0.6

0.3

0.9

1.2

1.4

0.6

1.6

1.9

3.0

0.9

0.8

0.4

1.1

1.7

1.9

0.8

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

0.7

1.0

1.2

0.5

COMB

1.1

0.6

1.3

0.7

1.7

0.9

0.5

0.6

0.9

PRE

CLR

3.0

3.5

4.0

Table 86. EPF10K10A Device IOE Timing Microparameters

Note (1) (Part 1 of 2)

-3 Speed Grade

Symbol -1 Speed Grade -2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.3

1.5

2.0

0.2

0.6

0.3

0.7

0.3

0.4

0.9

IOC

IOCO

IOCOMB

IOSU

0.8

1.0

1.3

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 86. EPF10K10A Device IOE Timing Microparameters

Note (1) (Part 2 of 2)

-3 Speed Grade

Symbol -1 Speed Grade -2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.8

1.0

1.3

IOH

1.2

2.9

6.6

1.2

2.9

6.6

5.2

3.1

1.4

3.5

7.8

1.4

3.5

7.8

6.3

3.8

1.9

IOCLR

OD1

4.7

OD2

10.5

1.9

OD3

1.9

ZX1

4.7

ZX2

10.5

8.4

ZX3

INREG

IOFD

INCOMB

5.0

100

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 87. EPF10K10A Device EAB Internal Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

3.3

1.0

2.6

2.7

0.0

1.2

0.1

3.9

1.3

3.1

3.2

0.0

1.4

0.2

5.2

1.7

4.1

4.3

0.0

1.8

0.2

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.4

0.1

1.7

0.1

2.2

0.1

4.5

5.4

7.3

2.0

0.7

0.5

0.6

0.9

2.4

0.8

0.6

0.7

1.1

3.2

1.1

0.7

0.9

1.5

WDSU

WDH

WASU

WAH

3.3

0.1

3.9

0.1

5.2

0.2

EABOUT

EABCH

EABCL

3.0

3.5

4.0

3.03

Altera Corporation

101

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 88. EPF10K10A Device EAB Internal Timing Macroparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

8.1

9.8

13.1

EABAA

8.1

5.8

2.0

3.5

9.4

9.8

6.9

13.1

9.3

EABRCCOMB

EABRCREG

EABWP

2.4

3.2

4.2

5.6

EABWCCOMB

EABWCREG

EABDD

11.2

14.8

6.9

1.3

8.3

1.5

11.0

2.0

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

2.4

0.0

4.1

0.0

1.4

0.0

2.5

0.0

3.0

0.0

4.9

0.0

1.6

0.0

3.0

0.0

3.9

0.0

6.5

0.0

2.2

0.0

4.1

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

6.2

7.5

9.9

EABWO

102

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 89. EPF10K10A Device Interconnect Timing Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

4.2

2.2

4.3

4.2

2.2

0.1

2.2

0.8

3.0

5.2

1.8

0.5

0.9

5.0

2.6

5.2

4.9

2.6

0.1

2.4

1.0

3.4

5.8

2.2

0.5

1.0

6.5

3.4

7.1

6.6

3.4

0.2

2.9

1.4

4.3

7.2

2.8

0.7

1.5

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 90. EPF10K10A External Reference Timing Parameters

Note (1)

-3 Speed Grade

Symbol

-1 Speed Grade

-2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

10.0

12.0

16.0

DRR

(2), (3)

1.6

0.0

2.0

2.1

0.0

2.0

2.8

0.0

2.0

INSU

(3)

INH

OUTCO

(3)

5.8

6.9

9.2

Table 91. EPF10K10A Device External Bidirectional Timing Parameters

Symbol -2 Speed Grade -3 Speed Grade

Note (1)

-4 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

2.4

0.0

2.0

3.3

0.0

2.0

4.5

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

5.8

6.3

6.9

7.5

9.2

9.9

ZXBIDIR

Altera Corporation

103

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 92 through 98 show EPF10K30A device internal and external

timing parameters.

Table 92. EPF10K30A Device LE Timing Microparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.8

0.6

1.2

0.6

1.3

0.2

0.8

0.6

0.9

1.1

0.4

0.6

1.1

0.7

1.5

0.6

1.5

0.3

1.0

0.8

1.1

1.3

0.6

0.7

1.5

1.0

2.0

1.0

2.0

0.4

1.3

1.0

1.4

1.7

0.7

0.9

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

0.9

1.1

0.9

1.3

1.4

1.7

0.5

0.6

0.8

PRE

CLR

3.0

3.5

4.0

Table 93. EPF10K30A Device IOE Timing Microparameters

Note (1) (Part 1 of 2)

-3 Speed Grade

Symbol -1 Speed Grade -2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

2.2

0.3

0.2

0.5

2.6

0.3

0.2

0.6

3.4

0.5

0.3

0.8

IOD

IOC

IOCO

IOCOMB

IOSU

1.4

1.7

2.2

104

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 93. EPF10K30A Device IOE Timing Microparameters

Note (1) (Part 2 of 2)

-3 Speed Grade

Symbol -1 Speed Grade -2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.9

1.1

1.4

IOH

0.7

1.9

4.8

7.0

2.2

5.1

7.3

4.4

3.8

0.8

2.2

5.6

8.2

2.6

6.0

8.6

5.2

4.5

1.0

2.9

IOCLR

OD1

7.3

OD2

10.8

3.4

OD3

3.4

ZX1

7.8

ZX2

11.3

6.8

ZX3

INREG

IOFD

INCOMB

5.9

Altera Corporation

105

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 94. EPF10K30A Device EAB Internal Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

5.5

1.1

2.4

2.1

0.0

1.7

0.0

6.5

1.3

2.8

2.5

0.0

2.0

0.0

8.5

1.8

3.7

3.2

0.2

2.6

0.3

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.2

0.1

1.4

0.1

1.9

0.3

4.2

5.0

6.5

3.8

0.1

4.5

0.1

5.9

0.2

WDSU

WDH

WASU

WAH

3.7

0.0

4.4

0.1

6.4

0.6

EABOUT

EABCH

EABCL

3.0

3.8

3.5

4.5

4.0

5.9

106

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 95. EPF10K30A Device EAB Internal Timing Macroparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

9.7

11.6

16.2

EABAA

9.7

5.9

3.8

4.0

9.8

11.6

7.1

16.2

9.7

EABRCCOMB

EABRCREG

EABWP

4.5

5.9

4.7

6.3

EABWCCOMB

EABWCREG

EABDD

11.6

16.6

9.2

1.7

11.0

2.1

16.1

3.4

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

2.3

0.0

3.3

0.0

3.2

0.0

3.7

0.0

2.7

0.0

3.9

0.0

3.8

0.0

4.4

0.0

3.5

0.0

4.9

0.0

5.0

0.0

5.1

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

6.1

7.3

11.3

EABWO

Altera Corporation

107

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 96. EPF10K30A Device Interconnect Timing Microparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

3.9

1.2

3.2

3.0

1.2

0.1

2.3

1.3

3.6

5.9

3.5

0.3

0.9

4.4

1.5

3.6

3.5

1.5

0.1

2.4

1.4

3.8

6.2

3.8

0.4

1.1

5.1

1.9

4.5

4.6

1.9

0.2

2.7

1.9

4.6

7.3

4.1

0.5

1.4

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 97. EPF10K30A External Reference Timing Parameters

Note (1)

-3 Speed Grade

Symbol

-1 Speed Grade

-2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

11.0

13.0

17.0

DRR

(2), (3)

2.5

0.0

2.0

3.1

0.0

2.0

3.9

0.0

2.0

INSU

(3)

INH

OUTCO

(3)

5.4

6.2

8.3

Table 98. EPF10K30A Device External Bidirectional Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

4.2

0.0

2.0

4.9

0.0

2.0

6.8

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

5.4

6.2

7.5

8.3

9.8

ZXBIDIR

108

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 99 through 105 show EPF10K100A device internal and external

timing parameters.

Table 99. EPF10K100A Device LE Timing Microparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.0

0.8

1.4

0.4

0.6

0.2

0.4

0.6

0.7

0.9

0.2

0.6

1.2

0.9

1.6

0.5

0.7

0.2

0.4

0.7

0.9

1.0

0.3

0.7

1.4

1.1

1.9

0.5

0.8

0.3

0.6

0.8

1.0

1.2

0.3

0.8

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

0.8

0.3

1.0

0.5

1.2

0.5

0.3

0.4

PRE

CLR

2.5

3.5

4.0

Altera Corporation

109

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 100. EPF10K100A Device IOE Timing Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

2.5

0.3

0.2

0.5

2.9

0.3

0.2

0.6

3.4

0.4

0.3

0.7

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

1.3

0.2

1.7

0.2

1.8

0.3

1.0

2.2

4.5

6.8

2.7

5.0

7.3

5.3

4.7

1.2

2.6

5.3

7.9

3.1

5.8

8.4

6.1

5.5

1.4

3.0

6.1

9.3

3.7

6.8

10.0

7.2

6.4

IOCLR

OD1

OD2

OD3

ZX1

ZX2

ZX3

INREG

IOFD

INCOMB

110

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 101. EPF10K100A Device EAB Internal Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.8

3.2

0.8

2.3

0.8

1.0

0.3

2.1

3.7

0.9

2.7

0.9

1.1

0.3

2.4

4.4

1.1

3.1

1.1

1.4

0.4

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

1.3

0.4

1.5

0.5

1.8

0.5

4.1

4.8

5.6

3.2

2.4

0.2

0.0

3.7

2.8

0.2

0.0

4.4

3.3

0.3

0.0

WDSU

WDH

WASU

WAH

3.4

0.3

3.9

0.3

4.6

0.4

EABOUT

EABCH

EABCL

2.5

3.2

3.5

3.7

4.0

4.4

Altera Corporation

111

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 102. EPF10K100A Device EAB Internal Timing Macroparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

6.8

7.8

9.2

EABAA

6.8

5.4

3.2

3.4

9.4

7.8

6.2

9.2

7.4

EABRCCOMB

EABRCREG

EABWP

3.7

4.4

3.9

4.7

EABWCCOMB

EABWCREG

EABDD

10.8

12.8

6.1

2.1

6.9

2.3

8.2

2.9

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

3.7

0.0

2.8

0.0

3.4

0.0

1.9

0.0

4.3

0.0

3.3

0.0

4.0

0.0

2.3

0.0

5.1

0.0

3.8

0.0

4.6

0.0

2.6

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

5.1

5.7

6.9

EABWO

112

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 103. EPF10K100A Device Interconnect Timing Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

4.8

2.0

2.4

2.6

2.0

0.1

1.5

5.5

7.0

8.5

3.9

0.2

0.4

5.4

2.4

2.7

3.0

2.4

0.1

1.7

6.5

8.2

9.9

4.2

0.2

0.5

6.0

2.7

2.9

3.5

2.7

0.1

1.9

7.4

9.3

11.2

4.5

0.3

0.6

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 104. EPF10K100A Device External Timing Parameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

12.5

14.5

17.0

DRR

(2), (3)

3.7

0.0

2.0

4.5

0.0

2.0

5.1

0.0

2.0

INSU

(3)

INH

OUTCO

(3)

5.3

6.1

7.2

Table 105. EPF10K100A Device External Bidirectional Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

4.9

0.0

2.0

5.8

0.0

2.0

6.8

0.0

2.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

5.3

7.4

6.1

8.6

7.2

10.1

ZXBIDIR

Altera Corporation

113

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 38 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

Tables 106 through 112 show EPF10K250A device internal and external

timing parameters.

Table 106. EPF10K250A Device LE Timing Microparameters

Note (1)

-3 Speed Grade

Symbol

-1 Speed Grade

-2 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

0.9

1.2

2.0

0.4

1.4

0.2

0.4

0.8

0.7

1.2

0.6

0.5

1.0

1.3

2.3

0.4

1.6

0.3

0.6

1.0

0.8

1.3

0.7

0.6

1.4

1.6

2.7

0.5

1.9

0.3

0.6

1.1

1.0

1.6

0.9

0.7

LUT

CLUT

RLUT

PACKED

CICO

CGEN

CGENR

CASC

COMB

1.2

1.4

1.3

1.7

1.6

0.7

0.8

0.9

PRE

CLR

2.5

3.0

3.5

114

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 107. EPF10K250A Device IOE Timing Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.2

0.4

0.8

0.7

1.3

0.4

0.9

0.7

1.6

0.5

1.1

0.8

IOD

IOC

IOCO

IOCOMB

IOSU

IOH

2.7

0.2

3.1

0.3

3.6

0.3

1.2

3.2

5.9

8.7

3.8

6.5

9.3

8.2

9.0

1.3

3.6

1.6

4.2

IOCLR

OD1

6.7

7.8

OD2

9.8

11.5

5.0

OD3

4.3

5.0

ZX1

7.4

8.6

ZX2

10.5

9.3

12.3

10.9

12.0

ZX3

INREG

IOFD

INCOMB

10.2

Altera Corporation

115

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 108. EPF10K250A Device EAB Internal Microparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

1.3

0.9

5.0

0.6

0.0

0.1

1.5

1.1

5.7

0.7

0.0

0.1

1.7

1.3

6.7

0.8

0.0

0.2

EABDATA1

EABDATA2

EABWE1

EABWE2

EABCLK

EABCO

EABBYPASS

EABSU

EABH

3.8

0.7

4.3

0.8

5.0

0.9

4.5

5.0

5.9

5.6

1.3

0.1

6.4

1.4

0.1

7.5

1.7

0.2

WDSU

WDH

WASU

WAH

4.1

0.1

4.6

0.1

5.5

0.2

EABOUT

EABCH

EABCL

2.5

5.6

3.0

6.4

3.5

7.5

116

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 109. EPF10K250A Device EAB Internal Timing Macroparameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

6.1

6.8

8.2

EABAA

6.1

4.6

6.8

5.1

8.2

6.1

EABRCCOMB

EABRCREG

EABWP

5.6

6.4

7.5

5.8

6.6

7.9

EABWCCOMB

EABWCREG

EABDD

15.8

17.8

21.0

5.7

0.7

6.4

0.8

7.8

1.0

EABDATACO

EABDATASU

EABDATAH

EABWESU

EABWEH

4.5

0.0

8.2

0.0

1.7

0.0

0.9

0.0

5.1

0.0

9.3

0.0

1.8

0.0

0.9

0.0

5.9

0.0

10.9

0.0

2.1

0.0

1.0

0.0

EABWDSU

EABWDH

EABWASU

EABWAH

5.3

6.0

7.4

EABWO

Altera Corporation

117

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 110. EPF10K250A Device Interconnect Timing Microparameters

Note (1)

Symbol

-1 Speed Grade

-2 Speed Grade

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

7.8

2.7

1.6

3.6

2.7

0.2

6.7

2.5

9.2

15.9

7.5

0.3

0.4

8.5

3.1

1.6

4.0

3.1

0.3

7.3

2.7

10.0

17.3

8.1

0.4

9.4

3.5

1.7

4.6

3.5

0.3

8.2

3.0

11.2

19.4

8.9

0.5

DIN2IOE

DIN2LE

DIN2DATA

DCLK2IOE

DCLK2LE

SAMELAB

SAMEROW

SAMECOLUMN

DIFFROW

TWOROWS

LEPERIPH

LABCARRY

LABCASC

Table 111. EPF10K250A Device External Reference Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

15.0

17.0

20.0

DRR

(2) (3)

6.9

0.0

2.0

8.0

0.0

2.0

9.4

0.0

2.0

INSU

(3)

INH

(3)

8.0

8.9

10.4

OUTCO

Table 112. EPF10K250A Device External Bidirectional Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade

Note (1)

-3 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

9.3

0.0

2.0

10.6

0.0

12.7

0.0

INSUBIDIR

INHBIDIR

OUTCOBIDIR

XZBIDIR

8.0

10.8

2.0

8.9

12.2

2.0

10.4

14.2

ZXBIDIR

118

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes to tables:

(1) All timing parameters are described in Tables 32 through 37 in this data sheet.

(2) Using an LE to register the signal may provide a lower setup time.

(3) This parameter is specified by characterization.

For the ClockLock and ClockBoost circuitry to function properly, the

ClockLock &

ClockBoost

Timing

incoming clock must meet certain requirements. If these specifications are

not met, the circuitry may not lock onto the incoming clock, which

generates an erroneous clock within the device. The clock generated by

the ClockLock and ClockBoost circuitry must also meet certain

specifications. If the incoming clock meets these requirements during

configuration, the ClockLock and ClockBoost circuitry will lock onto the

clock during configuration. The circuit will be ready for use immediately

after configuration. Figure 31 illustrates the incoming and generated clock

specifications.

Parameters

Figure 31. Speciﬁcations for the Incoming & Generated Clocks

The t parameter refers to the nominal input clock period; the t parameter refers to the

nominal output clock period.

t_CLK1

t_INDUTY

t_If_CLKDEV

Input

Clock

t_R

t_I

t_It_INCLKSTB

t_F

t_OUTDUTY

ClockLock-

Generated

Clock

t_O

t_O+ t_JITTERt_O– t_JITTER

Table 113 summarizes the ClockLock and ClockBoost parameters.

Table 113. ClockLock & ClockBoost Parameters (Part 1 of 2)

Symbol

Parameter

Min Typ

Max Unit

t_R

Input rise time

Input fall time

Input duty cycle

t_F

t_INDUTY

f_CLK1

t_CLK1

f_CLK2

t_CLK2

Input clock frequency (ClockBoost clock multiplication factor equals 1)

Input clock period (ClockBoost clock multiplication factor equals 1)

Input clock frequency (ClockBoost clock multiplication factor equals 2)

Input clock period (ClockBoost clock multiplication factor equals 2)

MHz

12.5

33.3

MHz

62.5

Altera Corporation

119

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Table 113. ClockLock & ClockBoost Parameters (Part 2 of 2)

Symbol

Parameter

Min Typ

Max Unit

f_CLKDEV1Input deviation from user specification in MAX+PLUS II (ClockBoost clock

multiplication factor equals 1) (1)

MHz

f_CLKDEV2Input deviation from user specification in MAX+PLUS II (ClockBoost clock

multiplication factor equals 2) (1)

0.5

MHz

t_INCLKSTBInput clock stability (measured between adjacent clocks)

100

µs

t_LOCK

Time required for ClockLock or ClockBoost to acquire lock (2)

Jitter on ClockLock or ClockBoost-generated clock (3)

t_JITTER

t_OUTDUTYDuty cycle for ClockLock or ClockBoost-generated clock

Notes:

(1) To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the

input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this

frequency. The f_CLKDEVparameter specifies how much the incoming clock can differ from the specified frequency

during device operation. Simulation does not reflect this parameter.

(2) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If

the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during

configuration, because the t_LOCKvalue is less than the time required for configuration.

(3) The t_JITTERspecification is measured under long-term observation.

The supply power (P) for FLEX 10K devices can be calculated with the

following equation:

Power

Consumption

P = P

+ P = (I

+ I

₎× V + P

CCACTIVE CC IO

INT

CCSTANDBY

Typical I

values are shown as I

in the FLEX 10K device DC

CC0

CCSTANDBY

operating conditions tables on pages 46, 49, and 52 of this data sheet. The

value depends on the switching frequency and the application

CCACTIVE

logic. This value is calculated based on the amount of current that each LE

typically consumes. The P value, which depends on the device output

load characteristics and switching frequency, can be calculated using the

guidelines given in Application Note 74 (Evaluating Power for Altera

Devices).

Compared to the rest of the device, the embedded array

consumes a negligible amount of power. Therefore, the

embedded array can be ignored when calculating supply

current.

The I

value is calculated with the following equation:

CCACTIVE

µA

--------------------------

= K × f

× N × tog

CCACTIVE

MAX

MHz × LE

The parameters in this equation are shown below:

120

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

tog

Maximum operating frequency in MHz

Total number of logic cells used in the device

Average percent of logic cells toggling at each clock

(typically 12.5%)

MAX

Constant, shown in Tables 114 and 115

Table 114. FLEX 10K K Constant Values

Device

K Value

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K70

EPF10K100

Table 115. FLEX 10KA K Constant Values

Device

K Value

EPF10K10A

EPF10K30A

EPF10K50V

EPF10K100A

EPF10K130V

EPF10K250A

This calculation provides an I estimate based on typical conditions with

no output load. The actual I should be verified during operation

because this measurement is sensitive to the actual pattern in the device

and the environmental operating conditions.

To better reflect actual designs, the power model (and the constant K in

the power calculation equations) for continuous interconnect FLEX

devices assumes that logic cells drive FastTrack Interconnect channels. In

contrast, the power model of segmented FPGAs assumes that all logic

cells drive only one short interconnect segment. This assumption may

lead to inaccurate results, compared to measured power consumption for

an actual design in a segmented interconnect FPGA.

Figure 32 shows the relationship between the current and operating

frequency of FLEX 10K devices.

Altera Corporation

121

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 32. I

vs. Operating Frequency (Part 1 of 3)

CCACTIVE

EPF10K10

EPF10K20

500

450

400

350

300

250

200

150

100

1,000

900

800

700

600

500

Supply

Current (mA)

400

300

200

100

Frequency (MHz)

EPF10K30

EPF10K40

1,600

1,400

1,200

1,000

800

2,500

2,000

1,500

1,000

500

Supply

Current (mA)

600

400

200

Frequency (MHz)

EPF10K70

EPF10K50

3,000

2,500

2,000

1,500

1,000

3,500

3,000

2,500

2,000

1,500

1,000

500

Supply

Current (mA)

500

Frequency (MHz)

122

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 32. I

vs. Operating Frequency (Part 2 of 3)

CCACTIVE

EPF10K50V

EPF10K100

700

600

4,500

4,000

3,500

500

400

300

200

100

3,000

2,500

2,000

1,500

1,000

Supply

Current (mA)

500

100

Frequency (MHz)

EPF10K130V

EPF10K10A

150

2,000

1,500

100

Supply

1,000

500

Current (mA)

100

Frequency (MHz)

EPF10K30A

EPF10K100A

1,200

900

400

300

200

100

Supply

Current (mA)

600

300

100

Frequency (MHz)

Altera Corporation

123

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Figure 32. I

vs. Operating Frequency (Part 3 of 3)

CCACTIVE

EPF10K250A

3,500

3,000

2,500

2,000

Supply

Current (mA)

1,500

1,000

500

100

Frequency (MHz)

The FLEX 10K architecture supports several configuration schemes. This

section summarizes the device operating modes and available device

configuration schemes.

Conﬁguration &

Operation

See Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000

Devices) for detailed descriptions of device configuration options, device

configuration pins, and for information on configuring FLEX 10K devices,

including sample schematics, timing diagrams, and configuration

parameters.

Operating Modes

The FLEX 10K architecture uses SRAM configuration elements that

require configuration data to be loaded every time the circuit powers up.

The process of physically loading the SRAM data into the device is called

configuration. Before configuration, as VCC rises, the device initiates a

Power-On Reset (POR). This POR event clears the device and prepares it

for configuration. The FLEX 10K POR time does not exceed 50 µs.

During initialization, which occurs immediately after configuration, the

device resets registers, enables I/ O pins, and begins to operate as a logic

device. The I/ O pins are tri-stated during power-up, and before and

during configuration. Together, the configuration and initialization

processes are called command mode; normal device operation is called user

mode.

124

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

SRAM configuration elements allow FLEX 10K devices to be reconfigured

in-circuit by loading new configuration data into the device. Real-time

reconfiguration is performed by forcing the device into command mode

with a device pin, loading different configuration data, reinitializing the

device, and resuming user-mode operation.

The entire reconfiguration process may be completed in less than 320 ms

using an EPF10K250A device with a DCLKfrequency of 10 MHz. This

process can be used to reconfigure an entire system dynamically. In-field

upgrades can be performed by distributing new configuration files.

Refer to the configuration device data sheet to obtain the POR

delay when using a configuration device method.

Programming Files

Despite being function- and pin-compatible, FLEX 10KA and FLEX 10KE

devices are not programming- or configuration-file compatible with

FLEX 10K devices. A design should be recompiled before it is transferred

from a FLEX 10K device to an equivalent FLEX 10KA or FLEX 10KE

device. This recompilation should be performed to create a new

programming or configuration file and to check design timing on the

faster FLEX 10KA or FLEX 10KE device. The programming or

configuration files for EPF10K50 devices can program or configure an

EPF10K50V device. However, Altera recommends recompiling a design

for the EPF10K50V device when transferring it from the EPF10K50 device.

Conﬁguration Schemes

The configuration data for a FLEX 10K device can be loaded with one of

five configuration schemes (see Table 116), chosen on the basis of the

target application. An EPC1, EPC2, EPC16, or EPC1441 configuration

device, intelligent controller, or the JTAG port can be used to control the

configuration of a FLEX 10K device, allowing automatic configuration on

system power-up.

Altera Corporation

125

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Multiple FLEX 10K devices can be configured in any of the five

configuration schemes by connecting the configuration enable (nCE) and

configuration enable output (nCEO) pins on each device.

Table 116. Data Sources for Configuration

Configuration Scheme

Data Source

Configuration device

EPC1, EPC2, EPC16, or EPC1441 configuration device

Passive serial (PS)

BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or

serial data source

Passive parallel asynchronous (PPA)

Passive parallel synchronous (PPS)

JTAG

Parallel data source

BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or

microprocessor with Jam STAPL file or Jam Byte-Code file

See the Altera web site (http://www.altera.com) or the Altera Digital

Library for pin-out information.

Device Pin-

Outs

The information contained in the FLEX 10K Embedded Programmable Logic

Device Family Data Sheet version 4.1 supersedes information published in

previous versions.

Revision

History

Version 4.1 Changes

ꢀ

Updated General Description section

Updated I/ O Element section

Updated SameFrame Pin-Outs section

Updated Figure 16

Updated Tables 13 and 116

Added Note 9 to Table 19

Added Note 10 to Table 24

Added Note 10 to Table 28

126

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Notes:

Altera Corporation

127

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

Altera, BitBlaster, ByteBlaster, ByteBlasterMV, ClockLock, ClockBoost, EPF10K10, EPF10K10A, EPF10K20,

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Applications Hotline:

(800) 800-EPLD

Customer Marketing:

(408) 544-7104

Literature Services:

(lit_req@altera.com

EPF10K30, EPF10K30A, EPF10K40, EPF10K50, EPF10K50V, EPF10K70, EPF10K100, EPF10K100A,

EPF10K130V, EPF10K250A, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, MAX,

MAX+PLUS, MAX+PLUS II, MultiVolt, Quartus, and Quartus II are trademarks and/ or service marks of

Altera Corporation in the United States and other countries. Altera products are protected under numerous

U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants

performance of its semiconductor products to current specifications in accordance with Altera’s standard

warranty, but reserves the right to make changes to any products and services at any time without notice.

Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by

Altera Corporation. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for

products or services

128

Altera Corporation

Printed on Recycled Paper.

Advanced Help

Results for: EPF10K*

296 part numbers found and 33 obsolete part numbers found

FLEX 10K Device Family (5.0V)

FLEX 10K/A Datasheet

Part Number Format

FLEX 10K Literature

Buying Altera Devices

Part Number

Device

Pins & Package Temperature Speeds Options

EPF10K10LC84-3

EPF10K10LC84-4

EPF10K10 84 pin PLCC

Pinout

Commercial

( 0 to 85°C)

-3, -4

None

EPF10K10LI84-4

EPF10K10 84 pin PLCC

Pinout

Industrial

( -40 to 100°C)

-4

EPF10K10QC208-3

EPF10K10QC208-4

EPF10K10 208 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

-4

EPF10K10QI208-4

EPF10K10 208 pin PQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K10TC144-3

EPF10K10TC144-4

EPF10K10 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

-4

EPF10K10TI144-4

EPF10K10 144 pin TQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K20RC208-3

EPF10K20RC208-4

EPF10K20 208 pin RQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

EPF10K20RC240-3

EPF10K20RC240-4

EPF10K20 240 pin RQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

-4

None

EPF10K20RI208-4

EPF10K20 208 pin RQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K20RI240-4

EPF10K20 240 pin RQFP

Pinout

Industrial

( -40 to 100°C)

-4

EPF10K20TC144-3

EPF10K20TC144-4

EPF10K20 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

-4

EPF10K20TI144-4

EPF10K20 144 pin TQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K30BC356-3

EPF10K30BC356-4

EPF10K30 356 pin BGA

Pinout

Commercial

( 0 to 85°C)

-3, -4

-4

EPF10K30RC208-3

EPF10K30RC208-4

EPF10K30 208 pin RQFP

Pinout

Commercial

( 0 to 85°C)

EPF10K30RC240-3

EPF10K30RC240-4

EPF10K30 240 pin RQFP

Pinout

Commercial

( 0 to 85°C)

EPF10K30RI208-4

EPF10K30 208 pin RQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K30RI240-4

EPF10K30 240 pin RQFP

Pinout

Industrial

( -40 to 100°C)

-4

EPF10K40RC208-3

EPF10K40RC208-4

EPF10K40 208 pin RQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

EPF10K40RC240-3

EPF10K40RC240-4

EPF10K40 240 pin RQFP

Pinout

Commercial

( 0 to 85°C)

EPF10K50BC356-3

EPF10K50BC356-4

EPF10K50 356 pin BGA

Pinout

Commercial

( 0 to 85°C)

EPF10K50GC403-3

EPF10K50GC403-4

EPF10K50 403 pin PGA

Pinout

Commercial

( 0 to 85°C)

EPF10K50RC240-3

EPF10K50RC240-4

EPF10K50 240 pin RQFP

Pinout

Commercial

( 0 to 85°C)

-3, -4

-4

None

EPF10K50RI240-4

EPF10K50 240 pin RQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K70GC503-3

EPF10K70GC503-4

EPF10K70 503 pin PGA

Pinout

Commercial

( 0 to 85°C)

-3, -4

EPF10K70RC240-2

EPF10K70RC240-3

EPF10K70RC240-4

EPF10K70 240 pin RQFP

Pinout

Commercial

( 0 to 85°C)

-2, -3, -4 None

EPF10K100GC503-3

EPF10K100GC503-3DX

EPF10K100GC503-4

EPF10K100 503 pin PGA

Pinout

Commercial

( 0 to 85°C)

-3, -4

DX: Has PLLs

FLEX 10KA Device Family (3.3V)

FLEX 10K/A Datasheet

Part Number Format

FLEX 10K Literature

Buying Altera Devices

Part Number

Device

Pins & Package Temperature Speeds

Options

EPF10K10AFC256-1

EPF10K10AFC256-2

EPF10K10AFC256-3

EPF10K10A 256 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

None

EPF10K10AQC208-1

EPF10K10AQC208-2

EPF10K10AQC208-3

EPF10K10A 208 pin PQFP

Pinout

Commercial

( 0 to 85°C)

None

EPF10K10AQI208-3

EPF10K10A 208 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-3

None

EPF10K10ATC100-1

EPF10K10ATC100-2

EPF10K10ATC100-3

EPF10K10A 100 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K10ATC144-1

EPF10K10ATC144-2

EPF10K10ATC144-3

EPF10K10A 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

None

EPF10K10ATI144-3

EPF10K10A 144 pin TQFP

Pinout

Industrial

( -40 to 100°C)

-3

None

EPF10K30ABC356-1

EPF10K30ABC356-2

EPF10K30ABC356-3

EPF10K30A 356 pin BGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K30ABI356-3

EPF10K30A 356 pin BGA

Pinout

Industrial

( -40 to 100°C)

-3

None

EPF10K30AFC256-1

EPF10K30AFC256-2

EPF10K30AFC256-3

EPF10K30A 256 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K30AFC484-1

EPF10K30AFC484-2

EPF10K30AFC484-3

EPF10K30A 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

None

EPF10K30AFI256-2

EPF10K30A 256 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K30AQC208-1

EPF10K30AQC208-2

EPF10K30AQC208-3

EPF10K30A 208 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K30AQC240-1

EPF10K30AQC240-2

EPF10K30AQC240-3

EPF10K30A 240 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

None

EPF10K30AQI208-3

EPF10K30A 208 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-3

None

EPF10K30AQI240-3

EPF10K30A 240 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-3

EPF10K30ATC144-1

EPF10K30ATC144-2

EPF10K30ATC144-3

EPF10K30A 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K30ATI144-3

EPF10K30A 144 pin TQFP

Pinout

Industrial

( -40 to 100°C)

-3

None

EPF10K50VBC356-1

EPF10K50VBC356-2

EPF10K50VBC356-3

EPF10K50VBC356-4

EPF10K50V 356 pin BGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3, -4 None

EPF10K50VBI356-3

EPF10K50VBI356-4

EPF10K50V 356 pin BGA

Pinout

Industrial

( -40 to 100°C)

-3, -4

None

EPF10K50VFC484-1

EPF10K50VFC484-2

EPF10K50VFC484-3

EPF10K50V 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K50VQC240-1

EPF10K50VQC240-2

EPF10K50VQC240-3

EPF10K50V 240 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3

-2

None

EPF10K50VQI240-2

EPF10K50V 240 pin PQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K50VRC240-1

EPF10K50VRC240-2

EPF10K50VRC240-3

EPF10K50VRC240-4

EPF10K50V 240 pin RQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3, -4 None

EPF10K50VRI240-3

EPF10K50VRI240-4

EPF10K50V 240 pin RQFP

Pinout

Industrial

( -40 to 100°C)

-3, -4

None

EPF10K100ABC356-1 EPF10K100A 356 pin BGA

EPF10K100ABC356-2

EPF10K100ABC356-3

Commercial

( 0 to 85°C)

-1, -2, -3

Pinout

EPF10K100ABC600-1 EPF10K100A 600 pin BGA

Commercial

( 0 to 85°C)

-1, -2, -3

-2, -3

None

EPF10K100ABC600-2

EPF10K100ABC600-3

Pinout

EPF10K100ABI356-2 EPF10K100A 356 pin BGA

EPF10K100ABI356-3 Pinout

Industrial

( -40 to 100°C)

EPF10K100ABI600-2 EPF10K100A 600 pin BGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K100AFC484-1 EPF10K100A 484 pin FBGA

Commercial

( 0 to 85°C)

-1, -2, -3

EPF10K100AFC484-2

EPF10K100AFC484-3

Pinout

EPF10K100ARC240-1 EPF10K100A 240 pin RQFP

Commercial

( 0 to 85°C)

-1, -2, -3

None

EPF10K100ARC240-2

EPF10K100ARC240-3

Pinout

EPF10K100ARI240-3 EPF10K100A 240 pin RQFP

Pinout

Industrial

( -40 to 100°C)

-3

None

EPF10K130VBC600-2 EPF10K130V 600 pin BGA

Commercial

( 0 to 85°C)

-2, -3, -4

EPF10K130VBC600-3

EPF10K130VBC600-4

Pinout

EPF10K130VGC599-2 EPF10K130V 599 pin PGA

Commercial

( 0 to 85°C)

-2, -3, -4

-1, -2, -3

None

EPF10K130VGC599-3

EPF10K130VGC599-4

Pinout

EPF10K250ABC600-1 EPF10K250A 600 pin BGA

Commercial

( 0 to 85°C)

EPF10K250ABC600-2

EPF10K250ABC600-3

Pinout

EPF10K250AGC599-1 EPF10K250A 599 pin PGA

Commercial

( 0 to 85°C)

EPF10K250AGC599-2

EPF10K250AGC599-3

Pinout

FLEX 10KE Device Family (2.5V)

FLEX 10KE Datasheet

Part Number Format

FLEX 10K Literature

Buying Altera Devices

Part Number

Device

Pins & Package Temperature Speeds Options

EPF10K30EFC256-1

EPF10K30EFC256-1X

EPF10K30EFC256-2

EPF10K30EFC256-2X

EPF10K30EFC256-3

EPF10K30E 256 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K30EFC484-1

EPF10K30EFC484-1X

EPF10K30EFC484-2

EPF10K30EFC484-2X

EPF10K30EFC484-3

EPF10K30E 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K30EFI256-2

EPF10K30E 256 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K30EQC208-1

EPF10K30EQC208-1X

EPF10K30EQC208-2

EPF10K30EQC208-2X

EPF10K30EQC208-3

EPF10K30E 208 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K30EQI208-2

EPF10K30E 208 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K30ETC144-1

EPF10K30ETC144-1X

EPF10K30ETC144-2

EPF10K30ETC144-2X

EPF10K30ETC144-3

EPF10K30E 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K30ETI144-2

EPF10K30E 144 pin TQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K50EFC256-1

EPF10K50EFC256-2

EPF10K50EFC256-3

EPF10K50E 256 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 None

EPF10K50EFC484-1

EPF10K50EFC484-2

EPF10K50EFC484-3

EPF10K50E 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K50EFI256-2

EPF10K50E 256 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K50EQC208-1

EPF10K50EQC208-2

EPF10K50EQC208-3

EPF10K50E 208 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 None

EPF10K50EQC240-1

EPF10K50EQC240-2

EPF10K50EQC240-3

EPF10K50E 240 pin PQFP

Pinout

Commercial

( 0 to 85°C)

EPF10K50EQI240-2

EPF10K50E 240 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K50ETC144-1

EPF10K50ETC144-2

EPF10K50ETC144-3

EPF10K50E 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 None

EPF10K50ETI144-2

EPF10K50E 144 pin TQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K50SBC356-1

EPF10K50SBC356-1X

EPF10K50SBC356-2

EPF10K50SBC356-2X

EPF10K50SBC356-3

EPF10K50S 356 pin BGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K50SFC256-1

EPF10K50SFC256-1X

EPF10K50SFC256-2

EPF10K50SFC256-2X

EPF10K50SFC256-3

EPF10K50S 256 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K50SFC484-1

EPF10K50SFC484-1X

EPF10K50SFC484-2

EPF10K50SFC484-2X

EPF10K50SFC484-3

EPF10K50S 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K50SFI484-2

EPF10K50S 484 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K50SQC208-1

EPF10K50SQC208-1X

EPF10K50SQC208-2

EPF10K50SQC208-2X

EPF10K50SQC208-3

EPF10K50S 208 pin PQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K50SQC240-1

EPF10K50SQC240-1X

EPF10K50SQC240-2

EPF10K50SQC240-2X

EPF10K50SQC240-3

EPF10K50S 240 pin PQFP

Pinout

Commercial

( 0 to 85°C)

EPF10K50SQI208-2

EPF10K50S 208 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K50STC144-1

EPF10K50STC144-1X

EPF10K50STC144-2

EPF10K50STC144-2X

EPF10K50STC144-3

EPF10K50S 144 pin TQFP

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K100EBC356-1 EPF10K100E 356 pin BGA

Commercial

( 0 to 85°C)

EPF10K100EBC356-1X

EPF10K100EBC356-2

EPF10K100EBC356-2X

EPF10K100EBC356-3

Pinout

EPF10K100EFC256-1

EPF10K100EFC256-1X

EPF10K100EFC256-2

EPF10K100EFC256-2X

EPF10K100EFC256-3

EPF10K100E 256 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K100EFC484-1

EPF10K100EFC484-1X

EPF10K100EFC484-2

EPF10K100EFC484-2X

EPF10K100EFC484-3

EPF10K100E 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K100EFI256-2

EPF10K100EFI484-2

EPF10K100E 256 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K100E 484 pin FBGA

Pinout

Industrial

( -40 to 100°C)

EPF10K100EQC208-1 EPF10K100E 208 pin PQFP

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K100EQC208-1X

EPF10K100EQC208-2

EPF10K100EQC208-2X

EPF10K100EQC208-3

Pinout

EPF10K100EQC240-1 EPF10K100E 240 pin PQFP

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K100EQC240-1X

EPF10K100EQC240-2

EPF10K100EQC240-2X

EPF10K100EQC240-3

Pinout

EPF10K100EQI208-2

EPF10K100E 208 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K100EQI240-2

EPF10K100E 240 pin PQFP

Pinout

Industrial

( -40 to 100°C)

EPF10K130EBC356-1 EPF10K130E 356 pin BGA

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K130EBC356-1X

EPF10K130EBC356-2

EPF10K130EBC356-2X

EPF10K130EBC356-3

Pinout

EPF10K130EBC600-1 EPF10K130E 600 pin BGA

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K130EBC600-1X

EPF10K130EBC600-2

EPF10K130EBC600-2X

EPF10K130EBC600-3

Pinout

EPF10K130EBI356-2

EPF10K130E 356 pin BGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K130EFC484-1

EPF10K130EFC484-1X

EPF10K130EFC484-2

EPF10K130EFC484-2X

EPF10K130EFC484-3

EPF10K130E 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K130EFC672-1

EPF10K130EFC672-1X

EPF10K130EFC672-2

EPF10K130EFC672-2X

EPF10K130EFC672-3

EPF10K130E 672 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K130EFI484-2

EPF10K130E 484 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K130EQC240-1 EPF10K130E 240 pin PQFP

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K130EQC240-1X

EPF10K130EQC240-2

EPF10K130EQC240-2X

EPF10K130EQC240-3

Pinout

EPF10K130EQI240-2

EPF10K130E 240 pin PQFP

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K200SBC356-1 EPF10K200S 356 pin BGA

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K200SBC356-1X

EPF10K200SBC356-2

EPF10K200SBC356-2X

EPF10K200SBC356-3

Pinout

EPF10K200SBC600-1 EPF10K200S 600 pin BGA

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K200SBC600-1X

EPF10K200SBC600-2

EPF10K200SBC600-2X

EPF10K200SBC600-3

Pinout

EPF10K200SBI356-2

EPF10K200S 356 pin BGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K200SFC484-1

EPF10K200SFC484-1X

EPF10K200SFC484-2

EPF10K200SFC484-2X

EPF10K200SFC484-3

EPF10K200S 484 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K200SFC672-1

EPF10K200SFC672-1X

EPF10K200SFC672-2

EPF10K200SFC672-2X

EPF10K200SFC672-3

EPF10K200S 672 pin FBGA

Pinout

Commercial

( 0 to 85°C)

EPF10K200SFI672-2

EPF10K200S 672 pin FBGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K200SRC240-1 EPF10K200S 240 pin RQFP

Commercial

( 0 to 85°C)

-1, -2, -3 X: Has PLLs

EPF10K200SRC240-1X

EPF10K200SRC240-2

EPF10K200SRC240-2X

EPF10K200SRC240-3

Pinout

EPF10K200EBC600-1 EPF10K200E 600 pin BGA

Commercial

( 0 to 85°C)

-1, -2, -3 None

EPF10K200EBC600-2

EPF10K200EBC600-3

Pinout

EPF10K200EBI600-2

EPF10K200E 600 pin BGA

Pinout

Industrial

( -40 to 100°C)

-2

None

EPF10K200EFC672-1

EPF10K200EFC672-2

EPF10K200EFC672-3

EPF10K200E 672 pin FBGA

Pinout

Commercial

( 0 to 85°C)

-1, -2, -3 None

EPF10K200EGC599-1 EPF10K200E 599 pin PGA

EPF10K200EGC599-2

EPF10K200EGC599-3

Commercial

( 0 to 85°C)

Pinout

Your search for EPF10K* found 33 obsolete part numbers.

Obsolete Part Numbers

Part Number Format

Buying Altera Devices

Part Number

Last Order Date

6/29/01

Last Ship Date

12/28/01

8/31/03

Replacement

Notes

EPF10K100BFC256-1

EPF10K100BFC256-2

EPF10K100BFC256-3

EPF10K100EFC256-1 PDN 0007

EPF10K100EFC256-2 PDN 0007

EPF10K100EFC256-3 PDN 0007

EPF10K100EQC208-1 PDN 0007

EPF10K100EQC208-2 PDN 0007

EPF10K100EQC208-3 PDN 0007

EPF10K100EQC240-1 PDN 0007

EPF10K100EQC240-2 PDN 0007

EPF10K100EQC240-3 PDN 0007

6/29/01

EPF10K100BQC208-1 6/29/01

EPF10K100BQC208-2 6/29/01

EPF10K100BQC208-3 6/29/01

EPF10K100BQC240-1 6/29/01

EPF10K100BQC240-2 6/29/01

EPF10K100BQC240-3 6/29/01

EPF10K100GC503-3

2/28/03

Contact Altera

PDN 0107

EPF10K100GC503-3DX 2/28/03

8/31/03

EPF10K100GC503-4

EPF10K100GC503-5

2/28/03

Order

8/31/03

Order

EPF10K100GC503-4 ADV 9615

EPF10K100GC503- EPF10K100GC503-

EPF10K10QC208-5

Order

EPF10K10QC208-4

ADV 9615

EPF10K10QC208-4 EPF10K10QC208-4

EPF10K130VBC600-2 2/28/03

EPF10K130VBC600-3 2/28/03

EPF10K130VBC600-4 2/28/03

EPF10K130VGC599-2 2/28/03

8/31/03

Contact Altera

PDN 0107

EPF10K130VGC599-3 2/28/03

EPF10K130VGC599-4 2/28/03

EPF10K200EGC599-1 2/28/03

EPF10K200EGC599-2 2/28/03

EPF10K200EGC599-3 2/28/03

EPF10K250AGC599-1 2/28/03

EPF10K250AGC599-2 2/28/03

EPF10K250AGC599-3 2/28/03

8/31/03

Order

Contact Altera

EPF10K30RC208-4

PDN 0107

ADV 9615

Please Give Us Feedback

EPF10K30RC208-5

Order

EPF10K30RC208-4 EPF10K30RC208-4

EPF10K50GC403-3

EPF10K50GC403-4

EPF10K50GC403-5

EPF10K50RC240-5

EPF10K70GC503-3

EPF10K70GC503-4

2/28/03

3/31/97

2/28/02

8/31/03

6/30/97

8/31/02

Contact Altera

PDN 0107

ADV 9623

PDN 0107

Contact Altera

EPF10K50GC403-4

EPF10K50RC240-4

Contact Altera

EPF10K*

Advanced Help

EPF10K30ABC356-2N [INTEL]

相关型号：

EPF10K30ABC356-3

EPF10K30ABC484-2

EPF10K30ABI256-2

EPF10K30ABI484-1

EPF10K30AFC256-2

EPF10K30AFC256-3

EPF10K30AFC256-3N

EPF10K30AFC484-1N

EPF10K30AFC484-2

EPF10K30AFC484-2N

EPF10K30AFC484-3N

EPF10K30AFI256-3