F28F008SA-L200 [INTEL]
Flash, 1MX8, 200ns, PDSO40, 10 X 20 MM, 1.20 MM HEIGHT, REVERSE, TSOP-40;
| 型号： | F28F008SA-L200 |
| 厂家： | 
INTEL |
| 描述： | Flash, 1MX8, 200ns, PDSO40, 10 X 20 MM, 1.20 MM HEIGHT, REVERSE, TSOP-40 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28F008SA-L
8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY
Y
Y
High-Density Symmetrically-Blocked
Architecture
Ð Sixteen 64-Kbyte Blocks
High-Performance Read
Ð 200 ns Maximum Access Time
Y
Deep Power-Down Mode
Typical
CC
Y
Y
Low-Voltage Operation
Ð 0.20 mA I
b
g g
3.3V 0.3V or 5.0V 10% V
CC
Ð
Y
Y
SRAM-Compatible Write Interface
Extended Cycling Capability
Ð 10,000 Block Erase Cycles
Ð 160,000 Block Erase
Cycles per Chip
Hardware Data Protection Feature
Ð Erase/Write Lockout during Power
Transitions
Y
Y
Industry Standard Packaging
Ð 40-Lead TSOP, 44-Lead PSOP
Y
Y
Automated Byte Write and Block Erase
Ð Command User Interface
Ð Status Register
ETOXTM III Nonvolatile Flash
Technology
Ð 12V Byte Write/Block Erase
System Performance Enhancements
Ý
Ð RY/BY Status Output
Ð Erase Suspend Capability
Intel’s 28F008SA-L 8 Mbit FlashFileTM Memory is the highest density nonvolatile read/write solution for solid-
state storage. The 28F008SA-L’s extended cycling, symmetrically-blocked architecture, fast access time, write
automation and very low power consumption provide a more reliable, lower power, lighter weight and higher
performance alternative to traditional rotating disk technology. The 28F008SA-L brings new capabilities to
portable computing. Application and operating system software stored in resident flash memory arrays provide
instant-on, rapid execute-in-place and protection from obsolescence through in-system software updates.
Resident software also extends system battery life and increases reliability by reducing disk drive accesses.
For high-density data acquisition applications, the 28F008SA-L offers a more cost-effective and reliable alter-
native to SRAM and battery. Traditional high-density embedded applications, such as telecommunications,
can take advantage of the 28F008SA-L’s nonvolatility, blocking and minimal system code requirements for
flexible firmware and modular software designs.
The 28F008SA-L is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages. Pin assign-
ments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write. The 28F008SA-L memory map consists of 16 separately erasable 64-Kbyte blocks.
Intel’s 28F008SA-L employs advanced CMOS circuitry for systems requiring low power consumption and
noise immunity. Its 200 ns access time provides superior performance when compared with magnetic storage
media. A deep power-down mode lowers power consumption to 0.66 mW typical thru V , crucial in portable
CC
computing, handheld instrumentation and other low-power applications. The RP power control input also
provides absolute data protection during system power-up/down.
Ý
Manufactured on Intel’s 0.8 micron ETOX process, the 28F008SA-L provides the highest levels of quality,
reliability and cost-effectiveness.
*Other brands and names are property of their respective owners.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
December 1995
Order Number: 290435-005
28F008SA-L
The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation.
PRODUCT OVERVIEW
The 28F008SA-L is
a
(8,388,608-bit) memory organized as
high-performance 8-Mbit
Mbyte
1
Ý
The RY/BY output gives an additional indicator of
(1,048,576 bytes) of 8 bits each. Sixteen 64-Kbyte
(65,536-byte) blocks are included on the
28F008SA-L. A memory map is shown in Figure 6 of
this specification. A block erase operation erases
one of the sixteen blocks of memory in typically 2.0
seconds, independent of the remaining blocks.
Each block can be independently erased and written
10,000 cycles. Erase Suspend mode allows sys-
tem software to suspend block erase to read data or
execute code from any other block of the
28F008SA-L.
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
Ý
for example). Status polling using RY/BY mini-
mizes both CPU overhead and system power con-
Ý
sumption. When low, RY/BY indicates that the
WSM is performing a block erase or byte write oper-
Ý
ation. RY/BY high indicates that the WSM is ready
for new commands, block erase is suspended or the
device is in deep powerdown mode.
Maximum access time is 200 ns (t
) over the
The 28F008SA-L is available in the 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and 44-
lead PSOP (Plastic Small Outline) packages. Pin-
outs are shown in Figures 2 and 4 of this specifica-
tion.
ACC
a
commercial temperature range (0 C to 70 C) and
supply voltage range (3.0V to 3.6V and
§
§
over V
CC
4.5V to 5.5V). I
5
3.3V 0.3V.
active current (CMOS Read) is
mA typical, 12 mA maximum at 5 MHz,
g
CC
The Command User Interface serves as the inter-
face between the microprocessor or microcontroller
and the internal operation of the 28F008SA-L.
Ý
Ý
When the CE and RP pins are at V , the I
CMOS Standby mode is enabled.
CC
CC
A Deep Powerdown mode is enabled when the
Ý
Byte Write and Block Erase Automation allow
byte write and block erase operations to be execut-
ed using a two-write command sequence to the
Command User Interface. The internal Write State
Machine (WSM) automatically executes the algo-
rithms and timings necessary for byte write and
block erase operations, including verifications,
thereby unburdening the microprocessor or micro-
controller. Writing of memory data is performed in
RP pin is at GND, minimizing power consumption
and providing write protection. I current in deep
CC
powerdown is 0.20 mA typical. Reset time of 500 ns
Ý
is required from RP switching high until outputs are
valid to read attempts. Equivalently, the device has a
Ý
wake time of 1 ms from RP high until writes to the
Command User Interface are recognized by the
Ý
28F008SA-L. With RP at GND, the WSM is reset
and the Status Register is cleared.
byte increments typically within 11 ms, I
byte
write and block erase currents are 10 mA typical,
PP
30 mA maximum. V byte write and block erase
PP
voltage is 11.4V to 12.6V.
2
28F008SA-L
Figure 1. Block Diagram
3
28F008SA-L
Symbol
Table 1. Pin Description
Name and Function
Type
A –A
0
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
19
DQ –DQ
0
INPUT/OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.
7
Ý
Ý
CE
RP
INPUT
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers,
Ý
Ý
decoders, and sense amplifiers. CE is active low; CE high deselects
the memory device and reduces power consumption to standby levels.
RESET/ DEEP POWERDOWN: Puts the device in deep powerdown
Ý
Ý
Ý
mode. RP is active low; RP high gates normal operation. RP also
locks out block erase or byte write operations when active low, providing
Ý
data protection during power transitions. RP active resets internal
automation. Exit from Deep Powerdown sets device to read-array mode.
Ý
OE
INPUT
INPUT
OUTPUT ENABLE: Gates the device’s outputs through the data buffers
Ý
during a read cycle. OE is active low.
Ý
WE
WRITE ENABLE: Controls writes to the Command User Interface and
Ý
array blocks. WE is active low. Addresses and data are latched on the
rising edge of the WE pulse.
Ý
Ý
Ý
READY/BUSY : Indicates the status of the internal Write State
Machine. When low, it indicates that the WSM is performing a block
RY/BY
OUTPUT
Ý
erase or byte write operation. RY/BY high indicates that the WSM is
ready for new commands, block erase is suspended or the device is in
Ý
deep powerdown mode. RY/BY is always active and does NOT float
to tri-state off when the chip is deselected or data outputs are disabled.
V
V
BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of
the array or writing bytes of each block.
NOTE:
PP
CC
k
With V
V
, memory contents cannot be altered.
PPLMAX
PP
g
g
DEVICE POWER SUPPLY (3.3V 0.3V, 5V 10%)
GROUND
GND
4
28F008SA-L
Standard Pinout
290435–2
Reverse Pinout
290435–3
Figure 2. TSOP Lead Configurations
5
28F008SA-L
Figure 3. TSOP Serpentine Layout
NOTE:
1. Connect all V
disconnected.
and GND pins of each device to common power supply outputs. DO NOT leave V
or GND inputs
CC
CC
6
28F008SA-L
290435–5
Figure 4. PSOP Lead Configuration
290435–6
Figure 5. 28F008SA-L Array Interface to Intel3.3V 80L186EB Embedded Microprocessor
7
28F008SA-L
PRINCIPLES OF OPERATION
FFFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-byte Block
The 28F008SA-L includes on-chip write automation
to manage write and erase functions. The Write
State Machine allows for: 100% TTL-level control
inputs; fixed power supplies during block erasure
and byte write; and minimal processor overhead with
RAM-like interface timings.
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
28F008SA-L functions as a read-only memory. Ma-
nipulation of external memory-control pins allow ar-
ray read, standby and output disable operations.
Both Status Register and intelligent identifiers can
also be accessed through the Command User Inter-
B0000
AFFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
A0000
9FFFF
90000
8FFFF
e
face when V
V
PPL
.
PP
80000
7FFFF
This same subset of operations is also available
when high voltage is applied to the V pin. In addi-
70000
6FFFF
PP
tion, high voltage on V enables successful block
PP
erasure and byte writing of the device. All functions
associated with altering memory contentsÐbyte
write, block erase, status and intelligent identifierÐ
are accessed via the Command User Interface and
verified thru the Status Register.
60000
5FFFF
50000
4FFFF
40000
3FFFF
Commands are written using standard microproces-
sor write timings. Command User Interface contents
serve as input to the WSM, which controls the block
erase and byte write circuitry. Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations. With the appropriate com-
mand written to the register, standard microproces-
sor read timings output array data, access the Intelli-
gent Identifier codes, or output byte write and block
erase status for verification.
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
Figure 6. Memory Map
Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the 28F008SA-L blocks. This code is copied
to, and executed from, system RAM during actual
flash memory update. After successful completion of
byte write and/or block erase, code/data reads from
the 28F008SA-L are again possible via the Read Ar-
ray command. Erase suspend/resume capability al-
lows system software to suspend block erase to
read data and execute code from any other block.
Command User Interface and Write
Automation
An on-chip state machine controls block erase and
byte write, freeing the system processor for other
tasks. After receiving the Erase Setup and Erase
Confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
Ý
via the Status Register and RY/BY output. Byte
write is similarly controlled, after destination address
and expected data are supplied. The program and
erase algorithms of past Intel flash memories are
now regulated by the state machine, including pulse
repetition where required and internal verification
and margining of data.
8
28F008SA-L
The first task is to write the appropriate read mode
command to the Command User Interface (array, In-
telligent Identifier, or Status Register). The
28F008SA-L automatically resets to Read Array
mode upon initial device powerup or after exit from
deep powerdown. The 28F008SA-L has four control
pins, two of which must be logically active to obtain
Data Protection
Depending on the application, the system designer
may choose to make the V power supply switcha-
PP
ble (available only when memory byte writes/block
erases are required) or hardwired to V
e
. When
PPH
, memory contents cannot be altered.
V
PP
V
PPL
Ý
data at the outputs. Chip Enable (CE ) is the device
selection control, and when active enables the se-
The 28F008SA-L Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
Ý
lected memory device. Output Enable (OE ) is the
data input/output (DQ –DQ ) direction control, and
applied to V . Additionally, all functions are dis-
PP
abled whenever V is below the write lockout volt-
0
7
when active drives data from the selected memory
CC
Ý
Ý
onto the I/O bus. RP and WE must also be at
. Figure 10 illustrates read bus cycle waveforms.
Ý
, or when RP is at V . The 28F008SA-L
IL
age V
LKO
V
IH
accommodates either design practice and encour-
ages optimization of the processor-memory inter-
face.
Output Disable
The two-step byte write/block erase Command User
Interface write sequence provides additional soft-
ware write protection.
Ý
With OE at a logic-high level (V ), the device out-
puts are disabled. Output pins (DQ –DQ ) are
placed in a high-impedance state.
IH
0
7
BUS OPERATION
Standby
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Ý
CE
at a logic-high level (V ) places the
IH
28F008SA-L in standby mode. Standby operation
disables much of the 28F008SA-L’s circuitry and
substantially reduces device power consumption.
The outputs (DQ –DQ ) are placed in a high-impe-
7
0
Ý
dence state independent of the status of OE . If the
28F008SA-L is deselected during block erase or
byte write, the device will continue functioning and
consuming normal active power until the operation
completes.
Read
The 28F008SA-L has three read modes. The memo-
ry can be read from any of its blocks, and informa-
tion can be read from the Intelligent Identifier or
Status Register. V can be at either V
PP
or V
.
PPH
PPL
Table 2. Bus Operations
Ý
Ý
Ý
Ý
Ý
Mode
Notes
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
RP
CE
OE
WE
A
V
DQ
RY/BY
0
PP
0–7
Read
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
D
X
X
X
IH
IL
IL
IH
IH
OUT
Output Disable
V
IH
X
X
X
High Z
High Z
High Z
89H
IH
IH
IL
Standby
V
X
X
IH
Deep PowerDown
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
V
X
X
X
V
V
V
IL
IH
IH
IH
OH
OH
1, 2
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IH
IH
IH
IL
1, 2
V
V
V
A1H
IH
OH
X
1, 2, 3, 4, 5
V
V
X
D
IN
IL
NOTES:
1. Refer to DC Characteristics. When V
e
2. X can be V or V for control pins and addresses, and V
V
PPL
, memory contents can be read but not written or erased.
for V . See DC Characteristics for V
PP
PP
or V
and V
PPL PPH
IL IH
PPL
PPH
voltages.
Ý
3. RY/BY is V when the Write State Machine is executing internal block erase or byte write algorithms. It is V
OL
the WSM is not busy, in Erase Suspend mode or deep powerdown mode.
when
OH
e
4. Command writes involving block erase or byte write are only successfully executed when V
5. Refer to Table 3 for valid D during a write operation.
IN
V
PPH
.
PP
9
28F008SA-L
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization fol-
Deep Power-Down
The 28F008SA-L offers a deep power-down feature,
Ý
entered when RP is at V . Current draw thru V
IL
CC
is 0.20 mA typical in deep powerdown mode, with
current draw through V typically 0.1 mA. During
PP
Ý
input. In this application RP is controlled by the
lowing a system reset through the use of the RP
Ý
same RESET signal that resets the system CPU.
Ý
read modes, RP -low deselects the memory,
places output drivers in a high-impedence state and
turns off all internal circuits. The 28F008SA-L re-
Ý
quires time t
(see AC Characteristics-Read-
PHQV
Only Operations) after return from powerdown until
initial memory access outputs are valid. After this
wakeup interval, normal operation is restored. The
Command User Interface is reset to Read Array, and
the upper 5 bits of the Status Register are cleared to
value 10000, upon return to normal operation.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manu-
facturer code, 89H; and the device code, A2H for
the 28F008SA-L. The system CPU can then auto-
matically match the device with its proper block
erase and byte write algorithms.
Ý
During block erase or byte write modes, RP low
will abort either operation. Memory contents of the
block being altered are no longer valid as the data
The manufacturer- and device-codes are read via
the Command User Interface. Following a write of
90H to the Command User Interface, a read from
address location 00000H outputs the manufacturer
code (89H). A read from address 00001H outputs
the device code (A2H). It is not necessary to have
will be partially written or erased. Time t after
PHWL
RP goes to logic-high (V ) is required before an-
Ý
other command can be written.
IH
Ý
This use of RP during system reset is important
high voltage applied to V to read the Intelligent
PP
Identifiers from the Command User Interface.
with automated write/erase devices. When the sys-
tem come out of reset, it expects to read from the
flash memory. Automated flash memories provide
Table 3. Command Definitions
Bus
First Bus Cycle
Second Bus Cycle
Command
Cycles Notes
Req’d
Operation Address Data Operation Address Data
Read Array/Reset
1
3
2
1
2
2
2
2
1
2, 3, 4
3
Write
Write
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
B0H
40H
10H
Intelligent Identifier
Read
Read
IA
X
IID
Read Status Register
X
SRD
Clear Status Register
X
Erase Setup/Erase Confirm
Erase Suspend/Erase Resume
Byte Write Setup/Write
Alternate Byte Write Setup/Write
2
BA
X
Write
Write
Write
Write
BA
X
D0H
D0H
WD
2, 3, 5
2, 3, 5
WA
WA
WA
WA
WD
NOTES:
1. Bus operations are defined in Table 2.
e
2. IA
BA
WA
Identifier Address: 00H for manufacturer code, 01H for device code.
Address within the block being erased.
e
e
3. SRD
Address of memory location to be written.
Data read from Status Register. See Table 4 for a description of the Status Register bits.
e
e
WD
e
IID
Ý
Data to be written at location WA. Data is latched on the rising edge of WE .
Data read from Intelligent Identifiers.
4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.
5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
6. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
10
28F008SA-L
Write
COMMAND DEFINITIONS
Writes to the Command User Interface enable read-
ing of device data and Intelligent Identifiers. They
also control inspection and clearing of the Status
When V
is applied to the V
pin, read opera-
PP
PPL
tions from the Status Register, Intelligent Identifiers,
or array blocks are enabled. Placing V on V
PPH
PP
e
Register. Additionally, when V
V
, the Com-
PPH
enables successful byte write and block erase oper-
ations as well.
PP
mand User Interface controls block erasure and byte
write. The contents of the interface register serve as
input to the internal state machine.
Device operations are selected by writing specific
commands into the Command User Interface. Table
3 defines the 28F008SA-L commands.
The Command User Interface itself does not occupy
an addressable memory location. The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command. Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased. The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written, while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written.
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the 28F008SA-L defaults to
Read Array mode. This operation is also initiated by
writing FFH into the Command User Interface. Mi-
croprocessor read cycles retrieve array data. The
device remains enabled for reads until the Com-
mand User Interface contents are altered. Once the
internal Write State Machine has started a block
erase or byte write operation, the device will not rec-
ognize the Read Array command, until the WSM has
completed its operation. The Read Array command
The Command User Interface is written by bringing
Ý
WE to a logic-low level (V ) while CE is low.
Addresses and data are latched on the rising edge
Ý
of WE . Standard microprocessor write timings are
used.
Ý
IL
e
is functional when V
V
or V
.
PPH
PP
PPL
Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations, Figure 11, for specific
timing parameters.
Intelligent Identifier Command
The 28F008SA-L contains an Intelligent Identifier
operation, initiated by writing 90H into the Command
Table 4. Status Register Definitions
WSMS
7
ESS
6
ES
BWS
VPPS
R
R
1
R
0
5
4
3
2
e
e
e
e
e
e
e
e
e
SR.7
WRITE STATE MACHINE STATUS
Ready
Busy
NOTES:
1
0
Ý
RY/BY or the Write State Machine Status bit must first
be checked to determine byte write or block erase com-
pletion, before the Byte Write or Erase Status bit are
checked for success.
SR.6
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress/Completed
1
0
If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt, an improper command se-
quence was entered. Attempt the operation again.
SR.5
ERASE STATUS
Error in Block Erasure
Successful Block Erase
1
0
If V low status is detected, the Status Register must be
PP
e
e
e
e
e
e
SR.4
BYTE WRITE STATUS
Error in Byte Write
Successful Byte Write
cleared before another byte write or block erase opera-
tion is attempted.
1
0
The V
PP
Status bit, unlike an A/D converter, does not
provide continuous indication of V level. The WSM in-
SR.3
V
PP
V
PP
V
PP
e
STATUS
Low Detect; Operation Abort
OK
PP
1
0
terrogates the V level only after the byte write or block
PP
erase command sequences have been entered and in-
forms the system if V has not been switched on. The
V
PP
Status bit is not guaranteed to report accurate feed-
SR.2–SR.0
RESERVED FOR FUTURE
ENHANCEMENTS
PP
back between V
and V
.
PPH
PPL
These bits are reserved for future use and
should be masked out when polling the Status
Register.
11
28F008SA-L
User Interface. Following the command write, a read
cycle from address 00000H retrieves the manufac-
turer code of 89H. A read cycle from address
00001H returns the device code of A1H. To termi-
nate the operation, it is necessary to write another
valid command into the register. Like the Read Array
command, the Intelligent Identifier command is func-
Interface, followed by the Erase Confirm command
(D0H). These commands require both appropriate
sequencing and an address within the block to be
erased to FFH. Block preconditioning, erase and
verify are all handled internally by the Write State
Machine, invisible to the system. After the two-com-
mand erase sequence is written to it, the 28F008SA-L
automatically outputs Status Register data when
read (see Figure 8; Block Erase Flowchart). The
CPU can detect the completion of the erase event
e
tional when V
V
PPL
or V
.
PP
PPH
Ý
by analyzing the output of the RY/BY pin, or the
WSM Status bit of the Status Register.
Read Status Register Command
The 28F008SA-L contains a Status Register which
may be read to determine when a byte write or block
erase operation is complete, and whether that oper-
ation completed successfully. The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In-
terface. After writing this command, all subsequent
read operations output data from the Status Regis-
ter, until another valid command is written to the
Command User Interface. The contents of the
Status Register are latched on the falling edge of
When erase is completed, the Erase Status bit
should be checked. If erase error is detected, the
Status Register should be cleared. The Command
User Interface remains in Read Status Register
mode until further commands are issued to it.
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased. Also, reliable block erasure can only
e
voltage, memory contents are protected against era-
occur when V
V
. In the absence of this high
PPH
PP
Ý
Ý
OE or CE , whichever occurs last in the read cy-
cle. OE or CE must be toggled to V before
Ý
Ý
e
the V Status bit will be set to ‘‘1’’. Erase attempts
sure. If block erase is attempted while V
V
,
IH
PP
PPL
further reads to update the Status Register latch.
The Read Status Register command functions when
PP
while V
k
k
and should not be attempted.
V
V
produce spurious results
PPL
PP
PPH
e
V
PP
V
PPL
or V
.
PPH
Clear Status Register Command
Erase Suspend/Erase Resume
Commands
The Erase Status and Byte Write Status bits are set
to ‘‘1’’s by the Write State Machine and can only be
reset by the Clear Status Register Command. These
bits indicate various failure conditions (see Table 4).
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively writing several bytes or eras-
ing multiple blocks in sequence). The Status Regis-
ter may then be polled to determine if an error oc-
curred during that sequence. This adds flexibility to
the way the device may be used.
The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory. Once the erase process starts, writing
the Erase Suspend command (B0H) to the Com-
mand User Interface requests that the WSM sus-
pend the erase sequence at a predetermined point
in the erase algorithm. The 28F008SA-L continues
to output Status Register data when read, after the
Erase Suspend command is written to it. Polling the
WSM Status and Erase Suspend Status bits will de-
termine when the erase operation has been sus-
Additionally, the V Status bit (SR.3) MUST be re-
PP
Ý
pended (both will be set to ‘‘1’’). RY/BY will also
set by system software before further byte writes or
block erases are attempted. To clear the Status
Register, the Clear Status Register command (50H)
is written to the Command User Interface. The Clear
transition to V
.
OH
At this point, a Read Array command can be written
to the Command User Interface to read data from
blocks other than that which is suspended. The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H), at which
time the WSM will continue with the erase process.
The Erase Suspend Status and WSM Status bits of
the Status Register will be automatically cleared and
e
Status Register command is functional when V
.
PPH
PP
V
or V
PPL
Erase Setup/Erase Confirm
Commands
Ý
RY/BY will return to V . After the Erase Resume
OL
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command User
command is written to it, the 28F008SA-L automati-
cally outputs Status Register data when read (see
Figure 9; Erase Suspend/Resume Flowchart). V
PP
must remain at V
Erase Suspend.
while the 28F008SA-L is in
PPH
12
28F008SA-L
bits. Figure 7 shows a system software flowchart for
device byte write. The entire sequence is performed
Byte Write Setup/Write Commands
(40H or 10H)
Ý
. Byte write abort occurs when RP
with V at V
PP
PPH
transitions to V , or V drops to V
Byte write is executed by a two-command sequence.
The Byte Write Setup command (40H or 10H) is writ-
ten to the Command User Interface, followed by a
second write specifying the address and data
. Although the
PPL
IL
PP
WSM is halted, byte data is partially written at the
location where byte write was aborted. Block era-
sure, or a repeat of byte write, is required to initialize
this data to a known value.
Ý
(latched on the rising edge of WE ) to be written.
The WSM then takes over, controlling the byte write
and write verify algorithms internally. After the two-
command byte write sequence is written to it, the
28F008SA-L automatically outputs Status Register
data when read (see Figure 7; Byte Write Flowchart).
The CPU can detect the completion of the byte write
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally, includ-
ing all preconditioning of block data. WSM opera-
tion, erase success and V high voltage presence
Ý
PP
are monitored and reported through RY/BY and
Ý
event by analyzing the output of the RY/BY pin, or
the WSM Status bit of the Status Register. Only the
Read Status Register command is valid while byte
write is active.
the Status Register. Additionally, if a command other
than Erase Confirm is written to the device following
Erase Setup, both the Erase Status and Byte Write
Status bits will be set to ‘‘1’’s. When issuing the
Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 8 shows a
system software flowchart for block erase.
When byte write is complete, the Byte Write Status
bit should be checked. If byte write error is detected,
the Status Register should be cleared. The internal
WSM verify only detects errors for ‘‘1’’s that do not
successfully write to ‘‘0’’s. The Command User In-
terface remains in Read Status Register mode until
further commands are issued to it. If byte write is
Erase typically takes 2.0 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 9.
e
be set to ‘‘1’’. Byte write attempts while V
attempted while V
V
, the V Status bit will
PP
PPL PP
k
produce spurious results and should not be
V
PP
PPL
k
attempted.
V
PPH
The entire sequence is performed with V at V
PP PPH
Abort occurs when RP transitions to V or V
.
EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING
Ý
, while erase is in progress. Block data is
IL
PP
falls to V
PPL
Intel has designed extended cycling capability into
its ETOX flash memory technologies. The
28F008SA-L is designed for 10,000 byte write/block
erase cycles on each of the sixteen 64-Kbyte
blocks. Low electric fields, advanced oxides and
minimal oxide area per cell subjected to the tunnel-
ing electric field combine to greatly reduce oxide
stress and the probability of failure. A 20-Mbyte sol-
id-state drive using an array of 28F008SA-Ls has a
MTBF (Mean Time Between Failure) of 3.33 million
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
DESIGN CONSIDERATIONS
Three-Line Output Control
The 28F008SA-L will often be used in large memory
arrays. Intel provides three control inputs to accom-
modate multiple memory connections. Three-line
control provides for:
(1)
hours , over 60 times more reliable than equivalent
rotating disk technology.
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
AUTOMATED BYTE WRITE
The 28F008SA-L integrates the Quick-Pulse pro-
gramming algorithm of prior Intel Flash Memory de-
vices on-chip, using the Command User Interface,
Status Register and Write State Machine (WSM).
On-chip integration dramatically simplifies system
software and provides processor interface timings to
the Command User Interface and Status Register.
WSM operation, internal verify and V high voltage
PP
presence are monitored and reported via the
Ý
RY/BY output and appropriate Status Register
To efficiently use these control inputs, an address
Ý
Ý
decoder should enable CE , while OE should be
connected to all memory devices and the system’s
Ý
READ control line. This assures that only selected
memory devices have active outputs while deselect-
Ý
ed memory devices are in Standby Mode. RP
should be connected to the system Powergood sig-
nal to prevent unintended writes during system pow-
er transitions. Powergood should also toggle during
system reset.
(1)
e
20 million file writes.
Assumptions: 10-Kbyte file written every 10 minutes. (20-Mbyte array)/(10-Kbyte file)
(2000 files writes/erase)
2,000 file writes before erase required.
c
(10 min/write)
e
10 MTBF.
(10,000 cycles per 28F008SA-L block)
e
6
10 file writes)
6
c
c
c
c
(20
(1 hr/60 min)
3.33
13
28F008SA-L
28F008SA-L, and returns to V
when the WSM
OH
has finished executing the internal algorithm.
Ý
RY/BY and Byte Write/Block Erase
Polling
Ý
RY/BY can be connected to the interrupt input of
the system CPU or controller. It is active at all times,
Ý
RY/BY is a full CMOS output that provides a hard-
ware method of detecting byte write and block erase
completion. It transitions low time t after a
WHRL
write or erase command sequence is written to the
Ý
Ý
not tristated if the 28F008SA-L CE or OE inputs
when the
Ý
are brought to V . RY/BY is also V
IH
OH
device is in Erase Suspend or deep powerdown
modes.
Bus
Command
Comments
Operation
e
Address
Write
Byte Write Data
40H (10H)
e
Byte to be written
Setup
Write
Byte Write Data to be written
e
Address
Byte to be written
Ý
Ready, V
or
Standby/Read
Check RY/BY
e
e
Busy
V
OH
OL
Read Status Register
Check SR.7
e
Toggle OE or CE to
e
Busy
1
Ready, 0
Ý
Ý
update Status Register
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
290435–13
Write FFH after the last byte write operation to reset the
device to Ready Array Mode
FULL STATUS CHECK PROCEDURE
Bus
Command
Comments
Operation
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Standby
Check SR.3
e
1
V
PP
Low Detect
Check SR.4
e
1
Byte Write Error
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
290435–14
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 7. Automated Byte Write Flowchart
14
28F008SA-L
Bus
Command
Comments
Operation
e
20H
Write
Erase
Setup
Data
e
Address
erased
Within block to be
e
D0H
Write
Erase
Data
e
Address
erased
Within block to be
Ý
Ready, V
or
Standby/Read
Check RY/BY
e
e
Busy
V
OH
OL
Read Status Register
Check SR.7
e
Toggle OE or CE to
e
Busy
1
Ready, 0
Ý
Ý
update Status Register
Repeat for subsequent bytes
Full status check can be done after each block or after a
sequence of blocks
290435–15
Write FFH after the last block erase operation to reset the
device to Ready Array Mode
FULL STATUS CHECK PROCEDURE
Bus
Command
Comments
Operation
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
Standby
Standby
Check SR.3
e
1
V
PP
Low Detect
Check SR.4,5
e
Both 1
Error
Command Sequence
Check SR.5
e
1
Block Erase Error
SR.3 MUST be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine
290435–16
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 8. Automated Block Erase Flowchart
15
28F008SA-L
Bus
Command
Comments
Operation
e
e
Write
Write
Erase
Data
Data
B0H
Suspend
Read
70H
Status Register
Ý
Check RY/BY
Standby/
Read
e
e
V
V
Ready,
Busy
OH
OL
or
Read Status Register
Check SR.7
e
Toggle OE or CE to
e
Busy
1
Ready, 0
Ý
Ý
Update Status Register
Standby
Write
Check SR.6
e
1
Suspended
e
FFH
Read Array
Data
Read
Write
Read array data from block
other than that being
erased.
e
Erase Resume Data
D0H
290435–17
Figure 9. Erase Suspend/Resume Flowchart
every 8 devices, a 4.7 mF electrolytic capacitor
should be placed at the array’s power supply con-
Power Supply Decoupling
nection between V
will overcome voltage slumps caused by PC board
trace inductances.
and GND. The bulk capacitor
Flash memory power switching characteristics re-
quire careful device decoupling. System designers
are interested in 3 supply current issues; standby
CC
current levels (I ), active current levels (I ) and
SB
CC
transient peaks produced by falling and rising edges
Ý
of CE . Transient current magnitudes depend on
V
Trace on Printed Circuit Boards
PP
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 mF ceramic capacitor
Writing flash memories, while they reside in the tar-
get system, requires that the printed circuit board
designer pay attention to the V power supply
PP
trace. The V pin supplies the memory cell current
PP
for writing and erasing. Use similar trace widths and
connected between each V
and GND, and be-
tween its V and GND. These high frequency, low
CC
PP
layout considerations given to the V power bus.
CC
Adequate V supply traces and decoupling will de-
inherent-inductance capacitors should be placed as
close as possible to package leads. Additionally, for
PP
crease V voltage spikes and overshoots.
PP
16
28F008SA-L
28F008SA-L ensures that the Command User Inter-
face is reset to the Read Array mode on power up.
Ý
, V , RP Transitions and the
Command/Status Registers
V
CC PP
A system designer must guard against spurious
when V
Byte write and block erase completion are not guar-
. If the V Status bit
writes for V
voltages above V
Ý
is
CC
LKO
PP
anteed if V drops below V
PP
PPH
PP
Ý
active. Since both WE and CE must be low for a
command write, driving either to V will inhibit
of the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further byte write/block erase attempts are allowed
by the WSM. Otherwise, the Byte Write (SR.4) or
Erase (SR.5) Status bits of the Status Register will
IH
writes. The Command User Interface architecture
provides an added level of protection since altera-
tion of memory contents only occurs after success-
ful completion of the two-step command sequences.
Ý
be set to ‘‘1’’s if error is detected. RP transitions to
during byte write and block erase also abort the
V
IL
Ý
Finally, the device is disabled until RP is brought to
, regardless of the state of its control inputs. This
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device poweroff, or
V
IH
provides an additional level of memory protection.
Ý
RP transitions to V , clear the Status Register to
initial value 10000 for the upper 5 bits.
IL
Power Dissipation
The Command User Interface latches commands as
issued by system software and is not altered by V
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us-
able battery life, because the 28F008SA-L does not
consume any power to retain code or data when the
system is off.
PP
Ý
or CE transitions or WSM actions. Its state upon
powerup, after exit from deep powerdown or after
V
CC
transitions below V
, is Read Array Mode.
LKO
After byte write or block erase is complete, even
after V transitions down to V , the Command
PP
PPL
User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired.
In addition, the 28F008SA-L’s deep powerdown
mode ensures extremely low power dissipation even
when system power is applied. For example, porta-
ble PCs and other power sensitive applications, us-
ing an array of 28F008SA-Ls for solid-state storage,
Power Up/Down Protection
Ý
can lower RP to V in standby or sleep modes,
IL
producing negligable power consumption. If access
to the 28F008SA-L is again needed, the part can
The 28F008SA-L is designed to offer protection
against accidental block erasure or byte writing dur-
ing power transitions. Upon power-up, the
28F008SA-L is indifferent as to which power supply,
again be read, following the t
PHQV
Ý
and t
wake-
PHWL
up cycles required after RP is first raised back to
. See AC CharacteristicsÐRead-Only and Write
V
IH
V
PP
ing is not required. Internal circuitry in the
or V , powers up first. Power supply sequenc-
CC
Operations and Figures 10 and 11 for more informa-
tion.
17
28F008SA-L
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet be-
fore finalizing a design.
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 C to 70 C
(1)
b
a
During Block Erase/Byte Write ÀÀÀÀ0 C to 70 C
§
§
a
§
§
§
§
b
a
Temperature Under BiasÀÀÀÀÀÀÀÀÀ 20 C to 80 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
a
§
Voltage on Any Pin
(except V and V
with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V
)
PP
CC
(2)
b
a
V
PP
Program Voltage with
Respect to GND during
Block Erase/Byte Write ÀÀÀ 2.0V to 14.0V
Supply Voltage
(2, 3)
b
a
V
CC
(2)
b
a
with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V
(4)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA
NOTES:
1. Operating temperature is for commercial product defined by this specification.
b
b
2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods
a
k
2.0V for periods 20 ns.
a
20 ns. Maximum DC voltage on input/output pins is V
0.5V which, during transitions, may overshoot to V
CC
CC
k
3. Maximum DC voltage on V may overshoot to 14.0V for periods 20 ns.
k
4. Output shorted for no more than one second. No more than one output shorted at a time.
a
PP
5. AC specifications are valid at both voltage ranges. See DC Characteristics for voltage range specific specification.
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
70
Unit
b
T
A
Operating Temperature
20
C
§
V
V
V
V
Supply Voltage
Supply Voltage
5
5
3.00
4.50
3.60
5.50
V
V
CC
CC
CC
CC
e
g
3.3V 0.3V Read, 3.0–3.6 Program/Erase
DC CHARACTERISTICS V
CC
Symbol
Parameter
Notes Min Typ
Max
Unit
Test Condition
e
g
I
I
I
Input Load Current
1
0.5
mA
V
V
V
Max
CC
or GND
LI
CC
e
V
IN
CC
e
g
Output Leakage Current
1
0.5
mA
mA
mA
mA
V
V
V
Max
CC
or GND
CC
LO
CCS
CC
e
V
OUT
e
V
Standby Current
1, 3
1.0
30
2.0
V
CE
V
Max
CC
CC
CC
e
e
Ý
Ý
RP
V
V
IH
e
100
1.2
V
CC
CE
V
Max
CC
e
Ý
e
Ý
g
0.2V
RP
CC
e
(RY/BY
Ý
g
GND 0.2V
I
V Deep PowerDown
CC
Current
1
0.20
RP
I
CCD
e
Ý
)
0 mA
OUT
18
28F008SA-L
DC CHARACTERISTICS (Continued)
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
e
5 MHz, I
e
Ý
GND
0 mA
I
V
CC
Read Current
1
5
12
mA V
f
V Max, CE
CC
CCR
CC
e
CMOS Inputs
e
OUT
e
5 MHz, I
e
V
Ý
0 mA
5
12
mA V
f
V
Max, CE
e
CC
CC
IL
e
TTL Inputs
OUT
I
I
I
V
CC
V
CC
V
CC
Byte Write Current
Block Erase Current
Erase Suspend
1
1
6
6
3
18
18
6
mA Byte Write In Progress
mA Block Erase In Progress
mA Block Erase Suspended
CCW
CCE
1, 2
CCES
e
V
IH
Ý
Current
CE
s
V
CC
g
g
I
I
V
V
Standby Current
1
1
1
15
mA V
PPS
PPD
PP
PP
e
Ý
g
Deep PowerDown
0.10
5.0
mA RP
GND 0.2V
l
V
CC
PP
Current
I
I
V
Read Current
200
30
mA V
PPR
PP
PP
PP
PP
e
V
PPH
V
Byte Write Current
1
1
1
10
10
90
mA V
PPW
Byte Write in Progress
e
V
PPH
I
I
V
V
Block Erase Current
30
mA V
PPE
PP
PP
Block Erase in Progress
e
V
PPH
Erase Suspend
200
mA V
PPES
PP
PP
Current
Block Erase Suspended
b
V
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage (TTL)
0.5
0.6
V
V
V
V
V
IL
a
2.0
V
0.5
IH
CC
e
e
e
3
3
0.4
V
V
V
V
Min, I
Min, I
2 mA
OL
OH1
OH2
CC
CC
CC
OL
e b
2.4
2 mA
Min
CC
OH
e
e
V
Output High Voltage
(CMOS)
0.85 V
I
I
2.5 mA, V
CC
OH
OH
CC
CC
b
e b
e
V
CC
V
0.4
100 mA, V
Min
CC
CC
V
PPL
V
PPH
V
LKO
V
PP
Operations
during Normal
4
0.0
6.5
V
V
V
V during Erase/Write
PP
Operations
11.4
2.0
12.0
12.6
V Erase/Write Lock
CC
Voltage
(5)
e
e
1 MHz
CAPACITANCE
T
A
25 C, f
§
Symbol
Parameter
Typ
6
Max
8
Unit
Condition
e
0V
C
C
Input Capacitance
Output Capacitance
pF
pF
V
IN
IN
e
0V
8
12
V
OUT
OUT
19
28F008SA-L
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
12.0V, T 25 C. These currents
3.3V, V
PP
§
CC
2. I
is specified with the device deselected. If the 28F008SA-L is read while in Erase Suspend Mode, current draw is
CCES
the sum of I
3. Includes RY/BY
and I
.
CCR
CCES
Ý
.
e
4. Block Erases/Byte Writes are inhibited when V
5. Sampled, not 100% tested.
V
PPL
and not guaranteed in the range between V
and V
.
PPL
PP
PPH
e
g
5.0V 10%
DC CHARACTERISTICS V
CC
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
e
V
g
I
I
I
Input Load Current
1
1.0
mA V
V
Max
CC
or GND
CC
LI
CC
IN
e
V
e
g
Output Leakage Current
1
10
2.0
mA V
V
V
Max
CC
LO
CCS
CC
e
V
or GND
OUT
CC
e
V
CC
Standby Current
1, 3
1.0
30
mA V
CC
CE
V
RP
Max
CC
e
e
Ý
Ý
V
V
IH
e
100
1.2
35
mA V
V
RP
Max
CC
e
Ý
CC
e
Ý
g
0.2V
CE
CC
e
(RY/BY
Ý
g
GND 0.2V
I
I
V Deep PowerDown
CC
Current
1
1
0.20
20
mA RP
CCD
CCR
e
0 mA
Ý
I
)
OUT
e
5 MHz, I
e
Ý
GND
0 mA
V
CC
Read Current
mA V
f
V Max, CE
CC
CC
e
CMOS Inputs
e
OUT
e
5 MHz, I
e
V
Ý
0 mA
25
50
mA V
f
V
Max, CE
e
CC
CC
IL
e
TTL Inputs
OUT
I
I
I
V
V
V
Byte Write Current
Block Erase Current
Erase Suspend
1
1
10
10
5
30
30
10
mA Byte Write In Progress
mA Block Erase In Progress
mA Block Erase Suspended,
CCW
CCE
CC
CC
CC
1, 2
CCES
e
V
IH
Ý
Current
CE
s
V
CC
g
g
I
I
V
Standby Current
1
1
1
15
mA V
PPS
PPD
PP
PP
PP
e
Ý
g
V
Deep PowerDown
0.10
5.0
mA RP
GND 0.2V
l
V
CC
Current
I
I
V
Read Current
1
1
90
10
200
30
mA V
PPR
PP
PP
PP
PP
e
V
PPH
V
Byte Write Current
mA V
PPW
Byte Write in Progress
e
V
PPH
I
I
V
V
Block Erase Current
Erase Suspend
1
1
10
90
30
mA V
PPE
PP
PP
Block Erase in Progress
e
V
PPH
200
mA V
PPES
PP
PP
Current
Block Erase Suspended
b
V
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
V
V
IL
a
2.0
V
0.5
IH
CC
e
e
e
3
3
0.45
V
V
V
V
Min, I
Min, I
5.8 mA
e b
2.5 mA
OL
OH1
OH2
CC
CC
CC
CC
OL
Output High Voltage (TTL)
2.4
OH
e b
e b
e
V
Output High Voltage
(CMOS)
0.85 V
I
2.5 mA, V
Min
Min
CC
OH
OH
CC
CC
b
e
V
V
0.4
I
100 mA, V
CC
CC
CC
V
PPL
V during Normal
PP
Operations
4
0.0
6.5
V
20
28F008SA-L
Test Condition
e
g
5.0V 10%
DC CHARACTERISTICS (Continued) V
CC
Symbol
Parameter
Notes
Min
Typ
12.0
Max
Unit
V
V during Erase/Write
PP
Operations
11.4
12.6
V
PPH
V
V Erase/Write Lock
CC
Voltage
2.0
V
LKO
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
5.0V, V
PP
12.0V, T
25 C. These currents
§
CC
2. I
is specified with the device deselected. If the 28F008SA-L is read while in Erase Suspend Mode, current draw is
CCES
the sum of I
3. Includes RY/BY
and I
.
.
CCES
CCR
Ý
e
4. Block Erases/Byte Writes are inhibited when V
V
PPL
and not guaranteed in the range between V
and V
.
PPL
PP
PPH
(2)
AC TESTING LOAD CIRCUIT
AC INPUT/OUTPUT REFERENCE WAVEFORM
290435–7
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a Logic ‘‘0’’. Input timing
k
begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%)
10 ns.
e
C
C
50 pF
L
L
Includes Jig
Capacitance
290435–8
e
R
L
3.3 kX
(1)
e
g
g
3.3V 0.3V, 5.0V 10%
AC CHARACTERISTICSÐRead-Only Operations
V
CC
Versions
28F008SA-150
Unit
Symbol
Parameter
Notes
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
Address to Output Delay
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
ELQV
PHQV
GLQV
ELQX
EHQZ
GLQX
GHQZ
RC
150
150
600
75
ACC
CE
Ý
CE to Output Delay
2
Ý
RP High to Output Delay
PWH
OE
Ý
OE to Output Delay
2
3
3
3
3
3
Ý
CE to Output Low Z
0
0
0
LZ
Ý
CE High to Output High Z
55
30
HZ
Ý
OE to Output Low Z
OLZ
DF
Ý
OE High to Output High Z
Ý
Output Hold from Addresses, CE or OE
Change, Whichever is First
Ý
OH
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
Ý
2. OE may be delayed up to t –t
3. Sampled, not 100% tested.
Ý
after the falling edge of CE without impact on t
.
CE
CE OE
21
28F008SA-L
Figure 10. AC Waveform for Read Operations
22
28F008SA-L
(1)
e
g
g
3.3V 0.3V, 5.0V 10%
AC CHARACTERISTICSÐWrite Operations
V
CC
Versions
28F008SA-L200
Unit
Symbol
Parameter
Notes
Min
200
1
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
sec
ms
AVAV
WC
PS
Ý
Ý
RP High Recovery to WE Going Low
2
PHWL
ELWL
Ý
Ý
CE Setup to WE Going Low
20
60
100
60
60
5
CS
Ý
WE Pulse Width
WLWH
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHRL
WHQV1
WHQV2
WHGL
WP
VPS
AS
Ý
Setup to WE Going High
V
PP
2
3
4
Ý
Address Setup to WE Going High
Ý
Data Setup to WE Going High
DS
Ý
Data Hold from WE High
DH
AH
Ý
Address Hold from WE High
5
Ý
Ý
CE Hold from WE High
10
30
CH
WPH
Ý
WE Pulse Width High
Ý
Ý
WE High to RY/BY Going Low
Duration of Byte Write Operation
Duration of Block Erase Operation
100
5, 6
5, 6
6
0.3
0
Write Recovery
before Read
Ý
V Hold from Valid SRD, RY/BY High
t
t
2, 6
0
ns
QVVL
VPH
PP
NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A for byte write or block erasure.
IN
4. Refer to Table 3 for valid D for byte write or block erasure.
IN
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard
Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and
erase verify (block erase).
e
0)
e
Ý
6. Byte write and block erase durations are measured to completion (SR.7
e
1, RY/BY
V ). V should be held at
OH PP
V
until determination of byte write/block erase success (SR.3/4/5
PPH
23
28F008SA-L
e
g
3.3V to 0.3V, 5.0V 10%
BLOCK ERASE AND BYTE WRITE PERFORMANCE V
CC
28F008SA-L-200
Parameter
Notes
Unit
(1)
Min
Typ
Max
12.5
Block Erase Time
Block Write Time
Byte Write Time
2
2
2.0
0.7
8
sec
sec
ms
2.6
(Note 3)
NOTES:
1. 25 C, 12.0 V
.
§
PP
2. Excludes System-Level Overhead.
3. Contact your Intel representative for information on the maximum byte write specification.
24
28F008SA-L
Figure 11. AC Waveform for Write Operations
25
28F008SA-L
e
Ý
ALTERNATIVE CE -CONTROLLED WRITES V
g
g
3.3V 0.3V, 5.0V 10%
CC
Versions
28F008SA-L200
Unit
Symbol
Parameter
Notes
Min
200
1
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
sec
ms
ns
AVAV
PHEL
WLEL
ELEH
VPEH
AVEH
DVEH
EHDX
EHAX
EHWH
EHEL
EHRL
EHQV1
EHQV2
EHGL
QVVL
WC
PS
Ý
Ý
RP High Recovery to CE Going Low
2
Ý
Ý
WE Setup to CE Going Low
0
WS
CP
Ý
CE Pulse Width
70
100
60
60
5
Ý
Setup to CE Going High
V
2
3
4
VPS
AS
PP
Ý
Address Setup to CE Going High
Ý
Data Setup to CE Going High
DS
Ý
Data Hold from CE High
DH
AH
Ý
Address Hold from CE High
5
Ý
Ý
WE Hold from CE High
0
WH
EPH
Ý
CE Pulse Width High
25
Ý
Ý
CE High to RY/BY Going Low
Duration of Byte Write Operation
Duration of Block Erase Operation
Write Recovery before Read
100
5
5
6
0.3
0
Ý
Hold from Valid SRD, RY/BY High
t
V
2, 5
0
VPH
PP
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE . In systems where
Ý
Ý
CE defines the write pulsewidth (within a longer WE timing waveform), all setup, hold and inactive WE times should
Ý
be measured relative to the CE waveform.
Ý
Ý
Ý
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A for byte write or block erasure.
IN
4. Refer to Table 3 for valid D for byte write or block erasure.
IN
5. Byte write and block erase durations are measured to completion (SR.7
e
0)
e
V
Ý
1, RY/BY
). V should be held at
OH PP
e
V
until determination of byte write/block erase success (SR.3/4/5
PPH
26
28F008SA-L
Figure 12. Alternate AC Waveform for Write Operations
27
28F008SA-L
ORDERING INFORMATION
290435–12
VALID COMBINATIONS:
E28F008SA-L200
F28F008SA-L200
PA28F008SA-L200
ADDITIONAL INFORMATION
References
Order
Number
290429
28F008SA Datasheet
28F008SA 8 Mbit (1Mbit x 8) Flash Memory SmartDieTM Product Specification 271296
AP-359 ‘‘28F008SA Hardware Interfacing’’
AP-360 ‘‘28F008SA Software Drivers’’
292094
292095
292099
294011
290412
AP-364 ‘‘28F008SA Automation and Algorithms’’
ER-27
ER-28
‘‘The Intel 28F008SA Flash Memory’’
‘‘ETOXTM III Flash Memory Technology’’
Revision History
Number
Description
002
Modified Erase Suspend Flowchart
Lowered V from 2.2V to 2.0V
Combined V Standby Current and V Read Current into One V Standby Current Spec.
LKO
PP
PP
PP
with Two Test Conditions (DC Characteristics Table)
Removed Ð250 Speed Bin
Ý
PWD renamed to RP for JEDEC standardization compatibility.
003
004
g g
standby current specifications from 10 mA to 15 mA in DC Characteristics
Changed I
tables.
PPS
e
e
5 MHz
Changed I
Changed I
test condition from f
8 MHz to f
CCR
Max spec. from 50 mA to 2.0 mA
CCS
Added I
PPR
Corrected I
spec.
spec. typo
PPS
Added V (Output High VoltageÐCMOS) spec.
Changed Operating Temp range (read) from 0 C–70 C to 20 C–70 C.
OHZ
b
§
§
§
§
g
Changed V range from 3.3V 0.3V to 3.15V–3.6V for Program/Erase.
CC
Added Byte Write Time spec.
005
Changed intelligent identifier device code from A1H to A2H
supply voltage (program/erase) is now the same as read
V
CC
I
max changed to 1.2 mA
AC CharacteristicsÐRead-only operation: t
CCD
e
e
e
150 ns,
ELQV
150 ns, t
150 ns, t
AVAV
AVQV
e
Corrected I
e
typical value to read 1.0.
t
600 ns, t
75 ns
PHQV
GLQV
CCS
28
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