FAGD1657832BA [INTEL]

Interface Circuit, PQFP32, 5 X 5 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-32;


型号：	FAGD1657832BA
厂家：	INTEL
描述：	Interface Circuit, PQFP32, 5 X 5 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-32 接口集成电路
文件：	总10页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2.5 Gbit/s

Retiming

Laser Driver

GD16578

an Intel company

Preliminary

General Description

Features

The GD16578 is a high performance low

power 2.5 Gbit/s Laser Driver with

optional on chip retiming of data.

Retiming of the data signal connected to

the pins DIN, DINQ is made by means of

a DFF clocked by an external clock sig-

nal at the data rate fed to the pins CKIN

and CKINQ.

Complies with ITU-T STM-16 and

SONET OC-48 standards.

Intended for driving a 25 W load, e.g.

a laser diode or Mach Zender modu-

lator with 25 W input impedance.

The GD16578 is designed to meet and

exceed ITU-T STM-16 or SONET OC-48

fiberoptic communication systems re-

quirements.

A Mark-Space monitor is available on the

pins MARKP and MARKN. Together with

the symmetry adjustment pin (SYM) this

may be used to control the mark space

ratio of the output signal.

Clocked or non-clocked operation.

The GD16578 is designed to sink a

Modulation Current into the IOUT pin and

a Pre-Bias Current into the IPRE pin. The

Modulation Current is adjustable up to

200 mA by means of the pin VMOD. The

Pre-Bias Current may be adjusted up to

60 mA by means of the VPRE pin.

Large modulation current adjustment

range from 70 mA to 200 mA.

The GD16578 can operate on a single

+5 V supply or a single -5.2 V supply.

Output voltage over / under shoot

less than ±5 % respectively ±10 %.

The circuit is available in a thermally

enhanced 32-pin TQFP plastic package.

Rise / fall times less than 100 ps.

Laser diode pre-bias adjustable up to

60 mA.

Mark-Space monitor.

Symmetry adjustment

Internal 50 W termination of data and

clock inputs.

VMOD

VPRE

Power dissipation: 1 W (typ.).

(excluding Modulation Current and

Pre-bias Current).

Modulation

Current

Control

Pre-Bias

Current

Control

IPRE

32 pin thermally enhanced TQFP

plastic package.

CKSEL

SPOL

VDD

VDDR

DIN

IOUT

DINQ

IOUTN

Input

Buffer

Output

Driver

Applications

VEE

VEEB

VEEP

VEER

DINT

Tele Communication:

–

SDH STM-16

SONET OC-48

CKIN

MARKP

MARKN

SYM

CKINQ

Input

Buffer

Mark/Space

Monitor

Data Communication.

CKINT

Electro Absorption laser driver.

Direct Modulation laser driver.

Mach Zender modulator driver.

Data Sheet Rev.: 10

Functional Details

GD16578 is a 2.5 Gbit/s laser driver with

an optional retiming of the data signal. It

is capable of driving high power laser di-

odes, typically having input impedance of

25 W, at a maximum modulation current

of 200 mA and a maximum pre-bias cur-

rent of 60 mA.

The output pin (IOUT) is an open collec-

tor output designed for driving external

loads with 25 W characteristic imped-

ance. Because of the nature of an open

collector the output therefore may be re-

garded as a current switch, with infinite

output impedance. The characteristic im-

pedance through the package is approxi-

mately 25 W. Optimum performance of

GD16578 therefore is achieved if the out-

put is terminated into a 25 W impedance.

2kW

VMOD

VEE

Data (DIN, DINQ) is input to GD16578

and retimed within a DFF clocked by an

external clock (CKIN, CKINQ). Optionally

the retiming may be bypassed controlled

by a select pin (CKSEL).

Figure 2. Equivalent schematic of the

VMOD input

The output modulation current is con-

trolled by the pin VMOD and can be con-

trolled in the range from 0 mA to 200 mA,

however the specifications is only valid in

the range from 70 mA to 200 mA. The

output voltage swing across the external

load may be varied accordingly. The

modulation current control on pin VMOD

is implemented as a current mirror and

therefore sinks a current proportional to

the modulation current. The current sink

into the VMOD pin is approximately

1/210 of the modulation current.

When DC coupled the output swing will

be limited by the specification for the

minimum voltage of V_DD-3 V on the

IOUT and IOUTN pins. Since 120 mA

into 25 W gives 3 V swing it will not be

possible to terminate the output with a

Both the differential data (DIN, DINQ)

and clock inputs (CKIN, CKINQ) are in-

ternally terminated to 50 W. Termination

is made with a 50 W resistor from the two

differential inputs to a common pin called

DINT and CKINT respectively. Each of

these termination pins is DC biased inter-

nally via 750 W to -1.3 V, hence there is

no need for external bias network. The

input sensitivity when driven with a single

ended signal is better than 150 mV on

both clock and data inputs.

25 W load to V_DD

If more than 120 mA modulation current

is required, either the load (i.e. the laser)

must be supplied from a positive supply

voltage, or AC coupling with a bias tee

must be used (see Figure 3).

The GD16578 can be used e.g. to boost

the output from the GD16553 MUX. This

differential output can be DC coupled to

the GD16578 input. A signal of 200 mV_PP

at a common mode level of -100 mV has

been observed to provide good perfor-

mance.

Control Voltage from

Modulation Current

Control System

Control Voltage from

Pre-Bias Current

Control System

Laser Diode Equivalent

25 W Input Impedance

VMOD / 20

VPRE / 16

Modulation

Current

Control

Pre-Bias

Current

Control

IPRE / 19

VTT

CKSEL / 1

SPOL / 9

DIN / 27

Differential or

Single-ended

Data Signal

IOUT / 13, 14

IOUTN / 11, 12

DINQ / 26

Input

Buffer

Output

Driver

750

VDD

100n

DINT / 28

-1.3V

VTT

CKIN / 31

Differential or

Single-ended

Clock Signal

MARKP / 7

100n

CKINQ / 32

Input

Buffer

Mark/Space

Monitor

MARKN / 6

CKINT / 30

750

100n

-1.3V

VEEP / 18

Negative Ref.

Supply

Figure 1. Application Diagram

Data Sheet Rev.: 10

GD16578

Page 2 of 10

An important parameter for laser drivers

is voltage overshoot on the output pin

(IOUT), because it determines the extinc-

tion ratio. GD16578 has been designed

with special emphasis on achieving a

very small voltage overshoot. For

GD16578 the voltage overshoot is less

than 5 % across the full modulation cur-

rent range, when driving a 25 W load.

Similarly the voltage undershoot is less

than 10 %.

VTT

220uH

10uH

100nF

Ext.

Load

IOUT

IOUTN

A mark-space monitor is provided

through the pins MARKP and MARKN.

These may be connected as shown in

the application diagram below, with a ca-

pacitor across the two outputs and a

comparator (or Op-amp) to determine the

mark density. Symmetry input (SYM) is

available which may be used to control

the mark-space ratio.

25W

VDD

Figure 3. AC Coupled Output

For high modulation currents it may be

necessary to use a positive supply for the

bias tee, depending on the resistance in

the bias coils. Measurements with the

set-up in Figure 3 with bias coils with 7 W

resistance show that a positive supply is

required for modulation current above

approximately 150 mA, and a voltage

V_TT= +1,0 V is sufficient to give 200 mA

with V_EE= –5.2 V supply. Less negative

V_EEvoltage must be compensated by

correspondingly higher V_TTsupply.

In the configuration shown in Figure 3

two coils in series are used for each

branch of the output for effective blocking

of high and low frequencies. Low fre-

quency ciols generally have high para-

sitic parallel capacitance.

Figure 4. Output waveform at 200 mA,

-4.7 V supply, AC coupled

load.

The pre-bias current is controlled by the

pin VPRE and can be controlled from

0 mA to 60 mA. The pre-bias current

control on pin VPRE is implemented as a

current mirror and therefore sinks a cur-

rent proportional to the pre-bias current.

The current sink into the VPRE pin is

approximately 3/500 of the pre-bias

current.

Data Sheet Rev.: 10

GD16578

Page 3 of 10

Pin List

Mnemonic:

Pin No.:

Pin Type:

Description:

DIN

DINQ

AC IN

Data inputs. Internally terminated in 50 W to DINT.

DINT

ANL IN

AC IN

Termination voltage for DIN and DINQ.

Internally biased to -1.3 V with 750 W.

CKIN

CKINQ

Clock inputs. Internally terminated in 50 W to CKINT. Data is sam-

pled on the positive going edge of the clock (CKIN).

CKINT

ANL IN

Termination voltage for CKIN and CKINQ.

Internally biased to -1.3 V with 750 W.

IOUT

IOUTN

13, 14

11, 12

OPEN

COLLECTOR

Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modula-

tion current, which is controlled by the pin VMOD. The polarity of

the output depends on the settings of SPOL, see below.

IPRE

OPEN

COLLECTOR

Pre-bias current output. IPRE sinks a current, which is controlled

by the pin VPRE.

VMOD

ANL IN

Modulation current control input. The control system is made as a

current mirror. VMOD sinks a current proportional to the modula-

tion current. This current is approximately 1/210 times “The modu-

lation current”.

VPRE

ANL IN

Pre-bias current control input. The control system is made as a

current mirror. VPRE sinks a current proportional to the pre-bias

current. This current is approximately 3/500 times “The pre-bias

current”.

CKSEL

SPOL

ECL IN

When CKSEL is low data is retimed. Otherwise data is bypassed

the retiming. May be connected to rails.

Data polarity select pin. When SPOL is high, a high level on DIN

will cause the IOUT output to sink current, i.e. causing the voltage

on IOUT to be low. SPOL is internally pulled to VDD with a 5 k re-

sistor. May be connected to rails.

SYM

ANL IN

SYM controls the mark-space ratio of the output. Decreasing the

voltage of the SYM pin decreases the pulse width of a current

high into the IOUT pin. When SYM is left open the output cross-

over will be 50%.

MARKP

MARKN

ANL OUT

Mark-space monitor outputs. High impedance CML outputs. The

output voltage of the MARKP pin is the same polarity as the volt-

age on the IOUT pin.

VDD

2, 3, 4, 10, 15

PWR

Ground pins for laser driver part.

Ground pin for retiming part.

VDDR

VEE

5, 8, 23

Negative supply pins for laser driver part. Package back is VEE.

Negative supply pin for pre-bias circuitry.

Negative supply pin for output driver.

Negative supply pin for retiming part.

Not Connected.

VEEB

VEEP

VEER

21, 22

Package back

Heat sink

Connected to VEE.

Data Sheet Rev.: 10

GD16578

Page 4 of 10

Package Pinout

CKSEL

VDD

SYM

VEE

VDD

VEE

VMOD

IPRE

VEEP

VEEB

MARKN

MARKP

VEE

Figure 5. Package 32 TQFP, Top View

Maximum Ratings

These are the limits beyond which the component may be damaged.

All voltages in table are referred to VDD.

All currents in table are defined positive out of the pin.

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

-6

TYP.:

MAX.:

UNIT:

Power Supply

0.5

V_O

Applied Voltage (All Outputs)

Applied Voltage IOUT and IOUTN

Applied Voltage (All Inputs)

Input Current (AC IN)

Input Current (VMOD)

Input Current (VPRE)

Operating Temperature

Storage Temperature

V_EE-0.5

-1

V_OIOUT/N

V_I

0.5

I_IAC IN

I_IVMOD

I_IVPRE

T_O

°C

-2

0.1

Note 1

Case

-1

-40

+110

+125

T_S

-65

Note 1: Voltage and/or current should be externally limited to specified range.

Data Sheet Rev.: 10

GD16578

Page 5 of 10

DC Characteristics

T_CASE= - 40 °C to 85 °C, appropriate heat sinking may be required. Device is DC-tested in the temperature range 0 °C to 85 °C,

specifications from -40 °C to 0 °C are guaranteed by design, and evaluated during the engineering test.

All voltages in table are referred to VDD.

All currents in table are defined positive out of the pin.

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

-4.7

UNIT:

Power Supply

- 5.5

I_EE

Negative Supply Current

V_EE= -5.2 V

I_OUT= 0 A

I_PRE= 0 A

160

180

P_DISS

Power Dissipation

V_EE= - 5.0 V,

I_OUT= 0 A,

I_PRE= 0 A, Note 4

V_ppAN IN

V_CAN IN

Peak- peak Voltage when Input is Driven Single V_VTH= - 1.3 V

ended.

150

-1.5

800

-0.5

Common Mode Voltage Range for Data and

Clock Inputs

V_IHECL

V_ILECL

V VMOD

I VMOD

V_INNN

ECL Input HI Voltage

-1.1

V_EE

-1.3

V_EE

- 1

-1.5

V_DD

ECL Input LO Voltage

Voltage Range for VMOD

Sink Current into Pin VMOD

Input Voltage Range for VPRE and SYM

Sink Current into pin VPRE and SYM

Input Voltage Range for SYM

Leakage Current for SYM

V_DD

I_SINKNN

V_INSYM

I_LEAKSYM

V_EE

- 1

V_DD

I_LEAKCKSEL,SPOL Leakage Current for CKSEL and SPOL

-2 < V_I< -0.7

- 1

V_LOMARK

R_OMARK

V_OIPRE

Low Output Voltage for Mark-Space Monitor

Output Impedance for Mark-Space Monitor

IPRE Output Voltage

- 2.0

4.0

- 3.0

- 60

- 3.0

-200

-6

I IPRE

IPRE Current

V_OIOUT

IOUT Output Voltage

Note 1

I_Mod,HIIOUT

I_Mod,LOIOUT

I_OUT/I_(VMOD)

IOUT High Modulation Current

IOUT Low Modulation Current

Note 1, 2

Note 1, 3

Modulation Control Current to Modulation

Current Gain

200

210

220

Note 1: R_LOAD= 25 W to V_DD+2 V connected to pin IOUT and IOUTN. Sink current is controlled by the VMOD pin, and may be

adjusted in the range as specified. Notice that high modulation current means that the output voltage level is low.

Note 2: The AC parameters are only specified in the range from -200 mA to -70 mA.

Note 3: This is a leakage current. Maximum leakage current is present at max modulation current (i.e. at 200 mA modulation

current). The leakage current decreases for smaller modulation currents.

Note 4: Please observe that the heat dissipation in the GD16578 is the sum of contributions from the modulation current, the

pre-bias current, and the device’s own power consumption. Furthermore, the GD16578’s own power consumption de-

pends on the modulation current. Please refer to Figure 6 and example on page 7 .

Data Sheet Rev.: 10

GD16578

Page 6 of 10

VDD

IPRE

IOUT

PRE

MOD

IOUTN

VEE

Figure 6. Equivalent of power dissipation

Example:

With V_EE= -5,2 V, I_PRE= 50 mA from a 25 W load to 0 V, and I_MOD= 200 mA from bias coils (» 0 W) connected to 0 V, and a base

consumption for the device itself at 160 mA + 0.1 × I_MODthe total power equals

Prebias:

(5.2V - (25 W × 50 mA)) × 50 mA » 0.2 W

Modulation current:

5.2 V × 200 mA » 1.04 W

Own consumption:

5.2 V × (160 + 0.1 × 200 mA) » 0.94 W

This amounts to a total of:

2.2 W.

Please observe that the heat sink is connected to VEE to obtain best thermal contact between die and heat sink of the package.

Data Sheet Rev.: 10

GD16578

Page 7 of 10

AC Characteristics

T_CASE= -40 °C to +85 °C, appropriate heat sinking may be required. Device is AC-tested in the temperature range 0 °C to 85 °C,

specifications from -40 °C to 0 °C are guaranteed by design, and evaluated during the engineering test.

t_CLK

CKIN

t_H

DIN

t_SU

Symbol:

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

UNIT:

Mbit/s

f_MAXOUT

Data Output Frequency

Added Output Jitter

Output Rise Time

Output Fall Time

2700

_ppOUT

Note 1, 2, 3

Note 1, 2

Note 2, 4

Note 1, 2

Note 2, 4

_RISEOUT

_FALLOUT

125

t_PM

Phase Margin Clock to Data

Data Set-up Time

Data Hold Time

300

t_SU

t_H

D_{CROSS_OVER}

Output Cross Over Control Range, Dhx/H

Ringing h1/H

± 30

Ringing h2/H

Ringing h3/H

Ringing h4/H

Note 1: I_LD= 140 mA. Rise/Fall times at 20 – 80 % of HI/LO voltage levels.

Note 2: Measured in GIGA evaluation board GD90571. IOUT and IOUTN are terminated to 25 W and DC terminated to V_DD

through a biastee.

Note 3: Added jitter. Measured as a peak-peak jitter value on a sampling oscilloscope in 60 s period. Measured with the data re-

timing enabled, and using the retiming clock signal as trigger for the oscilloscope.

Note 4: I_LD= 70 mA. Engineering test has shown that this is the worst case corner.

Data Sheet Rev.: 10

GD16578

Page 8 of 10

Package Outline

Figure 7. Package 32 pin TQFP EQUAD.

Device Marking

GD16578

Pin 1 - Mark

Figure 8. Device Marking. Top View.

Data Sheet Rev.: 10

GD16578

Page 9 of 10

Ordering Information

To order, please specify as shown below:

Product Name:

GD16578-32BA

Intel Order Number:

Package Type:

Case Temperature Range:

FAGD1657832BA

MM#: 836128

32L TQFP EDQUAD

-40..85 °C

GD16578, Data Sheet Rev.: 10 - Date: 20 June 2001

an Intel company

Mileparken 22, DK-2740 Skovlunde

Denmark

Phone : +45 7010 1062

Distributor:

The information herein is assumed to be

reliable. GIGA assumes no responsibility

for the use of this information, and all such

information shall be at the users own risk.

Prices and specifications are subject to

change without notice. No patent rights or

licenses to any of the circuits described

herein are implied or granted to any third

party. GIGA does not authorise or warrant

any GIGA Product for use in life support

devices and/or systems.

Fax : +45 7010 1063

E-mail : sales@giga.dk

Web site : http://www.intel.com/ixa

An Intel company

Please check our Internet web site

for latest version of this data sheet.

FAGD1657832BA [INTEL]

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