FW80321M600Q467B-1_技术文档

Intel^®80321 I/O Processor

Datasheet

Product Features

■ Core Features

■ DMA Controller

—Integrated Intel^®XScale^™Core

—ARM* V5T Instruction Set

—ARM V5E DSP Extensions

—400 MHz and 600 MHz

—Write Buffer, Write-back Cache

■ PCI Bus Interface

—Two Independent Channels Connected

to Internal Bus

—Up to 1064 Mbytes/s Burst Support in

PCI-X Mode

—Up to 1600 Mbytes/s Burst Support for

Internal Bus

—Two 1-Kbyte Queues in Ch-0 and Ch-1

—2³²Addressing Range on Internal Bus

Interface

—PCI Local Bus Specification, Rev. 2.2

compliant

—2⁶⁴Addressing Range on PCI Interface

■ Application Accelerator Unit

—PCI-X Addendum to the PCI Local Bus

Specification, Rev. 1.0a

—64-bit/66 MHz Operation in PCI Mode

—Performs XOR on Read Data

—64-bit/133 MHz Operation in PCI-X

Mode

—Compute Parity Across Local Memory

Blocks

—Support 32-bit PCI Initiators and Targets

—Four Split Read Requests as Initiator

—Eight Split Read Requests as Target

—64-bit Addressing Support

—1 Kbyte/512-byte Store Queue

■ I²C Bus Interface Units

—Two Separate I²C Units

—Serial Bus

—Master/Slave Capabilities

■ Memory Controller

—System Management Functions

■ SSP Serial Port

—PC200 Double Data Rate (DDR) SDRAM

—Up to 1 Gbyte of 64-bit DDR SDRAM

—Full-duplex Synchronous Serial Interface

—Supports 7.2 KHz to 1.84 MHz Bit Rates

■ Peripheral Performance Monitoring Unit

—One Dedicated Global Time Stamp

Counter

—Fourteen Programmable Event Counters

—Three Control/Status Registers

■ Timers

—Up to 512 Mbytes of 32-bit DDR

SDRAM

—Single-bit Error Correction, Multi-bit

Support (ECC)

—1024-byte Posted Memory Write Queue

—40- and 72-bit wide Memory Interface

■ Address Translation Unit

—2 Kbyte or 4 Kbyte Outbound Read

Queue

—Two Dual-programmable 32-bit Timers

—Watchdog Timer

—4 Kbyte Outbound Write Queue

■ 544-Ball, Plastic Ball Grid Array (PBGA)

■ Eight General Purpose I/O Pins

—4 Kbyte Inbound Read and Write Queue

—Connects Internal Bus to PCI/PCI-X Bus

Document Number: 273518-005

January 2005

Intel^®80321 I/O Processor

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Intel may make changes to specifications and product descriptions at any time, without notice.

The Intel^®80321 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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*Other names and brands may be claimed as the property of others.

2

January 2005

Datasheet

Intel^®80321 I/O Processor

Contents

1.0

Introduction.........................................................................................................................7

1.1

About This Document............................................................................................7

1.1.1 Terminology..............................................................................................7

1.1.2 Other Relevant Documents......................................................................8

About the Intel^®80321 I/O Processor ...................................................................9

1.2

2.0

Features ...........................................................................................................................11

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

Internal Bus .........................................................................................................11

DMA Controller....................................................................................................11

Address Translation Unit.....................................................................................12

Messaging Unit....................................................................................................12

Memory Controller...............................................................................................12

Peripheral Bus Interface......................................................................................12

Application Accelerator Unit ................................................................................13

Performance Monitoring Unit...............................................................................13

I²C Bus Interface Units........................................................................................13

Synchronous Serial Port Unit ..............................................................................13

3.0

Package Information ........................................................................................................14

3.1

3.2

Package Introduction...........................................................................................14

3.1.1 Functional Signal Definitions..................................................................14

3.1.2 544-Lead PBGA Package ......................................................................25

Package Thermal Specifications.........................................................................39

3.2.1 Thermal Characteristics .........................................................................39

3.2.2 Thermal Specifications...........................................................................40

3.2.2.1 Ambient Temperature................................................................40

3.2.2.2 Case Temperature ....................................................................40

3.2.3 80321 JTAG Emulator Vendor ...............................................................40

4.0

Electrical Specifications....................................................................................................41

4.1

4.2

4.3

4.4

Absolute Maximum Ratings.................................................................................41

Pin Requirements ...................................................................................41

V

CCPLL

Targeted DC Specifications.................................................................................42

Targeted AC Specifications.................................................................................44

4.4.1 Clock Signal Timings..............................................................................44

4.4.2 PCI Interface Signal Timings..................................................................45

4.4.3 DDR SDRAM Interface Signal Timings..................................................46

4.4.4 Peripheral Bus Interface Signal Timings ................................................46

4.4.5 I²C Interface Signal Timings...................................................................47

4.4.6 SSP Interface Signal Timings.................................................................47

4.4.7 Boundary Scan Test Signal Timings ......................................................48

AC Timing Waveforms ........................................................................................49

AC Test Conditions .............................................................................................53

4.5

4.6

Figures

1

2

3

Intel^®80321 I/O Processor Functional Block Diagram........................................10

544-Lead PBGA Package (Top View).................................................................25

544-Lead PBGA Package (Bottom View)............................................................26

Datasheet

January 2005

3

Intel^®80321 I/O Processor

4

Ball Map - Left Side - Top View...........................................................................27

5

6

Ball Map - Right Side - Top View ........................................................................28

Thermocouple Attachment—No Heatsink...........................................................40

7

V

Lowpass Filter ........................................................................................41

CCPLL

8

9

Clock Timing Measurement Waveforms .............................................................49

Output Timing Measurement Waveforms ...........................................................49

Input Timing Measurement Waveforms ..............................................................50

I²C Interface Signal Timings................................................................................50

DDR SDRAM Write Timings ...............................................................................51

DDR SDRAM Read Timings ...............................................................................52

AC Test Load for all Signals Except PCI and DDR SDRAM...............................53

PCI/PCI-X TOV(max) Rising Edge AC Test Load...............................................53

PCI/PCI-X TOV(max) Falling Edge AC Test Load ..............................................53

PCI/PCI-X TOV(min) AC Test Load ....................................................................54

PCI_RST# vs. PWRDELAY Timings During Power-Up ......................................54

PCI_RST# vs. PWRDELAY Timings During Power-Down .................................54

10

11

12

13

14

15

16

17

18

19

4

January 2005

Datasheet

Intel^®80321 I/O Processor

Tables

1

2

3

4

5

6

7

8

Related Documentation.........................................................................................8

Pin Description Nomenclature.............................................................................14

DDR SDRAM Signals..........................................................................................15

Peripheral Bus Interface Signals.........................................................................16

PCI Bus Signals ..................................................................................................19

Serial Port Interface Signals................................................................................20

Miscellaneous Signals.........................................................................................21

Pin Mode Behavior..............................................................................................23

544-Lead PBGA Package - Alphabetical Ball Listing..........................................29

544-Lead PBGA Package - Alphabetical Signal Listing......................................34

544-Lead PBGA Package Thermal Characteristics ............................................39

JTAG Emulator Vendor .......................................................................................40

Absolute Maximum Ratings.................................................................................41

Operating Conditions...........................................................................................41

DC Characteristics ..............................................................................................42

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

I

Characteristics ..............................................................................................43

CC

Clock Timings......................................................................................................44

PCI Signal Timings..............................................................................................45

DDR SDRAM Signal Timings..............................................................................46

Peripheral Bus Signal Timings ............................................................................46

I²C Signal Timings...............................................................................................47

SSP Signal Timings.............................................................................................47

Boundary Scan Test Signal Timings ...................................................................48

DAT Mode Timings..............................................................................................48

Bypass Mode Timings.........................................................................................48

AC Measurement Conditions ..............................................................................53

Datasheet

January 2005

5

Intel^®80321 I/O Processor

Revision History

Date

Revision #

Description

January 2005

005

Updated case temperature range and other text in first paragraph of Section

3.2, “Package Thermal Specifications” on page 39.

Added Section 3.2.1, “Thermal Characteristics” on page 39.

Added Table 11 “544-Lead PBGA Package Thermal Characteristics” on

page 39.

Updated Table 13 “Absolute Maximum Ratings” on page 41:

•

Updated ratings for “Case temperature under bias.”

Updated Table 14 “Operating Conditions” on page 41:

Updated maximum value for “Case temperature under bias.”

In Table 7 “Miscellaneous Signals”:

•

January 2003

004

•

For signal GPIO[4]/SDA1, added sentence “2.7K pull-up is required.”

For signal GPIO[5]/SCL1, added sentence “2.7K pull-up is required.”

For signal GPIO[6]/SDA0, added sentence “2.7K pull-up is required.”

For signal GPIO[7]/SCL0, added sentence “2.7K pull-up is required.”

Added signal P_BMI with count and type values, and description.

In Table 8 “Pin Mode Behavior”:

•

Changed RDYRCV# signal from VI to VO for Reset.

Added signal P_BMI with reset and norm values.

In Table 9 “544-Lead PBGA Package - Alphabetical Ball Listing”: Changed

AE23 from NC2 to P_BMI.

In Table 10 “544-Lead PBGA Package - Alphabetical Signal Listing”: Changed

NC2 to P_BMI.

In Section 4.3, “Targeted DC Specifications”: Revised notice to state “The

specifications are subject to change without notice. Contact your local Intel

representative before finalizing a design.”

Revised Table 16 “I_CCCharacteristics”.

In Table 19 “DDR SDRAM Signal Timings”: Added TVA6 with description, and

minimum signal timing value.

In Figure 13 “DDR SDRAM Read Timings”:

•

Revised signal timing relationships for TVA5 and TVA6 to CK and

rcveno#.

•

Added TVA6 signal timing relationship to reveni# and DQS.

Added Figure 18 “PCI_RST# vs. PWRDELAY Timings During Power-Up”.

Added Figure 19 “PCI_RST# vs. PWRDELAY Timings During Power-Down”.

June 2002

003

002

001

Formatting Changes.

Removed Advance Information designation.

Initial release.

February 2002

6

January 2005

Datasheet

1.0

Introduction

1.1

About This Document

This is the Intel^®80321 I/O Processor Datasheet. This datasheet contains a functional overview,

package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed

functional descriptions other than parametric performance is published in the Intel^®80321 I/O

Processor Developer’s Manual.

Intel Corporation assumes no responsibility for any errors which may appear in this document nor

does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice. In

particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment

to implement them. In fact, this document does not imply a commitment by Intel to design,

manufacture, or sell the product described herein.

1.1.1

Terminology

To aid the discussion of the Intel^®80321 I/O processor (80321) architecture, the following

terminology is used:

Downstream

At or toward a PCI bus with a higher number (after configuration)

Host processor Processor located upstream from the 80321

Local processor Intel XScale^®core (ARM* architecture compliant) within the 80321

Local bus

80321 Internal Bus

Local memory Memory subsystem on the Intel XScale^®core PC200 DDR SDRAM or Peripheral Bus

Interface busses

Upstream

At or toward a PCI bus with a lower number (after configuration)

Datasheet

January 2005

7

Intel^®80321 I/O Processor

Introduction

1.1.2

Related Documentation

Document Title

Document# / Contact

Intel^®80312 I/O Companion Chip Developer’s Manual

273410

273416

273411

273354

273414

273415

Intel^®80312 I/O Companion Chip Specification Update

Intel^®80200 Processor based on Intel^®XScale^™Microarchitecture Developer’s Manual

Intel^®80310 I/O Processor Chipset with Intel^®XScale^™Microarchitecture Design Guide

Intel^®80200 Processor based on Intel^®XScale^™Microarchitecture Datasheet

Intel^®80200 Processor based on Intel^®XScale^™Microarchitecture Specification Update

PCI Local Bus Specification, Revision 2.2

PCI Special Interest Group

1-800-433-5177

PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a

PCI-to-PCI Bridge Architecture Specification, Revision 1.1

PCI System Design Guide, Revision 1.0

http://www.pcisig.com/home

PCI Hot-Plug Specification, Revision 1.0

PCI Bus Power Management Interface Specification, Revision 1.1

I²C Peripherals for Microcontrollers

Philips Semiconductor*

Advanced Configuration and Power Interface Specification, Revision 1.0 (ACPI)

NOTE: Also see our product website at: http://developer.intel.com/design/iio/.

http://www.teleport.com/~acpi/

8

January 2005

Datasheet

Intel^®80321 I/O Processor

Introduction

1.2

About the Intel^®80321 I/O Processor

The 80321 is a single-function device that integrates the Intel XScale^®core with intelligent

peripherals, including a PCI bus application bridge. The 80321 consolidates into a single system:

• Intel XScale^®core

• PCI - Local Memory Bus Address Translation Unit

• Messaging Unit

• Direct Memory Access (DMA) Controller

• Peripheral Bus Interface Unit

• Integrated Memory Controller

• Performance Monitor

• Application Accelerator

• Two I²C Bus Interface Units

• Synchronous Serial Port Unit

• Eight General Purpose Input Output (GPIO) ports

It is an integrated processor that addresses the needs of intelligent I/O applications and helps

reduce intelligent I/O system costs.

The PCI Bus is an industry standard, high performance, low latency system bus. The 80321 PCI

Bus is capable of 133 MHz operation in PCI-X mode as defined by the PCI-X Addendum to the

PCI Local Bus Specification, Revision 1.0a. Also, the processor supports a 66 MHz conventional

PCI mode as defined by the PCI Local Bus Specification, Revision 2.2. The addition of the Intel

XScale^®core brings intelligence to the PCI bus application bridge.

The 80321 is a single-function PCI device. This function represents the address translation unit.

The address translation unit is an ‘application bridge’ as defined by the PCI-X Addendum to the

PCI Local Bus Specification, Revision 1.0a. The 80321 contains PCI configuration space

accessible through the PCI bus.

Datasheet

January 2005

9

Intel^®80321 I/O Processor

Introduction

Figure 1 is a block diagram of the 80321.

Figure 1.

Intel^®80321 I/O Processor Functional Block Diagram

2

I C

72-Bit

I/F

32-Bit

I/F

Serial Bus

Intel^®

XScale™

Core

2

DDR I/F

Unit

PBI Unit

(Flash)

I C Bus

Application

Accelerator

SSP

Serial Bus

Interface

Internal Bus

Two

DMA

Channels

Performance

Monitoring

Unit

Address

Translation

Unit

Messaging

Unit

Intel^®80321 I/O Processor

64-bit / 32-bit PCI Bus

Notes:

Intel XScale Microarchitecture is ARM* Architecture compliant.

* Other brands and names are the property of their respective owners.

A7610-02

10

January 2005

Datasheet

Intel^®80321 I/O Processor

Features

2.0

Features

The 80321 combines the Intel XScale^®core with powerful new features to create an intelligent I/O

processor. This single-function PCI device is fully compliant with the PCI Local Bus Specification,

Revision 2.2. 80321-specific features include:

• Address Translation Unit

• Memory Controller

• Peripheral Bus Interface

• Application Accelerator Unit

• I²C Bus Interface Units

• DMA Controller

• Performance Monitoring Unit

• Synchronous Serial Port Unit

• Messaging Unit

• I O* Compatibility

2

The subsections that follow briefly overview each feature. Refer to the appropriate chapter in the

Intel^®80321 I/O Processor Developer’s Manual for full technical descriptions.

The 80321 core is based upon the Intel XScale^®core. The core processor operates at a maximum

frequency of 600 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative.

Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative and a

mini data cache that is 2 Kbytes and is 2-way set associative.

The 80321 includes 8 General Purpose I/O (GPIO) pins.

2.1

2.2

Internal Bus

The Internal Bus is a high-speed interconnect between all internal units and controllers. The

Internal Bus operates at 200 MHz and is 64 bits wide.

DMA Controller

The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents

and the local memory. Two separate DMA channels accommodate data transfers on the PCI bus.

The DMA Controller supports chaining and unaligned data transfers. It is programmable through

the Intel XScale^®core only.

Datasheet

January 2005

11

Intel^®80321 I/O Processor

Features

2.3

Address Translation Unit

The Address Translation Unit (ATU) allows PCI transactions direct access to the 80321 local

memory. The ATU supports transactions between PCI address space and the 80321 address space.

Address translation is controlled through programmable registers accessible from both the PCI

interface and the Intel XScale^®core. Dual access to registers allows flexibility in mapping the two

address spaces. The ATU also supports the following extended capability configuration headers:

1. Power Management header as defined by PCI Bus Power Management Interface

Specification, Revision 1.1.

2. Message Signaled Interrupt capability structure specified in PCI Local Bus Specification,

Revision 2.2.

3. PCI-X Capabilities List Item specified in the PCI-X Addendum to the PCI Local Bus

Specification, Revision 1.0a.

2.4

Messaging Unit

The Messaging Unit (MU) provides data transfer between the PCI system and the 80321. It uses

interrupts to notify each system when new data arrives. The MU has four messaging mechanisms:

• Message Registers

• Doorbell Registers

• Circular Queues

• Index Registers

Each allows a host processor or external PCI device and the 80321 to communicate through

message passing and interrupt generation.

2.5

2.6

Memory Controller

The Memory Controller allows direct control of a PC200 DDR SDRAM memory subsystem. It

features programmable chip selects and support for error correction codes (ECC). External memory

may be configured as PCI addressable memory or private 80321 memory.

Peripheral Bus Interface

The Peripheral Bus Interface Unit (PBI) is a data communication path to certain components of a

80321 hardware system that do not have PCI bus interfaces and/or do not optimally reside on the

PCI Bus. Examples of such components include Flash Memory and DSP host interface ports. The

PBI allows the processor to manipulate data and interact with these components in the I/O

environment. To perform these tasks at high bandwidth, the bus features a burst transfer capability

which allows successive 32-bit data transfers. The bus has a 33 MHz, 66 MHz and a 100 MHz

operating mode.

12

January 2005

Datasheet

Intel^®80321 I/O Processor

Features

2.7

2.8

Application Accelerator Unit

The Application Accelerator Unit transfers blocks of data to and from the local memory and

performs boolean operations, such as XOR, on the data.

Performance Monitoring Unit

The Performance Monitoring Unit (PMON) allows various events on the 80321 to be monitored.

The 14 Event Counters may be programmed to observe events selected from a pre-defined set of

events.

2.9

I²C Bus Interface Units

There are two I²C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel XScale^®core to

serve as a master and slave device residing on the I²C bus. The I²C unit uses a serial bus developed

by Philips Semiconductor* consisting of a two-pin interface. The bus allows the 80321 to interface

to other I²C peripherals and microcontrollers for system management functions. It requires a

minimum of hardware for an economical system to relay status and reliability information on the

I/O subsystem to an external device. Also refer to I²C Peripherals for Microcontrollers (Philips

Semiconductor*).

2.10

Synchronous Serial Port Unit

The Synchronous Serial Port (SSP) Unit is a full-duplex synchronous serial interface. It may

connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and

many other devices which use serial protocols for transferring data. It supports the National

Microwire*, Texas Instrument* synchronous serial protocol, and the Motorola* serial peripheral

interface (SPI) protocol.

Datasheet

January 2005

13

Intel^®80321 I/O Processor

Package Information

3.0

Package Information

3.1

Package Introduction

The 80321 is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array

package with 508 ball connections in the outer area of the package and a square 6x6 grid of rows of

ball connections in the middle area of the package. See Figure 3 “544-Lead PBGA Package

(Bottom View)” on page 26.

3.1.1

Functional Signal Definitions

This section defines the pins and signals.

Pin Description Nomenclature

Table 2.

Symbol

Description

I

Input pin only

O

I/O

Output pin only

Pin may be either an input or output.

Open Drain pin

OD

-

Pin must be connected as described.

Sync(...)

Synchronous. Signal meets timings relative to an input clock.

Sync(P) Synchronous to P_CLK

Sync(M) Synchronous to M_CK[2:0]

Sync(PB) Synchronous to PB_CLK

Sync(SS) Synchronous to SSCKO

Sync(T) Synchronous to TCK

Async

Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals

are level-sensitive.

Rst(P)

Rst(M)

The pin is reset with P_RST#.

The pin is reset with M_RST#.

Note that M_RST# is asserted when P_RST# is asserted or PCSR[5] is set with software.

Rst(T)

The pin is reset with TRST#.

(Configuration These pins are used during reset to configure the processor.

Pin)

These pins have internal pullup resisters which are turned on when P_RST# is low. To

configure the pin low connect a 4.7KΩ resister from the pin to ground. By default the pin is

configured high.

14

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 3.

DDR SDRAM Signals

Name

Count

Type

Description

RCVENI#

1

I

RECEIVE ENABLE IN provides delay information for enabling the input

receivers and must be connected to RCVENO# of the 80321.

RCVENO#

M_CK[2:0]

M_CK[2:0]#

M_RST#

1

3

O

RECEIVE ENABLE OUT must be connected to RCVENI# of the 80321

and be trace length matched to Clock Trace plus average DQ Traces.

MEMORY CLOCKS are used to provide the positive differential clocks to

the external SDRAM memory subsystem.

3

MEMORY CLOCKS are used to provide the negative differential clocks to

the external SDRAM memory subsystem.

1

O

Async

MEMORY RESET indicates when the memory subsystem has been reset

with P_RST# or a software reset.

SA[12:0]

13

O

MEMORY ADDRESS BUS carries the multiplexed row and column

Sync(M) addresses to the SDRAM memory banks. For SA[10], See Note 1.

Rst(M)

SBA[1:0]

SRAS#

2

1

O

SDRAM BANK ADDRESS indicates which of the SDRAM internal banks

Sync(M) are read or written during the current transaction. See Note 1.

Rst(M)

O

SDRAM ROW ADDRESS STROBE indicates the presence of a valid row

Sync(M) address on the Multiplexed Address Bus SA[12:0]. See Note 1.

Rst(M)

SCAS#

1

O

SDRAM COLUMN ADDRESS STROBE indicates the presence of a valid

Sync(M) column address on the Multiplexed Address Bus SA[12:0]. See Note 1.

Rst(M)

SWE#

1

O

SDRAM WRITE ENABLE indicates that the current memory transaction

Sync(M) is a write operation. See Note 1.

Rst(M)

SCE[1:0]#

SCKE[1:0]

DQ[63:0]

2

O

SDRAM CHIP SELECT enables the SDRAM devices for a memory

Sync(M) access (Physical banks 0 and 1). See Note 1.

Rst(M)

2

O

SDRAM CLOCK ENABLE enables the clocks for the SDRAM memory.

Sync(M) Deasserting places the SDRAM in self-refresh mode. See Note 1.

Rst(M)

64

I/O

SDRAM DATA BUS carries 64-bit data to and from memory. During a

Sync(M) data cycle, read or write data is present on one or more contiguous bytes.

Rst(M) During write operations, unused pins are driven to determinate values.

See Note 1.

SCB[7:0]

DQS[8:0]

SDQM[8:0]

8

9

1

I/O

SDRAM ECC CHECK BITS carry the 8-bit ECC code to and from

Sync(M) memory during data cycles. See Note 1.

Rst(M)

I/O

SDRAM DATA STROBES carry the strobe signals which are used to

Sync(M) capture data on the data bus. See Note 1.

Rst(M)

O

SDRAM DATA MASK controls which bytes on the data bus should be

Sync(M) written. When SDQM[8:0] is asserted, the SDRAM devices do not accept

Rst(M) valid data from the byte lanes. See Note 1.

V_REF

I

SDRAM VOLTAGE REFERENCE is used to supply the reference voltage

to the differential inputs of the memory controller pins.

NOTE:

1. These pins remain functional for 20 M_CK[2:0] periods after M_RST# is asserted for a warm boot. The

designated Rst(M) state applies after 20 M_CK[2:0] periods after M_RST# is asserted. For more details,

refer to the MCU Chapter of the Intel^®80321 I/O Processor Developer’s Manual.

Datasheet

January 2005

15

Intel^®80321 I/O Processor

Package Information

Table 4.

Peripheral Bus Interface Signals (Sheet 1 of 3)

Name

Count

Type

Description

AD[31:0]

32

I/O

ADDRESS / DATA BUS During an address cycle bits 31-2 contain the

Sync(PB) physical word address and bits 1-0 specify the number of data transfers

Rst(M) during the bus transaction.

00= 1 Transfer

01= 2 Transfers

10= 3 Transfers

11= 4 Transfers.

During a data cycle bits 31-0, 15-0 or 7-0 contain valid data, depending on

the corresponding 32-, 16- or 8-bit bus width. During 16- and 8-bit bus

write operations the unused bus pins are driven to determinate values.

A[3:2]

2

4

O

ADDRESS [3:2] carries a demultiplexed version of bits 3 and 2 of the

Sync(PB) address bus. During an address cycle A[3:2] matches AD[3:2]. During a

Rst(M) bursted read or write data cycle A[3:2] represents the current DWORD

address in the bursted transaction.

BE[3:0]#

O

BYTE ENABLES select which of up to four data bytes on the bus

Sync(PB) participate in the current bus access. The byte enables are asserted

Rst(M) during the address cycle. These signals do not toggle during a burst and

they remain active through the last data cycle. Byte enable encoding is

dependent on the bus width:

32-bit bus:

•

BE[3]# enables data on AD[31:24]

BE[2]# enables data on AD[23:16]

BE[1]# enables data on AD[15:8]

BE[0]# enables data on AD[7:0]

16-bit bus:

•

BE[3]# enables data on AD[15:8]

BE[2]# is not used (state is high)

BE[1]# becomes Address Bit 1 (A[1])

BE[0]# enables data on AD[7:0]

8-bit bus:

•

BE[3]# is not used (state is high)

BE[2]# is not used (state is high)

BE[1]# becomes Address Bit 1 (A[1])

BE[0]# becomes Address Bit 0 (A[0])

For 16- and 8-bit bus accesses these address bits are asserted in

conjunction with A[3:2].

ALE

1

O

ADDRESS LATCH ENABLE indicates the transfer of a physical address.

Sync(PB) The pin is asserted during the first address cycle and deasserted during

Rst(M) the second address cycle. The pin floats whenever the bus is relinquished

to an external device

ADS#

O

ADDRESS STROBE indicates a valid address and the start of a new bus

Sync(PB) access. The pin is asserted during the second address cycle and

Rst(M) deasserted during the first data cycle. The pin floats whenever the bus is

relinquished to an external device

PB_CLK

W/R#

1

O

PERIPHERAL BUS CLOCK is the reference clock for all signals on the

peripheral bus.

O

WRITE / READ indicates whether the bus access is a write or a read with

Sync(PB) respect to the 80321 and is valid during the entire bus access. This pin

Rst(M) may be used to control the OE# input on the flash ROM. The pin floats

whenever the bus is relinquished to an external device

0 = Read

1 = Write

16

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 4.

Peripheral Bus Interface Signals (Sheet 2 of 3)

Name

FWE#

Count

Type

Description

FLASH WRITE ENABLE indicates whether the bus access is a write or a

1

O

Sync(PB) read with respect to the 80321 and is valid during the entire bus access.

Rst(M) This pin is used for flash memory accesses and controls the SWE# input

on the ROM. The pin floats whenever the bus is relinquished to an

external device.

0 = Write

1 = Read

DEN#

1

O

DATA ENABLE indicates data transfer cycles during a bus access. DEN#

Sync(PB) is asserted at the start of the first data cycle and deasserted at the end of

Rst(M) the last data cycle. The pin is used to provide control for data transceivers

connected to the bus. The pin floats whenever the bus is relinquished to

an external device

BLAST#

1

O

BURST LAST indicates the last data transfer of a bus access. BLAST#

Sync(PB) remains active when wait states are inserted and becomes inactive after

Rst(M) the final data transfer is complete. The pin floats whenever the bus is

relinquished to an external device

RDYRCV#

I/O

READY / RECOVER During a data cycle the pin indicates that data may

Sync(PB) be sampled or removed.

Rst(M)

0 = Sample data

1 = Insert wait state

During a recover state the pin indicates that the recover state is repeated.

This function allows slow external devices longer to float their pins before

the next address is driven.

0 = Insert recovery state

1 = Recovery complete

NOTE: PBI Base Address Register 0 bit 9 (Flash Window Enable) is

enabled for flash by default to support the boot process. See PBBAR0

description in the 80321 I/O Processor Developer’s Manual.

HOLD

1

I

HOLD is used by an external device to request access to the bus.

Sync(PB)

HOLDA

O

HOLD ACKNOWLEDGE indicates to an external device that it has been

Sync(PB) granted access to the bus.

Rst(M)

PB_RST#

1

O

PERIPHERAL BUS RESET indicates when the peripheral bus has been

Async reset with P_RST# or a software reset.

PCE[5]# /

I/O

PERIPHERAL CHIP ENABLES specify which of the six memory address

Sync(PB) ranges are associated with the current bus access. The pin remains valid

Rst(M) during the entire bus access.

PBI100MHZ#

PERIPHERAL BUS 100 MHz ENABLE is latched at the deasserting edge

of P_RST# and it indicates the speed at which the PBI bus operates.

(Configuration

Pin)

[PBI100MHZ#, PBI66MHZ#]

11 = 33 MHz

10 = 66 MHz

01 = 100 MHz

00 = Undefined

(Default Mode)

(Reserved - Do Not Use)

PCE[4]# /

1

I/O

PERIPHERAL CHIP ENABLES specify which of the six memory address

Sync(PB) ranges are associated with the current bus access. The pin remains valid

Rst(M) during the entire bus access.

PBI66MHZ#

PERIPHERAL BUS 66MHz ENABLE is latched at the deasserting edge

of P_RST# and it indicates the speed at which the PBI bus operates.

(Configuration

Pin)

[PBI100MHZ#, PBI66MHZ#]

11 = 33 MHz

10 = 66 MHz

01 = 100 MHz

00 = Undefined

(Default Mode)

(Reserved - Do Not Use)

Datasheet

January 2005

17

Intel^®80321 I/O Processor

Package Information

Table 4.

Peripheral Bus Interface Signals (Sheet 3 of 3)

Name

Count

Type

Description

PCE[3]# /

1

O

PERIPHERAL CHIP ENABLES specify which of the six memory address

Sync(PB) ranges are associated with the current bus access. The pin remains valid

Rst(M) during the entire bus access.

P_BOOT16#

PERIPHERAL BUS BOOT WIDTH 16 ENABLE specifies the width of the

peripheral bus for flash accesses during boot up.

(Configuration

Pin)

0 = 16-bit bus width

1 = 8-bit bus width

(Requires Pull-Down Resistor)

(Default Mode)

PCE[2]# /

1

I/O

PERIPHERAL CHIP ENABLES specify which of the six memory address

Sync(PB) ranges are associated with the current bus access. The pin remains valid

Rst(M) during the entire bus access.

32BITPCI#

32 BIT PCI is latched at the deasserting edge of P_RST# and it indicates

the width of the PCI-X bus to the PCI-X Status Register (bit 16 of the

PCI-X Status Register).

(Configuration

Pin)

0 = 32-Bit PCI-X Bus (Requires pull-down resistor)

1 = 64-Bit PCI-X Bus (Default mode)

PCE[1]# /

1

I/O

PERIPHERAL CHIP ENABLES specify which of the six memory address

Sync(PB) ranges are associated with the current bus access. The pin remains valid

Rst(M) during the entire bus access.

RETRY

RETRY is latched at the deasserting edge of P_RST# and it determines

when the Primary PCI interface disables PCI configuration cycles by

signaling a Retry until the Configuration Cycle Retry bit is cleared in the

PCI Configuration and Status Register.

(Configuration

Pin)

0 = Configuration Cycles enabled (Requires pull-down resistor)

1 = Retry enabled (Default mode)

PCE[0]# /

1

I/O

PERIPHERAL CHIP ENABLES specify which of the six memory address

Sync(PB) ranges are associated with the current bus access. The pin remains valid

Rst(M) during the entire bus access.

RST_MODE#

RESET MODE is latched at the deasserting edge of P_RST# and it

determines when the 80321 is held in reset until the Intel XScale^®

microprocessor Reset bit is cleared in the PCI Configuration and Status

Register.

(Configuration

Pin)

0 = Hold in reset (Requires pull-down resistor)

1 = Don’t hold in reset (Default mode)

WIDTH[1:0]

2

O

WIDTH denotes the physical memory attributes for a bus transaction. The

Sync(PB) pins float whenever the bus is relinquished to an external device.

Rst(M)

00 = 8 Bits Wide

01 = 16 Bits Wide

10 = 32 Bits Wide

11 = Reserved

18

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 5.

PCI Bus Signals (Sheet 1 of 2)

Name

Count

Type

Description

PCI ADDRESS/DATA is the multiplexed PCI address and bottom 32 bits

P_AD[31:0]

32

I/O

Sync(P) of the data bus.

Rst(P)

P_AD[63:32]

P_PAR

32

1

I/O

PCI DATA is the upper 32 bits of the PCI data bus driven during the data

Sync(P) phase.

Rst(P)

I/O

PCI BUS PARITY is even parity across P_AD[31:0] and P_C/BE[3:0]#.

Sync(P)

Rst(P)

P_PAR64

1

I/O

PCI BUS UPPER DWORD PARITY is even parity across P_AD[63:32]

Sync(P) and P_C/BE[7:4]#.

Rst(P)

P_C/BE[3:0]#

P_C/BE[7:4]#

4

I/O

PCI BUS COMMAND and BYTE ENABLES are multiplexed on the same

Sync(P) PCI pins. During the address phase, they define the bus command. During

Rst(P) the data phase, they are used as byte enables for P_AD[31:0].

4

I/O

PCI BUS BYTE ENABLES are as byte enables for P_AD[63:32] during

Sync(P) the data phase.

Rst(P)

P_REQ#

1

O

PCI BUS REQUEST indicates to the PCI bus arbiter that the 80321

Rst(P) desires use of the PCI bus.

P_REQ64#

I/O

PCI BUS REQUEST 64-BIT TRANSFER indicates the attempt of a 64-bit

Sync(P) transaction on the PCI bus. When the target is 64-bit capable, the target

Rst(P) acknowledges the attempt with the assertion of P_ACK64#.

P_GNT#

1

I

PCI BUS GRANT indicates that access to the PCI bus has been granted.

PCI BUS ACKNOWLEDGE 64-BIT TRANSFER indicates that the device

Sync(P)

P_ACK64#

I/O

Sync(P) has positively decoded its address as the target of the current access and

Rst(P) the target transfers data using the full 64-bit data bus.

P_FRAME#

P_IRDY#

1

I/O

PCI BUS CYCLE FRAME is asserted to indicate the beginning and

Sync(P) duration of an access.

Rst(P)

I/O

PCI BUS INITIATOR READY indicates the initiating agent’s ability to

Sync(P) complete the current data phase of the transaction. During a write, it

Rst(P) indicates that valid data is present on the Address/Data bus. During a

read, it indicates the processor is ready to accept the data.

P_TRDY#

1

I/O

PCI BUS TARGET READY indicates the target agent’s ability to complete

Sync(P) the current data phase of the transaction. During a read, it indicates that

Rst(P) valid data is present on the Address/Data bus. During a write, it indicates

the target is ready to accept the data.

P_STOP#

1

I/O

PCI BUS STOP indicates a request to stop the current transaction on the

Sync(P) PCI bus.

Rst(P)

P_DEVSEL#

P_SERR#

I/O

PCI BUS DEVICE SELECT is driven by a target agent that has

Sync(P) successfully decoded the address. As an input, it indicates whether or not

Rst(P) an agent has been selected.

I/O

OD

PCI BUS SYSTEM ERROR is driven for address parity errors on the PCI

bus.

Sync(P)

Rst(P)

P_CLK

1

I

PCI BUS INPUT CLOCK provides the timing for all PCI transactions and

is the clock source for most internal 80321 units.

Datasheet

January 2005

19

Intel^®80321 I/O Processor

Package Information

Table 5.

PCI Bus Signals (Sheet 2 of 2)

Name

P_RST#

Count

Type

Description

1

I

RESET brings PCI-specific registers, sequencers, and signals to a

Async consistent state. When P_RST# is asserted: PCI output signals are driven

to a known consistent state.

PCI bus interface output signals are three-stated.

Open drain signals such as P_SERR# are floated. P_RST# may be

asynchronous to P_CLK when asserted or deasserted. Although

asynchronous, deassertion must be guaranteed to be a clean, bounce-free

edge.

P_PERR#

1

I/O

PCI BUS PARITY ERROR is asserted when a data parity error occurs

Sync(P) during a PCI bus transaction.

Rst(P)

P_IDSEL

1

4

I

PCI BUS INITIALIZATION DEVICE SELECT is used to select the 80321

Sync(P) during a Configuration Read or Write command on the PCI bus.

P_INT[A:D]#

O

PCI BUS INTERRUPT requests an interrupt. The assertion and

OD

deassertion of P_INT[A:D]# is asynchronous to P_CLK. A device asserts

Async its P_INT[A:D]# line when requesting attention from its device driver. Once

Rst(P) the P_INT[A:D]# signal is asserted, it remains asserted until the device

driver clears the pending request. P_INT[A:D]# Interrupts are level

sensitive.

P_M66EN

1

I

PCI BUS 66 MHz ENABLE indicates the speed of the PCI bus. When this

signal is sampled high the PCI bus speed is 66 MHz, when low the bus

speed is 33 MHz.

Table 6.

Serial Port Interface Signals

Name

Count

Type

Description

SSCKO

SFRM

1

O

SERIAL PORT CLOCK OUT is the output bit-rate clock.

O

SERIAL FRAME indicates the beginning and end of a serial data word.

Sync(SS)

Rst(M)

TXD

1

O

TRANSMIT DATA is the outbound serial data pin.

RECEIVE DATA is the inbound serial data pin.

Sync(SS)

Rst(M)

RXD

1

I

Sync(SS)

SSCKI

I

SERIAL PORT CLOCK IN is the input bit-rate clock which may be used

when a frequency other than the default of 3.7 MHz is needed.

20

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 7.

Miscellaneous Signals (Sheet 1 of 2)

Name

Count

Type

Description

PCI-X Bus Master Indicator is an output used for hiding an I/O Controller

P_BMI

1

O

Async on the same bus segment as the 80321 by controlling the IDSEL line of

Rst(M) that I/O Controller. The output state of this signal is controlled by bit 0 of

the GPOD register and the default state at Reset is 0. When not being

used, this pin will be a NC. Please see the 80321 Specification Update,

Specification Clarification section for more details.

XINT[3:0]#

4

I

EXTERNAL INTERRUPT REQUESTS are used by external devices to

Async request interrupt service. These pins are level-detect only and are

internally synchronized. These interrupts may be directed to either the

PCI pins P_INT[A:D]# or to the 80321 interrupt controller pins XINT[3:0]#

as shown below.

XINT[0]# ⇒ P_INT[A]# or XINT[0]#

XINT[1]# ⇒ P_INT[B]# or XINT[1]#

XINT[2]# ⇒ P_INT[C]# or XINT[2]#

XINT[3]# ⇒ P_INT[D]# or XINT[3]#

HPI#

1

4

1

I

HIGH PRIORITY INTERRUPT causes a high priority non-maskable

Async interrupt to the 80321. This pin is level-detect only and is internally

synchronized.

GPIO[3:0]

I/O

GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on

Async a per pin basis as general purpose inputs or outputs. The default mode is

Rst(M) a general purpose input.

GPIO[4] /

I/O

GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on

Async a per pin basis as general purpose inputs or outputs. The default mode is

Rst(P) a general purpose input.

SDA1

I²C DATA is used for data transfer and arbitration on the I²C bus. This is

I/O

OD

Rst(M)

one of two I²C buses that the user may enable. 2.7K pull-up is required.

GPIO[5] /

1

I/O

GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on

Async a per pin basis as general purpose inputs or outputs. The default mode is

Rst(P) a general purpose input.

I/O

SCL1

I²C CLOCK provides synchronous operation of the I²C bus. This is one of

two I²C buses that the user may enable. 2.7K pull-up is required.

OD

Rst(M)

GPIO[6] /

I/O

GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on

Async a per pin basis as general purpose inputs or outputs. The default mode is

Rst(P) a general purpose input.

I/O

OD

SDA0

I²C DATA is used for data transfer and arbitration on the I²C bus. This is

one of two I²C buses that the user may enable. 2.7K pull-up is required.

Rst(M)

GPIO[7] /

I/O

GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on

Async a per pin basis as general purpose inputs or outputs. The default mode is

Rst(P) a general purpose input.

SCL0

I²C CLOCK provides synchronous operation of the I²C bus. This is one of

I/O

OD

Rst(M)

two I²C buses that the user may enable. 2.7K pull-up is required.

TCK

TDI

1

I

TEST CLOCK is an input which provides the clocking function for the

Rst(T) IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data

are clocked into the component on the rising edge and data is clocked out

of the component on the falling edge.

I

TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is

Sync(T) sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR

Rst(T) states of the Test Access Port. This signal has a weak internal pull-up to

ensure proper operation when this signal is unconnected.

TDO

O

TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO is

Sync(T)R driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR

st(T)

states of the Test Access Port. At other times, TDO floats. The behavior of

TDO is independent of P_RST#.

Datasheet

January 2005

21

Intel^®80321 I/O Processor

Package Information

Table 7.

Miscellaneous Signals (Sheet 2 of 2)

Name

Count

Type

Description

TRST#

1

I

TEST RESET asynchronously resets the Test Access Port (TAP)

Asyn

controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). This

Rst(T) signal has a weak internal pull-up.

TMS

1

I

TEST MODE SELECT is sampled at the rising edge of TCK to select the

Sync(T) operation of the test logic for IEEE 1149.1 Boundary Scan testing. This

Rst(T) signal has a weak internal pull-up to ensure proper operation when this

signal is unconnected.

RCOMP

PWRDELAY

POR#

1

I

RESISTER COMPENSATION is connected through a 30.1 Ω 1% 1/4 W

resister to ground. This is used to minimize the PCI pin variations due to

voltage and temperature variations.

I

POWER FAIL DELAY is used with external delay circuits to delay the

Async reset of the memory controller in a power-fail condition. This allows the

self-refresh command to be sent to the DDR SDRAM array.

I

POWER ON RESET should be tied to the 1.3 V supply. It is used to

provide clocks to the core from an internal ring oscillator during power up,

which prevents internal contention. It also tristates the other pins to

prevent external power sequencing contention.

NC[2:0]

V_CCPLL1

3

1

I/O

NO CONNECT pins have no usable function. However they are in the

boundary scan chain and must not be connected to any signal, power or

ground.

PWR

PLL POWER is a separate V_CC13supply ball for the phase lock loop clock

generator. It is to be connected to the board V_CC13plane. In noisy

environments, add a simple bypass filter circuit to reduce noise-induced

clock jitter and its effects on timing relationships.

V_CCPLL2

1

PWR

PLL POWER is a separate V_CC13supply ball for the phase lock loop clock

generator. It is to be connected to the board V_CC13plane. In noisy

environments, add a simple bypass filter circuit to reduce noise-induced

clock jitter and its effects on timing relationships.

V_CC33

V_CC25

V_CC13

V_SS

51

38

PWR

GND

3.3 V POWER balls to be connected to a 3.3 V power board plane.

2.5 V POWER balls to be connected to a 2.5 V power board plane.

1.3 V POWER balls to be connected to a 1.3 V power board plane.

GROUND balls to be connected to a ground board plane.

34

118

22

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 8.

Pin Mode Behavior (Sheet 1 of 2)

Reset

Norm

Hold

32-Bit PCI

32-Bit Mem

ECC Off

RCVENI#

RCVENO#

M_CK[2:0]

M_CK[2:0]#

M_RST#

SA[12:0]

SBA[1:0]

SRAS#

VI

1*

VO

0

VI

-

VO

VB

VO

VB

VO

VI

-

0*

1*

0*

Z*

0

-

SCAS#

-

SWE#

-

SCE[1:0]#

SCKE[1:0]

DQ[63:32]

Q[31:0]

-

ID

-

SCB[7:0]

DQS[7:4]

DQS[3:0]

DQS[8]

-

ID

-

ID

-

ID

-

SDQM[7:4]

SDQM[3:0]

SDQM[8]

AD[31:16]

AD[15:8]

AD[7:0]

-

Z

-

Z

-

Z

-

0

-

0

-

A[3:2]

0

-

BE[3:0]#

ALE

1

-

0

-

ADS#

1

-

PB_CLK

W/R#

VO

0

-

Z

-

FWE#

1

-

DEN#

1

-

BLAST#

RDYRCV#

HOLD

1

-

VO

VI

VO

0

-

VI

-

HOLDA

VO

1

-

PB_RST#

-

PCE[5]# /

H

1

-

PBI100MHZ#

PCE[4]# /

PBI66MHZ#

H

0

VO

1

Z

-

PCE[3]# /

P_BOOT16#

PCE[2]# /

32BITPCI#

PCE[1]# /

RETRY

PCE[0]# /

RST_MODE#

WIDTH[1:0]

Datasheet

January 2005

23

Intel^®80321 I/O Processor

Package Information

Table 8.

Pin Mode Behavior (Sheet 2 of 2)

Reset

Norm

Hold

32-Bit PCI

32-Bit Mem

ECC Off

P_AD[63:32]

P_AD[31:16]

P_AD[15:0]

P_PAR

Z

VB

VO

VB

VI

-

H

-

H

-

H

-

Z

P_PAR64

P_C/BE[3:0]#

P_C/BE[7:4]#

P_REQ#

P_REQ64#

P_GNT#

P_ACK64#

P_FRAME#

P_IRDY#

P_TRDY#

P_STOP#

P_DEVSEL#

P_SERR#

P_CLK

Z

VI

Z

VB

VI

Z

VI

Z

P_RST#

P_PERR#

P_IDSEL

P_INT[A:D]#

P_M66EN

SSCKO

VI

VB

VI

Z

VO

VI

VO

VI

0

VO

VI

SFRM

TXD

RXD

SSCKI

VI

P_BMI

VO

VI

XINT[3:0]#

HPI#

VI

H

VI

GPIO[7]

GPIO[6]

GPIO[5]

GPIO[4:0]

TCK

VB

VI

TDI

H

TDO

Z

VO

H

TRST#

H

TMS

H

PWRDELAY

NC[2:0]

VI

H

VI

H

NOTES:

NOTES:(continued)

L = pulled down to V_SS

1 = driven to V_CC

0 = driven to V_SS

Z = output disabled (Floats)

X = driven to unknown state

ID = The input is disabled

H = pulled up to V_CC

PD = pull-up disabled

VB = acts like a Valid Bidirectional pin.

VO = a Valid Output level is driven.

VI = Need to drive a Valid Input level.

* = After power fail sequence completes.

** = Caused by Hi-Z from mode pins only.

24

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

3.1.2

544-Lead PBGA Package

Figure 2.

544-Lead PBGA Package (Top View)

0.127 C

-A-

Pin A1

Corner

35.00 ± 0.20

35.00 ± 0.25

-B-

Pin 1 ID

22.00 REF

0.127 A

45º Chamfer

(4 places)

22.00 REF

TOP VIEW

30º

2.38 ± 0.21

1.17 ± 0.05

0.61 ± 0.06

0.15 C

-C-

0.20

2

SIDE VIEW

0.60 ± 0.10

Seating Plane

B1100-01

Datasheet

January 2005

25

Intel^®80321 I/O Processor

Package Information

Figure 3.

544-Lead PBGA Package (Bottom View)

Pin #1Corner

0.90

0.60

26

24

22

20

18

16

14

12

10

8

6

4

2

ø

25

23

21

19

17

15

13

11

9

7

5

3

1

ø

0.30 S C A S B S

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

1.27

W

Y

AA

AB

AC

AD

AE

AF

1.63 REF

ø

1.0

(3 places)

1.63 REF

1.27

A9257-01

26

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Figure 4.

Ball Map - Left Side - Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

SDQM

8

SDQM

3

SA1

DQ35 DQ38

DQ34 DQ33 VREF SCB3

SCB0

SA2

DQ30T

DQ28

A

B

REV

SA0

DQ39

DQS4

DQS8

SA3

DQ29

VSS

VENO#

SDQM

4

SA10

VCC25

DQ36 VCC25 SCB7 SCB1 VCC25 SA4

DQ27 VCC25 DQ24

VSS

C

D

E

REV

SRAS# SBA0

SBA1

DQ37 DQ32

SCB2 SCB5

DQ31 DQ26 DQ25

SA6

SA5

VSS

VENI#

SCB6

DQ45

DQ44 DQ40 VCC25

SCB4

DQS3

VSS

SDQM5 DQS5 VCC25 DQ41

VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25

VSS

F

G

H

DQ46

DQ47 DQ43 DQ42 VCC25 VCC13 VCC13 VCC13 VCC13

VSS

DQ49 DQ48 SCAS# SWE#

VCC25 VCC13

VSS

DQS6

VCC25 DQ53 DQ52 VCC25 VCC13

VSS

J

K

L

M

N

P

R

T

DQ50 DQ54 SDQM6 DQ55

VCC25 VCC13

VSS

DQ60

DQ51 SCE1# SCE0# VCC25

VSS

DQ57 DQ61 VCC25 DQ56

VSS

VCC25

VSS

DQ62

DQ59

DQ58 SDQM7 DQS7

M_

CK2#

DQ63

VSS VCC25

CK2

M_

CK1

M_

CK0#

M_

VCC13

P_

VSS

VCC25

CK0

M_

P_

RCOMP VSS

VCC33

CK1# INTB# INTA#

P_

INTD#

R_

VSS

VCC33 VCC13

U

REQ# INTC# RST#

P_

AD31

P_

GNT#

P_

AD30

VCC33

VSS

P_

VCC33 VCC13

V

W

Y

P_

AD29

P_

VSS

AD27 AD28 AD26

P_

VSS

P_

VCC13 VCC13 VCC13

VCC13

VCC33

AD25 CBE3# AD24 IDSEL

P_

VSS VCC33

P_ P_

VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC13 VCC33

AA AD23

AD22 AD20

P_

AD9

P_

AD4

P_

CBE7#

P_

AD62

VSS

P_

VSS

P_

AB

AD19 AD21 AD18 AD16

P_

REQ64

#

P_

AD17

P_

AD2

P_

AD0

P_

VSS FRAME

#

AC

AD

AE

AF

TRDY# AD13 CBE0# CLK

PAR64 CBE4# AD58

P_

M66EN

P_

AD3

P_

AD6

P_

CBE5#

P_

AD60

P_

CBE2#

VCC33

STOP#

VCC33

AD15 AD11

P_

ACK64#

P_

IRDY#

P_

AD14

VCC

PLL2

P_

AD7

P_

AD61

VSS

PAR

VSS

P_

DEV

SEL#

P_

VCC

PLL1

PERR# SERR# CBE1#

AD12 AD10

AD8

AD5

AD1

CBE6# AD63 AD59

1

2

3

4

5

6

7

8

9

10

11

12

13

B1102-01

Datasheet

January 2005

27

Intel^®80321 I/O Processor

Package Information

Figure 5.

Ball Map - Right Side - Top View

14

15

16

17

18

19

20

21

22

23

24

25

26

SA8

DQ18 DQS2 DQ20 SCKE0 DQ14

DQS1 DQS8 DQS6 DQS0

DQ5

DQ0

AD31

A

SA7

DQ21

SCKE1

DQ13

DQ2

DQ4

AD30

AD28

AD26

AD23

VSS

B

DQ23 VCC25 DQ17

SA9 VCC25 SDQM1 DQ12 VCC25 SDQM0 DQ1 VCC25 AD29

C

D

E

M-

RST#

AD25

BE3#

AD27

DQ19 SDQM2 DQ16 SA11 DQ11 DQ15

DQ9

DQ7

VSS

AD22 AD24

VSS

DQ22

VSS

DQ10

VSS

DQ3

VSS

SA12

VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 BE2# AD21

VCC23

AD20

AD18

AD15

AD12

VSS

F

VSS

BE1# AD17 AD19

VCC13 VCC13 VCC13 VCC13 VCC33

VCC13 VCC33

G

WIDTH

1

AD14 AD16

VSS

H

VCC13 VCC33 VSS

AD11 VCC33 AD13

J

WIDTH

VCC13 VCC33

AD8

AD10

AD5

AD9

AD8

AD3

AD1

ALE

VSS

AD7

K

L

0

VCC33 VSS

BE0#

VSS

VCC13

A3

AD4 VCC33 VSS

M

N

P

R

T

VCC33 VSS

A2

AD0

AD2

VSS

ADS#

VCC13 FWE# W/R#

RDY

VCC33 VSS

RCV#

BLAST

#

VCC33

DEN#

PB_

RST#

PB_

CLK

HOLDA HOLD VSS

VCC13 VCC33 VSS

PCE5# PCE4# PCE3# PCE2#

U

VCC13 VCC33 PCE0#

VCC13 VCC33 VSS

NC0

PCE1#

VCC33 VSS

V

GPIO7 GPIO6 GPIO5 GPIO4

W

Y

GPIO3 GPIO2 GPIO1

VSS

GPIO0

TXD

VCC13 VCC13 VCC13 VCC13 VCC33

SFRM

RXD

VCC13 VCC33 VCC13 VCC33 VCC33 VCC33 VCC33 VCC33 VSS

VCC33

AA

AB

AC

AD

P_

AD54

P_

AD48

P_

AD40

P_

AD32

VSS

P_

VSS

P_

VSS

P_

VSS VCC33

HPI# SSCKI VSS SSCKO

P_

XINT XINT

3# 2#

XINT

1#

TDO TRST#

VSS

AD56 AD52

AD50 AD44 AD42

AD36 AD34

P_

AD57

P_

AD49

P_

AD46

P_ P_

AD38 AD35

XINT

0#

VCC33

VCC33 TCK

NC1 VCC33 VSS

P_

AD53

P_

AD45

P_

AD39

P_

BMI

VSS

TDI

VCC33 VCC33 AE

P_

AD47

P_

PWR

POR#

TMS

VCC33 VCC33 VCC33

DELAY

AF

AD55 AD51

AD43 AD41

AD37 AD33

14

15

16

17

18

19

20

21

22

23

24

25

26

B1103-01

28

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 9.

544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 1 of 5)

Ball

Signal

Ball

Signal

Ball

Signal

A1

A2

SA1

DQ35

DQ38

DQ34

DQ33

V_REF

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

V_SS

SA7

C25

C26

D1

AD29

AD28

SRAS#

SBA0

SBA1

V_SS

A3

V_SS

A4

DQ21

V_SS

D2

A5

D3

A6

SCKE1

V_SS

D4

A7

SCB3

SDQM8

SCB0

SA2

D5

DQ37

DQ32

RCVENI#

SCB2

SCB5

DQ31

DQ26

DQ25

SA6

A8

DQ13

V_SS

D6

A9

D7

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

DQ2

D8

DQ30

SDQM3

DQ28

SA8

V_SS

D9

DQ4

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

V_SS

AD30

SA10

V_SS

DQ18

DQS2

DQ20

SCKE0

DQ14

DQS1

DQ8

C2

DQ19

SDQM2

DQ16

SA11

DQ11

DQ15

DQ9

C3

V_CC25

SDQM4

DQ36

V_CC25

SCB7

SCB1

V_CC25

SA4

C4

C5

C6

C7

DQ6

C8

DQS0

DQ5

C9

M_RST#

DQ7

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

DQ0

DQ27

V_CC25

DQ24

DQ23

V_CC25

DQ17

SA9

AD25

AD27

V_SS

AD31

SA0

B2

DQ39

V_SS

AD26

DQ45

V_SS

B3

B4

DQS4

V_SS

E2

B5

E3

DQ44

DQ40

V_CC25

V_SS

B6

RCVENO#

V_SS

V_CC25

SDQM1

DQ12

V_CC25

SDQM0

DQ1

E4

B7

E5

B8

DQS8

V_SS

E6

B9

E7

SCB6

V_SS

B10

B11

B12

SA3

E8

V_SS

E9

SCB4

V_SS

DQ29

V_CC25

E10

Datasheet

January 2005

29

Intel^®80321 I/O Processor

Package Information

Table 9.

544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 2 of 5)

Ball

Signal

Ball

Signal

Ball

Signal

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

DQS3

V_SS

F23

F24

F25

F26

G1

AD21

V_CC33

V_SS

J1

J2

DQS6

V_SS

SA5

J3

V_CC25

DQ53

DQ52

V_CC25

V_CC13

V_CC33

V_SS

AD20

DQ46

V_SS

J4

DQ22

V_SS

J5

G2

J6

SA12

V_SS

G3

DQ47

DQ43

DQ42

V_CC25

V_CC13

V_CC33

V_SS

J7

G4

J20

J21

J22

J23

J24

J25

J26

K1

DQ10

V_SS

G5

G6

DQ3

G7

AD11

V_CC33

AD13

AD12

DQ50

DQ54

SDQM6

DQ55

V_SS

G8

BE3#

AD22

AD24

AD23

SDQM5

DQS5

V_CC25

DQ41

V_SS

G9

G10

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

H1

K2

K3

F2

K4

F3

K5

F4

K6

V_CC25

V_CC13

V_CC33

WIDTH0

AD8

F5

BE1#

AD17

AD19

AD18

DQ49

DQ48

SCAS#

SWE#

V_SS

K7

F6

V_CC25

BE2#

K20

K21

K22

K23

K24

K25

K26

L1

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

H2

AD10

V_SS

H3

H4

AD9

H5

DQ60

V_SS

H6

V_CC25

V_CC13

V_CC33

WIDTH1

AD14

AD16

V_SS

L2

H7

L3

DQ51

SCE1#

SCE0#

V_CC25

V_SS

H20

H21

H22

H23

H24

H25

H26

L4

L5

L6

L11

L12

L13

L14

V_SS

AD15

V_SS

30

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 9.

544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 3 of 5)

Ball

Signal

Ball

Signal

Ball

Signal

L15

L16

L21

L22

L23

L24

L25

L26

M1

V_SS

N21

N22

N23

N24

N25

N26

P1

V_CC33

V_SS

R23

R24

R25

R26

T1

RDYRCV#

V_CC33

V_SS

A2

BLAST#

DEN#

AD0

BE0#

AD5

AD2

M_CK1#

P_INTB#

P_INTA#

RCOMP

V_SS

AD1

T2

AD7

DQ59

M_CK2#

M_CK2

DQ63

V_SS

T3

AD6

P2

T4

DQ57

DQ61

V_CC25

DQ56

V_SS

P3

T5

M2

P4

T6

V_CC33

M3

P5

T11

T12

T13

T14

T15

T16

T21

T22

T23

T24

T25

T26

U1

V_SS

M4

P6

V_CC25

V_SS

M5

P11

P12

P13

P14

P15

P16

P21

P22

P23

P24

P25

P26

R1

V_SS

M6

V_CC25

V_SS

M11

M12

M13

M14

M15

M16

M21

M22

M23

M24

M25

M26

N1

V_SS

V_CC13

V_SS

PB_RST#

HOLDA

HOLD

V_SS

V_CC13

FWE#

W/R#

ADS#

V_SS

V_CC13

A3

PB_CLK

P_INTD#

V_SS

AD4

V_CC33

V_SS

ALE

U2

M_CK1

V_SS

U3

P_REQ#

P_INTC#

P_RST#

V_CC33

AD3

R2

U4

DQ62

V_SS

R3

V_CC25

M_CK0#

M_CK0

V_CC25

V_SS

U5

N2

R4

U6

N3

DQ58

SDQM7

DQS7

V_CC25

V_SS

R5

U7

V_CC13

N4

R6

U20

U21

U22

U23

U24

U25

U26

V1

V_CC13

N5

R11

R12

R13

R14

R15

R16

R21

R22

V_CC33

N6

V_SS

N11

N12

N13

N14

N15

N16

V_SS

PCE5#

PCE4#

PCE3#

PCE2#

P_AD31

P_GNT#

V_SS

V_CC33

V_SS

V2

Datasheet

January 2005

31

Intel^®80321 I/O Processor

Package Information

Table 9.

544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 4 of 5)

Ball

Signal

Ball

Signal

Ball

Signal

V3

V4

V_CC33

P_AD30

V_SS

Y19

Y20

V_CC13

V_CC33

GPIO3

GPIO2

GPIO1

V_SS

AB5

AB6

V_SS

P_AD9

V_SS

V5

Y21

AB7

V6

V_CC33

V_CC13

V_CC33

PCE0#

NC0

Y22

AB8

P_AD$

V_SS

V7

Y23

AB9

V20

V21

V22

V23

V24

V25

V26

W1

W2

W3

W4

W5

W6

W7

W20

W21

W22

W23

W24

W25

W26

Y1

Y24

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

P_CBE7#

V_SS

Y25

Y26

GPIO0

P_AD23

V_SS

P_AD62

V_SS

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

AB2

AB3

AB4

V_CC33

V_SS

P_AD54

V_SS

V_CC33

P_AD22

P_AD20

V_CC33

V_CC13

V_CC33

V_CC13

V_CC33

V_CC13

V_CC33

V_SS

PCE1#

P_AD29

V_SS

P_AD48

V_SS

P_AD40

V_SS

P_AD27

P_AD28

P_AD26

V_CC33

V_CC13

V_CC33

V_SS

P_AD32

V_SS

V_CC33

HPI#

SSCKI

V_SS

SSCKO

P_AD17

V_SS

GPIO7

GPIO6

GPIO5

GPIO4

P_AD25

P_CBE3#

P_AD24

P_IDSEL

V_SS

AC2

AC3

P_FRAME#

P_TRDY#

P_AD13

P_CBE0#

P_CLK

P_AD2

P_AD0

P_REQ64#

P_PAR64

P_CBE4#

P_AD58

P_AD56

P_AD52

P_AD50

AC4

AC5

Y2

AC6

Y3

AC7

Y4

AC8

Y5

SFRM

V_CC33

RXD

AC9

Y6

V_CC33

V_CC13

AC10

AC11

AC12

AC13

AC14

AC15

AC16

Y7

Y8

TXD

Y9

P_AD19

P_AD21

P_AD18

P_AD16

Y10

Y17

Y18

32

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 9.

544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 5 of 5)

Ball

Signal

Ball

Signal

Ball

Signal

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

P_AD44

P_AD42

P_AD36

P_AD34

TDO

AD21

AD22

AD23

AD24

AD25

AD26

AE1

V_CC33

TCK

AE24

AE25

AE26

AF1

V_SS

V_CC33

NC1

V_CC33

V_SS

P_DEVSEL#

P_PERR#

P_SERR#

P_CBE1#

V_CCPLL1

P_AD12

P_AD10

P_AD8

AF2

TRST#

V_SS

XINT0#

P_IRDY#

V_SS

AF3

AF4

XINT3#

XINT2#

XINT1#

P_CBE2#

P_STOP#

V_CC33

AE2

AF5

AE3

P_PAR

V_SS

AF6

AE4

AF7

AE5

P_AD14

V_SS

AF8

AD2

AE6

AF9

P_AD5

AD3

AE7

V_CCPLL2

V_SS

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

P_AD1

AD4

P_AD15

P_AD11

V_CC33

AE8

P_CBE6#

P_AD63

P_AD59

P_AD55

P_AD51

P_AD47

P_AD43

P_AD41

P_AD37

P_AD33

POR#

AD5

AE9

P_AD7

V_SS

AD6

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AD7

P_AD6

P_M66EN

V_CC33

P_ACK64#

V_SS

AD8

AD9

P_AD61

V_SS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

P_AD3

P_CBE5#

V_CC33

P_AD53

V_SS

P_AD60

P_AD57

V_CC33

P_AD45

V_SS

P_AD39

V_SS

TMS

P_AD49

P_AD46

V_CC33

PWRDELAY

V_CC33

TDI

V_SS

V_CC33

P_AD38

P_AD35

P_BMI

V_CC33

Datasheet

January 2005

33

Intel^®80321 I/O Processor

Package Information

Table 10.

544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 1 of 5)

Signal

Ball

Signal

Ball

Signal

Ball

A2

N23

M22

N24

N26

N25

M26

M23

L24

L26

L25

K23

K26

K24

J23

BE2#

BE3#

BLAST#

DEN#

DQ0

F22

E23

R25

R26

A25

C23

B22

E21

B24

A24

A22

D22

A21

D20

E19

D18

C20

B20

A19

D19

D16

C16

A15

D14

A17

B16

E15

C14

C13

D12

D11

C11

A13

B12

A11

D10

D6

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

A4

A2

C5

D5

A3

B2

E4

F4

A3

AD0

AD1

AD2

AD3

DQ1

AD4

DQ2

AD5

DQ3

AD6

DQ4

G5

G4

E3

E1

G1

G3

H2

H1

K1

L3

AD7

DQ5

AD8

DQ6

AD9

DQ7

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

ADS#

ALE

DQ8

DQ9

J26

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

J25

H23

H26

H24

G24

G26

G25

F26

F23

E24

E26

E25

D23

D26

D24

C26

C25

B26

A26

P24

P26

L23

G23

J5

J4

K2

K4

M4

M1

N3

P1

L1

M2

N1

P4

A23

A20

A16

E11

B4

F2

BE0#

BE1#

J1

A5

N5

34

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 10.

544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 2 of 5)

Signal

Ball

Signal

Ball

Signal

Ball

DQS8

FWE#

B8

P22

Y26

Y24

Y23

Y22

W26

W25

W24

W23

T24

T23

AB23

R5

P_AD14

P_AD15

P_AD16

P_AD17

P_AD18

P_AD19

P_AD20

P_AD21

P_AD22

P_AD23

P_AD24

P_AD25

P_AD26

P_AD27

P_AD28

P_AD29

P_AD30

P_AD31

P_AD32

P_AD33

P_AD34

P_AD35

P_AD36

P_AD37

P_AD38

P_AD39

P_AD40

P_AD41

P_AD42

P_AD43

P_AD44

P_AD45

P_AD46

P_AD47

P_AD48

P_AD49

P_AD50

P_AD51

AE5

AD4

AB4

AC1

AB3

AB1

AA5

AB2

AA4

AA1

Y3

P_AD52

P_AD53

AC15

AE15

AB14

AF14

AC14

AD14

AC13

AF13

AD13

AE13

AB12

AF12

AC6

AF4

AD1

Y2

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

HOLD

P_AD54

P_AD55

P_AD56

P_AD57

P_AD58

P_AD59

P_AD60

P_AD61

P_AD62

HOLDA

HPI#

Y1

P_AD63

W5

P_CBE0#

P_CBE1#

P_CBE2#

P_CBE3#

P_CBE4#

P_CBE5#

P_CBE6#

P_CBE7#

P_CLK

M_CK0

M_CK0#

M_CK1

M_CK1#

M_CK2

M_CK2#

M_RST#

NC0

W3

R4

W4

R1

W1

T1

V4

AC12

AD11

AF11

AB10

AC7

AF1

AC3

V2

P3

V1

P2

AB20

AF20

AC20

AD20

AC19

AF19

AD19

AE19

AB18

AF18

AC18

AF17

AC17

AE17

AD17

AF16

AB16

AD16

AC16

AF15

D21

V23

AD23

AE23

AE11

AC9

AF10

AC8

AD10

AB8

AF9

AD7

AE9

AF8

AB6

AF7

AD5

AF6

AC5

NC1

P_DEVSEL#

P_FRAME#

P_GNT#

P_IDSEL

P_INTA#

P_INTB#

P_INTC#

P_INTD#

P_IRDY#

P_M66EN

P_PAR

P_BMI

P_ACK64#

P_AD0

P_AD1

P_AD2

P_AD3

P_AD4

P_AD5

P_AD6

P_AD7

P_AD8

P_AD9

P_AD10

P_AD11

P_AD12

P_AD13

Y4

T3

T2

U4

U1

AE1

AD8

AE3

AC11

AF2

U3

P_PAR64

P_PERR#

P_REQ#

P_REQ64#

P_RST#

AC10

U5

P_SERR#

AF3

Datasheet

January 2005

35

Intel^®80321 I/O Processor

Package Information

Table 10.

544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 3 of 5)

Signal

Ball

Signal

Ball

Signal

Ball

P_STOP#

P_TRDY#

PB_CLK

PB_RST#

PCE0#

PCE1#

PCE2#

PCE3#

PCE4#

PCE5#

POR#

AD2

AC4

T26

T22

V22

V26

U26

U25

U24

U23

AF21

AF23

D1

SCB4

SCB5

SCB6

SCB7

SCKE0

SCKE1

SCE0#

SCE1#

SDQM0

SDQM1

SDQM2

SDQM3

SDQM4

SDQM5

SDQM6

SDQM7

SDQM8

SFRM

SSCKI

SSCKO

TCK

E9

D9

V_CC13

V_CC25

J20

K7

E7

K20

U7

C7

A18

B18

L5

U20

V7

W7

W20

Y7

L4

C22

C19

D15

A12

C4

Y8

Y9

PWRDELAY

SRAS#

RCOMP

RCVENI#

RCVENO#

RDYRCV#

RXD

Y10

Y17

Y19

Y20

M21

P21

T21

V20

Y18

AA12

AA14

AA16

C3

T4

F1

D7

K3

B6

N4

R23

AA25

B1

A8

AA23

AB24

AB26

AD22

AE21

AC21

AF22

AC22

AA26

F20

G7

SA0

SA1

A1

SA2

A10

B10

C10

E13

D13

B14

A14

C17

C1

SA3

TDI

SA4

TDO

SA5

TMS

SA6

TRST#

TXD

C6

SA7

C9

SA8

V_CC25

V_CC13

C12

C15

C18

C21

C24

E5

SA9

SA10

G8

SA11

D17

E17

D2

G9

SA12

G10

G17

G18

G19

G20

H7

SBA0

SBA1

D3

F3

SCAS#

SCB0

H3

F6

A9

F7

SCB1

C8

F8

SCB2

D8

H20

J7

F9

SCB3

A7

F10

36

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

Table 10.

544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 4 of 5)

Signal

Ball

Signal

Ball

Signal

Ball

V_CC25

V_CC33

F11

F12

F13

F14

F15

F16

F17

F18

F19

F21

G6

V_CC33

V_CCPLL1

V_CCPLL2

V_REF

AA21

AA24

AB22

AD24

AA3

AA6

AA7

AA8

AA9

AA10

AA11

AA13

AA15

AA17

AA18

AA19

AA20

AD3

AD6

AD9

AD12

AD15

AD18

AD21

AE25

AE26

AF24

AF25

AF26

T6

V_SS

B3

B5

B7

B9

B11

B13

B15

B17

B19

B21

B23

B25

C2

H6

J3

J6

D25

D4

K6

L6

E2

M3

E6

M6

E8

N6

E10

E12

E14

E16

E18

E20

E22

F5

P6

R3

R6

F24

G21

H21

J21

J24

K21

L21

M24

N21

R21

R24

U21

V21

V24

W21

Y21

F25

G2

G22

H5

U6

H25

J2

V3

V6

J22

K5

W6

Y6

K25

L2

AF5

AE7

A6

L11

L12

Datasheet

January 2005

37

Intel^®80321 I/O Processor

Package Information

Table 10.

544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 5 of 5)

Signal

Ball

Signal

Ball

Signal

Ball

V_SS

L13

L14

L15

L16

L22

M5

V_SS

R11

R12

R13

R14

R15

R16

R22

T5

V_SS

AB15

AB17

AB19

AB21

AB25

AC2

V_SS

M11

M12

M13

M14

M15

M16

M25

N2

V_SS

AC23

AD25

AE2

V_SS

T11

T12

T13

T14

T15

T16

T25

U2

V_SS

AE4

V_SS

AE6

V_SS

AE8

V_SS

AE10

AE12

AE14

AE16

AE18

AE20

AE22

AE24

H4

V_SS

N11

N12

N13

N14

N15

N16

N22

P5

V_SS

U22

V5

V_SS

V25

W2

V_SS

W22

Y5

SWE#

WIDTH00

WIDTH01

W/R#

XINT0#

XINT1#

XINT2#

XINT3#

K22

P11

P12

P13

P14

P15

P16

P25

R2

Y25

AA2

AA22

AB5

AB7

AB9

AB11

AB13

H22

P23

AD26

AC26

AC25

AC24

38

January 2005

Datasheet

Intel^®80321 I/O Processor

Package Information

3.2

Package Thermal Specifications

The device is specified for operation when T (case temperature) is within the range of 0 °C to

C

95 °C, depending on operating conditions. Case temperature can be measured in any environment

to determine whether the processor is within specified operating range. Case temperature is best

measured at the center of the top surface, opposite the ballpad.

3.2.1

Thermal Characteristics

Table 11 summarizes the thermal simulation data for the 80321.

The thermal performance of the 80321 package is represented by the following parameters:

1. Ψ , thermal characterization parameter from junction-to-top center

JT

Ψ

= (T - T ) / P

JT

J T

where

— T = T , the temperature of the top-center of the package

T

C

— Ψ simulations are carried out to show the thermal performance of the 80321.

JT

Table 11.

544-Lead PBGA Package Thermal Characteristics

Thermal Resistance Parameter °C/W

Parameter

Value

Ψ_JT

0.6

Datasheet

January 2005

39

Intel^®80321 I/O Processor

Package Information

3.2.2

Thermal Specifications

This section defines the terms used for thermal analysis.

3.2.2.1

Ambient Temperature

Ambient temperature, T , is the temperature of the ambient air surrounding the package. In a

A

system environment, ambient temperature is the temperature of the air upstream from the package.

3.2.2.2

Case Temperature

When measuring case temperature, attention to detail is required to ensure accuracy. When a

thermocouple is used, calibrate it before taking measurements. Errors may result when the

measured surface temperature is affected by the surrounding ambient air temperature. Such errors

may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by

radiation, or conduction through thermocouple leads.

To minimize measurement errors:

• Use a 35 gauge K-type thermocouple or equivalent.

• Attach the thermocouple bead or junction to the package top surface at a location

corresponding to the center of the die (Figure 6). The center of the die gives a more accurate

measurement and less variation as the boundary condition changes.

• Attach the thermocouple bead at a 0° angle with respect to the package as shown in Figure 6,

when no heatsink is attached.

Figure 6.

Thermocouple Attachment—No Heatsink

Intel^®80321

I/O Processor

Thermocouple

3.2.3

80321 JTAG Emulator Vendor

Table 12.

JTAG Emulator Vendor

Company

Part #

ARM, Ltd.

Multi-ICE Interface Unit

ARM KP1-0019A

www.arm.com

WindRiver HSI

visionPROBE/visionICE for Intel XScale^®microarchitecture

www.windriver.com

40

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

Table 13.

Absolute Maximum Ratings

Parameter

Maximum Rating

–55° C to +125 °C

0° C to +95 °C

NOTICE: The specifications are subject to

change without notice. Contact your local Intel

representative before finalizing a design.

Storage temperature

Case temperature under bias

Supply voltage V_CC33wrt. V_SS

Supply voltage V_CC25wrt. V_SS

Supply voltage V_CC13wrt. V_SS

Voltage on any ball wrt. V_SS

–0.5 V to +4.1 V

–0.5 V to +3.6 V

–0.5 V to +2.1 VV

–0.5 V to V_CCP+ 0.5 V

†WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended

exposure beyond the “Operating Conditions” may affect device reliability.

Table 14.

Operating Conditions

Symbol

V_CC33

Parameter

3.3 V PCI supply voltage

2.5 V DDR supply voltage

1.3 V CORE supply voltage

Min

3.0

Max

3.6

Units

V

Notes

V_CC25

2.3

2.7

V

V_CC13

1.235

V_CC13

1.365

V_CC13

V

V_CCPLL1PLL supply voltage

V_CCPLL2PLL supply voltage

V

V_REF

F_{P_CLK}

T_C

Memory I/O reference voltage

V _CC25/2 - 0.05 V _CC25/2 + 0.05

V

Input clock frequency

16

0

133

95

MHz

°C

Case temperature under bias

4.2

V_CCPLLPin Requirements

To reduce clock skew, the V

, V

and V

balls for the Phase Lock

SSPLL2

CCPLL1

CCPLL2

SSPLL1

Loop (PLL) circuit are isolated on the package. The lowpass filter, as shown in Figure 7, reduces

noise induced clock jitter and its effects on timing relationships in system designs. The 4.7 µF

capacitor must be (low ESR solid tantalum), the 0.01 µF capacitor must be of the type X7R and the

node connecting V

must be as short as possible. The VSSPLL balls should be connected to

CCPLL

the board ground plane.

Figure 7.

V

CCPLL

Lowpass Filter

V_CCPLL

+

V_CC13

(Board Plane)

10Ω, 5%, 1/8W

4.7µF

0.01µF

Datasheet

January 2005

41

Intel^®80321 I/O Processor

Electrical Specifications

4.3

Targeted DC Specifications

Table 15.

DC Characteristics

Symbol

Parameter

Min

Max

Units

Notes

V_IL1

Input Low Voltage (SDRAM)

Input High Voltage (SDRAM)

Input Low Voltage (Misc.)

Input High Voltage (Misc.)

Input Low Voltage (PCI-X)

Input High Voltage (PCI-X/PCI)

Input Low Voltage (PCI)

-0.3

V_REF- 0.15

V

3, 5

4

V_IH1

V_IL2

V_REF+ 0.15 V_CC25+ 0.3

-0.3

2.0

0.8

V

V_IH2

V_IL3

V_CC33+ 0.3

0.35 V_CC33

V_CC33+ 0.5

0.3 V_CC33

0.4

V

4

-0.5

V

1

V_IH3

V_IL4

0.5 V_CC33

-0.5

V

1

V

1

V_OL1

V_OH1

V_OL2

V_OH2

V_OL3

V_OH3

C_IN

Output Low Voltage (Misc.)

Output High Voltage (Misc.)

Output Low Voltage (SDRAM)

Output High Voltage (SDRAM)

Output Low Voltage (PCI-X)

Output HIGH Voltage (PCI-X)

Input pin Capacitance

V

I_OL= 6 mA (4)

I_OH= -2 mA (4)

I_OL= 15.2 mA (3, 5)

I_OH= -15.2 mA (3, 5)

I_OL= 1500 µA (1)

I_OH= -500 µA (1)

1, 2

2.4

1.95

V

0.35

V

0.1 V_CC33

V

0.9 V_CC33

V

8

pF

nH

C_CLK

L_PIN

Clock pin Capacitance

5

1, 2

Ball Inductance

15

1, 2

NOTES:

1. As required by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.

2. Not tested.

3. SDRAM signals include MA[12:0], BA[1:0], CAS#, CS[1:0]#, CKE[1:0], DM[8:0], RAS#, WE#, RCVENI#,

RCVENO#, M_CK[2:0], M_CK[2:0]#, DQ[63:0], DQS[8:0] and CB[7:0].

4. Miscellaneous signals include all signals that are not PCI or SDRAM signals.

5. Only 2.5 V DDR SDRAM is supported.

42

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

Table 16.

I

Characteristics

CC

Symbol

I_LI1

Parameter

Typ

Max

Units

Notes

Input Leakage Current for each signal except TCK,

TMS, TRST#, TDI.

±2

µA

0<V_IN<V_CC(1)

I_LI2

Input Leakage Current for TCK, TMS, TRST#, TDI. -140

-250

µA

V_IN=0.45 V (1)

(2)

I_cc13Active Core and Analog Current – 600 MHz.

(Thermal)

1.2

A

I_cc13Active Core and Analog Current – 400 MHz.

(Thermal)

1.08

0.38

0.34

A

(2)

(3)

I_cc25Active DDR Current – 200 MHz at 2.5 V.

(Thermal)

I_cc33Active PCI/PBI Current – 100 MHz/133 MHz at 3.3 V.

(Thermal)

I_cc13Active Core and Analog Current – 600 MHz

(Power

Supply)

1.72

1.55

0.42

0.36

I_cc13Active Core and Analog Current – 400 MHz

(Power

Supply)

A

(3)

I_cc25Active DDR Current – 200 MHz at 2.5 V

(Power

Supply)

I_cc33Active PCI/PBI Current – 10 0MHz/133 MHz at 3.3 V

(Power

Supply)

NOTES:

1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs with

tri-state outputs..

2. I_CCActive (Thermal) value is provided for system thermal management. Typical I_CCis measured with

V_CC13= 1.3 V, V_CC25= 2.5 V, V_CC33= 3.3 V and ambient temperature = 55°C.

3. I_CCActive (Power Supply) value is provided for selecting system power supply. It is measured using one of

the worst case instruction mixes with V_CC13= 1.365 V, V_CC25= 2.75 V, V_CC33= 3.63 V and ambient

temperature = 55°C.

Datasheet

January 2005

43

Intel^®80321 I/O Processor

Electrical Specifications

4.4

Targeted AC Specifications

4.4.1

Clock Signal Timings

Table 17.

Clock Timings

PCI-X 133 PCI-X 100 PCI-X 66

PCI 66

PCI 33

Symbol

Parameter

Units Notes

Min Max Min Max Min Max Min Max Min Max

T_F1

PCI clock Frequency

PCI clock Cycle Time

PCI clock High Time

PCI clock Low Time

PCI clock Slew Rate

100 133 66 100 50

66

20

33

15

6

66

30

16

30

11

1

33 MHz

1

T_C1

7.5

3

10

3

15

6

60

ns

1, 3

T_CH1

T_CL1

T_SR1

3

6

ns

1.5

4

1.5

4

1.5

4

1.5

4

V/ns

2

Spread Spectrum Requirements

f_mod

PCI clock modulation

frequency

30

-1

33

30

33

30

33

30

-1

33

0

KHz

%

f_spread

PCI clock frequency

spread

0

-1

0

-1

0

PC200

Symbol

Parameter

Units Notes

Min

Max

T_F2

DDR SDRAM clock Frequency

DDR SDRAM clock Cycle Time

DDR SDRAM clock High Time

DDR SDRAM clock Low Time

DDR SDRAM clock Period Stability

100

MHz

ns

T_C2

10

4.5

T_CH2

T_CL2

T_CS2

T_skew2

5.5

ns

± ±90

200

ps

DDR SDRAM clock skew for M_CK[2:0] and M_CK[2:0]#

ps

PBI 100

PBI 66

PBI 33

Symbol

Parameter

Units Notes

Min Max Min Max Min Max

T_F3

PBI clock Frequency

PBI clock Cycle Time

PBI clock High Time

PBI clock Low Time

PBI clock Period Stability

100

66

33 MHz

T_C3

10

3

15

6

30

11

ns

ps

T_CH3

T_CL3

T_CS3

NOTES:

3

6

± ±90

1. The clock frequency may not change beyond the spread-spectrum limits except while P_RST# is asserted.

2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.

3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system

jitter.

44

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

4.4.2

PCI Interface Signal Timings

Table 18.

PCI Signal Timings

PCI-X 133

PCI-X 100

PCI-X 66

PCI 66

PCI 33

Symbol

Parameter

Units Notes

Min Max Min Max Min Max Min Max

T_OV1

T_OV2

Clock to Output Valid Delay for

bused signals

0.7 3.8 0.7 3.8

1

6

2

11

12

28

ns

1, 2, 3

Clock to Output Valid Delay for

point to point signals

0.7 3.8 0.7 3.8

2

6

2

T_OF

T_IS1

Clock to Output Float Delay

7

14

ns

1, 7

Input Setup to clock for bused

signals

1.2

1.7

3

5

7

3, 4, 8

T_IS2

Input Setup to clock for point to 1.2

point signals

10,

12

ns

3, 4

4

T_IH1

T_RST

T_RF

Input Hold time from clock

Reset Active Time

0.5

1

0.5

1

0

1

0

1

ns

ms

ns

Reset Active to output float

delay

40

50

40

50

40

50

40

50

5, 6

T_IS3

T_IH2

T_IS4

REQ64# to Reset setup time

Reset to REQ64# hold time

10

0

10

0

10

0

10

0

clocks

ns

PCI-X initialization pattern to

Reset setup time

10

clocks

T_IH3

Reset to PCI-X initialization

pattern hold time

0

ns

NOTES:

1. See the timing measurement conditions in Figure 9 “Output Timing Measurement Waveforms” on page 49.

2. See Figure 15 “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 53, Figure 16 “PCI/PCI-X

TOV(max) Falling Edge AC Test Load” on page 53 and Figure 17 “PCI/PCI-X TOV(min) AC Test Load” on

page 54.

3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused.

4. See the timing measurement conditions in Figure 10 “Input Timing Measurement Waveforms” on page 50.

5. RST# is asserted and deasserted asynchronously with respect to CLK.

6. All output drivers must be floated when RST# is active.

7. For purposes of Active/Float timing measurements, the HI-Z or “off” state is defined to be when the total

current delivered through the component pin is less than or equal to the leakage current specification.

8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at

the same time.

Datasheet

January 2005

45

Intel^®80321 I/O Processor

Electrical Specifications

4.4.3

DDR SDRAM Interface Signal Timings

Table 19.

DDR SDRAM Signal Timings

Symbol

Parameter

Min

1.3

Max

Units Notes

T_VB1

T_VA1

T_VB2

T_VA2

T_VB3

T_VA3

T_VB4

T_VA4

T_VB5

T_VA5

T_VB6

T_VA6

NOTES:

DQ, CB and DM output valid time before associated DQS

DQ, CB and DM output valid time after associated DQS

DQS output valid time before M_CK

ns

4

5

1.4

1.0

DQS output valid time after M_CK

Address and Control write output valid before M_CK

Address and Control write output valid after M_CK

DQS read input valid time before DQ

4.2

3.3

1.6

1.4

1.0

DQS read input valid time after DQ

RCVENO# output valid time before M_CK

RCVENO# output valid time after M_CK

RCVENI# input valid time before DQS

3.0

0.8

RCVENI# hold from DQS valid

1. See Figure 9 “Output Timing Measurement Waveforms” on page 49.

2. See Figure 10 “Input Timing Measurement Waveforms” on page 50.

3. These output valid times are specified with a 0 pF loading.

4. See Figure 12 “DDR SDRAM Write Timings” on page 51.

5. See Figure 13 “DDR SDRAM Read Timings” on page 52.

4.4.4

Peripheral Bus Interface Signal Timings

Table 20.

Peripheral Bus Signal Timings

Sym

T_OV1

Parameter

Output Valid Delay from PB_CLK

Min

Max

Units Notes

1

5.5

ns

1, 3

2

T_OF

Output Float Delay from PB_CLK

Input Setup to PB_CLK

T_IS1

4.9

2

T_IH1

Input Hold from PB_CLK

2

NOTES:

1. See Figure 9 “Output Timing Measurement Waveforms” on page 49.

2. See Figure 10 “Input Timing Measurement Waveforms” on page 50.

3. See Figure 14 “AC Test Load for all Signals Except PCI and DDR SDRAM” on page 53.

46

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

4.4.5

I²C Interface Signal Timings

Table 21.

I²C Signal Timings

Std. Mode

Fast Mode

Symbol

Parameter

Units Notes

Min

Max

Min

Max

F_SCL

T_BUF

SCL Clock Frequency

0

100

0

400

KHz

Bus Free Time Between STOP and START

Condition

4.7

1.3

µs

1

T_HDSTA

T_LOW

Hold Time (repeated) START Condition

SCL Clock Low Time

4

0.6

1.3

0.6

µs

1, 3

1, 2

1

4.7

4

T_HIGH

SCL Clock High Time

T_SUSTA

Setup Time for a Repeated START

Condition

4.7

T_HDDAT

T_SUDAT

T_SR

Data Hold Time

0

3.45

0

0.9

µs

ns

µs

1

Data Setup Time

250

100

SCL and SDA Rise Time

SCL and SDA Fall Time

Setup Time for STOP Condition

1000 20+0.1C_b

300

1, 4

1

T_SF

300

20+0.1C_b

0.6

T_SUSTO

NOTES:

4

1. See Figure 11 “I²C Interface Signal Timings” on page 50.

2. Not tested.

3. After this period, the first clock pulse is generated.

4. C_b= the total capacitance of one bus line, in pF.

4.4.6

SSP Interface Signal Timings

Table 22.

SSP Signal Timings

Symbol

Parameter

Min

Max

Units Notes

T_IS

Input Setup to SSCKO

Input Hold from SSCKO

9

0

ns

T_IH

T_OV

Output Valid Delay from SSCKO

-1

3

2

Output Valid Delay from SSCKI to SSCKO in external clock

10

mode.

Datasheet

January 2005

47

Intel^®80321 I/O Processor

Electrical Specifications

4.4.7

Boundary Scan Test Signal Timings

Table 23.

Boundary Scan Test Signal Timings

Symbol

Parameter

TCK Frequency

Min

Max

Units

Notes

T_BSF

0

66

MHz

ns

T_BSCH

T_BSCL

T_BSCR

T_BSCF

T_BSIS1

T_BSIH1

T_BSOV1

TCK High Time

TCK Low Time

7.5

Measured at 1.5 V (1)

ns

Measured at 1.5 V (1)

TCK Rise Time

TCK Fall Time

5

ns

0.8 V to 2.0 V (1)

ns

2.0 V to 0.8 V (1)

Input Setup to TCK

Input Hold from TCK

3

1

ns

4

ns

4

TDO Output Valid Delay from

falling edge of TCK.

11

ns

2, 3

T_OF1

TDO Output Float Delay from

1

ns

2, 5

falling edge of TCK.

NOTES:

1. Not tested.

2. Outputs precharged to V_CC5

.

3. See Figure 9 “Output Timing Measurement Waveforms” on page 49.

4. See Figure 10 “Input Timing Measurement Waveforms” on page 50.

5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See

Figure 9 “Output Timing Measurement Waveforms” on page 49.

48

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

4.5

AC Timing Waveforms

Figure 8.

Clock Timing Measurement Waveforms

T_CR

T_CF

V_tch

V_ih(min)

V_test

Vil(max)

V_tcl

T_CH

T_CL

T_C

Figure 9.

Output Timing Measurement Waveforms

V_th

CLK

V_test

V_tl

T_OV

V_tfall

OUTPUT

DELAY FALL

T_OV

OUTPUT

DELAY RISE

Vtrise

T_OF

OUTPUT

FLOAT

Datasheet

January 2005

49

Intel^®80321 I/O Processor

Electrical Specifications

Figure 10.

Input Timing Measurement Waveforms

V_th

CLK

V_test

V_tl

T_IH

T_IS

V_th

INPUT

V_test

Valid

V_test

V_max

V_tl

Figure 11.

I²C Interface Signal Timings

SDA

T_SF

T_HDSTA

T_LOW

T_BUF

T_SR

T_SP

SCL

T_HDSTA

T_SUSTO

T_HDDAT

T_HIGH

T_SUDAT

T_SUSTA

Stop

Start

Stop

Repeated

Start

50

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

Figure 12.

DDR SDRAM Write Timings

T_VA3

ADDR/CTRL

T_VB3

M_CK

DQS

T_VB2

T_VA2

T_VA1

T_VB1

DQ

Datasheet

January 2005

51

Intel^®80321 I/O Processor

Electrical Specifications

Figure 13.

DDR SDRAM Read Timings

M_CK

T_VA5

T_VB5

rcveno#

T_VA6

rcveni#

DQS

T_VB6

T_VB4

T_VA4

DQ

52

January 2005

Datasheet

Intel^®80321 I/O Processor

Electrical Specifications

4.6

AC Test Conditions

Table 26.

AC Measurement Conditions

Symbol

PCI-X

PCI

DDR

PBI

Units

Notes

V_tch

V_tcl

0.6 V_CC33

0.2 V_CC33

0.6 V_CC33

0.25 V_CC33

0.4 V_CC33

0.285 V_CC33

0.615 V_CC33

0.4 V_CC33

1.5

0.6 V_CC33

0.2 V_CC33

0.6 V_CC33

0.2 V_CC33

0.4 V_CC33

0.285 V_CC33

0.615 V_CC33

0.4 V_CC33

1.5

-

V

-

V_th

2.0

0.5

1.25

1.5

2.0

0.8

1.5

1.2

1.5

V

V_tl

V

V_test

V

V_trise

V_tfall

V

V_max

Slew Rate

V

V/nS

1

1. Input signal slew rate is measured between V_iland V_ih.

Figure 14.

AC Test Load for all Signals Except PCI and DDR SDRAM

Test

Point

Output

50pF

Figure 15.

PCI/PCI-X T

Rising Edge AC Test Load

OV(max)

Test

Point

Output

25Ω

10pF

Figure 16.

PCI/PCI-X T

Falling Edge AC Test Load

OV(max)

V_CC33

Test

Point

25Ω

Output

10pF

Datasheet

January 2005

53

Intel^®80321 I/O Processor

Electrical Specifications

Figure 17.

PCI/PCI-X T

AC Test Load

OV(min)

V_CC33

1KΩ

Test

Point

Output

1KΩ

10pF

Figure 18.

PCI_RST# vs. PWRDELAY Timings During Power-Up

Few m illiseconds

PCI_RST#

PWRDELAY

BRD_PWRDELAY

Note:

The delay depends on the size of the capacitor.

A delay of about 1 m s is adequate.

Figure 19.

PCI_RST# vs. PWRDELAY Timings During Power-Down

Few milliseconds

PCI_RST#

PWRDELAY

BRD_PWRDELAY

Note:

The delay depends on the size of the capacitor.

A delay of about 1 ms is adequate.

54

January 2005

Datasheet


型号：	FW80321M600Q467B-1
厂家：	INTEL
描述：	Micro Peripheral IC, PBGA544
文件：	总54页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FW80321M600Q467B-1 [INTEL]

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