GD80960JS-33 [INTEL]
RISC Microprocessor, 32-Bit, 33MHz, CMOS, PBGA196, PLASTIC, BGA-196;型号: | GD80960JS-33 |
厂家: | INTEL |
描述: | RISC Microprocessor, 32-Bit, 33MHz, CMOS, PBGA196, PLASTIC, BGA-196 时钟 外围集成电路 |
文件: | 总86页 (文件大小:4360K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
80960JA/JF/JD/JS/JC/JT 3.3 V
Embedded 32-Bit Microprocessor
Datasheet
Product Features
■ Code Compatible with all 80960Jx
■ On-Chip Data RAM
Processors
—1 Kbyte Critical Variable Storage
—Single-Cycle Access
■ High-Performance Embedded Architecture
—One Instruction/Clock Execution
■ 3.3 V Supply Voltage
—Core Clock Rate is:
—5 V Tolerant Inputs
1x the Bus Clock for 80960JA/JF/JS
2x the Bus Clock for 80960JD/JC
3x the Bus Clock for 80960JT
—TTL Compatible Outputs
■ High Bandwidth Burst Bus
—32-Bit Multiplexed Address/Data
—Programmable Memory Configuration
—Selectable 8-, 16-, 32-Bit Bus Widths
—Supports Unaligned Accesses
—Big or Little Endian Byte Ordering
■ High-Speed Interrupt Controller
—31 Programmable Priorities
—Eight Maskable Pins plus NMI#
—Up to 240 Vectors in Expanded Mode
■ Two On-Chip Timers
—Load/Store Programming Model
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers (8 sets)
—Nine Addressing Modes
—User/Supervisor Protection Model
■ Two-Way Set Associative Instruction
Cache
—80960JA - 2 Kbyte
—80960JF/JD - 4 Kbyte
—80960JS/JC/JT - 16 Kbyte
—Programmable Cache-Locking
Mechanism
—Independent 32-Bit Counting
—Clock Prescaling by 1, 2, 4 or 8
—Internal Interrupt Sources
■ Direct Mapped Data Cache
—80960JA - 1 Kbyte
■ Halt Mode for Low Power
■ IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
■ Packages
—80960JF/JD - 2 Kbyte
—80960JS/JC/JT - 4 Kbyte
—Write Through Operation
■ On-Chip Stack Frame Cache
—Seven Register Sets May Be Saved
—Automatic Allocation on Call/Return
—132-Lead Pin Grid Array (PGA)
—132-Lead Plastic Quad Flat Pack
(PQFP)
—196-Ball Mini Plastic Ball Grid Array
(MPBGA)
—0-7 Frames Reserved for High-Priority
Interrupts
Order Number: 273159-006
August 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
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*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2002, 2004
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................7
2.0 80960Jx Overview..........................................................................................................................9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
80960 Processor Core........................................................................................................10
Burst Bus ............................................................................................................................11
Timer Unit ...........................................................................................................................11
Priority Interrupt Controller..................................................................................................11
Instruction Set Summary ....................................................................................................12
Faults and Debugging.........................................................................................................12
Low Power Operation .........................................................................................................12
Test Features......................................................................................................................12
Memory-Mapped Control Registers....................................................................................13
2.10 Data Types and Memory Addressing Modes......................................................................13
3.0 Packaging Information................................................................................................................15
3.1
3.2
Available Processors and Packages ..................................................................................15
Pin Descriptions..................................................................................................................16
3.2.1 Functional Pin Definitions ......................................................................................16
3.2.2 80960Jx 132-Lead PGA Pinout .............................................................................23
3.2.3 80960Jx 132-Lead PQFP Pinout ...........................................................................27
3.2.4 80960Jx 196-Ball MPBGA Pinout..........................................................................30
4.0 Electrical Specifications .............................................................................................................35
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute Maximum Ratings................................................................................................35
Operating Conditions..........................................................................................................35
Connection Recommendations...........................................................................................36
VCC5 Pin Requirements (VDIFF).......................................................................................36
VCCPLL Pin Requirements ................................................................................................37
D.C. Specifications .............................................................................................................38
A.C. Specifications..............................................................................................................42
4.7.1 A.C. Test Conditions and Derating Curves............................................................45
4.7.1.1 Output Delay or Hold vs. Load Capacitance..........................................46
4.7.1.2
TLX vs. AD Bus Load Capacitance.........................................................47
4.7.1.3 ICC Active vs. Frequency ......................................................................49
4.7.2 A.C. Timing Waveforms.........................................................................................53
5.0 Device Identification....................................................................................................................59
5.1
5.2
5.3
80960JS/JC/JT Device Identification Register....................................................................60
80960JD Device Identification Register..............................................................................61
80960JA/JF Device Identification Register.........................................................................62
6.0 Thermal Specifications ...............................................................................................................63
6.1
Thermal Management Accessories ....................................................................................68
6.1.1 Heatsinks...............................................................................................................68
7.0 Bus Functional Waveforms ........................................................................................................69
7.1
7.2
Basic Bus States.................................................................................................................79
Boundary-Scan Register.....................................................................................................80
Datasheet
3
Contents
Figures
1
2
3
4
5
6
7
8
9
80960Jx Microprocessor Package Options..................................................................................7
80960Jx Block Diagram..............................................................................................................10
132-Lead Pin Grid Array Top View-Pins Facing Down...............................................................23
132-Lead Pin Grid Array Bottom View-Pins Facing Up..............................................................24
132-Lead PQFP - Top View .......................................................................................................27
196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down............................................30
196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up ...........................................31
VCC5 Current-Limiting Resistor .................................................................................................36
VCCPLL Lowpass Filter .............................................................................................................37
10 A.C. Test Load............................................................................................................................45
11 Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) ..........................46
12 Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5 V Signals) .............................46
13 Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD....................................................47
14
15
16
17
T
T
T
LX vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3 V Signals) .........................................47
LX vs. AD Bus Load Capacitance–80960JS/JC/JT (5 V Signals) ............................................48
LX vs. AD Bus Load Capacitance–80960JA/JF/JD...................................................................48
ICC Active (Power Supply) vs. Frequency–80960JA/JF .............................................................49
18 80960JA/JF ICC Active (Thermal) vs. Frequency .......................................................................49
19 80960JD ICC Active (Power Supply) vs. Frequency...................................................................50
20 80960JD ICC Active (Thermal) vs. Frequency ............................................................................50
21 80960JC ICC Active (Power Supply) vs. Frequency...................................................................51
22 80960JC ICC Active (Thermal) vs. Frequency ............................................................................51
23 80960JS ICC Active (Power Supply) vs. Frequency ...................................................................52
24 80960JS ICC Active (Thermal) vs. Frequency ............................................................................52
25 CLKIN Waveform........................................................................................................................53
26
27
28
29
30
31
32
T
T
T
T
T
T
T
OV1 Output Delay Waveform ....................................................................................................53
OF Output Float Waveform .......................................................................................................54
IS1 and TIH1 Input Setup and Hold Waveform ..........................................................................54
IS2 and TIH2 Input Setup and Hold Waveform ..........................................................................54
IS3 and TIH3 Input Setup and Hold Waveform ..........................................................................55
IS4 and TIH4 Input Setup and Hold Waveform ..........................................................................55
LX, TLXL and TLXA Relative Timings Waveform........................................................................56
33 DT/R# and DEN# Timings Waveform.........................................................................................56
34 TCK Waveform...........................................................................................................................57
35
36
37
38
T
T
T
T
BSIS1 and TBSIH1 Input Setup and Hold Waveforms.................................................................57
BSOV1 and TBSOF1 Output Delay and Output Float Waveform.................................................57
BSOV2 and TBSOF2 Output Delay and Output Float Waveform.................................................58
BSIS2 and TBSIH2 Input Setup and Hold Waveform...................................................................58
39 80960JS/JC/JT Device Identification Register Fields.................................................................60
40 80960JD Device Identification Register Fields...........................................................................61
41 80960JA/JF Device Identification Register Fields ......................................................................62
42 Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus.................................69
43 Burst Read and Write Transactions Without Wait States, 32-Bit Bus ........................................70
44 Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus..................................................71
45 Burst Read and Write Transactions Without Wait States, 8-Bit Bus ..........................................72
46 Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus .....................................................................................73
47 Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian ........................................................................74
4
Datasheet
Contents
48 HOLD/HOLDA Waveform For Bus Arbitration............................................................................75
49 Cold Reset Waveform.................................................................................................................76
50 Warm Reset Waveform ..............................................................................................................77
51 Entering the ONCE State............................................................................................................78
52 Bus States with Arbitration..........................................................................................................80
53 Summary of Aligned and Unaligned Accesses (32-Bit Bus).......................................................84
54 Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)...................................85
Tables
1
80960Jx 3.3-V Microprocessor Family .........................................................................................7
2
3
4
5
6
7
8
9
80960Jx Instruction Set ..............................................................................................................14
80960Jx Processors Available in 132-Pin PGA Package...........................................................15
80960Jx Processors Available in 132-Pin PQFP Package.........................................................15
80960Jx Processors Available in Extended Temperature .........................................................16
80960Jx Processors Available in 196-Ball MPBGA Package.....................................................16
Pin Description Nomenclature ....................................................................................................17
Pin Description—External Bus Signals.......................................................................................18
Pin Description—Processor Control Signals, Test Signals, and Power .....................................21
10 Pin Description—Interrupt Unit Signals ......................................................................................22
11 132-Lead PGA Pinout—In Signal Order.....................................................................................25
12 132-Lead PGA Pinout—In Pin Order..........................................................................................26
13 132-Lead PQFP Pinout—In Signal Order...................................................................................28
14 132-Lead PQFP Pinout—In Pin Order........................................................................................29
15 196-Ball MPBGA Pinout—In Signal Order..................................................................................32
16 196-Ball MPBGA Pinout—In Pin Order ......................................................................................33
17 Absolute Maximum Ratings........................................................................................................35
18 80960Jx Operating Conditions ...................................................................................................35
19 VDIFF Parameters......................................................................................................................37
20 80960Jx D.C. Characteristics .....................................................................................................38
21 80960Jx ICC Characteristics .......................................................................................................39
22 80960Jx A.C. Characteristics .....................................................................................................42
23 Note Definitions for Table 22, 80960Jx AC Characteristics........................................................45
24 80960Jx Device Type and Stepping Reference .........................................................................59
25 80960JS/JC/JT Device ID Register Field Definitions..................................................................60
26 80960JS/JC/JT Device ID Model Types.....................................................................................60
27 80960JD Device ID Field Definitions ..........................................................................................61
28 80960JD Device ID Model Types ...............................................................................................61
29 80960JA/JF Device ID Field Definitions .....................................................................................62
30 80960JA/JF Device ID Model Types ..........................................................................................62
31 Thermal Resistance for qCA and qJC Reference Table ..............................................................63
32 Maximum Ambient Temperature Reference Table.....................................................................63
33 132-Lead PGA Package Thermal Characteristics......................................................................64
34 80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics.........................................64
35 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics.........................................65
36 132-Lead PQFP Package Thermal Characteristics....................................................................65
37 Maximum TA at Various Airflows in °C (80960JT) ......................................................................66
38 Maximum TA at Various Airflows in °C (80960JC)......................................................................66
39 Maximum TA at Various Airflows in °C (80960JD)......................................................................67
40 Maximum TA at Various Airflows in °C (80960JS)......................................................................67
41 Maximum TA at Various Airflows in °C (80960JA/JF).................................................................68
Datasheet
5
Contents
42 Boundary-Scan Register—Bit Order ..........................................................................................81
43 Natural Boundaries for Load and Store Accesses......................................................................81
44 Summary of Byte Load and Store Accesses..............................................................................82
45 Summary of Short Word Load and Store Accesses...................................................................82
46 Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)..................................................83
Revision History
Date
Revision
Description
To address the fact that many of the package prefix variables have
changed, all package prefix variables in this document are now
indicated with an "x".
August 2004
006
Removed reference to A80960JF-16 from Table 3 on page 15.
Removed reference to NG80960JC-40, NG80960JC-33, NG80960JS-16,
and NG80960JF-16 from Table 4 on page 15.
Removed reference to GD80960JC-40, GD80960JC-33, and 80960JS-16
in Table 6 on page 16.
September 2002
005
Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and
80960JF-16 in Table 18 on page 35.
Removed reference to 80960JC-40, 80960JC-33, 80960JS-16, and
80960JF-16 from Table 21 on page 39.
Removed reference to 80960JC-40, 80960JC-33, 80960JS-16 and
80960JF-16 from Table 22 on page 42.
Added new extended temp device offerings. See Table 5 on page 16.
Removed PGA package availability from JS/JC/JT processors.
September 1999
June 1999
004
003
Changed AC timing parameter T
See Table 22 on page 42.
(min) for extended temp devices only.
OV1
Merged the 80960JS/JC datasheet information into this datasheet
(previously named 80960JA/JF/JD/JT 3.3 V Embedded 32-Bit
Microprocessor datasheet).
Updated I values for the 80960JS/JC/JT processors.
CC
Increased TIH1 specification for the 80960JS/JC/JT processors.
Updated MPBGA thermal specifications.
Corrected orientation of MPBGA package diagrams (Figure 6 on page 30
and Figure 7 on page 31).
December 1998
002
001
Added Figure 11 on page 46, Figure 12 on page 46, Figure 14 on page 47,
and Figure 15 on page 48 to distinguish 80960JT 3.3-V and 5-V signal
derating curves from the 80960JA/JF/JD derating curves.
This datasheet supersedes revisions to the following 80960Jx datasheets:
#273109 (JT), #272971-002 (JD), and #276146-001 (JA/JF). In addition to
combining the documents into one, the following content was changed:
Figure 1 on page 7: Added MPBGA package to diagram.
March 1998
Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page 30: Added new
Figures 6 and 7, Tables 10, 11 and 13.
Figure 16 on page 48: Added with the note that follows the figure.
6
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
1.0
Introduction
This document contains information for the 80960Jx microprocessors, including electrical
characteristics and package pinout information. Detailed functional descriptions, other than
parametric performance, are published in the i960® Jx Microprocessor Developer’s Manual
(272483) and may be viewed online at http://developer.intel.com/design/i960/Techinfo/80960JX/.
Figure 1. 80960Jx Microprocessor Package Options
x80960JX
XXXXXXXXSS
M
i
®
x80960JX
XXXXXXXSS
M
i960
i
© 19xx
©
19xx
x80960JX
XXXXXXXX SS
M
©
19xx
i
196-Ball MPBGA
132-Pin PQFP
132-Pin PGA
Throughout this datasheet, references to ‘80960Jx’ indicate features that apply to the 3.3-V Jx
processors only:
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix
variables in this document are now indicated with an "x".
Table 1. 80960Jx 3.3-V Microprocessor Family
Instruction
Cache
Data
Cache
Processor
Voltage
Core Clock
80960JA
80960JF
80960JD
80960JS
80960JC
80960JT
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
2 Kbyte
4 Kbyte
4 Kbyte
16 Kbyte
16 Kbyte
16 Kbyte
1 Kbyte
2 Kbyte
2 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
1x
1x
2x
1x
2x
3x
Datasheet
7
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
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8
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
2.0
80960Jx Overview
The 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications.
The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustained
execution at the rate of one instruction per clock. This processor’s features include generous
instruction cache, data cache, and data RAM. It also boasts a fast interrupt mechanism and
dual-programmable timer units.
The 80960Jx processor’s clock multiplication operates the processor core at two or three times the
bus clock rate to improve execution performance without increasing the complexity of board
designs.
Memory subsystems for cost-sensitive embedded applications often impose substantial wait state
penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus.
The 80960Jx rapidly allocates and de-allocates local register sets during context switches. The
processor must flush a register set to the stack only when it saves more than seven sets to its local
register cache.
A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full
complement of control signals simplifies the connection of the 80960Jx to external components.
The user programs physical and logical memory attributes through memory-mapped control
registers (MMRs), an extension not found on the i960® Kx, Sx or Cx processors. Physical and
logical configuration registers enable the processor to operate with all combinations of bus width
and data object alignment. The processor supports a homogeneous byte ordering model.
This processor integrates two important peripherals: a timer unit and an interrupt controller. These
and other hardware resources are programmed through memory-mapped control registers, an
extension to the familiar i960 processor architecture.
The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and
general-purpose system timing. These operate in either single-shot or auto-reload mode and may
generate interrupts.
The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.
The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The
ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt
latency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% compared
to the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% compared
to the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reduce
latency. Acting independently from the core, the ICU compares the priorities of posted interrupts
with the current process priority, off-loading this task from the core. The ICU also supports the
integrated timer interrupts.
The 80960Jx features a Halt mode designed to support applications where low power consumption
is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up
to 90 percent.
The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.
Datasheet
9
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
The Solutions960® program features a wide variety of development tools which support the i960
processor family. Many of these tools are developed by partner companies; some are developed by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.
Figure 2. 80960Jx Block Diagram
Control
Physical Region
32-bit buses
address / data
CLKIN
Configuration
PLL, Clocks,
Power Mgmt
21
Instruction Cache
80960JA - 2K
Bus
Control Unit
Address/
Data Bus
80960JF/JD - 4K
80960JS/JC/JT - 16K
Bus Request
Queues
TAP
5
Boundary Scan
Controller
32
Two 32-Bit
Timers
Instruction Sequencer
Interrupt
Port
Constants
Control
Programmable
Interrupt Controller
9
8-Set
Local Register Cache
Execution
and
Memory
Interface
Unit
Memory-Mapped
Register Interface
Multiply
Divide
Unit
Address
Generation
128
Unit
32-bit Address
32-bit Data
1K Data RAM
Global / Local
Register File
effective
address
SRC1 SRC2 DEST
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JS/JC/JT -
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
• Core operates at the bus speed with the 80960JA/JF/JS
• Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,
respectively
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline break latency
• Register and resource scoreboarding allow overlapped instruction execution
• 128-bit register bus speeds local register caching
• Two-way set associative, integrated instruction cache
• Direct-mapped, integrated data cache
• 1-Kbyte integrated data RAM delivers zero wait state program data
10
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
2.2
Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory
organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and
data caching are programmed through a group of logical memory templates and a defaults register.
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16-, and 8-bit bus widths to simplify I/O interfaces
• External ready control for address-to-data, data-to-data and data-to-next-address wait state
types
• Support for big or little endian byte ordering to facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).
2.3
2.4
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the TU registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault when
unauthorized writes from user mode are detected. Clock prescaling is supported.
Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-
triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channels
and a single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their priority
levels relative to the current process priority.
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
• Interrupt vectors and interrupt handler routines may be reserved on-chip.
• Register frames for high-priority interrupt handlers may be cached on-chip.
• The interrupt stack may be placed in cacheable memory space.
• Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and
80960JT, respectively.
Datasheet
11
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
2.5
Instruction Set Summary
The 80960Jx adds several new instructions to the i960 processor core architecture. The new
instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control
Table 2 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx Microprocessor
Developer’s Manual (272483) for a detailed description of each instruction.
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to
detect as many as seven different trace event types. Alternatively, mark and fmark instructions
may generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s
sub-micron topology provides the circuit density for optimal cache size and high operating speeds
while dissipating modest power. The processor also uses dynamic power management to turn off
clocks to unused circuits.
Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,
the processor core stops completely while the integrated peripherals continue to function, reducing
overall power requirements up to 90 percent. Processor execution resumes from internally or
externally generated interrupts.
2.8
Test Features
The 80960Jx incorporates numerous features that enhance the user’s ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
12
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins
(ONCE mode). ONCE mode may also be initiated at reset without using the boundary scan
mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to
electrically “remove” itself from a circuit board. This allows for system-level testing in which a
remote tester, such as an in-circuit emulator, may exercise the processor system.
The provided test logic does not interfere with component or circuit board behavior and ensures
that components function correctly, connections between various components are correct, and
various components interact correctly on the printed circuit board.
The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.
It may examine connections that might otherwise be inaccessible to a test system.
2.9
Memory-Mapped Control Registers
The 80960Jx, although compliant with the i960 processor core, has the added advantage of
memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These
registers give software the interface to easily read and modify internal control registers.
Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The processor ensures that these accesses do not
generate external bus cycles.
2.10
Data Types and Memory Addressing Modes
As with all i960 processors, the 80960Jx instruction set supports several data types and formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960Jx provides a full set of addressing modes for C and assembly programming:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement
• IP with displacement
Datasheet
13
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 2. 80960Jx Instruction Set
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Add
Subtract
Multiply
And
Set Bit
Divide
Not And
And Not
Or
Clear Bit
Remainder
Not Bit
Load
Modulo
Alter Bit
Store
Shift
Exclusive Or
Not Or
Scan For Bit
Span Over Bit
Extract
Move
Conditional Select†
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Conditional Add†
Conditional Subtract†
Rotate
Or Not
Load Address
Nor
Modify
Exclusive Nor
Not
Scan Byte for Equal
Byte Swap†
Nand
Comparison
Branch
Call/Return
Fault
Compare
Call
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Check Bit
Unconditional Branch
Conditional Branch
Compare and Branch
Call Extended
Call System
Return
Conditional Fault
Synchronize Faults
Branch and Link
Debug
Processor Management
Atomic
Flush Local Registers
Modify Arithmetic
Controls
Modify Trace Controls
Mark
Modify Process Controls
Halt†
Atomic Add
Atomic Modify
Force Mark
System Control
Cache Control†
Interrupt Control†
†
Denotes new 80960 instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB processors.
14
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
3.0
Packaging Information
3.1
Available Processors and Packages
The 80960Jx is offered in various speed grades and three package types.
The 132-pin Pin Grid Array (PGA) device is specified for operation at VCC = 3.3 V ± 0.15 V over
a case temperature range of 0° C to 100° C. The following processor versions are available in the
PGA package:
Table 3. 80960Jx Processors Available in 132-Pin PGA Package
Processor
x80960JD-66
Core Speed
Bus Speed
66 MHz
33 MHz
33 MHz
25 MHz
33 MHz
16 MHz
33 MHz
25 MHz
x80960JD-33
x80960JA/JF-33
x80960JF-25
For pinout diagrams for the PGA package, see Section 3.2.2, “80960Jx 132-Lead PGA Pinout” on
page 23.
The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at
V
CC = 3.3 V ± 0.15 V over a case temperature range of 0° C to 100° C. Table 4 presents 80960Jx
processor versions that are available in the 132-pin PQFP package:
Table 4. 80960Jx Processors Available in 132-Pin PQFP Package
Processor
Core Speed
Bus Speed
x80960JT-100
x80960JC-66
x80960JC-50
x80960JS-33
x80960JS-25
x80960JD-66
x80960JD-40
x80960JA/JF-33
x80960JA/JF-25
x80960JA-16
100 MHz
66 MHz
50 MHz
33 MHz
25 MHz
66 MHz
40 MHz
33 MHz
25 MHz
16 MHz
33 MHz
33 MHz
25 MHz
33 MHz
25 MHz
33 MHz
20 MHz
33 MHz
25 MHz
16 MHz
For pinout diagrams of the PQFP package, see Section 3.2.3, “80960Jx 132-Lead PQFP Pinout” on
page 27.
Extended temperature devices are specified for operation at VCC = 3.3 V ± 0.15 V over a case
temperature range of -40° C to 100° C. Table 5 presents 80960Jx processor versions that are
available in the extended temperature 132-pin PQFP package and MPBGA package:
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix
variables in this document are now indicated with an "x".
Datasheet
15
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 5. 80960Jx Processors Available in Extended Temperature
Processor
Core Speed
Bus Speed
Package Type
x80960JA-25
x80960JS-25
x80960JS-33
x80960JC-66
x80960JT-100
x80960JC-66ET
25 MHz
25 MHz
33 MHz
66 Mhz
100 MHz
66 MHz
25 MHz
25 MHz
33 MHz
33 MHz
33 MHz
33 MHz
PQFP
PQFP
PQFP
PQFP
PQFP
MPBGA
The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at
VCC = 3.3 V ± 0.15 V over a case temperature range of 0° C to 100° C. Table 6 presents the
80960Jx processor versions that are available in the 196-ball MPBGA package:
Table 6. 80960Jx Processors Available in 196-Ball MPBGA Package
Processor
Core Speed
Bus Speed
x80960JT-100
x80960JC-66
x80960JS-33
x80960JS-25
x80960JD-50
x80960JA/JF-33
100 MHz
66 MHz
33 MHz
25 MHz
50 MHz
33 MHz
33 MHz
33 MHz
33 MHz
25 MHz
25 MHz
33 MHz
For pinout diagrams of the PQFP package, see Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout”
on page 30.
For additional package specifications and information, refer to the Intel Packaging Databook,
available in individual chapters, at http://www.intel.com.
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix
variables in this document are now indicated with an "x".
3.2
Pin Descriptions
This section describes the pins for the 80960Jx processors. For a description of pin function, see
Section 3.2.1, “Functional Pin Definitions” on page 16. Refer to the following sections for pinout
information for the three package types:
• Section 3.2.2, “80960Jx 132-Lead PGA Pinout” on page 23.
• Section 3.2.3, “80960Jx 132-Lead PQFP Pinout” on page 27.
• Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page 30.
3.2.1
Functional Pin Definitions
Table 7 presents the legend for interpreting the three pin description tables that follow. These tables
define the pins associated with the bus interface, basic control and test functions, and the Interrupt
Unit.
16
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 7. Pin Description Nomenclature
Symbol
Description
I
O
Input pin only.
Output pin only.
I/O
–
Pin may be either an input or output.
Pin must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.
S
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to CLKIN.
A (...)
A(E) Edge sensitive input
A(L) Level sensitive input
While the processor’s RESET# pin is asserted, the pin:
R(1) is driven to V
R(0) is driven to V
CC
R (...)
SS
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to V
CC
While the processor is in the hold state, the pin:
H(1) is driven to V
H(0) is driven to V
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
CC
H (...)
P (...)
SS
While the processor is halted, the pin:
P(1) is driven to V
P(0) is driven to V
CC
SS
P(Q) Maintains previous state or continues to be a valid output
Datasheet
17
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 8. Pin Description—External Bus Signals (Sheet 1 of 4)
NAME
TYPE
DESCRIPTION
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (T ) cycle, bits 31:2 contain a physical word
a
address (bits 0-1 indicate SIZE; see below). During a data (T ) cycle, read or write
d
data is present on one or more contiguous bytes, comprising AD[31:24], AD[23:16],
AD[15:8] and AD[7:0]. During write operations, unused pins are driven to
determinate values.
SIZE, which comprises bits 0-1 of the AD lines during a T cycle, specifies the
a
number of data transfers during the bus transaction.
AD1
AD0
Bus Transfers
1 Transfer
I/O
S(L)
R(X)
H(Z)
P(Q)
0
0
1
1
0
1
0
1
AD[31:0]
2 Transfers
3 Transfers
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
•
•
write — AD[31:2] are driven with the last data value on the AD bus.
read — AD[31:4] are driven with the last address value on the AD bus; AD[3:2]
are driven with the value of A[3:2] from the last data cycle.
Typically, AD[1:0] reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
O
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
R(0)
H(Z)
P(0)
ALE
ALE#
ADS#
asserted during a T cycle and deasserted before the beginning of the T state. It is
a
d
active HIGH and floats to a high impedance state during a hold cycle (T ).
h
O
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE# is
the inverted version of ALE. This signal gives the 80960Jx a high degree of
compatibility with existing 80960Kx systems.
R(1)
H(Z)
P(1)
O
ADDRESS STROBE indicates a valid address and the start of a new bus access.
R(1)
H(Z)
P(1)
The processor asserts ADS# for the entire T cycle. External bus control logic
a
typically samples ADS# at the end of the cycle.
ADDRESS[3:2] comprise a partial demultiplexed address bus.
32-bit memory accesses: the processor asserts address bits A[3:2] during T . The
a
partial word address increments with each assertion of RDYRCV# during a burst.
O
R(X)
H(Z)
P(Q)
16-bit memory accesses: the processor asserts address bits A[3:1] during T with A1
driven on the BE1# pin. The partial short word address increments with each
assertion of RDYRCV# during a burst.
a
A[3:2]
8-bit memory accesses: the processor asserts address bits A[3:0] during T , with
a
A[1:0] driven on BE[1:0]#. The partial byte address increments with each assertion of
RDYRCV# during a burst.
18
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 8. Pin Description—External Bus Signals (Sheet 2 of 4)
NAME
TYPE
DESCRIPTION
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3# enables data on AD[31:24]
BE2# enables data on AD[23:16]
BE1# enables data on AD[15:8]
BE0# enables data on AD[7:0]
16-bit bus:
BE3# becomes Byte High Enable (enables data on AD[15:8])
BE2# is not used (state is high)
O
R(1)
H(Z)
P(1)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Byte Low Enable (enables data on AD[7:0])
BE[3:0]#
8-bit bus:
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during T .
a
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last T cycle.
d
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A[3:2] described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus
transaction:
WIDTH/
HLTD1
WIDTH/
HLTD0
O
0
0
1
1
0
1
0
1
8 Bits Wide
WIDTH/
HLTD[1:0]
R(0)
H(Z)
P(1)
16 Bits Wide
32 Bits Wide
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
DATA/CODE indicates that a bus access is a data access (1) or an instruction
access (0). D/C# has the same timing as W/R#.
O
R(X)
H(Z)
P(Q)
D/C#
0 = instruction access
1 = data access
WRITE/READ specifies, during a T cycle, whether the operation is a write (1) or
a
O
read (0). It is latched on-chip and remains valid during T cycles.
d
R(0)
H(Z)
P(Q)
W/R#
0 = read
1 = write
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
O
address/data bus. It is low during T and T /T cycles for a read; it is high during T
a
w
d
a
R(0)
H(Z)
P(Q)
and T /T cycles for a write. DT/R# never changes state when DEN# is asserted.
w d
DT/R#
0 = receive
1 = transmit
Datasheet
19
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 8. Pin Description—External Bus Signals (Sheet 3 of 4)
NAME
TYPE
DESCRIPTION
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is
asserted at the start of the first data cycle in a bus access and deasserted at the end
of the last data cycle. DEN# is used with DT/R# to provide control for data
transceivers connected to the data bus.
O
R(1)
H(Z)
P(1)
DEN#
0 = data cycle
1 = not data cycle
BURST LAST indicates the last transfer in a bus access. BLAST# is asserted in the
last data transfer of burst and non-burst accesses. BLAST# remains active as long
as wait states are inserted through the RDYRCV# pin. BLAST# becomes inactive
after the final data transfer in a bus cycle.
O
R(1)
H(Z)
P(1)
BLAST#
0 = last data transfer
1 = not last data transfer
READY/RECOVER indicates that data on AD lines may be sampled or removed.
When RDYRCV# is not asserted during a T cycle, the T cycle is extended to the
d
d
next cycle by inserting a wait state (T ).
w
0 = sample data
1 = don’t sample data
I
RDYRCV#
S(L)
The RDYRCV# pin has another function during the recovery (T ) state. The
r
processor continues to insert additional recovery states until it samples the pin
HIGH. This function gives slow external devices more time to float their buffers
before the processor begins to drive address again.
0 = insert wait states
1 = recovery complete
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK# output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK#. This prevents external agents from accessing memory involved
in semaphore operations.
I/O
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
S(L)
R(H)
H(Z)
P(1)
LOCK#/
ONCE#
ONCE MODE: The processor samples the ONCE# input during reset. When it is
asserted LOW at the end of reset, the processor enters ONCE mode. In ONCE
mode, the processor stops all clocks and floats all output pins. The pin has a weak
internal pullup which is active during reset to ensure normal operation when the pin
is left unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T state. When
h
I
HOLD is deasserted, the processor deasserts HOLDA and enters either the T or T
i
a
HOLD
S(L)
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
20
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 8. Pin Description—External Bus Signals (Sheet 4 of 4)
NAME
TYPE
DESCRIPTION
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
O
relinquished control of the bus. The processor may grant HOLD requests and enter
R(Q)
H(1)
P(Q)
the T state during reset and while halted as well as during regular operation.
h
HOLDA
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960® Jx Microprocessor Developer’s Manual (272483).
Arbitration logic may examine this signal to determine when an external bus master
should acquire/relinquish the bus.
O
R(0)
H(Q)
P(0)
BSTAT
0 = no potential stall
1 = potential stall
Table 9. Pin Description—Processor Control Signals, Test Signals, and Power (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
CLOCK INPUT provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
CLKIN
I
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK#/ONCE#,
STEST and HOLD.
I
RESET#
A(L)
The RESET# pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET# must be asserted a minimum of 10,000
CLKIN cycles with V and CLKIN stable. On a warm reset, RESET# should be
CC
asserted for a minimum of 15 cycles.
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
I
STEST
S(L)
0 = self test disabled
1 = self test enabled
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL# is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
O
•
When self-test passes, the processor deasserts FAIL# and begins operation
from user code.
R(0)
H(Q)
P(1)
FAIL#
•
When self-test fails, the processor asserts FAIL# and then stops executing.
0 = self test failed
1 = self test passed
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TCK
TDI
I
I
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge
of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
S(L)
Datasheet
21
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 9. Pin Description—Processor Control Signals, Test Signals, and Power (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION
O
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
R(Q)
HQ)
P(Q)
TDO
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
I
TRST#
TMS
feature, connect a pull-down resistor between this pin and V . When TAP is not
SS
A(L)
used, this pin must be connected to V ; however, no resistor is required. See
SS
Section 4.3, “Connection Recommendations” on page 36.
I
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of
the test logic for IEEE 1149.1 Boundary Scan testing.
S(L)
V
–
–
POWER pins intended for external connection to a V board plane.
CC
CC
PLL POWER is a separate V supply pin for the phase lock loop clock generator. It
CC
is intended for external connection to the V board plane. In noisy environments,
CC
VCCPLL
VCC5
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on
timing relationships.
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
buffers. This signal should be connected to +5 V for use with inputs which exceed
3.3 V. When all inputs are from 3.3 V components, this pin should be connected to
3.3 V.
–
V
–
–
GROUND pins intended for external connection to a V board plane.
SS
SS
NC
NO CONNECT pins. Do not make any system connections to these pins.
Table 10. Pin Description—Interrupt Unit Signals
NAME
TYPE
DESCRIPTION
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT[7:0]#
pins may be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
may be programmed to be level (low) or edge (falling) sensitive.
I
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
XINT[7:0]#
A(E/L)
Mixed Mode: The XINT[7:5]# pins act as dedicated sources and the XINT[4:0]# pins
act as the five most significant bits of a vectored source. The least significant bits of
the vectored source are set to 010 internally.
2
Unused external interrupt pins should be connected to V
.
CC
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI# is the highest priority interrupt source and is falling edge-triggered. when NMI#
I
NMI#
A(E)
is unused, it should be connected to V
.
CC
22
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
3.2.2
80960Jx 132-Lead PGA Pinout
Figure 3. 132-Lead Pin Grid Array Top View-Pins Facing Down
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P
P
AD6 AD11 AD13
V
V
V
V
V
V
V
CC
AD18 AD19 AD22 AD25
AD20 AD24 AD26 AD27
CC
CC
SS
CC
CC
CC
CC
N
N
AD3
AD0
AD7 AD10
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
M
M
AD9
AD12
AD21 AD23
AD4 AD8
AD1 AD5
AD14 AD15 AD16
AD17
NC AD29 AD30
AD28 BE3# BE2#
L
L
V
V
CC
CC
K
J
K
J
V
AD2
AD31
BE1#
V
V
SS
SS
SS
CC
CC
V
V
V
V
NC
VCCPLL
NC
V
V
CC
SS
H
G
F
E
D
x80960Jx
H
G
F
E
D
CLKIN
BE0#
ALE
V
V
V
SS
SS
SS
CC
M
© 19xx
V
V
V
V
SS
CC
CC
i
BSTAT
V
V
V
V
V
V
RDYRCV#
SS
SS
SS
CC
CC
XXXXXXXX SS
V
RESET#
TDI
CC
DEN#
DT/R#
CC
SS
SS
V
V
V
CC
SS
CC
C
B
A
C
B
A
LOCK#/
ONCE#
NC STESTTRST#XINT0#XINT1# HOLD NC
VCC5
FAIL#
A2
A3 BLAST# HOLDA
NC
TCK XINT3#XINT4#XINT6#
V
V
V
V
SS
NC TDO WIDTH/ D/C# W/R#
HLTD0
SS
SS
SS
NC
NC
ALE#
TMS XINT2# XINT5#XINT7# NMI#
V
V
V
V
WIDTH/ ADS#
HLTD1
CC
CC
CC
CC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix
variables in this document are now indicated with an "x".
Datasheet
23
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 4. 132-Lead Pin Grid Array Bottom View-Pins Facing Up
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
P
AD25 AD22 AD19 AD18
AD27 AD26 AD24 AD20
V
V
V
V
V
V
V
CC
AD13 AD11
AD10 AD7
AD6
AD3
CC
CC
CC
SS
CC
CC
SS
CC
N
N
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
M
M
AD23 AD21
AD12
AD9
AD17 AD16 AD15 AD14
AD8 AD4
AD5 AD1
AD0
AD30 AD29 NC
BE2# BE3# AD28
L
K
J
L
K
J
V
CC
CC
V
V
V
V
V
V
AD31
BE1#
AD2
NC
SS
CC
CC
SS
V
V
V
SS
SS
SS
CC
SS
H
G
F
H
G
F
VCCPLL V
CLKIN
V
V
BE0#
ALE
CC
CC
SS
V
NC
V
V
SS
SS
SS
CC
BSTAT
V
V
V
V
RDYRCV#V
RESET# V
V
CC
CC
SS
SS
SS
CC
E
D
E
D
V
DEN#
DT/R#
CC
V
V
TDI
V
V
CC
CC
SS
C
B
A
C
B
A
LOCK#/
ONCE#
HOLDA BLAST# A3
A2
FAIL#
VCC5
NC HOLD XINT1#XINT0# TRST#STEST NC
W/R# D/C# WIDTH/ TDO NC
HLTD0
V
V
V
V
SS
XINT6#XINT4#XINT3# TCK
NC
SS
SS
SS
ALE#
NC
NC
ADS# WIDTH/
HLTD1
V
V
V
V
NMI# XINT7#XINT5# XINT2# TMS
CC
CC
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 11. 132-Lead PGA Pinout—In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A2
C5
C4
AD31
ADS#
ALE
K3
A1
TDO
TMS
B4
A14
C12
A6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
B9
D2
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
A3
AD0
M14
L13
K12
N14
M13
L12
P14
N13
M12
M11
N12
P13
M10
P12
M9
G3
A3
TRST#
D13
E2
AD1
ALE#
BE0#
BE1#
BE2#
BE3#
BLAST#
BSTAT
CLKIN
D/C#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
AD2
H3
A7
E13
F2
AD3
J3
A8
AD4
L1
A9
F13
G2
AD5
L2
D1
AD6
C3
D14
E1
G13
H2
AD7
F3
AD8
H14
B2
E14
F1
H13
J2
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
DEN#
DT/R#
FAIL#
HOLD
HOLDA
LOCK#/ONCE#
NC
E3
F14
G1
G14
H1
J13
K2
D3
C6
K13
N5
C9
C2
J1
N6
M8
C1
J14
K1
N7
M7
A4
N8
M6
NC
A5
K14
L14
P5
N9
P4
NC
B5
N10
N11
B1
P3
NC
B14
C8
N4
NC
P6
W/R#
WIDTH/HLTD0
WIDTH/HLTD1
XINT0#
M5
NC
C14
G12
J12
M3
A10
F12
E12
C13
B13
D12
P7
B3
P2
NC
P8
A2
M4
NC
P9
C11
C10
A13
B12
B11
A12
B10
A11
N3
NC
P10
P11
H12
C7
XINT1#
P1
NMI#
XINT2#
N2
RDYRCV#
RESET#
STEST
TCK
VCCPLL
VCC5
XINT3#
N1
XINT4#
L3
V
V
V
B6
XINT5#
SS
SS
SS
M2
B7
XINT6#
M1
TDI
B8
XINT7#
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Datasheet
25
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 12. 132-Lead PGA Pinout—In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
A2
ADS#
WIDTH/HLTD1
ALE#
C6
C7
FAIL#
VCC5
NC
H1
H2
V
M10
M11
M12
M13
M14
N1
AD12
AD9
CC
V
SS
A3
C8
H3
BE0#
AD8
A4
NC
C9
HOLD
XINT1#
XINT0#
TRST#
STEST
NC
H12
H13
H14
J1
VCCPLL
AD4
A5
NC
C10
C11
C12
C13
C14
D1
V
AD0
SS
A6
V
V
V
V
CLKIN
AD27
AD26
AD24
AD20
CC
CC
CC
CC
A7
V
N2
CC
A8
J2
V
N3
SS
A9
J3
BE1#
NC
N4
A10
A11
A12
A13
A14
B1
NMI#
XINT7#
XINT5#
XINT2#
TMS
V
J12
J13
J14
K1
N5
V
V
V
V
V
V
V
CC
SS
SS
SS
SS
SS
SS
SS
D2
V
V
N6
SS
SS
CC
CC
D3
DT/R#
TDI
V
V
N7
D12
D13
D14
E1
N8
V
K2
V
N9
SS
CC
CC
SS
W/R#
V
V
K3
AD31
AD2
N10
N11
N12
N13
N14
P1
B2
D/C#
K12
K13
K14
L1
B3
WIDTH/HLTD0
TDO
E2
V
V
AD10
AD7
SS
SS
CC
B4
E3
DEN#
V
B5
NC
E12
E13
E14
F1
RESET#
BE2#
BE3#
AD28
AD5
AD3
B6
V
V
V
V
V
L2
AD25
AD22
AD19
AD18
SS
SS
SS
SS
SS
CC
CC
B7
V
V
L3
P2
B8
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
P3
B9
F2
V
AD1
P4
SS
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
XINT6#
XINT4#
XINT3#
TCK
F3
BSTAT
V
P5
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
F12
F13
F14
G1
RDYRCV#
AD30
AD29
NC
P6
V
P7
SS
CC
CC
V
V
P8
NC
AD23
AD21
AD17
AD16
AD15
AD14
P9
LOCK#/ONCE#
HOLDA
BLAST#
A3
G2
V
P10
P11
P12
P13
P14
SS
G3
ALE
NC
G12
G13
G14
AD13
AD11
AD6
V
SS
CC
A2
V
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
26
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
3.2.3
80960Jx 132-Lead PQFP Pinout
Figure 5. 132-Lead PQFP - Top View
AD9
TRST#
TCK
TMS
HOLD
XINT0#
XINT1#
XINT2#
1
2
3
4
5
6
7
99
98
V
(I/O)
(I/O)
CC
V
97
96
95
94
93
SS
AD10
AD11
V
V
V
(I/O)
(I/O)
(Core)
CC
SS
CC
XINT3#
92
91
90
8
9
10
V
(Core)
V
V
(I/O)
SS
CC
AD12
(I/O)
SS
89
88
87
86
85
84
83
82
81
80
79
78
11
12
13
14
15
16
17
18
19
20
21
22
AD13
AD14
AD15
XINT4#
XINT5#
XINT6#
V
(I/O)
XINT7#
NMI#
CC
V
(I/O)
SS
®
AD16
AD17
AD18
AD19
V
V
(Core)
(Core)
CC
SS
i960
NC
NC
V
V
(I/O)
(I/O)
VCC5
NC
NC
FAIL#
ALE#
TDO
CC
SS
AD20
AD21
AD22
AD23
x80960Jx
77
76
75
74
73
72
71
23
24
25
26
27
28
29
XXXXXXXX SS
V
(Core)
V
V
(I/O)
CC
CC
M
© 19xx
V
(Core)
(I/O)
SS
SS
i
V
V
(I/O)
(I/O)
WIDTH/HLTD1
CC
V
V
(Core)
(Core)
SS
CC
AD24
70
69
68
67
30
31
32
33
SS
WIDTH/HLTD0
A2
AD25
AD26
NC
A3
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix
variables in this document are now indicated with an "x".
Datasheet
27
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 13. 132-Lead PQFP Pinout—In Signal Order
Signal
Pin
Signal
Pin
Signal
(Core)
Pin
Signal
(Core)
SS
Pin
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
60
61
ALE#
ADS#
24
36
33
32
55
54
53
52
28
31
35
37
42
43
34
132
50
4
V
V
V
V
V
V
V
47
59
V
124
10
27
40
48
56
64
71
79
85
93
97
106
112
131
18
19
21
22
67
121
122
126
127
14
13
12
11
CC
CC
CC
CC
CC
CC
CC
(Core)
(Core)
(Core)
(Core)
(Core)
(Core)
V
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
62
A3
74
V
V
V
V
V
V
V
V
V
V
V
V
V
63
A2
92
66
BE3#
113
115
123
9
68
BE2#
69
BE1#
70
BE0#
V
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
75
WIDTH/HLTD1
WIDTH/HLTD0
D/C#
V
V
V
V
V
V
V
V
V
V
V
V
V
26
76
41
77
49
78
W/R#
57
81
DT/R#
65
82
DEN#
72
83
BLAST#
RDYRCV#
LOCK#/ONCE#
HOLD
80
84
86
NC
87
94
NC
NC
NC
NC
NC
NC
NC
NC
88
98
89
HOLDA
BSTAT
CLKIN
RESET#
STEST
FAIL#
44
51
117
125
128
23
2
105
111
129
119
20
90
95
96
VCCPLL
VCC5
99
AD8
100
101
102
103
104
107
108
109
110
45
V
(CLK)
(Core)
(Core)
(Core)
(Core)
(Core)
(Core)
(Core)
(Core)
(Core)
118
17
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
AD7
TCK
V
V
V
V
V
V
V
V
V
XINT7#
XINT6#
XINT5#
XINT4#
XINT3#
XINT2#
XINT1#
XINT0#
NMI#
AD6
TDI
130
25
1
30
AD5
TDO
38
AD4
TRST#
TMS
46
AD3
3
58
8
AD2
V
(CLK)
(Core)
(Core)
(Core)
120
16
29
39
73
7
CC
CC
CC
CC
AD1
V
V
V
91
6
AD0
114
116
5
ALE
15
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
28
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 14. 132-Lead PQFP Pinout—In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
TRST#
TCK
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
BLAST#
D/C#
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
AD8
AD7
AD6
AD5
AD4
2
AD26
AD25
AD24
3
TMS
ADS#
W/R#
4
HOLD
XINT0#
XINT1#
XINT2#
XINT3#
5
V
V
(Core)
(Core)
V
(I/O)
(I/O)
SS
CC
SS
CC
6
V
V
(I/O)
CC
7
V
(I/O)
(I/O)
V
(Core)
(Core)
V
(I/O)
SS
CC
SS
CC
SS
8
V
V
AD3
9
V
(I/O)
(I/O)
DT/R#
DEN#
HOLDA
ALE
AD23
AD2
AD1
AD0
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
V
AD22
AD21
AD20
SS
XINT4#
XINT5#
XINT6#
XINT7#
NMI#
V
(I/O)
CC
V
V
(Core)
(Core)
V
(I/O)
V
(I/O)
SS
CC
SS
CC
SS
V
(I/O)
V
(Core)
(Core)
(Core)
(Core)
CC
SS
CC
SS
V
(I/O)
(I/O)
AD19
AD18
AD17
AD16
V
V
V
SS
CC
V
V
(Core)
V
CC
SS
(Core)
NC
LOCK#/ONCE#
BSTAT
BE0#
CLKIN
V (CLK)
SS
NC
V
(I/O)
SS
CC
VCC5
NC
BE1#
V
(I/O)
VCCPLL
BE2#
AD15
AD14
AD13
AD12
V
CC (CLK)
NC
BE3#
NC
FAIL#
ALE#
TDO
V
(I/O)
(I/O)
NC
SS
CC
V
V
(Core)
(Core)
CC
SS
V
(Core)
(Core)
V
(Core)
V
SS
CC
SS
CC
V
(I/O)
V
V
(Core)
RESET#
NC
CC
V
(I/O)
AD31
V
(I/O)
(I/O)
SS
SS
CC
WIDTH/HLTD1
AD30
AD29
AD28
V
NC
V
V
(Core)
(Core)
AD11
AD10
STEST
CC
SS
V
(I/O)
CC
WIDTH/HLTD0
V
(I/O)
V
(I/O)
TDI
(I/O)
SS
CC
SS
CC
A2
A3
V
(I/O)
V
(I/O)
V
SS
AD27
AD9
RDYRCV#
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Datasheet
29
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
3.2.4
80960Jx 196-Ball MPBGA Pinout
Figure 6. 196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
A
B
C
NC
AD28
V
NC
V
V
AD22
V
AD18
V
AD15 AD13
V
CC
AD8
NC
CC
CC
CC
CC
V
AD30 AD27 AD29
AD23 AD20 AD17 AD14 AD12 AD10 AD9 AD7
AD4
CC
CC
AD26 AD25 AD24 AD21 AD19 AD16
V
V
AD11 AD6
AD5 AD0
AD2
AD1
NC
NC
AD31
NC
NC
NC
CC
CC
D
E
F
G
H
J
D
E
F
G
H
J
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
AD3
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
NC
NC
NC
NC
NC
NC
V
V
V
CC
CC
CC
CC
SS
SS
SS
SS
CC
CC
VCCPLL
V
V
V
V
V
CC
CC
SS
SS
SS
SS
SS
SS
SS
SS
NC CLKIN NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
NC
V
NC
SS
SS
BE1# BE2# BE3#
CC
BSTAT
V
V
V
BE0#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
TDI
NC
NC
NC RESET#
CC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
K
L
K
L
LOCK#/
ONCE#
ALE
V
STEST
V
V
V
V
V
CC
CC
SS
SS
HOLDA DEN#
V
V
V
V
NC RDYRCV#
CC
SS
SS
SS
SS
SS
M
N
M
N
DT/R#
V
NC
NC
NC
NC
A3
A2
V
V
ALE# VCC5
V
XINT2# XINT0# TMS TRST# TCK
CC
CC
CC
W/R# D/C#
TDO
NC XINT4# NC XINT6#XINT1#XINT3# HOLD
CC
P
P
BLAST#
V
WIDTH0
NC
ADS#
WIDTH1FAIL#
NC
NC
NMI# XINT7#XINT5#
V
NC
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
30
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 7. 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
A
B
C
NC
AD8
V
AD13 AD15
V
AD18
V
AD22
V
NC
V
CC
AD28
NC
CC
CC
CC
CC
AD4
AD7 AD9 AD10 AD12 AD14 AD17 AD20 AD23
V
AD29 AD27 AD30
V
CC
CC
V
V
AD25 AD26
AD2
AD1
AD6 AD11
AD0 AD5
AD16 AD19 AD21 AD24
NC
NC
AD31
NC
NC
NC
CC
CC
D
E
F
G
H
J
D
E
F
G
H
J
AD3
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
CC
CC
CC
CC
SS
CC
VCCPLL
V
V
V
V
V
V
V
V
V
V
NC
NC
NC
NC
CC
SS
SS
SS
SS
SS
SS
SS
SS
CC
CC
NC CLKIN NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
BE3# BE2# BE1#
NC
V
NC
CC
V
V
BSTAT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
BE0#
V
CC
SS
SS
RESET# NC
TDI
NC
NC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
K
L
K
L
ALE
LOCK#/
ONCE#
STEST
V
CC
V
V
V
V
V
SS
SS
SS
CC
RDYRCV# NC
V
V
V
V
CC
DEN# HOLDA
SS
SS
SS
SS
M
N
M
N
DT/R#
TCK TRST# TMS XINT0# XINT2#
V
VCC5 ALE#
V
V
A3
A2
NC
NC
NC
NC
V
CC
CC
CC
HOLD XINT3# XINT1# XINT6# NC XINT4# NC
TDO
D/C# W/R#
CC
P
P
WIDTH0 V
BLAST#
NC
V
XINT5# XINT7# NMI# NC
NC
FAIL# WIDTH1
ADS#
NC
CC
CC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Datasheet
31
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 15. 196-Ball MPBGA Pinout—In Signal Order (Sheet 1 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A2
N5
M5
D13
D14
C14
D11
B14
D12
C13
B13
A13
B12
B11
C12
B10
A11
B9
BE0#
BE1#
BE2#
BE3#
BLAST#
BSTAT
CLKIN
DEN#
D/C#
DT/R#
FAIL#
HOLD
HOLDA
LOCK#/ONCE#
NC
J2
H1
NC
NC
M4
N3
V
V
V
V
V
V
V
V
V
V
J1
K3
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
A3
AD0
H2
NC
N4
K13
L3
AD1
H3
NC
N8
AD2
P3
NC
N10
P1
M2
M6
M9
N6
P4
AD3
J3
NC
AD4
G13
L2
NC
P8
AD5
NC
P9
AD6
N2
NC
P14
P10
L14
J14
K14
M14
J12
N7
AD7
M1
P7
NMI#
RDYRCV#
RESET#
STEST
TCK
TDI
P13
F14
D4
D5
D6
D7
D8
D9
D10
E4
AD8
VCCPLL
AD9
N14
L1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
ADS#
ALE
K2
A1
NC
A4
TDO
TMS
TRST#
VCC5
NC
A14
C1
M12
M13
M8
A10
C9
NC
NC
C3
B8
NC
D1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A3
E5
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
A8
NC
D2
A5
E6
C8
NC
D3
A7
E7
B7
NC
E1
A9
E8
C7
NC
E2
A12
B1
E9
A6
NC
F1
E10
E11
F4
B6
NC
F2
B5
C6
NC
G1
G2
G12
G14
H12
H14
J13
K12
L12
L13
M3
C10
C11
E3
C5
NC
F5
C4
NC
F6
B3
NC
E12
E13
E14
F3
F7
A2
NC
F8
B4
NC
F9
B2
NC
F10
F11
G4
G5
G6
C2
NC
F12
F13
G3
P2
NC
K1
NC
ALE#
M7
NC
H13
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
32
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 15. 196-Ball MPBGA Pinout—In Signal Order (Sheet 2 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G7
G8
V
V
V
V
V
V
V
V
V
V
V
V
H11
J4
V
V
V
V
V
V
V
V
V
V
V
V
K7
K8
K9
K10
K11
L5
V
SS
L11
P5
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
WIDTH0
WIDTH1
W/R#
G9
J5
P6
G10
G11
H4
J6
N1
J7
XINT0#
XINT1#
XINT2#
XINT3#
XINT4#
XINT5#
XINT6#
XINT7#
M11
N12
M10
N13
N9
J8
H5
J9
L6
H6
J10
J11
K4
K5
K6
L7
H7
L8
H8
L9
P12
N11
P11
H9
L10
L4
H10
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 16. 196-Ball MPBGA Pinout—In Pin Order (Sheet 1 of 2)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
BSTAT
A1
A2
NC
C11
C12
C13
C14
D1
V
F7
F8
V
V
V
V
V
V
V
J3
J4
CC
SS
SS
SS
SS
SS
CC
CC
AD28
AD11
AD6
AD2
NC
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
A3
V
F9
J5
CC
A4
NC
F10
F11
F12
F13
F14
G1
J6
A5
V
J7
CC
A6
AD22
D2
NC
J8
A7
V
D3
NC
J9
CC
A8
AD18
D4
V
V
V
V
V
V
V
VCCPLL
NC
J10
J11
J12
J13
J14
K1
K2
K3
K4
K5
K6
K7
K8
SS
SS
SS
SS
SS
SS
SS
A9
V
D5
CC
A10
A11
A12
A13
A14
B1
AD15
AD13
D6
G2
NC
TDI
NC
D7
G3
V
V
V
V
V
V
V
V
V
CC
SS
SS
SS
SS
SS
SS
SS
SS
V
D8
G4
RESET#
ALE
CC
AD8
NC
D9
G5
D10
D11
D12
D13
D14
E1
G6
LOCK#/ONCE#
V
AD3
AD5
AD0
AD1
NC
G7
V
CC
CC
B2
AD30
AD27
AD29
G8
V
V
V
V
V
SS
SS
SS
SS
SS
B3
G9
B4
G10
G11
G12
B5
V
CC
B6
AD23
E2
NC
NC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Datasheet
33
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 16. 196-Ball MPBGA Pinout—In Pin Order (Sheet 2 of 2)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
B7
B8
AD20
AD17
AD14
AD12
AD10
AD9
E3
E4
V
G13
G14
H1
CLKIN
NC
K9
K10
K11
K12
K13
K14
L1
V
V
V
CC
SS
SS
SS
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
CC
CC
CC
B9
E5
BE1#
BE2#
BE3#
B10
B11
B12
B13
B14
C1
E6
H2
NC
E7
H3
V
CC
E8
H4
V
V
V
V
V
V
V
V
STEST
SS
SS
SS
SS
SS
SS
SS
SS
AD7
E9
H5
HOLDA
DEN#
AD4
E10
E11
E12
E13
E14
F1
H6
L2
NC
H7
L3
V
CC
C2
AD31
NC
V
V
V
H8
L4
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
C3
H9
L5
C4
AD26
AD25
AD24
AD21
AD19
AD16
H10
H11
H12
H13
H14
J1
L6
C5
NC
NC
L7
C6
F2
NC
L8
C7
F3
V
V
L9
CC
CC
C8
F4
V
NC
L10
L11
L12
P4
SS
SS
SS
C9
F5
V
V
V
CC
C10
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
V
F6
J2
BE0#
NC
CC
NC
M10
M11
M12
M13
M14
N1
XINT2#
XINT0#
TMS
TRST#
TCK
N7
TDO
NC
V
CC
RDYRCV#
DT/R#
N8
P5
WIDTH0
N9
XINT4#
NC#
P6
WIDTH1
FAIL#
NC
V
N10
N11
N12
N13
N14
P1
P7
CC
NC
NC
A3
XINT6#
XINT1#
XINT3#
HOLD
NC
P8
W/R#
D/C#
NC
P9
NC
N2
P10
P11
P12
P13
P14
NMI#
V
N3
XINT7#
XINT5#
CC
ALE#
N4
NC
VCC5
N5
A2
P2
ADS#
BLAST#
V
CC
V
N6
V
P3
NC
CC
CC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
34
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
This document contains information on products in the production phase of development. The
specifications within this datasheet are subject to change without prior notice. Verify with your
local Intel sales office or the world wide web to ensure that you have the latest datasheet and device
specification update before finalizing a design.
Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These
are stress ratings only. Table 17 presents the absolute maximum ratings.
Table 17. Absolute Maximum Ratings
Parameter
Maximum Rating
–65o C to +150o C
Storage Temperature
Case Temperature Under Bias
Supply Voltage wrt. V
–65o C to +110o C
–0.5 V to + 4.6 V
–0.5 V to + 6.5 V
SS
Voltage on VCC5 wrt. VSS
Voltage on Other Pins wrt. V
–0.5 V to V + 0.5 V
SS
CC
4.2
Operating Conditions
Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Table 18 presents the operating conditions for the 80960Jx 3.3 V processors.
Table 18. 80960Jx Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
V
Supply Voltage
3.15
3.15
3.45
5.5
V
V
CC
VCC5
Input Protection Bias
(†)
Input Clock Frequency
80960JT-100
80960JC-66
15
15
15
15
15
12
12
12
12
12
12
12
33.3
33.3
25
33
25
33.3
25
20
16.67
33.3
25
80960JC-50
80960JS-33
80960JS-25
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA-16
f
MHz
CLKIN
16
Operating Case Temperature
PGA, MPBGA, and PQFP
T
0
-40
100
100
°C
C
Extended temp PQFP and MPBGA
†
See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 36.
Datasheet
35
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
4.3
Connection Recommendations
For clean on-chip power distribution, VCC and VSS pins separately feed the device’s functional
units. Power and ground connections must be made to all 80960Jx power and ground pins. On the
circuit board, every VCC pin should connect to a power plane and every VSS pin should connect to
a ground plane. Place liberal decoupling capacitance near the 80960Jx, since the processor may
cause transient power surges.
The 80960JS/JC/JT processors are produced on Intel’s advanced CMOS process. Proper bulk
decoupling must be used to prevent device damage during initial power up and during transitions
from low power mode to normal processor operation. Power supply behavior during these
transitions may cause the power supply to exceed the maximum VCC specification and may cause
device damage.
Pay special attention to the Test Reset (TRST#) pin. It is essential that the JTAG Boundary Scan
Test Access Port (TAP) controller initializes to a known state whether it may be used or not. When
the JTAG Boundary Scan function may be used, connect a pull-down resistor between the TRST#
pin and VSS. When the JTAG Boundary Scan function may not be used (even for board-level
testing), connect the TRST# pin to VSS.
Do not connect the TDI, TDO, and TCK pins when the TAP Controller may not be used.
Note: Pins identified as NC must not be connected in the system.
4.4
VCC5 Pin Requirements (VDIFF)
In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V VCC plane.
In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V
components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation, and
prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and its
3.3 V VCC pins must not exceed 2.25 V. When this requirement is not met, current flow through the
pin may exceed the value at which the processor is damaged. Instances when the voltage may
exceed 2.25 V is during power up or power down, where one source reaches its level faster than the
other, briefly causing an excess voltage differential. Another instance is during steady-state
operation, where the differential voltage of the regulator (provided a regulator is used) cannot be
maintained within 2.25 V. Two methods are possible to prevent this from happening:
• Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V.
or:
• As shown in Figure 8, place a 100 Ω resistor in series with the VCC5 pin to limit the current
through VCC5.
Figure 8. VCC5 Current-Limiting Resistor
+5 V (±0.25 V)
VCC5 Pin
100 Ω
(±5%, 0.5 W)
36
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
When the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple
and reliable method for limiting current. The resistor may also prevent damage in the case of a
power failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
Table 19. VDIFF Parameters
Symbol
Parameter
Min
Max
Units
Notes
VCC5 input should not exceed V by more than 2.25 V
during power-up and power-down, or during steady-
state operation.
CC
VCC5-V
Difference
CC
VDIFF
2.25
V
4.5
VCCPLL Pin Requirements
To reduce clock skew on the 80960Jx processor, the VCCPLL pin for the Phase Lock Loop (PLL)
circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise induced
clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor must be
low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node connecting
VCCPLL must be as short as possible.
When the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any
time, including the power up and power down sequences, excessive currents may permanently
damage on-chip electrostatic discharge (ESD) protection diodes. The damage may accumulate over
multiple episodes.
In actual applications, this problem occurs only when the VCCPLL and VCC pins are driven by
separate power supplies or voltage regulators. Applications that use one power supply for
VCCPLL and VCC are not typically at risk. Verify that your application does not allow the
VCCPLL voltage to exceed VCC by 0.5 V.
The VCCPLL low-pass filter recommendation does not promote this problem.
Figure 9. VCCPLL Lowpass Filter
100
10
Ω (80960JA/JF/JD)
Ω (80960JS/JC/JT)
VCCPLL
(On 80960Jx)
+
V
CC
4.7 µF
0.01 µF
(Board Plane)
F_CA078A
Datasheet
37
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
4.6
D.C. Specifications
Table 20. 80960Jx D.C. Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
Input Low Voltage
-0.3
2.0
0.8
V
V
V
V
V
IL
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Ground Bounce
V
+ 0.3
IH
CC5
V
0.4
I
= 3 mA
= -1 mA
(1,2)
OL
OH
OL
V
2.4
I
OH
V
<0.8
OLP
Input Capacitance
PGA
PQFP
15
15
15
C
pF
pF
pF
f
f
f
= f
= f
= f
(2)
(2)
(2)
IN
MIN
MIN
MIN
CLKIN
CLKIN
CLKIN
MPBGA
I/O or Output Capacitance
PGA
PQFP
MPBGA
15
15
15
C
C
OUT
CLK
CLKIN Capacitance
PGA
PQFP
15
15
15
MPBGA
NOTES:
1. Typical is measured with V = 3.3 V and temperature = 25°C.
CC
2. Not tested.
38
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 21. 80960Jx ICC Characteristics (Sheet 1 of 3)
Symbol
Parameter
Typ
Max
Units
Notes
0 ≤ V ≤ V
CC
Input Leakage Current for each pin
except TCK, TDI, TRST# and TMS
I
± 1
µA
LI1
LI2
IN
Input Leakage Current for TCK, TDI,
TRST# and TMS
80960 JA/JF/JD
I
-140
-250
-250
-300
µA
µA
kΩ
V
= 0.45V (1)
IN
80960 JS/JC/JT
0.4 ≤ V
≤
OUT
I
Output Leakage Current
± 1
LO
V
CC
Internal Pull-UP Resistance for
ONCE#, TMS, TDI and TRST#
R
20
30
pu
80960JT-100
505
80960JC-66
80960JC-50
360
280
80960JS-33
80960JS-25
240
185
I
Active
CC
mA
(2,3)
(Power Supply)
80960JD-66
80960JD-50
80960JD-40
80960JD-33
580
447
367
310
80960JA/JF-33
80960JA/JF-25
80960JA-16
320
241
154
80960JT-100
480
80960JC-66
80960JC-50
345
270
80960JS-33
80960JS-25
221
170
I
Active
CC
mA
(2,4)
(Thermal)
80960JD-66
80960JD-50
80960JD-40
80960JD-33
510
390
320
260
80960JA/JF-33
80960JA/JF-25
80960JA-16
271
215
152
Datasheet
39
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 21. 80960Jx ICC Characteristics (Sheet 2 of 3)
Symbol
Parameter
Typ
Max
Units
Notes
Reset mode
80960JT-100
380
80960JC-66
80960JC-50
275
210
80960JS-33
80960JS-25
240
182
80960JD-66
80960JD-50
80960JD-40
80960JD-33
475
425
345
300
80960JA/JF-33
80960JA/JF-25
80960JA-16
250
200
150
I
Test
CC
Halt mode
mA
(5)
(Power modes)
80960JT-100
52
80960JC-66
80960JC-50
45
34
80960JS-33
80960JS-25
35
30
80960JD-66
80960JD-50
80960JD-40
80960JD-33
50
40
34
29
80960JA/JF-33
80960JA/JF-25
80960JA-16
31
26
21
ONCE mode
10
40
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 21. 80960Jx ICC Characteristics (Sheet 3 of 3)
Symbol
Parameter
80960JT-100
Typ
Max
Units
Notes
80960JC-66
80960JC-50
80960JS-33
80960JS-25
ICC5 Current on the
VCC5 Pin
200
µA
(6)
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA-16
NOTES:
1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 10, “A.C. Test Load” on
page 45.
3. I Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
CC
one of the worst case instruction mixes with V = 3.45 V. This parameter is characterized but not tested.
CC
4. I Active (Thermal) value is provided for your system’s thermal management. Typical I is measured
CC
CC
with V =3.3 V and temperature = 25° C. This parameter is characterized but not tested.
CC
5. I Test (Power modes) refers to the I values that are tested when the 80960JD is in Reset mode, Halt
CC
CC
mode or ONCE mode with V = 3.45 V.
CC
6. I
is tested at V = 3.3 V, VCC5 = 5.25 V.
CC5
CC
Datasheet
41
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
4.7
A.C. Specifications
The 80960Jx A.C. timings are based upon device characterization.
Table 22. 80960Jx A.C. Characteristics (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
Input Clock Timings
CLKIN Frequency
80960JT-100
15
33.3
80960JC-66
80960JC-50
15
15
33.3
25
80960JS-33
80960JS-25
15
15
33.3
25
T
MHz
F
80960JD-66
80960JD-50
80960JD-40
80960JD-33
12
12
12
12
33.3
25
20
16.67
80960JA/JF-33
80960JA/JF-25
80960JA-16
12
12
12
33.3
25
16
CLKIN Period
80960JT-100
30
66.7
80960JC-66
80960JC-50
30
40
66.7
66.7
80960JS-33
80960JS-25
30
40
66.7
66.7
T
ns
C
80960JD-66
80960JD-50
80960JD-40
80960JD-33
30
40
50
60
83.3
83.3
83.3
83.3
80960JA/JF-33
80960JA/JF-25
80960JA-16
30
40
62.5
83.3
83.3
83.3
T
T
CLKIN Period Stability
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
± 250
ps
ns
ns
ns
ns
(1, 2)
CS
8
8
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
CH
T
CL
CR
T
4
4
T
CF
NOTE: See Table 23 on page 45 for note definitions for this table.
42
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 22. 80960Jx A.C. Characteristics (Sheet 2 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
Synchronous Output Timings
Output Valid Delay, Except ALE/ALE#
Inactive and DT/R# for 3.3 V input
signals
2.5
2.5
13.5
16.5
Same as above, but for 5.5 V input
signals
T
OV1
Extended Temp MPBGA and PQFP
(JS/JC/JT only):
ns
(2, 11)
Output Valid Delay, Except ALE/ALE#
Inactive and DT/R# for 3.3 V input
signals
1.75
1.75
13.5
16.5
Same as above, but for 5.5 V input
signals
Output Valid Delay, DT/R#
80960JS/JC/JT
80960JD
0.5T + 7 0.5T + 9
C
C
T
ns
ns
OV2
0.5T + 7 0.5T + 9
C
C
80960JA/JF
0.5T + 4 0.5T + 18
C
C
T
Output Float Delay
2.5
13.5
(4)
(5)
(5)
(6)
OF
Synchronous Input Timings
Input Setup to CLKIN — AD[31:0], NMI#,
XINT[7:0]#
80960JS/JC/JT
T
6
6
9
ns
ns
ns
IS1
80960JD
80960JA/JF
Input Hold from CLKIN — AD[31:0],
NMI#, XINT[7:0]#
80960JS/JC/JT
T
T
IH1
2.0
1.5
1.0
80960JD
80960JA/JF
Input Setup to CLKIN — RDYRCV# and
HOLD
80960JS/JC/JT
80960JD
6.5
6.5
IS2
80960JA/JF
10.0
Input Hold from CLKIN — RDYRCV#
and HOLD
T
T
1
ns
ns
(6)
(7)
IH2
Input Setup to CLKIN — RESET#
80960JS/JC/JT
7
7
8
IS3
80960JD
80960JA/JF
Input Hold from CLKIN — RESET#
80960JS/JC/JT
2
2
1
T
ns
ns
(7)
(8)
IH3
IS4
80960JD
80960JA/JF
Input Setup to RESET# — ONCE#,
STEST
7
7
8
T
80960JS/JC/JT
80960JD
80960JA/JF
NOTE: See Table 23 on page 45 for note definitions for this table.
Datasheet
43
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 22. 80960Jx A.C. Characteristics (Sheet 3 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
Input Hold from RESET# — ONCE#,
STEST
2
2
1
T
80960JS/JC/JT
80960JD
80960JA/JF
ns
(8)
IH4
Relative Output Timings
Address Valid to ALE/ALE# Inactive
T
For 3.3 V Data Input Signals
For 5.0 V Data Input Signals
0.5T - 5
ns
ns
(9)
LX
C
0.5T - 8
C
T
ALE/ALE# Width
LXL
LXA
DXD
T
Address Hold from ALE/ALE# Inactive
DT/R# Valid to DEN# Active
0.5T - 7
Equal Loading (9)
C
T
Boundary Scan Test Signal Timings
T
TCK Frequency
0.5T
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BSF
F
T
TCK High Time
15
15
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
BSCH
T
TCK Low Time
BSCL
BSCR
T
TCK Rise Time
5
5
T
TCK Fall Time
2.0 V to 0.8 V (1)
BSCF
BSIS1
BSIH1
T
T
Input Setup to TCK — TDI, TMS
Input Hold from TCK — TDI, TMS
TDO Valid Delay
4
6
3
3
3
3
T
T
T
T
30
30
30
30
(1, 10)
(1, 10)
(1, 10)
(1, 10)
BSOV1
BSOF1
BSOV2
BSOF2
TDO Float Delay
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
Input Setup to TCK — All Inputs
(Non-Test)
T
4
6
ns
ns
BSIS2
Input Hold from TCK — All Inputs
(Non-Test)
T
BSIH2
NOTE: See Table 23 on page 45 for note definitions for this table.
44
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 23. Note Definitions for Table 22, 80960Jx AC Characteristics
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is
OL
designed to be no longer than the valid delay.
5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI#
and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees
recognition at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be asserted
for a minimum of two CLKIN periods to ensure recognition.
6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE# and STEST# must be stable at the rising edge of RESET# for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11.Worst-case T condition occurs on I/O pins when pins transition from a floating high input to driving a low
OV
output state. The Address/Data Bus pins encounter this condition between the last access of a read, and
the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at 50 pF
loads.
4.7.1
A.C. Test Conditions and Derating Curves
The A.C. Specifications in Section 4.7, “A.C. Specifications” are tested with the 50 pF load
indicated in Figure 10.
Figure 10. A.C. Test Load
Output Pin
CL = 50 pF for all signals
CL
Refer to the following sections for the specified derating curves:
• Section 4.7.1.1, “Output Delay or Hold vs. Load Capacitance” on page 46
• Section 4.7.1.2, “TLX vs. AD Bus Load Capacitance” on page 47
Datasheet
45
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
4.7.1.1
Output Delay or Hold vs. Load Capacitance
Figure 11. Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals)
AC Timings vs. Load Capacitance
(3.3 V Signals)
nom + 10
nom + 8
nom + 6
nom + 4
nom + 2
nom + 0
50
100
150
AD Bus Capacitive Load (pF)
Figure 12. Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5 V Signals)
AC Timings vs. Load Capacitance
(5 V Signals)
nom + 16
nom + 14
nom + 12
nom + 10
nom + 8
nom + 6
nom + 4
nom + 2
nom + 0
50
100
150
AD Bus Capacitive Load (pF)
46
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 13. Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD
AC Timings vs. Load Capacitance
nom + 8
nom + 7
nom + 6
nom + 5
nom + 4
nom + 3
nom + 2
nom + 1
nom + 0
50
100
150
AD Bus Capacitive Load (pF)
Rise and Fall times are identical.
4.7.1.2
T
vs. AD Bus Load Capacitance
LX
Figure 14. TLX vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3 V Signals)
AC Timings vs. Load Capacitance
(3.3 V Signals)
nom - 10
nom - 8
nom - 6
nom - 4
nom - 2
nom - 0
50
100
150
AD Bus Capacitive Load (pF)
Datasheet
47
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Note: The TLX Derating curve applies only when an imbalance in the capacitive load occurs between the
AD bus and ALE. The TLX derating is based on a 50 pF load on ALE. The derating applies to ALE
and ALE#.
Figure 15. TLX vs. AD Bus Load Capacitance–80960JS/JC/JT (5 V Signals)
AC Timings vs. Load Capacitance
(5 V Signals)
nom - 20
nom - 15
nom - 10
nom - 5
nom - 0
50
100
150
AD Bus Capacitive Load (pF)
Note: The TLX Derating curve applies only when an imbalance in the capacitive load occurs between the
AD bus and ALE. The TLX derating is based on a 50 pF load on ALE. The derating applies to ALE
and ALE#.
Figure 16. TLX vs. AD Bus Load Capacitance–80960JA/JF/JD
AC Timings vs. Load Capacitance
nom- 8
nom- 7
nom- 6
nom- 5
nom- 4
nom- 3
nom- 2
nom- 1
nom- 0
50
100
150
AD Bus Capacitive Load (pF)
Rise and Fall times are identical.
48
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Note: The TLX Derating curve applies only when an imbalance in the capacitive load occurs between the
AD bus and ALE. The TLX derating is based on a 50 pF load on ALE. The derating applies to ALE
and ALE#.
4.7.1.3
ICC Active vs. Frequency
Figure 17. ICC Active (Power Supply) vs. Frequency–80960JA/JF
Icc Active (Pow er Supply) vs Frequency
350
300
250
200
150
100
50
0
12
15
18
21
24
27
30
33
CLKIN Fre quency M Hz
Figure 18. 80960JA/JF ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
300
250
200
150
100
50
0
12
15
18
21
24
27
30
33
CLKIN Frequency M Hz
Datasheet
49
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 19. 80960JD ICC Active (Power Supply) vs. Frequency
Icc Active (Pow er Supply) vs. Frequency
600
500
400
300
200
100
0
12
15
18
21
24
27
30
33
CLKIN Fre que ncy (M Hz)
Figure 20. 80960JD ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
600
500
400
300
200
100
0
12
15
18
21
24
27
30
33
CLKIN Fre que ncy (M Hz)
50
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 21. 80960JC ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs Frequency
80960 JC
400
350
300
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKIN Frequency MHz
Figure 22. 80960JC ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs Frequency
80960 JC
400
350
300
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKINFrequency MHz
Datasheet
51
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 23. 80960JS ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs Frequency
80960 JS
300
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKIN Frequency MHz
Figure 24. 80960JS ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
80960 JS
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKINFrequency MHz
52
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
4.7.2
A.C. Timing Waveforms
Figure 25. CLKIN Waveform
T
T
CF
CR
2.0 V
1. 5V
0.8 V
T
CH
T
CL
T
C
Figure 26. TOV1 Output Delay Waveform
1.5 V
1.5 V
CLKIN
T
OV1
AD[31:0],
ALE (active),
ALE# (active),
ADS#, A[3:2],
1.5 V
BE[3:0]#,
WIDTH/HLTD[1:0],
D/C#, W/R#, DEN#,
BLAST#, LOCK#,
HOLDA, BSTAT, FAIL#
Datasheet
53
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 27. TOF Output Float Waveform
1.5 V
1.5 V
CLKIN
T
OF
AD[31:0],
ALE, ALE#
ADS#, A[3:2],
BE[3:0]#,
WIDTH/HLTD[1:0],
D/C#, W/R#, DT/R#,
DEN#, BLAST#, LOCK#
Figure 28. TIS1 and TIH1 Input Setup and Hold Waveform
1.5 V
1.5 V
IH1
1.5 V
CLKIN
T
T
IS1
AD[31:0]
NMI#
Valid
1.5 V
XINT[7:0]#
Figure 29. TIS2 and TIH2 Input Setup and Hold Waveform
1.5 V
1.5 V
1.5 V
CLKIN
T
IH2
T
IS2
HOLD,
1.5 V
Valid
1.5 V
RDYRCV#
54
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 30. TIS3 and TIH3 Input Setup and Hold Waveform
1.5 V
1.5 V
CLKIN
T
T
IS3
IH3
RESET#
Figure 31. TIS4 and TIH4 Input Setup and Hold Waveform
RESET#
T
IH4
T
IS4
ONCE#,
STEST
Valid
Datasheet
55
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 32. TLX, TLXL and TLXA Relative Timings Waveform
Ta
Tw/Td
1.5 V
1.5 V
1.5 V
CLKIN
TLXL
ALE
1.5 V
Valid
1.5 V
1.5 V
ALE#
TLX
TLXA
1.5 V
AD[31:0]
Valid
Figure 33. DT/R# and DEN# Timings Waveform
Ta
Tw/Td
CLKIN
1.5 V
1.5 V
1.5 V
TOV2
Valid
DT/R#
TDXD
DEN#
TOV1
56
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 34. TCK Waveform
T
T
BSCR
BSCF
2.0 V
1.5 V
0.8 V
T
BSCH
T
BSCL
Figure 35. TBSIS1 and TBSIH1 Input Setup and Hold Waveforms
1.5 V
1.5 V
BSIH1
1.5 V
TCK
T
T
BSIS1
TMS
TDI
1.5V
Valid
1.5V
Figure 36. TBSOV1 and TBSOF1 Output Delay and Output Float Waveform
TCK
1.5 V
1.5 V
1.5 V
T
T
BSOV1
BSOF1
Valid
1.5 V
TDO
Datasheet
57
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 37. TBSOV2 and TBSOF2 Output Delay and Output Float Waveform
TCK
1.5 V
1.5 V
1.5 V
T
T
BSOF2
BSOV2
Non-Test
Outputs
Valid
1.5 V
Figure 38. TBSIS2 and TBSIH2 Input Setup and Hold Waveform
TCK
1.5 V
1.5 V
1.5 V
TBSIS2 TBSIH2
Non-Test
Inputs
1.5 V
Valid
1.5 V
58
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
5.0
Device Identification
80960Jx processors may be identified electrically, according to device type and stepping (see
Figure 39, and Table 25 through Table 30). Table 24 identifies the device type and stepping
for all 5 V, 80960Jx processors. Figure 39, and Table 25 through Table 30 identify all 3.3 V
to 5 V-tolerant 80960Jx processors. The device ID was enhanced to differentiate between 3.3 V and
5 V supply voltages, and between non-clock-doubled and clock-doubled cores when stepping from
the A2 stepping to the C0 stepping. The 32-bit identifier is accessible in several ways:
• Upon reset, the identifier is placed into the g0 register.
• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID
register at address FF008710H.
• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the
IDCODE instruction.
• The device and stepping letter is also printed on the top side of the product package.
Table 24. 80960Jx Device Type and Stepping Reference
Device and
Stepping
Version
Number
Complete ID
(Hex)
Part Number
Manufacturer
X
80960JT A0, A1
80960JC A1
80960JS A1
80960JD C0
80960JF C0
80960JA C0
0000
0011
0011
0011
0011
0011
0000 1000 0010 1011
0000 1000 0011 0011
0000 1000 0010 0011
0000 1000 0011 0000
0000 1000 0010 0000
0000 1000 0010 0001
0000 0001 001
0000 0001 001
0000 0001 001
0000 0001 001
0000 0001 001
0000 0001 001
1
1
1
1
1
1
0082B013
30833013
30823013
30830013
30820013
30821013
Datasheet
59
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
5.1
80960JS/JC/JT Device Identification Register
Figure 39. 80960JS/JC/JT Device Identification Register Fields
Part Number
Product
VCC
Type
Version
Gen
Model
Manufacturer ID
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0 0 1
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
Table 25. 80960JS/JC/JT Device ID Register Field Definitions
Field
Version
Value
Definition
See Table 26
Indicates major stepping changes.
Indicates that a device is 3.3 V.
V
0 = 3.3 V device
CC
000 100
(Indicates i960 CPU)
Product Type
Designates type of product.
Indicates the generation (or series) to which the
product belongs.
Generation Type 0001 = J-series
D DPCC
D = Clock Multiplier
(01) Clock-Tripled
(P) Product Derivative
(0) Jx
Indicates member within a series and specific model
information.
Model
C = Cache Size
(11) 16K I-cache, 4K D-cache
000 0000 1001
(Indicates Intel)
Manufacturer ID
Manufacturer ID assigned by IEEE.
Table 26. 80960JS/JC/JT Device ID Model Types
Device
Version
V
Product
Gen.
Model
Manufacturer ID
‘1’
CC
80960JT A0, A1
80960JC A1
80960JS A1
0000
0000
0000
0
000100
000100
000100
0001
0001
0001
01011
10011
00011
00000001001
00000001001
00000001001
1
1
1
0
0
60
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
5.2
80960JD Device Identification Register
Figure 40. 80960JD Device Identification Register Fields
Part Number
Product
VCC
Type
Version
Gen
Model
Manufacturer ID
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0 0 1
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
Table 27. 80960JD Device ID Field Definitions
Field
Version
Value
See Table 24.
Definition
Indicates major stepping changes.
Indicates that a device is 3.3 V.
0 = 3.3 V device
1 = 5 V device
V
CC
00 0100
(Indicates i960 CPU)
Product Type
Designates type of product.
Indicates the generation (or series) to which the product
belongs.
Generation Type 0001 = J-series
D000C
D = Clock Doubled
(0) Not Clock-Doubled
(1) Clock Doubled
Indicates member within a series and specific model
information.
Model
C = Cache Size
(0) 4K I-cache, 2K D-cache
(1) 2K I-cache, 1K D-cache
000 0000 1001
(Indicates Intel)
Manufacturer ID
Manufacturer ID assigned by IEEE.
Table 28. 80960JD Device ID Model Types
Device
80960JD C0
Version
V
Product
Gen.
Model
Manufacturer ID
‘1’
CC
0011
0
000100
0001
10000
00000001001
1
Datasheet
61
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
5.3
80960JA/JF Device Identification Register
Figure 41. 80960JA/JF Device Identification Register Fields
Part Number
Product
VCC
Type
Version
Gen
Model
Manufacturer ID
1
0
0
0
0
1
0
0
0
0 0 1
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
Table 29. 80960JA/JF Device ID Field Definitions
Field
Version
Value
Definition
See Table 30.
Indicates major stepping changes.
Indicates that a device is 3.3 V.
0 = 3.3 V device
1 = 5 V device
V
CC
00 0100
(Indicates i960 CPU)
Product Type
Designates type of product.
Indicates the generation (or series) to which the
product belongs.
Generation Type 0001 = J-series
0000C
C = Cache Size
Model
Indicates member within a series and specific
model information.
0 = 4K I-cache, 2K D-cache
1 = 2K I-cache, 1K D-cache
000 0000 1001
(Indicates Intel)
Manufacturer ID
Manufacturer ID assigned by IEEE.
Table 30. 80960JA/JF Device ID Model Types
Device
Version
V
Product
Gen.
Model
Manufacturer ID
‘1’
CC
80960JA C0
80960JF C0
0011
0011
0
000100
000100
0001
0001
00001
00000
00000001001
00000001001
1
1
0
62
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
6.0
Thermal Specifications
The 80960Jx is specified for operation when TC (case temperature) is within the range of 0° C to
100° C for PGA, MPBGA and PQFP packages. Extended temperature devices are also available in
a PQFP package and an MPBGA package with TC = -40° C to 100° C. Case temperature may be
measured in any environment to determine whether the 80960Jx is within its specified operating
range. The case temperature should be measured at the center of the top surface, opposite the pins.
θCA is the thermal resistance from case to ambient. Use the following equation to calculate TA, the
maximum ambient temperature to conform to a particular case temperature:
TA = TC - P (θ
)
CA
Junction temperature (TJ) is commonly used in reliability calculations. TJ may be calculated from
θJC (thermal resistance from junction to case) using the following equation:
TJ = TC + P (θ
)
JC
Similarly, when TA is known, the corresponding case temperature (TC) may be calculated as
follows:
TC = TA + P (θ
)
CA
Compute P by multiplying ICC from Table 21, “80960Jx ICC Characteristics” on page 39 and VCC
See the following tables for θJC and θCA values:
.
Table 31. Thermal Resistance for θCA and θJC Reference Table
Package
Table
Table 33 on page 64
PGA package
MPBGA package
PQFP package
Table 34 on page 64 and Table 35 on page 65
Table 36 on page 65
For high speed operation, the processor’s θJA may be significantly reduced by adding a heatsink
and/or by increasing airflow.
Refer to the following tables for the maximum ambient temperature (TA) permitted without
exceeding TC for the PGA, MPBGA, and PQFP packages. The values are based on typical ICC and
CC of +3.3 V, with a TC of +100° C.
V
Table 32. Maximum Ambient Temperature Reference Table
Processor
Table
Table 37 on page 66
80960JT processor
80960JC processor
80960JD processor
80960JS processor
Table 38 on page 66
Table 39 on page 67
Table 40 on page 67
80960JA/JF processor Table 41 on page 68
Datasheet
63
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 33. 132-Lead PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.08)
θ
θ
θ
θ
(Junction-to-Case)
0.7
25
15
16
0.7
19
9
0.7
14
6
0.7
12
5
0.7
11
4
0.7
10
4
JC
(Case-to-Ambient) (No Heatsink)
CA
CA (Case-to-Ambient) (Omnidirectional Heatsink)
CA (Case-to-Ambient) (Unidirectional Heatsink)
8
6
5
4
4
θ
θ
CA
JA
θ
JC
θ
J-PIN
θ
J-CAP
NOTES:
1. This table applies to a PGA device plugged into a socket or soldered directly into a board.
2. θ = θ + θ
JA
JC
CA
3. θ
4. θ
5. θ
6. θ
7. θ
8. θ
= 5.6° C/W (approximate) (no heatsink)
J-CAP
J-PIN
J-PIN
J-CAP
J-PIN
J-PIN
= 6.4° C/W (inner pins) (approximate) (no heatsink)
= 6.2° C/W (outer pins) (approximate) (no heatsink)
= 3° C/W (approximate) (with heatsink)
= 3.3° C/W (inner pins) (approximate) (with heatsink)
= 3.3° C/W (outer pins) (approximate) (with heatsink)
Table 34. 80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.08)
θ
θ
(Junction-to-Case)
2
2
2
2
2
2
JC
(Case-to-Ambient) (No Heatsink)
30
22
20
19
18
18
CA
θ
JA
θ
CA
θ
JC
NOTES:
1. This table applies to an MPBGA device soldered directly into a board with all V connections.
SS
2. θ = θ + θ
JA
JC
CA
64
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 35. 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.08)
θ
θ
(Junction-to-Case)
2
2
2
2
2
2
JC
(Case-to-Ambient) (No Heatsink)
34
25
23
22
21
20
CA
θ
JA
θ
CA
θ
JC
NOTES:
1. This table applies to an MPBGA device soldered directly into a board with all V connections.
SS
2. θ = θ + θ
JA
JC
CA
Table 36. 132-Lead PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θ
θ
(Junction-to-Case)
4.1
23
4.3
19
4.3
18
4.3
16
4.3
14
4.7
11
4.9
9
JC
(Case-to-Ambient -No Heatsink)
CA
θ
CA
θ
JA
θ
JC
θ
JB
θ
JL
NOTES:
1. This table applies to a PQFP device soldered directly into board.
2. θ = θ + θ
JA
JC
CA
3. θ = 13° C/W (approx.)
JL
4. θ = 13.5° C/W (approx.)
JB
Datasheet
65
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 37. Maximum TA at Various Airflows in °C (80960JT)
Airflow-ft/min (m/sec)
f
0
200
400
600
800
1000
CLKIN
(MHz)
(0)
(1.01) (2.03) (3.04) (4.06) (5.07)
PQFP
Package
T
without Heatsink
33
63
74
78
82
86
87
A
T
without Heatsink
33
33
60
76
70
86
78
90
81
92
82
94
84
94
A
T
with Omnidirectional
A
PGA
Package
Heatsink1
T
with Unidirectional
A
33
33
74
46
87
60
90
63
92
65
94
66
94
68
Heatsink2
MPBGA
Package
T
without Heatsink
A
NOTES:
1. 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
spacing).
2. 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 38. Maximum TA at Various Airflows in °C (80960JC)
Airflow-ft/min (m/sec)
0
(0)
200
400
600
800
1000
f
(MHz)
CLKIN
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
20
75
79
84
86
82
86
89
90
85
87
90
92
88
90
92
93
90
92
94
95
91
93
94
95
PQFP
Package
T
without Heatsink
A
16.67
33
25
20
73
78
83
85
79
83
87
89
85
87
90
92
87
89
92
93
88
90
92
93
89
91
93
94
T
without Heatsink
A
16.67
33
25
20
84
87
90
91
90
92
94
95
93
95
96
96
95
96
97
97
96
96
97
98
96
96
97
98
PGA
T
with Omnidirectional
A
Package Heatsink1
16.67
33
25
20
82
86
89
90
91
93
94
95
93
95
96
96
95
96
97
97
96
96
97
98
96
96
97
98
T
with Unidirectional
A
Heatsink2
16.67
33
25
20
63
69
76
80
73
78
83
85
75
79
84
86
76
80
85
87
77
81
85
87
78
82
86
88
MPBGA
Package
T
without Heatsink
A
16.67
NOTES:
1. 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
spacing).
2. 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
66
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 39. Maximum TA at Various Airflows in °C (80960JD)
Airflow-ft/min (m/sec)
0
(0)
200
400
600
800
1000
f
(MHz)
CLKIN
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
20
61
70
75
79
73
79
82
86
76
82
85
87
81
86
88
90
85
88
90
92
86
90
91
93
PQFP
Package
T
without Heatsink
A
16.67
33
25
20
58
68
73
78
68
75
79
83
76
82
85
87
80
84
87
89
81
86
88
90
83
87
89
91
T
without Heatsink
A
16.67
33
25
20
75
81
84
87
85
88
90
92
90
92
93
95
92
94
95
96
93
95
96
96
93
95
96
96
PGA
T
with Omnidirectional
A
Package Heatsink1
16.67
33
25
20
73
79
82
86
86
90
91
93
90
92
93
95
92
94
95
96
93
95
96
96
93
96
96
96
T
with Unidirectional
A
Heatsink2
16.67
MPBGA
Package
T
without Heatsink
25
61
72
74
76
77
77
A
NOTES:
1. 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
spacing).
2. 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 40. Maximum TA at Various Airflows in °C (80960JS)
Airflow-ft/min (m/sec)
0
(0)
200
400
600
800
1000
f
(MHz)
CLKIN
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
16.67
84
86
91
89
90
94
90
92
94
92
93
96
94
95
96
94
95
97
PQFP
Package
T
without Heatsink
A
33
25
16.67
83
85
90
87
89
92
90
92
94
92
93
95
92
93
96
93
94
96
T
without Heatsink
A
33
25
16.67
90
91
94
94
95
96
96
96
98
97
97
98
97
98
98
97
98
98
PGA
T
with Omnidirectional
A
Package Heatsink1
33
25
16.67
89
90
94
94
95
97
96
96
98
97
97
98
97
98
98
97
98
98
T
with Unidirectional
A
Heatsink2
33
25
16.67
76
80
86
83
85
90
84
86
91
85
87
91
85
87
92
86
88
92
MPBGA
Package
T
without Heatsink
A
NOTES:
1. 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
spacing).
2. 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin
spacing).
Datasheet
67
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 41. Maximum TA at Various Airflows in °C (80960JA/JF)
Airflow-ft/min (m/sec)
0
(0)
200
400
600
800
1000
f
(MHz)
CLKIN
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
16
79
84
89
86
89
92
87
90
93
90
92
95
92
94
96
93
94
96
For x80960JA/JF
without Heatsink
T
A
PQFP
Package
For x80960JA-25
25
84
89
90
92
94
94
T
without Heatsink
A
33
25
16
78
83
88
83
87
91
87
90
93
89
92
94
90
92
95
91
93
95
T
without Heatsink
A
33
25
16
87
90
93
92
94
96
95
96
97
96
97
98
96
97
98
96
97
98
PGA
T
with Omnidirectional
A
Package Heatsink1
33
25
16
86
89
92
93
94
96
95
96
97
96
97
98
96
97
98
96
97
98
T
with Unidirectional
A
Heatsink2
MPBGA
Package
33
25
73
79
80
84
82
86
83
87
84
87
84
87
T
without Heatsink
A
NOTES:
1. 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
spacing).
2. 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin
spacing).
3. To address the fact that many of the package prefix variables have changed, all package prefix variables
in this document are now indicated with an "x".
6.1
Thermal Management Accessories
The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an
endorsement or a warranty of the performance of any of the listed products and/or companies.
6.1.1
Heatsinks
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(972) 243-4321
2. Wakefield Engineering
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
3. Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 528-3400
68
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
7.0
Bus Functional Waveforms
Figure 42 through Figure 47 illustrate typical 80960Jx bus transactions. Figure 48 depicts the bus
arbitration sequence. Figure 49 illustrates the processor reset sequence from the time power is
applied to the device. Figure 50 illustrates the processor reset sequence when the processor is in
operation. Figure 51 illustrates the processor ONCE# sequence from the time power is applied to
the device. Figure 53 and Figure 54 also show accesses on 32-bit buses. Table 44 through Table 46
summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to
data alignment.
Figure 42. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
T
T
T
T
T
T
T
T
T
T
i
a
d
r
i
i
a
d
r
i
CLKIN
D
ADDR
ADDR
Invalid
DATA Out
AD31:0
In
ALE
ADS#
A3:2
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF030A
Datasheet
69
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 43. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
TA
TD
TD
TR
TA
TD
TD
TD TD
TR
CLKIN
D
In
DATA
Out
DATA
Out
D
DATA DATA
ADDR
ADDR
AD31:0
In
Out Out
ALE
ADS#
00 or 10
01 or 11
00
01
10
11
A3:2
BE3:0#
1 0
WIDTH1:0
D/C#
1 0
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
70
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 44. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
TA
TW
TW
TD
TW
TD
TW
TD
TW
TD
TR
CLKIN
AD31:0
ALE
DATA
Out
DATA
Out
DATA
Out
DATA
Out
ADDR
ADS#
A3:2
0 0
0 1
1 0
1 1
BE3:0#
WIDTH1:0
D/C#
1 0
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF032A
Datasheet
71
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 45. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
TA
TD
TD
TR
TA
TD
TD
TD
TD
TR
CLKIN
DATA
Out
D
In
D
In
DATA DATA
DATA
ADDR
ADDR
AD31:0
Out Out Out
ALE
ADS#
A3:2
00,01,10 or 11
00,01,10 or 11
01 or
BE1#/A1
BE0#/A0
00
01
10
11
00 or 10
11
WIDTH1:0
D/C#
00
00
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF033A
72
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 46. Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus
TW TD
TD
TR
TR
TA
TW
TD TD
TR
TA
CLKIN
AD31:0
ALE
D
D
DATA
DATA
Out
ADDR
ADDR
In
In
Out
ADS#
00,01,10, or 11
00,01,10, or 11
A3:2
0
0
1
BE1#/A1
1
BE3#/BHE
BE0#/BLE
01
01
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
F_JF034A
RDYRCV#
Datasheet
73
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 47. Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian
TA
TD
TR
TA
TD
TR
TA
TD
TR
TA
TD
TR
CLKIN
AD31:0
ALE
D
In
D
In
D
In
D
In
A
A
A
A
ADS#
A3:2
00
00
01
10
BE3:0#
WIDTH1:0
D/C#
0 0 0 0
1 1 1 0
0 0 1 1
1 1 0 1
1 0
Valid
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
74
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 48. HOLD/HOLDA Waveform For Bus Arbitration
TI or TR
TH
TH
TI or TA
CLKIN
Outputs:
AD31:0,
ALE, ALE#,
ADS#, A3:2,
BE3:0#,
Valid
Valid
WIDTH/HLTD1:0,
D/C#, W/R#,
DT/R#, DEN#,
BLAST#, LOCK#
HOLD
HOLDA
(Note)
NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the
same edge in which it recognizes HOLD when the last state was Ti or the last Tr of a bus transaction. Similarly,
the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Datasheet
75
CLKIN
VCC
ALE#, ADS#,
BE3:0#, DEN#,
BLAST#
ALE#,W/R#,DT/R#
WIDTH/HLTD1:0
(Note 1)
FAIL#
Idle (Note 2)
AD31:0, A3:2,D/C#
Valid Input (Note 3)
Valid Output (Note 3)
HOLD
HOLDA
LOCK#/
ONCE#
(Output)
(Input)
Valid
STEST
RESET#
First
Built-in self-test (Note 4)
V
CC and CLKIN stable to RESET High, minimum
10,000 CLKIN periods, for PLL stabilization.
Bus
Activity
Notes:
1. The processor asserts FAIL# during built-in self-test. When self- test passes, the FAIL# pin is deasserted.The processor also asserts FAIL#
during the bus confidence test. When the bus confidence test passes, FAIL# is deasserted and the processor begins user program execution.
2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
3. Since the bus is idle, hold requests are honored during reset and built-in self-test.
4. When selected, built-in self test requires approximately (in CLKIN periods): 393,000 for 80960JT, 580,012 for the 80960JC,
1,176,025 for the 80960JS, 207,000 for 80960JD, and 414,000 for 80960JA/JF.
CLKIN
ALE#, ADS#, BE3:0#,
DEN#, BLAST#
ALE, W/R#,DT/R#, BSTAT,
WIDTH/HLTD1:0
FAIL#
AD31:0, A3:2, D/C#
HOLD
HOLDA
LOCK#/ONCE#
STEST
Valid
Maximum RESET# Low to Reset State
4 CLKIN Cycles
RESET#
RESET# High to First Bus
Activity: (CLKIN cycles)
Minimum RESET# Low Time
15 CLKIN Cycles
80960JT - 26
80960JC - 40
80960JS - 60
80960JD - 46
80960JA/JF - 92
CLKIN may not be allowed to float.
It must be driven high or low or continue to run.
CLKIN
VCC
ALE#, ADS#,
BE3:0#, DEN#, BLAST#
ALE,W/R,#
DT/R#, WIDTH/HLTD1:0
FAIL#
AD31:0, A3:2,
D/C#
HOLD
HOLDA
(Input)
LOCK#/
ONCE#
STEST
RESET#
(Note 1)
VCC and CLKIN stable to RESET# High,
minimum 10,000 CLKIN periods, for PLL
stabilization.
NOTES:
1. ONCE# mode may be entered prior to the rising edge of RESET#: ONCE# input is not latched until the rising edge of RESET#.
2. The ONCE# input may be removed after the processor enters ONCE# Mode.
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
7.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
Figure 52 shows the five bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when
RESET# is asserted. When the processor needs to initiate a bus access, it enters the Ta state to
transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV# input signal indicates completion of each transfer. When data is
not ready, the processor may wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case
of a burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next
data word. The processor asserts the BLAST# signal during the last Tw/Td states of an access.
Once all data words transfer in a burst access (up to four), the bus enters the Tr state to allow
devices on the bus to recover.
The processor remains in the Tr state until RDYRCV# is deasserted. When the recovery state
completes, the bus enters the Ti state when no new accesses are required. When an access is
pending, the bus enters the Ta state to transmit the new address.
Datasheet
79
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 52. Bus States with Arbitration
(READY AND BURST)
OR NOT READY
Tw/Td
RECOVERED AND
REQUEST
PENDING AND (NO
HOLD OR LOCKED)
READY AND NO BURST
Ta
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NOT
RECOVERED
Tr
RECOVERED AND
NO REQUEST AND
(NO HOLD OR
LOCKED)
REQUEST
PENDING AND
NO HOLD
NO REQUEST
AND (NO HOLD
OR LOCKED)
Ti
ONCE & RESET
DEASSERTION
RECOVERED AND
HOLD AND NOT
LOCKED
NO REQUEST
AND NO HOLD
Th
RESET
To
HOLD AND
NOT LOCKED
HOLD
Ti — IDLE STATE
READY — RDYRCV# ASSERTED
Ta — ADDRESS STATE
NOT READY — RDYRCV# NOT ASSERTED
BURST — BLAST# NOT ASSERTED
NO BURST — BLAST# ASSERTED
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
RECOVERED — RDYRCV# NOT ASSERTED
NOT RECOVERED — RDYRCV# ASSERTED
REQUEST PENDING — NEW TRANSACTION
NOREQUEST — NO NEW TRANSACTION
HOLD — HOLD REQUEST ASSERTED
To — ONCE STATE
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RESET — RESET# ASSERTED
ONCE — ONCE# ASSERTED
7.2
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and
HIGHZ pins.
Table 42 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain ‘CTL’ select the direction of bidirectional pins or HIGHZ output pins. When a 1 is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
80
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 42. Boundary-Scan Register—Bit Order
Input/
Output
Input/
Output
Input/
Output
Bit
Signal
Bit
Signal
DEN#
Bit
Signal
AD17
RDYRCV#
(TDI)
0
I
24
O
48
I/O
1
2
HOLD
I
I
25
26
HOLDA
ALE
O
O
49
50
AD16
AD15
I/O
I/O
XINT0#
LOCK#/
ONCE# cell
3
XINT1#
I
27
Enable cell†
51
AD14
I/O
LOCK#/
ONCE#
4
5
6
XINT2#
XINT3#
XINT4#
I
I
I
28
29
30
I/O
O
52
53
54
AD13
AD12
I/O
I/O
BSTAT
BE0#
Enable
cell†
O
AD cells
7
XINT5#
XINT6#
I
31
32
33
34
35
36
37
38
39
40
41
42
43
44
BE1#
BE2#
BE3#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
O
55
56
57
58
59
60
61
62
63
64
65
66
67
68
AD11
AD10
AD9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
8
I
O
9
XINT7#
I
O
10
11
12
13
14
15
16
17
18
19
20
NMI#
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD8
FAIL#
I
AD7
ALE#
O
AD6
WIDTH/HLTD1
WIDTH/HLTD0
A2
O
AD5
O
AD4
O
AD3
A3
O
AD2
CONTROL1
CONTROL2
BLAST#
D/C#
Enable cell†
AD1
Enable cell†
AD0
O
O
CLKIN
RESET#
I
STEST
(TDO)
21
ADS#
O
45
AD20
I/O
69
I
22
23
W/R#
O
O
46
47
AD19
AD18
I/O
I/O
DT/R#
†
Enable cells are active low.
Table 43. Natural Boundaries for Load and Store Accesses
Data Width
Natural Boundary (Bytes)
Byte
1
2
Short Word
Word
4
Double Word
Triple Word
Quad Word
8
16
16
Datasheet
81
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 44. Summary of Byte Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit
Bus (WIDTH1:0=01)
Accesses on 32 Bit Bus
(WIDTH1:0=10)
+0 (aligned)
Byte access
Byte access
Byte access
Table 45. Summary of Short Word Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit
Bus (WIDTH1:0=01)
Accesses on 32 Bit Bus
(WIDTH1:0=10)
+0 (aligned)
+1
Burst of 2 bytes
Short-word access
Two byte accesses
Short-word access
Two byte accesses
Two byte accesses
82
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Table 46. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
Address Offset
from Natural
Boundary in Bytes
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit Bus
(WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
•
•
•
Case n=1:
burst of 2 short words
Case n=2:
burst of 4 short words
+0 (aligned)
(n =1, 2, 3, 4)
•
n burst(s) of 4 bytes
•
Burst of n word(s)
Case n=3:
burst of 4 short words
burst of 2 short words
•
Case n=4:
2 bursts of 4 short words
•
•
•
Byte access
•
•
•
Byte access
•
•
•
•
Byte access
+1 (n =1, 2, 3, 4)
+5 (n = 2, 3, 4)
+9 (n = 3, 4)
Short-word access
Short-word access
Burst of 2 bytes
n-1 burst(s) of 4 bytes
Byte access
n-1 burst(s) of 2 short
words
n-1 word
access(es)
+13 (n = 3, 4)
•
Byte access
•
Byte access
•
•
Short-word access
•
•
Short-word access
+2 (n =1, 2, 3, 4)
+6 (n = 2, 3, 4)
+10 (n = 3, 4)
+14 (n = 3, 4)
•
•
•
Burst of 2 bytes
n-1 burst(s) of 2 short
words
n-1 word
access(es)
n-1 burst(s) of 4 bytes
Burst of 2 bytes
•
Short-word access
Byte access
•
Short-word access
Byte access
•
•
•
•
•
•
•
•
Byte access
+3 (n =1, 2, 3, 4)
+7 (n = 2, 3, 4)
+11 (n = 3, 4)
+15 (n = 3, 4)
n-1 burst(s) of 2 short
words
n-1 word
access(es)
n-1 burst(s) of 4 bytes
Burst of 2 bytes
Byte access
•
•
Short-word access
Byte access
•
•
Short-word access
Byte access
+4 (n = 2, 3, 4)
+8 (n = 3, 4)
•
n burst(s) of 4 bytes
•
n burst(s) of 2 short words
•
n word access(es)
+12 (n = 3, 4)
Datasheet
83
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 53. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
0
0
4
8
12
3
16
4
20
5
24
6
Byte Offset
Word Offset
1
2
Short Access (Aligned)
Byte, Byte Accesses
Short-Word
Load/Store
Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned)
Byte, Short, Byte, Accesses
Short, Short Accesses
Word
Load/Store
Byte, Short, Byte Accesses
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Accesses
Short, Word, Short Accesses
Double-Word
Load/Store
Byte, Word, Short, Byte Accesses
Word, Word Accesses
One Double-Word
Burst (Aligned)
84
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Figure 54. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
0
4
1
8
2
12
3
16
4
20
5
24
6
Byte Offset
Word Offset
0
One Three-Word
Burst (Aligned)
Byte, Short, Word,
Word, Byte Accesses
Short, Word, Word,
Short Accesses
Triple-Word
Load/Store
Byte, Word, Word,
Short, Byte Accesses
Word, Word,
Word Accesses
Word, Word,
Word Accesses
Word,
Word,
Word
Accesses
One Four-Word
Burst (Aligned)
Byte, Short, Word, Word,
Word, Byte Accesses
Short, Word, Word, Word,
Short Accesses
Quad-Word
Load/Store
Byte, Word, Word, Word,
Short, Byte Accesses
Word, Word, Word,
Word Accesses
Word,
Word,
Word,
Word,
Accesses
Datasheet
85
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
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Datasheet
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