GT28F016B3B120_技术文档

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK

BYTE-WIDE

8-MBIT (1024K x 8), 16-MBIT (2056K x 8)

FLASH MEMORY FAMILY

28F008B3, 28F016B3

Flexible SmartVoltage Technology

2.7V–3.6V Program/Erase

Extended Cycling Capability

10,000 Block Erase Cycles

2.7V–3.6V Read Operation

12V V_PPFast Production

Programming

Automated Byte Program and Block

Erase

Command User Interface

Status Registers

2.7V or 1.8V I/O Option

Reduces Overall System Power

SRAM-Compatible Write Interface

Automatic Power Savings Feature

Optimized Block Sizes

Eight 8-Kbyte Blocks for Data,

Top or Bottom Locations

Up to Thirty-One 64-Kbyte Blocks

for Code

Reset/Deep Power-Down

1 µA I_CCTypical

Spurious Write Lockout

Standard Surface Mount Packaging

48-Ball µBGA* Package

High Performance

2.7V–3.6V: 120 ns Max Access Time

40-Lead TSOP Package

Block Locking

Footprint Upgradeable

Upgradeable from 2-, 4- and 8-Mbit

Boot Block

V_CC-Level Control through WP#

Low Power Consumption

20 mA Maximum Read Current

ETOX™ V (0.4 µ) Flash Technology

Absolute Hardware-Protection

V_PP= GND Option

x8-Only Input/Output Architecture

For Space-Constrained 8-bit

Applications

V_CCLockout Voltage

Extended Temperature Operation

–40°C to +85°C

Supports Code plus Data Storage

Optimized for FDI, Flash Data

Integrator Software

Fast Program Suspend Capability

Fast Erase Suspend Capability

The new Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.4µ technology, represents a feature-

rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability

(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been

added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and

interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device.

Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective,

monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Byte-Wide

products will be available in 40-lead TSOP and 48-ball µBGA* packages. Additional information on this

product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp

May 1997

Order Number: 290605-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F008B3 and 28F016B3 may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

*Third-party brands and names are the property of their respective owners.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

CG-041493

*Third-party brands and names are the property of their respective owners.

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

CONTENTS

PAGE

3.5 Power Consumption...................................26

3.5.1 Active Power .......................................26

3.5.2 Automatic Power Savings (APS) .........27

3.5.3 Standby Power ....................................27

3.5.4 Deep Power-Down Mode.....................27

3.6 Power-Up/Down Operation.........................27

3.6.1 RP# Connected to System Reset ........27

3.6.2 V_CC, V_PPand RP# Transitions .............27

3.7 Power Supply Decoupling ..........................28

3.7.1 V_PPTrace on Printed Circuit Boards....28

1.0 INTRODUCTION .............................................5

1.1 Smart 3 Advanced Boot Block Flash

Memory Enhancements ..............................5

1.2 Product Overview.........................................6

2.0 PRODUCT DESCRIPTION..............................6

2.1 Package Pinouts ..........................................7

2.2 Block Organization.....................................11

2.2.1 Parameter Blocks................................11

2.2.2 Main Blocks.........................................11

3.0 PRINCIPLES OF OPERATION .....................14

3.1 Bus Operation............................................14

3.1.1 Read....................................................15

3.1.2 Output Disable.....................................15

3.1.3 Standby...............................................15

3.1.4 Deep Power-Down/Reset ....................15

3.1.5 Write....................................................15

3.2 Modes of Operation....................................15

3.2.1 Read Array..........................................16

3.2.2 Read Intelligent Identifier.....................17

3.2.3 Read Status Register ..........................17

3.2.4 Program Mode.....................................18

3.2.5 Erase Mode.........................................19

3.3 Block Locking.............................................26

3.3.1 V_PP= V_ILfor Complete Protection .......26

3.3.2 WP# = V_ILfor Block Locking................26

3.3.3 WP# = V_IHfor Block Unlocking............26

3.4 V_PPProgram and Erase Voltages ..............26

4.0 ABSOLUTE MAXIMUM RATINGS................29

5.0 OPERATING CONDITIONS

(V_CCQ= 2.7V–3.6V).......................................29

5.1 DC Characteristics: V_CCQ= 2.7V–3.6V.......30

6.0 OPERATING CONDITIONS

(V_CCQ= 1.8V–2.2V).......................................34

6.1 DC Characteristics: V_CCQ= 1.8V–2.2V.......34

7.0 AC CHARACTERISTICS...............................39

7.1 Reset Operations .......................................43

APPENDIX A: Ordering Information .................45

APPENDIX B: Write State Machine Current/

Next States ..................................................46

APPENDIX C: Access Time vs.

Capacitive Load...........................................47

APPENDIX D: Architecture Block Diagram ......48

APPENDIX E: Additional Information ...............49

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REVISION HISTORY

Number

Description

-001

Original version

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

1.0 INTRODUCTION

1.1

Smart 3 Advanced Boot Block

Flash Memory Enhancements

This

preliminary

datasheet

contains

the

specifications for the Advanced Boot Block flash

memory family, which is optimized for low power,

portable systems. This family of products features

1.8V–2.2V or 2.V–3.6V I/Os and a low V_CC/V_PP

operating range of 2.7V–3.6V for read and

program/erase operations. In addition this family is

capable of fast programming at 12V. Throughout

this document, the term “2.7V” refers to the full

voltage range 2.7V–3.6V (except where noted

otherwise) and “V_PP= 12V” refers to 12V ±5%.

Section 1 and 2 provides an overview of the flash

memory family including applications, pinouts and

pin descriptions. Section 3 describes the memory

organization and operation for these products.

The new 8-Mbit and 16-Mbit Smart 3 Advanced

Boot Block flash memory provides a convenient

upgrade from and/or compatibility to previous 4-

Mbit and 8-Mbit Boot Block products. The Smart 3

product functions are similar to lower density

products in both command sets and operation,

providing similar pinouts to ease density upgrades.

The Smart 3 Advanced Boot Block flash memory

features

•

Enhanced blocking for easy segmentation of

code and data or additional design flexibility

Program Suspend command which permits

program suspend to read

Finally, Sections 4, 5,

operating specifications.

6 and 7 contain the

WP# pin to lock and unlock the upper two (or

lower two, depending on location) 8-Kbyte

blocks

•

V_CCQinput for 1.8V–2.2V on all I/Os. See

Figures 1–3 for pinout diagrams and V^CCQ

location

Maximum program time specification for

improved data storage.

Table 1. Smart 3 Advanced Boot Block Feature Summary

28F016B3/28F008B3/28F004B3

Feature

V_CCRead Voltage

V_CCQI/O Voltage

V_PPProgram/Erase Voltage

Bus Width

Reference

2.7V– 3.6V

Table 9, Table 12

Table 2

1.8V–2.2V or 2.7V– 3.6V

2.7V– 3.6V or 11.4V– 12.6V

8 bits

Speed

120 ns

Table 15

Memory Arrangement

Blocking (top or bottom)

1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)

Eight 8-Kbyte parameter blocks (8/16 Mbit) &

Fifteen 64-Kbyte blocks (8 Mbit)

Section 2.2

Figures 4 and 5

Thirty-one 64-Kbyte main blocks (16 Mbit)

Locking

WP# locks/unlocks parameter blocks

All other blocks protected using V_PPswitch

Section 3.3

Table 8

Operating Temperature

Program/Erase Cycling

Packages

Extended: –40°C to +85°C

10,000 cycles

Table 9, Table 12

Figures 1, 2, and 3

40-Lead TSOP, 48-Ball µBGA* CSP

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Program and erase automation allows program and

erase operations to be executed using an industry-

standard two-write command sequence to the CUI.

Data writes are performed in byte increments. Each

byte in the flash memory can be programmed

independently of other memory locations; every

erase operation erases all locations within a block

simultaneously. Program suspend allows system

software to suspend the program command in order

to read from any other block. Erase suspend allows

system software to suspend the block erase

command in order to read from or program data to

any other block.

1.2

Product Overview

Intel provides the most flexible voltage solution in

the flash industry, providing three discrete voltage

supply pins: V_CCfor read operation, V_CCQfor output

swing, and V_PPfor program and erase operation.

Discrete supply pins allow system designers to use

the optimal voltage levels for their design. All Smart

3 Advanced Boot Block flash memory products

provide program/erase capability at 2.7V or 12V

and read with V_CCat 2.7V. Since many designs

read from the flash memory a large percentage of

the time, 2.7V V_CCoperation can provide

substantial power savings. The 12V V_PPoption

maximizes program and erase performance during

production programming.

The Smart 3 Advanced Boot Block flash memory is

also designed with an Automatic Power Savings

(APS) feature which minimizes system current

drain, allowing for very low power designs. This

mode is entered immediately following the

completion of a read cycle.

The Smart 3 Advanced Boot Block flash memory

products are high-performance devices with low

power operation. The available densities for the

byte-wide devices (x8) are

When the CE# and RP# pins are at V_CC, the I_CC

CMOS standby mode is enabled. A deep power-

down mode is enabled when the RP# pin is at

GND, minimizing power consumption and providing

write protection. I_CCcurrent in deep power-down is

1 µA typical (2.7V V_CC). A minimum reset time of

t_PHQVis required from RP# switching high until

outputs are valid to read attempts. With RP# at

GND, the WSM is reset and Status Register is

cleared. Section 3.5 contains additional information

on using the deep power-down feature, along with

other power consumption issues.

a. 8-Mbit (8,388,608-bit)

flash

memory

organized as 1 Mbyte of 8 bits each

b. 16-Mbit (16,777,216-bit) flash memory

organized as 2 Mbytes of 8 bits each.

For word-wide devices (x16) see the Smart 3

Advanced Boot Block Word-Wide Flash Memory

Family datasheet.

The parameter blocks are located at either the top

(denoted by -T suffix) or the bottom (-B suffix) of the

address map in order to accommodate different

microprocessor protocols for kernel code location.

The upper two (or lower two) parameter blocks can

be locked to provide complete code security for

system initialization code. Locking and unlocking is

controlled by WP# (see Section 3.3 for details).

The RP# pin provides additional protection against

unwanted command writes that may occur during

system reset and power-up/down sequences due to

invalid system bus conditions (see Section 3.6).

Refer to the DC Characteristics Table, Sections 5.1

and 6.1, for complete current and voltage

specifications. Refer to the AC Characteristics

Table, Section 7.0, for read, program and erase

performance specifications.

The Command User Interface (CUI) serves as the

interface

between

the

microprocessor

or

microcontroller and the internal operation of the

flash memory. The internal Write State Machine

(WSM) automatically executes the algorithms and

timings necessary for program and erase

operations, including verification, thereby un-

burdening the microprocessor or microcontroller.

The status register indicates the status of the WSM

by signifying block erase or byte program

completion and status.

2.0 PRODUCT DESCRIPTION

This section explains device pin description and

package pinouts.

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

2.1

Package Pinouts

The Smart 3 Advanced Boot Block flash memory is

available in 40-lead TSOP (see Figure 1) and 48-

ball µBGA packages (see Figures 2 and 3). In

Figure 1, pin changes from one density to the next

are circled. Both packages, 40-lead TSOP and 48-

ball µBGA package, are 8-bits wide and fully

upgradeable across product densities (from 8 Mb to

16 Mb).

28F016 28F008

28F008 28F016

A₁₆

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₉

A₁₆

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₉

A₁₇

GND

A₂₀

A₁₉

A₁₀

DQ₇

DQ₆

DQ₅

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

GND

NC

A₁₉

A₁₀

DQ₇

DQ₆

DQ₅

DQ₄

V_CCQ

V_CC

NC

DQ₃

DQ₂

DQ₁

DQ₀

OE#

GND

A₈

WE#

RP#

V_PP

WE#

RP#

V_PP

DQ₄

V_CCQ

V_CC

Advanced Boot Block

40-Lead TSOP

10 mm x 20 mm

NC

WP#

DQ₃

DQ₂

DQ₁

DQ₀

OE#

GND

A₁₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₁₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

TOP VIEW

CE#

A₀

CE#

A₀

0605-01

Figure 1. 40-Lead TSOP Package

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1

2

3

4

5

WP#

A₁₉

6

7

A₇

8

A₄

A

B

A₁₄

A₁₂

A₈

V_PP

RP#

NC

A₁₈

A₆

A₁₅

A₁₀

A₁₃

NC

A₁₁

D₇

WE#

A₉

A₅

A₂

C

A₁₆

A₃

A₁

D

E

A₁₇

D₅

NC

D₄

D₂

D₃

NC

CE#

D₀

D₁

A₀

V_CCQ

GND

D₆

GND

OE#

F

NC

V_CC

0605-03

NOTE:

Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.

Routing is not recommended in this area.

Figure 2. 8-Mbit 48-Ball µBGA* Chip Size Package

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

1

2

3

4

5

WP#

A₁₉

6

7

A₇

8

A₄

A

B

A₁₄

A₁₂

A₈

V_PP

RP#

A₂₀

A₁₈

A₆

A₁₅

A₁₀

A₁₃

NC

A₁₁

D₇

WE#

A₉

A₅

A₂

C

A₁₆

A₃

A₁

D

E

A₁₇

D₅

NC

D₄

D₂

D₃

NC

CE#

D₀

D₁

A₀

V_CCQ

GND

D₆

GND

OE#

F

NC

V_CC

0605-02

NOTE:

Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.

Routing is not recommended in this area.

Figure 3. 16-Mbit 48-Ball µBGA* Chip Size Package

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

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The pin descriptions table details the usage of each device pin.

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions

Symbol

Type

Name and Function

ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a program or erase cycle.

A₀–A₂₀

INPUT

28F008B3: A[0-19], 28F016B3: A[0-20]

DQ₀–DQ₇

INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

WE# cycle during a Program command. Inputs commands to the

Command User Interface when CE# and WE# are active. Data is

internally latched. Outputs array, Intelligent Identifier and Status Register

data. The data pins float to tri-state when the chip is de-selected or the

outputs are disabled.

CE#

INPUT

CHIP ENABLE: Activates the internal control logic, input buffers,

decoders and sense amplifiers. CE# is active low. CE# high de-selects

the memory device and reduces power consumption to standby levels. If

CE# and RP# are high, but not at a CMOS high level, the standby

current will increase due to current flow through the CE# and RP# inputs.

OE#

WE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through the data

buffers during an array or status register read. OE# is active low.

WRITE ENABLE: Controls writes to the Command Register and memory

array. WE# is active low. Addresses and data are latched on the rising

edge of the second WE# pulse.

RP#

INPUT

RESET/DEEP POWER-DOWN: Uses two voltage levels (V_IL, V_IH) to

control reset/deep power-down mode.

When RP# is at logic low, the device is in reset/deep power-down

mode, which drives the outputs to High-Z, resets the Write State

Machine, and draws minimum current.

When RP# is at logic high, the device is in standard operation.

When RP# transitions from logic-low to logic-high, the device defaults to

the read array mode.

WP#

INPUT

WRITE PROTECT: Provides a method for locking and unlocking the two

lockable parameter blocks.

When WP# is at logic low, the lockable blocks are locked,

preventing program and erase operations to those blocks. If a program

or erase operation is attempted on a locked block, SR.1 and either SR.4

[program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and

can be programmed or erased.

See Section 3.3 for details on write protection.

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)

Symbol

Type

Name and Function

VCCQ

INPUT

OUTPUT V_CC: Enables all outputs to be driven to 2.0V ±10% while the

_CCis at 2.7V. When this mode is used, the V_CCshould be regulated to

2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC

Characteristics: V_CCQ= 1.8V–2.2V).

V

This input may be tied directly to V_CC(2.7V–3.6V).

See the DC Characteristics for further details.

DEVICE POWER SUPPLY: 2.7V–3.6V

V_CC

V_PP

PROGRAM/ERASE POWER SUPPLY: For erasing memory array

blocks or programming data in each block, a voltage of either 2.7V–3.6V

or 12V ± 5% must be applied to this pin. When V_PP< V_PPLKall blocks

are locked and protected against Program and Erase commands.

Applying 11.4V–12.6V to V_PPcan only be done for a maximum of 1000

cycles on the main blocks and 2500 cycles on the parameter blocks.

V

_PPmay be connected to 12V for a total of 80 hours maximum (see

Section 3.4 for details).

GND

NC

GROUND: For all internal circuitry. All ground inputs must be

connected.

NO CONNECT: Pin may be driven or left floating.

2.2.1

PARAMETER BLOCKS

2.2

Block Organization

The Smart 3 Advanced Boot Block flash memory

architecture includes parameter blocks to facilitate

storage of frequently updated small parameters

(e.g., data that would normally be stored in an

EEPROM. By using software techniques, the byte-

rewrite functionality of EEPROMs can be emulated.

Each 8-/16-Mbit device contains eight parameter

blocks of 8 Kbytes (8,192-bytes) each.

The Smart

3

Advanced Boot Block is an

asymmetrically-blocked architecture that enables

system integration of code and data within a single

flash device. Each block can be erased

independently of the others up to 10,000 times. For

the address locations of each block, see the

memory maps in Figure 4 (top boot blocking) and

Figure 5 (bottom boot blocking).

2.2.2

MAIN BLOCKS

After the parameter blocks, the remainder of the

array is divided into equal size main blocks for data

or code storage. Each 16-Mbit device contains

thirty-one 64-Kbyte (65,536-byte) blocks. Each

8-Mbit device contains fifteen 64-Kbyte blocks.

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16-Mbit Advanced Boot

Block

8-Mbit Advanced Boot

Block

1FFFFF

FFFFF

8-Kbyte Block

38

37

22

21

1FE000

FE000

1FDFFF

1FC000

1FBFFF

FDFFF

FC000

FBFFF

8-Kbyte Block

64-Kbyte Block

8-Kbyte Block

64-Kbyte Block

36

35

34

33

32

31

30

20

19

18

17

16

15

14

1FA000

1F9FFF

1F8000

1F7FFF

FA000

F9FFF

F8000

F7FFF

1F6000

1F5FFF

F6000

F5FFF

1F4000

1F3FFF

F4000

F3FFF

1F2000

1F1FFF

1F0000

1EFFFF

F2000

F1FFF

F0000

EFFFF

1E0000

1DFFFF

E0000

DFFFF

64-Kbyte Block

29

28

27

26

13

12

11

10

9

1D0000

1CFFFF

1C0000

1BFFFF

D0000

CFFFF

C0000

BFFFF

1B0000

1AFFFF

B0000

AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

A0000

9FFFF

25

24

90000

8FFFF

8

80000

7FFFF

23

22

7

170000

16FFFF

70000

6FFFF

6

5

4

3

2

10

160000

15FFFF

60000

5FFFF

21

20

19

18

17

16

50000

4FFFF

150000

14FFFF

40000

3FFFF

140000

13FFFF

130000

12FFFF

30000

2FFFF

120000

11FFFF

20000

1FFFF

10000

0FFFF

110000

10FFFF

00000

0

100000

0FFFFF

15

14

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

64-Kbyte Block

13

12

0C0000

0BFFFF

64-Kbyte Block

11

10

9

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

8

080000

07FFFF

7

070000

06FFFF

6

5

4

3

2

10

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

0

000000

0605-05

Figure 4. 8-/16-Mbit Advanced Boot Block Byte-Wide Top Boot Memory Maps

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

16-Mbit Advanced Boot

Block

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

64-Kbyte Block

38

37

64-Kbyte Block

36

35

34

33

32

31

30

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

64-Kbyte Block

29

28

27

26

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

25

24

23

22

100000

0FFFFF

8-Mbit Advanced Boot

Block

0F0000

0EFFFF

FFFFF

64-Kbyte Block

22

21

20

19

18

17

16

F0000

0E0000

0DFFFF

EFFFF

E0000

DFFFF

0D0000

0CFFFF

20

19

18

17

16

15

14

D0000

CFFFF

C0000

BFFFF

0C0000

0BFFFF

64-Kbyte Block

0B0000

0AFFFF

B0000

AFFFF

0A0000

09FFFF

A0000

9FFFF

090000

08FFFF

90000

8FFFF

80000

7FFFF

15

14

080000

07FFFF

070000

06FFFF

70000

6FFFF

64-Kbyte Block

13

12

64-Kbyte Block

8-Kbyte Block

060000

05FFFF

13

12

11

10

9

60000

5FFFF

050000

04FFFF

50000

4FFFF

64-Kbyte Block

8-Kbyte Block

11

10

9

040000

03FFFF

40000

3FFFF

030000

02FFFF

30000

2FFFF

020000

01FFFF

20000

1FFFF

8

010000

00FFFF

8

10000

0FFFF

7

00E000

00DFFF

7

0E000

0DFFF

6

5

4

3

2

10

00C000

00BFFF

00A000

009FFF

6

5

4

3

2

10

0C000

0BFFF

0A000

09FFF

008000

007FFF

08000

07FFF

006000

005FFF

06000

05FFF

004000

003FFF

002000

001FFF

04000

03FFF

02000

01FFF

0

000000

00000

0

0605-06

Figure 5. 8-/16-Mbit Advanced Boot Block Byte-Wide Bottom Boot Memory Maps

13

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

associated with altering memory contents, namely

program and erase, are accessible via the CUI.

The internal Write State Machine (WSM) completely

automates program and erase operations while the

CUI signals the start of an operation and the status

register reports status. The CUI handles the WE#

interface to the data and address latches, as well

as system status requests during WSM operation.

3.0 PRINCIPLES OF OPERATION

Flash memory combines EEPROM functionality

with in-circuit electrical program and erase

capability. The Smart 3 Advanced Boot Block flash

memory family utilizes a Command User Interface

(CUI) and automated algorithms to simplify program

and erase operations. The CUI allows for 100%

CMOS-level control inputs, fixed power supplies

during erasure and programming, and maximum

EEPROM compatibility.

3.1

Bus Operation

When V_PP< V_PPLK, the device will only execute the

following commands successfully: Read Array,

Read Status Register, Clear Status Register and

Read Intelligent Identifier. The device provides

standard EEPROM read, standby and output

disable operations. Manufacturer identification and

device identification data can be accessed through

the CUI. In addition, 2.7V or 12V on V_PPallows

program and erase of the device. All functions

Smart

3

Advanced Boot Block flash memory

devices read, program and erase in-system via the

local CPU or microcontroller. All bus cycles to or

from the flash memory conform to standard

microcontroller bus cycles. Four control pins dictate

the data flow in and out of the flash component:

CE#, OE#, WE# and RP#. These bus operations

are summarized in Table 3.

Table 3. Bus Operations for Byte-Wide Mode

Mode

Notes RP#

CE#

V_IL

V_IH

X

OE#

V_IL

V_IH

X

WE#

V_IH

X

WP#

X

A₀

X

V_PP

X

DQ_0–7

D_OUT

Read

1,2,3

2

V_IH

V_IL

V_IH

Output Disable

Standby

X

High Z

89 H

2

X

Deep Power-Down

Intelligent Identifier (Mfr.)

Intelligent Identifier (Dvc.)

Write

2,9

2,4

2,4,5

X

V_IL

V_IH

V_IL

X

V_IL

V_IH

X

See Table 5

D_IN

2,6,7,

8

X

V_PPH

NOTES:

1. Refer to DC Characteristics.

2. X must be V_IL, V_IHfor control pins and addresses, V_PPLK, V_PPH1or V_PPH2for V_PP

.

3. See DC Characteristics for V_PPLK, V_PPH1, V_PPH2voltages.

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A₁–A₂₀= X

5. See Table 5 for device IDs.

6. Refer to Table 6 for valid D_INduring a write operation.

7. Command writes for block erase or byte program are only executed when V_PP= V_PPH1or V_PPH2

.

8. To program or erase the lockable blocks, hold WP# at V . See Section 3.3.

IH

9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.

14

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

3.1.1

READ

valid. A delay (t_PHWLor t_PHEL) is required after

return from power-down before a write sequence

can be initiated. After this wake-up interval, normal

operation is restored. The CUI resets to read array

mode, and the status register is set to 80H (ready).

The flash memory has three read modes available:

read array, read identifier, and read status. These

modes are accessible independent of the V_PP

voltage. The appropriate read mode command must

be issued to the CUI to enter the corresponding

mode. Upon initial device power-up or after exit

from deep power-down mode, the device

automatically defaults to read array mode.

If RP# is taken low for time t_PLPHduring a program

or erase operation, the operation will be aborted

and the memory contents at the aborted location

are no longer valid. After returning from an aborted

operation, time t_PHQVor t_PHWL/t_PHELmust be met

CE# and OE# must be driven active to obtain data

at the outputs. CE# is the device selection control;

when active it enables the flash memory device.

OE# is the data output (DQ₀–DQ₇) control and it

drives the selected memory data onto the I/O bus.

For all read modes, WE# and RP# must be at V_IH.

Figure 14 illustrates a read cycle.

before

respectively.

a read or write operation is initiated

3.1.5

WRITE

A write is any command that alters the contents of

the memory array. There are two write commands:

Program (40H) and Erase (20H). Writing either of

these commands to the internal Command User

Interface (CUI) initiates a sequence of internally-

timed functions that culminate in the completion of

the requested task (unless that operation is aborted

by either RP# being driven to V_ILfor of t_PLRHor an

appropriate suspend command).

3.1.2

OUTPUT DISABLE

With OE# at a logic-high level (V_IH), the device

outputs are disabled. Output pins DQ₀–DQ₇are

placed in a high-impedance state.

3.1.3

STANDBY

The Command User Interface does not occupy an

addressable memory location. Instead, commands

are written into the CUI using standard

microprocessor write timings when WE# and CE#

are low, OE# = V_IH, and the proper address and

data (command) are presented. The command is

latched on the rising edge of the first WE# or CE#

pulse, whichever occurs first. Figure 15 illustrates a

write operation.

Deselecting the device by bringing CE# to a logic-

high level (V_IH) places the device in standby mode,

which substantially reduces device power

consumption. In standby, outputs DQ₀–DQ₇are

placed in a high-impedance state independent of

OE#. If deselected during program or erase

operation, the device continues to consume active

power until the program or erase operation is

complete.

Device operations are selected by writing specific

commands into the CUI. Table

4 defines the

available commands. Appendix B provides detailed

information on moving between the different modes

of operation.

3.1.4

DEEP POWER-DOWN/RESET

RP# at V_ILinitiates the deep power-down mode,

sometimes referred to as reset mode.

3.2

Modes of Operation

From read mode, RP# going low for time t_PLPH

accomplishes the following:

The flash memory has three read modes and two

write modes. The read modes are read array, read

identifier, and read status. The write modes are

program and block erase. Three additional mode

(erase suspend to program, erase suspend to read

and program suspend to read) are available only

during suspended operations. These modes are

1. deselects the memory

2. places output drivers in a high-impedance

state

After return from power-down, a time t_PHQVis

required until the initial memory access outputs are

15

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

reached using the commands summarized in Table

When the device is in the read array mode, four

control signals must be controlled to obtain data at

the outputs.

4.

A comprehensive chart showing the state

transitions is in Appendix B.

•

WE# must be logic high (V_IH)

CE# must be logic low (V_IL)

OE# must be logic low (V_IL)

RP# must be logic high (V_IH)

3.2.1

READ ARRAY

When RP# transitions from V_IL(reset) to V_IH, the

device will be in the read array mode and will

respond to the read control inputs (CE#, address

inputs, and OE#) without any commands being

written to the CUI.

In addition, the address of the desired location must

be applied to the address pins.

If the device is not in read array mode, as would be

the case after a program or erase operation, the

Read Array command (FFH) must be written to the

CUI before array reads can take place.

Table 4. Command Codes and Descriptions

Code Device Mode

Description

00

FF

40

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to

redefine these codes for future functions.

Read Array

Places the device in read array mode, such that array data will be output on the

data pins.

Program

Set-Up

This is a two-cycle command. The first cycle prepares the CUI for a program

operation. The second cycle latches addresses and data information and

initiates the WSM to execute the Program algorithm. The flash outputs status

register data when CE# or OE# is toggled. A Read Array command is required

after programming to read array data. See Section 3.2.4.

10

20

Alternate

Program Set-Up

(See 40H/Program Set-Up)

Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not

an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the

status register to a “1,” (b) place the device into the read status register mode,

and (c) wait for another command. See Section 3.2.5.

D0

Program

Resume

If the previous command was an Erase Set-Up command, then the CUI will

close the address and data latches, and begin erasing the block indicated on the

address pins. If a program or erase operation was previously suspended, this

command will resume that operation.

Erase Resume/

Erase Confirm

During program/erase, the device will respond only to the Read Status Register,

Program Suspend/Erase Suspend commands and will output status register

data when CE# or OE# is toggled.

16

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Table 4. Command Codes and Descriptions (Continued)

Code Device Mode

Description

B0

Program

Suspend

Issuing this command will begin to suspend the currently executing

program/erase operation. The status register will indicate when the operation

has been successfully suspended by setting either the program suspend (SR.2)

or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The

WSM will continue to idle in the SUSPEND state, regardless of the state of all

input control pins except RP#, which will immediately shut down the WSM and

the remainder of the chip if it is driven to V_IL. See Sections 3.2.4.1 and 3.2.5.1.

Erase

Suspend

70

Read Status

Register

This command places the device into read status register mode. Reading the

device will output the contents of the status register, regardless of the address

presented to the device. The device automatically enters this mode after a

program or erase operation has been initiated. See Section 3.2.3.

50

90

Clear Status

Register

The WSM can set the Block Lock Status (SR.1) , V_PPStatus (SR.3), Program

Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it

cannot clear them to “0.” Issuing this command clears those bits to “0.”

Intelligent

Identifier

Puts the device into the intelligent identifier read mode, so that reading the

device will output the manufacturer and device codes (A₀= 0 for manufacturer,

A₀= 1 for device, all other address inputs are ignored). See Section 3.2.2.

NOTE:

See Appendix B for mode transition information.

3.2.2

READ INTELLIGENT IDENTIFIER

3.2.3

READ STATUS REGISTER

To read the manufacturer and device codes, the

device must be in read intelligent identifier mode,

which can be reached by writing the Intelligent

Identifier command (90H). Once in intelligent

identifier mode, A₀= 0 outputs the manufacturer’s

identification code and A₀= 1 outputs the device

code. See Table 5 for product signatures. To return

to read array mode, write the Read Array command

(FFH).

The device status register indicates when

a

program or erase operation is complete, and the

success or failure of that operation. To read the

status register issue the Read Status Register

(70H) command to the CUI. This causes all

subsequent read operations to output data from the

status register until another command is written to

the CUI. To return to reading from the array, issue

the Read Array (FFH) command.

Table 5. Intelligent Identifier Table

The status register bits are output on DQ₀–DQ₇.

Device ID

The contents of the status register are latched on

the falling edge of OE# or CE#. This prevents

possible bus errors which might occur if status

register contents change while being read. CE# or

OE# must be toggled with each subsequent status

read, or the status register will not indicate

completion of a program or erase operation.

Size

Mfr. ID

-T

-B

(Top Boot) (Bottom

Boot)

8-Mbit

16-Mbit

89H

D2H

D0H

D3H

D1H

17

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

When the WSM is active, bit 7 (SR.7) of the status

register will indicate the status of the WSM; the

remaining bits in the status register indicate

whether or not the WSM was successful in

performing the desired operation (see Table 7).

When programming is complete, the Program

Status bits should be checked. If the programming

operation was unsuccessful, bit SR.4 of the status

register is set to indicate a program failure. If SR.3

is set then V_PPwas not within acceptable limits, and

the WSM did not execute the program command. If

SR.1 is set, a program operation was attempted to

a locked block and the operation was aborted.

3.2.3.1

Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and

clears bits 2, 6 and 7 to “0,” but cannot clear status

bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4,

and 5 indicate various error conditions, these bits

can only be cleared by the controlling CPU through

the use of the Clear Status Register (50H)

command. By allowing the system software to

control the resetting of these bits, several

operations may be performed (such as cumulatively

programming several addresses or erasing multiple

blocks in sequence) before reading the status

register to determine if an error occurred during that

series. Clear the Status Register before beginning

another command or sequence. Note, again, that

the Read Array command must be issued before

data can be read from the memory array.

The status register should be cleared before

attempting the next operation. Any CUI instruction

can follow after programming is completed;

however, to prevent inadvertent status register

reads, be sure to reset the CUI to read array mode.

3.2.4.1

Suspending and Resuming

Program

The Program Suspend command allows program

suspension in order to read data in other locations

of memory. Once the programming process starts,

writing the Program Suspend command to the CUI

requests that the WSM suspend the program

sequence (at predetermined points in the program

algorithm). The device continues to output status

register data after the Program Suspend command

is written. Polling status register bits SR.7 and SR.2

will determine when the program operation has

been suspended (both will be set to “1”).

3.2.4

PROGRAM MODE

Programming is executed using

a

two-write

sequence. The Program Setup command (40H) is

written to the CUI followed by a second write which

specifies the address and data to be programmed.

The WSM will execute the following sequence of

internally timed events:

t

_WHRH1/t_EHRH1specify the program suspend latency.

A Read Array command can now be written to the

CUI to read data from blocks other than that which

is suspended. The only other valid commands,

while program is suspended, are Read Status

Register and Program Resume. After the Program

Resume command is written to the flash memory,

the WSM will continue with the program process

and status register bits SR.2 and SR.7 will

automatically be cleared. After the Program

Resume command is written, the device

automatically outputs status register data when

read (see Figure 7, Program Suspend/Resume

Flowchart). V_PPmust remain at the same V_PPlevel

used for program while in program suspend mode.

RP# must also remain at V_IH.

1. Program the desired bits of the addressed

memory.

2. Verify that the desired bits are sufficiently

programmed.

Programming of the memory results in specific bits

within an address location being changed to a “0.” If

the user attempts to program “1”s, there will be no

change of the memory cell contents and no error

occurs.

The status register indicates programming status:

while the program sequence is executing, bit 7 of

the status register is a “0.” The status register can

be polled by toggling either CE# or OE#. While

programming, the only valid commands are Read

Status Register, Program Suspend, and Program

Resume.

3.2.4.2

V_PPSupply Voltage during

Program

V_PPsupply voltage considerations are outlined in

Section 3.4.

18

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

3.2.5.1 Suspending and Resuming Erase

3.2.5

ERASE MODE

To erase a block, write the Erase Set-up and Erase

Confirm commands to the CUI, along with an

address identifying the block to be erased. This

address is latched internally when the Erase

Confirm command is issued. Block erasure results

in all bits within the block being set to “1.” Only one

block can be erased at a time.

Since an erase operation requires on the order of

seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in

order to read data from or program data to another

block in memory. Once the erase sequence is

started, writing the Erase Suspend command to the

CUI requests that the WSM pause the erase

sequence at a predetermined point in the erase

algorithm. The status register will indicate if/when

the erase operation has been suspended.

The WSM will execute the following sequence of

internally timed events to:

A Read Array/Program command can now be

written to the CUI in order to read/write data from/to

blocks other than that which is suspended. The

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are

sufficiently programmed to “0.”

Program

command

can

subsequently

be

suspended to read yet another array location. The

only valid commands while erase is suspended are

Erase Resume, Program, Program Resume, Read

Array, or Read Status Register.

3. Erase all bits within the block to “1.”

4. Verify that all bits within the block are

sufficiently erased.

While the erase sequence is executing, bit 7 of the

status register is a “0.”

During erase suspend mode, the chip can be

placed in a pseudo-standby mode by taking CE# to

V_IH. This reduces active current consumption.

When the status register indicates that erasure is

complete, check the Erase Status bit to verify that

the erase operation was successful. If the Erase

operation was unsuccessful, SR.5 of the status

register will be set to a “1,” indicating an erase

error. If V_PPwas not within acceptable limits after

the Erase Confirm command was issued, the WSM

will not execute the erase sequence; instead, SR.5

of the status register is set to indicate an erase

error, and SR.3 is set to a “1” to identify that V_PP

supply voltage was not within acceptable limits.

Erase Resume continues the erase sequence when

CE# = V_IL. As with the end of a standard erase

operation, the status register must be read and

cleared before the next instruction is issued.

3.2.5.2

V_PPSupply Voltage during Erase

V_PPsupply voltage considerations are outlined in

Section 3.4.

After an erase operation, clear the Status Register

(50H) before attempting the next operation. Any

CUI instruction can follow after erasure is

completed; however, to prevent inadvertent status

register reads, it is advisable to reset the flash to

read array after the erase is complete.

19

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

Table 6. Command Bus Definitions

First Bus Cycle

Second Bus Cycle

Command

Read Array

Notes

Oper

Write

Addr

X

Data

Oper

Addr

Data

5

2,3,5

5

FFH

90H

70H

50H

40H

10H

20H

B0H

D0H

Intelligent Identifier

X

Read

IA

X

ID

Read Status Register

Clear Status Register

Write (Program)

X

SRD

5

X

4,5

5

X

Write

PA

BA

PD

Alternate Write (Program)

Block Erase/Confirm

Program/Erase Suspend

Program/Erase Resume

X

D0H

5

X

5

X

ADDRESS

DATA

BA = Block Address

IA = Identifier Address

PA = Program Address

X = Don’t Care

SRD = Status Register Data

ID = Identifier Data

PD = Program Data

NOTES:

1. Bus operations are defined in Table 3.

2. ₀= 0 for manufacturer code, A₀= 1 for device code.

A

3. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.

4. Either 40H or 10H command is valid.

20

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Table 7. Status Register Bit Definition

WSMS

7

ESS

6

ES

5

PS

4

VPPS

3

PSS

2

BLS

1

R

0

NOTES:

SR.7 WRITE STATE MACHINE STATUS

Check Write State Machine bit first to determine

Byte Program or Block Erase completion, before

checking Program or Erase Status bits.

1 = Ready

0 = Busy

(WSMS)

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

When Erase Suspend is issued, WSM halts

execution and sets both WSMS and ESS bits to

“1.” ESS bit remains set to “1” until an Erase

Resume command is issued.

0 = Erase In Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure

0 = Successful Block Erase

When this bit is set to “1,” WSM has applied the

max. number of erase pulses to the block and is

still unable to verify successful block erasure.

SR.4 = PROGRAM STATUS (PS)

1 = Error in Byte Program

When this bit is set to “1,” WSM has attempted

but failed to program a byte.

0 = Successful Byte Program

SR.3 = V_PPSTATUS (VPPS)

1 = V_PPLow Detect, Operation Abort

0 = V_PPOK

The V_PPStatus bit does not provide continuous

indication of V_PPlevel. The WSM interrogates V_PP

level only after the Program or Erase command

sequences have been entered, and informs the

system if V_PPhas not been switched on. The V_PP

is also checked before the operation is verified by

the WSM. The V_PPStatus bit is not guaranteed to

report accurate feedback between V_PPLKand

V_PPH

.

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

When Program Suspend is issued, WSM halts

execution and sets both WSMS and PSS bits to

“1.” PSS bit remains set to “1” until a Program

Resume command is issued.

0 = Program in Progress/Completed

SR.1 = Block Lock Status

If a program or erase operation is attempted to

one of the locked blocks, this bit is set by the

WSM. The operation specified is aborted and the

device is returned to read status mode.

1 = Program/Erase attempted on locked

block; Operation aborted

0 = No operation to locked blocks

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use and should

be masked out when polling the Status Register.

21

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

Start

Bus Operation

Command

Program Setup

Program

Comments

Write

Data = 40H

Write 40H

Data = Data to Program

Addr = Location to Program

Program Address/Data

Read Status Register

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

Repeat for subsequent programming operations.

No

SR.7 = 1?

Yes

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Standby

Command

Comments

Check SR.3

1

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4

1 = V_PPProgram Error

Standby

0

SR.4 =

0

Check SR.1

1

1 = Attempted Program to

Locked Block - Program

Aborted

Standby

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Block - Aborted

SR.1 =

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases where multiple bytes are programmed before full status is checked.

0

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

0605-07

Figure 6. Automated Byte Programming Flowchart

22

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Bus Operation

Command

Comments

Data = B0H

Start

Write

Program Suspend

Addr = X

Write B0H

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read

Addr = X

Read Status Register

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

0

SR.7 =

Check SR.2

1 = Program Suspended

0 = Program Completed

Standby

Write

1

Data = FFH

Addr = X

Read Array

SR.2 =

Program Completed

Read array data from block

other than the one being

programmed.

1

Read

Write FFH

Data = D0H

Addr = X

Write

Program Resume

Read Array Data

No

Done

Reading

Yes

Write D0H

Write FFH

Program Resumed

Read Array Data

0605-08

Figure 7. Program Suspend/Resume Flowchart

23

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

Start

Bus Operation

Command

Comments

Data = 20H

Addr = Within Block to Be

Erased

Write

Erase Setup

Write 20H

Data = D0H

Addr = Within Block to Be

Erased

Erase Confirm

Write D0H and

Block Address

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read

Read Status Register

Suspend

Erase Loop

Check SR.7

1 = WSM Ready

0 = WSM Busy

Standby

No

0

Yes

SR.7 =

1

Suspend Erase

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase or after a sequence of

block erasures.

Full Status

Check if Desired

Write FFH after the last write operation to reset device to read array mode.

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Command

Comments

Check SR.3

Standby

1

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4,5

Standby

Both 1 = Command Sequence

Error

0

SR.4,5 =

0

1

Check SR.5

1 = Block Erase Error

Command Sequence

Error

Check SR.1

1 = Attempted Erase of

Locked Block - Erase Aborted

SR.5 =

0

Block Erase Error

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases

where multiple bytes are erased before full status is checked.

Attempted Erase of

Locked Block - Aborted

SR.1 =

0

If an error is detected, clear the status register before attempting retry or other

error recovery.

Block Erase

Successful

0605-09

Figure 8. Automated Block Erase Flowchart

24

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Bus Operation

Command

Comments

Data = B0H

Start

Write

Erase Suspend

Addr = X

Write B0H

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Read

Addr = X

Read Status Register

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

0

SR.7 =

Check SR.6

1 = Erase Suspended

0 = Erase Completed

Standby

Write

1

Data = FFH

Addr = X

Read Array

SR.6 =

Erase Completed

Read array data from block

other than the one being

erased.

1

Read

Write FFH/40H

Program data to block other

than the one being erased.

Program

Write

Read Array Data/

Program Array

Data = D0H

Addr = X

Erase Resume

Done

Reading and/or

Programming

No

Yes

Write D0H

Write FFH

Erase Resumed

Read Array Data

0605-010

Figure 9. Erase Suspend/Resume Flowchart

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E

The 12V V_PPmode enhances programming

performance during the short period of time typically

found in manufacturing processes; however, it is

not intended for extended use. 12V may be applied

to V_PPduring program and erase operations for a

maximum of 1000 cycles on the main blocks and

2500 cycles on the parameter blocks. V_PPmay be

connected to 12V for a total of 80 hours maximum.

Stressing the device beyond these limits may cause

permanent damage.

3.3

Block Locking

The Smart 3 Advanced Boot Block flash memory

architecture features two hardware-lockable

parameter blocks so that the kernel code for the

system can be kept secure while other parameter

blocks are programmed or erased as necessary.

3.3.1

V

_PP= V_ILFOR COMPLETE

PROTECTION

Table 8. Write Protection Truth Table for

Advanced Boot Block Flash Memory Family

The V_PPprogramming voltage can be held low for

complete write protection of all blocks in the flash

device. When V_PPis below V_PPLK, any program or

erase operation will result in a error, prompting the

corresponding Status Register bit (SR.3) to be set.

V_PP

WP#

RP#

Write Protection

Provided

X

V_IL

V_IH

All Blocks Locked

V_IL

3.3.2

WP# = V_ILFOR BLOCK LOCKING

≥ V_PPLK

V_IL

Lockable Blocks

Locked

The lockable blocks are locked when WP# = V_IL;

any program or erase operation to a locked block

will result in an error, which will be reflected in the

status register. For top configuration, the top two

parameter blocks (blocks #37 and #38 for the

16-Mbit, and blocks #21 and #22 for the 8-Mbit) are

lockable. For the bottom configuration, the bottom

two parameter blocks (blocks #0 and #1 for 8-/16-

Mbit) are lockable. Unlocked blocks can be

programmed or erased normally (unless V_PPis

below V_PPLK).

≥ V_PPLK

V_IH

All Blocks Unlocked

3.5

Power Consumption

While in operation, the flash device consumes

active power. However, Intel flash devices have a

three-tiered approach to power savings that can

significantly reduce overall system power

consumption. The Automatic Power Savings (APS)

feature reduces power consumption when the

device is idle. If the CE# is deasserted, the flash

enters its standby mode, where current

consumption is even lower. If RP# = V_ILthe flash

enters a deep power-down mode, where current is

at a minimum. The combination of these features

can minimize overall memory power consumption,

and therefore, overall system power consumption.

3.3.3

WP# = V_IHFOR BLOCK UNLOCKING

WP# = V_IHunlocks all lockable blocks.

These blocks can now be programmed or erased.

Note that RP# does not override WP# locking as in

previous Boot Block devices. WP# controls all block

locking and V_PPprovides protection against

spurious writes. Table 8 defines the write protection

methods.

3.5.1

ACTIVE POWER

With CE# at a logic-low level and RP# at a logic-

high level, the device is in the active mode. Refer to

the DC Characteristics tables for I_CCcurrent values.

Active power is the largest contributor to overall

system power consumption. Minimizing the active

current could have a profound effect on system

power consumption, especially for battery-operated

devices.

3.4

V

Program and Erase

PP

Voltages

Intel’s Smart

programming and erase at 2.7V–3.6V V_PP. For

customers requiring fast programming in their

3

products provide in-system

manufacturing environment, Smart

3 Advanced

Boot Block includes an additional low-cost,

backward-compatible 12V programming feature.

26

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

3.5.2

AUTOMATIC POWER SAVINGS (APS)

During deep power-down, all internal circuits are

switched to a low power savings mode (RP#

transitioning to V_ILor turning off power to the device

clears the status register).

Automatic Power Savings provides low-power

operation during active mode. Power Reduction

Control (PRC) circuitry allows the flash to put itself

into a low current state when not being accessed.

After data is read from the memory array, PRC

logic controls the device’s power consumption by

entering the APS mode where typical I_CCcurrent is

comparable to I_CCS. The flash stays in this static

state with outputs valid until a new location is read.

3.6

Power-Up/Down Operation

The device is protected against accidental block

erasure or programming during power transitions.

Power supply sequencing is not required, since the

device is indifferent as to which power supply, V_PP

or V_CC, powers-up first.

APS reduces active current to standby current

levels for 2.7V–3.6V CMOS input levels.

3.6.1

RP# CONNECTED TO SYSTEM

RESET

3.5.3

STANDBY POWER

With CE# at a logic-high level (V_IH) and the CUI in

read mode, the flash memory is in standby mode,

which disables much of the device’s circuitry and

substantially reduces power consumption. Outputs

(DQ₀–DQ₇) are placed in a high-impedance state

independent of the status of the OE# signal. If CE#

transitions to a logic-high level during erase or

program operations, the device will continue to

perform the operation and consume corresponding

active power until the operation is completed.

The use of RP# during system reset is important

with automated program/erase devices since the

system expects to read from the flash memory

when it comes out of reset. If a CPU reset occurs

without

a

flash memory reset, proper CPU

initialization will not occur because the flash

memory may be providing status information

instead of array data. Intel recommends connecting

RP# to the system CPU RESET# signal to allow

proper CPU/flash initialization following system

reset.

System engineers should analyze the breakdown of

standby time versus active time and quantify the

respective power consumption in each mode for

their specific application. This will provide a more

accurate measure of application-specific power and

energy requirements.

System designers must guard against spurious

writes when V_CCvoltages are above V_LKOand V_PP

is active. Since both WE# and CE# must be low for

a command write, driving either signal to V_IHwill

inhibit writes to the device. The CUI architecture

provides additional protection since alteration of

memory contents can only occur after successful

completion of the two-step command sequences.

The device is also disabled until RP# is brought to

V_IH, regardless of the state of its control inputs. By

holding the device in reset (RP# connected to

system PowerGood) during power-up/down, invalid

bus conditions during power-up can be masked,

providing yet another level of memory protection.

3.5.4

DEEP POWER-DOWN MODE

The deep power-down mode of the Smart

3

Advanced Boot Block products switches the device

into a low power savings mode, which is especially

important for battery-based devices. This mode is

activated when RP# = V_IL. (GND ± 0.2V).

During read modes, RP# going low de-selects the

memory and places the output drivers in a high

impedance state. Recovery from the deep power-

down state, requires a minimum time equal to t_PHQV

(see AC Characteristics table).

3.6.2

V_CC, V_PPAND RP# TRANSITIONS

The CUI latches commands as issued by system

software and is not altered by V_PPor CE#

transitions or WSM actions. Its default state upon

power-up, after exit from deep power-down mode or

after V_CCtransitions above V_LKO(Lockout voltage),

is read array mode.

During program or erase modes, RP# transitioning

low will abort the operation, but the memory

contents of the address being programmed or the

block being erased are no longer valid as the data

integrity has been compromised by the abort.

27

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

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After any program or block erase operation is

complete (even after V_PPtransitions down to

Transient current magnitudes depend on the device

outputs’ capacitive and inductive loading. Two-line

control and proper decoupling capacitor selection

will suppress these transient voltage peaks. Each

V

_PPLK), the CUI must be reset to read array mode

via the Read Array command if access to the flash

memory array is desired.

flash device should have

a

0.1 µF ceramic

capacitor connected between each V_CCand GND,

and between its V_PPand GND. These high-

frequency, inherently low-inductance capacitors

should be placed as close as possible to the

package leads.

Refer to AP-617 Additional Flash Data Protection

Using V_PP, RP#, and WP# for a circuit-level

description of how to implement the protection

schemes discussed in Section 3.5.

3.7.1

V

_PPTRACE ON PRINTED CIRCUIT

3.7

Power Supply Decoupling

BOARDS

Flash memory’s power switching characteristics

require careful device decoupling. System

designers should consider three supply current

issues:

Designing for in-system writes to the flash memory

requires special consideration of the V_PPpower

supply trace by the printed circuit board designer.

The V_PPpin supplies the flash memory cells current

for programming and erasing. V_PPtrace widths and

layout should be similar to that of V_CC. Adequate

V_PPsupply traces, and decoupling capacitors

placed adjacent to the component, will decrease

spikes and overshoots.

1. Standby current levels (I_CCS

)

2. Active current levels (I_CCR

)

3. Transient peaks produced by falling and rising

edges of CE#.

28

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

4.0 ABSOLUTE MAXIMUM

RATINGS*

NOTICE: This datasheet contains preliminary information on

products in production. The specifications are subject to

change without notice. Verify with your local Intel Sales

office that you have the latest datasheet before finalizing a

design.

Extended Operating Temperature

During Read ............................ –40°C to +85°C

* WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent damage. These

are stress ratings only. Operation beyond the "Operating

Conditions" is not recommended and extended exposure

beyond the "Operating Conditions" may effect device

reliability.

During Block Erase

and Program............................ –40°C to +85°C

Temperature Under Bias ......... –40°C to +85°C

Storage Temperature................... –65°C to +125°C

Voltage on Any Pin

(except V_CC, VCCQ and V_PP

)

NOTES:

with Respect to GND............... –0.5V to +5.0V¹

1. Minimum DC voltage is –0.5V on input/output pins.

During transitions, this level may undershoot to–2.0V

for periods < 20 ns. Maximum DC voltage on

input/output pins is V_CC+ 0.5V which, during

transitions, may overshoot to V_CC+ 2.0V for periods <

20 ns.

V_PPVoltage (for Block

Erase and Program)

with Respect to GND.........–0.5V to +13.5V^1,2,4

V_CCand V_CCQSupply Voltage

with Respect to GND............... –0.2V to +5.0V¹

2. Maximum DC voltage on V_PPmay overshoot to +14.0V

for periods < 20 ns.

Output Short Circuit Current...................... 100 mA³

3. Output shorted for no more than one second.No more

than one output shorted at a time.

4.

V_PPProgram voltage is normally 2.7V–3.6V.

Connection to supply of 11.4V–12.6V can only be done

for 1000 cycles on the main blocks and 2500 cycles on

the parameter blocks during program/erase. V may

PP

be connected to 12V for a total of 80 hours maximum.

See Section 3.4 for details.

5.0 OPERATING CONDITIONS (V

= 2.7V–3.6V)

CCQ

Table 9. Temperature and Voltage Operating Conditions⁴

Symbol

T_A

Parameter

Notes

Min

–40

Max

+85

3.6

Units

°C

Operating Temperature

V_CC

2.7V–3.6V V_CCSupply Voltage

2.7V–3.6V I/O Supply Voltage

Program and Erase Voltage

1,4

1,2,4

4

2.7

Volts

Cycles

V_CCQ

V_PP1

2.7

3.6

2.7

3.6

V_PP2

3

11.4

10,000

12.6

Cycling

Block Erase Cycling

5

NOTES:

1. See DC Characteristics tables for voltage range-specific specifications.

2. The voltage swing on the inputs, V_INis required to match V_CCQ

3. Applying V_PP= 11.4V–12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks

.

and 2500 cycles on the parameter blocks. V may be connected to 12V for a total of 80 hours maximum. See section 3.4

PP

for details.

4.

V_CC, V_CCQand V_PP1must share the same supply when all three are between 2.7V and 3.6V.

5. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to

30,000 cycles.

29

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

5.1

DC Characteristics: V

= 2.7V–3.6V

CCQ

Table 10. DC Characteristics

Sym

Parameter

Notes V_CC= 2.7V–3.6V Unit

Test Conditions

Typ

Max

V_CC= V_CCMax = V_CCQMax

V_IN= V_CCQor GND

I_LI

Input Load Current

1

± 1.0

µA

V_CC= V_CCMax = V_CCQMax

V_IN= V_CCQor GND

I_LO

I_CCS

Output Leakage Current

V_CCStandby Current

± 10

50

1,7

20

1

CMOS INPUTS

V_CC= V_CCMax = V_CCQMax

CE# = RP# = V_CCQ

CMOS INPUTS

I_CCD

V_CCDeep Power-Down

Current

1,7

10

20

µA

V_CC= V_CCMax = V_CCQMax

V_IN= V_CCQor GND

RP# = GND ± 0.2V

CMOS INPUTS

V_CC= V_CCMax = V_CCQMax

OE# = V_IH, CE# =V_IL

f = 5 MHz,

I_CCR

V_CCRead Current

1,5,7

10

mA

I_OUT= 0 mA

Inputs = V_ILor V_IH

I_CCW

V_CCProgram Current

V_CCErase Current

1,4,7

8

20

50

mA

µA

V_PP= V_PPH1(3V)

Program in Progress

V_PP= V_PPH2(12V)

Program in Progress

I_CCE

8

V_PP= V_PPH1(3V)

Erase in Progress

8

V_PP= V_PPH2(12V)

Erase in Progress

I_CCESV_CCErase Suspend

Current

1,2,4,7

20

CE# = V_IH

Erase Suspend in Progress

I_CCWSV_CCProgram Suspend

Current

1,2,4,7

20

0.2

2

50

5

µA

CE# = V_IH

Program Suspend in Progress

I_PPD

V_PPDeep Power-Down

Current

1

RP# = GND ± 0.2V

I_PPR

V_PPRead Current

±50

V_PP≤ V_CC

30

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Table 10. DC Characteristics (Continued)

Sym

Parameter

Notes V_CC= 2.7V–3.6V

Unit

Test Conditions

Typ

Max

I_PPW

V_PPProgram Current

1,4

15

40

mA

µA

V_PP= V_PPH1(3V)

Program in Progress

10

13

8

25

V_PP= V_PPH2(12V)

Program in Progress

I_PPE

V_PPErase Current

V_PP= V_PPH1(3V)

Erase in Progress

25

V_PP= V_PPH2(12V)

Erase in Progress

I_PPESV_PPErase Suspend

Current

1,4

50

200

V_PP= V_PPH1or V_PPH2

Erase Suspend in Progress

I_PPWSV_PPProgram Suspend

Current

1,4

µA

V_PP= V_PPH1or V_PPH2

Program Suspend in Progress

31

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

Table 10. DC Characteristics (Continued)

Sym

Parameter

Notes V_CC= 2.7V–3.6V

Unit

Test Conditions

Min

Max

V_IL

Input Low Voltage

–0.4

0.4

V

V^CCQ–

0.4V

V_IH

Input High Voltage

V_OL

Output Low Voltage

Output High Voltage

0.10

V

V_CC= V_CCMin = VCCQMin

I_OL= 100 µA

V_OH

VCCQ –

0.1V

V_CC= V_CCMin = VCCQMin

I_OH= –100 µA

V_PPLKV_PPLock-Out Voltage

3

1.5

2.7

V

Complete Write Protection

V_PPH1V_PPduring Prog/Erase

Operations

3.6

V_PPH2

3,6

11.4

1.5

12.6

V

V_CCProgram/Erase Lock

V_LKO

Voltage

V_CCQProgram/Erase

V_LKO2

1.2

V

Lock Voltage

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V_CC, T_A= +25°C.

2. _CCESand I_CCWSare specified with device de-selected. If device is read while in erase suspend, current draw is I_CCR. If the

device is read while in program suspend, current draw is I_CCR

I

.

3. Erase and Program are inhibited when V_PP< V_PPLKand not guaranteed outside the valid V_PPranges of V_PPH1and V_PPH2

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto approximately standby levels in static operation (CMOS inputs).

6. Applying V_PP= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter blocks. V may be connected to 12V for a total of 80 hours maximum. See Section 3.4

PP

for details.

7. Includes the sum of V_CCand V_CCQcurrent.

Table 11. Capacitance (T_A= 25°C, f = 1 MHz)

Sym

Parameter

Notes

Typ

6

Max

8

Units

pF

Conditions

C_IN

Input Capacitance

1

V_IN= 0V

V_OUT= 0V

C_OUTOutput Capacitance

10

12

pF

NOTE:

1. Sampled, not 100% tested.

32

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

V_CCQ

2

V_CCQ

OUTPUT

INPUT

TEST POINTS

2

0.0

0605-011

NOTE:

AC test inputs are driven at V_CCQfor a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at V_CCQ/2.

Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are when V_CCQ=2.7V.

Figure 10. 2.7V–3.6V Input Range and Measurement Points

Test Configuration Component Values

for Worst Case Speed Conditions

Test Configuration C_L(pF) R₁(Ω) R₂(Ω)

2.7V Standard Test 50 25K 25K

V

CCQ

R

1

Device

under

Test

Out

C_L

2

0605-012

NOTE:

See table for component values.

Figure 11. Test Configuration

33

PRELIMINARY

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6.0 OPERATING CONDITIONS (V

= 1.8V–2.2V)

CCQ

Table 12. Temperature and V_CCOperating Conditions

Symbol

T_A

Parameter

Notes

Min

–40

2.7

Max

+85

2.85

3.3

Units

°C

Operating Temperature

V_CC1

V_CC2

V_CCQ

V_PP1

2.7V–2.85V V_CCSupply Voltage

2.7V–3.3V V_CCSupply Voltage

1.8V–2.2V I/O Supply Voltage

Program and Erase Voltage

1

Volts

Cycles

2.7

1,4

1

1.8

2.2

2.7

2.85

3.3

V_PP2

1

2.7

V_PP3

1,2

3

11.4

10,000

12.6

Cycling

Block Erase Cycling

NOTES:

1. See DC Characteristics tables for voltage range-specific specifications.

2. Applying V_PP= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter. V may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for

PP

details.

3. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to

30,000 cycles.

4. The voltage swing on the inputs, V_INis required to match V_CCQ

.

6.1

DC Characteristics: V

= 1.8V–2.2V

CCQ

These tables are valid for the following power supply combinations only:

1. V_CC1and V_CCQand (V_PP1or V_PP3

)

2. V_CC2and V_CCQand (V_PP2or V_PP3

Wherever the input voltage V_INis mentioned, it is required that V_INmatches the chosen V_CCQ

.

34

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Table 13. DC Characteristics: V_CCQ= 1.8V–2.2V

V_CC1

2.7V–2.85V

V_CC2

2.7V–3.3V

:

Sym

Parameter

Notes

Unit

Test Conditions

:

Typ

Max

V_CC= V_CCMax

V_CCQ= V_CCQMax

V_IN= V_CCQor GND

I_LI

Input Load Current

1

± 1.0

± 10

50

µA

V_CC= V_CCMax

V_CCQ= V_CCQMax

V_IN= V_CCQor GND

I_LO

Output Leakage Current

V_CCStandby Current

I_CCS

1,7

20

150

1

CMOS INPUTS

V_CC= V_CC1Max (2.7V–2.85V)

V_CCQ= V_CCQMax

CE# = RP# = V_CCQ

250

10

µA

CMOS INPUTS

V_CC= V_CC2Max (2.7V–3.3V)

V_CCQ= V_CCQMax

CE# = RP# = V_CCQ

CMOS INPUTS

V_CC= V_CCMax (V_CC1or V_CC2

V_CCQ= V_CCQMax

I_CCD

V_CCDeep Power-Down

Current

1,7

)

V_IN= V_CCQor GND

RP# = GND ± 0.2V

CMOS INPUTS

V_CC= V_CC1Max (2.7V–2.85V)

V_CCQ= V_CCQMax

I_CCR

V_CCRead Current

1,5,7

8

18

mA

OE# = V_IH, CE# = V_IL

f = 5 MHz, I_OUT= 0 mA

Inputs = V_ILor V_IH

CMOS INPUTS

12

23

mA

V_CC= V_CC2Max (2.7V–3.3V)

V_CCQ= V_CCQMax

OE# = V_IH, CE# = V_IL

f = 5 MHz, I_OUT= 0 mA

Inputs = GND ± 0.2V or V_CCQ

35

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E

Table 13. DC Characteristics: V_CCQ= 1.8V–2.2V (Continued)

V_CC1

2.7V–2.85V

V_CC2

2.7V–3.3V

:

Sym

Parameter

Notes

Unit

Test Conditions

:

Typ

Max

I_CCW

V_CCProgram Current

V_CCErase Current

1,4,7

8

20

mA

µA

V_PP= V_PPH1or V_PPH2

Program in Progress

8

20

50

5

V_PP= V_PPH3(12V)

Program in Progress

I_CCE

8

V_PP= V_PPH1or V_PPH2

Erase in Progress

8

V_PP= V_PPH3(12V)

Erase in Progress

I_CCESV_CCErase Suspend

Current

1,2,4,7

1

20

0.2

CE# = V_IH

Erase Suspend in Progress

I_CCWSV_CCProgram Suspend

Current

µA

CE# = V_IH

Program Suspend in Progress

I_PPD

V_PPDeep Power-Down

Current

µA

RP# = GND ± 0.2V

I_PPR

I_PPW

V_PPRead and Standby

Current

1

2

±50

40

µA

V_PP≤ V_CC

V_PPProgram Current

1,4

15

mA

V_PP= V_PPH1or V_PPH2

Program in Progress

10

13

8

25

mA

µA

V_PP= V_PPH3(12V)

Program in Progress

V

_PP= V_PPH1or V_PPH2

I_PPE

V_PPErase Current

1,4

Erase in Progress

25

V_PP= V_PPH3(12V)

Erase in Progress

I_PPESV_PPErase Suspend

Current

1

50

200

V_PP= V_PPH1, V_PPH2, or V_PPH3

Erase Suspend in Progress

I_PPWSV_PPProgram Suspend

Current

µA

V_PP= V_PPH1, V_PPH2, or V_PPH3

Program Suspend in Progress

36

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Table 13. DC Characteristics: V_CCQ= 1.8V–2.2V (Continued)

V_CC1

2.7V–2.85V

V_CC2

2.7V–3.3V

:

Sym

Parameter

Notes

Unit

Test Conditions

:

Typ

Max

V_IL

Input Low Voltage

–0.2

0.2

V

V_CCQ

0.2V

–

V_IH

Input High Voltage

V_CC= V_CCMin

V_CCQ= V_CCQMin

_OL= 100 µA

V_OL

Output Low Voltage

Output High Voltage

–0.10

0.10

V

I

V_CC= V_CCMin

V_CCQ= V_CCQMin

I_OH= –100 µA

V_OH

V_CCQ

0.1V

–

V

V_PPLKV_PPLock-Out Voltage

3

1.5

2.7

V

Complete Write Protection

V_PPduring Prog./Erase

Operations

V_PPH1

2.85

V_PPH2

V_PPH3

V_LKO1

3

2.7

11.4

1.5

3.3

V

3,6

12.6

V_CCProgram/Erase Lock

Voltage

V_CCQProgram/Erase

Lock Voltage

V_LKO2

1.2

V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V_CC, T_A= +25°C.

2. _CCESand I_CCWSare specified with device de-selected. If device is read while in erase suspend, current draw is I_CCR. If the

device is read while in program suspend, current draw is I_CCR

I

.

3. Erases and Writes inhibited when V_PP< V_PPLK, and not guaranteed outside the valid V_PPranges of V_PPH1,V_PPH2. or V_PPH3.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto approximately standby levels in static operation (CMOS inputs).

6. Applying V_PP= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter blocks. V may be connected to 12V for a total of 80 hours maximum. See Section 3.4

PP

for details.

7

Includes the sum of V_CCand V_CCQcurrent

Table 14. Capacitance (T_A= 25°C, f = 1 MHz)

Sym

C_IN

Parameter

Notes

Typ

6

Max

8

Units

pF

Conditions

Input Capacitance

1

V_IN= 0V

V_OUT= 0V

C_OUTOutput Capacitance

10

12

pF

NOTE:

1. Sampled, not 100% tested.

37

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

V_CCQ

2

OUTPUT

INPUT

TEST POINTS

2

0.0

0605-011

NOTE:

AC test inputs are driven at V_CCQfor a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at V_CCQ/2.

Input rise and fall times (10%–90%) <10 ns. For worst case speed conditions V_CCQ=1.8V.

Figure 12. 1.8V—2.2V Input Range and Measurement Points

Test Configuration Component Values

for Worst Case Speed Conditions

Test Configuration C_L(pF) R₁(Ω) R₂(Ω)

50 16.7K 16.7K

V

CCQ

1.8V Standard Test

R

1

NOTE:

C

_Lincludes jig capacitance.

Device

under

Test

Out

C_L

2

0605-012

NOTE:

See table for component values.

Figure 13. Test Configuration

38

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

7.0 AC CHARACTERISTICS

AC Characteristics are applicable to both V_CCQranges.

Table 15. AC Characteristics: Read Operations (Extended Temperature)

Load

V_CC

C_L= 50 pF

#

Symbol

Parameter

2.7V–3.6V⁴

Units

Prod

Notes

120 ns

150 ns

Min

Max

Min

Max

R1

R2

R3

R4

R5

R6

R7

R8

R9

t_AVAV

t_AVQV

t_ELQV

t_GLQV

t_PHQV

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

Read Cycle Time

120

150

ns

Address to Output Delay

CE# to Output Delay

OE# to Output Delay

RP# to Output Delay

CE# to Output in Low Z

OE# to Output in Low Z

CE# to Output in High Z

OE# to Output in High Z

120

65

150

65

2

600

3

0

40

R10 t_OH

Output Hold from Address, CE#,

or OE# Change, Whichever

Occurs First

0

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t_ELQV–t_GLQVafter the falling edge of CE# without impact on t_ELQV

.

3. Sampled, but not 100% tested.

4. See Test Configuration (Figures 11 and 13), 2.7V–3.6V and 1.8V–2.2V Standard Test component values.

39

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

Data

Valid

Device and

Standby

Address Selection

V_IH

ADDRESSES (A)

Address Stable

V_IL

R1

V_IH

CE# (E)

OE# (G)

V_IL

V_IH

R8

R9

V_IL

V_IH

WE# (W)

R4

R3

R7

R10

V_IL

V_OH

R6

R5

High Z

DATA (D/Q)

V_OL

Valid Output

R2

V_IH

RP#(P)

V_IL

0605-015

Figure 14. AC Waveform: Read Operations

40

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

Table 16. AC Characteristics: Write Operations (Extended Temperature)¹

Load 50 pF

V_CC

#

Symbol

Parameter

2.7V–3.6V⁵

2.7V-3.6V⁵

150 ns

Units

Prod

120 ns

Notes

Min

Max

Min

Max

W1

W2

W3

W4

W5

W6

W7

W8

W9

t_PHWL

t_PHEL

RP# High Recovery to

WE# (CE#) Going Low

600

ns

t_ELWL

t_WLEL

CE# (WE#) Setup to

WE# (CE#) Going Low

0

t_WLWH

t_ELEH

WE# (CE#) Pulse Width

90

70

90

0

90

70

90

0

t_DVWH

t_DVEH

Data Setup to WE#

(CE#) Going High

3

2

t_AVWH

t_AVEH

Address Setup to WE#

(CE#) Going High

t_WHEH

t_EHWH

CE# (WE#) Hold Time

from WE# (CE#) High

t_WHDX

t_EHDX

Data Hold Time from

WE# (CE#) High

3

2

0

t_WHAX

t_EHAX

Address Hold Time from

WE# (CE#) High

0

t_WHWL

t_EHEL

WE# (CE#) Pulse Width

High

30

200

0

30

200

0

W10 t_VPWH

t_VPEH

V_PPSetup to WE# (CE#)

Going High

4

W11 t_QVVL

t_LOCK

V_PPHold from Valid SRD

4

ns

Block Unlock / Lock

Delay

4, 6

200

NOTES:

1. Read timing characteristics during program suspend and erase suspend are the same as during read-only operations.

Refer to AC Characteristics during read mode.

2. Refer to command definition table for valid A_IN(Table6).

3. Refer to command definition table for valid D_IN(Table 6).

4. Sampled, but not 100% tested.

5. See Test Configuration (Figure 11 and 13), 2.7V–3.6V and 1.8V–2.2V Standard Test component values.

6. Time t_LOCKis required for successful locking and unlocking of all lockable blocks.

41

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

A

B

C

D

E

F

V_IH

ADDRESSES [A]

CE#(WE#) [E(W)]

A_IN

V_IL

V_IH

W8

(Note 1)

W5

V_IL

V_IH

W6

W2

OE# [G]

V_IL

V_IH

W9

(Note 1)

WE#(CE#) [W(E)]

V_IL

W3

W4

W7

V_IH

V_IL

High Z

W1

Valid

SRD

DATA [D/Q]

D_IN

V_IH

V_IL

V_IH

V_IL

RP# [P]

WP#

W10

W11

V_PPH2

V_PPH

V_PPLK

V_IL

1

V

[V]

PP

0605-016

NOTES:

1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register

Data.

A.

V

Power-Up and Standby.

CC

B. Write Program or Erase Setup Command.

C. Write Valid Address and Data (for Program) or Erase Confirm Command.

D. Automated Program or Erase Delay.

E. Read Status Register Data (SRD): reflects completed program/erase operation.

F. Write Read Array Command.

Figure 15. AC Waveform: Program and Erase Operations

42

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

7.1

Reset Operations

V

IH

RP# (P)

t_PHQV

t_PHWL

t_PHEL

V_IL

t _PLPH

(A) Reset during Read Mode

Abort

Complete

t_PHQV

t_PHWL

t_PHEL

t _PLRH

V_IH

V_IL

RP# (P)

t _PLPH

t_PLPH

t _PLRH

<

(B) Reset during Program or Block Erase,

Abort Deep

Complete Power-

t_PHQV

t_PHWL

t_PHEL

Down

t _PLRH

V_IH

V_IL

RP# (P)

t _PLPH

(C) Reset Program or Block Erase,

>

t _PLPHt _PLRH

0605-17

Figure 16. AC Waveform: Deep Power-Down/Reset Operation

Reset Specifications

V_CC= 2.7–3.6V

Symbol

Parameter

Notes

Min

Max

Unit

t_PLPH

RP# Low to Reset during Read

(If RP# is tied to V_CC, this specification is not

applicable)

1,3

100

ns

t_PLRH

RP# Low to Reset during Block Erase or Program

2,3

22

µs

NOTES:

1. If t_PLPHis < 100 ns the device may still RESET but this is not guaranteed.

2. If RP# is asserted while a block erase or byte program operation is not executing, the reset will complete within 100 ns.

3. Sampled but not 100% tested.

43

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

Table 17. Erase and Program Timings

V_PP= 2.7V

V_PP= 12V

Typ¹Max³

Sym

Parameter

Notes

Typ¹

Max³

Unit

t_BWPB

Block Program Time

(Parameter)

2

.16

.48

.08

.24

sec

t_BWMB

Block Program Time (Main)

2

1.23

17

3.69

165

.58

8

1.74

185

sec

t_WHQV1Program Time

t_EHQV1

µs

t_WHQV2Block Erase Time (Parameter)

t_EHQV2

2

3

1

1.8

5

5.0

8.0

10

0.8

1.1

5

4.8

7.0

10

sec

µs

t_WHQV3Block Erase Time (Main)

t_EHQV3

t_WHRH1Program Suspend Latency

t_EHRH1

t_WHRH2Erase Suspend Latency

t_EHRH2

5

20

6

12

µs

NOTES:

1. Typical values measured at T_A= +25°C and nominal voltages.

2. Excludes external system-level overhead.

3. Sampled but not 100% tested.

44

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

APPENDIX A

ORDERING INFORMATION

T E 2 8 F 1 6 0 B 3 T 1 2 0

Package

TE = 40-Lead TSOP

GT = 48-Ball µBGA* CSP

Access Speed (ns)

(120, 150)

T = Top Blocking

Product line designator

B = Bottom Blocking

for all Intel Flash products

Product Family

B3 = Smart 3 Advanced Boot Block

V_CC= 2.7V - 3.6V

Device Density

016 = x8 (16-Mbit)

008 = x8 (8-Mbit)

V_PP= 2.7V - 3.6V or 11.4V - 12.6V

VALID COMBINATIONS

Extended

40-Lead TSOP

TE28F016B3T120

TE28F016B3B120

48-Ball µBGA* CSP

GT28F016B3T120

GT28F016B3B120

16M

8M

TE28F016B3T150

TE28F016B3B150

GT28F016B3T150

GT28F016B3B150

Extended

TE28F008B3T120

TE28F008B3B120

GT28F008B3T120

GT28F008B3B120

TE28F008B3T150

TE28F008B3B150

GT28F008B3T150

GT28F008B3B150

45

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

APPENDIX B

WRITE STATE MACHINE CURRENT/NEXT STATES

Command Input (and Next State)

Current

State

SR.7

Data

When

Read

Array

(FFH)

Program

Setup

Erase

Setup

(20H)

Erase

Confirm

(D0H)

Program / Program /

Read

Status

(70H)

Clear

Status

(50H)

Read ID

(90H)

Erase

Susp.

(B0H)

Erase

Resume

(D0)

(40/10H)

Read Array

“1”

“0”

“1”

Array

Status

Read

Array

Program

Setup

Erase

Setup

Read Array

Read

Array

Read

Status

Identifier

Program

Setup

Pgm.¹

Program (Command input = Data to be programmed)

Program

Pgm Susp.

to Status

Program

(Not Comp.)

Program

Read

Array

Program

Setup

Erase

Setup

Read Array

Read

Array

Read

(Complete)

Status

Identifier

Program

Suspend to

Status

Prog.

Susp. to

Array

Program Suspend

to Array

Program

Susp. to

Array

Program

Prog.

Susp. to

Status

Program Suspend to

Array

Program

Suspend to

Array

“1”

Array

Prog.

Susp. to

Array

Program Suspend

to Array

Program

Erase

Program

Susp. to

Array

Program

Erase

Prog.

Susp. to

Array

Susp. to Susp. to

Status Array

Erase Setup

“1”

“0”

“1”

Status

Erase Command Error

Erase

Erase Command Error

Cmd. Err.

Erase

Read

Program

Setup

Erase

Read Array

Read

Status

Read

Array

Read

Cmd. Error

Array

Setup

Identifier

Erase

Ers. Susp.

to Status

Erase

(Not Comp)

Erase

Read

Array

Program

Setup

Erase

Setup

Read Array

Read

Array

Read

(Complete)

Status

Identifier

Erase

Suspend to

Status

Erase

Susp. to

Array

Program

Setup

Erase

Susp. to

Array

Erase

Susp. to

Array

Erase

Susp. to

Status

Erase Suspend

to Array

Erase. Susp.

to Array

“1”

Array

Erase

Susp. to

Array

Program

Setup

Erase

Susp. to

Array

Erase

Susp. to

Array

Erase

Susp. to

Status

Erase Suspend

to Array

Read Status

“1”

Status

ID

Read

Array

Program

Setup

Erase

Setup

Read Array

Read

Array

Read

Status

Identifier

Read

Array

Program

Setup

Erase

Setup

Read Array

Read

Array

Read

Identifier

Status

Identifier

1. You cannot program “1”s to the flash. Writing FFH following the Program Setup will initiate the internal program algorithm

of the WSM. Although the algorithm will execute, array data is not changed. The WSM returns to read status mode without

reporting any error. Assuming V_PP> V_PPLKwriting a second FFH while in read status mode will return the flash to read

array mode.

46

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

APPENDIX C

ACCESS TIME VS. CAPACITIVE LOAD

(t vs. C )

AVQV

L

Access Time vs. Load Capacitance

Derating Curve

124

123

122

121

120

119

118

117

116

115

Smart 3 Advanced Boot

Block

30

50

70

100

Load Capacitance(pF)

NOTE:

V_CCQ= 2.7V

This chart shows a derating curve for device access time with respect to capacitive load. The value in the

DC characteristics section of the specification corresponds to C_L= 50 pF.

NOTE:

1. Sampled, but not 100% tested

47

PRELIMINARY

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

E

APPENDIX D

ARCHITECTURE BLOCK DIAGRAM

DQ₀-DQ₇

V_CCQ

Output Buffer

Input Buffer

Identifier

Register

Status

Register

I/O Logic

CE#

WE#

OE#

RP#

Command

User

Interface

Power

Reduction

Control

Data

Comparator

WP#

A₀-A₂₀

Y-Decoder

Y-Gating/Sensing

Write State

Machine

Program/Erase

Voltage Switch

Input Buffer

V_PP

Address

Latch

X-Decoder

V_CC

GND

Address

Counter

48

PRELIMINARY

E

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

APPENDIX E

(1,2

ADDITIONAL INFORMATION

)

Order Number

Document/Tool

210830

290580

1997 Flash Memory Databook

Smart 3 Advanced Boot Block Word-Wide 4-Mbit (256K x 16), 8-Mbit (512K

x16), 16-Mbit (1024K x16) Flash Memory Family Datasheet

292172

AP-617 Additional Flash Data Protection Using V_PP, RP# and WP#

NOTE:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.

49

PRELIMINARY


型号：	GT28F016B3B120
厂家：	INTEL
描述：	SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE 智能3高级启动块的字节宽
文件：	总49页 (文件大小：403K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GT28F016B3B120 [INTEL]

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