HBLXT9785HC.B2SE001_技术文档

LXT9785/9785E

Advanced 10/100 8-Port Transceivers

Datasheet

The LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers that support IEEE

802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide both Serial/

Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media

Independent Interface (RMII) for switching and other independent port applications. The

LXT9785 and LXT9785E are identical except for the IP telephony features included in the

LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects

Data Terminal Equipment (DTE) capable of being powered remotely from the switch over a

Category 5 cable. The system can use the information collected by the LXT97985E to apply

power if the DTE at the far end requires power over the cable, such as an IP telephone.

All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for

both 10 Mbps or 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair, or 100

Mbps (100BASE-FX) Ethernet over fiber-optic media.

The LXT9785/9785E provides three discrete LED driver outputs for each port. The devices

support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a

single 2.5V power supply.

Applications

I Enterprise switches

I Storage Area Networks

I IP telephony switches

I Multi-port Network Interface Cards (NICs)

Product Features

I Eight IEEE 802.3-compliant 10BASE-T or I MDIO sectionalization into 2x4 or 1x8

100BASE-TX ports with integrated filters. configurations.

I 100BASE-FX fiber-optic capability on all I Supports both auto-negotiation systems and

ports.

I 2.5V operation.

legacy systems without auto-negotiation

capability.

I Robust baseline wander correction.

I Low power consumption; 250 mW per port

typical.

I Configurable via MDIO port or external

control pins.

I Multiple RMII or SMII/SS-SMII ports for

independent PHY port operation.

I JTAG boundary scan.

I Auto MDIX crossover capabilities.

I 208-pin PQFP: LXT9785HC,

LXT9785EHC, LXT9785HE.

I Proprietary Optimal Signal Processing™

architecture improves SNR by 3 dB over

ideal analog filters.

I 241-ball BGA: LXT9785BC,

LXT9785EBC.

I Optimized for dual-high stacked RJ-45

I DTE detection for remote powering

applications.

applications (LXT9785E only).

o

I Extended temperature operation of -40 C to

o

+85 C (LXT9785HE).

Order Number: 249241-005

January 2002

Information in this document is provided in connection with Intel^®products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The LXT9785/9785E may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

2

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

1.0 Pin Assignments and Signal Descriptions ...............................................................................12

1.1 Signal Name Conventions ..................................................................................................39

2.0 Functional Description................................................................................................................52

2.1

2.2

Introduction.........................................................................................................................52

2.1.1 OSP™ Architecture ...............................................................................................52

2.1.2 Comprehensive Functionality ................................................................................52

2.1.2.1 Sectionalization......................................................................................53

Interface Descriptions.........................................................................................................53

2.2.1 10/100 Network Interface.......................................................................................53

2.2.1.1 Twisted-Pair Interface............................................................................54

2.2.1.2 MDI Crossover (MDIX)...........................................................................54

2.2.1.3 Fiber Interface........................................................................................55

Media Independent Interface (MII) Interfaces.....................................................................55

2.3.1 Global MII Mode Select .........................................................................................55

2.3.2 Internal Loopback ..................................................................................................55

2.3.3 RMII Data Interface................................................................................................56

2.3.4 Serial Media Independent Interface (SMII) and Source

2.3

Synchronous- Serial Media Independent Interface (SS-SMII)...............................56

2.3.4.1 SMII Interface.........................................................................................56

2.3.4.2 Source Synchronous-Serial Media Independent Interface ....................56

2.3.5 Configuration Management Interface ....................................................................56

2.3.6 MII Isolate ..............................................................................................................57

2.3.6.1 MDIO Management Interface.................................................................57

2.3.6.2 MII Sectionalization................................................................................58

2.3.6.3 MII Interrupts..........................................................................................58

2.3.6.4 Global Hardware Control Interface ........................................................59

Operating Requirements.....................................................................................................59

2.4.1 Power Requirements .............................................................................................59

2.4.2 Clock/SYNC Requirements....................................................................................59

2.4.2.1 Reference Clock ....................................................................................59

2.4.2.2 TxCLK Signal (SS-SMII only).................................................................60

2.4.2.3 TxSYNC Signal (SMII/SS-SMII).............................................................60

2.4.2.4 RxSYNC Signal (SS-SMII only) .............................................................60

2.4.2.5 RxCLK Signal (SS-SMII only) ................................................................60

Initialization.........................................................................................................................60

2.5.1 MDIO Control Mode...............................................................................................60

2.5.2 Hardware Control Mode.........................................................................................60

2.5.3 Power-Down Mode ................................................................................................61

2.5.3.1 Global (Hardware) Power Down ............................................................62

2.5.3.2 Port (Software) Power Down .................................................................62

2.5.4 Reset .....................................................................................................................62

2.5.5 Hardware Configuration Settings...........................................................................63

Link Establishment..............................................................................................................63

2.6.1 Auto-Negotiation ....................................................................................................63

2.6.1.1 Base Page Exchange ............................................................................63

2.6.1.2 Next Page Exchange .............................................................................63

2.4

2.5

2.6

Datasheet

3

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

2.6.1.3 Controlling Auto-Negotiation..................................................................64

2.6.1.4 Link Criteria............................................................................................64

2.6.1.5 Parallel Detection...................................................................................64

2.6.1.6 Reliable Link Establishment while Auto MDIX is

Enabled in Forced Speed Mode ............................................................65

2.7

Serial MII Operation............................................................................................................65

2.7.1 SMII Reference Clock............................................................................................69

2.7.2 TxSYNC Pulse (SMII/SS-SMII)..............................................................................69

2.7.3 Transmit Data Stream............................................................................................69

2.7.3.1 Transmit Enable.....................................................................................69

2.7.3.2 Transmit Error........................................................................................69

2.7.4 Receive Data Stream.............................................................................................70

2.7.4.1 Carrier Sense.........................................................................................70

2.7.4.2 Receive Data Valid ................................................................................70

2.7.4.3 Receive Error.........................................................................................70

2.7.4.4 Receive Status Encoding.......................................................................70

2.7.5 Collision ................................................................................................................. 70

2.7.5.1 Source Synchronous-Serial Media Independent Interface ....................72

RMII Operation ...................................................................................................................76

2.8.1 RMII Reference Clock............................................................................................76

2.8.2 Transmit Enable.....................................................................................................76

2.8.3 Carrier Sense & Data Valid....................................................................................76

2.8.4 Receive Error.........................................................................................................76

2.8.5 Out-of-Band Signalling...........................................................................................76

2.8.6 4B/5B Coding Operations......................................................................................76

100 Mbps Operation ...........................................................................................................80

2.9.1 100BASE-X Network Operations...........................................................................80

2.9.2 100BASE-X Protocol Sublayer Operations............................................................80

2.9.2.1 PCS Sublayer ........................................................................................80

2.9.3 PMA Sublayer........................................................................................................82

2.9.3.1 Twisted-Pair PMD Sublayer...................................................................84

2.9.3.2 Fiber PMD Sublayer...............................................................................84

2.8

2.9

2.10 10 Mbps Operation .............................................................................................................85

2.10.1 Preamble Handling ................................................................................................85

2.10.2 Dribble Bits ............................................................................................................85

2.10.3 Link Test ................................................................................................................85

2.10.3.1 Link Failure ............................................................................................86

2.10.4 Jabber....................................................................................................................86

2.11 DTE Discovery Process......................................................................................................86

2.11.1 Definitions..............................................................................................................87

2.11.2 Interaction between Processor, MAC and PHY.....................................................87

2.11.3 Management Interface and Control .......................................................................88

2.11.4 DTE Discovery Process Flow ................................................................................89

2.12 Monitoring Operations ........................................................................................................92

2.12.1 Monitoring Auto-Negotiation ..................................................................................92

2.12.2 Per-Port LED Driver Functions ..............................................................................92

2.12.3 Out-of-Band Signalling...........................................................................................93

2.12.4 Boundary Scan Interface .......................................................................................94

2.12.5 State Machine........................................................................................................94

2.12.6 Instruction Register................................................................................................94

2.12.7 Boundary Scan Register........................................................................................94

4

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

3.0 Application Information ..............................................................................................................95

3.1

3.2

Design Recommendations..................................................................................................95

General Design Guidelines.................................................................................................95

3.2.1 Power Supply Filtering...........................................................................................95

3.2.2 Power and Ground Plane Layout Considerations..................................................96

3.2.2.1 Chassis Ground .....................................................................................96

3.2.3 MII Terminations ....................................................................................................96

3.2.4 Twisted-Pair Interface............................................................................................96

3.2.4.1 Magnetic Requirements .........................................................................97

3.2.5 The Fiber Interface ................................................................................................97

3.2.6 LED Circuit.............................................................................................................98

Typical Application Circuits.................................................................................................99

3.3

4.0 Test Specifications....................................................................................................................104

5.0 Register Definitions...................................................................................................................129

6.0 Package Specifications.............................................................................................................147

Ordering Information 150

Datasheet

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

Figures

1

2

3

4

5

6

7

8

9

LXT9785/9785E Block Diagram .................................................................................................11

LXT9785/9785E RMII 208-Pin PQFP Assignments ...................................................................12

LXT9785/9785E SMII 208-Pin PQFP Assignments ...................................................................13

LXT9785/9785E SS-SMII 208-Pin PQFP Assignments .............................................................14

LXT9785/9785E RMII 241-Ball PBGA Assignments ..................................................................15

LXT9785/9785E SMII 241-Ball PBGA Assignments ..................................................................16

LXT9785/9785E SS-SMII 241-Ball PBGA Assignments ............................................................17

LXT9785/9785E Interfaces.........................................................................................................54

Internal Loopback.......................................................................................................................56

10 Management Interface Read Frame Structure...........................................................................57

11 Management Interface Write Frame Structure ...........................................................................57

12 Port Address Scheme.................................................................................................................58

13 Interrupt Logic.............................................................................................................................59

14 Initialization Sequence................................................................................................................61

15 Auto-Negotiation Operation........................................................................................................65

16 Typical SMII Interface Diagram ..................................................................................................67

17 Typical SMII Quad Sectionalization Diagram .............................................................................68

18 100 Mbps Serial MII Data Flow ..................................................................................................69

19 Serial MII Transmit Synchronization...........................................................................................70

20 Serial MII Receive Synchronization............................................................................................71

21 Typical SS-SMII Interface Diagram ............................................................................................73

22 Typical SS-SMII Quad Sectionalization Diagram .......................................................................74

23 SS-SMII Transmit Timing ...........................................................................................................75

24 SS-SMII Receive Timing ............................................................................................................75

25 RMII Data Flow...........................................................................................................................77

26 Typical RMII Interface Diagram ..................................................................................................78

27 Typical RMII Quad Sectionalization Diagram .............................................................................79

28 100BASE-X Frame Format.........................................................................................................80

29 Protocol Sublayers .....................................................................................................................81

30 Typical IP Telephone System Connection..................................................................................86

31 LXT9785E Negotiation Flow Chart.............................................................................................91

32 LED Pulse Stretching .................................................................................................................93

33 RMII Programmable Out-of-Bank Signaling ...............................................................................93

34 LED Circuit .................................................................................................................................98

35 Power and Ground Supply Connections ....................................................................................99

36 Typical Twisted-Pair Interface ..................................................................................................100

37 Typical LXT9785/9785E to 3.3V Fiber Transceiver Interface Circuitry.....................................101

38 Typical LXT9785/9785E to 5V Fiber Transceiver Interface Circuitry........................................102

39 ON Semiconductor Triple PECL-to-LVPECL Translator ..........................................................103

40 SMII - 100BASE-TX Receive Timing........................................................................................108

41 SMII - 100BASE-TX Transmit Timing.......................................................................................109

42 SMII - 100BASE-FX Receive Timing........................................................................................110

43 SMII - 100BASE-FX Transmit Timing.......................................................................................111

44 SMII - 10BASE-T Receive Timing ............................................................................................112

45 SMII - 10BASE-T Transmit Timing ...........................................................................................113

46 SS-SMII - 100BASE-TX Receive Timing..................................................................................114

47 SS-SMII - 100BASE-TX Transmit Timing.................................................................................115

48 SS-SMII - 100BASE-FX Receive Timing..................................................................................116

49 SS-SMII - 100BASE-FX Transmit Timing.................................................................................117

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Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

50 SS-SMII - 10BASE-T Receive Timing ......................................................................................118

51 SS-SMII - 10BASE-T Transmit Timing .....................................................................................119

52 RMII - 100BASE-TX Receive Timing........................................................................................120

53 RMII - 100BASE-TX Transmit Timing.......................................................................................121

54 RMII - 100BASE-FX Receive Timing........................................................................................122

55 RMII - 100BASE-FX Transmit Timing.......................................................................................123

56 RMII - 10BASE-T Receive Timing ............................................................................................124

57 RMII - 10BASE-T Transmit Timing ...........................................................................................125

58 Auto-Negotiation and Fast Link Pulse Timing...........................................................................126

59 Fast Link Pulse Timing .............................................................................................................126

60 MDIO Write Timing (MDIO Sourced by MAC) ..........................................................................127

61 MDIO Read Timing (MDIO Sourced by PHY)...........................................................................127

62 Power-Up Timing......................................................................................................................128

63 Reset Recovery Timing ............................................................................................................128

64 PHY Identifier Bit Mapping........................................................................................................132

65 LXT9785/9785E 208-Pin PQFP Plastic Package Specification................................................147

66 LXT9785/9785E 241-Ball PBGA Package Specs - Top/Side View(LXT9785BC) ....................148

67 LXT9785/9785E 241-Ball PBGA Package Specs - Bottom View (LXT9785BC) ......................149

68 Ordering Information - Sample .................................................................................................150

Tables

1

RMII PQFP Pin List.....................................................................................................................18

2

3

4

6

5

7

8

9

SMII PQFP Pin List.....................................................................................................................25

SS-SMII PQFP Pin List...............................................................................................................32

LXT9785/9785E RMII Signal Descriptions .................................................................................39

LXT9785/9785E SMII Specific Signal Descriptions....................................................................41

LXT9785/9785E SMII / SS-SMII Common Signal Descriptions..................................................41

LXT9785/9785E SS-SMII Specific Signal Descriptions..............................................................42

MDIO Control Interface Signals..................................................................................................43

LXT9785/9785E Signal Detect ...................................................................................................44

10 LXT9785/9785E Network Interface Signal Descriptions.............................................................44

11 LXT9785/9785E JTAG Test Signal Descriptions........................................................................45

12 LXT9785/9785E Miscellaneous Signal Descriptions ..................................................................46

13 LXT9785/9785E LED Signal Descriptions..................................................................................48

14 LXT9785/9785E Power Supply Signal Descriptions...................................................................49

15 Unused / Reserved Pins.............................................................................................................51

16 MDIX Selection...........................................................................................................................55

17 MII Mode Select..........................................................................................................................55

18 Global Hardware Configuration Settings ....................................................................................63

19 SMII Signal Summary.................................................................................................................66

20 RX Status Encoding Bit Definitions.............................................................................................71

21 SS-SMII .....................................................................................................................................72

22 4B/5B Coding..............................................................................................................................82

23 Next Page Message #5 Code Word Definitions .........................................................................90

24 BSR Mode of Operation..............................................................................................................94

25 Supported JTAG Instructions......................................................................................................94

26 Magnetics Requirements............................................................................................................97

27 Absolute Maximum Ratings......................................................................................................104

28 Operating Conditions................................................................................................................104

Datasheet

7

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

29 Digital I/O DC Electrical Characteristics (VCCIO = 2.5V +/- 5%) .............................................105

30 Digital I/O DC Electrical Characteristics (VCCIO = 3.3V +/- 5%) .............................................106

31 Required Clock Characteristics ................................................................................................106

32 100BASE-TX Transceiver Characteristics................................................................................106

33 100BASE-FX Transceiver Characteristics................................................................................107

34 10BASE-T Transceiver Characteristics....................................................................................107

35 SMII - 100BASE-TX Receive Timing Parameters ....................................................................108

36 SMII - 100BASE-TX Transmit Timing Parameters ...................................................................109

37 SMII - 100BASE-FX Receive Timing Parameters ....................................................................110

38 SMII - 100BASE-FX Transmit Timing Parameters ...................................................................111

39 SMII - 10BASE-T Receive Timing Parameters.........................................................................112

40 SMII-10BASE-T Transmit Timing Parameters..........................................................................113

41 SS-SMII - 100BASE-TX Receive Timing Parameters ..............................................................114

42 SS-SMII - 100BASE-TX Transmit Timing.................................................................................115

43 SS-SMII - 100BASE-FX Receive Timing Parameters ..............................................................116

44 SS-SMII - 100BASE-FX Transmit Timing Parameters .............................................................117

45 SS-SMII - 10BASE-T Receive Timing Parameters...................................................................118

46 SS-SMII - 10BASE-T Transmit Timing Parameters..................................................................119

47 RMII - 100BASE-TX Receive Timing Parameters ....................................................................120

48 RMII - 100BASE-TX Transmit Timing Parameters...................................................................121

49 RMII - 100BASE-FX Receive Timing Parameters ....................................................................122

50 RMII - 100BASE-FX Transmit Timing Parameters...................................................................123

51 RMII - 10BASE-T Receive Timing Parameters ........................................................................124

52 RMII - 10BASE-T Transmit Timing Parameters .......................................................................125

53 Auto-Negotiation and Fast Link Pulse Timing Parameters.......................................................126

54 MDIO Timing Parameters.........................................................................................................127

55 Power-Up Timing Parameters .................................................................................................128

56 Reset Recovery Timing Parameters.........................................................................................128

57 Register Set..............................................................................................................................129

58 Control Register (Address 0)....................................................................................................130

59 Status Register (Address 1) .....................................................................................................131

60 PHY Identification Register 1 (Address 2)................................................................................132

61 PHY Identification Register 2 (Address 3)................................................................................132

62 Auto-Negotiation Advertisement Register (Address 4)6...........................................................133

63 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ...................................134

64 Auto-Negotiation Expansion (Address 6) .................................................................................135

65 Auto-Negotiation Next Page Transmit Register (Address 7)....................................................135

66 Auto-Negotiation Link Partner Next Page Receive Register (Address 8).................................136

67 Port Configuration Register (Address 16, Hex 10) ...................................................................137

68 Quick Status Register (Address 17, Hex 11)............................................................................138

69 Interrupt Enable Register (Address 18, Hex 12).......................................................................139

70 Interrupt Status Register (Address 19, Hex 13)........................................................................140

71 LED Configuration Register (Address 20, Hex 14)...................................................................141

72 Receive Error Count Register (Address 21).............................................................................142

73 RMII Out-of-Band Signalling Register (Address 25).................................................................143

74 Trim Enable Register (Address 27) ..........................................................................................144

75 Trim Status Register (Address 28) ...........................................................................................144

76 Register Bit Map.......................................................................................................................145

77 LXT9785/9785E 241-Ball PBGA Package Dimensions............................................................149

78 Product Information ..................................................................................................................150

8

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

Revision History

Date

Revision

Page

Description

Added bullet to Product Features

1

Modified Table 12 “LXT9785/9785E Miscellaneous Signal

Descriptions” (Added FIFOSEL1 and FIFOSEL0)

46

65

Added Section 2.6.1.6, “Reliable Link Establishment while Auto

MDIX is Enabled in Forced Speed Mode”

Modified Figure 37 “Typical LXT9785/9785E to 3.3V Fiber

Transceiver Interface Circuitry”

101

102

103

Added Figure 38 “Typical LXT9785/9785E to 5V Fiber Transceiver

Interface Circuitry”

Added Figure 39 “ON Semiconductor Triple PECL-to-LVPECL

Translator”

104

Modified Table 27 “Absolute Maximum Ratings”

Modified Table 28 “Operating Conditions”

January 2002

005

Modified Table 30 “Digital I/O DC Electrical Characteristics (VCCIO

= 3.3V +/- 5%)” (Output low voltage SD pins - Max)

106

120

122

124

137

Modified Figure 52 “RMII - 100BASE-TX Receive Timing” and

Table 47 “RMII - 100BASE-TX Receive Timing Parameters”

Modified Figure 54 “RMII - 100BASE-FX Receive Timing” and

Table 49 “RMII - 100BASE-FX Receive Timing Parameters”

Modified Figure 56 “RMII - 10BASE-T Receive Timing” and

Table 51 “RMII - 10BASE-T Receive Timing Parameters”

Modified Table 67 “Port Configuration Register (Address 16, Hex

10)” (Bits 16.5 and 16.6)

139

150

Modified Table 69 “Interrupt Enable Register (Address 18, Hex 12)”

Added product ordering table and diagram.

Datasheet

9

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Contents

Date

Revision

Page

Description

1

Modified and added new language to front page.

Reset: Modified language in first paragraph.

Added new section on DTE discovery.

62

87

Supported JTAG Instructions table: replaced long hit streams with

hex.

94

98

LED Circuit: Modified paragraph language.

LED Circuit diagram: Modified diagram.

Replaced Typical Fiber Interface diagram.

100

Required Clock Characteristics table: Replaced SMII Input

frequency and RMII Input frequency symbol with “f”.

103

123

April 2001

003

Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP

burst width under Typ = 2.

127

129

132

134

142

147

Control Register table: Modified table and tablenotes.

PHY Identification Register 2 (Address 3): Modified table.

PHY Identifier Bit Mapping: Modified diagram.

Auto-Negotiation Expansion: Modified table and tablenotes.

Port Configuration Register table: Modified table and tablenotes.

Trim Enable Register: Modified table (DTE Discovery).

Modified Register Bit Map table.

10

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 1. LXT9785/9785E Block Diagram

8-Port Global

Functions

RMII/SMII Contr

ADD_<4:0>

Management /

Mode Select

Logic & LED

Drivers

RESET

MDIO

PWRDN

2

MDC

Clock

Generator

REFCLK

2

MDINT

2

SYNC (SMII only)

Register Set

+

Manchester

Encoder

10

TP

Driver

Pulse

Shaper

TxDatan

TP /

Fiber

Out

TPFOPn

TPFONn

Parallel/Serial

Converter

Scrambler

& Encoder

100

-

+

ECL

Driver

Auto

Negotiation

Mgmt

Counters

CIM

-

Fiber

select n

Register Set

+

Media

Select

Clock Generator

Adaptive EQ with BL

Wander Cancellation

100TX

100FX

10BT

Port LED

Drivers

-

3

LEDn_<2:0>

RxDatan

+

Manchester

TPFIPn

TPFINn

TP /

Fiber In

Serial to

Parallel

Converter

10

Decoder

Slicer

-

Decoder &

Descrambler

100

Carrier Sense

Data Valid

+

Error Detect

-

Per-Port Functions

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

Datasheet

11

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

1.0

Pin Assignments and Signal Descriptions

Figure 2. LXT9785/9785E RMII 208-Pin PQFP Assignments

CRS_DV6..... 1

RxER6 ..... 2

TxEN6..... 3

TxData6_0 ..... 4

TxData6_1 ..... 5

REFCLK1..... 6

RxData5_1..... 7

RxData5_0..... 8

GNDIO..... 9

CRS_DV5..... 10

RxER5 ..... 11

TxEN5..... 12

TxData5_0 ..... 13

TxData5_1 ..... 14

RxData4_1..... 15

RxData4_0..... 16

CRS_DV4..... 17

VCCIO ..... 18

156 .......TPFIN7

155 .......GNDR7

154 .......TPFOP7

153 .......TPFON7

152 .......VCCT6/7

151 .......TPFON6

150 .......TPFOP6

149 .......GNDR6

148 .......GNDT6/7

147 .......TPFIN6

146 .......TPFIP6

145 .......VCCR6

144 .......VCCR5

143 .......TPFIP5

142 .......TPFIN5

141 .......GNDR5

140 .......TPFOP5

139 .......TPFON5

138 .......VCCT4/5

137 .......TPFON4

136 .......TPFOP4

135 .......GNDR4

134 .......GNDT4/5

133 .......TPFIN4

132 .......TPFIP4

131 .......VCCR4

130 .......VCCR3

129 .......TPFIP3

128 .......TPFIN3

127 .......GNDT2/3

126 .......GNDR3

125 .......TPFOP3

124 .......TPFON3

123 .......VCCT2/3

122 .......TPFON2

121 .......TPFOP2

120 .......GNDR2

119 .......TPFIN2

118 .......TPFIP2

117 .......VCCR2

116 .......VCCR1

115 .......TPFIP1

114 .......TPFIN1

113 .......GNDT0/1

112 .......GNDR1

111 .......TPFOP1

110 .......TPFON1

109 .......VCCT0/1

108 .......TPFON0

107 .......TPFOP0

106 .......GNDR0

105 .......TPFIN0

GNDIO..... 19

RxER4 ..... 20

TxEN4..... 21

TxData4_0 ..... 22

TxData4_1 ..... 23

MDC1 ..... 24

Part #

LOT #

FPO #

LXT9785/9785E XX

XXXXXX

XXXXXXXX

Rev #

MDIO1 ..... 25

MDINT1..... 26

RxData3_1..... 27

RxData3_0..... 28

VCCIO ..... 29

GNDIO..... 30

CRS_DV3..... 31

RxER3 ..... 32

TxEN3..... 33

TxData3_0 ..... 34

TxData3_1 ..... 35

RxData2_1..... 36

RxData2_0..... 37

GNDIO..... 38

CRS_DV2..... 39

RxER2 ..... 40

TxEN2..... 41

TxData2_0 ..... 42

TxData2_1 ..... 43

REFCLK0..... 44

RxData1_1..... 45

RxData1_0..... 46

VCCIO ..... 47

GNDIO..... 48

CRS_DV1..... 49

xER1/PAUSE..... 50

TxEN1..... 51

TxData1_0 ..... 52

12

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 3. LXT9785/9785E SMII 208-Pin PQFP Assignments

N/C..... 1

N/C..... 2

N/C..... 3

156 .......TPFIN7

155 .......GNDR7

154 .......TPFOP7

153 .......TPFON7

152 .......VCCT6/7

151 .......TPFON6

150 .......TPFOP6

149 .......GNDR6

148 .......GNDT6/7

147 .......TPFIN6

146 .......TPFIP6

145 .......VCCR6

144 .......VCCR5

143 .......TPFIP5

142 .......TPFIN5

141 .......GNDR5

140 .......TPFOP5

139 .......TPFON5

138 .......VCCT4/5

137 .......TPFON4

136 .......TPFOP4

135 .......GNDR4

134 .......GNDT4/5

133 .......TPFIN4

132 .......TPFIP4

131 .......VCCR4

130 .......VCCR3

129 .......TPFIP3

128 .......TPFIN3

127 .......GNDT2/3

126 .......GNDR3

125 .......TPFOP3

124 .......TPFON3

123 .......VCCT2/3

122 .......TPFON2

121 .......TPFOP2

120 .......GNDR2

119 .......TPFIN2

118 .......TPFIP2

117 .......VCCR2

116 .......VCCR1

115 .......TPFIP1

114 .......TPFIN1

113 .......GNDT0/1

112 .......GNDR1

111 .......TPFOP1

110 .......TPFON1

109 .......VCCT0/1

108 .......TPFON0

107 .......TPFOP0

106 .......GNDR0

105 .......TPFIN0

TxData6 ..... 4

N/C..... 5

REFCLK1..... 6

N/C..... 7

RxData5..... 8

GNDIO..... 9

N/C..... 10

N/C..... 11

N/C..... 12

TxData5 ..... 13

N/C..... 14

N/C..... 15

RxData4..... 16

N/C..... 17

VCCIO..... 18

GNDIO..... 19

N/C..... 20

N/C..... 21

TxData4 ..... 22

N/C..... 23

MDC1 ..... 24

MDIO1..... 25

MDINT1..... 26

N/C..... 27

RxData3..... 28

VCCIO..... 29

GNDIO..... 30

N/C..... 31

Rev #

Part #

LOT #

FPO #

LXT9785/9785E XX

XXXXXX

XXXXXXXX

N/C..... 32

N/C..... 33

TxData3 ..... 34

SYNC0..... 35

N/C..... 36

RxData2..... 37

GNDIO..... 38

N/C..... 39

N/C..... 40

N/C..... 41

TxData2 ..... 42

N/C..... 43

REFCLK0..... 44

N/C..... 45

RxData1..... 46

VCCIO..... 47

GNDIO..... 48

N/C..... 49

PAUSE..... 50

N/C..... 51

TxData1 ..... 52

Datasheet

13

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 4. LXT9785/9785E SS-SMII 208-Pin PQFP Assignments

N/C..... 1

N/C..... 2

N/C..... 3

156 .......TPFIN7

155 .......GNDR7

154 .......TPFOP7

153 .......TPFON7

152 .......VCCT6/7

151 .......TPFON6

150 .......TPFOP6

149 .......GNDR6

148 .......GNDT6/7

147 .......TPFIN6

146 .......TPFIP6

145 .......VCCR6

144 .......VCCR5

143 .......TPFIP5

142 .......TPFIN5

141 .......GNDR5

140 .......TPFOP5

139 .......TPFON5

138 .......VCCT4/5

137 .......TPFON4

136 .......TPFOP4

135 .......GNDR4

134 .......GNDT4/5

133 .......TPFIN4

132 .......TPFIP4

131 .......VCCR4

130 .......VCCR3

129 .......TPFIP3

128 .......TPFIN3

127 .......GNDT2/3

126 .......GNDR3

125 .......TPFOP3

124 .......TPFON3

123 .......VCCT2/3

122 .......TPFON2

121 .......TPFOP2

120 .......GNDR2

119 .......TPFIN2

118 .......TPFIP2

117 .......VCCR2

116 .......VCCR1

115 .......TPFIP1

114 .......TPFIN1

113 .......GNDT0/1

112 .......GNDR1

111 .......TPFOP1

110 .......TPFON1

109 .......VCCT0/1

108 .......TPFON0

107 .......TPFOP0

106 .......GNDR0

105 .......TPFIN0

TxData6 ..... 4

N/C..... 5

REFCLK1..... 6

RxData5..... 7

N/C..... 8

GNDIO..... 9

N/C..... 10

N/C..... 11

N/C..... 12

TxData5 ..... 13

N/C..... 14

RxData4..... 15

N/C..... 16

RxSYNC1 ..... 17

VCCIO ..... 18

GNDIO..... 19

N/C..... 20

RxCLK1..... 21

TxData4 ..... 22

N/C..... 23

MDC1 ..... 24

MDIO1 ..... 25

MDINT1..... 26

RxData3..... 27

N/C..... 28

VCCIO ..... 29

GNDIO..... 30

N/C..... 31

TxCLK0 ..... 32

N/C..... 33

TxData3 ..... 34

TxSYNC0 ..... 35

RxData2..... 36

N/C..... 37

GNDIO..... 38

N/C..... 39

Rev #

Part #

LOT #

FPO #

LXT9785/9785E XX

XXXXXX

XXXXXXXX

N/C..... 40

N/C..... 41

TxData2 ..... 42

N/C..... 43

REFCLK0..... 44

RxData1..... 45

N/C..... 46

VCCIO ..... 47

GNDIO..... 48

N/C..... 49

PAUSE..... 50

N/C..... 51

TxData1 ..... 52

14

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 5. LXT9785/9785E RMII 241-Ball PBGA Assignments

RMI

I

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

RxData

1_0

TxData

2_1

CRS_D

V2

TxData

3_1

TxData

4_0

RxData

4_0

TxData

6_1

A

B

C

D

E

F

GNDD

VCCIO

TxEN3

VCCIO

GNDD

MDIO1

RxER4

TxEN5

RxER5

RxER6

A

B

RxData

0_1

RxData

1_1

TxData

2_0

RxData

2_0

CRS_D

V3

RxData

3_1

CRS_D

V4

TxData

5_0

RxData

5_0

RxData

5_1

CRS_

DV6

RXD6_

1

TxEN1

GNDD

TXD1_0

GNDD

MDC1

TxEN4

VCCIO

RXD0_

0

CRS_D

V1

RxData

2_1

TxData

4_1

RxData

4_1

RxData

6_0

TxData

7_1

VCCIO

GNDD

TxEN2

GNDD

RxER3

MDINT1

GNDD

TxEN6

VCCIO

GNDD

RxER7

GNDD

C

D

E

F

RxER0/

MDIX

TxData

1_1

RxER1/

PAUSE

TxData

3_0

RxData

3_0

TxData

5_1

CRS_D

V5

TxData

6_0

RxER2

GNDD

TxEN7

TxData

0_0

CRS_D

V0

REF

CLK0

REF

CLK1

CRS_D

V7

RxData

7_0

MDC0

TxEN0

MDIO0

LED3_2

LED2_2

LED1_2

LED0_1

CFG_2

ADD_2

GNDD

VCCD

N/C

GNDD

VCCD

TXD7_0

TxData

0_1

RXD7_

1

MDINT0

LED2_3

LED1_3

LED0_3

LED3_1

N/C

LED7_3

N/C

LED7_2

LED6_3

LED5_3

LED4_3

LED4_2

G

H

J

LED3_3

N/C

LED7_1

LED6_1

LED5_1

N/C

G

H

J

LED2_1

N/C

GNDD

LED6_2

LED5_2

LED4_1

LED1_1

N/C

VCCD

N/C

VCCD

SGND

AMDIX_

EN

K

L

LED0_2

CFG_3

ADD_3

ADD_0

SD0

K

L

VCC

PECL

VCC

PECL

PWR

DWN

SEC

TION

MODE

SEL_0

MODE

SEL_1

MDDIS

CFG_1

ADD_1

ADD_4

TxSLE

W_1

GND

PECL

GND

PECL

G_FX/

TP

M

N

P

R

T

RESET

TDO

TCK

TMS

SD5

TRST

SD7

M

N

P

R

T

TxSLE

W_0

SD1

SD3

VCCT

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

TDI

SD_2P5

V

SD2

VCCR

GNDR

GNDT

VCCR

GNDT

SD4

SD6

TPFIP

(0)

TPFON(

1)

TPFIP

(2)

TPFIN

(3)

TPFON

(4)

TPFIP

(6)

TPFOP

(7)

TPFIP

(7)

GNDT

TPFIN

(0)

TPFOP

(0)

TPFOP

(1)

TPFIN

(1)

TPFIN

(2)

TPFOP

(2)

TPFON

(3)

TPFIP

(3)

TPFIP

(4)

TPFOP

(4)

TPFOP

(5)

TPFIN

(5)

TPFIN

(6)

TPFOP

(6)

TPFON

(7)

TPFIN

(7)

TPFON

(0)

TPFIP

(1)

TPFON

(2)

TPFOP

(3)

TPFIN

(4)

TPFON

(5)

TPFIP

(5)

TPFON

(6)

U

GNDT

GNDR

GNDT

U

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

Datasheet

15

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 6. LXT9785/9785E SMII 241-Ball PBGA Assignments

SMI

I

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

RxData

1

TxData

4

RxData

4

A

GNDD

VCCIO

N/C

SYNC0

N/C

VCCIO

GNDD

MDIO1

N/C

A

B

TxData

2

RxData

2

TxData

5

RxData

5

B

C

D

E

F

N/C

GNDD

N/C

GNDD

N/C

MDC1

N/C

VCCIO

N/C

SYNC1

N/C

RxData

0

TxData

1

RxData

6

VCCIO

GNDD

PAUSE

GNDD

VCCD

N/C

MDINT1

GNDD

N/C

GNDD

C

D

E

F

TxData

3

RxData

3

TxData

6

MDIX

GNDD

N/C

GNDD

N/C

GNDD

VCCIO

GNDD

N/C

TxData

0

REF

CLK0

REF

CLK1

TxData

7

RxData

7

MDC0

N/C

GNDD

VCCD

GNDD

MDINT0

LED2_3

LED1_3

LED0_3

LED3_1

N/C

MDIO0

LED3_2

LED2_2

LED1_2

LED0_1

CFG_2

ADD_2

N/C

LED7_3

N/C

LED7_2

LED6_3

LED5_3

LED4_3

LED4_2

G

H

J

LED3_3

N/C

LED7_1

LED6_1

LED5_1

N/C

G

H

J

LED2_1

N/C

GNDD

LED6_2

LED5_2

LED4_1

LED1_1

N/C

VCCD

N/C

VCCD

SGND

AMDIX_

EN

K

L

LED0_2

CFG_3

ADD_3

ADD_0

SD0

K

L

VCC

PECL

VCC

PECL

PWR

DWN

SECTIO

N

MODE

SEL_0

MODE

SEL_1

MDDIS

CFG_1

ADD_1

ADD_4

TxSLE

W_1

GND

PECL

GND

PECL

G_FX/

TP

M

N

P

R

T

RESET

TDO

TCK

TMS

SD5

TRST

SD7

M

N

P

R

T

TxSLE

W_0

SD1

SD3

VCCT

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

TDI

SD_2P5

V

SD2

VCCR

GNDR

GNDT

VCCR

GNDT

SD4

SD6

TPFIP

(0)

TPFON(

1)

TPFIP

(2)

TPFIN

(3)

TPFON(

4)

TPFIP

(6)

TPFOP(

7)

TPFIP

(7)

GNDT

TPFIN(0

)

TPFOP(

0)

TPFOP(

1)

TPFIN(1

)

TPFIN(2

)

TPFOP(

2)

TPFON(

3)

TPFIP

(3)

TPFIP

(4)

TPFOP(

4)

TPFOP(

5)

TPFIN

(5)

TPFIN

(6)

TPFOP(

6)

TPFON(

7)

TPFIN(7

)

TPFON(

0)

TPFIP

(1)

TPFON(

2)

TPFOP(

3)

TPFIN

(4)

TPFON(

5)

TPFIP

(5)

TPFON(

6)

U

GNDT

GNDR

GNDT

U

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

16

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 7. LXT9785/9785E SS-SMII 241-Ball PBGA Assignments

SS-

SMI

I

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

TxSYN

C0

TxData

4

A

B

C

D

E

F

GNDD

VCCIO

N/C

VCCIO

GNDD

MDIO1

N/C

A

B

RxData

0

RxData

1

TxData

2

RxData

3

Rx

CLK1

RxSYN

C1

TxData

5

RxData

5

RxData

6

N/C

GNDD

N/C

GNDD

N/C

MDC1

N/C

RxData

0

TxData

1

RxData

2

TxCLK

0

RxData

4

TxSYN

C1

VCCIO

GNDD

N/C

GNDD

PAUSE

GNDD

VCCD

N/C

MDINT1

N/C

VCCIO

N/C

GNDD

N/C

GNDD

N/C

GNDD

C

D

E

F

TxData

3

TxData

6

TxCLK

1

MDIX

TXD0

GNDD

N/C

GNDD

N/C

VCCIO

N/C

Rx

CLK0

RxSYN

C0

REF

CLK0

REF

CLK1

TxData

7

MDC0

GNDD

VCCD

N/C

GNDD

RxData

7

MDINT0

LED2_3

LED1_3

LED0_3

LED3_1

N/C

MDIO0

LED3_2

LED2_2

LED1_2

LED0_1

CFG_2

ADD_2

N/C

LED3_3

N/C

LED7_3

N/C

LED7_2

LED6_3

LED5_3

LED4_3

LED4_2

G

H

J

N/C

LED7_1

LED6_1

LED5_1

N/C

G

H

J

LED2_1

N/C

GNDD

LED6_2

LED5_2

LED4_1

LED1_1

N/C

VCCD

N/C

VCCD

SGND

AMDIX_

EN

K

L

LED0_2

CFG_3

ADD_3

ADD_0

SD0

K

L

VCC

PECL

VCC

PECL

PWR

DWN

SEC

TION

MODE

SEL_0

MODE

SEL_1

MDDIS

CFG_1

ADD_1

ADD_4

TxSLE

W_1

GND

PECL

GND

PECL

G_FX/

TP

M

N

P

R

T

RESET

TDO

TCK

TMS

SD5

TRST

SD7

M

N

P

R

T

TxSLE

W_0

SD1

SD3

VCCT

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

TDI

SD_2P

5V

SD2

VCCR

GNDR

GNDT

VCCR

GNDT

SD4

SD6

TPFIP

(0)

TPFON

(1)

TPFIP

(2)

TPFIN

(3)

TPFON

(4)

TPFIP

(6)

TPFOP

(7)

TPFIP

(7)

GNDT

TPFIN

(0)

TPFOP

(0)

TPFOP

(1)

TPFIN

(1)

TPFIN

(2)

TPFOP

(2)

TPFON

(3)

TPFIP

(3)

TPFIP

(4)

TPFOP

(4)

TPFOP

(5)

TPFIN

(5)

TPFIN

(6)

TPFOP

(6)

TPFON

(7)

TPFIN

(7)

TPFON

(0)

TPFIP

(1)

TPFON

(2)

TPFOP

(3)

TPFIN

(4)

TPFON

(5)

TPFIP

(5)

TPFON

(6)

U

GNDT

GNDR

GNDT

U

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

Datasheet

17

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List

Reference for Full

Description

Symbol

Type¹

1

CRS_DV6

RxER6

O, TS, SL

O, TS, SL, ID

I, ID

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 8 on page 43

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

2

3

TxEN6

4

TxData6_0

TxData6_1

REFCLK1

RxData5_1

RxData5_0

GNDIO

I, ID

5

I, ID

6

I

7

O, TS, ID

O, TS

8

9

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

CRS_DV5

RxER5

O, TS, SL

O, TS, SL, ID

I, ID

TxEN5

TxData5_0

TxData5_1

RxData4_1

RxData4_0

CRS_DV4

VCCIO

I, ID

O, TS,ID

O, TS

O, TS, SL

–

GNDIO

–

RxER4

O, TS, SL, ID

I, ID

TxEN4

TxData4_0

TxData4_1

MDC1

I, ID

I, ST, ID

I/O, TS, SL, IP

OD, TS, SL, IP

O, TS, ID

O, TS

MDIO1

MDINT1

RxData3_1

RxData3_0

VCCIO

–

GNDIO

–

CRS_DV3

RxER3

O, TS, SL

O, TS, SL, ID

I, ID

TxEN3

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

18

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

TxData3_0

TxData3_1

RxData2_1

RxData2_0

GNDIO

I, ID

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 12 on page 46

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 12 on page 46

Table 4 on page 39

Table 8 on page 43

Table 14 on page 49

Table 8 on page 43

O, TS, ID

O, TS

–

CRS_DV2

RxER2

O, TS, SL

O, TS, SL, ID

TxEN2

I, ID

TxData2_0

TxData2_1

REFCLK0

RxData1_1

RxData1_0

VCCIO

I, ID

I

O, TS, ID

O, TS

–

GNDIO

–

CRS_DV1

RxER1/PAUSE

TxEN1

O, TS, SL

O, TS, SL, ID

I, ID

TxData1_0

TxData1_1

RxData0_1

RxData0_0

VCCIO

I, ID

O, TS, ID

O, TS

–

GNDIO

–

CRS_DV0

RxER0/MDIX

TxEN0

O, TS, SL

O, TS, SL, ID

I, ID

TxData0_0

TxData0_1

MDC0

I, ID

I, ST, ID

MDIO0

I/O, TS, SL, IP

VCCD

–

GNDD

–

MDINT0

OD, TS, SL, IP

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

19

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

LED3_3

OD, TS, SO, IP

OD, TS, SL, IP

–

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 12 on page 46

Table 8 on page 43

Table 12 on page 46

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

LED3_2

LED3_1

LED2_3

LED2_2

LED2_1

GNDIO

LED1_3

LED1_2

LED1_1

VCCD

OD, TS, SL, IP

–

GNDD

–

LED0_3

LED0_2

LED0_1

AMDIX_EN

MDDIS

CFG_3

CFG_2

CFG_1

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

TxSLEW_1

TxSLEW_0

SD_2P5V

SD0

OD, TS, SL, IP

I, ST, IP

I, ST, ID

I

SD1

I

VCCPECL

GNDPECL

SD2

–

I

SD3

I

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

20

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

N/C

–

Table 15 on page 51

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

VCCR0

TPFIP0

TPFIN0

GNDR0

TPFOP0

TPFON0

VCCT0/1

TPFON1

TPFOP1

GNDR1

GNDT0/1

TPFIN1

TPFIP1

VCCR1

VCCR2

TPFIP2

TPFIN2

GNDR2

TPFOP2

TPFON2

VCCT2/3

TPFON3

TPFOP3

GNDR3

GNDT2/3

TPFIN3

TPFIP3

VCCR3

VCCR4

TPFIP4

TPFIN4

GNDT4/5

GNDR4

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

21

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

TPFOP4

AO/AI

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 15 on page 51

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

Table 11 on page 45

TPFON4

VCCT4/5

TPFON5

TPFOP5

GNDR5

TPFIN5

TPFIP5

VCCR5

VCCR6

TPFIP6

TPFIN6

GNDT6/7

GNDR6

TPFOP6

TPFON6

VCCT6/7

TPFON7

TPFOP7

GNDR7

TPFIN7

TPFIP7

VCCR7

N/C

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

N/C

–

SD4

I

SD5

I

GNDPECL

VCCPECL

SD6

–

I

SD7

I

TDI

I, ST, IP

O, TS

I, ST, IP

TDO

TMS

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

22

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

TCK

I, ST, ID

Table 11 on page 45

Table 15 on page 51

Table 12 on page 46

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

TRST

I, ST, IP

N/C

–

G_FX/TP

PWRDWN

RESET

Section

ModeSel0

ModeSel1

SGND

I, ST, ID

I, ST, IP

I, ST, ID

–

LED4_1

LED4_2

LED4_3

GNDD

OD, TS, SL, IP

–

VCCD

–

LED5_1

LED5_2

LED5_3

GNDIO

LED6_1

LED6_2

LED6_3

LED7_1

LED7_2

LED7_3

GNDD

OD, TS, SL, IP

–

OD, TS, SL, IP

–

VCCD

–

RxData7_1

RxData7_0

GNDIO

CRS_DV7

RxER7

O, TS, ID

O, TS

–

O, TS, SL

O, TS, SL, ID

I, ID

TxEN7

TxData7_0

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

23

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

204

205

206

207

208

TxData7_1

RxData6_1

RxData6_0

GNDIO

I, ID

Table 4 on page 39

Table 14 on page 49

O, TS, ID

O, TS

–

VCCIO

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

24

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 2. SMII PQFP Pin List

Reference for Full

Description

Symbol

Type¹

1

N/C

–

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 6 on page 41

Table 14 on page 49

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 6 on page 41

Table 15 on page 51

Table 14 on page 49

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 8 on page 43

Table 15 on page 51

Table 6 on page 41

Table 14 on page 49

Table 15 on page 51

2

N/C

–

3

N/C

–

4

TxData6

N/C

I, ID

5

I, ID

6

REFCLK1

N/C

I

7

–

8

RxData5

GNDIO

N/C

O, TS

9

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

–

N/C

–

N/C

–

TxData5

N/C

I, ID

–

N/C

O, TS,ID

RxData4

N/C

O, TS

–

VCCIO

GNDIO

N/C

–

O, TS, SL, ID

N/C

I, ID

TxData4

N/C

I, ID

–

MDC1

MDIO1

MDINT1

N/C

I, ST, ID

I/O, TS, SL, IP

OD, TS, SL, IP

–

RxData3

VCCIO

GNDIO

N/C

O, TS

–

N/C

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

25

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

TxData3

I, ID

Table 5 on page 41

Table 6 on page 41

Table 15 on page 51

Table 6 on page 41

Table 14 on page 49

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 6 on page 41

Table 14 on page 49

Table 15 on page 51

Table 12 on page 46

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 6 on page 41

Table 14 on page 49

Table 15 on page 51

Table 12 on page 46

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 8 on page 43

Table 14 on page 49

Table 8 on page 43

SYNC0

N/C

I, ID

–

RxData2

GNDIO

N/C

O, TS

–

N/C

–

N/C

–

TxData2

N/C

I, ID

–

REFCLK0

N/C

I

–

RxData1

VCCIO

GNDIO

N/C

O, TS

–

PAUSE

N/C

I, ID

–

TxData1

N/C

I, ID

–

N/C

–

RxData0

VCCIO

GNDIO

N/C

O, TS

–

MDIX

N/C

I, ID

–

TxData0

N/C

I, ID

–

MDC0

MDIO0

VCCD

GNDD

MDINT0

I, ST, ID

I/O, TS, SL, IP

–

OD, TS, SL, IP

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

26

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

LED3_3

OD, TS, SO, IP

OD, TS, SL, IP

–

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 12 on page 46

Table 8 on page 43

Table 12 on page 46

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

LED3_2

LED3_1

LED2_3

LED2_2

LED2_1

GNDIO

LED1_3

LED1_2

LED1_1

VCCD

OD, TS, SL, IP

–

GNDD

–

LED0_3

LED0_2

LED0_1

AMDIX_EN

MDDIS

CFG_3

CFG_2

CFG_1

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

TxSLEW_1

TxSLEW_0

SD_2P5V

SD0

OD, TS, SL, IP

I, ST, IP

I, ST, ID

I

SD1

I

VCCPECL

GNDPECL

SD2

–

I

SD3

I

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

27

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

N/C

–

Table 15 on page 51

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

VCCR0

TPFIP0

TPFIN0

GNDR0

TPFOP0

TPFON0

VCCT0/1

TPFON1

TPFOP1

GNDR1

GNDT0/1

TPFIN1

TPFIP1

VCCR1

VCCR2

TPFIP2

TPFIN2

GNDR2

TPFOP2

TPFON2

VCCT2/3

TPFON3

TPFOP3

GNDR3

GNDT2/3

TPFIN3

TPFIP3

VCCR3

VCCR4

TPFIP4

TPFIN4

GNDT4/5

GNDR4

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

28

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

TPFOP4

TPFON4

VCCT4/5

TPFON5

TPFOP5

GNDR5

TPFIN5

TPFIP5

VCCR5

VCCR6

TPFIP6

TPFIN6

GNDT6/7

GNDR6

TPFOP6

TPFON6

VCCT6/7

TPFON7

TPFOP7

GNDR7

TPFIN7

TPFIP7

VCCR7

N/C

AO/AI

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 15 on page 51

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

Table 11 on page 45

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

N/C

–

SD4

I

SD5

I

GNDPECL

VCCPECL

SD6

–

I

SD7

I

TDI

I, ST, IP

O, TS

I, ST, IP

TDO

TMS

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

29

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

TCK

I, ST, ID

Table 11 on page 45

Table 15 on page 51

Table 12 on page 46

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 4 on page 39

Table 6 on page 41

Table 14 on page 49

Table 15 on page 51

Table 5 on page 41

TRST

I, ST, IP

N/C

–

G_FX/TP

PWRDWN

RESET

Section

ModeSel0

ModeSel1

SGND

I, ST, ID

I, ST, IP

I, ST, ID

–

LED4_1

LED4_2

LED4_3

GNDD

OD, TS, SL, IP

–

VCCD

–

LED5_1

LED5_2

LED5_3

GNDIO

LED6_1

LED6_2

LED6_3

LED7_1

LED7_2

LED7_3

GNDD

OD, TS, SL, IP

–

OD, TS, SL, IP

–

VCCD

–

N/C

O, TS, ID

RxData7

GNDIO

N/C

O, TS

–

N/C

–

N/C

–

TxData7

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

30

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

204

205

206

207

208

SYNC1

I, ID

Table 6 on page 41

Table 15 on page 51

Table 6 on page 41

Table 14 on page 49

N/C

–

O, TS

–

RxData6

GNDIO

VCCIO

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

31

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List

Reference for Full

Description

Symbol

Type¹

1

N/C

–

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 5 on page 41

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 7 on page 42

Table 15 on page 51

Table 7 on page 42

Table 14 on page 49

Table 15 on page 51

Table 7 on page 42

Table 5 on page 41

Table 15 on page 51

Table 8 on page 43

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

Table 15 on page 51

Table 7 on page 42

Table 15 on page 51

2

N/C

–

3

N/C

–

4

TxData6

N/C

I, ID

5

I, ID

6

REFCLK1

RxData5

N/C

I

7

O, TS, ID

8

–

9

GNDIO

N/C

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

–

N/C

–

N/C

–

TxData5

N/C

I, ID

–

RxData4

N/C

O, TS, ID

–

RxSYNC1

VCCIO

GNDIO

N/C

O, TS, ID

–

RxCLK1

TxData4

N/C

O, TS, ID

I, ID

–

MDC1

MDIO1

MDINT1

RxData3

N/C

I, ST, ID

I/O, TS, SL, IP

OD, TS, SL, IP

O, TS, ID

–

VCCIO

GNDIO

N/C

–

TxCLK0

N/C

I, ID

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

32

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

TxData3

I, ID

Table 5 on page 41

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 5 on page 41

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

Table 15 on page 51

Table 12 on page 46

Table 15 on page 51

Table 5 on page 41

Table 15 on page 51

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

Table 7 on page 42

Table 12 on page 46

Table 7 on page 42

Table 5 on page 41

Table 15 on page 51

Table 8 on page 43

Table 14 on page 49

Table 8 on page 43

TxSYNC0

RxData2

N/C

I, ID

O, TS, ID

–

GNDIO

N/C

–

N/C

–

N/C

–

TxData2

N/C

I, ID

–

REFCLK0

RxData1

N/C

I

O, TS, ID

–

VCCIO

GNDIO

N/C

–

PAUSE

N/C

I, ID

–

TxData1

N/C

I, ID

–

RxData0

N/C

O, TS, ID

–

VCCIO

GNDIO

RxSYNC0

MDIX

–

O, TS, ID

I, ID

RxCLK0

TxData0

N/C

–

I, ID

–

MDC0

MDIO0

VCCD

GNDD

MDINT0

I, ST, ID

I/O, TS, SL, IP

–

OD, TS, SL, IP

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

33

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

LED3_3

OD, TS, SO, IP

OD, TS, SL, IP

–

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 12 on page 46

Table 8 on page 43

Table 12 on page 46

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

LED3_2

LED3_1

LED2_3

LED2_2

LED2_1

GNDIO

LED1_3

LED1_2

LED1_1

VCCD

OD, TS, SL, IP

–

GNDD

–

LED0_3

LED0_2

LED0_1

AMDIX_EN

MDDIS

CFG_3

CFG_2

CFG_1

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

TxSLEW_1

TxSLEW_0

SD_2P5V

SD0

OD, TS, SL, IP

I, ST, IP

I, ST, ID

I

SD1

I

VCCPECL

GNDPECL

SD2

–

I

SD3

I

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

34

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

N/C

–

Table 15 on page 51

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

VCCR0

TPFIP0

TPFIN0

GNDR0

TPFOP0

TPFON0

VCCT0/1

TPFON1

TPFOP1

GNDR1

GNDT0/1

TPFIN1

TPFIP1

VCCR1

VCCR2

TPFIP2

TPFIN2

GNDR2

TPFOP2

TPFON2

VCCT2/3

TPFON3

TPFOP3

GNDR3

GNDT2/3

TPFIN3

TPFIP3

VCCR3

VCCR4

TPFIP4

TPFIN4

GNDT4/5

GNDR4

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

35

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

TPFOP4

TPFON4

VCCT4/5

TPFON5

TPFOP5

GNDR5

TPFIN5

TPFIP5

VCCR5

VCCR6

TPFIP6

TPFIN6

GNDT6/7

GNDR6

TPFOP6

TPFON6

VCCT6/7

TPFON7

TPFOP7

GNDR7

TPFIN7

TPFIP7

VCCR7

N/C

AO/AI

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 15 on page 51

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

Table 11 on page 45

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

N/C

–

SD4

I

SD5

I

GNDPECL

VCCPECL

SD6

–

I

SD7

I

TDI

I, ST, IP

O, TS

I, ST, IP

TDO

TMS

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

36

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

TCK

I, ST, ID

Table 11 on page 45

Table 15 on page 51

Table 12 on page 46

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

Table 15 on page 51

Table 7 on page 42

Table 15 on page 51

Table 5 on page 41

TRST

I, ST, IP

N/C

–

G_FX/TP

PWRDWN

RESET

Section

ModeSel0

ModeSel1

SGND

I, ST, ID

I, ST, IP

I, ST, ID

–

LED4_1

LED4_2

LED4_3

GNDD

OD, TS, SL, IP

–

VCCD

–

LED5_1

LED5_2

LED5_3

GNDIO

LED6_1

LED6_2

LED6_3

LED7_1

LED7_2

LED7_3

GNDD

OD, TS, SL, IP

–

OD, TS, SL, IP

–

VCCD

–

RxData7

N/C

O, TS, ID

–

GNDIO

N/C

–

TxCLK1

N/C

I, ID

–

TxData7

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

37

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

204

205

206

207

208

TxSYNC1

RxData6

N/C

I, ID

Table 7 on page 42

Table 15 on page 51

Table 14 on page 49

O, TS, ID

–

GNDIO

VCCIO

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

38

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

1.1

Signal Name Conventions

Signal names may contain either a port designation or a serial designation, or a combination of the

two designations. Signal naming conventions are as follows:

• Port Number Only. Individual signals that apply to a particular port are designated by the

Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit

Enable signals would be identified as TxEN0, TxEN1, and TxEN2.

• Serial Number Only. A set of signals which are not tied to any specific port are designated by

the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set

of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.

• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each

signal is designated in the following order: Signal Mnemonic, Port Designation, an

underscore, and the serial designation. For example, a set of three Port Configuration signals

would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and

RxData2_0 and RxData2_1.

Table 4. LXT9785/9785E RMII Signal Descriptions

Pin-Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Reference Clock. 50 MHz RMII reference clock is always required. RMII

inputs are sampled on the rising edge of REFCLK, RMII outputs are

sourced on the falling edge. See “Clock/SYNC Requirements” on page 59

for detailed CLK requirements.

44

6

E6,

E12

REFCLK0

REFCLK1

I

61

62

E2,

F4

TxData0_0

TxData0_1

Transmit Data - Port 0. Inputs containing 2-bit parallel di-bits to be

transmitted from port 0 are clocked in synchronously to REFCLK.

I, ID

52

53

C3,

D4

TxData1_0

TxData1_1

Transmit Data - Port 1. Inputs containing 2-bit parallel di-bits to be

transmitted from port 1 are clocked in synchronously to REFCLK

42

43

B5

A4

TxData2_0

TxData2_1

Transmit Data - Port 2. Inputs containing 2-bit parallel di-bits to be

transmitted from port 2 are clocked in synchronously to REFCLK.

34

35

D8,

A6

TxData3_0

TxData3_1

Transmit Data - Port 3. Inputs containing 2-bit parallel di-bits to be

transmitted from port 3 are clocked in synchronously to REFCLK.

22

23

A11,

C10

TxData4_0

TxData4_1

Transmit Data - Port 4. Inputs containing 2-bit parallel di-bits to be

transmitted from port 4 are clocked in synchronously to REFCLK.

13

14

B13,

D11

TxData5_0

TxData5_1

Transmit Data - Port 5. Inputs containing 2-bit parallel di-bits to be

transmitted from port 5 are clocked in synchronously to REFCLK.

4

5

D13,

A16

TxData6_0

TxData6_1

Transmit Data - Port 6. Inputs containing 2-bit parallel di-bits to be

transmitted from port 6 are clocked in synchronously to REFCLK.

203

204

E14,

C16

TxData7_0

TxData7_1

Transmit Data - Port 7. Inputs containing 2-bit parallel di-bits to be

transmitted from port 7 are clocked in synchronously to REFCLK.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes

and during H/W reset.

Datasheet

39

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 4. LXT9785/9785E RMII Signal Descriptions (Continued)

Pin-Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

60

PBGA

E3,

TxEN0

51

41

33

21

12

3

B2,

C6,

A7,

B11,

A14,

C14,

D16

TxEN1

TxEN2

TxEN3

TxEN4

TxEN5

TxEN6

TxEN7

Transmit Enable - Ports 0-7. Active High input enables respective port

transmitter. This signal must be synchronous to the REFCLK.

I, ID

202

55

54

C2,

B1

RxData0_0

RxData0_1

O, TS

O, TS, ID

Receive Data - Port 0. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

46

45

A3,

B4

RxData1_0

RxData1_1

O, TS

O, TS, ID

Receive Data - Port 1. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

37

36

B6,

C7

RxData2_0

RxData2_1

O, TS

O, TS, ID

Receive Data - Port 2. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

28

27

D9,

B9

RxData3_0

RxData3_1

O, TS

O, TS, ID

Receive Data - Port 3. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

16

15

A13,

C12

RxData4_0

RxData4_1

O, TS

O, TS, ID

Receive Data - Port 4. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

8

7

B14,

B15

RxData5_0

RxData5_1

O, TS

O, TS, ID

Receive Data - Port 5. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

206

205

C15,

B17

RxData6_0

RxData6_1

O, TS

O, TS, ID

Receive Data - Port 6. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

198

197

E16,

F14

RxData7_0

RxData7_1

O, TS

O, TS, ID

Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

58

49

39

31

17

10

1

E4,

C4,

A5,

B8,

B12,

D12,

B16,

E15

CRS_DV0

CRS_DV1

CRS_DV2

CRS_DV3

CRS_DV4

CRS_DV5

CRS_DV6

CRS_DV7

Carrier Sense/Receive Data Valid - Ports 0-7. On detection of valid

carrier, these signals are asserted asynchronously with respect to

REFCLK. CRS_DVn is de-asserted on loss of carrier, synchronous to

REFCLK.

O, TS, SL,

ID

200

59

50

40

32

20

11

2

D2,

D5,

D7,

C8,

A12,

A15,

A17,

D17

RxER0

RxER1

RxER2

RxER3

RxER4

RxER5

RxER6

RxER7

Receive Error - Ports 0-7. These signals are synchronous to the

respective REFCLK. Active High indicates that received code group is

invalid, or that PLL is not locked.

O, TS, SL,

ID

201

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes

and during H/W reset.

40

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 5. LXT9785/9785E SMII / SS-SMII Common Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

61

52

42

34

22

13

4

E2,

C3,

B5,

D8,

A11,

B13,

D13,

E14

TxData0

TxData1

TxData2

TxData3

TxData4

TxData5

TxData6

TxData7

Transmit Data - Ports 0-7. These serial input streams provide data to be

transmitted to the network. The LXT9785/9785E clocks the data in

synchronously to REFCLK.

I, ID

203

Reference Clock. The LXT9785/9785E always requires a 125 MHz reference

clock input. Refer to Functional Description for detailed clock requirements.

REFCLK0 and REFCLK1 are always connected regardless of sectionalization

mode.

E6,

44

6

REFCLK0

REFCLK1

I

E12

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Table 6. LXT9785/9785E SMII Specific Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

SMII Synchronization. The MAC must generate a SYNC pulse every 10

REFCLK cycles to synchronize the SMII. SYNC0 is used when 1x8 port

sectionalization is selected. SYNC0 and SYNC1 are to be used when 2x4

port sectionalization is chosen.

35

204

A6,

C16

SYNC0

SYNC1

I, ID

55

46

37

28

16

8

C2,

A3,

B6,

D9,

A13,

B14,

C15,

E16

RxData0

RxData1

RxData2

RxData3

RxData4

RxData5

RxData6

RxData7

Receive Data - Ports 0-7. These serial output streams provide data received

from the network. The LXT9785/9785E drives the data out synchronously to

REFCLK.

O, TS

206

198

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

3. RxData[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and during H/W reset.

Datasheet

41

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 7. LXT9785/9785E SS-SMII Specific Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

SS-SMII Transmit Synchronization. The MAC must generate a TxSYNC

pulse every 10 TxCLK cycles to mark the start of TxData segments.

TxSYNC0 is used when 1x8 port sectionalization is selected.

35

204

A6,

C16

TxSYNC0

TxSYNC1

I, ID

SS-SMII Receive Synchronization. The LXT9785/9785E generates these

pulses every 10 RxCLK cycles to mark the start of RxData segments for the

MAC. RxSYNC1 is used and RxSYNC0 is tri-stated when 1x8 port

sectionalization is selected. These outputs are only enabled when SS-SMII

mode is enabled.

RxSYNC0

RxSYNC1

58

17

E4,

B12

O, TS,

ID

SS-SMII Transmit Clock. The MAC sources this 125 MHz clock as the

timing reference for TxData and TxSYNC. Only TxCLK0 is used when 1x8

port sectionalization is selected. See “Clock/SYNC Requirements” on page 59 for

detailed clock requirements.

32

201

C8,

D17

TxCLK0

TxCLK1

I, ID

SS-SMII Receive Clock. The LXT9785/9785E generates these clocks,

based on REFCLK, to provide a timing reference for RxData and RxSYNC to

the MAC. RxCLK1 used and RxCLK0 is tri-stated when 1x8 port

sectionalization is selected. See “Clock/SYNC Requirements” on page 59 for

detailed clock requirements. These outputs are only enabled when SS-SMII

mode is enabled.

60

21

E3,

B11

RxCLK0

RxCLK1

O, TS,

ID

54

45

36

27

15

7

B1,

B4,

C7,

B9,

C12,

B15,

B17,

F14

RxData0

RxData1

RxData2

RxData3

RxData4

RxData5

RxData6

RxData7

Receive Data - Ports 0-7. These serial output streams provide data received

from the network. The LXT9785/9785E drives the data out synchronously to

REFCLK.

O, TS,

ID

205

197

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are tri-stated in Isolation and H/W Power-Down modes and during H/W

reset.

42

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 8. MDIO Control Interface Signals

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3,4

PQFP

PBGA

Management Data Input/Output. Bidirectional serial data channel for

communication between the PHY and MAC or switch ASIC. Only MDIO0

is used when 1x8 port sectionalization is selected. In 2x4 port

sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses

ports 4-7. Refer to Figure 22 on page 74.

64

25

F3,

A10

MDIO0

MDIO1

I/O, TS, SL,

IP

Management Data Interrupt. When Register bit 18.1 = 1, an active Low

output on this Pin indicates status change. Only MDINT0 is used when 1x8

67

26

F1,

C9

MDINT0

MDINT1

OD,TS, SL, port sectionalization is selected. In 2x4 port sectionalization mode,

IP

MDINT0 is associated with ports 0-3 and MDINT1 is associated with ports

4-7. Refer to Figure 22 on page 74.

Management Data Clock. Clock for the MDIO serial data channel.

Maximum frequency is 20 MHz. Only MDC0 is used when 1x8 port

sectionalization is selected. In 2x4 port sectionalization mode, MDC0

clocks ports 0-3 register accesses and MDC1 clocks ports 4-7 register

accesses. Refer to Figure 22 on page 74.

63

24

E1,

B10

MDC0

MDC1

I, ST, ID

Management Disable. When MDDIS is tied High, the MDIO port is

completely disabled and the Hardware Control Interface pins set their

respective bits at power up and reset.

When MDDIS is pulled Low at power up or reset, via the internal pull-down

resistor or by tieing it to ground, the Hardware Control Interface Pins

control only the initial or “default” values of their respective register bits.

After the power-up/reset cycle is complete, bit control reverts to the MDIO

serial channel.

84

L1

MDDIS

I, ST, ID

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. MDIO[0:1] and MDINT[0:1] outputs are tri-stated in H/W Power-Down mode and during H/W reset.

4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the

register number (0-32) and Y is the bit number (0-15).

Datasheet

43

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 9. LXT9785/9785E Signal Detect

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Signal Detect 2.5 Volt Interface. When the SD interface is at 2.5 V, tie this

input to VCCPECL. Floating this input or tieing it to GNDPECL indicates that

a 3.3 V SD interface is being used.

95

P1

SD_2P5V

I, ST, ID

96

97

P2,

N4,

P3,

N5,

P15,

P16,

P17,

N17

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

Signal Detect - Ports 0-7. The SD inputs are only applicable for ports set in

Fiber mode.

100

101

161

162

165

166

I

When SD is high, the process of searching for receive idles for the purpose of

bring link up is initiated.

If SD is low, link is declared lost.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

3. Tie SD[0:7] inputs to GNDPECL if unused.

Table 10. LXT9785/9785E Network Interface Signal Descriptions

Pin/Ball Designation

Symbol

Type¹

Signal Description

PQFP

PBGA

107, 108

111, 110

121, 122

125, 124

136, 137

140, 139

150, 151

154, 153

T2, U1,

T3, R4,

T6, U5,

U7, T7,

T10, R10,

T11, U11,

T14,U15,

R14, T15

TPFOP0, TPFON0

TPFOP1, TPFON1

TPFOP2, TPFON2

TPFOP3, TPFON3

TPFOP4, TPFON4

TPFOP5, TPFON5

TPFOP6, TPFON6

TPFOP7, TPFON7

Twisted-Pair/Fiber Outputs², Positive & Negative,

Ports 0-7.

During 100BASE-TX or 10BASE-T operation, TPFO pins drive

802.3 compliant pulses onto the line.

AO/AI

During 100BASE-FX operation, TPFO pins produce differential

PECL outputs for fiber transceivers.

104, 105

115, 114

118, 119

129, 128

132, 133

143, 142

146, 147

157, 156

R2, T1,

U3, T4,

R6, T5,

T8, R8,

TPFIP0, TPFIN0

TPFIP1, TPFIN1

TPFIP2, TPFIN2

TPFIP3, TPFIN3

TPFIP4, TPFIN4

TPFIP5, TPFIN5

TPFIP6, TPFIN6

TPFIP7, TPFIN7

Twisted-Pair/Fiber Inputs³, Positive & Negative,

Ports 0-7.

During 100BASE-TX or 10BASE-T operation, TPFI pins receive

differential 100BASE-TX or 10BASE-T signals from the line.

AI/AO

T9, U9,

U13, T12,

R12, T13,

R16, T16

During 100BASE-FX operation, TPFI pins receive differential

PECL inputs from fiber transceivers.

1. Type Column Coding: AI = Analog Input, AO = Analog Output.

2. Switched to Inputs (see TPFIP/N desc.) when not in Fiber mode and MDIX is not active [i.e., Twisted-Pair, non-crossover MDI

mode].

3. Switched to Outputs (see TPFOP/N desc.) when not in Fiber mode and MDIX is not active [i.e., Twisted-Pair, non-crossover

MDI mode].

44

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 11. LXT9785/9785E JTAG Test Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

167

168

169

170

171

N14

N15

N16

M16

M17

TDI

I, ST, IP

O, TS

Test Data Input. Test data sampled with respect to the rising edge of TCK.

Test Data Output. Test data driven with respect to the falling edge of TCK.

Test Mode Select.

TDO

TMS

TCK

I, ST, IP

I, ST, ID

I, ST, IP

Test Clock. Clock input for JTAG test.

TRST

Test Reset. Reset input for JTAG test.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Tri-State-able output, SMT = Schmitt Triggered input, SL

= Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. TDO output is tri-stated in H/W Power-Down mode and during H/W reset.

Datasheet

45

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 12. LXT9785/9785E Miscellaneous Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

Tx Output Slew Controls 0 and 1 Defaults.

These pins are read at startup or reset. Their value at that time is used to

set the default state of Register bits 27.11:10 for all ports. These register

bits can be read and overwritten after startup / reset.

These pins select the TX output slew rate for all ports (rise and fall time)

as follows:

TxSLEW_0

TxSLEW_1

94

93

N3,

M4

I, ST, ID

TxSLEW_1

TxSLEW_0

Slew Rate (Rise and Fall Time)

0

1

0

1

0

1

3.3 ns

3.6 ns

3.9 ns

4.2 ns

Pause Default. This pin is read at startup or reset. Its value at that time is

used to set the default state of Register bit 4.10 for all ports. This register

bit can be read and overwritten after startup / reset.

When High, the LXT9785/9785E advertises Pause capabilities on all

ports during auto-negotiation.

50

D5

PAUSE

I, ID

This pin is shared with RMII-RxER1. An external pull-up resistor (see

applications section for value) can be used to set Pause active while

RxER1 is tri-stated during H/W reset. If no pull-up is used, the default

Pause state is set inactive via the internal pull-down resistor.

Power-Down. When High, forces the LXT9785/9785E into global power-

down mode.

174

175

L14

PWRDWN

RESET

I, ST, ID

I, ST, IP

Pin is not on JTAG chain.

Reset. This active low input is ORed with the control register Reset

Register bit 0.15. When held Low, all outputs are forced to inactive state.

M15

Pin is not on JTAG chain.

Address <4:0>. Sets base address. Each port adds its port number

(starting with 0) to this address to determine its PHY address.

Port 0 Address = Base

88

89

90

91

92

L4,

M2,

M3,

N1,

N2

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

Port 1 Address = Base + 1

Port 2 Address = Base + 2

Port 3 Address = Base + 3

Port 4 Address = Base + 4

Port 5 Address = Base + 5

Port 6 Address = Base + 6

Port 7 Address = Base + 7

I, ST, ID

Mode Select[1:0]

00 = RMII

01 = SMII

10 = SS-SMII

11= Reserved

178

177

L17,

L16

MODESEL_1

MODESEL_0

I, ST, ID

All ports are configured the same. Interfaces cannot be mixed and must

be all RMII, SMII, or SS-SMII.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

46

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 12. LXT9785/9785E Miscellaneous Signal Descriptions (Continued)

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

Sectionalization Select. This pin selects sectionalization into separate

ports.

176

L15

K1

SECTION

I, ST, ID

0 = 1x8 ports,

1 = 2x4 ports

Auto-MDIX Enable Default. This pin is read at startup or reset. Its value

at that time is used to set the default state of Register bit 27.9 for all ports.

These register bits can be read and overwritten after startup / reset. Refer

to Table 16 on page 55.

83

AMDIX_EN

I, ST, IP

When active (high), automatic MDI crossover (MDIX) (regardless of

segmentation) is selected for all ports. When inactive (low) MDIX is

selected according to the MDIX pin.

MDIX Select Default. This pin is read at startup or reset. Its value at that

time is used to set the default state of Register bit 27.8 for all ports. These

register bits can be read and overwritten after startup / reset. Refer to

Table 16 on page 55.

When AMDIX_EN is active this pin is ignored.

When AMDIX_EN is inactive, all ports are forced to the MDI or the MDIX

function regardless of segmentation. If this pin is active (high), MDI

crossover (MDIX) is selected. If this pin is inactive, non-crossover MDI

mode is set.

59

D2

MDIX

I, ID

This pin is shared with RMII-RxER0. An external pull-up resistor (see

applications section for value) can be used to set MDIX active while

RxER0 is tri-stated during H/W reset. If no pull-up is used, the default

MDIX state is set inactive via the internal pull-down resistor. Do not tie this

pin directly to VCCIO (vs. using a pull-up) in non-RMII modes.

Global Port Configuration Defaults 1-3. These pins are read at startup

or reset. Their value at that time is used to set the default state of register

bits shown in Table 18 on page 63 for all ports. These register bits can be

read and overwritten after startup / reset.

85

86

87

L2,

L3,

M1

CFG_3

CFG_2

CFG_1

I, ST, ID

When operating in Hardware Control Mode, these pins provide

configuration control options for all the ports (refer to page 63 for details).

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Datasheet

47

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 12. LXT9785/9785E Miscellaneous Signal Descriptions (Continued)

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

Global FX/TP Enable Default. This pin is read at startup or reset. Its

value at that time is used to set the default state of Register bit 16.0 for all

ports. These register bits can be read and overwritten after startup /

reset. Refer to “Port Configuration Register (Address 16, Hex 10)” on

page 137.

173

M14

G_FX/TP

I, ST, ID

This input selects whether all the ports are defaulted to TP vs. FX mode.

FIFO Select <1:0>: These pins are read at startup or reset. Their value at

that time is used to set the default state of Register bits 18.15:14 for all

ports. These register bits can be read and overwritten after startup/reset.

11

20

A15

A12

FIFOSEL1

FIFOSEL0

These pins are shared with RMII-RxER<5:4>. An external pull-up resistor

(see applications section for value) can be used to set FIFO Select<1:0>

to active while RxER<5:4> are tri-stated during hardware reset. If no pull-

up is used, the default FIFO select state is set via the internal pull-down

resistors.

I, ID

Preamble Select: This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 16.5 for all ports. This

register bit can be read and overwritten after startup/reset.

This pin is shared with RMII-RxER2. An external pull-up resistor (see

applications section for value) can be used to set Preamble Select to

active while RxER2 is tri-stated during hardware reset. If no pull-up is

used, the default Preamble Select state is set via the internal pull-down

resistors.

40

D7

PREASEL

I, ID

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Table 13. LXT9785/9785E LED Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Port 0 LED Drivers 1-3. These pins drive LED indicators for Port 0.

OD, TS, SL, Each LED can display one of several available status conditions as

82

81

80

K3,

K2,

J1

LED0_1

LED0_2

LED0_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

Port 1 LED Drivers 1-3. These pins drive LED indicators for Port 1.

OD, TS, SL, Each LED can display one of several available status conditions as

77

76

75

J4,

J3,

H1

LED1_1

LED1_2

LED1_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

Port 2 LED Drivers 1-3. These pins drive LED indicators for Port 2.

OD, TS, SL, Each LED can display one of several available status conditions as

73

72

71

H2,

H3,

G1

LED2_1

LED2_2

LED2_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. The LED outputs are tri-stated in H/W Power-Down mode and during H/W reset.

4.

48

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

(Continued)

Table 13. LXT9785/9785E LED Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Port 3 LED Drivers 1-3. These pins drive LED indicators for Port 3.

OD, TS, SL, Each LED can display one of several available status conditions as

70

69

68

F2,

G3,

G4

LED3_1

LED3_2

LED3_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

Port 4 LED Drivers 1-3. These pins drive LED indicators for Port 4.

OD, TS, SL, Each LED can display one of several available status conditions as

180

181

182

K16,

K17,

J17

LED4_1

LED4_2

LED4_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

Port 5 LED Drivers 1-3. These pins drive LED indicators for Port 5.

OD, TS, SL, Each LED can display one of several available status conditions as

185

186

187

J15,

J16,

H17

LED5_1

LED5_2

LED5_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

Port 6 LED Drivers 1-3. These pins drive LED indicators for Port 6.

OD, TS, SL, Each LED can display one of several available status conditions as

189

190

191

H15,

H16,

G17

LED6_1

LED6_2

LED6_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

Port 7 LED Drivers 1-3. These pins drive LED indicators for Port 7.

OD, TS, SL, Each LED can display one of several available status conditions as

192

193

194

G15,

F17,

F16

LED7_1

LED7_2

LED7_3

IP

selected by the LED Configuration Register (refer to Table 71 on

page 141 for details).

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. The LED outputs are tri-stated in H/W Power-Down mode and during H/W reset.

4.

Table 14. LXT9785/9785E Power Supply Signal Descriptions

Pin/Ball Designation

Symbol

Type

Signal Description

PQFP

PBGA

65, 78, 184, G13, J14,

VCCD

-

Digital Power Supply - Core. +2.5V supply for core digital circuits.

196

F5, J5

Digital Power Supply - I/O Ring. +2.5/3.3V supply for digital I/O

circuits. The digital input circuits running off of this rail, having a TTL-level

threshold and over-voltage protection, may be interfaced with 3.3/5.0V,

when the IO supply is 3.3V, and 2.5/3.3/5.0V when 2.5V.

A2, A8,

C1, C11,

D14

18, 29, 47,

56, 208

VCCIO

VCCPECL

VCCR

Digital Power Supply - PECL Signal Detect Inputs. +2.5/3.3V supply

for PECL Signal Detect input circuits. If Fiber Mode is not used, tie these

pins to GNDPECL to save power.

98, 164

L13, L5

-

103, 116,

117, 130,

131, 144,

145, 158

N13, P4,

P7, P8,

P9, P10,

P11, P12

Analog Power Supply - Receive. +2.5V supply for all analog receive

circuits.

N6, N7,

N9, N11,

N12

109, 123,

138, 152

Analog Power Supply - Transmit. +2.5V supply for all analog transmit

circuits.

VCCT

Datasheet

49

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 14. LXT9785/9785E Power Supply Signal Descriptions (Continued)

Pin/Ball Designation

Symbol

Type

Signal Description

PQFP

PBGA

A1, A9,

B3, B7,

C5, C13,

C17, D1,

D3, D6,

D10, D15,

66, 79,

183, 195

E5, E7,

Digital Ground. Ground return for core digital supplies (VCCD). All

ground pins can be tied together using a single ground plane.

GNDD

-

E9, E11,

E13, E17,

F13, H8,

H9, H10,

J8, J9,

J10, K8,

K9, K10

9, 19, 30,

38, 48, 57,

74, 188,

GNDIO

-

Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO).

199, 207

Digital GND - PECL Signal Detect Inputs. Ground return for PECL

Signal Detect input circuits.

99, 163

M5, M13

GNDPECL

GNDR

106, 112,

120, 126,

135, 141,

149, 155

P5, P6,

P13, R7,

R9, R11,

R13, U8

Analog Ground - Receive. Ground return for receive analog supply. All

ground pins can be tied together using a single ground plane.

P14, R1,

R3, R5,

R15, R17,

T17, U2,

U4, U6,

U10, U12,

U14, U16,

U17

113, 127,

134, 148

Analog Ground - Transmit. Ground return for transmit analog supply.

All ground pins can be tied together using a single ground plane.

GNDT

SGND

-

Substrate Ground. Ground for chip substrate. All ground pins can be

tied together using a single ground plane.

179

K14

50

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 15. Unused / Reserved Pins

Pin/Ball Designation

Symbol

Type¹

Signal Description

PQFP

PBGA

F15, G2,

G5, G14,

G16, H4,

H14, J2,

J13, K4,

K15

N/C

No Connection.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2.

Datasheet

51

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

2.0

Functional Description

2.1

Introduction

The LXT9785/9785E is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10 Mbps and

100 Mbps networks, complying with all applicable requirements of IEEE 802.3 standards. The

device incorporates a Serial Media Independent Interface (SMII), Source Synchronous-Serial

Media Independent Interface (SS-SMII), and a Reduced Serial Independent Interface (RMII) to

enable each individual network port to interface with multiple 10/100 MACs. Each port directly

drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785/9785E also supports

100BASE-FX operation via a Pseudo-ECL (PECL) interface. The device has a 241-pin BGA or a

208- pin QFP package.

Unless otherwise noted, all information in this document applies to both the LXT9785 and

LXT9785E.

2.1.1

OSP™ Architecture

The Intel LXT9785/9785E incorporates high-efficiency Optimal Signal Processing™ design

techniques, combining the best properties of digital and analog signal processing to produce a truly

optimal device.

The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by

as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques

in the receive equalizer avoids the quantization noise and calculation truncation errors found in

traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result

is improved receiver noise and cross-talk performance.

The OSP architecture also requires substantially less computational logic than traditional DSP-

based designs. The result is lower power consumption and reduced logic switching noise generated

by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable

source of EMI when generated from the device’s power supplies.

The OSP-based LXT9785/9785E provides improved data recovery, EMI performance and power

consumption.

2.1.2

Comprehensive Functionality

The LXT9785/9785E performs all functions of the Physical Coding Sublayer (PCS) and Physical

Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This

device also performs all functions of the Physical Media Dependent (PMD) sublayer for

100BASE-TX connections.

On power-up, the LXT9785/9785E reads its configuration inputs to check for forced operation

settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to

automatically determine line operating conditions. If the PHY device on the other side of the link

supports auto-negotiation, the LXT9785/9785E auto-negotiates with it using Fast Link Pulse (FLP)

Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/9785E automatically

detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set

its operating conditions accordingly.

52

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

The LXT9785/9785E provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.

2.1.2.1

Sectionalization

The LXT9785/9785E’s sectional design allows flexibility with large multiport MACs and ASICs.

With the use of the Section pin, the LXT9785/9785E can be configured into a single 8-port or two

separate 4-port sections, each with its own MDIO (with separate MDC clock) and MII data (with

separate REFCLK/TxCLK/RxCLK clocks) interfaces. See Figure 17 on page 68, Figure 22 on

page 74, and Figure 27 on page 79.

2.2

Interface Descriptions

2.2.1

10/100 Network Interface

The LXT9785/9785E supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet

over twisted-pair, or 100 Mbps (100BASE-FX) Ethernet over fiber media. Each network interface

port consists of four external pins (two differential signal pairs). The pins are shared between

twisted-pair (TP) and fiber. The LXT9785/9785E pinout is designed to interface seamlessly with

dual-high stacked RJ-45 connectors. Refer to Table 10 on page 44 for specific pin assignments.

The LXT9785/9785E output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX

output. When not transmitting data, the device generates IEEE 802.3-compliant link pulses or idle

code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input,

depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to

determine the speed of this interface.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 8. LXT9785/9785E Interfaces

TXENn

TXDn_0

TPFOPn

TXDn_1

TXCLK

RXCLK

RXDn_1

TPFONn

Network

I/F

DATA

I/F

TPFIPn

TPFINn

RXDn_0

RXERn

CRS_DVn

MDIOn

MDCn

MDIO

Mgmt

I/F

MDINTn

MDDIS

Direct Drive

LEDn_2

Port LEDs/

Controls

LEDn_2

LEDn_3

+3.3V

OR

+2.5V

MDIX_Enb

Mode Select

ADD<4:0>

Addr &

MDIX/

Contr

VCCIO

VCCD

GNDD

+2.5V

.01uF

2.2.1.1

Twisted-Pair Interface

The LXT9785/9785E supports either 100BASE-TX or 10BASE-T connections over 100Ω,

Category 5, Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45, and bypass capacitors are

required to complete this interface. Using Intel’s patented waveshaping technology, the transmitter

shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings

(refer to Table 12 on page 46) allow the designer to match the output waveform to the magnetic

characteristics. Both transmit and receive terminations are built into the LXT9785/9785E so no

external components are required between the LXT9785/9785E and the external transformer. The

transmitter uses a transformer with a center tap to help reduce power consumption.

When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not

transmitting data, the LXT9785/9785E generates “IDLE” symbols.

During 10 Mbps operation, LXT9785/9785E encoded data is exchanged. When no data are being

exchanged, the line is left in an idle state with NLPs transmitted to maintain link.

2.2.1.2

MDI Crossover (MDIX)

The LXT9785/9785E crossover function, which is compliant to the IEEE 802.3, clause 23

standard, connects the transmit output of the device to the far-end receiver in a link segment. This

function can be disabled via Register bit 27.9:8 or by using the hardware configuration pins.

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Table 16. MDIX Selection

AMDIX_EN

MDIX

MDIX Mode

0

1

0

1

X

MDI forced

MDIX forced

Auto-MDIX

2.2.1.3

Fiber Interface

The LXT9785/9785E provides a PECL interface that complies with the ANSI X3.166

specification. This interface is suitable for driving a fiber-optic coupler (see Figure 37 on page

101).

Fiber ports cannot be enabled via auto-negotiation and must be enabled via the Global Hardware

Control Interface pins or MDIO registers. All ports are selected for fiber or twisted-pair when

configured via hardware, and can only be intermixed via software. Using external circuitry, the

LXT9785/9785E can interface the fiber transceiver with 2.5V, 3.3V, or 5V supply voltages. Fiber

mode per port may be selected using Register 16.0. Please refer to Table 10 on page 44 for correct

pin assignments.

2.3

Media Independent Interface (MII) Interfaces

The LXT9785/9785E supports Reduced MII or Serial MII, but not concurrently. The interface

mode selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports.

Refer to Table 17 for the mode select settings.

2.3.1

Global MII Mode Select

The mode select pins are used for MII interface configuration settings upon power-up sequencing.

All ports are configured the same and cannot be intermixed.

Table 17. MII Mode Select

ModeSel1

ModeSel0

RMII

SMII

0

1

0

1

0

1

SS-SMII

Reserved

2.3.2

Internal Loopback

A test loopback function is available for 10 Mbps and 100 Mbps mode testing. Bits 0.8, 0.13, and

0.14 must be set to 1 for correct operation. When data is looped back, whatever the MAC transmits

is looped back in its entirety, including the preamble.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 9. Internal Loopback

LXT9785/9785E

Fx

Driver

RMII/

SMII/

SS-

SMII

inter

face

Analog

Block

Digital

Block

Loopback

Tx

Driver

2.3.3

RMII Data Interface

The LXT9785/9785E provides a separate RMII for each network port, each complying with the

RMII standard. The RMII includes both a data interface and an MDIO management interface. The

RMII Data Interface exchanges data between the LXT9785/9785E and up to eight Media Access

Controllers (MACs).

2.3.4

Serial Media Independent Interface (SMII) and Source Synchronous-

Serial Media Independent Interface (SS-SMII)

2.3.4.1

SMII Interface

The LXT9785/9785E provides an independent serial interface for each network port. All SMII

ports use a common reference clock and SYNC signal. The SMII Data Interface exchanges data

between the LXT9785/9785E and multiple Media Access Controllers (MACs). All signals are

synchronous to the reference clock. One SYNC control stream is sourced by the MAC to the PHY.

Both the transmit and receive data streams are segmented into boundaries delimited by the SYNC

pulses. This interface is expected to drive up to 6 inches of trace lengths.

2.3.4.2

2.3.5

Source Synchronous-Serial Media Independent Interface

The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to

relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK,

and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and

referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the

MAC and in reference to the REFCLK.

Configuration Management Interface

The LXT9785/9785E provides an MDIO Management Interface and a Hardware Control Interface

(via the CFG pins) for device configuration and management. Mode control selection is provided

via the MDDIS pin as shown in Table 8 on page 43. When sectionalization (2x4) is selected,

separate MDIO interfaces are enabled (see Figure 14 on page 61).

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2.3.6

MII Isolate

In applications where the MII needs to be isolated from the bus, the RMII and the SMII/SS-SMII

configurations can be tri-stated using Register 0.10. Ports 0 and 1 control RxCLK0, RxCLK1,

RxSYNC0, and RxSYNC1. When 2x4 sectionalization is selected, ports 1-3 and 5-7 can be

individually port isolated. For global shut down, Ports 0 and 1 must be isolated to control the

RxCLKn and RxSYNCn synchronization pins. If ports 0 and 1 are individually set to isolate, the

remaining associated quad sectionalization ports must also be set to isolate.

2.3.6.1

MDIO Management Interface

The LXT9785/9785E supports the IEEE 802.3 MII Management Interface, also known as the

Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to

monitor and control the state of the LXT9785/9785E. The MDIO interface consists of a physical

connection, a specific protocol that runs across the connection, and an internal set of addressable

registers. Some registers are required and their functions are defined by the IEEE 802.3

specification. Additional registers allow for expanded functionality. Specific bits in the registers

are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit

number (0-15).

The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this

interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are

completely disabled. The Hardware Control Interface provides primary configuration control.

When MDDIS is Low, the MDIO port is enabled for both read and write operations and the

Hardware Control Interface is not used. The timing for the MDIO Interface is shown in Table 54

on page 127. MDIO read and (write) cycles are shown in Figures 10 (read) and 11 (write) on

page 57.

Figure 10. Management Interface Read Frame Structure

MDC

MDIO

(Read)

High Z

D1

D0

A4

A3

A0

R4

R3

R0

D15 D14

D14 D1

D15

Z

0

1

0

32 "1"s

Turn

Around

Data

Read

Idle

Preamble

ST

Op Code

PHY Address

Register Address

Write

Figure 11. Management Interface Write Frame Structure

MDC

MDIO

(Write)

A4

A3

A0

R4

R3

R0

D15

D14

D1

D0

32 "1"s

0

1

0

1

0

1

Turn

Around

Idle

Preamble

ST

Op Code

PHY Address

Register Address

Data

Idle

Write

The protocol allows one controller to communicate with multiple LXT9785/9785E chips. Pins

ADD_<4:0> determine the base address. Each port adds its port number to the base address to

obtain its port address as shown in Figure 12.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 12. Port Address Scheme

BASE ADD_<4:0>

(exampleADD_<4:0> = 4)

LXT9785

LXT9785/9785E

PHY ADD_<4:0> (BASE+0)

ex. 4

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Por t 7

PHY ADD_<4:0> (BASE+1)

ex. 5

PHY ADD_<4:0> (BASE+2)

ex. 6

PHY ADD_<4:0> (BASE+3)

ex. 7

PHY ADD_<4:0> (BASE+4)

ex. 8

PHY ADD_<4:0> (BASE+5)

ex. 9

PHY ADD_<4:0> (BASE+6)

ex. 10

PHY ADD_<4:0> (BASE+7)

ex. 11

2.3.6.2

MII Sectionalization

When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access

ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function

is unaffected and operates normally. Sectionalization is selected by pulling pin 176 (Section) High

on the initial power-up sequence (refer to Figure 14). In applications that need sectionalization,

such as 1x8 and 2x4 and have a single MDIO bus structure, it is necessary that the addressing

scheme be contiguous. For example, the first eight ports are addressed 0-7, so the next four ports

must be addressed 8-11.

2.3.6.3

MII Interrupts

The LXT9785/9785E provides a single per-section interrupt pin that is available to all ports.

Interrupt logic is shown in Figure 13. The LXT9785/9785E also provides two dedicated interrupt

registers for each port. Register 18 provides interrupt enable and mask functions and Register 19

provides interrupt status. Setting Register bit 18.1 = 1 enables a port to request interrupt via the

MDINT pin. An active Low on this pin indicates a status change on the device. Because it is a

shared interrupt, there is no indication which port is requesting interrupt service (see Figure 13).

There are five conditions that may cause an interrupt:

• Auto-negotiation complete.

• Speed status change.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

• Duplex status change.

• Link status change.

• Isolate status change.

Figure 13. Interrupt Logic

Event X Enable Reg

AND

Event X Status Reg

OR

Port

Combine

Logic

Interrupt Pin

AND

.

Per Event

.

Per port

Force Interrupt

Interrupt Enable

Interrupt (Event) Status Register is cleared on read.

X = Any Interrupt capability

2.3.6.4

Global Hardware Control Interface

The LXT9785/9785E provides a Hardware Control Interface for applications where the MDIO is

not desired. Refer to “Initialization” on page 60 for additional details.

2.4

Operating Requirements

2.4.1

Power Requirements

The LXT9785/9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO.

The digital and analog circuits require 2.5V supplies (VCCD, VCCR, and VCCT). These inputs

may be supplied from a single source although decoupling is required to each respective ground.

The fiber VCCPECL supply can be connected to either 2.5V or 3.3V.

A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The

power supply may be either +2.5V or +3.3V. VCCIO should be supplied from the same power

source used to supply the controller on the other side of the interface. Refer to Table 29 and

Table 30 on page 106 for I/O characteristics.

As a matter of good practice, these supplies should be as clean as possible. Typical filtering and

decoupling are shown in Figure 35 on page 99.

2.4.2

Clock/SYNC Requirements

Reference Clock

2.4.2.1

The LXT9785/9785E requires a constant enabled reference clock (REFCLK). REFCLK’s

frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used

to generate transmit signals and recover receive signals. A crystal-based clock is recommended

over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to Table 31 on page 106

for clock timing requirements.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must always

be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1 are not tied

together.

2.4.2.2

2.4.2.3

2.4.2.4

2.4.2.5

TxCLK Signal (SS-SMII only)

The LXT9785/9785E requires a 125 MHz input transmit clock synchronous with TxDatan and

frequency locked to REFCLK. See Figure 23 on page 75.

TxSYNC Signal (SMII/SS-SMII)

The LXT9785/9785E requires a 12.5 MHz input pulse for SMII synchronization. See Figure 23 on

page 75.

RxSYNC Signal (SS-SMII only)

The LXT9785/9785E provides a 12.5 MHz output pulse synchronous with the RxDatan outputs.

See Figure 24 on page 75.

RxCLK Signal (SS-SMII only)

In SMII mode, the LXT9785/9785E provides a 125 MHz clock output in reference to the output

RxDatan. RxCLK is referenced and synchronized to the REFCLK. See Figure 24 on page 75.

2.5

Initialization

When the LXT9785/9785E is first powered on, reset, or encounters a link failure state, it checks the

MDIO register configuration bits to determine the line speed and operating conditions to use for

the network link. The configuration bits may be set by the Hardware Control or MDIO interface as

shown in Figure 14 on page 61.

2.5.1

2.5.2

MDIO Control Mode

In the MDIO Control mode, the LXT9785/9785E reads the Hardware Control Interface pins to set

the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts

to the MDIO interface.

Hardware Control Mode

In the Hardware Control Mode, the LXT9785/9785E disables direct write operations to the MDIO

registers via the MDIO Interface. On power-up or hardware reset, the LXT9785/9785E reads the

Hardware Control Interface pins and sets the MDIO registers accordingly.

The following modes are available using either Hardware Control or MDIO Control:

• Force network link to 100BASE-FX (Fiber).

• Force network link operation to:

— 100BASE-TX, Full-Duplex

— 100BASE-TX, Half-Duplex

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Advanced 10/100 8-Port PHY — LXT9785/9785E

— 10BASE-T, Full-Duplex

— 10BASE-T, Half-Duplex

• Allow auto-negotiation/parallel-detection.

• Auto/Manual MDIX enable/disable.

• Pause for full duplex links operation.

• Global Output Slew Rate Control.

When the network link is forced to a specific configuration, the LXT9785/9785E immediately

begins operating the network interface as commanded. When auto-negotiation is enabled, the

LXT9785/9785E begins the auto-negotiation/ parallel-detection operation.

Figure 14. Initialization Sequence

Power-up or Reset

Read H/W Control

Interface

Initialize MDIO Registers

MDIO Control

Mode

Hardware Control

Mode

MDDIS Voltage

Level?

Low

High

Pass Control to MDIO

Interface

Disable MDIO Writes

Software

Reset?

Hardware

Reset?

Yes

Reset MDIO Registers to

values read at H/W

Control Interface at last

Hardware Reset

2.5.3

Power-Down Mode

The LXT9785/9785E incorporates numerous features to maintain the lowest power possible. The

device can be put into a low-power state via Register 0 as well as a near-zero power state with the

power down pin. When in power-down mode, the device is not capable of receiving or transmitting

packets.

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The lowest power operation is achieved using the Global power-down pin, which is active High.

This pin powers down every circuit in the device, including all clocks. All registers are unaltered

and maintained when the Global PWRDWN pin is released.

Individual ports (software power down) can be powered down using Register bit 0.11. This bit

powers down a significant portion of the port, but clocks to the register section remain active. This

allows the management interface to remain active during register power-down. The power-down

bit is active High.

2.5.3.1

Global (Hardware) Power Down

The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the

following conditions are true:

• All LXT9785/9785E ports and the clock are shut down.

• All outputs are tri-stated.

• All weak pad pull-up and pull-down resistors are disabled.

• The MDIO registers are not accessible.

• Configuration pins are not read upon release of the PWRDWN pin, and registers are reloaded

with the value of the last Hardware reset.

2.5.3.2

Port (Software) Power Down

Individual port power-down control is provided by Register bit 0.11 in the respective port Control

Registers (refer to Table 58 on page 130). During individual port power-down, the following

conditions are true:

• The individual port is shut down.

• The MDIO registers remain accessible.

• Pull-up and pull-down resisters are not affected and the outputs are not tri-stated.

• The register remains unchanged.

2.5.4

Reset

The LXT9785/9785E provides both hardware and software resets. Configuration control of Auto-

Negotiation, speed, and duplex mode selection is handled differently for each. During a hardware

reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to Table 18 on

page 63 for pin settings and Table 58 on page 130 and Table 62 on page 133 for register bit

definitions).

During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins and

revert back to the values that were read in during the last hardware reset. Any changes to pin values

from the last hardware reset is not detected during a software reset.

During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.

All MII interface pins are disabled during a hardware reset and released to the bus on de-assertion

of reset.

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During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be

polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not

affected.

2.5.5

Hardware Configuration Settings

The LXT9785/9785E provides a hardware option to set the initial device configuration. The

hardware option uses three Global CFG pins that provide control for all ports (see Table 18).

Table 18. Global Hardware Configuration Settings

CFG

Desired Mode

Resulting Register Bit Values

Pin Settings¹

AutoNeg

Speed

Duplex

1

2

3

0.12

0.13

0.8

4.8

4.7

4.6

4.5

Half

Full

Half

Full

Half

Full

Half

Full

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

0

1

0

1

0

1

0

1

10

0

N/A

Auto-Negotiation Advertisement

Disabled

0

100

1

0

1

0

1

N/A

0

Enabled

1

0

1

10/100

1. Refer to for CFG pin assignments.

2.6

Link Establishment

2.6.1

Auto-Negotiation

The LXT9785/9785E attempts to auto-negotiate with its link partner by sending Fast Link Pulse

(FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 µs apart. Odd link pulses (clock

pulses) are always present. Even link pulses (data pulses) may also be present or absent to indicate

a “1” or a “0”. Each FLP burst exchanges 16 bits of data, referred to as a “page”. All devices that

support auto-negotiation must implement the “Base Page”, defined by IEEE 802.3 (registers 4 and

5). The LXT9785/9785E also supports the optional “Next Page” function (registers 7 and 8).

2.6.1.1

2.6.1.2

Base Page Exchange

By exchanging Base Pages, the LXT9785/9785E and its link partner communicate their

capabilities to each other. Both sides must receive at least three identical base pages for negotiation

to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on

the operating state of the line.

Next Page Exchange

Additional information, exceeding that required by base page exchange, is also sent via “Next

Pages.” The LXT9785/9785E fully supports the IEEE 802.3 method of negotiation via Next Page

exchange. The Next Page exchange uses Register 7 to send information and Register 8 to receive it.

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Next Page exchange occurs only if both ends of the link partners advertise their ability to exchange

Next Pages. A special mode has been added to make next page exchange easier for software. When

Register 6 “page” is received, it stays set until read. This bit should be cleared whenever a new

negotiation occurs, preventing the user from reading an old value in Register 6 and assuming there

is valid information in Registers 5 and 8. Additionally, Register 6 contains a new bit that indicates

when the current received page is the base page. This information is useful for recognizing when

next pages must be resent due to the start of a new negotiation process. Register bit 16.1 and the

page received bit are also cleared upon reading Register 6.

2.6.1.3

Controlling Auto-Negotiation

When auto-negotiation is controlled by software, the following steps are recommended:

• After power-up, power-down, or reset, the power-down recovery time, as specified in Table 55

on page 128, must be exhausted before proceeding.

• Set the auto-negotiation advertisement register bits.

• Enable auto-negotiation (set MDIO Register bit 0.12 = 1).

2.6.1.4

Link Criteria

In 100 Mbps mode, link is established when the scrambler becomes locked and remains locked for

approximately 50ms. Link remains up unless the descrambler receives less than 12 consecutive idle

symbols in any 2 ms period. This provides a very robust operation, filtering out any small noise hits

that may disrupt the link.

In 10 Mbps mode, link is established based on the link state machine found in IEEE 802.3, 14.X.

Receiving 100 Mbps idle patterns does not bring up a 10 Mbps link.

2.6.1.5

Parallel Detection

In parallel with auto-negotiation, the LXT9785/9785E also monitors for 10 Mbps Normal Link

Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device automatically

reverts to the corresponding operating mode. Parallel detection allows the LXT9785/9785E to

communicate with devices that do not support auto-negotiation.

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Figure 15. Auto-Negotiation Operation

Power-Up, Reset,

Link Failure

Start

Disable

Auto-Negotiation

Enable

0.12 = 0

0.12 = 1

Auto-Neg/Parallel Detection

Check Value

0.12

Go To Forced

Settings

Attempt Auto-

Negotiation

Listen for 100TX

Idle Symbols

Listen for 10T

Link Pulses

YES

NO

Done

Link Set?

2.6.1.6

Reliable Link Establishment while Auto MDIX is Enabled in Forced Speed

Mode

With auto MDIX hardware enabled, end users experience reliable link establishment under all

possible settings of auto MDIX and speed between the LXT9785 and its link partners. As stated in

the IEEE clauses 40.4.5.1 (Auto MDIX) and 28.3.2 (Parallel Detect), when ports are forced to

10 Mbps or 100 Mbps and auto MDIX is enabled, and the port is connected to a partner with auto-

negotiate enabled, an undefined condition exists between the IEEE auto MDIX and Parallel Detect

specifications. Therefore, link may never occur according to the IEEE specification. In this

situation, the LXT9785 performs beyond IEEE specification requirements and establishes link.

During the undefined condition, the LXT9785/9785E establishes link within 10 seconds when the

link partner is auto-negotiate enabled and the LXT9785/9785E is set to 10 Mbps or 100 Mbps

speeds, and auto MDIX is hardware enabled. Customers who want auto MDIX disabled on power-

up and enabled through software can disable auto MDIX via software with a boot program and re-

enable auto MDIX via software at any time. Hardware disabling auto MDIX is recommended for

systems not requiring auto MDIX during a forced 100 Mbps speed setting. Ports forced to

100 Mbps speed will not establish link when auto MDIX is hardware disabled and software re-

enabled.

2.7

Serial MII Operation

The LXT9785/9785E exchanges transmit and receive data with the controller via the Serial MII

(SMII). The SMII performs the following functions:

• Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.

• Allows a multi-port MAC/PHY communication with one system clock.

• Operates in both half and full duplex.

• Supports per-packet switching between 10 Mbps and 100 Mbps data rates.

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The Serial MII operates at 125 MHz using a global reference clock and frame synchronization

signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and

RxDatan). All signals are synchronous to REFCLK. Table 19 summarizes the SMII signals.

Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B

coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new

data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times.

Table 19. SMII Signal Summary

Signal

TxData

To

PHY

From

MAC

Purpose

Transmit data & control

Synchronization

SYNC

PHY

MAC

PHY

RxData

Receive data & control

MAC &

PHY

REFCLK

System

Synchronization

1. Refer to Table 5 on page 41 for detailed signal descriptions.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 16. Typical SMII Interface Diagram

Typical SMII Interface

in a 16-Port System

SECTION

8

TxDatan

SYNC0

n

RxData

MDIO0

MDC0

MDINT0

RefCLK0 RefCLK1

125 MHz Sourced

Externally or from

Switch ASIC

SYSTEM CLK

RefCLK0 RefCLK1

8

TxData

SYNC0

n

RxDatan

MDIO0

MDC0

MDINT0

SECTION

Datasheet

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Document #: 249241

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 17. Typical SMII Quad Sectionalization Diagram

Typical SMII Interface in a

24-Port System

RefClk1

RefClk0

8

TxDatan

SYNC0

8

RxDatan

MDIO0

MDC0

MDINT0

SECTION

n

TxData

4

SYNC0

n

RxData

4

MDIO0

MDC0

MDINT0

RefClk0

125 MHz Sourced

Externally or from

Switch ASIC

RefClk1

TxDatan

4

SYNC1

4

n

RxData

VCC

MDINT1

MDIO1

MDC1

SECTION

MDINT0

MDIO0

MDC0

8

TxData n

SYNC0

8

RxData n

SECTION

RefClk0 RefClk1

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 18. 100 Mbps Serial MII Data Flow

Strip

Serial Data Stream

To/From

2 Nibbles Tx/Rx Data

D0 D1 D2 D3

2 Symbols Tx/Rx Data

S0 S1 S2 S3 S4

TX_EN &

TX_ER

Status

Bits

MAC

S0 S1 D0 D1 D2

4B/5B

To/From

PMD

Insert

CRS &

RX_DV

Status

Bits

D3 D4 D5 D6 D7

D0 D1 D2 D3

S0 S1 S2 S3 S4

Sublayer

2.7.1

2.7.2

2.7.3

SMII Reference Clock

The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always

be synchronized to the REFCLK by the MAC and PHY. The LXT9785/9785E samples these

signals on the rising edge of the REFCLK.

TxSYNC Pulse (SMII/SS-SMII)

The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must

continuously generate a TxSYNC pulse once every 10 REFCLK cycles. The TxSYNC pulse

signals the start of each new segment (see Figure 22 on page 74).

Transmit Data Stream

Transmit data and control information are signaled in ten- bit segments. In 100 Mbps mode, each

segment contains a new byte of data. In 10 Mbps mode, the MAC must repeat a 10M serial word

ten times on TxData. The LXT9785/9785E may sample that serial word at any point.

The TxSYNC pulse signals the start of a new segment as shown in Figure 19.

2.7.3.1

2.7.3.2

Transmit Enable

The MAC must assert the TxEN bit in each segment of TxData, and de-assert TxENn after the last

segment of the packet.

Transmit Error

When the MAC asserts the TxER bit in 100BASE-X mode, the LXT9785/9785E drives “H”

symbols onto the network interface. TxER does not have any function in 10M operation.

Datasheet

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Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 19. Serial MII Transmit Synchronization

CLOCK

TxSYNC

TX

TxER TxEN

TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TxER

2.7.4

Receive Data Stream

Receive data and control information are signalled in ten-bit segments. In 100 Mbps mode, each

segment contains a new byte of data. In 10 Mbps mode, each segment is repeated ten times (except

for the CRS bit), and the MAC can sample any of the ten segments.

2.7.4.1

2.7.4.2

Carrier Sense

The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS

bit is set in real time, even in 10 Mbps mode (all other bits are repeated in 10 sequential segments).

Receive Data Valid

The LXT9785/9785E asserts the RX_DV bit (slot 1) when it receives a valid packet. The assertion

timing changes depending on line operating speed:

• For 100BASE-TX and 100BASE-FX links, the RX_DV bit is asserted from the first nibble of

preamble to the last nibble of the data packet.

• For 10BASE-T links, the entire preamble is truncated. The RX_DV bit is asserted with the

first nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of

the packet.

2.7.4.3

2.7.4.4

Receive Error

When the LXT9785/9785E receives an invalid symbol from the network in 100BASE-TX mode, it

drives “1110” on the associated RxData pin.

Receive Status Encoding

The LXT9785/9785E encodes status information onto the RxData line during IPG as seen in

Table 20 on page 71. Status bit RxData<5> indicates the validity of the upper nibble (RxData<7:4>

of the last byte of the previous frame). RxData and RX_DV are passed through the internal

elasticity FIFO to smooth any clock rate differences between the recovered clock and the 125 MHz

reference clock.

2.7.5

Collision

The SMII interface does not provide a collision output and relies on the MAC to interpret COL

conditions using CRS and TxEN. CRS is unaffected by the transmit path.

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 20. Serial MII Receive Synchronization

CLOCK

RxSYNC

RXD0

RXER

RXD1

Speed

RXD2

RXD3

RXD4

Jabber

RXD5

Valid

RXD6

FCE

RXD7

RX

CRS

RX_DV

Duplex Link

Table 20. RX Status Encoding Bit Definitions

Signal

Definition

CRS

Carrier Sense - identical to MII, except that it is not an asynchronous signal.

Receive Data Valid - identical to MII. When RX_DV = 0, status information is

transmitted to the MAC. When RX_DV = 1, received data is transmitted to the

MAC.

0 = Status Byte

1 = Valid Data Byte

RxDV

RxER

Inter-frame status bit RxData0 indicates whether or not the PHY detected an error 0 = No Error

(RxData0)

somewhere in the previous frame.

1 = Error

SPEED

(RxData1)

0 = 10 Mbps

1 = 100 Mbps

Inter-frame status bit RxData1 indicates port operating speed.

DUPLEX

(RxData2)

0 = Half

1 = Full

Inter-frame status bit RxData2 indicates port duplex condition.

Inter-frame status bit RxData3 indicates port link status.

Inter-frame status bit RxData4 indicates port jabber status.

LINK

(RxData3)

0 = Down

1 = Up

JABBER

(RxData4)

0 = OK

1 = Error

VALID

(RxData5)

Inter-frame status bit RxData5 conveys the validity of the upper nibble of the last

byte of the previous frame.

0 = Invalid

1 = Valid

False Carrier

(RxData6)

Inter-frame status bit RxData6 indicates whether or not the PHY has detected a

false carrier event.

0 = No FC detected

1 = FC detected

RxData7

This bit is set to 1.

Always = 1

1. Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid until the first data

segment of the next frame begins.

Datasheet

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

2.7.5.1

Source Synchronous-Serial Media Independent Interface

Some system designs require the PHY to be placed between 3 to 12 inches away from the MAC. A

new Source Synchronous-Serial Media Independent Interface (SS-SMII) definition has been added

because of this requirement. To provide a source synchronous interface between the PHY and

MAC, the PHY must drive the RxCLK and the RxSYNC signals to the MAC. Also, the MAC must

drive the TxCLK and the TxSYNC signal to the PHY. The REFCLK is also needed to synchronize

the data to the PHY’s core clock domain. TxData is clocked in using TxCLK and then

synchronized to REFCLK and transmitted to the twisted-pair. The RxData is synchronized to the

RxCLK. See Figure 24 on page 75.

Table 21. SS-SMII

Signal

To

From

MAC

Purpose

TxData

TxCLK

PHY

MAC

Transmit data & control

Transmit clock

MAC

PHY

TxSYNC

RxData

RxCLK

Synchronization pulses

Receive data & control

Receive clock

PHY

RxSYNC

REFCLK

PHY

Receive Synchronization

Synchronization

System

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Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 21. Typical SS-SMII Interface Diagram

Typical SS-SMII Interface in

a 16-Port System

SECTION

8

TxDatan

TxSYNC0

TxCLK0

8

RxDatan

RxSYNC1

RxCLK1

MDIO0

MDC0

MDINT0

RefCLK0,1

125 MHz Sourced

Externally or from

Switch ASIC

SYS_CLK

RefCLK0,1

8

TxData

n

TxSYNC0

TxCLK0

RxData

n

RxSYNC1

RxCLK1

MDIO0

MDC0

MDINT0

SECTION

NOTE: For SMII operation TxCLK1, RxSYNCn and RxCLKn pins are ignored

Datasheet

73

Document #: 249241

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 22. Typical SS-SMII Quad Sectionalization Diagram

Typical SS-SMII Interface

in a 24-Port System

RefClk0 RefClk1

8

TxData n

TxSYNC0

TxCLK0

8

RxData n

RxSYNC1

RxCLK1

MDIO0

MDC0

MDINT0

SECTION

TxData

n

4

TxSYNC0

TxCLK0

RxData

n

4

RxSYNC0

RxCLK0

MDIO0

MDC0

MDINT0

RefClk0

125 MHz Sourced

Externally or from

Switch ASIC

RefClk1

TxData

n

4

TxSYNC1

TxCLK1

4

RxData

n

RxSYNC1

RxCLK1

VCC

MDINT1

MDIO1

SECTION

MDC1

MDINT0

MDIO0

MDC0

8

TxData

n

TxSYNC0

TxCLK0

8

RxData n

RxSYNC1

RxCLK1

SECTION

RefClk0 RefClk1

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 23. SS-SMII Transmit Timing

SS-SMII Transmit Timing

TxCLK

TxSYNC

TxData

TXER

TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER

TxCLK

TxSYNC

TxData

TXER

Frcerr Speed

Dplx LINK Jabr

TXEN

TXER

All signals are

synchronous to the clock

Figure 24. SS-SMII Receive Timing

SS-SMII Receive Timing

RxCLK

RxSYNC

RxData

CRS

RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS

RxCLK

RxSYNC

RxData

CRS

RXER Speed

CRS

RXDV

Dplx LINK Jabr UPnib FlsCar

All signals are

synchronous to the clock

Datasheet

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Document #: 249241

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

2.8

RMII Operation

The LXT9785/9785E provides an independent Reduced MII port for each network port. Each

RMII uses four signals to pass received data to the MAC: RxDatan<1:0>, RxERn, and CRS_DVn

(where n reflects the port number). Three signals are used to transmit data from the MAC:

TxDatan_<1:0> and TxENn. Both receive and transmit signals are clocked by REFCLK. Data

transmission across the RMII is implemented in di-bit pairs which equal a 4-bit wide nibble.

2.8.1

2.8.2

RMII Reference Clock

The LXT9785/9785E requires a 50 MHz reference clock (REFCLK). The device samples the RMII

input signals on the rising edge of REFCLK and drives RMII output signals on the falling edge.

Transmit Enable

TxENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert

TxENn at the same time as the first nibble of preamble. TxENn must be de-asserted after the last

bit of the packet.

2.8.3

2.8.4

Carrier Sense & Data Valid

The LXT9785/9785E asserts CRS_DVn when it detects activity on the line. However, RxDatan

outputs zeros until the received data is decoded and available for transfer to the controller.

Receive Error

Whenever the LXT9785/9785E receives an error symbol from the network, it asserts RxERn.

When it detects a bad Start-of-Stream Delimiter (SSD) it drives a “10” jam pattern on the RxData

pins to indicate a false carrier event.

2.8.5

2.8.6

Out-of-Band Signalling

The LXT9785/9785E has the capability of encoding status information in the RxData stream

during IPG. See “Monitoring Operations” on page 92 for details.

4B/5B Coding Operations

The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However,

data is normally transmitted across the RMII interface in 2-bit nibblets or “di-bits”. The LXT9785/

9785E incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles,

and a 4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit symbols for the

100BASE-X connection. Figure 25 on page 77 shows the data conversion flow from nibbles to

symbols. Table 22 on page 82 shows 4B/5B symbol coding (not all symbols are valid).

76

Datasheet

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Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 25. RMII Data Flow

Reduced MII Mode Data Flow

+1

Parallel

to

Serial

0

Scramble

D0 D2

D1 D3

-1

4B/5B

MLT3

D0 D1 D2 D3

S0 S1 S2 S3 S4

De-

Scramble

Transition = 1.

No Transition = 0.

All transitions must follow

pattern: 0, +1, 0, -1, 0, +1...

Serial

to

Parallel

di-bit

pairs

4-bit

nibbles

5-bit

symbols

Datasheet

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 26. Typical RMII Interface Diagram

Typical RMII Interface

in a 16-Port System

SECTION

TxD0n

8

TxD1n

8

TxENn

RxD0n

8

RxD1n

CRS_DV

n

RxERn

MDIO0

MDC0

MDINT0

RefClk0 RefClk1

50 Mhz Sourced

Externally or from

Switch ASIC

RefClk0

MDINT0

RefClk1

MDIO0

MDC0

8

TxD0

TxD1

n

8

TxEN

RxD0

n

8

RxD1

CRS_DV

RxER

n

8

n

SECTION

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Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 27. Typical RMII Quad Sectionalization Diagram

Typical RMII Interface

in a 24-Port System

RefClk0 RefClk1

TxD0n

TxD1

8

n

8

TxENn

RxD0n

8

RxD1n

CRS_DVn

RxERn

MDIO0

MDC0

MDINT0

SECTION

4

TxD0n

TxD1n

TxENn

RxD0n

RxD1n

4

CRS_DVn

RxERn

4

MDIO0

MDC0

MDINT0

RefClk0

50 MHz Sourced

Externally or from

Switch ASIC

RefClk1

4

TxD0

TxD1

TxEN

n

4

RxD0n

RxD1n

CRS_DV

RxER n

n

VCC

MDINT1

MDIO1

MDC1

SECTION

MDINT0

MDIO0

MDC0

8

TxD0n

n

TxD1

n

TxEN

8

RxD0n

RxD1n

CRS_DVn

RxERn

SECTION

RefClk0 RefClk1

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

2.9

100 Mbps Operation

2.9.1

100BASE-X Network Operations

During 100BASE-X operation, the LXT9785/9785E transmits and receives 5-bit symbols across

the network link. Figure 28 shows the structure of a standard frame packet. When the MAC is not

actively transmitting data, the LXT9785/9785E sends out Idle symbols on the line.

In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3

line code. The MLT-3 signals received from the network are de-scrambled and decoded, and sent

across the RMII to the MAC.

In 100BASE-FX mode, the LXT9785/9785E transmits and receives NRZI signals across the PECL

interface. An external 100BASE-FX transceiver module is required to complete the fiber

connection.

As shown in Figure 28, the MAC starts each transmission with a preamble pattern. As soon as the

LXT9785/9785E detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD)

symbol to the network. It then encodes and transmits the rest of the packet, including the balance of

the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends,

the LXT9785/9785E transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to

transmitting Idle symbols.

Figure 28. 100BASE-X Frame Format

64-Bit Preamble

(8 Octets)

Destination and Source

Address (6 Octets each)

Packet Length

(2 Octets)

Data Field

(Pad to minimum packet size)

Frame Check Field InterFrame Gap / Idle Code

(4 Octets)

(> 12 Octets)

CRC

IFG

SFD

P0 P1 P6

DA DA SA SA L1

L2

D0 D1 Dn

I0

Replaced by

/T/R/ code-groups

End-of-Stream Delimiter (ESD)

Replaced by

Start-of-Frame

Delimiter (SFD)

/J/K/ code-groups

Start-of-Stream

Delimiter (SSD)

2.9.2

100BASE-X Protocol Sublayer Operations

In a 7-layer communications model, the LXT9785/9785E is a Physical Layer 1 (PHY) device. The

LXT9785/9785E implements the Physical Coding Sublayer (PCS), Physical Medium Attachment

(PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the

IEEE 802.3u specification. The following paragraphs discuss the LXT9785/9785E operation from

the reference model point of view.

2.9.2.1

PCS Sublayer

The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/

decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE

symbols to the PMD-layer line driver as long as TxEN is de-asserted. For 10T operation, the PCS

layer merely provides a bus interface and serialization/de-serialization function. 10T operation

does not use the 4B/5B encoder.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

2.9.2.1.1 Preamble Handling

When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of-

Stream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer

continues to encode the remaining RMII data until TxEN is de-asserted (see Table 22 on page 82).

It then returns to supplying IDLE symbols to the line driver.

The PCS layer performs the opposite function in the receive direction by substituting two preamble

nibbles for the SSD.

2.9.2.1.2 Dribble Bits

The LXT9785/9785E handles dribble bits in all modes. If one through four dribble bits are

received, the nibble is passed across the RMII, padded with ones if necessary. If five through seven

dribble bits are received, the second nibble is not sent to the RMII bus.

Figure 29. Protocol Sublayers

MII Interface

LXT9785

PCS

Encoder/Decoder

Serializer/De-serializer

Sublayer

PMA

Sublayer

Link/Carrier Detect

PECL Interface

PMD

Sublayer

Scrambler/

De-scrambler

Fiber Transceiver

100BASE-TX

100BASE-FX

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

2.9.3

PMA Sublayer

Table 22. 4B/5B Coding

4B Code

Code Type

5B Code

4 3 2 1 0

Name

Interpretation

3 2 1 0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0

1 1 1 1 0

0 1 0 0 1

1 0 1 0 0

1 0 1 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 1 0

0 1 1 1 1

1 0 0 1 0

1 0 0 1 1

1 0 1 1 0

1 0 1 1 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 11

1 1 0 0 0

1 0 0 0 1

0 1 1 0 1

0 0 1 1 1

0 0 1 0 0

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 1 0 0

1 0 0 0 0

1 1 0 0 1

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Data 8

Data 9

Data A

Data B

Data C

Data D

Data E

Data F

1

2

3

4

5

6

DATA

0 1 1 1

1 0 0 0

7

8

1 0 0 1

9

1 0 1 0

A

1 0 1 1

B

1 1 0 0

C

1 1 0 1

D

1 1 1 0

E

1 1 1 1

F

I ¹

J ²

K ²

T ³

R ³

H ⁴

IDLE

undefined

0 1 0 1

Idle. Used as inter stream fill code.

Start-of-Stream Delimiter (SSD), part 1 of 2.

CONTROL

0 1 0 1

Start-of-Stream Delimiter (SSD), part 2 of 2.

undefined

End-of-Stream Delimiter (ESD), part 1 of 2.

End-of-Stream Delimiter (ESD), part 2 of 2.

Transmit Error. Used to force signalling errors.

Invalid

INVALID

1. The /I/ (Idle) code group is sent continuously between frames.

2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.

3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.

4. An /H/ (Error) code group is used to signal an error condition.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

2.9.3.0.1 Link

In 100 Mbps mode, the LXT9785/9785E establishes a link whenever the scrambler becomes

locked and remains locked for approximately 50 ms. Whenever the scrambler loses lock (<12

consecutive idle symbols during a 2 ms window), the link is taken down. This provides a robust

link, filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100 Mbps

idle patterns will not bring up a 10 Mbps link.

The LXT9785/9785E reports link failure via the RMII status bits (1.2, 17.10, and 19.4) and

interrupt functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.

2.9.3.0.2 Link Failure Override

The LXT9785/9785E normally transmits 100 Mbps data packets or Idle symbols only if it detects

the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this

function, allowing the LXT9785/9785E to transmit data packets even when the link is down. This

feature is provided as a diagnostic tool.

Note: Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-

negotiation is enabled, the LXT9785/9785E automatically begins transmitting FLP bursts if the

link goes down.

2.9.3.0.3 Carrier Sense/Data Valid (RMII)

The LXT9785/9785E asserts CRS_DV whenever the respective port receiver is in a non-idle state

(as defined by the RMII Specification Revision 1.2), including false carrier events. Assertion of

CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not

complete when CRS_DV is asserted, the LXT9785/9785E outputs 00 on the RxData1:0 lines until

the decoded data are available.

When the line returns to an idle state, CRS_DV is de-asserted asynchronously with respect to

REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is de-

asserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals,

CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.

2.9.3.0.4 Carrier Sense (SMII)

For 100BASE-TX and 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair

causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair

causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received

without /T/R/. In this event, the RxER bit in the RX Status Frame is asserted for one clock cycle

when CRS is de-asserted.

For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of

an End-of-Frame (EOF) marker.

2.9.3.0.5 Receive Data Valid (SMII)

The LXT9785/9785E asserts the RX_DV bit when it receives a valid packet. However, RxData

outputs zeros until the received data are decoded and available for transfer to the controller.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

2.9.3.1

Twisted-Pair PMD Sublayer

The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and

descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well

as receiving, polarity correction, and baseline wander correction functions.

2.9.3.1.1 Scrambler/Descrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using

an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial

whenever IDLE symbols are received.

The scrambler/descrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is

automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic

and test support.

2.9.3.1.2 Baseline Wander Correction

The LXT9785/9785E provides a baseline wander correction function which makes the device

robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is,

by definition, “unbalanced”. This means that the DC average value of the signal voltage can

“wander” significantly over short time intervals (tenths of seconds). This wander may cause

receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact

characteristics of the wander are completely data dependent.

The LXT9785/9785E baseline wander correction characteristics allow the device to recover error-

free data while receiving worst-case “killer” packets over all cable lengths.

2.9.3.1.3 Polarity Correction

The LXT9785/9785E automatically detects and corrects for the condition where the receive signal

(TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted

End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not received by

the maximum receive time-out period, the polarity state is reset to a non-inverted state.

2.9.3.2

Fiber PMD Sublayer

The LXT9785/9785E provides a PECL interface for connection to an external fiber-optic

transceiver. (The external transceiver provides the PMD function for fiber media.) The device uses

an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not

support 10FL applications.

2.9.3.2.1 Far End Fault Indications

The LXT9785/9785E Signal Detect pins independently detect signal faults from the local fiber

transceivers via the SD pins. The device also uses Register bit 1.4 to report Remote Fault

indications received from its link partner. The device “ORs” both fault conditions to set bit 1.4.

Register bit 1.4 is set once and clears when read.

Either fault condition causes the LXT9785/9785E to drop the link unless Forced Link Pass is

selected (16.14 = 1). Link down condition is then reported via interrupts and status bits.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

In response to locally detected signal faults (SD activated by the local fiber transceiver), the

affected port can transmit the far end fault code if fault code transmission is enabled by Register bit

16.2.

• When Register bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785/

9785E transmits far end fault code if fault conditions are detected by the Signal Detect pins.

• When Register bit 16.2 = 0, the LXT9785/9785E does not transmit far end fault code. It

continues to transmit idle code and may or may not drop link depending on the setting for

Register bit 16.14.

The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer

to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones’s followed

by a single “0” and is repeated until the Far End Fault condition is removed.

2.10

10 Mbps Operation

The LXT9785/9785E operates as a standard 10BASE-T transceiver and supports all the standard

10 Mbps functions. During 10BASE-T (10T) operation, the LXT9785/9785E transmits and

receives Manchester-encoded data across the network link. When the MAC is not actively

transmitting data, the device sends out link pulses on the line.

In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals

received from the network are decoded by the LXT9785/9785E and sent across the RMII to the

MAC.

Note: The LXT9785/9785E does not support fiber connections at 10 Mbps.

2.10.1

Preamble Handling

The LXT9785/9785E offers two options for preamble handling, selected by Register bit 16.5. In

10T Mode when Register bit 16.5 = 0, the device strips the entire preamble off the received

packets. CRS_DV is asserted simultaneously with SFD. CRS_DV is held Low for the duration of

the preamble. When CRS_DV is asserted, the very first two nibbles driven by the LXT9785/9785E

are the SFD “5D” hex followed by the body of the packet.

When Register bit 16.5 = 1 in 10T mode, the LXT9785/9785E passes the preamble through the

RMII and asserts CRS_DV simultaneously.

2.10.2

2.10.3

Dribble Bits

The LXT9785/9785E device handles dribble bits in all modes. If one through four dribble bits are

received, the nibble is passed across the RMII. If five through seven dribble bits are received, the

second nibble is not sent onto the RMII bus.

Link Test

The LXT9785/9785E always transmits link pulses in 10T mode. When enabled, the link test

function monitors the connection for link pulses. Once link pulses are detected, data transmission is

enabled and remains enabled as long as either the link pulses or data transmission continue. If link

pulses stop, the data transmission is disabled.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

If the link test function is disabled, the LXT9785/9785E transmits to the connection regardless of

detected link pulses. The link test function is disabled by setting Register bit 16.14 = 1.

2.10.3.1

2.10.4

Link Failure

Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this

condition occurs, the LXT9785/9785E returns to the auto-negotiation phase if auto-negotiation is

enabled.

Jabber

If a transmission exceeds the jabber timer, the LXT9785/9785E disables the transmit and loopback

functions. The RMII does not include a Jabber pin, but the MAC may read Register 1 or 25 to

determine Jabber status. The LXT9785/9785E automatically exits jabber mode after the unjab time

has expired. This function is disabled by setting Register bit 16.10 = 1.

2.11

DTE Discovery Process

The DTE discovery process is port dependent and must be enabled through software. The process

is implemented as a next page option to the auto-negotiation flow. This feature applies to the

LXT9785E transceiver only.

The process depends upon an IP phone, or any other DTE capable of being powered remotely,

having a specific filter that passes NLPs and FLPs. This filter should be non-polarized to insure

that the latest status of Auto-MDIX operation does not effect operation. This filter attenuates 100

Mbps MLT3 signals and 10 Mbps Manchester-encoded signals, and must be bypassed when power

is applied to the IP phone. Figure 30 shows a typical IP telephone system connection.

Figure 30. Typical IP Telephone System Connection

VoIP-Enabled Switch

S

D

Pro

HP

C

u

rv

e

Sw

i

tc

h

2

4

l

2

4

M

J4122B

10 / 1 0 0B a s e- T Ports

M

o

d

u

e

S

a

t

u

s

t

1

X

2

X

3

X

4

X

5

X

6

X

1

3

X

1

4

X

1

5

X

1

6

X

1

7

X

1

8

X

1

2

3

4

5

6

1

3

1

4

1

5

1

6

1

7

1

8

L

i

n

k

SelfTes

Mode

1

9

2

0

2

1

2

3

2

4

7

8

9

1

0

1

2

L

i

n

k

Consol e

M

o

d

e

Power

Ac

t

Fdx

1

0

R

e

s

e

t

C lear

M

o

d

e

Se

l

e

c

t

Fautl

7

X

8

X

9

X

1

0

X

1

X

1

2

X

1

9

X

2

0

X

2

1

X

2

X

2

3

X

2

4

Power cable

Power and data over

Category 5 cable

Power

Outlet

UPS/

Generator

Power cable

1

2

3

4

7

5

8

6

9

8

#

*

Power

Outlet

IP Telephone

Computer

Data only over

Category 5 cable

86

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Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

2.11.1

Definitions

The following terms are used throughout the DTE discovery sections:

Negotiation Process:

System:

This includes auto-negotiation and parallel detection processes

The switch system using the LXT9785E for DTE Discovery

A device connected to the LXT9785E through twisted pair cables

Data Terminal Equipment; any end-of-link partner

Link Partner:

DTE:

A link partner that is not requiring power over a Category 5 cable;

typically a PC

Standard Link Partner:

Data Terminal Equipment requiring power over a Category 5 cable;

typically an IP telephone

Remote-Power DTE:

Discovery:

The process of identifying the type of link partner present

2.11.2

Interaction between Processor, MAC and PHY

The state machines that control the mechanics of the Discovery process reside within the

LXT9785E device. However, control of the power supply and overall system control reside in the

system processor. The processor communicates with the power supply unit (PSU) and switches it

on and off dependant on the data that is supplied by the PHY. The PHY register data is read by the

MAC using the MDIO interface. The required control bits are contained in the PHY device register

map and are discussed in detail in the section labeled “Management Interface and Control” on

page 88.

Note: The details of the processor/MAC interface and the processor/PSU interface are implementation

specific and therefore are out of the scope of this specification.

The following is an overview of the system control for a successful Remote-Power DTE discovery:

1. The discovery process is enabled by the DTE Discovery Process Enable (Dis_EN) Register bit

27.6 and the Auto-Negotiation Enable Register bit 0.12.

2. The LXT9785E PHY then tests to see if a Remote-Power DTE is present as the link partner. If

a Remote-Power DTE is found, the Power Enable (Power_EN) Register bit 27.4 is set. The

processor polls this signal via the MAC.

3. Upon detecting a Remote-Power DTE, the processor instructs the power supply to switch on.

Once power has been applied to the DTE, normal negotiation takes place. The processor must

enable the required negotiation process by restarting auto-negotiation, or by setting forced

speed mode after power has been applied. The processor must poll the link-up Register bit 1.2

for the corresponding LXT9785E port, or the link status change interrupt, to ensure that the

link has been established.

4. A time-out must be connected with this feature so that if link is not established within a pre-

determined time period (system dependant), the processor instructs the power supply to switch

off. If link is not established prior to the expiration of the “link fail inhibit timer”, the

LXT9785E restarts negotiation with DTE detection if auto-negotiation mode was used to

establish link with the phone, and the DTE process is still enabled. The LXT9785E restarts

negotiation without DTE detection if either forced speed mode is used to establish link with

the phone, or the DTE process is disabled.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

5. If power is applied and link is established, the system must still poll the Link Status Register

bit 1.2 for the corresponding LXT9785E port or the link status change interrupt. This is

required since link status is the only way to know when the Remote-Power DTE is removed or

unplugged. On seeing the Link_Down condition, the processor instructs the power supply to

switch off, and the DTE Discovery begins again or is disabled.

2.11.3

Management Interface and Control

The management and control of the DTE discovery process is via the MDIO port. Each port on the

LXT9785E is capable of running the discovery process, thus each port is independently controlled.

This is achieved by each port having a dedicated set of control and status bits. These bits are found

in Register 27 as follows:

DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN)

R/W Default value = 0: Disabled.

Register bit 27.6 controls the operation of the process. The discovery process is disabled when

Register bit 27.6 = 0, and enabled when Register bit 27.6 = 1. The MAC controller sets Register bit

27.6 to a 1 when a port search for a DTE requiring power is desired. Once set, Register bit 27.6

remains = 1 until the MAC clears it, either by directly clearing it or by resetting the PHY. This

allows the discovery process to continue to function if unsuccessful in detecting a DTE, without

being continually re-enabled by the MAC. If Register bit 27.6 is set after link is established, no

action is taken until after the link goes down.

POWER ENABLE - Register Bit 27.4 (Power_EN)

RO Default value = 0: No Remote-Power DTE found.

Register bit 27.4 contains the result of the discovery process. When Register bit 27.4 = 0, the

discovery process has not found Remote-Power DTE, and when Register bit 27.4 = 1, the

discovery process has potentially found a DTE requiring power. This indicates power should be

applied to the Category 5 cable. Register bit 27.4 is polled by the MAC during the discovery

process, and is cleared when the PHY is reset, when auto-negotiation is restarted, or when auto-

negotiation is disabled. In the event of a discovery process being interrupted due to detection of an

already powered link partner (auto-negotiation completion or Parallel Detection), Register

bit 27.4 = 0.

STANDARD LINK PARTNER DETECTED - Register Bit 27.3 (SLP_Det)

R/W Clear on Read Default value = 0: No link partner found.

When Register bit 27.3 = 1, a standard link partner has been detected by the LXT9785E (NLPs,

MLT3 data, FLPs without next page support, or FLPs with non-matching next pages). This

indicates power should not be applied to the Category 5 cable. When Register bit 27.3 = 0, other

bits are checked to determine overall status of the link partner. Register bit 27.3 is cleared on read,

or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled.

LINK FAIL TIMEOUT - Register Bit 27.2 (LFIT Expired)

R/W Clear on Read Default value = 0 (Link Fail Inhibit timer has expired without establishment of

link with a standard link partner). Valid only when Standard Link Partner Detected Register bit

27.3 = 1.

Register bit 27.2 is set if link is not established prior to the Link Fail Inhibit Timer expiring. This

indicates that the Discovery process has restarted and the Standard Link Partner Detected Register

bit may no longer be valid. Register bit 27.2 is cleared on read, or DTE discovery is disabled, link

is established, or auto-negotiation is either restarted or disabled.

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

2.11.4

DTE Discovery Process Flow

The following section describes the DTE Discovery process. See Figure 31 on page 91 for a flow

chart of the discovery process.When DTE Discovery (27.6) and auto-negotiation (0.12) are enabled

(auto-negotiation mode is required), the LXT9785E transmits the auto-negotiation base page with

the next page ability bit set (Auto-Negotiation Advertisement Register (Address 4)).

System software polls Register 27 to determine if or when a Remote-Power DTE is detected. The

receiver monitors the line to determine if NLPs, MLT3 data, or FLP bursts are being received. If

the receive activity is FLP bursts, the status of the next page ability bit is checked. If the detected

“link partner” also supports next page, then the LXT9785E transmits out the next page sequence

associated with message code #5 (Organizationally Unique Identifier (OUI) Tag Code). The

definition for the next pages to be sent out for this message code include some user-defined code

values. These values are loaded with randomly created data from an internal LSFR that is free

running and seeded with the PHY address of the LXT9785E port. The Next Pages are hard coded

in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in Table 23

on page 90. The receiver monitors the next pages to determine that the exact next page data

(especially the random data) transmitted is received. The Power-Enable Register bit 27.4 is set

when a Remote-Power DTE is detected as the link partner, and the last next page is repeatedly

transmitted until software restarts the required negotiation process (auto-negotiation or forced-

speed mode).

The software should be written so that the negotiation is not restarted until the DTE has been

powered up over the Category 5 cable. The Power-Enable Register bit 27.4 is cleared upon

restarting or disabling auto-negotiation (selecting forced mode). The system must be able to detect

over-current conditions and be capable of disabling power in case the link partner is not a Remote-

Power DTE. Some examples of devices that would mistakenly set Power-Enable Register bit 27.4

are a token-ring balun and a loopback cable. Once link partner power has been stabilized and

sufficient time has passed for the link partner to initialize, the auto-negotiation process may be

restarted.

The negotiation process establishes link if a compatible mode exists between the LXT9785E and

the link partner. If a compatible mode does not exist (not compatible or not established within the

Link Fail Inhibit Timer period), the LXT9785E either restarts auto-negotiation/DTE discovery

(discovery is enabled (27.6=1) and auto-negotiation is enabled (0.12 = 1)), or normal negotiation

(discovery is disabled (27.6=0) and auto-negotiation is enabled (0.12 = 1)), or either 10 Mbps or

100 Mbps forced-mode operation (auto-negotiation is disabled (0.12 = 0)). The software must

detect this non-link state and disable power.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 23. Next Page Message #5 Code Word Definitions

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

OUI

Tagged

Message

1

a

1

0

t

0

1

0

1

UserPage

1

a

0

t

3.10 3.11 3.12 3.13 3.14 3.15 2.0 2.1 2.2 2.3 2.4

2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15

UserPage

2

UserPage

3

0

L.8 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0

UserPage

4

L.10 L.9 L.8 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0

1. a is the acknowledge bit; t is the toggle bit; L is the LFSR

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 31. LXT9785E Negotiation Flow Chart

Start

Assumptions:

Auto-Negotiation/Forced Speed Set by Pins

Advertisement Requirements Set by Pins

Power Up

or

Link Down 1.2 = 0 and Dis_EN 27.6 = 0

or

Link Down 1.2 = 0 and Forced Mode

LFIT Expired 27.2 = 1

Link Fail Timeout = 1

Dis_EN Not Set 27.6 = 0

Default Mode

Transmit based upon hardware

configuration

NLPs or IDLE Symbols

Detected

FLP, NLP or IDLE Symbols

LFIT Expired 27.2 = 1

Dis_EN 27.6 = 0

Software Intervention

Auto-negotiation 0.12 = 1 (if needed)

Power_EN 27.6 = 1

FLP Detected

NLPs or IDLE Symbols

Link Down 1.2 = 0

Discovery Base

Transmit FLPs

Base Page (Register 4)

with Next Page 4.15 = 1

Detected

Parallel Detection

Determine Compatibility on

Speed and Duplex

and

Dis_EN 27.6 = 1

and

Auto-Neg 0.12 = 1

LFIT Expired 27.2 = 1

Check Advertisement

Dis_EN 27.6 = 1

LFIT Expired 27.2 = 1

Dis_EN 27.6 = 1

FLP Detected

No

Auto Negotiation

Determine Compatibility Options

No

Yes

Auto-

Negotiation?

Compatibility

Next Page Transmission

Use Random Data for User Defined

Bits as Code

Power Applied

No

Next Pages Received

Compatibility

Power On

Wait State for

Proper Power

Assertiion

Pages = Code

Transmitted?

Set Mode

Restart

Auto-Negotiation

Yes

or

Software Intervention

Software Polled Power_EN 27.4 = 1

Turn On Power Supply

Force Speed

DTE Discovered

Transmit Last Page Continuously

Power_EN 27.4 = 1

Link Up

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

2.12

Monitoring Operations

2.12.1

Monitoring Auto-Negotiation

Auto-negotiation may be monitored as follows:

• Bits 1.2 and 17.10 = 1 once the link is established.

• Additional bits in Register 1 (refer to Table 59 on page 131) and Register 17 (refer to Table 68

on page 138) can be used to determine the link operating conditions and status.

2.12.2

Per-Port LED Driver Functions

The LXT9785/9785E incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and

LEDn_3). On power up, all the LEDs lights up for approximately one second after reset de-asserts.

Each LED may be programmed to one of several different display modes using the LED

Configuration Register. Each per-port LED may be programmed (refer to Table 71 on page 141) to

indicate one of the following conditions:

• Operating Speed

• Transmit Activity

• Receive Activity

• Collision Condition

• Link Status

• Duplex Mode

• Isolate Condition

The LEDs can also be programmed to display various combined status conditions. For example,

setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:

• If Link is down, LED is off.

• If Link is up, LED is on.

• If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits

20.3:2 and continues to blink as long as activity is present.

The LED driver pins are open drain circuits (10mA max current rating). Refer to “LED Circuit” on

page 98 under the Application Information Section for LED circuit design details. The LED

Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during

this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see

Table 71 on page 141).

When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.

The LED driver remains asserted until the stretch timer expires. If another event occurs before the

stretch timer expires, the stretch timer is reset and the stretch time extended.

When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.

When the stretch timer expires, the edge detector is reset so that a long event causes another pulse

to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED

driver to remain asserted. Figure 32 on page 93 shows how the stretch operation functions.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 32. LED Pulse Stretching

Event

LED

stretch

Note: The direct drive LED outputs in this diagram are shown as active Low.

2.12.3

Out-of-Band Signalling

The LXT9785/9785E provides an out-of-band signalling option to transfer status information

across the RMII receive interface. This feature is enabled when Register bit 25.0 = 1 and uses the

RxData(1:0) data bus during the Inter-Packet Gap (IPG) time as shown in Figure 33.

The two status bits transferred across the RxData bus are software selectable via Register 25 (see

Table 73 on page 143).

In normal operation, the LXT9785/9785E stuffs the RxData bus with zeros during the IPG. A

software-selectable bit enables the RMII out-of-band signalling feature. Once this bit is set, the

LXT9785/9785E replaces the zeros with selected status bits during the IPG.

Figure 33. RMII Programmable Out-of-Bank Signaling

REFCLK

CRS_DV

RXD(1)

RXD(0)

status 1

status 0

status 1

status 0

data

status 1

status 0

status 1

status 0

status 1

status 0

status 1

status 0

0s

statu s 1

status 0

1. When network activity is detected, the LXT9785/9785E asserts CRS_DV asynchronously with respect to REFCLK.

2. After CRS_DV is asserted, the LXT9785/9785E zero-stuffs the RxData bits until the received data has been processed

through the FIFO.

3. When network activity ceases, the LXT9785/9785E de-asserts CRS_DV synchronously with respect to REFCLK. CRS_DV

toggles until all data in the FIFO has been processed through the RMII. Once the FIFO is empty, LXT9785/9785E drives the

status bits selected by the Out-of-Band Signalling Register (refer to Table 73 on page 143) on the RxData outputs.

The LXT9785/9785E includes an IEEE 1149.1 boundary scan test port for board level testing. All

digital input, output, and input/output pins are accessible.

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

2.12.4

2.12.5

2.12.6

2.12.7

Boundary Scan Interface

This interface consists of five pins (TMS, TDI, TDO, TCK and TRST). It includes a state machine,

data register array, and instruction register. The TMS and TDI pins are internally pulled up and the

TCK pin is internally pulled down. TDO does not have an internal pull-up or pull-down.

State Machine

The TAP controller is a 16-state machine driven by the TCK and TMS pins. Upon reset, the

TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are

High for five TCK periods.

Instruction Register

The IDCODE instruction is always invoked after the state machine resets. The decode logic

ensures the correct data flow to the Data registers according to the current instruction. Valid

instructions are listed in Table 25.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the

serial shift stage and the parallel output stage. There are four modes of operation as listed in

Table 24.

Table 24. BSR Mode of Operation

Mode

Description

Capture

1

2

3

4

Shift

Update

System Function

Table 25. Supported JTAG Instructions

Data

Register

Name

Code

Description

External Test

EXTEST

IDCODE

SAMPLE

High Z

0000 Hex

BSR

FFFE Hex

FFF8 Hex

FFCF Hex

FFEF Hex

FFFF Hex

ID Code Inspection

Sample Boundary

Force Float

ID REG

BSR

Bypass

BSR

Clamp

BYPASS

Bypass Scan

Bypass

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Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

3.0

Application Information

3.1

Design Recommendations

The LXT9785/9785E is designed to comply with IEEE 802.3 requirements to provide outstanding

receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum

performance from the LXT9785/9785E, attention to detail and good design practices are required.

Refer to the LXT9785 Design and Layout Guide application note for detailed design and layout

information.

3.2

General Design Guidelines

Adherence to generally accepted design practices is essential to minimize noise levels on power

and ground planes. Up to 50mV maximum of noise is considered acceptable. High-frequency

switching noise can be reduced, and its effects eliminated, by following these simple guidelines

throughout the design:

• Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC

or ground plane that is not located adjacent to the signal layer.

• Use ample bulk and decoupling capacitors throughout the design (a value of 0.01µF is

recommended for decoupling caps).

• Provide ample power and ground planes.

• Provide termination on all high-speed switching signals and clock lines.

• Provide impedance matching on long traces to prevent reflections.

• Route high-speed signals next to a continuous, unbroken ground plane.

• Filter and shield DC-DC converters, oscillators, etc.

• Do not route any digital signals between the LXT9785/9785E and the RJ-45 connectors at the

edge of the board.

• Do not extend any circuit power and ground plane past the center of the magnetics or to the

edge of the board. Use this area for chassis ground, or leave it void.

3.2.1

Power Supply Filtering

Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and

degrade line performance. The best approach to this problem is to minimize ground noise as much

as possible using good general techniques and by filtering the VCC plane. It is generally difficult to

predict in advance the performance of any design, although certain factors greatly increase the risk

of having problems:

• Poorly-regulated or over-burdened power supplies.

• Wide data busses (32-bits+) running at a high clock rate.

• DC-to-DC converters.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/9785E. This

has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the

LXT9785/9785E, helping with line performance. Second, if the VCC planes are laid out correctly,

digital switching noise is kept away from external connectors, reducing EMI problems.

The recommended implementation is to break the VCC plane into two sections. The digital section

supplies power to the VCCD and VCCIO pins of the LXT9785/9785E. The analog section supplies

power to the VCCA pins. The break between the two planes should run underneath the device. In

designs with more than one the LXT9785/9785E, a single continuous analog VCC plane can be

used to supply them all.

The digital and analog VCC planes should be joined at one or more points by ferrite beads. The

beads should produce at least a 100Ω impedance at 100 MHz. Beads should be placed so that

current flow is evenly distributed. The maximum current rating of the beads should be at least

150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10µF) should

be placed on each side of each bead.

In addition, a high-frequency bypass cap (0.01uF) should be placed near each analog VCC pin.

3.2.2

Power and Ground Plane Layout Considerations

Great care needs to be taken when laying out the power and ground planes.

• Follow the guidelines in the LXT9785 Design and Layout Guide (formerly Application Note

151) for locating the split between the digital and analog VCC planes.

• Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and

the RJ-45 connectors.

• Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the

ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.

3.2.2.1

Chassis Ground

For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the

board and is isolated via moats and keep-out areas from all circuit-ground planes and active

signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used

to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications,

provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In

multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV

isolation to the Bob Smith termination.

3.2.3

MII Terminations

Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785/

9785E. Special trace layout consideration should be used when using the SMII interface. Keep all

traces orthogonal and as short as possible. Whenever possible, route the clock and sync traces

evenly between the longest and shortest data routes. This minimizes round-trip, clock-to-data

delays and allows a larger margin to the setup and hold requirements.

3.2.4

Twisted-Pair Interface

Use the following standard guidelines for a twisted-pair interface:

96

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Advanced 10/100 8-Port PHY — LXT9785/9785E

• Place the magnetics as close as possible to the LXT9785/9785E.

• Keep transmit pair traces as short as possible; both traces should have the same length.

• Avoid vias and layer changes as much as possible.

• Keep the transmit and receive pairs apart to avoid cross-talk.

• Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the

transmit traces two to three layers from the ground plane, with no intervening signals.

• Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400

mA may be used to supply center tap current to all ports.

3.2.4.1

Magnetic Requirements

The LXT9785/9785E requires a 1:1 ratio for both the receive transformers and the transmit

transformers. The transmit isolation voltage should be rated at 1.5 kV to protect the circuitry from

static voltages across the connectors and cables. The LXT9785/9785E is a current driven

transceiver that requires an external voltage (center tap) to drive the transmit signal. In order to

support the Auto-MDIX functionality of the LXT9785/9785E, the magnetic must provide a center

tap for both the transmit and receive magnetic winding, with both connected to VCCT. See the

LXT9785/9785E Design and Layout Guide (249509-001) for magnetic testing with the LXT9785/

9785E. Before committing to a specific component, designers should contact the manufacturer for

current product specifications, and validate the magnetics for the specific application. Table 26

provides the magnetics requirements.

Table 26. Magnetics Requirements

Parameter

Min

Nom

Max

Units

Test Condition

Rx turns ratio

–

1:1

0.6

–

Tx turns ratio

–

Insertion loss

0.0

350

–

1.1

–

dB

µH

kV

Primary inductance

Transformer isolation

2

–

Differential to common mode

rejection

40

–

dB

.1 to 60 MHz

35

-16

-10

–

dB

60 to 100 MHz

30 MHz

Return Loss

80 MHz

3.2.5

The Fiber Interface

The fiber interface consists of an LVPECL transmit and receive pair to an external fiber optic

transceiver. 3.3V fiber optic transceivers and 5V fiber optic transceivers can be used with the

LXT9785/9785E. The transmit pair should always be AC-coupled to the transceiver, and re-biased

appropriately. The receive pair should be DC-coupled to a 3.3V fiber optic transceiver, and AC-

coupled and re-biased to a 5V fiber optic transceiver. The signal detect pin can be DC-coupled to a

3.3V fiber optic transceiver. In 5V fiber optic transceiver applications, a PECL-to-LVPECL logic

translator is required on the signal detect pin. Refer to the fiber transceiver manufacturer’s

recommendations for termination circuitry. Figure 37, “Typical LXT9785/9785E to 3.3V Fiber

Transceiver Interface Circuitry” on page 101 shows a typical example of an LXT9785/9785E-to-

3.3V fiber transceiver interface. Figure 38, “Typical LXT9785/9785E to 5V Fiber Transceiver

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Interface Circuitry” on page 102 shows a typical example of an LXT9785-to-5V fiber transceiver

interface, and Figure 39, “ON Semiconductor Triple PECL-to-LVPECL Translator” on page 103

shows the interface circuitry for the logic translator.

3.2.6

LED Circuit

Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected via a current-

limiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin drives Low.

The open-drain LED pins are 5V tolerant, allowing use of either a 3.3V or 5V rail (a 2.5V rail is

unlikely to work with standard forward voltage LEDs). A 5V rail eases LED component selection

by allowing more common, high-forward voltage LEDs to be used. Refer to Figure 34 for a circuit

illustration.

Figure 34. LED Circuit

V_LED

R

LEDn_m

Outside

IC

Inside

IC

VCCIO VLED

5.0V + 5%

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Advanced 10/100 8-Port PHY — LXT9785/9785E

3.3

Typical Application Circuits

Figure 35 through Figure 38 on page 102 show typical application circuits for the LXT9785/

9785E. Figure 39 on page 103 shows the interface circuitry for the logic translator.

Figure 35. Power and Ground Supply Connections

SGND

GNDR/GNDT

0.01µF

VCCR/VCCT

10µF

+

Analog Supply Plane

Ferrite

Bead

LXT9785/9785E

Digital Supply Plane

10µF

+2.5V

VCCD

GNDD

VCCIO

0.01µF

+ 2.5V

or +3.3V

+2.5V

or +3.3V

VCCPECL

GNDPECL

0.1µF

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 36. Typical Twisted-Pair Interface

TPFOP

RJ-45

1:1

1

2

3

4

5

6

7

8

1

TPFON

TPFIP

50 Ω

LXT9785/9785E

50 Ω

2

50 Ω

TPFIN

.01 µF

* = 0.001 µF /

2.0 kV

* = 0.001 µF /

2.0 kV

VCCT

GNDA

.01µF

0.1µF

1. The 100Ω transmit load termination resistor typically required is integrated in the LXT9785/

9785E.

2. The 100Ω receive load termination resistor typically required is integrated in the LXT9785/9785E.

100

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 37. Typical LXT9785/9785E to 3.3V Fiber Transceiver Interface Circuitry

+3.3V

+2.5V +2.5V

0.01µF

− 0.1µF

0.01µF

1.3kΩ 1.3kΩ

27Ω

50Ω

− 0.1µF

50Ω

0.01 µF

TPFONn

TPFOPn

TD -

TD +

0.01 µF

2kΩ

Fiber Txcvr

LXT9785

+3.3V

130Ω

SD/TPn

SD

1

82Ω

RD -

TPFINn

TPFIPn

RD +

130Ω 130Ω

2D_2P5V

GNDPECL

3.3V

VCCPECL

1. Refer to the transceiver manufacturers’ recommendations for termination circuitry.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 38. Typical LXT9785/9785E to 5V Fiber Transceiver Interface Circuitry

+5V

+2.5V

0.01µF

− 0.1µF

0.01µF

− 0.1µF

27Ω

1.1kΩ

50Ω

0.01µF

TD -

TPFONn

TPFOPn

TD +

3.1kΩ

Fiber Txcvr

LXT9785

2

ON Semiconductor

MC100LVEL92

SD/TPn

SD

PECL-to-LVPECL

Logic Translator

+2.5V

1

0.01µF

− 0.1µF

169Ω 169Ω

0.01µF

RD -

TPFINn

TPFIPn

RD +

158Ω 158Ω

130Ω 130Ω

2D_2P5V

GNDPECL

3.3V

VCCPECL

1. Refer to the transceiver manufacturers’ recommendations for termination circuitry.

2. See Figure 39 on page 103 for recommended logic translator interface circuitry.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 39. ON Semiconductor Triple PECL-to-LVPECL Translator

5V

0.01 µF

5V

3.3V

ON Semiconductor

Vcc

82Ω

130Ω

82Ω

1

2

3

Vcc

20

19

18

17

16

15

14

13

12

11

PECL Input

Signal

(5V Fiber

Txcvr)

LVPECL

Output Signal

(LXT9785)

D0

__

D0

Q0

__

Q0

130Ω

VBB PECL

4

5

6

LVCC

3.3V

D1

__

D1

Q1

__

Q1

VBB PECL

7

LVCC

D2

__

D2

Q2

__

Q2

8

9

0.01 µF

3.3V

130Ω

GND

Vcc

10

MC100LVEL92

82Ω

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LXT9785/9785E — Advanced 10/100 8-Port PHY

4.0

Test Specifications

Note: Table 27 through Table 56 and Figure 40 through Figure 63 represent the target specifications of

the LXT9785/9785E. These specifications are not guaranteed and are subject to change without

notice. Minimum and maximum values listed in Table 29 through Table 56 apply over the

recommended operating conditions specified in Table 28.

Table 27. Absolute Maximum Ratings

Parameter

Sym

Min

Max

Units

VCCIO, VCCPECL

VCCA, VCCD

TST

-0.3

-65

4.0

3.0

V

Supply voltage

Storage temperature

+150

ºC

Caution: Exceeding these values may cause permanent damage. Functional operation under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 28. Operating Conditions

1

Typ

Parameter

Sym

Min

Max

Units

(2.5 VCCIO)

(3.3 VCCIO)

Ambient

TOPA

TOPC

TOPA

TOPC

0

–

70

108

85

ºC

Commercial Operating

Temperature

Case

Ambient

-40

2.38

3.14

2.38

–

ºC

Extended Operating

Temperature

Case

123

2.63

3.46

2.63

810

160

410

200

765

90

ºC

Analog & Digital

I/O

Vcca, Vccd

Vccio

2.5

N/A

2.5

3.3

N/A

V

Supply voltage²

I/O (SD_2P5V = 0)

I/O (SD_2P5V = 1)

V

VCCPECL

V

ICC

ICCIO

ICC

780

380

710

20

mA

100BASE-TX

100BASE-FX

–

60

90

30

2

130

170

70

3

–

ICCIO

ICC

–

Operating Current - RMII 10BASE-T

ICCIO

ICC

–

20

Power-Down Mode

Hardware

ICCIO

ICC

–

4

–

500

540

4

Auto-Negotiation

ICCIO

–

2

4

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Voltages with respect to ground unless otherwise specified.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 28. Operating Conditions (Continued)

1

Typ

Parameter

Sym

Min

Max

Units

(2.5 VCCIO)

(3.3 VCCIO)

ICC

–

800

380

740

50

830

160

410

200

770

130

50

mA

100BASE-TX

100BASE-FX

10BASE-T

ICCIO

ICC

70

90

60

3

130

170

110

5

ICCIO

ICC

Operating Current - SMII

ICCIO

ICC

Power-Down Mode

Hardware

ICCIO

ICC

5

520

800

380

740

30

570

30

Auto-Negotiation

100BASE-TX

100BASE-FX

10BASE-T

ICCIO

ICC

20

90

3

30

835

200

410

200

770

180

40

ICCIO

ICC

170

150

5

ICCIO

ICC

Operating Current -

SS-SMII

ICCIO

ICC

Power-Down Mode

Hardware

ICCIO

ICC

5

530

570

80

Auto-Negotiation

ICCIO

50

70

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Voltages with respect to ground unless otherwise specified.

Table 29. Digital I/O DC Electrical Characteristics (VCCIO = 2.5V +/- 5%)

1

Parameter

Input Low voltage

Sym

Min

Typ

Max

Units

Test Conditions

VIL

VIH

–

1.75

-100

–

0.75

–

V

–

Input High voltage

–

Input current

II

100

0.2

0.5

–

µA

V

0.0 < VI < VCC

IOL = 4 mA

IOL = 10 mA

IOH = -4 mA

–

Output Low voltage

VOL

Output Low voltage (LEDm_n pins)

Output High voltage

VOL-LED

VOH

–

V

2.07

–

V

Input Low voltage SD pins

Input High voltage SD pins

VIL-SD

VIH-SD

0.755

–

V

1.58

V

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 30. Digital I/O DC Electrical Characteristics (VCCIO = 3.3V +/- 5%)

1

Parameter

Input Low voltage

Sym

Min

Typ

Max

Units

Test Conditions

VIL

VIH

–

2.0

-100

–

0.8

–

V

–

Input High voltage

–

Input current

II

100

0.2

0.5

–

µA

V

0.0 < VI < VCC

IOL = 4 mA

IOL = 10 mA

IOH = -4 mA

–

Output Low voltage

VOL

Output Low voltage (LEDm_n pins)

Output High voltage

VOL-LED

VOH

–

V

2.4

–

V

Input Low voltage SD pins

Input High voltage SD pins

VIL-SD

VIH-SD

1.515

–

V

2.42

V

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 31. Required Clock Characteristics

2

Parameter

SMII Input frequency

Sym

Min

Typ

Max

Units

Test Conditions

f

–

125

50

–

MHz

ppm

%

–

RMII Input frequency

–

Input clock frequency tolerance¹

Input clock duty cycle¹

∆f

Tdc

–

± 50

65

–

35

50

RMII selection

Input clock duty cycle - REFCLK,

TxCLK¹

Tdc

40

45

50

60

55

%

SMII/SS-SMII selection

SS-SMII only

Output RxCLK duty cycle

1. Parameter is guaranteed by design; not subject to production testing.

2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 32. 100BASE-TX Transceiver Characteristics

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Peak differential output voltage

Signal amplitude symmetry

Signal rise/fall time

VP

Vss

t_rf

0.95

98

3

–

1.05

102

5

V

Note 2

%

ns

Rise/fall time symmetry

t_rfs

–

0.5

Offset from 16 ns pulse width at

50% of pulse peak

Duty cycle distortion

Overshoot

–

+/- 0.5

5

ns

%

VO

–

Jitter magnitude (measured

differentially)

t_tx-jit

1.4

ns

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Measured at the line side of the transformer, line replaced by 100Ω (+/-1%) resistor.

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 33. 100BASE-FX Transceiver Characteristics

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Transmitter

Peak differential output voltage

(single ended)

VOP

t_rf

0.6

–

1.44

–

V

–

Signal rise/fall time

1.6

1.4

ns

10 to 90%, 2.0 pF load

Jitter magnitude (measured

differentially)

t_tx-jit

–

Receiver

Peak differential input voltage

Common mode input range

VIP

0.55

–

V

–

VCMIR

–

VCC - 0.5

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 34. 10BASE-T Transceiver Characteristics

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Transmitter

Peak differential output voltage

Link transmit period

VOP

2.2

8

2.5

2.8

V

Note 2

–

24

11

ms

–

Jitter magnitude added by the

MAU and PLS sections ^{3, 4}

t_tx-jit

–

ns

–

Receiver

Receive input impedance³

Link min receive timer

ZIN

–

2

100

–

7

W

ms

Between TPFIP and TPFIN

TLRmin

TLRmax

VDS

–

Link max receive timer

50

–

150

–

ms

–

Differential squelch threshold

475

mV Peak

5 MHz square wave input

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Parameter is guaranteed by design; not subject to production testing.

3. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.

4. After line model specified by IEEE 802.3 for 10BASE-T MAU.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 40. SMII - 100BASE-TX Receive Timing

REFCLK

t5

t6

SYNC

RxData

TPFI

t1

t2

t3

t4

Table 35. SMII - 100BASE-TX Receive Timing Parameters

1

Parameter

Sym

Min Typ

Max Units

Test Conditions

RxData output delay from REFCLK

rising edge

Minimum CL = 5 pF

Maximum CL = 20 pF

t1

t2

t3

1.5

–

5

–

ns

RxData Rise/Fall Time

1.0

21

–

Synchronous sampling of

SMII

Receive start of /J/ to CRS asserted

–

29

BT²

Receive start of /T/ to CRS de-

asserted

Synchronous sampling of

SMII

t4

–

25

30

BT²

SYNC setup to REFCLK rising edge

SYNC hold from REFCLK rising edge

t5

t6

1.5

1.0

–

ns

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 41. SMII - 100BASE-TX Transmit Timing

REFCLK

t1

t2

SYNC

t1

t2

TxData

t3

TPFO

Table 36. SMII - 100BASE-TX Transmit Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

SYNC setup to REFCLK rising edge and

TxData setup to REFCLK rising edge

t1

1.5

–

ns

–

SYNC hold from REFCLK rising edge and

TxData hold from REFCLK rising edge

t2

t3

1.0

–

ns

–

TxEN sampled to start of /J/

–

11

14

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 42. SMII - 100BASE-FX Receive Timing

REFCLK

t5

t6

SYNC

RxData

TPFI

t1

t2

t3

t4

Table 37. SMII - 100BASE-FX Receive Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

RxData output delay from REFCLK

rising edge

Minimum CL = 5 pF

Maximum CL = 20 pF

t1

t2

t3

1.5

–

1

5

–

ns

RxData Rise/Fall Time

–

Synchronous

sampling of SMII

Receive start of /J/ to CRS asserted

–

18

26

BT²

Receive start of /T/ to CRS de-

asserted

Synchronous

sampling of SMII

t4

–

23

27

BT²

SYNC setup to REFCLK rising edge

SYNC hold from REFCLK rising edge

t5

t6

1.5

1.0

–

ns

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

110

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 43. SMII - 100BASE-FX Transmit Timing

REFCLK

t1

t2

SYNC

t1

t2

TxData

t3

TPFO

Table 38. SMII - 100BASE-FX Transmit Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

SYNC setup to REFCLK rising edge and

TxData setup to REFCLK rising edge

t1

1.5

–

ns

–

SYNC hold from REFCLK rising edge

and TxData hold from REFCLK rising

edge

t2

t3

1.0

–

ns

–

TxEN sampled to start of /J/

–

10

13

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

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Document #: 249241

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 44. SMII - 10BASE-T Receive Timing

REFCLK

t5

t6

SYNC

t1

t2

RxData

t3

t4

TPFI

Table 39. SMII - 10BASE-T Receive Timing Parameters

1

Parameter

Sym

t1

Min

Typ

Max

Units

Test Conditions

RxData output delay from

REFCLK rising edge

Minimum CL = 5 pF

Maximum CL = 20 pF

1.5

–

5

ns

RxData Rise/Fall Time

t2

t3

1

–

ns

–

Receive Start-of-Frame to CRS

asserted

–

17

18

BT³

Synchronous sampling of SMII²

Receive Start-of-Idle to CRS

de-asserted

t4

t5

t6

–

17

–

18

–

BT³

ns

Synchronous sampling of SMII²

SYNC setup to REFCLK rising

edge

1.5

1.0

–

SYNC hold from REFCLK rising

edge

–

ns

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. Assumes each SMII segment is sampled for CRS.

3. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

112

Datasheet

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Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 45. SMII - 10BASE-T Transmit Timing

REFCLK

t1

t2

SYNC

t1

t2

TxData

t3

TPFO

Table 40. SMII-10BASE-T Transmit Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

SYNC setup to REFCLK rising edge and

TxData setup to REFCLK rising edge

t1

1.5

–

ns

–

SYNC hold to REFCLK rising edge and

TxData hold from REFCLK rising edge

t2

t3

1.0

–

ns

–

TxEN sampled to start-of-frame

–

10

12.5

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

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Document #: 249241

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 46. SS-SMII - 100BASE-TX Receive Timing

REFCLK

t1

RxCLK

t2

RxSYNC

t3

RxData

t4

t5

TPFI

Table 41. SS-SMII - 100BASE-TX Receive Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

REFCLK rising edge to RxCLK

rising edge

t1

–

1.5

–

ns

–

RxData/RxSYNC output delay

from RxCLK rising edge

Minimum CL = 5pF

Maximum CL = 40pF

t2

t3

t4

1.5

–

5

–

ns

RxData/RxSYNC Rise/Fall time

1.0

21

–

Receive start of /J/ to CRS

asserted

–

25

BT²

Receive start of /T/ to CRS

de-asserted

t5

–

25

30

BT²

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

114

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 47. SS-SMII - 100BASE-TX Transmit Timing

TxCLK

t1

t2

TxSYNC

TxData

t1

t2

t3

TPFO

Table 42. SS-SMII - 100BASE-TX Transmit Timing

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

TxSYNC setup to TxCLK rising edge and

TxData setup to TxCLK rising edge

t1

1.5

–

ns

–

TxSYNC hold from TxCLK rising edge and

TxData hold to TxCLK rising edge

t2

t3

1.0

–

ns

–

TxEN sampled to start of /J/

–

11

14

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

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Document #: 249241

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 48. SS-SMII - 100BASE-FX Receive Timing

REFCLK

t1

RxCLK

t2

RxSYNC

t3

RxData

t4

t5

TPFI

Table 43. SS-SMII - 100BASE-FX Receive Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

REFCLK rising edge to RxCLK rising edge

t1

–

1.5

ns

–

RxData/RxSYNC output delay from RxCLK

rising edge

Minimum CL = 5pF

Maximum CL = 40pF

t2

1.5

–

5

ns

RxData/RxSYNC Rise/Fall time

t3

t4

t5

–

1

–

ns

–

Receive start of /J/ to CRS asserted

Receive start of /T/ to CRS de-asserted

18

21

23

26

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

116

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Document #: 249241

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 49. SS-SMII - 100BASE-FX Transmit Timing

TxCLK

t1

t2

TxSYNC

TxData

t1

t2

t3

TPFO

Table 44. SS-SMII - 100BASE-FX Transmit Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

TxSYNC setup to TxCLK rising edge and

TxData setup to TxCLK rising edge

t1

1.5

–

ns

–

TxSYNC hold from TxCLK rising edge and

TxData hold to TxCLK rising edge

t2

t3

1.0

–

ns

–

TxData to TPFO Latency

–

11

13

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

117

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 50. SS-SMII - 10BASE-T Receive Timing

REFCLK

t1

RxCLK

t2

RxSYNC

t3

RxData

t4

t5

TPFI

Table 45. SS-SMII - 10BASE-T Receive Timing Parameters

1

Parameter

Sym

Min Typ

Max Units

Test Conditions

REFCLK rising edge to RxCLK rising

edge

t1

–

1.5

–

ns

–

RxData/RxSYNC output delay from

RxCLK rising edge

Minimum CL = 5pF

Maximum CL = 40pF

t2

t3

t4

1.5

–

1

5

–

ns

RxData/RxSYNC Rise/Fall time

–

Synchronous sampling of

SMII²

Receive Start-of-Frame to CRS asserted

–

10

11

BT³

Synchronous sampling of

SMII²

Receive Start-of-Idle to CRS de-asserted

t5

–

18

19

BT³

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. Assumes each SMII segment is sampled for CRS.

3. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

118

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 51. SS-SMII - 10BASE-T Transmit Timing

TxCLK

t1

t2

TxSYNC

TxData

t1

t2

t3

TPFO

Table 46. SS-SMII - 10BASE-T Transmit Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

TxSYNC setup to TxCLK rising edge and

TxData setup to TxCLK rising edge

t1

1.5

–

ns

–

TxSYNC hold to TxCLK rising edge and TxData

hold from TxCLK rising edge

t2

t3

1.0

–

ns

–

TxData to TPFO Latency

–

10

12.5

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

119

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 52. RMII - 100BASE-TX Receive Timing

REFCLK

t1 t2

RxData[1:0]

TPFI

t3

t4

CRS_DV

Table 47. RMII - 100BASE-TX Receive Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

RxData<1:0>, CRS_DV, RXER setup to REFCLK

rising edge³

t1

t2

2

–

14

ns

–

RxData<1:0>, CRS_DV, RXER hold from REFCLK

rising edge³

Receive start of /J/ to CRS_DV asserted

Receive start of /T/ to CRS_DV de-asserted

t3

t4

–

16

20

27

BT²

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

3. Values and conditions from RMII Specification, Rev. 1.2.

120

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 53. RMII - 100BASE-TX Transmit Timing

REFCLK

t1

t2

TxData(1:0)

TPFO

t1

t3

t2

TxEN

Table 48. RMII - 100BASE-TX Transmit Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

TxData<1:0>/TxEN setup to REFCLK rising

edge

t1

4

–

ns

–

TxData<1:0>/TxEN hold from REFCLK rising

edge

t2

t3

2

–

ns

–

TxEN sampled to TPFO out (Tx latency)

–

12

13

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

121

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 54. RMII - 100BASE-FX Receive Timing

REFCLK

t1

t2

RxData[1:0]

TPFI

t3

t4

CRS_DV

Table 49. RMII - 100BASE-FX Receive Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

RxData<1:0>, CRS_DV, RXER setup to

REFCLK rising edge³

t1

t2

2

–

14

ns

–

RxData<1:0>, CRS_DV, RXER hold from

REFCLK rising edge³

Receive start of /J/ to CRS_DV asserted

Receive start of /T/ to CRS_DV de-asserted

t3

t4

–

14

18

25

BT²

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

3. Values and conditions from RMII Specification, Rev. 1.2.

122

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 55. RMII - 100BASE-FX Transmit Timing

REFCLK

t1

t2

TxData(1:0)

TPFO

t1

t3

t2

TxEN

Table 50. RMII - 100BASE-FX Transmit Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

TxData<1:0>/TxEN setup to REFCLK rising edge

t1

t2

t3

4

2

–

ns

–

TxData<1:0>/TX-EN hold from REFCLK rising

edge

–

TxEN sampled to TPFO out (Tx latency)

10

12

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

123

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 56. RMII - 10BASE-T Receive Timing

REFCLK

t1 t2

RxData[1:0]

TPFI

t3

t4

CRS_DV

Table 51. RMII - 10BASE-T Receive Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

RxData<1:0>, CRS_DV setup to REFCLK rising

edge³

t1

t2

2

–

14

ns

–

RxData<1:0>, CRS_DV hold from REFCLK rising

edge³

TPFI in to CRS_DV asserted

t3

t4

1.5

14

3

4

BT²

–

TPFI quiet to CRS_DV de-asserted

15

16

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

3. Values and conditions from RMII Specification, Rev. 1.2.

124

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 57. RMII - 10BASE-T Transmit Timing

REFCLK

t1

t2

TxData(1:0)

TPFO

t1

t3

t2

TxEN

Table 52. RMII - 10BASE-T Transmit Timing Parameters

Test

Conditions

1

Parameter

Sym

Min

Typ

Max

Units

TxData<1:0>/TxEN setup to REFCLK rising

edge

t1

4

–

ns

–

TxData<1:0>/TxEN hold from REFCLK rising

edge

t2

t3

2

–

ns

–

TxEN sampled to TPFO out (Tx latency)

–

8.5

10.5

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

125

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 58. Auto-Negotiation and Fast Link Pulse Timing

Clock Pulse

Data Pulse

Clock Pulse

TPFOP

t1

t3

t2

Figure 59. Fast Link Pulse Timing

FLP Burst

TPFOP

t4

t5

Table 53. Auto-Negotiation and Fast Link Pulse Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Clock/Data pulse width

Clock pulse to Data pulse

Clock pulse to Clock pulse

FLP burst width

t1

t2

t3

t4

t5

–

55.5

111

–

100

–

69.5

139

–

ns

µs

–

µs

2

ms

ea

FLP burst to FLP burst

Clock/Data pulses per burst

8

–

24

17

–

33

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

Datasheet

126

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 60. MDIO Write Timing (MDIO Sourced by MAC)

MDC

t2

t1

MDIO

Figure 61. MDIO Read Timing (MDIO Sourced by PHY)

MDC

t3

MDIO

Table 54. MDIO Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

MDIO setup before MDC, sourced by

STA

t1

10

–

ns

–

MDIO hold after MDC,

sourced by STA

t2

t3

10

0

–

ns

–

MDC to MDIO output delay, sourced

by PHY

40

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

Datasheet

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Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 62. Power-Up Timing

v1

VCC

tPDR

MDIO,etc

Table 55. Power-Up Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Voltage Threshold

v1

2.1

–

V

–

Power-Up recovery time

tPDR

100

ms

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

Figure 63. Reset Recovery Timing

tPW

RESET

tRcdly

MDIO,etc

Table 56. Reset Recovery Timing Parameters

1

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Reset pulse width

tPW

10

–

ns

–

Reset recovery delay

tRcdly

0.4

ms

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

128

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Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

5.0

Register Definitions

The LXT9785/9785E register set includes multiple 16-bit registers, 17 registers per port. Table 57

presents a complete register listing. Table 58 through Table 73 define individual registers and

Table 76 provides a consolidated memory map of all registers.

Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and

Media Independent Interface” and “Physical Layer Link Signalling for 10/100 Mbps Auto-

Negotiation” sections of the IEEE 802.3 standard.

Additional registers (16 through 20) are defined in accordance with the IEEE 802.3 standard for

adding unique chip functions.

Table 57. Register Set

Address

Register Name

Bit Assignments

0

1

Control Register

Status Register

Refer to Table 58 on page 130

Refer to Table 59 on page 131

Refer to Table 60 on page 132

Refer to Table 61 on page 132

Refer to Table 62 on page 133

Refer to Table 63 on page 134

Refer to Table 64 on page 135

Refer to Table 65 on page 135

2

PHY Identification Register 1

3

PHY Identification Register 2

4

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Base Page Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Transmit Register

5

6

7

8

Auto-Negotiation Link Partner Next Page Receive Register Refer to Table 66 on page 136

9

1000BASE-T/100BASE-T2 Control Register

1000BASE-T/100BASE-T2 Status Register

Extended Status Register

Port Configuration Register

Quick Status Register

Not Implemented

10

15

16

17

18

19

20

21

22

23 - 24

25

26

27

28-31

Not Implemented

Refer to Table 67 on page 137

Refer to Table 68 on page 138

Refer to Table 69 on page 139

Refer to Table 70 on page 140

Refer to Table 71 on page 141

Refer to Table 72 on page 142

Interrupt Enable Register

Interrupt Status Register

LED Configuration Register

Receive Error Count Register

Reserved

Reserved-Analog Status Register

RMII Out-of-Band Signalling Register

Reserved-Analog Status Register

Trim Enable Register

Refer to Table 73 on page 143

Refer to Table 74 on page 144

Reserved

Datasheet

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Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 58. Control Register (Address 0)

Bit

Name

Description

Type ²

Default

1 = PHY reset

R/W

SC

0.15

RESET

0¹

0 = normal operation

1 = Enable loopback mode

0 = Disable loopback mode

0.14

0.13

Loopback

R/W

0

0.6 0.13

1

0

1 = Reserved

0 = 1000 Mbps (not allowed)

1 = 100 Mbps

Speed Selection

R/W

LSHR^3,4

0 = 10 Mbps

1 = Enable Auto-Negotiation Process

0 = Disable Auto-Negotiation Process

Auto-Negotiation

Enable

0.12

R/W

LSHR^3,4

1 = power-down

0 = normal operation

0.11

0.10

Power-Down

Isolate

R/W

0

1 = Electrically isolate PHY from RMII or SMII interface

0 = normal operation

Restart

R/W

SC

1 = Restart Auto-Negotiation Process

0 = normal operation

0.9

0.8

0¹

Auto-Negotiation

1 = Full Duplex

0 = Half Duplex

Duplex Mode

Collision Test

R/W

LSHR^3,4

This bit is ignored by the LXT9785/9785E

0.7

0

1 = Enable COL signal test

0 = Disable COL signal test

0.6 0.13

1

0

1 = Reserved

0 = 1000 Mbps (not allowed)

1 = 100 Mbps

Speed Selection

1000 Mbps

0.6

R/W

0

0 = 10 Mbps

0.5:0

Reserved

Write as 0, ignore on Read

00000

1. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the

LHR information is not re-read from the pins. This information reverts back to the information that was read

in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms after de-

assertion of the reset. During a software reset (0.15) the registers are available for reading. The reset bit

should be polled to see when the part has completed reset.

2. R/W = Read/Write, RO = Read Only, SC = Self Clearing when read.

3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

4. Default value of bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 18 on

page 63.

130

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Document #: 249241

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 59. Status Register (Address 1)

Bit

Name

Description

Type ¹

Default

1 = PHY able to perform 100BASE-T4

0 = PHY not able to perform 100BASE-T4

1.15 100BASE-T4

RO

0

100BASE-X Full

Duplex

1 = PHY able to perform full-duplex 100BASE-X

0 = PHY not able to perform full-duplex 100BASE-X

1.14

RO

1

100BASE-X Half

Duplex

1 = PHY able to perform half-duplex 100BASE-X

0 = PHY not able to perform half-duplex 100BASE-X

1.13

1 = PHY able to operate at 10 Mbps in full-duplex mode

0 = PHY not able to operate at 10 Mbps full-duplex

mode

1.12 10 Mbps Full Duplex

RO

1

1 = PHY able to operate at 10 Mbps in half-duplex

1.11 10 Mbps Half Duplex mode

0 = PHY not able to operate at 10 Mbps in half-duplex

100BASE-T2 Full

Duplex

1 = PHY able to perform full-duplex 100BASE-T2

0 = PHY not able to perform full-duplex 100BASE-T2

1.10

1.9

RO

0

100BASE-T2 Half

Duplex

1 = PHY able to perform half duplex 100BASE-T2

0 = PHY not able to perform half-duplex 100BASE-T2

1 = Extended status information in Register 15

0 = No extended status information in Register 15

1.8

1.7

Extended Status

Reserved

RO

0

1 = Ignore on read

1 = PHY accepts management frames with preamble

suppressed

0 = PHY will not accept management frames with

MF Preamble

Suppression

1.6

RO

0

preamble suppressed

Auto-Negotiation

complete

1 = Auto-negotiation complete

0 = Auto-negotiation not complete

1.5

1.4

1.3

1.2

RO

0

1

0

RO/LH

Note 2

1 = Remote fault condition detected

0 = No remote fault condition detected

Remote Fault

Auto-Negotiation

Ability

1 = PHY is able to perform Auto-Negotiation

0 = PHY is not able to perform Auto-Negotiation

RO

RO/LL

Note 2

1 = Link is up

0 = Link is down

Link Status

RO/LH

Note 2

1 = Jabber condition detected

0 = Jabber condition not detected

1.1

1.0

Jabber Detect

0

1

1 = Extended register capabilities

0 = Basic register capabilities

Extended Capability

RO

1. RO = Read Only

2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 60. PHY Identification Register 1 (Address 2)

Bit

Name

Description

Type ¹

Default

The PHY identifier composed of bits 3 through 18 of the

OUI

2.15:0 PHY ID Number

1. RO = Read Only

RO

0013 hex

Table 61. PHY Identification Register 2 (Address 3)

Bit

Name

Description

Type ¹

Default

The PHY identifier composed of bits 19

through 24 of the OUI

3.15:10 PHY ID Number

RO

011110

Manufacturer’s

3.9:4

6 bits containing manufacturer’s part number

RO

001111

XXX

(See Table 3 in

Specification

Update)

Model Number

Manufacturer’s

3 bits containing manufacturer’s revision

number

3.3:1

Revision

Number

0 = LXT9785

1 = LXT9785E

3.0

Model Variant

X

1. RO = Read Only

Figure 64. PHY Identifier Bit Mapping

a

1

r

s

x

b

2

c

Organizationally Unique Identifier

18 19

24

3

0

1

3

9

3

I/G

0

15

0

1

15

0

10

4

0

PHY ID Register #1 (Address 2)

PHY ID Register #2 (Address 3)

0

1

0

1

0

1

0

X

0

2

B

7

5

0

3

1

0

00

20

7B

Revision

Number

Manufacturer’s

Model Number

The Intel OUI is 00207B hex.

Model

Variant

132

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 62. Auto-Negotiation Advertisement Register (Address 4)⁶

Bit

Name

Description

Type ¹

Default

1 = Port has ability to send multiple pages

0 = Port has no ability to send multiple pages

4.15

4.14

4.13

4.12

4.11

R/W

RO

0

Ignore on read

1 = Remote fault

0 = No remote fault

Remote Fault

Reserved

R/W

Ignore

Asymmetric

Pause

Pause operation defined in Clause 40 and 27

1 = Pause operation enabled for full-duplex links

0 = Pause operation disabled

4.10

Pause⁵

R/W

LSHR^2,3

1 = 100BASE-T4 capability is available

0 = 100BASE-T4 capability is not available

(The LXT9785/9785E does not support 100BASE-T4 but

allows this bit to be set to advertise in the Auto-Negotiation

sequence for 100BASE-T4 operation. An external 100BASE-

T4 transceiver could be switched in if this capability is

desired.)

4.9

100BASE-T4

R/W

0

100BASE-TX 1 = Port is 100BASE-TX full duplex capable

4.8

4.7

R/W

LSHR^2,4

full duplex

0 = Port is not 100BASE-TX full duplex capable.

1 = Port is 100BASE-TX capable

0 = Port is not 100BASE-TX capable

100BASE-TX

1 = Port is 10BASE-T full duplex capable

0 = Port is not 10BASE-T full duplex capable

10BASE-T

full duplex

4.6

4.5

R/W

LSHR^2,4

LSHR²⁴³

1 = Port is 10BASE-T capable

10BASE-T

0 = Port is not 10BASE-T capable

<00001> = IEEE 802.3

<00010> = IEEE 802.9 ISLAN-16T

Selector

4.4:0 Field,

S<4:0>

<00000> = Reserved for future Auto-Negotiation development

<11111> = Reserved for future Auto-Negotiation development

Unspecified or reserved combinations should not be

transmitted

R/W

00001

1. R/W = Read/Write, RO = Read Only

2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

3. The default setting of Register bit 4.10 is determined by the PAUSE pin.

4. Default settings for bits 4.5:8 are determined by CFG pins as described in Table 18 on page 63.

5. Pause operation is only valid for full-duplex modes.

6. Restart Auto-Negotiation process whenever Register 4 is written/modified.

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 63. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)

Bit

Name

Description

Type ¹

Default

1 = Link Partner has ability to send multiple pages

0 = Link Partner has no ability to send multiple pages

5.15 Next Page

RO

0

1 = Link Partner has received Link Code Word from the

LXT9785/9785E.

0 = Link Partner has not received Link Code Word from the

the LXT9785/9785E

5.14 Acknowledge

RO

0

1 = Remote fault

0 = No remote fault

5.13 Remote Fault

5.12 Reserved

RO

0

Ignore on read

Pause operation defined in Clause 40 and 27

Asymmetric

Pause

5.11

RO

0

1 = Link Partner is Pause capable

0 = Link Partner is not Pause capable

1 = Link Partner is Pause capable

0 = Link Partner is not Pause capable

5.10 Pause

RO

0

1 = Link Partner is 100BASE-T4 capable

0 = Link Partner is not 100BASE-T4 capable

5.9

5.8

5.7

100BASE-T4

100BASE-TX

full duplex

1 = Link Partner is 100BASE-TX full duplex capable

0 = Link Partner is not 100BASE-TX full duplex capable

1 = Link Partner is 100BASE-TX capable

0 = Link Partner is not 100BASE-TX capable

100BASE-TX

10BASE-T

full duplex

1 = Link Partner is 10BASE-T full duplex capable

0 = Link Partner is not 10BASE-T full duplex capable

5.6

5.5

RO

0

1 = Link Partner is 10BASE-T capable

0 = Link Partner is not 10BASE-T capable

10BASE-T

<00001> = IEEE 802.3

<00010> = IEEE 802.9 ISLAN-16T

Selector Field

S<4:0>

5.4:0

<00000> = Reserved for future Auto-Negotiation development

<11111> = Reserved for future Auto-Negotiation development

Unspecified or reserved combinations shall not be transmitted

RO

00000

1. RO = Read Only

134

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Document #: 249241

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 64. Auto-Negotiation Expansion (Address 6)

Bit

Name

Description

Type ¹

Default

6.15:6 Reserved

Ignore on read

RO

0

This bit indicates the status of the Auto-Negotiation

variable, base page. It flags synchronization with the Auto-

Negotiation state diagram allowing detection of interrupted

links. This bit is only used if Register bit 16.1 (Alternate NP

feature) is set.

RO/

LH

6.5

Base Page

Parallel

0

1 = base_page = true

0 = base_page = false

1 = Parallel detection fault has occurred.

Detection Fault 0 = Parallel detection fault has not occurred.

RO/

LH

6.4

6.3

6.2

0

1

Link Partner 1 = Link partner is next page able

Next Page Able 0 = Link partner is not next page able

RO

1 = Local device is next page able

Next Page Able

0 = Local device is not next page able

Indicates that a new page has been received and the

received code word has been loaded into Register 5 or

Register 8 as specified in clause 28 of 802.3.

RO

LH

6.1

6.0

Page Received 1 = Three identical and consecutive link code words have

been received from link partner

0

0 = Three identical and consecutive link code words have

not been received from link partner

Link Partner A/ 1 = Link partner is auto-negotiation able

RO

N Able

0 = Link partner is not auto-negotiation able

1. RO = Read Only, LH = Latching High cleared when read

Table 65. Auto-Negotiation Next Page Transmit Register (Address 7)

Bit

Name

Description

Type ¹

Default

1 = Additional next pages follow

0 = Last page

7.15

R/W

RO

0

1

7.14 Reserved

Write as 0, ignore on read

Message Page 1 = Message page

7.13

7.12

R/W

(MP)

0 = Unformatted page

Acknowledge 2 1 = Complies with message

R/W

0

(ACK2)

0 = Cannot comply with message

1 = Previous value of the transmitted Link Code Word

equalled logic zero

0 = Previous value of the transmitted Link Code Word

equalled logic one

Toggle

(T)

7.11

Message/

7.10:0 Unformatted

Code Field

MP = 1: Code interpreted as “message page”

MP = 0: Code interpreted as “unformatted page”

R/W

00000000001

1. R/W = Read Write, RO = Read Only

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 66. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)

Bit

Name

Description

Type ¹

Default

0 = Link Partner has no additional next pages to send

8.15

RO

0

(NP)

1 = Link Partner has received Link Code Word from

the LXT9785/9785E

Acknowledge

(ACK)

8.14

RO

0

0 = Link Partner has not received Link Code Word

from the LXT9785/9785E

1 = Page sent by the Link Partner is a Message Page

Message Page

(MP)

8.13

8.12

RO

0

0 = Page sent by the Link Partner is an Unformatted

Page

Acknowledge 2

(ACK2)

1 = Link Partner complies with the message

0 = Link Partner cannot comply with the message

1 = Previous value of the transmitted Link Code Word

equalled logic zero

0 = Previous value of the transmitted Link Code Word

Toggle

(T)

8.11

RO

0

equalled logic one

Message/

8.10:0 Unformatted

MP = 1: Code interpreted as “message page”

MP = 0: Code interpreted as “unformatted page”

00000000000

Code Field

1. RO = Read Only

136

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 67. Port Configuration Register (Address 16, Hex 10)

Bit

Name

Reserved

Description

Write as 0, ignore on read

Type ¹

Default

16.15

R/W

0

1 = Force Link pass. Sets appropriate registers and LEDs

16.14

Link Disable

to Pass.

R/W

0

0 = Normal operation

1 = Disable Twisted-Pair transmitter

0 = Normal Operation

16.13

16.12

16.11

16.10

Transmit Disable

R/W

0

Bypass Scramble 1 = Bypass Scrambler and Descrambler

(100BASE-TX)

0 = Normal Operation

Bypass 4B5B

(100BASE-TX)

1 = Bypass 4B5B encoder and decoder

0 = Normal Operation

Jabber

(10BASE-T)

1 = Disable Jabber

0 = Normal operation

This bit is ignored by the LXT9785/9785E

SQE

(10BASE-T)

16.9

16.8

R/W

0

1

1 = Enable Heart Beat

0 = Disable Heart Beat

TP Loopback

(10BASE-T)

1 = Disable TP loopback during half duplex operation

0 = Normal Operation

16.7

16.6

Reserved

Write as one. Ignore on read.

Write as zero. Ignore on read.

R/W

RW

1

0

0 = No Preamble (default)

10 Mbps

0

1 = Preamble Enabled

16.5

Preamble Enable

R/W

100 Mbps Always enabled

Write as zero. Ignore on read.

N/A

0

16.4

16.3

Reserved

R/W

0

Far End Fault

Transmission

Enable

1 = Enable Far End Fault Transmission

0 = Disable Far End Fault Transmission

16.2

R/W

1

16.1

16.0

Reserved

Write as zero. Ignore on read.

R/W

0

1 = Select fiber mode for this port

0 = Select TP mode for this port

Fiber Select

LSHR^2,3

1. R/W = Read/Write

2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

3. The default value of Register bit 16.0 is determined by the G_FX/TP pin.

If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default

value of Register bit 16.0 = 1.

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 68. Quick Status Register (Address 17, Hex 11)

Bit

Name

Description

Type ¹

Default

17.15 Reserved

Always 0

RO

0

1 = The LXT9785/9785E is operating in 100BASE-TX

mode.

17.14 10/100 Mode

RO

0

0 = The LXT9785/9785E is not operating 100BASE-TX

mode.

1 = The LXT9785/9785E is transmitting a packet

0 = The LXT9785/9785E is not transmitting a packet

RO

LH

17.13 Transmit Status

17.12 Receive Status

17.11 Collision Status

17.10 Link

0

1 = The LXT9785/9785E is receiving a packet

0 = The LXT9785/9785E is not receiving a packet

RO

LH

1 = Collision is occurring

0 = No collision

RO

LH

1 = Link is up

0 = Link is down

RO

1 = Full duplex

0 = Half duplex

17.9

17.8

Duplex Mode

1 = The LXT9785/9785E is in Auto-Negotiation Mode

0 = The LXT9785/9785E is in manual mode

Auto-Negotiation

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

Auto-Negotiation

Complete

17.7

17.6

RO

0

This bit is only valid when auto-negotiate is enabled, and is

equivalent to Register bit 1.5.

1 = FIFO error has occurred (Overflow or Underflow)

0 = No FIFO error has occurred

RO

LH

FIFO Error

1 = Polarity is reversed

0 = Polarity is not reversed

17.5

17.4

Polarity

Pause

RO

0

1 = The LXT9785/9785E is Pause capable

0 = The LXT9785/9785E is Not Pause capable

1 = Error Occurred (Remote Fault, RxERCntFUL, FIFO

error, Jabber, Parallel Detect Fault)

0 = No error occurred

RO

LH

17.3

Error

0

17.2

17.1

17.0

Reserved

Ignore

RO

0

Always 0

1. RO = Read Only, LH = Latching High cleared when read.

138

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Document #: 249241

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Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 69. Interrupt Enable Register (Address 18, Hex 12)

Bit

Name

Description

Type¹

Default

00 =

01 =

10 =

11 =

Reserve

Low, 16 bits

18.15:14²RxFIFO Initial Fill

R/W

0

Normal, 32 bits (Default)

Jumbo packets, 256 bits

When 16.5 = 1:

1 = Enabled

SFD Frame

Alignment³

10 Mbps

R/W

0

0 = Disabled

18.13²

( RxDV asserts

with CRS when

enabled)

When 16.5 = 0, SFD is always aligned

1 =

0 =

Enabled

Disabled

100 Mbps

R/W

0

18.12:9

18.8

Reserved

Write as 0, ignore on read

Mask for Counter Full

CNTRMSK

R/W

0

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Auto-Negotiate Complete

18.7

18.6

18.5

18.4

18.3

ANMSK

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Speed Interrupt

SPEEDMSK

DUPLEXMSK

LINKMSK

ISOLMSK

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Duplex Interrupt

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Link Status Interrupt

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Isolate Interrupt

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

18.2

18.1

Reserved

INTEN

Write as 0, ignore on read

R/W

0

1 = Enable interrupts on this port

0 = Disable interrupts on this port

1 = Test Force interrupt on MDINT

0 = Normal operation

18.0

TINT

R/W

0

1. R/W = Read/Write

2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = ‘11’ because

the minimum Inter-Packet Gap becomes less than IEEE 802.3 specification.

3. SFD Frame Alignment is applicable to SMII and SS-SMII only.

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 70. Interrupt Status Register (Address 19, Hex 13)

Bit

Name

Description

Type ¹

Default

19.15:9 Reserved

Ignore on read

RO

0

RxER Counter Full Status

0

N/A

0

1 = One of the internal counters has reached its maximum

value

0 = The internal counters have not reached maximum values

19.8

19.7

RxERCntFUL

RO/SC

Auto-Negotiation Status

ANDONE

1= Auto-Negotiation has completed

0= Auto-Negotiation has not completed

Speed Change Status

1 = A Speed Change has occurred since last reading this

register

19.6

19.5

19.4

SPEEDCHG

RO/SC

0 = A Speed Change has not occurred since last reading this

register

Duplex Change Status

1 = A Duplex Change has occurred since last reading this

DUPLEXCHG register

0

0 = A Duplex Change has not occurred since last reading

this register

Link Status Change Status

1 = A Link Change has occurred since last reading this

register

LINKCHG

0 = A Link Change has not occurred since last reading this

register

MII Isolate Change Status

1 = An Isolate change has occurred since last reading this

register

19.3

19.2

Isolate

MDINT

RO/SC

0

0 = An Isolate change has not occurred since last reading

this register

1 = RMII/SMII/SS-SMII interrupt pending

0 = No RMII/SMII/SS-SMII interrupt pending

19.1

19.0

Reserved

Ignore on read

RO/SC

RO

0

1. R/W = Read/Write, RO = Read Only, SC = Self Clearing when read

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 71. LED Configuration Register (Address 20, Hex 14)

Bit

Name

Description

Type ¹Default

0000 = Display Speed Status (Continuous, Default)

0001 = Display Transmit Status (Stretched)

0010 = Display Receive Status (Stretched)

0011 = Display Collision Status (Stretched)

0100 = Display Link Status (Continuous)

0101 = Display Duplex Status (Continuous)

0110 = Display Isolate Status (Continuous)

0111 = Display Receive or Transmit Activity (Stretched)

1000 = Test mode- turn LED on (Continuous)

1001 = Test mode- turn LED off (Continuous)

1010 = Test mode- blink LED fast (Continuous)

1011 = Test mode- blink LED slow (Continuous)

1100 = Display Link and Receive Status combined ²

(Stretched)³

LED1

20.15:12

R/W

0000

Programming

bits

1101 = Display Link and Activity Status combined ²

(Stretched)³

1110 = Display Duplex and Collision Status combined ⁴

(Stretched)³

1111 = Display Link and RxER Status combined ²(Blink)

0000 = Display Speed Status

0001 = Display Transmit Status

0010 = Display Receive Status

0011 = Display Collision Status

0100 = Display Link Status

0101 = Display Duplex Status

0110 = Display Isolate Status

0111 = Display Receive or Transmit Activity

1000 = Test mode- turn LED on

1001 = Test mode- turn LED off

1010 = Test mode- blink LED fast

1011 = Test mode- blink LED slow

1100 = Display Link and Receive Status combined ²

(Stretched)³

LED2

20.11:8

R/W

1101

Programming

bits

1101 = Display Link and Activity Status combined ²

(Default)(Stretched)³

1110 = Display Duplex and Collision Status combined ⁴

(Stretched)³

1111 = Display Link and RxER Status combined ²(Blink)

1. R/W = Read/Write, RO = Read Only, LH = Latching High.

2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).

3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings

are stretched regardless of the value of 20.1.

4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

Datasheet

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LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 71. LED Configuration Register (Address 20, Hex 14) (Continued)

Bit

Name

Description

Type ¹Default

0000 = Display Speed Status

0001 = Display Transmit Status

0010 = Display Receive Status

0011 = Display Collision Status

0100 = Display Link Status

0101 = Display Duplex Status

0110 = Display Isolate Status

0111 = Display Receive or Transmit Activity

1000 = Test mode- turn LED on

1001 = Test mode- turn LED off

1010 = Test mode- blink LED fast

1011 = Test mode- blink LED slow

1100 = Display Link and Receive Status combined ²

(Stretched)³

LED3

20.7:4

R/W

1110

Programming

bits

1101 = Display Link and Activity Status combined ²

(Stretched)³

1110 = Display Duplex and Collision Status combined ⁴

(Default) (Blink)³

1111 = Display Link and RxER Status combined ²(Blink)

00 = Stretch LED events to 30 ms

01 = Stretch LED events to 60 ms

10 = Stretch LED events to 100 ms

11 = Reserved

20.3:2

LEDFREQ

R/W

00

PULSE-

STRETCH

1 = Enable pulse stretching of all LEDs

0 = Disable pulse stretching of all LEDs ²

20.1

20.0

R/W

1

0

Reserved

1. R/W = Read/Write, RO = Read Only, LH = Latching High.

2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).

3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings

are stretched regardless of the value of 20.1.

4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

Table 72. Receive Error Count Register (Address 21)

Bit

Name

Description

Type ¹

Default

A 16-bit counter value indicating the number of times a

receive packet with errors occurred. Only one event gets

Receive Error counted per packet. When maximum count is reached, the

RO/

SC

21.15:0

0

Count

16-bit counter remains full until cleared. Refer to the

discussion of “Out-of-Band Signalling” on page 76 for

details.

1. RO = Read Only

S/C = Self Clearing when read

142

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Advanced 10/100 8-Port PHY — LXT9785/9785E

Table 73. RMII Out-of-Band Signalling Register (Address 25)

Bit

Name

Description

Type ¹

Default

25.15:7 Reserved

Reserved

R/W

0

These three bits select which status information is

available on the RxData(1) bit of the RMII bus.

000 = Link

001 = Speed

010 = Duplex

25.6:4

BIT1

R/W

000

011 = Auto-negotiation complete

100 = Polarity reversed

101 = Jabber detected

110 = Interrupt pending

111 = Isolate

These three bits select which status information is

available on the RxData(0) bit of the RMII bus.

000 = Link

001 = Speed

010 = Duplex

25.3:1

BIT0

R/W

000

011 = Auto-negotiation complete

100 = Polarity reversed

101 = Jabber detected

110 = Interrupt pending

111 = Isolate

1 = Enable programmable RMII Out-of-Band

signalling. When enabled, bits 6:1 specify which

status bits are available on the RMII RxData data

bus.

25.0

PROGRMII

R/W

0

0 = Disable Out-of-Band signalling.

1. R/W = Read/Write

RO = Read Only

Datasheet

143

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Table 74. Trim Enable Register (Address 27)

00 = 3.3ns

Per-Port

27.11:10 Rise Time

01 = 3.6ns

R/W

LSHR^1,2

10 = 3.9ns

Control

11 = 4.2ns

0 = Disable auto MDIX

27.9

27.8

AMDIX_EN

MDIX

R/W

LSHR^1,3

LSHR^1,4

1 = Enable auto MDIX

Manual MDI/MDIX selection: (This bit is ignored when

Register bit 27.9 = 1)

0 = MDI, transmit on pair A and receive on pair B

1 = MDIX transmit on pair B and receive on pair A

1 = Enable analog loop back (transmits on twisted-pair)

0 = Disable analog loop back

Analog

Loop back

27.7

27.6

R/W

0

DTE Discovery Process Enable

1 = Enable DTE discovery process

0 = Disable DTE discovery process

Dis_EN

Loop back

Speed Up

Enable

1 = enable automatic loop back detection speed up

0 = disable automatic loop back detection speed up

27.5

27.4

R/W

RO

0

Power Enable (Requires Auto-Negotiation Enable Register

bit 0.12 = 1)

1 = Potential Remote-Power DTE discovered; indication to

turn on power over the cable.

Power_EN

SLP_Det

0 = Remote-Power DTE not discovered; process may not be

complete.

Standard Link Partner Detected

1 = Standard link partner discovered; indication not to turn on

power over the cable.

0 = Standard link partner not discovered; process may not be

complete.

R/W

SC

27.3

27.2

0

Link Fail Inhibit Timer expiration indicator. Valid only when

SLP_Det = 1.

1 = Link Fail Inhibit Timer expired with a standard link partner

detected since last register read or link establishment

0 = Timer has not expired or standard link partner not

discovered

LFIT

Expired

R/W

SC

1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as

the pin(s) are latched at startup or hardware reset.

2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins.

3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin.

4. Default value for Register bit 27.8 is determined by the MDIX pin.

5. SC = Self Clearing when read; RO = Read Only; R/W = Read/Write.

144

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Datasheet

145

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

146

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

6.0

Package Specifications

Figure 65. LXT9785/9785E 208-Pin PQFP Plastic Package Specification

208-Pin Plastic Quad Flat Package

• Part Number LXT9785HC, LXT9785EHC,

LXT9785HE

• Commercial Temperature Range (0°C to 70°C)

• Extended Temperature Range (-40°C to +85°C)

Millimeters

Max

Dim

Min

D

D₁

A

-

4.10

-

A1

A2

0.25

3.20

3.60

0.27

30.90

28.30

30.90

28.30

b

D

0.17

e

E₁

30.30

27.70

30.30

27.70

E

D₁

E

e

/

2

E₁

e

.50 BASIC

L

0.50

0.75

θ

L₁

q

1.30 REF

2

L₁

0°

5°

7°

θ₂

θ₃

A₂

16°

A

θ

A₁

θ

3

b

L

Datasheet

147

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Figure 66. LXT9785/9785E 241-Ball PBGA Package Specs - Top/Side View(LXT9785BC)

D

D1

Pin A1 corner

Pin A1 I.D.

14.70 REF

E1 E

14.70 REF

45° Chamfer

(4 places)

Top View

A2

A

c

30°

A1

Side View

Seating Plane

148

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

Advanced 10/100 8-Port PHY — LXT9785/9785E

Figure 67. LXT9785/9785E 241-Ball PBGA Package Specs - Bottom View (LXT9785BC)

Pin A1 corner

16

14

12

10

8

6

4

2

17

15

13

11

9

7

5

3

1

A

B

C

D

E

F

b

G

H

J

e

K

L

M

N

P

R

T

U

J

e

241 BGA

Bottom View

l

Table 77. LXT9785/9785E 241-Ball PBGA Package Dimensions

Symbol

Min

2.14

Nominal

2.33

Max

2.51

Units

mm

Note

A

A1

A2

D

0.50

0.60

0.70

mm

1.12

1.17

1.22

22.90

19.30

22.90

19.30

23.00

10.50

23.00

19.50

24.00

19.70

24.00

19.70

D1

E

E1

e

1.27 (solder ball pitch)

1.34 REF.

I

J

1.34 REF.

M

b²

c

17 x 17 Matrix

0.60

0.52

0.75

0.56

1.27

0.90

0.60

e

1. All dimensions and tolerances conform to ANSI Y14.5-1982.

2. Dimension is measured at maximum solder ball diameter parallel to primary

datum (-C-).

3. Primary datum (-C-) and seating plane are defined by the spherical crowns of

the solder balls.

Datasheet

149

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002

LXT9785/9785E — Advanced 10/100 8-Port PHY

Appendix A Ordering Information

Table 78. Product Information

Number

Revision

Qualification

Tray MM

Tape & Reel MM

HBLXT9785HC.A4

FWLXT9785BC.A4

HBLXT9785HC.B2

FWLXT9785BC.B2

HBLXT9785EHC.B2

FWLXT9785EBC.B2

HBLXT9785HE.B2

A4

B2

S

Q

S

837464

834129

N/A

837465

837457

844582

838254

838225

N/A

838202

839978

N/A

Figure 68. Ordering Information - Sample

A6

S

E001

FW

LXT

9785E

B

C

Build Format

= Tray

= Tape and reel

E000

E001

Qualification

= Pre-production material

= Production material

Q

S

Product Revision

= 2 Alphanumeric characters

xn

Temperature Range

= Ambient (0 - 55° C)

= Commercial (0 - 70° C)

= Extended (-40 - +85° C)

A

C

E

Internal Package Designator

= LQFP

L

= PLCC

= DIP

= PQFP

= QFP with heat spreader

= TQFP

P

N

Q

H

T

= BGA

= TBGA

= HSBGA (BGA with heat slug)

B

E

K

xxxx

= 3-5 Digit Alphanumeric Product Code

IXA Product Prefix

= PHY layer device

= Switching engine

= Formatting device (MAC)

= Network processor

LXT

IXE

IXF

IXP

Intel Package Designator

DJ

FA

FL

FW

HB

HD

HG

S

= LQFP

= TQFP

= PBGA (<1.0 mm pitch)

= PBGA (1.27 mm pitch)

= QFP with heat spreader

= QFP with heat slug

= SOIC

= QFP

GC

N

= TBGA

= PLCC

150

Datasheet

Document #: 249241

Revision #: 005

Rev. Date: January 24, 2002


型号：	HBLXT9785HC.B2SE001
厂家：	INTEL
描述：	Ethernet Transceiver, 8-Trnsvr, PQFP208, 以太网：16GBASE-T 电信电信集成电路
文件：	总150页 (文件大小：1859K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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